1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
9 #include <linux/types.h>
10 #include <asm/byteorder.h>
12 #include <linux/bitops.h>
13 #include <linux/delay.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/errno.h>
16 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/pci.h>
19 #include <linux/slab.h>
20 #include <linux/string.h>
24 #include "qed_init_ops.h"
27 #include "qed_reg_addr.h"
31 qed_int_comp_cb_t comp_cb
;
35 struct qed_sb_sp_info
{
36 struct qed_sb_info sb_info
;
38 /* per protocol index data */
39 struct qed_pi_info pi_info_arr
[PIS_PER_SB
];
42 #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \
43 ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn)
45 #define ATTN_STATE_BITS (0xfff)
46 #define ATTN_BITS_MASKABLE (0x3ff)
47 struct qed_sb_attn_info
{
48 /* Virtual & Physical address of the SB */
49 struct atten_status_block
*sb_attn
;
52 /* Last seen running index */
55 /* Previously asserted attentions, which are still unasserted */
58 /* Cleanup address for the link's general hw attention */
62 static inline u16
qed_attn_update_idx(struct qed_hwfn
*p_hwfn
,
63 struct qed_sb_attn_info
*p_sb_desc
)
68 /* Make certain HW write took affect */
71 index
= le16_to_cpu(p_sb_desc
->sb_attn
->sb_index
);
72 if (p_sb_desc
->index
!= index
) {
73 p_sb_desc
->index
= index
;
77 /* Make certain we got a consistent view with HW */
84 * @brief qed_int_assertion - handles asserted attention bits
87 * @param asserted_bits newly asserted bits
90 static int qed_int_assertion(struct qed_hwfn
*p_hwfn
,
93 struct qed_sb_attn_info
*sb_attn_sw
= p_hwfn
->p_sb_attn
;
96 /* Mask the source of the attention in the IGU */
97 igu_mask
= qed_rd(p_hwfn
, p_hwfn
->p_dpc_ptt
,
98 IGU_REG_ATTENTION_ENABLE
);
99 DP_VERBOSE(p_hwfn
, NETIF_MSG_INTR
, "IGU mask: 0x%08x --> 0x%08x\n",
100 igu_mask
, igu_mask
& ~(asserted_bits
& ATTN_BITS_MASKABLE
));
101 igu_mask
&= ~(asserted_bits
& ATTN_BITS_MASKABLE
);
102 qed_wr(p_hwfn
, p_hwfn
->p_dpc_ptt
, IGU_REG_ATTENTION_ENABLE
, igu_mask
);
104 DP_VERBOSE(p_hwfn
, NETIF_MSG_INTR
,
105 "inner known ATTN state: 0x%04x --> 0x%04x\n",
106 sb_attn_sw
->known_attn
,
107 sb_attn_sw
->known_attn
| asserted_bits
);
108 sb_attn_sw
->known_attn
|= asserted_bits
;
110 /* Handle MCP events */
111 if (asserted_bits
& 0x100) {
112 qed_mcp_handle_events(p_hwfn
, p_hwfn
->p_dpc_ptt
);
113 /* Clean the MCP attention */
114 qed_wr(p_hwfn
, p_hwfn
->p_dpc_ptt
,
115 sb_attn_sw
->mfw_attn_addr
, 0);
118 DIRECT_REG_WR((u8 __iomem
*)p_hwfn
->regview
+
119 GTT_BAR0_MAP_REG_IGU_CMD
+
120 ((IGU_CMD_ATTN_BIT_SET_UPPER
-
121 IGU_CMD_INT_ACK_BASE
) << 3),
124 DP_VERBOSE(p_hwfn
, NETIF_MSG_INTR
, "set cmd IGU: 0x%04x\n",
131 * @brief - handles deassertion of previously asserted attentions.
134 * @param deasserted_bits - newly deasserted bits
138 static int qed_int_deassertion(struct qed_hwfn
*p_hwfn
,
141 struct qed_sb_attn_info
*sb_attn_sw
= p_hwfn
->p_sb_attn
;
144 if (deasserted_bits
!= 0x100)
145 DP_ERR(p_hwfn
, "Unexpected - non-link deassertion\n");
147 /* Clear IGU indication for the deasserted bits */
148 DIRECT_REG_WR((u8 __iomem
*)p_hwfn
->regview
+
149 GTT_BAR0_MAP_REG_IGU_CMD
+
150 ((IGU_CMD_ATTN_BIT_CLR_UPPER
-
151 IGU_CMD_INT_ACK_BASE
) << 3),
152 ~((u32
)deasserted_bits
));
154 /* Unmask deasserted attentions in IGU */
155 aeu_mask
= qed_rd(p_hwfn
, p_hwfn
->p_dpc_ptt
,
156 IGU_REG_ATTENTION_ENABLE
);
157 aeu_mask
|= (deasserted_bits
& ATTN_BITS_MASKABLE
);
158 qed_wr(p_hwfn
, p_hwfn
->p_dpc_ptt
, IGU_REG_ATTENTION_ENABLE
, aeu_mask
);
160 /* Clear deassertion from inner state */
161 sb_attn_sw
->known_attn
&= ~deasserted_bits
;
166 static int qed_int_attentions(struct qed_hwfn
*p_hwfn
)
168 struct qed_sb_attn_info
*p_sb_attn_sw
= p_hwfn
->p_sb_attn
;
169 struct atten_status_block
*p_sb_attn
= p_sb_attn_sw
->sb_attn
;
170 u32 attn_bits
= 0, attn_acks
= 0;
171 u16 asserted_bits
, deasserted_bits
;
175 /* Read current attention bits/acks - safeguard against attentions
176 * by guaranting work on a synchronized timeframe
179 index
= p_sb_attn
->sb_index
;
180 attn_bits
= le32_to_cpu(p_sb_attn
->atten_bits
);
181 attn_acks
= le32_to_cpu(p_sb_attn
->atten_ack
);
182 } while (index
!= p_sb_attn
->sb_index
);
183 p_sb_attn
->sb_index
= index
;
185 /* Attention / Deassertion are meaningful (and in correct state)
186 * only when they differ and consistent with known state - deassertion
187 * when previous attention & current ack, and assertion when current
188 * attention with no previous attention
190 asserted_bits
= (attn_bits
& ~attn_acks
& ATTN_STATE_BITS
) &
191 ~p_sb_attn_sw
->known_attn
;
192 deasserted_bits
= (~attn_bits
& attn_acks
& ATTN_STATE_BITS
) &
193 p_sb_attn_sw
->known_attn
;
195 if ((asserted_bits
& ~0x100) || (deasserted_bits
& ~0x100)) {
197 "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n",
198 index
, attn_bits
, attn_acks
, asserted_bits
,
199 deasserted_bits
, p_sb_attn_sw
->known_attn
);
200 } else if (asserted_bits
== 0x100) {
202 "MFW indication via attention\n");
204 DP_VERBOSE(p_hwfn
, NETIF_MSG_INTR
,
205 "MFW indication [deassertion]\n");
209 rc
= qed_int_assertion(p_hwfn
, asserted_bits
);
214 if (deasserted_bits
) {
215 rc
= qed_int_deassertion(p_hwfn
, deasserted_bits
);
223 static void qed_sb_ack_attn(struct qed_hwfn
*p_hwfn
,
224 void __iomem
*igu_addr
,
227 struct igu_prod_cons_update igu_ack
= { 0 };
229 igu_ack
.sb_id_and_flags
=
230 ((ack_cons
<< IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT
) |
231 (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT
) |
232 (IGU_INT_NOP
<< IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT
) |
233 (IGU_SEG_ACCESS_ATTN
<<
234 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT
));
236 DIRECT_REG_WR(igu_addr
, igu_ack
.sb_id_and_flags
);
238 /* Both segments (interrupts & acks) are written to same place address;
239 * Need to guarantee all commands will be received (in-order) by HW.
245 void qed_int_sp_dpc(unsigned long hwfn_cookie
)
247 struct qed_hwfn
*p_hwfn
= (struct qed_hwfn
*)hwfn_cookie
;
248 struct qed_pi_info
*pi_info
= NULL
;
249 struct qed_sb_attn_info
*sb_attn
;
250 struct qed_sb_info
*sb_info
;
254 if (!p_hwfn
->p_sp_sb
) {
255 DP_ERR(p_hwfn
->cdev
, "DPC called - no p_sp_sb\n");
259 sb_info
= &p_hwfn
->p_sp_sb
->sb_info
;
260 arr_size
= ARRAY_SIZE(p_hwfn
->p_sp_sb
->pi_info_arr
);
263 "Status block is NULL - cannot ack interrupts\n");
267 if (!p_hwfn
->p_sb_attn
) {
268 DP_ERR(p_hwfn
->cdev
, "DPC called - no p_sb_attn");
271 sb_attn
= p_hwfn
->p_sb_attn
;
273 DP_VERBOSE(p_hwfn
, NETIF_MSG_INTR
, "DPC Called! (hwfn %p %d)\n",
274 p_hwfn
, p_hwfn
->my_id
);
276 /* Disable ack for def status block. Required both for msix +
277 * inta in non-mask mode, in inta does no harm.
279 qed_sb_ack(sb_info
, IGU_INT_DISABLE
, 0);
281 /* Gather Interrupts/Attentions information */
282 if (!sb_info
->sb_virt
) {
285 "Interrupt Status block is NULL - cannot check for new interrupts!\n");
287 u32 tmp_index
= sb_info
->sb_ack
;
289 rc
= qed_sb_update_sb_idx(sb_info
);
290 DP_VERBOSE(p_hwfn
->cdev
, NETIF_MSG_INTR
,
291 "Interrupt indices: 0x%08x --> 0x%08x\n",
292 tmp_index
, sb_info
->sb_ack
);
295 if (!sb_attn
|| !sb_attn
->sb_attn
) {
298 "Attentions Status block is NULL - cannot check for new attentions!\n");
300 u16 tmp_index
= sb_attn
->index
;
302 rc
|= qed_attn_update_idx(p_hwfn
, sb_attn
);
303 DP_VERBOSE(p_hwfn
->cdev
, NETIF_MSG_INTR
,
304 "Attention indices: 0x%08x --> 0x%08x\n",
305 tmp_index
, sb_attn
->index
);
308 /* Check if we expect interrupts at this time. if not just ack them */
309 if (!(rc
& QED_SB_EVENT_MASK
)) {
310 qed_sb_ack(sb_info
, IGU_INT_ENABLE
, 1);
314 /* Check the validity of the DPC ptt. If not ack interrupts and fail */
315 if (!p_hwfn
->p_dpc_ptt
) {
316 DP_NOTICE(p_hwfn
->cdev
, "Failed to allocate PTT\n");
317 qed_sb_ack(sb_info
, IGU_INT_ENABLE
, 1);
321 if (rc
& QED_SB_ATT_IDX
)
322 qed_int_attentions(p_hwfn
);
324 if (rc
& QED_SB_IDX
) {
327 /* Look for a free index */
328 for (pi
= 0; pi
< arr_size
; pi
++) {
329 pi_info
= &p_hwfn
->p_sp_sb
->pi_info_arr
[pi
];
330 if (pi_info
->comp_cb
)
331 pi_info
->comp_cb(p_hwfn
, pi_info
->cookie
);
335 if (sb_attn
&& (rc
& QED_SB_ATT_IDX
))
336 /* This should be done before the interrupts are enabled,
337 * since otherwise a new attention will be generated.
339 qed_sb_ack_attn(p_hwfn
, sb_info
->igu_addr
, sb_attn
->index
);
341 qed_sb_ack(sb_info
, IGU_INT_ENABLE
, 1);
344 static void qed_int_sb_attn_free(struct qed_hwfn
*p_hwfn
)
346 struct qed_dev
*cdev
= p_hwfn
->cdev
;
347 struct qed_sb_attn_info
*p_sb
= p_hwfn
->p_sb_attn
;
351 dma_free_coherent(&cdev
->pdev
->dev
,
352 SB_ATTN_ALIGNED_SIZE(p_hwfn
),
359 static void qed_int_sb_attn_setup(struct qed_hwfn
*p_hwfn
,
360 struct qed_ptt
*p_ptt
)
362 struct qed_sb_attn_info
*sb_info
= p_hwfn
->p_sb_attn
;
364 memset(sb_info
->sb_attn
, 0, sizeof(*sb_info
->sb_attn
));
367 sb_info
->known_attn
= 0;
369 /* Configure Attention Status Block in IGU */
370 qed_wr(p_hwfn
, p_ptt
, IGU_REG_ATTN_MSG_ADDR_L
,
371 lower_32_bits(p_hwfn
->p_sb_attn
->sb_phys
));
372 qed_wr(p_hwfn
, p_ptt
, IGU_REG_ATTN_MSG_ADDR_H
,
373 upper_32_bits(p_hwfn
->p_sb_attn
->sb_phys
));
376 static void qed_int_sb_attn_init(struct qed_hwfn
*p_hwfn
,
377 struct qed_ptt
*p_ptt
,
379 dma_addr_t sb_phy_addr
)
381 struct qed_sb_attn_info
*sb_info
= p_hwfn
->p_sb_attn
;
383 sb_info
->sb_attn
= sb_virt_addr
;
384 sb_info
->sb_phys
= sb_phy_addr
;
386 /* Set the address of cleanup for the mcp attention */
387 sb_info
->mfw_attn_addr
= (p_hwfn
->rel_pf_id
<< 3) +
388 MISC_REG_AEU_GENERAL_ATTN_0
;
390 qed_int_sb_attn_setup(p_hwfn
, p_ptt
);
393 static int qed_int_sb_attn_alloc(struct qed_hwfn
*p_hwfn
,
394 struct qed_ptt
*p_ptt
)
396 struct qed_dev
*cdev
= p_hwfn
->cdev
;
397 struct qed_sb_attn_info
*p_sb
;
399 dma_addr_t p_phys
= 0;
402 p_sb
= kmalloc(sizeof(*p_sb
), GFP_ATOMIC
);
404 DP_NOTICE(cdev
, "Failed to allocate `struct qed_sb_attn_info'\n");
409 p_virt
= dma_alloc_coherent(&cdev
->pdev
->dev
,
410 SB_ATTN_ALIGNED_SIZE(p_hwfn
),
411 &p_phys
, GFP_KERNEL
);
414 DP_NOTICE(cdev
, "Failed to allocate status block (attentions)\n");
419 /* Attention setup */
420 p_hwfn
->p_sb_attn
= p_sb
;
421 qed_int_sb_attn_init(p_hwfn
, p_ptt
, p_virt
, p_phys
);
426 /* coalescing timeout = timeset << (timer_res + 1) */
427 #define QED_CAU_DEF_RX_USECS 24
428 #define QED_CAU_DEF_TX_USECS 48
430 void qed_init_cau_sb_entry(struct qed_hwfn
*p_hwfn
,
431 struct cau_sb_entry
*p_sb_entry
,
438 memset(p_sb_entry
, 0, sizeof(*p_sb_entry
));
440 SET_FIELD(p_sb_entry
->params
, CAU_SB_ENTRY_PF_NUMBER
, pf_id
);
441 SET_FIELD(p_sb_entry
->params
, CAU_SB_ENTRY_VF_NUMBER
, vf_number
);
442 SET_FIELD(p_sb_entry
->params
, CAU_SB_ENTRY_VF_VALID
, vf_valid
);
443 SET_FIELD(p_sb_entry
->params
, CAU_SB_ENTRY_SB_TIMESET0
, 0x7F);
444 SET_FIELD(p_sb_entry
->params
, CAU_SB_ENTRY_SB_TIMESET1
, 0x7F);
446 /* setting the time resultion to a fixed value ( = 1) */
447 SET_FIELD(p_sb_entry
->params
, CAU_SB_ENTRY_TIMER_RES0
,
448 QED_CAU_DEF_RX_TIMER_RES
);
449 SET_FIELD(p_sb_entry
->params
, CAU_SB_ENTRY_TIMER_RES1
,
450 QED_CAU_DEF_TX_TIMER_RES
);
452 cau_state
= CAU_HC_DISABLE_STATE
;
454 if (p_hwfn
->cdev
->int_coalescing_mode
== QED_COAL_MODE_ENABLE
) {
455 cau_state
= CAU_HC_ENABLE_STATE
;
456 if (!p_hwfn
->cdev
->rx_coalesce_usecs
)
457 p_hwfn
->cdev
->rx_coalesce_usecs
=
458 QED_CAU_DEF_RX_USECS
;
459 if (!p_hwfn
->cdev
->tx_coalesce_usecs
)
460 p_hwfn
->cdev
->tx_coalesce_usecs
=
461 QED_CAU_DEF_TX_USECS
;
464 SET_FIELD(p_sb_entry
->data
, CAU_SB_ENTRY_STATE0
, cau_state
);
465 SET_FIELD(p_sb_entry
->data
, CAU_SB_ENTRY_STATE1
, cau_state
);
468 void qed_int_cau_conf_sb(struct qed_hwfn
*p_hwfn
,
469 struct qed_ptt
*p_ptt
,
475 struct cau_sb_entry sb_entry
;
478 qed_init_cau_sb_entry(p_hwfn
, &sb_entry
, p_hwfn
->rel_pf_id
,
479 vf_number
, vf_valid
);
481 if (p_hwfn
->hw_init_done
) {
482 val
= CAU_REG_SB_ADDR_MEMORY
+ igu_sb_id
* sizeof(u64
);
483 qed_wr(p_hwfn
, p_ptt
, val
, lower_32_bits(sb_phys
));
484 qed_wr(p_hwfn
, p_ptt
, val
+ sizeof(u32
),
485 upper_32_bits(sb_phys
));
487 val
= CAU_REG_SB_VAR_MEMORY
+ igu_sb_id
* sizeof(u64
);
488 qed_wr(p_hwfn
, p_ptt
, val
, sb_entry
.data
);
489 qed_wr(p_hwfn
, p_ptt
, val
+ sizeof(u32
), sb_entry
.params
);
491 /* Initialize Status Block Address */
492 STORE_RT_REG_AGG(p_hwfn
,
493 CAU_REG_SB_ADDR_MEMORY_RT_OFFSET
+
497 STORE_RT_REG_AGG(p_hwfn
,
498 CAU_REG_SB_VAR_MEMORY_RT_OFFSET
+
503 /* Configure pi coalescing if set */
504 if (p_hwfn
->cdev
->int_coalescing_mode
== QED_COAL_MODE_ENABLE
) {
505 u8 timeset
= p_hwfn
->cdev
->rx_coalesce_usecs
>>
506 (QED_CAU_DEF_RX_TIMER_RES
+ 1);
509 qed_int_cau_conf_pi(p_hwfn
, p_ptt
, igu_sb_id
, RX_PI
,
510 QED_COAL_RX_STATE_MACHINE
,
513 timeset
= p_hwfn
->cdev
->tx_coalesce_usecs
>>
514 (QED_CAU_DEF_TX_TIMER_RES
+ 1);
516 for (i
= 0; i
< num_tc
; i
++) {
517 qed_int_cau_conf_pi(p_hwfn
, p_ptt
,
519 QED_COAL_TX_STATE_MACHINE
,
525 void qed_int_cau_conf_pi(struct qed_hwfn
*p_hwfn
,
526 struct qed_ptt
*p_ptt
,
529 enum qed_coalescing_fsm coalescing_fsm
,
532 struct cau_pi_entry pi_entry
;
536 sb_offset
= igu_sb_id
* PIS_PER_SB
;
537 memset(&pi_entry
, 0, sizeof(struct cau_pi_entry
));
539 SET_FIELD(pi_entry
.prod
, CAU_PI_ENTRY_PI_TIMESET
, timeset
);
540 if (coalescing_fsm
== QED_COAL_RX_STATE_MACHINE
)
541 SET_FIELD(pi_entry
.prod
, CAU_PI_ENTRY_FSM_SEL
, 0);
543 SET_FIELD(pi_entry
.prod
, CAU_PI_ENTRY_FSM_SEL
, 1);
545 pi_offset
= sb_offset
+ pi_index
;
546 if (p_hwfn
->hw_init_done
) {
547 qed_wr(p_hwfn
, p_ptt
,
548 CAU_REG_PI_MEMORY
+ pi_offset
* sizeof(u32
),
549 *((u32
*)&(pi_entry
)));
552 CAU_REG_PI_MEMORY_RT_OFFSET
+ pi_offset
,
553 *((u32
*)&(pi_entry
)));
557 void qed_int_sb_setup(struct qed_hwfn
*p_hwfn
,
558 struct qed_ptt
*p_ptt
,
559 struct qed_sb_info
*sb_info
)
561 /* zero status block and ack counter */
563 memset(sb_info
->sb_virt
, 0, sizeof(*sb_info
->sb_virt
));
565 qed_int_cau_conf_sb(p_hwfn
, p_ptt
, sb_info
->sb_phys
,
566 sb_info
->igu_sb_id
, 0, 0);
570 * @brief qed_get_igu_sb_id - given a sw sb_id return the
578 static u16
qed_get_igu_sb_id(struct qed_hwfn
*p_hwfn
,
583 /* Assuming continuous set of IGU SBs dedicated for given PF */
584 if (sb_id
== QED_SP_SB_ID
)
585 igu_sb_id
= p_hwfn
->hw_info
.p_igu_info
->igu_dsb_id
;
587 igu_sb_id
= sb_id
+ p_hwfn
->hw_info
.p_igu_info
->igu_base_sb
;
589 DP_VERBOSE(p_hwfn
, NETIF_MSG_INTR
, "SB [%s] index is 0x%04x\n",
590 (sb_id
== QED_SP_SB_ID
) ? "DSB" : "non-DSB", igu_sb_id
);
595 int qed_int_sb_init(struct qed_hwfn
*p_hwfn
,
596 struct qed_ptt
*p_ptt
,
597 struct qed_sb_info
*sb_info
,
599 dma_addr_t sb_phy_addr
,
602 sb_info
->sb_virt
= sb_virt_addr
;
603 sb_info
->sb_phys
= sb_phy_addr
;
605 sb_info
->igu_sb_id
= qed_get_igu_sb_id(p_hwfn
, sb_id
);
607 if (sb_id
!= QED_SP_SB_ID
) {
608 p_hwfn
->sbs_info
[sb_id
] = sb_info
;
612 sb_info
->cdev
= p_hwfn
->cdev
;
614 /* The igu address will hold the absolute address that needs to be
615 * written to for a specific status block
617 sb_info
->igu_addr
= (u8 __iomem
*)p_hwfn
->regview
+
618 GTT_BAR0_MAP_REG_IGU_CMD
+
619 (sb_info
->igu_sb_id
<< 3);
621 sb_info
->flags
|= QED_SB_INFO_INIT
;
623 qed_int_sb_setup(p_hwfn
, p_ptt
, sb_info
);
628 int qed_int_sb_release(struct qed_hwfn
*p_hwfn
,
629 struct qed_sb_info
*sb_info
,
632 if (sb_id
== QED_SP_SB_ID
) {
633 DP_ERR(p_hwfn
, "Do Not free sp sb using this function");
637 /* zero status block and ack counter */
639 memset(sb_info
->sb_virt
, 0, sizeof(*sb_info
->sb_virt
));
641 p_hwfn
->sbs_info
[sb_id
] = NULL
;
647 static void qed_int_sp_sb_free(struct qed_hwfn
*p_hwfn
)
649 struct qed_sb_sp_info
*p_sb
= p_hwfn
->p_sp_sb
;
652 if (p_sb
->sb_info
.sb_virt
)
653 dma_free_coherent(&p_hwfn
->cdev
->pdev
->dev
,
654 SB_ALIGNED_SIZE(p_hwfn
),
655 p_sb
->sb_info
.sb_virt
,
656 p_sb
->sb_info
.sb_phys
);
661 static int qed_int_sp_sb_alloc(struct qed_hwfn
*p_hwfn
,
662 struct qed_ptt
*p_ptt
)
664 struct qed_sb_sp_info
*p_sb
;
665 dma_addr_t p_phys
= 0;
669 p_sb
= kmalloc(sizeof(*p_sb
), GFP_ATOMIC
);
671 DP_NOTICE(p_hwfn
, "Failed to allocate `struct qed_sb_info'\n");
676 p_virt
= dma_alloc_coherent(&p_hwfn
->cdev
->pdev
->dev
,
677 SB_ALIGNED_SIZE(p_hwfn
),
678 &p_phys
, GFP_KERNEL
);
680 DP_NOTICE(p_hwfn
, "Failed to allocate status block\n");
685 /* Status Block setup */
686 p_hwfn
->p_sp_sb
= p_sb
;
687 qed_int_sb_init(p_hwfn
, p_ptt
, &p_sb
->sb_info
, p_virt
,
688 p_phys
, QED_SP_SB_ID
);
690 memset(p_sb
->pi_info_arr
, 0, sizeof(p_sb
->pi_info_arr
));
695 static void qed_int_sp_sb_setup(struct qed_hwfn
*p_hwfn
,
696 struct qed_ptt
*p_ptt
)
702 qed_int_sb_setup(p_hwfn
, p_ptt
, &p_hwfn
->p_sp_sb
->sb_info
);
704 DP_NOTICE(p_hwfn
->cdev
,
705 "Failed to setup Slow path status block - NULL pointer\n");
707 if (p_hwfn
->p_sb_attn
)
708 qed_int_sb_attn_setup(p_hwfn
, p_ptt
);
710 DP_NOTICE(p_hwfn
->cdev
,
711 "Failed to setup attentions status block - NULL pointer\n");
714 int qed_int_register_cb(struct qed_hwfn
*p_hwfn
,
715 qed_int_comp_cb_t comp_cb
,
720 struct qed_sb_sp_info
*p_sp_sb
= p_hwfn
->p_sp_sb
;
721 int qed_status
= -ENOMEM
;
724 /* Look for a free index */
725 for (pi
= 0; pi
< ARRAY_SIZE(p_sp_sb
->pi_info_arr
); pi
++) {
726 if (!p_sp_sb
->pi_info_arr
[pi
].comp_cb
) {
727 p_sp_sb
->pi_info_arr
[pi
].comp_cb
= comp_cb
;
728 p_sp_sb
->pi_info_arr
[pi
].cookie
= cookie
;
730 *p_fw_cons
= &p_sp_sb
->sb_info
.sb_virt
->pi_array
[pi
];
739 int qed_int_unregister_cb(struct qed_hwfn
*p_hwfn
, u8 pi
)
741 struct qed_sb_sp_info
*p_sp_sb
= p_hwfn
->p_sp_sb
;
742 int qed_status
= -ENOMEM
;
744 if (p_sp_sb
->pi_info_arr
[pi
].comp_cb
) {
745 p_sp_sb
->pi_info_arr
[pi
].comp_cb
= NULL
;
746 p_sp_sb
->pi_info_arr
[pi
].cookie
= NULL
;
753 u16
qed_int_get_sp_sb_id(struct qed_hwfn
*p_hwfn
)
755 return p_hwfn
->p_sp_sb
->sb_info
.igu_sb_id
;
758 void qed_int_igu_enable_int(struct qed_hwfn
*p_hwfn
,
759 struct qed_ptt
*p_ptt
,
760 enum qed_int_mode int_mode
)
762 u32 igu_pf_conf
= IGU_PF_CONF_FUNC_EN
| IGU_PF_CONF_ATTN_BIT_EN
;
764 p_hwfn
->cdev
->int_mode
= int_mode
;
765 switch (p_hwfn
->cdev
->int_mode
) {
766 case QED_INT_MODE_INTA
:
767 igu_pf_conf
|= IGU_PF_CONF_INT_LINE_EN
;
768 igu_pf_conf
|= IGU_PF_CONF_SINGLE_ISR_EN
;
771 case QED_INT_MODE_MSI
:
772 igu_pf_conf
|= IGU_PF_CONF_MSI_MSIX_EN
;
773 igu_pf_conf
|= IGU_PF_CONF_SINGLE_ISR_EN
;
776 case QED_INT_MODE_MSIX
:
777 igu_pf_conf
|= IGU_PF_CONF_MSI_MSIX_EN
;
779 case QED_INT_MODE_POLL
:
783 qed_wr(p_hwfn
, p_ptt
, IGU_REG_PF_CONFIGURATION
, igu_pf_conf
);
786 void qed_int_igu_enable(struct qed_hwfn
*p_hwfn
,
787 struct qed_ptt
*p_ptt
,
788 enum qed_int_mode int_mode
)
792 p_hwfn
->b_int_enabled
= 1;
794 /* Mask non-link attentions */
795 for (i
= 0; i
< 9; i
++)
796 qed_wr(p_hwfn
, p_ptt
,
797 MISC_REG_AEU_ENABLE1_IGU_OUT_0
+ (i
<< 2), 0);
799 /* Enable interrupt Generation */
800 qed_int_igu_enable_int(p_hwfn
, p_ptt
, int_mode
);
802 /* Configure AEU signal change to produce attentions for link */
803 qed_wr(p_hwfn
, p_ptt
, IGU_REG_LEADING_EDGE_LATCH
, 0xfff);
804 qed_wr(p_hwfn
, p_ptt
, IGU_REG_TRAILING_EDGE_LATCH
, 0xfff);
806 /* Flush the writes to IGU */
809 /* Unmask AEU signals toward IGU */
810 qed_wr(p_hwfn
, p_ptt
, MISC_REG_AEU_MASK_ATTN_IGU
, 0xff);
813 void qed_int_igu_disable_int(struct qed_hwfn
*p_hwfn
,
814 struct qed_ptt
*p_ptt
)
816 p_hwfn
->b_int_enabled
= 0;
818 qed_wr(p_hwfn
, p_ptt
, IGU_REG_PF_CONFIGURATION
, 0);
821 #define IGU_CLEANUP_SLEEP_LENGTH (1000)
822 void qed_int_igu_cleanup_sb(struct qed_hwfn
*p_hwfn
,
823 struct qed_ptt
*p_ptt
,
829 u32 pxp_addr
= IGU_CMD_INT_ACK_BASE
+ sb_id
;
830 u32 sleep_cnt
= IGU_CLEANUP_SLEEP_LENGTH
;
837 /* Set the data field */
838 SET_FIELD(data
, IGU_CLEANUP_CLEANUP_SET
, cleanup_set
? 1 : 0);
839 SET_FIELD(data
, IGU_CLEANUP_CLEANUP_TYPE
, 0);
840 SET_FIELD(data
, IGU_CLEANUP_COMMAND_TYPE
, IGU_COMMAND_TYPE_SET
);
842 /* Set the control register */
843 SET_FIELD(cmd_ctrl
, IGU_CTRL_REG_PXP_ADDR
, pxp_addr
);
844 SET_FIELD(cmd_ctrl
, IGU_CTRL_REG_FID
, opaque_fid
);
845 SET_FIELD(cmd_ctrl
, IGU_CTRL_REG_TYPE
, IGU_CTRL_CMD_TYPE_WR
);
847 qed_wr(p_hwfn
, p_ptt
, IGU_REG_COMMAND_REG_32LSB_DATA
, data
);
851 qed_wr(p_hwfn
, p_ptt
, IGU_REG_COMMAND_REG_CTRL
, cmd_ctrl
);
853 /* Flush the write to IGU */
856 /* calculate where to read the status bit from */
857 sb_bit
= 1 << (sb_id
% 32);
858 sb_bit_addr
= sb_id
/ 32 * sizeof(u32
);
860 sb_bit_addr
+= IGU_REG_CLEANUP_STATUS_0
;
862 /* Now wait for the command to complete */
864 val
= qed_rd(p_hwfn
, p_ptt
, sb_bit_addr
);
866 if ((val
& sb_bit
) == (cleanup_set
? sb_bit
: 0))
869 usleep_range(5000, 10000);
870 } while (--sleep_cnt
);
874 "Timeout waiting for clear status 0x%08x [for sb %d]\n",
878 void qed_int_igu_init_pure_rt_single(struct qed_hwfn
*p_hwfn
,
879 struct qed_ptt
*p_ptt
,
888 qed_int_igu_cleanup_sb(p_hwfn
, p_ptt
, sb_id
, 1, opaque
);
891 qed_int_igu_cleanup_sb(p_hwfn
, p_ptt
, sb_id
, 0, opaque
);
893 /* Clear the CAU for the SB */
894 for (pi
= 0; pi
< 12; pi
++)
895 qed_wr(p_hwfn
, p_ptt
,
896 CAU_REG_PI_MEMORY
+ (sb_id
* 12 + pi
) * 4, 0);
899 void qed_int_igu_init_pure_rt(struct qed_hwfn
*p_hwfn
,
900 struct qed_ptt
*p_ptt
,
904 u32 igu_base_sb
= p_hwfn
->hw_info
.p_igu_info
->igu_base_sb
;
905 u32 igu_sb_cnt
= p_hwfn
->hw_info
.p_igu_info
->igu_sb_cnt
;
909 val
= qed_rd(p_hwfn
, p_ptt
, IGU_REG_BLOCK_CONFIGURATION
);
910 val
|= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN
;
911 val
&= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN
;
912 qed_wr(p_hwfn
, p_ptt
, IGU_REG_BLOCK_CONFIGURATION
, val
);
914 DP_VERBOSE(p_hwfn
, NETIF_MSG_INTR
,
915 "IGU cleaning SBs [%d,...,%d]\n",
916 igu_base_sb
, igu_base_sb
+ igu_sb_cnt
- 1);
918 for (sb_id
= igu_base_sb
; sb_id
< igu_base_sb
+ igu_sb_cnt
; sb_id
++)
919 qed_int_igu_init_pure_rt_single(p_hwfn
, p_ptt
, sb_id
,
920 p_hwfn
->hw_info
.opaque_fid
,
924 sb_id
= p_hwfn
->hw_info
.p_igu_info
->igu_dsb_id
;
925 DP_VERBOSE(p_hwfn
, NETIF_MSG_INTR
,
926 "IGU cleaning slowpath SB [%d]\n", sb_id
);
927 qed_int_igu_init_pure_rt_single(p_hwfn
, p_ptt
, sb_id
,
928 p_hwfn
->hw_info
.opaque_fid
,
933 int qed_int_igu_read_cam(struct qed_hwfn
*p_hwfn
,
934 struct qed_ptt
*p_ptt
)
936 struct qed_igu_info
*p_igu_info
;
937 struct qed_igu_block
*blk
;
940 u16 prev_sb_id
= 0xFF;
942 p_hwfn
->hw_info
.p_igu_info
= kzalloc(sizeof(*p_igu_info
), GFP_ATOMIC
);
944 if (!p_hwfn
->hw_info
.p_igu_info
)
947 p_igu_info
= p_hwfn
->hw_info
.p_igu_info
;
949 /* Initialize base sb / sb cnt for PFs */
950 p_igu_info
->igu_base_sb
= 0xffff;
951 p_igu_info
->igu_sb_cnt
= 0;
952 p_igu_info
->igu_dsb_id
= 0xffff;
953 p_igu_info
->igu_base_sb_iov
= 0xffff;
955 for (sb_id
= 0; sb_id
< QED_MAPPING_MEMORY_SIZE(p_hwfn
->cdev
);
957 blk
= &p_igu_info
->igu_map
.igu_blocks
[sb_id
];
959 val
= qed_rd(p_hwfn
, p_ptt
,
960 IGU_REG_MAPPING_MEMORY
+ sizeof(u32
) * sb_id
);
962 /* stop scanning when hit first invalid PF entry */
963 if (!GET_FIELD(val
, IGU_MAPPING_LINE_VALID
) &&
964 GET_FIELD(val
, IGU_MAPPING_LINE_PF_VALID
))
967 blk
->status
= QED_IGU_STATUS_VALID
;
968 blk
->function_id
= GET_FIELD(val
,
969 IGU_MAPPING_LINE_FUNCTION_NUMBER
);
970 blk
->is_pf
= GET_FIELD(val
, IGU_MAPPING_LINE_PF_VALID
);
971 blk
->vector_number
= GET_FIELD(val
,
972 IGU_MAPPING_LINE_VECTOR_NUMBER
);
974 DP_VERBOSE(p_hwfn
, NETIF_MSG_INTR
,
975 "IGU_BLOCK[sb_id]:%x:func_id = %d is_pf = %d vector_num = 0x%x\n",
976 val
, blk
->function_id
, blk
->is_pf
,
980 if (blk
->function_id
== p_hwfn
->rel_pf_id
) {
981 blk
->status
|= QED_IGU_STATUS_PF
;
983 if (blk
->vector_number
== 0) {
984 if (p_igu_info
->igu_dsb_id
== 0xffff)
985 p_igu_info
->igu_dsb_id
= sb_id
;
987 if (p_igu_info
->igu_base_sb
==
989 p_igu_info
->igu_base_sb
= sb_id
;
990 } else if (prev_sb_id
!= sb_id
- 1) {
991 DP_NOTICE(p_hwfn
->cdev
,
992 "consecutive igu vectors for HWFN %x broken",
997 /* we don't count the default */
998 (p_igu_info
->igu_sb_cnt
)++;
1004 DP_VERBOSE(p_hwfn
, NETIF_MSG_INTR
,
1005 "IGU igu_base_sb=0x%x igu_sb_cnt=%d igu_dsb_id=0x%x\n",
1006 p_igu_info
->igu_base_sb
,
1007 p_igu_info
->igu_sb_cnt
,
1008 p_igu_info
->igu_dsb_id
);
1010 if (p_igu_info
->igu_base_sb
== 0xffff ||
1011 p_igu_info
->igu_dsb_id
== 0xffff ||
1012 p_igu_info
->igu_sb_cnt
== 0) {
1014 "IGU CAM returned invalid values igu_base_sb=0x%x igu_sb_cnt=%d igu_dsb_id=0x%x\n",
1015 p_igu_info
->igu_base_sb
,
1016 p_igu_info
->igu_sb_cnt
,
1017 p_igu_info
->igu_dsb_id
);
1025 * @brief Initialize igu runtime registers
1029 void qed_int_igu_init_rt(struct qed_hwfn
*p_hwfn
)
1031 u32 igu_pf_conf
= 0;
1033 igu_pf_conf
|= IGU_PF_CONF_FUNC_EN
;
1035 STORE_RT_REG(p_hwfn
, IGU_REG_PF_CONFIGURATION_RT_OFFSET
, igu_pf_conf
);
1038 u64
qed_int_igu_read_sisr_reg(struct qed_hwfn
*p_hwfn
)
1040 u64 intr_status
= 0;
1041 u32 intr_status_lo
= 0;
1042 u32 intr_status_hi
= 0;
1043 u32 lsb_igu_cmd_addr
= IGU_REG_SISR_MDPC_WMASK_LSB_UPPER
-
1044 IGU_CMD_INT_ACK_BASE
;
1045 u32 msb_igu_cmd_addr
= IGU_REG_SISR_MDPC_WMASK_MSB_UPPER
-
1046 IGU_CMD_INT_ACK_BASE
;
1048 intr_status_lo
= REG_RD(p_hwfn
,
1049 GTT_BAR0_MAP_REG_IGU_CMD
+
1050 lsb_igu_cmd_addr
* 8);
1051 intr_status_hi
= REG_RD(p_hwfn
,
1052 GTT_BAR0_MAP_REG_IGU_CMD
+
1053 msb_igu_cmd_addr
* 8);
1054 intr_status
= ((u64
)intr_status_hi
<< 32) + (u64
)intr_status_lo
;
1059 static void qed_int_sp_dpc_setup(struct qed_hwfn
*p_hwfn
)
1061 tasklet_init(p_hwfn
->sp_dpc
,
1062 qed_int_sp_dpc
, (unsigned long)p_hwfn
);
1063 p_hwfn
->b_sp_dpc_enabled
= true;
1066 static int qed_int_sp_dpc_alloc(struct qed_hwfn
*p_hwfn
)
1068 p_hwfn
->sp_dpc
= kmalloc(sizeof(*p_hwfn
->sp_dpc
), GFP_ATOMIC
);
1069 if (!p_hwfn
->sp_dpc
)
1075 static void qed_int_sp_dpc_free(struct qed_hwfn
*p_hwfn
)
1077 kfree(p_hwfn
->sp_dpc
);
1080 int qed_int_alloc(struct qed_hwfn
*p_hwfn
,
1081 struct qed_ptt
*p_ptt
)
1085 rc
= qed_int_sp_dpc_alloc(p_hwfn
);
1087 DP_ERR(p_hwfn
->cdev
, "Failed to allocate sp dpc mem\n");
1090 rc
= qed_int_sp_sb_alloc(p_hwfn
, p_ptt
);
1092 DP_ERR(p_hwfn
->cdev
, "Failed to allocate sp sb mem\n");
1095 rc
= qed_int_sb_attn_alloc(p_hwfn
, p_ptt
);
1097 DP_ERR(p_hwfn
->cdev
, "Failed to allocate sb attn mem\n");
1103 void qed_int_free(struct qed_hwfn
*p_hwfn
)
1105 qed_int_sp_sb_free(p_hwfn
);
1106 qed_int_sb_attn_free(p_hwfn
);
1107 qed_int_sp_dpc_free(p_hwfn
);
1110 void qed_int_setup(struct qed_hwfn
*p_hwfn
,
1111 struct qed_ptt
*p_ptt
)
1113 qed_int_sp_sb_setup(p_hwfn
, p_ptt
);
1114 qed_int_sp_dpc_setup(p_hwfn
);
1117 int qed_int_get_num_sbs(struct qed_hwfn
*p_hwfn
,
1120 struct qed_igu_info
*info
= p_hwfn
->hw_info
.p_igu_info
;
1126 *p_iov_blks
= info
->free_blks
;
1128 return info
->igu_sb_cnt
;