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1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
3 *
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
6 * this source tree.
7 */
8
9 #include <linux/stddef.h>
10 #include <linux/pci.h>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/version.h>
14 #include <linux/delay.h>
15 #include <asm/byteorder.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/string.h>
18 #include <linux/module.h>
19 #include <linux/interrupt.h>
20 #include <linux/workqueue.h>
21 #include <linux/ethtool.h>
22 #include <linux/etherdevice.h>
23 #include <linux/vmalloc.h>
24 #include <linux/qed/qed_if.h>
25
26 #include "qed.h"
27 #include "qed_sp.h"
28 #include "qed_dev_api.h"
29 #include "qed_mcp.h"
30 #include "qed_hw.h"
31
32 static const char version[] =
33 "QLogic QL4xxx 40G/100G Ethernet Driver qed " DRV_MODULE_VERSION "\n";
34
35 MODULE_DESCRIPTION("QLogic 25G/40G/50G/100G Core Module");
36 MODULE_LICENSE("GPL");
37 MODULE_VERSION(DRV_MODULE_VERSION);
38
39 #define FW_FILE_VERSION \
40 __stringify(FW_MAJOR_VERSION) "." \
41 __stringify(FW_MINOR_VERSION) "." \
42 __stringify(FW_REVISION_VERSION) "." \
43 __stringify(FW_ENGINEERING_VERSION)
44
45 #define QED_FW_FILE_NAME \
46 "qed/qed_init_values_zipped-" FW_FILE_VERSION ".bin"
47
48 MODULE_FIRMWARE(QED_FW_FILE_NAME);
49
50 static int __init qed_init(void)
51 {
52 pr_notice("qed_init called\n");
53
54 pr_info("%s", version);
55
56 return 0;
57 }
58
59 static void __exit qed_cleanup(void)
60 {
61 pr_notice("qed_cleanup called\n");
62 }
63
64 module_init(qed_init);
65 module_exit(qed_cleanup);
66
67 /* Check if the DMA controller on the machine can properly handle the DMA
68 * addressing required by the device.
69 */
70 static int qed_set_coherency_mask(struct qed_dev *cdev)
71 {
72 struct device *dev = &cdev->pdev->dev;
73
74 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
75 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
76 DP_NOTICE(cdev,
77 "Can't request 64-bit consistent allocations\n");
78 return -EIO;
79 }
80 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
81 DP_NOTICE(cdev, "Can't request 64b/32b DMA addresses\n");
82 return -EIO;
83 }
84
85 return 0;
86 }
87
88 static void qed_free_pci(struct qed_dev *cdev)
89 {
90 struct pci_dev *pdev = cdev->pdev;
91
92 if (cdev->doorbells)
93 iounmap(cdev->doorbells);
94 if (cdev->regview)
95 iounmap(cdev->regview);
96 if (atomic_read(&pdev->enable_cnt) == 1)
97 pci_release_regions(pdev);
98
99 pci_disable_device(pdev);
100 }
101
102 /* Performs PCI initializations as well as initializing PCI-related parameters
103 * in the device structrue. Returns 0 in case of success.
104 */
105 static int qed_init_pci(struct qed_dev *cdev,
106 struct pci_dev *pdev)
107 {
108 int rc;
109
110 cdev->pdev = pdev;
111
112 rc = pci_enable_device(pdev);
113 if (rc) {
114 DP_NOTICE(cdev, "Cannot enable PCI device\n");
115 goto err0;
116 }
117
118 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
119 DP_NOTICE(cdev, "No memory region found in bar #0\n");
120 rc = -EIO;
121 goto err1;
122 }
123
124 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
125 DP_NOTICE(cdev, "No memory region found in bar #2\n");
126 rc = -EIO;
127 goto err1;
128 }
129
130 if (atomic_read(&pdev->enable_cnt) == 1) {
131 rc = pci_request_regions(pdev, "qed");
132 if (rc) {
133 DP_NOTICE(cdev,
134 "Failed to request PCI memory resources\n");
135 goto err1;
136 }
137 pci_set_master(pdev);
138 pci_save_state(pdev);
139 }
140
141 if (!pci_is_pcie(pdev)) {
142 DP_NOTICE(cdev, "The bus is not PCI Express\n");
143 rc = -EIO;
144 goto err2;
145 }
146
147 cdev->pci_params.pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
148 if (cdev->pci_params.pm_cap == 0)
149 DP_NOTICE(cdev, "Cannot find power management capability\n");
150
151 rc = qed_set_coherency_mask(cdev);
152 if (rc)
153 goto err2;
154
155 cdev->pci_params.mem_start = pci_resource_start(pdev, 0);
156 cdev->pci_params.mem_end = pci_resource_end(pdev, 0);
157 cdev->pci_params.irq = pdev->irq;
158
159 cdev->regview = pci_ioremap_bar(pdev, 0);
160 if (!cdev->regview) {
161 DP_NOTICE(cdev, "Cannot map register space, aborting\n");
162 rc = -ENOMEM;
163 goto err2;
164 }
165
166 cdev->db_phys_addr = pci_resource_start(cdev->pdev, 2);
167 cdev->db_size = pci_resource_len(cdev->pdev, 2);
168 cdev->doorbells = ioremap_wc(cdev->db_phys_addr, cdev->db_size);
169 if (!cdev->doorbells) {
170 DP_NOTICE(cdev, "Cannot map doorbell space\n");
171 return -ENOMEM;
172 }
173
174 return 0;
175
176 err2:
177 pci_release_regions(pdev);
178 err1:
179 pci_disable_device(pdev);
180 err0:
181 return rc;
182 }
183
184 int qed_fill_dev_info(struct qed_dev *cdev,
185 struct qed_dev_info *dev_info)
186 {
187 struct qed_ptt *ptt;
188
189 memset(dev_info, 0, sizeof(struct qed_dev_info));
190
191 dev_info->num_hwfns = cdev->num_hwfns;
192 dev_info->pci_mem_start = cdev->pci_params.mem_start;
193 dev_info->pci_mem_end = cdev->pci_params.mem_end;
194 dev_info->pci_irq = cdev->pci_params.irq;
195 dev_info->is_mf_default = IS_MF_DEFAULT(&cdev->hwfns[0]);
196 ether_addr_copy(dev_info->hw_mac, cdev->hwfns[0].hw_info.hw_mac_addr);
197
198 dev_info->fw_major = FW_MAJOR_VERSION;
199 dev_info->fw_minor = FW_MINOR_VERSION;
200 dev_info->fw_rev = FW_REVISION_VERSION;
201 dev_info->fw_eng = FW_ENGINEERING_VERSION;
202 dev_info->mf_mode = cdev->mf_mode;
203
204 qed_mcp_get_mfw_ver(cdev, &dev_info->mfw_rev);
205
206 ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev));
207 if (ptt) {
208 qed_mcp_get_flash_size(QED_LEADING_HWFN(cdev), ptt,
209 &dev_info->flash_size);
210
211 qed_ptt_release(QED_LEADING_HWFN(cdev), ptt);
212 }
213
214 return 0;
215 }
216
217 static void qed_free_cdev(struct qed_dev *cdev)
218 {
219 kfree((void *)cdev);
220 }
221
222 static struct qed_dev *qed_alloc_cdev(struct pci_dev *pdev)
223 {
224 struct qed_dev *cdev;
225
226 cdev = kzalloc(sizeof(*cdev), GFP_KERNEL);
227 if (!cdev)
228 return cdev;
229
230 qed_init_struct(cdev);
231
232 return cdev;
233 }
234
235 /* Sets the requested power state */
236 static int qed_set_power_state(struct qed_dev *cdev,
237 pci_power_t state)
238 {
239 if (!cdev)
240 return -ENODEV;
241
242 DP_VERBOSE(cdev, NETIF_MSG_DRV, "Omitting Power state change\n");
243 return 0;
244 }
245
246 /* probing */
247 static struct qed_dev *qed_probe(struct pci_dev *pdev,
248 enum qed_protocol protocol,
249 u32 dp_module,
250 u8 dp_level)
251 {
252 struct qed_dev *cdev;
253 int rc;
254
255 cdev = qed_alloc_cdev(pdev);
256 if (!cdev)
257 goto err0;
258
259 cdev->protocol = protocol;
260
261 qed_init_dp(cdev, dp_module, dp_level);
262
263 rc = qed_init_pci(cdev, pdev);
264 if (rc) {
265 DP_ERR(cdev, "init pci failed\n");
266 goto err1;
267 }
268 DP_INFO(cdev, "PCI init completed successfully\n");
269
270 rc = qed_hw_prepare(cdev, QED_PCI_DEFAULT);
271 if (rc) {
272 DP_ERR(cdev, "hw prepare failed\n");
273 goto err2;
274 }
275
276 DP_INFO(cdev, "qed_probe completed successffuly\n");
277
278 return cdev;
279
280 err2:
281 qed_free_pci(cdev);
282 err1:
283 qed_free_cdev(cdev);
284 err0:
285 return NULL;
286 }
287
288 static void qed_remove(struct qed_dev *cdev)
289 {
290 if (!cdev)
291 return;
292
293 qed_hw_remove(cdev);
294
295 qed_free_pci(cdev);
296
297 qed_set_power_state(cdev, PCI_D3hot);
298
299 qed_free_cdev(cdev);
300 }
301
302 static void qed_disable_msix(struct qed_dev *cdev)
303 {
304 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
305 pci_disable_msix(cdev->pdev);
306 kfree(cdev->int_params.msix_table);
307 } else if (cdev->int_params.out.int_mode == QED_INT_MODE_MSI) {
308 pci_disable_msi(cdev->pdev);
309 }
310
311 memset(&cdev->int_params.out, 0, sizeof(struct qed_int_param));
312 }
313
314 static int qed_enable_msix(struct qed_dev *cdev,
315 struct qed_int_params *int_params)
316 {
317 int i, rc, cnt;
318
319 cnt = int_params->in.num_vectors;
320
321 for (i = 0; i < cnt; i++)
322 int_params->msix_table[i].entry = i;
323
324 rc = pci_enable_msix_range(cdev->pdev, int_params->msix_table,
325 int_params->in.min_msix_cnt, cnt);
326 if (rc < cnt && rc >= int_params->in.min_msix_cnt &&
327 (rc % cdev->num_hwfns)) {
328 pci_disable_msix(cdev->pdev);
329
330 /* If fastpath is initialized, we need at least one interrupt
331 * per hwfn [and the slow path interrupts]. New requested number
332 * should be a multiple of the number of hwfns.
333 */
334 cnt = (rc / cdev->num_hwfns) * cdev->num_hwfns;
335 DP_NOTICE(cdev,
336 "Trying to enable MSI-X with less vectors (%d out of %d)\n",
337 cnt, int_params->in.num_vectors);
338 rc = pci_enable_msix_exact(cdev->pdev,
339 int_params->msix_table, cnt);
340 if (!rc)
341 rc = cnt;
342 }
343
344 if (rc > 0) {
345 /* MSI-x configuration was achieved */
346 int_params->out.int_mode = QED_INT_MODE_MSIX;
347 int_params->out.num_vectors = rc;
348 rc = 0;
349 } else {
350 DP_NOTICE(cdev,
351 "Failed to enable MSI-X [Requested %d vectors][rc %d]\n",
352 cnt, rc);
353 }
354
355 return rc;
356 }
357
358 /* This function outputs the int mode and the number of enabled msix vector */
359 static int qed_set_int_mode(struct qed_dev *cdev, bool force_mode)
360 {
361 struct qed_int_params *int_params = &cdev->int_params;
362 struct msix_entry *tbl;
363 int rc = 0, cnt;
364
365 switch (int_params->in.int_mode) {
366 case QED_INT_MODE_MSIX:
367 /* Allocate MSIX table */
368 cnt = int_params->in.num_vectors;
369 int_params->msix_table = kcalloc(cnt, sizeof(*tbl), GFP_KERNEL);
370 if (!int_params->msix_table) {
371 rc = -ENOMEM;
372 goto out;
373 }
374
375 /* Enable MSIX */
376 rc = qed_enable_msix(cdev, int_params);
377 if (!rc)
378 goto out;
379
380 DP_NOTICE(cdev, "Failed to enable MSI-X\n");
381 kfree(int_params->msix_table);
382 if (force_mode)
383 goto out;
384 /* Fallthrough */
385
386 case QED_INT_MODE_MSI:
387 rc = pci_enable_msi(cdev->pdev);
388 if (!rc) {
389 int_params->out.int_mode = QED_INT_MODE_MSI;
390 goto out;
391 }
392
393 DP_NOTICE(cdev, "Failed to enable MSI\n");
394 if (force_mode)
395 goto out;
396 /* Fallthrough */
397
398 case QED_INT_MODE_INTA:
399 int_params->out.int_mode = QED_INT_MODE_INTA;
400 rc = 0;
401 goto out;
402 default:
403 DP_NOTICE(cdev, "Unknown int_mode value %d\n",
404 int_params->in.int_mode);
405 rc = -EINVAL;
406 }
407
408 out:
409 cdev->int_coalescing_mode = QED_COAL_MODE_ENABLE;
410
411 return rc;
412 }
413
414 static void qed_simd_handler_config(struct qed_dev *cdev, void *token,
415 int index, void(*handler)(void *))
416 {
417 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns];
418 int relative_idx = index / cdev->num_hwfns;
419
420 hwfn->simd_proto_handler[relative_idx].func = handler;
421 hwfn->simd_proto_handler[relative_idx].token = token;
422 }
423
424 static void qed_simd_handler_clean(struct qed_dev *cdev, int index)
425 {
426 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns];
427 int relative_idx = index / cdev->num_hwfns;
428
429 memset(&hwfn->simd_proto_handler[relative_idx], 0,
430 sizeof(struct qed_simd_fp_handler));
431 }
432
433 static irqreturn_t qed_msix_sp_int(int irq, void *tasklet)
434 {
435 tasklet_schedule((struct tasklet_struct *)tasklet);
436 return IRQ_HANDLED;
437 }
438
439 static irqreturn_t qed_single_int(int irq, void *dev_instance)
440 {
441 struct qed_dev *cdev = (struct qed_dev *)dev_instance;
442 struct qed_hwfn *hwfn;
443 irqreturn_t rc = IRQ_NONE;
444 u64 status;
445 int i, j;
446
447 for (i = 0; i < cdev->num_hwfns; i++) {
448 status = qed_int_igu_read_sisr_reg(&cdev->hwfns[i]);
449
450 if (!status)
451 continue;
452
453 hwfn = &cdev->hwfns[i];
454
455 /* Slowpath interrupt */
456 if (unlikely(status & 0x1)) {
457 tasklet_schedule(hwfn->sp_dpc);
458 status &= ~0x1;
459 rc = IRQ_HANDLED;
460 }
461
462 /* Fastpath interrupts */
463 for (j = 0; j < 64; j++) {
464 if ((0x2ULL << j) & status) {
465 hwfn->simd_proto_handler[j].func(
466 hwfn->simd_proto_handler[j].token);
467 status &= ~(0x2ULL << j);
468 rc = IRQ_HANDLED;
469 }
470 }
471
472 if (unlikely(status))
473 DP_VERBOSE(hwfn, NETIF_MSG_INTR,
474 "got an unknown interrupt status 0x%llx\n",
475 status);
476 }
477
478 return rc;
479 }
480
481 int qed_slowpath_irq_req(struct qed_hwfn *hwfn)
482 {
483 struct qed_dev *cdev = hwfn->cdev;
484 int rc = 0;
485 u8 id;
486
487 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
488 id = hwfn->my_id;
489 snprintf(hwfn->name, NAME_SIZE, "sp-%d-%02x:%02x.%02x",
490 id, cdev->pdev->bus->number,
491 PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id);
492 rc = request_irq(cdev->int_params.msix_table[id].vector,
493 qed_msix_sp_int, 0, hwfn->name, hwfn->sp_dpc);
494 if (!rc)
495 DP_VERBOSE(hwfn, (NETIF_MSG_INTR | QED_MSG_SP),
496 "Requested slowpath MSI-X\n");
497 } else {
498 unsigned long flags = 0;
499
500 snprintf(cdev->name, NAME_SIZE, "%02x:%02x.%02x",
501 cdev->pdev->bus->number, PCI_SLOT(cdev->pdev->devfn),
502 PCI_FUNC(cdev->pdev->devfn));
503
504 if (cdev->int_params.out.int_mode == QED_INT_MODE_INTA)
505 flags |= IRQF_SHARED;
506
507 rc = request_irq(cdev->pdev->irq, qed_single_int,
508 flags, cdev->name, cdev);
509 }
510
511 return rc;
512 }
513
514 static void qed_slowpath_irq_free(struct qed_dev *cdev)
515 {
516 int i;
517
518 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
519 for_each_hwfn(cdev, i) {
520 if (!cdev->hwfns[i].b_int_requested)
521 break;
522 synchronize_irq(cdev->int_params.msix_table[i].vector);
523 free_irq(cdev->int_params.msix_table[i].vector,
524 cdev->hwfns[i].sp_dpc);
525 }
526 } else {
527 if (QED_LEADING_HWFN(cdev)->b_int_requested)
528 free_irq(cdev->pdev->irq, cdev);
529 }
530 qed_int_disable_post_isr_release(cdev);
531 }
532
533 static int qed_nic_stop(struct qed_dev *cdev)
534 {
535 int i, rc;
536
537 rc = qed_hw_stop(cdev);
538
539 for (i = 0; i < cdev->num_hwfns; i++) {
540 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
541
542 if (p_hwfn->b_sp_dpc_enabled) {
543 tasklet_disable(p_hwfn->sp_dpc);
544 p_hwfn->b_sp_dpc_enabled = false;
545 DP_VERBOSE(cdev, NETIF_MSG_IFDOWN,
546 "Disabled sp taskelt [hwfn %d] at %p\n",
547 i, p_hwfn->sp_dpc);
548 }
549 }
550
551 return rc;
552 }
553
554 static int qed_nic_reset(struct qed_dev *cdev)
555 {
556 int rc;
557
558 rc = qed_hw_reset(cdev);
559 if (rc)
560 return rc;
561
562 qed_resc_free(cdev);
563
564 return 0;
565 }
566
567 static int qed_nic_setup(struct qed_dev *cdev)
568 {
569 int rc;
570
571 rc = qed_resc_alloc(cdev);
572 if (rc)
573 return rc;
574
575 DP_INFO(cdev, "Allocated qed resources\n");
576
577 qed_resc_setup(cdev);
578
579 return rc;
580 }
581
582 static int qed_set_int_fp(struct qed_dev *cdev, u16 cnt)
583 {
584 int limit = 0;
585
586 /* Mark the fastpath as free/used */
587 cdev->int_params.fp_initialized = cnt ? true : false;
588
589 if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX)
590 limit = cdev->num_hwfns * 63;
591 else if (cdev->int_params.fp_msix_cnt)
592 limit = cdev->int_params.fp_msix_cnt;
593
594 if (!limit)
595 return -ENOMEM;
596
597 return min_t(int, cnt, limit);
598 }
599
600 static int qed_get_int_fp(struct qed_dev *cdev, struct qed_int_info *info)
601 {
602 memset(info, 0, sizeof(struct qed_int_info));
603
604 if (!cdev->int_params.fp_initialized) {
605 DP_INFO(cdev,
606 "Protocol driver requested interrupt information, but its support is not yet configured\n");
607 return -EINVAL;
608 }
609
610 /* Need to expose only MSI-X information; Single IRQ is handled solely
611 * by qed.
612 */
613 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
614 int msix_base = cdev->int_params.fp_msix_base;
615
616 info->msix_cnt = cdev->int_params.fp_msix_cnt;
617 info->msix = &cdev->int_params.msix_table[msix_base];
618 }
619
620 return 0;
621 }
622
623 static int qed_slowpath_setup_int(struct qed_dev *cdev,
624 enum qed_int_mode int_mode)
625 {
626 int rc, i;
627 u8 num_vectors = 0;
628
629 memset(&cdev->int_params, 0, sizeof(struct qed_int_params));
630
631 cdev->int_params.in.int_mode = int_mode;
632 for_each_hwfn(cdev, i)
633 num_vectors += qed_int_get_num_sbs(&cdev->hwfns[i], NULL) + 1;
634 cdev->int_params.in.num_vectors = num_vectors;
635
636 /* We want a minimum of one slowpath and one fastpath vector per hwfn */
637 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns * 2;
638
639 rc = qed_set_int_mode(cdev, false);
640 if (rc) {
641 DP_ERR(cdev, "qed_slowpath_setup_int ERR\n");
642 return rc;
643 }
644
645 cdev->int_params.fp_msix_base = cdev->num_hwfns;
646 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors -
647 cdev->num_hwfns;
648
649 return 0;
650 }
651
652 u32 qed_unzip_data(struct qed_hwfn *p_hwfn, u32 input_len,
653 u8 *input_buf, u32 max_size, u8 *unzip_buf)
654 {
655 int rc;
656
657 p_hwfn->stream->next_in = input_buf;
658 p_hwfn->stream->avail_in = input_len;
659 p_hwfn->stream->next_out = unzip_buf;
660 p_hwfn->stream->avail_out = max_size;
661
662 rc = zlib_inflateInit2(p_hwfn->stream, MAX_WBITS);
663
664 if (rc != Z_OK) {
665 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "zlib init failed, rc = %d\n",
666 rc);
667 return 0;
668 }
669
670 rc = zlib_inflate(p_hwfn->stream, Z_FINISH);
671 zlib_inflateEnd(p_hwfn->stream);
672
673 if (rc != Z_OK && rc != Z_STREAM_END) {
674 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "FW unzip error: %s, rc=%d\n",
675 p_hwfn->stream->msg, rc);
676 return 0;
677 }
678
679 return p_hwfn->stream->total_out / 4;
680 }
681
682 static int qed_alloc_stream_mem(struct qed_dev *cdev)
683 {
684 int i;
685 void *workspace;
686
687 for_each_hwfn(cdev, i) {
688 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
689
690 p_hwfn->stream = kzalloc(sizeof(*p_hwfn->stream), GFP_KERNEL);
691 if (!p_hwfn->stream)
692 return -ENOMEM;
693
694 workspace = vzalloc(zlib_inflate_workspacesize());
695 if (!workspace)
696 return -ENOMEM;
697 p_hwfn->stream->workspace = workspace;
698 }
699
700 return 0;
701 }
702
703 static void qed_free_stream_mem(struct qed_dev *cdev)
704 {
705 int i;
706
707 for_each_hwfn(cdev, i) {
708 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
709
710 if (!p_hwfn->stream)
711 return;
712
713 vfree(p_hwfn->stream->workspace);
714 kfree(p_hwfn->stream);
715 }
716 }
717
718 static void qed_update_pf_params(struct qed_dev *cdev,
719 struct qed_pf_params *params)
720 {
721 int i;
722
723 for (i = 0; i < cdev->num_hwfns; i++) {
724 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
725
726 p_hwfn->pf_params = *params;
727 }
728 }
729
730 static int qed_slowpath_start(struct qed_dev *cdev,
731 struct qed_slowpath_params *params)
732 {
733 struct qed_mcp_drv_version drv_version;
734 const u8 *data = NULL;
735 struct qed_hwfn *hwfn;
736 int rc;
737
738 rc = request_firmware(&cdev->firmware, QED_FW_FILE_NAME,
739 &cdev->pdev->dev);
740 if (rc) {
741 DP_NOTICE(cdev,
742 "Failed to find fw file - /lib/firmware/%s\n",
743 QED_FW_FILE_NAME);
744 goto err;
745 }
746
747 rc = qed_nic_setup(cdev);
748 if (rc)
749 goto err;
750
751 rc = qed_slowpath_setup_int(cdev, params->int_mode);
752 if (rc)
753 goto err1;
754
755 /* Allocate stream for unzipping */
756 rc = qed_alloc_stream_mem(cdev);
757 if (rc) {
758 DP_NOTICE(cdev, "Failed to allocate stream memory\n");
759 goto err2;
760 }
761
762 /* Start the slowpath */
763 data = cdev->firmware->data;
764
765 rc = qed_hw_init(cdev, true, cdev->int_params.out.int_mode,
766 true, data);
767 if (rc)
768 goto err3;
769
770 DP_INFO(cdev,
771 "HW initialization and function start completed successfully\n");
772
773 hwfn = QED_LEADING_HWFN(cdev);
774 drv_version.version = (params->drv_major << 24) |
775 (params->drv_minor << 16) |
776 (params->drv_rev << 8) |
777 (params->drv_eng);
778 strlcpy(drv_version.name, params->name,
779 MCP_DRV_VER_STR_SIZE - 4);
780 rc = qed_mcp_send_drv_version(hwfn, hwfn->p_main_ptt,
781 &drv_version);
782 if (rc) {
783 DP_NOTICE(cdev, "Failed sending drv version command\n");
784 return rc;
785 }
786
787 return 0;
788
789 err3:
790 qed_free_stream_mem(cdev);
791 qed_slowpath_irq_free(cdev);
792 err2:
793 qed_disable_msix(cdev);
794 err1:
795 qed_resc_free(cdev);
796 err:
797 release_firmware(cdev->firmware);
798
799 return rc;
800 }
801
802 static int qed_slowpath_stop(struct qed_dev *cdev)
803 {
804 if (!cdev)
805 return -ENODEV;
806
807 qed_free_stream_mem(cdev);
808
809 qed_nic_stop(cdev);
810 qed_slowpath_irq_free(cdev);
811
812 qed_disable_msix(cdev);
813 qed_nic_reset(cdev);
814
815 release_firmware(cdev->firmware);
816
817 return 0;
818 }
819
820 static void qed_set_id(struct qed_dev *cdev, char name[NAME_SIZE],
821 char ver_str[VER_SIZE])
822 {
823 int i;
824
825 memcpy(cdev->name, name, NAME_SIZE);
826 for_each_hwfn(cdev, i)
827 snprintf(cdev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i);
828
829 memcpy(cdev->ver_str, ver_str, VER_SIZE);
830 cdev->drv_type = DRV_ID_DRV_TYPE_LINUX;
831 }
832
833 static u32 qed_sb_init(struct qed_dev *cdev,
834 struct qed_sb_info *sb_info,
835 void *sb_virt_addr,
836 dma_addr_t sb_phy_addr, u16 sb_id,
837 enum qed_sb_type type)
838 {
839 struct qed_hwfn *p_hwfn;
840 int hwfn_index;
841 u16 rel_sb_id;
842 u8 n_hwfns;
843 u32 rc;
844
845 /* RoCE uses single engine and CMT uses two engines. When using both
846 * we force only a single engine. Storage uses only engine 0 too.
847 */
848 if (type == QED_SB_TYPE_L2_QUEUE)
849 n_hwfns = cdev->num_hwfns;
850 else
851 n_hwfns = 1;
852
853 hwfn_index = sb_id % n_hwfns;
854 p_hwfn = &cdev->hwfns[hwfn_index];
855 rel_sb_id = sb_id / n_hwfns;
856
857 DP_VERBOSE(cdev, NETIF_MSG_INTR,
858 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
859 hwfn_index, rel_sb_id, sb_id);
860
861 rc = qed_int_sb_init(p_hwfn, p_hwfn->p_main_ptt, sb_info,
862 sb_virt_addr, sb_phy_addr, rel_sb_id);
863
864 return rc;
865 }
866
867 static u32 qed_sb_release(struct qed_dev *cdev,
868 struct qed_sb_info *sb_info,
869 u16 sb_id)
870 {
871 struct qed_hwfn *p_hwfn;
872 int hwfn_index;
873 u16 rel_sb_id;
874 u32 rc;
875
876 hwfn_index = sb_id % cdev->num_hwfns;
877 p_hwfn = &cdev->hwfns[hwfn_index];
878 rel_sb_id = sb_id / cdev->num_hwfns;
879
880 DP_VERBOSE(cdev, NETIF_MSG_INTR,
881 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
882 hwfn_index, rel_sb_id, sb_id);
883
884 rc = qed_int_sb_release(p_hwfn, sb_info, rel_sb_id);
885
886 return rc;
887 }
888
889 static int qed_set_link(struct qed_dev *cdev,
890 struct qed_link_params *params)
891 {
892 struct qed_hwfn *hwfn;
893 struct qed_mcp_link_params *link_params;
894 struct qed_ptt *ptt;
895 int rc;
896
897 if (!cdev)
898 return -ENODEV;
899
900 /* The link should be set only once per PF */
901 hwfn = &cdev->hwfns[0];
902
903 ptt = qed_ptt_acquire(hwfn);
904 if (!ptt)
905 return -EBUSY;
906
907 link_params = qed_mcp_get_link_params(hwfn);
908 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG)
909 link_params->speed.autoneg = params->autoneg;
910 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) {
911 link_params->speed.advertised_speeds = 0;
912 if ((params->adv_speeds & SUPPORTED_1000baseT_Half) ||
913 (params->adv_speeds & SUPPORTED_1000baseT_Full))
914 link_params->speed.advertised_speeds |=
915 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
916 if (params->adv_speeds & SUPPORTED_10000baseKR_Full)
917 link_params->speed.advertised_speeds |=
918 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
919 if (params->adv_speeds & SUPPORTED_40000baseLR4_Full)
920 link_params->speed.advertised_speeds |=
921 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G;
922 if (params->adv_speeds & 0)
923 link_params->speed.advertised_speeds |=
924 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G;
925 if (params->adv_speeds & 0)
926 link_params->speed.advertised_speeds |=
927 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_100G;
928 }
929 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_FORCED_SPEED)
930 link_params->speed.forced_speed = params->forced_speed;
931
932 rc = qed_mcp_set_link(hwfn, ptt, params->link_up);
933
934 qed_ptt_release(hwfn, ptt);
935
936 return rc;
937 }
938
939 static int qed_get_port_type(u32 media_type)
940 {
941 int port_type;
942
943 switch (media_type) {
944 case MEDIA_SFPP_10G_FIBER:
945 case MEDIA_SFP_1G_FIBER:
946 case MEDIA_XFP_FIBER:
947 case MEDIA_KR:
948 port_type = PORT_FIBRE;
949 break;
950 case MEDIA_DA_TWINAX:
951 port_type = PORT_DA;
952 break;
953 case MEDIA_BASE_T:
954 port_type = PORT_TP;
955 break;
956 case MEDIA_NOT_PRESENT:
957 port_type = PORT_NONE;
958 break;
959 case MEDIA_UNSPECIFIED:
960 default:
961 port_type = PORT_OTHER;
962 break;
963 }
964 return port_type;
965 }
966
967 static void qed_fill_link(struct qed_hwfn *hwfn,
968 struct qed_link_output *if_link)
969 {
970 struct qed_mcp_link_params params;
971 struct qed_mcp_link_state link;
972 struct qed_mcp_link_capabilities link_caps;
973 u32 media_type;
974
975 memset(if_link, 0, sizeof(*if_link));
976
977 /* Prepare source inputs */
978 memcpy(&params, qed_mcp_get_link_params(hwfn), sizeof(params));
979 memcpy(&link, qed_mcp_get_link_state(hwfn), sizeof(link));
980 memcpy(&link_caps, qed_mcp_get_link_capabilities(hwfn),
981 sizeof(link_caps));
982
983 /* Set the link parameters to pass to protocol driver */
984 if (link.link_up)
985 if_link->link_up = true;
986
987 /* TODO - at the moment assume supported and advertised speed equal */
988 if_link->supported_caps = SUPPORTED_FIBRE;
989 if (params.speed.autoneg)
990 if_link->supported_caps |= SUPPORTED_Autoneg;
991 if (params.pause.autoneg ||
992 (params.pause.forced_rx && params.pause.forced_tx))
993 if_link->supported_caps |= SUPPORTED_Asym_Pause;
994 if (params.pause.autoneg || params.pause.forced_rx ||
995 params.pause.forced_tx)
996 if_link->supported_caps |= SUPPORTED_Pause;
997
998 if_link->advertised_caps = if_link->supported_caps;
999 if (params.speed.advertised_speeds &
1000 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1001 if_link->advertised_caps |= SUPPORTED_1000baseT_Half |
1002 SUPPORTED_1000baseT_Full;
1003 if (params.speed.advertised_speeds &
1004 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1005 if_link->advertised_caps |= SUPPORTED_10000baseKR_Full;
1006 if (params.speed.advertised_speeds &
1007 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1008 if_link->advertised_caps |= SUPPORTED_40000baseLR4_Full;
1009 if (params.speed.advertised_speeds &
1010 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1011 if_link->advertised_caps |= 0;
1012 if (params.speed.advertised_speeds &
1013 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_100G)
1014 if_link->advertised_caps |= 0;
1015
1016 if (link_caps.speed_capabilities &
1017 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1018 if_link->supported_caps |= SUPPORTED_1000baseT_Half |
1019 SUPPORTED_1000baseT_Full;
1020 if (link_caps.speed_capabilities &
1021 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1022 if_link->supported_caps |= SUPPORTED_10000baseKR_Full;
1023 if (link_caps.speed_capabilities &
1024 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1025 if_link->supported_caps |= SUPPORTED_40000baseLR4_Full;
1026 if (link_caps.speed_capabilities &
1027 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1028 if_link->supported_caps |= 0;
1029 if (link_caps.speed_capabilities &
1030 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_100G)
1031 if_link->supported_caps |= 0;
1032
1033 if (link.link_up)
1034 if_link->speed = link.speed;
1035
1036 /* TODO - fill duplex properly */
1037 if_link->duplex = DUPLEX_FULL;
1038 qed_mcp_get_media_type(hwfn->cdev, &media_type);
1039 if_link->port = qed_get_port_type(media_type);
1040
1041 if_link->autoneg = params.speed.autoneg;
1042
1043 if (params.pause.autoneg)
1044 if_link->pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1045 if (params.pause.forced_rx)
1046 if_link->pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1047 if (params.pause.forced_tx)
1048 if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1049
1050 /* Link partner capabilities */
1051 if (link.partner_adv_speed &
1052 QED_LINK_PARTNER_SPEED_1G_HD)
1053 if_link->lp_caps |= SUPPORTED_1000baseT_Half;
1054 if (link.partner_adv_speed &
1055 QED_LINK_PARTNER_SPEED_1G_FD)
1056 if_link->lp_caps |= SUPPORTED_1000baseT_Full;
1057 if (link.partner_adv_speed &
1058 QED_LINK_PARTNER_SPEED_10G)
1059 if_link->lp_caps |= SUPPORTED_10000baseKR_Full;
1060 if (link.partner_adv_speed &
1061 QED_LINK_PARTNER_SPEED_40G)
1062 if_link->lp_caps |= SUPPORTED_40000baseLR4_Full;
1063 if (link.partner_adv_speed &
1064 QED_LINK_PARTNER_SPEED_50G)
1065 if_link->lp_caps |= 0;
1066 if (link.partner_adv_speed &
1067 QED_LINK_PARTNER_SPEED_100G)
1068 if_link->lp_caps |= 0;
1069
1070 if (link.an_complete)
1071 if_link->lp_caps |= SUPPORTED_Autoneg;
1072
1073 if (link.partner_adv_pause)
1074 if_link->lp_caps |= SUPPORTED_Pause;
1075 if (link.partner_adv_pause == QED_LINK_PARTNER_ASYMMETRIC_PAUSE ||
1076 link.partner_adv_pause == QED_LINK_PARTNER_BOTH_PAUSE)
1077 if_link->lp_caps |= SUPPORTED_Asym_Pause;
1078 }
1079
1080 static void qed_get_current_link(struct qed_dev *cdev,
1081 struct qed_link_output *if_link)
1082 {
1083 qed_fill_link(&cdev->hwfns[0], if_link);
1084 }
1085
1086 void qed_link_update(struct qed_hwfn *hwfn)
1087 {
1088 void *cookie = hwfn->cdev->ops_cookie;
1089 struct qed_common_cb_ops *op = hwfn->cdev->protocol_ops.common;
1090 struct qed_link_output if_link;
1091
1092 qed_fill_link(hwfn, &if_link);
1093
1094 if (IS_LEAD_HWFN(hwfn) && cookie)
1095 op->link_update(cookie, &if_link);
1096 }
1097
1098 static int qed_drain(struct qed_dev *cdev)
1099 {
1100 struct qed_hwfn *hwfn;
1101 struct qed_ptt *ptt;
1102 int i, rc;
1103
1104 for_each_hwfn(cdev, i) {
1105 hwfn = &cdev->hwfns[i];
1106 ptt = qed_ptt_acquire(hwfn);
1107 if (!ptt) {
1108 DP_NOTICE(hwfn, "Failed to drain NIG; No PTT\n");
1109 return -EBUSY;
1110 }
1111 rc = qed_mcp_drain(hwfn, ptt);
1112 if (rc)
1113 return rc;
1114 qed_ptt_release(hwfn, ptt);
1115 }
1116
1117 return 0;
1118 }
1119
1120 static int qed_set_led(struct qed_dev *cdev, enum qed_led_mode mode)
1121 {
1122 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
1123 struct qed_ptt *ptt;
1124 int status = 0;
1125
1126 ptt = qed_ptt_acquire(hwfn);
1127 if (!ptt)
1128 return -EAGAIN;
1129
1130 status = qed_mcp_set_led(hwfn, ptt, mode);
1131
1132 qed_ptt_release(hwfn, ptt);
1133
1134 return status;
1135 }
1136
1137 const struct qed_common_ops qed_common_ops_pass = {
1138 .probe = &qed_probe,
1139 .remove = &qed_remove,
1140 .set_power_state = &qed_set_power_state,
1141 .set_id = &qed_set_id,
1142 .update_pf_params = &qed_update_pf_params,
1143 .slowpath_start = &qed_slowpath_start,
1144 .slowpath_stop = &qed_slowpath_stop,
1145 .set_fp_int = &qed_set_int_fp,
1146 .get_fp_int = &qed_get_int_fp,
1147 .sb_init = &qed_sb_init,
1148 .sb_release = &qed_sb_release,
1149 .simd_handler_config = &qed_simd_handler_config,
1150 .simd_handler_clean = &qed_simd_handler_clean,
1151 .set_link = &qed_set_link,
1152 .get_link = &qed_get_current_link,
1153 .drain = &qed_drain,
1154 .update_msglvl = &qed_init_dp,
1155 .chain_alloc = &qed_chain_alloc,
1156 .chain_free = &qed_chain_free,
1157 .set_led = &qed_set_led,
1158 };
1159
1160 u32 qed_get_protocol_version(enum qed_protocol protocol)
1161 {
1162 switch (protocol) {
1163 case QED_PROTOCOL_ETH:
1164 return QED_ETH_INTERFACE_VERSION;
1165 default:
1166 return 0;
1167 }
1168 }
1169 EXPORT_SYMBOL(qed_get_protocol_version);