1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/stddef.h>
34 #include <linux/pci.h>
35 #include <linux/kernel.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
38 #include <asm/byteorder.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/string.h>
41 #include <linux/module.h>
42 #include <linux/interrupt.h>
43 #include <linux/workqueue.h>
44 #include <linux/ethtool.h>
45 #include <linux/etherdevice.h>
46 #include <linux/vmalloc.h>
47 #include <linux/crash_dump.h>
48 #include <linux/crc32.h>
49 #include <linux/qed/qed_if.h>
50 #include <linux/qed/qed_ll2_if.h>
53 #include "qed_sriov.h"
55 #include "qed_dev_api.h"
58 #include "qed_iscsi.h"
62 #include "qed_selftest.h"
63 #include "qed_debug.h"
65 #define QED_ROCE_QPS (8192)
66 #define QED_ROCE_DPIS (8)
67 #define QED_RDMA_SRQS QED_ROCE_QPS
69 static char version
[] =
70 "QLogic FastLinQ 4xxxx Core Module qed " DRV_MODULE_VERSION
"\n";
72 MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Core Module");
73 MODULE_LICENSE("GPL");
74 MODULE_VERSION(DRV_MODULE_VERSION
);
76 #define FW_FILE_VERSION \
77 __stringify(FW_MAJOR_VERSION) "." \
78 __stringify(FW_MINOR_VERSION) "." \
79 __stringify(FW_REVISION_VERSION) "." \
80 __stringify(FW_ENGINEERING_VERSION)
82 #define QED_FW_FILE_NAME \
83 "qed/qed_init_values_zipped-" FW_FILE_VERSION ".bin"
85 MODULE_FIRMWARE(QED_FW_FILE_NAME
);
87 static int __init
qed_init(void)
89 pr_info("%s", version
);
94 static void __exit
qed_cleanup(void)
96 pr_notice("qed_cleanup called\n");
99 module_init(qed_init
);
100 module_exit(qed_cleanup
);
102 /* Check if the DMA controller on the machine can properly handle the DMA
103 * addressing required by the device.
105 static int qed_set_coherency_mask(struct qed_dev
*cdev
)
107 struct device
*dev
= &cdev
->pdev
->dev
;
109 if (dma_set_mask(dev
, DMA_BIT_MASK(64)) == 0) {
110 if (dma_set_coherent_mask(dev
, DMA_BIT_MASK(64)) != 0) {
112 "Can't request 64-bit consistent allocations\n");
115 } else if (dma_set_mask(dev
, DMA_BIT_MASK(32)) != 0) {
116 DP_NOTICE(cdev
, "Can't request 64b/32b DMA addresses\n");
123 static void qed_free_pci(struct qed_dev
*cdev
)
125 struct pci_dev
*pdev
= cdev
->pdev
;
127 if (cdev
->doorbells
&& cdev
->db_size
)
128 iounmap(cdev
->doorbells
);
130 iounmap(cdev
->regview
);
131 if (atomic_read(&pdev
->enable_cnt
) == 1)
132 pci_release_regions(pdev
);
134 pci_disable_device(pdev
);
137 #define PCI_REVISION_ID_ERROR_VAL 0xff
139 /* Performs PCI initializations as well as initializing PCI-related parameters
140 * in the device structrue. Returns 0 in case of success.
142 static int qed_init_pci(struct qed_dev
*cdev
, struct pci_dev
*pdev
)
149 rc
= pci_enable_device(pdev
);
151 DP_NOTICE(cdev
, "Cannot enable PCI device\n");
155 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
156 DP_NOTICE(cdev
, "No memory region found in bar #0\n");
161 if (IS_PF(cdev
) && !(pci_resource_flags(pdev
, 2) & IORESOURCE_MEM
)) {
162 DP_NOTICE(cdev
, "No memory region found in bar #2\n");
167 if (atomic_read(&pdev
->enable_cnt
) == 1) {
168 rc
= pci_request_regions(pdev
, "qed");
171 "Failed to request PCI memory resources\n");
174 pci_set_master(pdev
);
175 pci_save_state(pdev
);
178 pci_read_config_byte(pdev
, PCI_REVISION_ID
, &rev_id
);
179 if (rev_id
== PCI_REVISION_ID_ERROR_VAL
) {
181 "Detected PCI device error [rev_id 0x%x]. Probably due to prior indication. Aborting.\n",
186 if (!pci_is_pcie(pdev
)) {
187 DP_NOTICE(cdev
, "The bus is not PCI Express\n");
192 cdev
->pci_params
.pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
193 if (IS_PF(cdev
) && !cdev
->pci_params
.pm_cap
)
194 DP_NOTICE(cdev
, "Cannot find power management capability\n");
196 rc
= qed_set_coherency_mask(cdev
);
200 cdev
->pci_params
.mem_start
= pci_resource_start(pdev
, 0);
201 cdev
->pci_params
.mem_end
= pci_resource_end(pdev
, 0);
202 cdev
->pci_params
.irq
= pdev
->irq
;
204 cdev
->regview
= pci_ioremap_bar(pdev
, 0);
205 if (!cdev
->regview
) {
206 DP_NOTICE(cdev
, "Cannot map register space, aborting\n");
211 cdev
->db_phys_addr
= pci_resource_start(cdev
->pdev
, 2);
212 cdev
->db_size
= pci_resource_len(cdev
->pdev
, 2);
213 if (!cdev
->db_size
) {
215 DP_NOTICE(cdev
, "No Doorbell bar available\n");
222 cdev
->doorbells
= ioremap_wc(cdev
->db_phys_addr
, cdev
->db_size
);
224 if (!cdev
->doorbells
) {
225 DP_NOTICE(cdev
, "Cannot map doorbell space\n");
232 pci_release_regions(pdev
);
234 pci_disable_device(pdev
);
239 int qed_fill_dev_info(struct qed_dev
*cdev
,
240 struct qed_dev_info
*dev_info
)
242 struct qed_hwfn
*p_hwfn
= QED_LEADING_HWFN(cdev
);
243 struct qed_hw_info
*hw_info
= &p_hwfn
->hw_info
;
244 struct qed_tunnel_info
*tun
= &cdev
->tunnel
;
247 memset(dev_info
, 0, sizeof(struct qed_dev_info
));
249 if (tun
->vxlan
.tun_cls
== QED_TUNN_CLSS_MAC_VLAN
&&
250 tun
->vxlan
.b_mode_enabled
)
251 dev_info
->vxlan_enable
= true;
253 if (tun
->l2_gre
.b_mode_enabled
&& tun
->ip_gre
.b_mode_enabled
&&
254 tun
->l2_gre
.tun_cls
== QED_TUNN_CLSS_MAC_VLAN
&&
255 tun
->ip_gre
.tun_cls
== QED_TUNN_CLSS_MAC_VLAN
)
256 dev_info
->gre_enable
= true;
258 if (tun
->l2_geneve
.b_mode_enabled
&& tun
->ip_geneve
.b_mode_enabled
&&
259 tun
->l2_geneve
.tun_cls
== QED_TUNN_CLSS_MAC_VLAN
&&
260 tun
->ip_geneve
.tun_cls
== QED_TUNN_CLSS_MAC_VLAN
)
261 dev_info
->geneve_enable
= true;
263 dev_info
->num_hwfns
= cdev
->num_hwfns
;
264 dev_info
->pci_mem_start
= cdev
->pci_params
.mem_start
;
265 dev_info
->pci_mem_end
= cdev
->pci_params
.mem_end
;
266 dev_info
->pci_irq
= cdev
->pci_params
.irq
;
267 dev_info
->rdma_supported
= QED_IS_RDMA_PERSONALITY(p_hwfn
);
268 dev_info
->dev_type
= cdev
->type
;
269 ether_addr_copy(dev_info
->hw_mac
, hw_info
->hw_mac_addr
);
272 dev_info
->fw_major
= FW_MAJOR_VERSION
;
273 dev_info
->fw_minor
= FW_MINOR_VERSION
;
274 dev_info
->fw_rev
= FW_REVISION_VERSION
;
275 dev_info
->fw_eng
= FW_ENGINEERING_VERSION
;
276 dev_info
->b_inter_pf_switch
= test_bit(QED_MF_INTER_PF_SWITCH
,
278 dev_info
->tx_switching
= true;
280 if (hw_info
->b_wol_support
== QED_WOL_SUPPORT_PME
)
281 dev_info
->wol_support
= true;
283 dev_info
->abs_pf_id
= QED_LEADING_HWFN(cdev
)->abs_pf_id
;
285 qed_vf_get_fw_version(&cdev
->hwfns
[0], &dev_info
->fw_major
,
286 &dev_info
->fw_minor
, &dev_info
->fw_rev
,
291 ptt
= qed_ptt_acquire(QED_LEADING_HWFN(cdev
));
293 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev
), ptt
,
294 &dev_info
->mfw_rev
, NULL
);
296 qed_mcp_get_mbi_ver(QED_LEADING_HWFN(cdev
), ptt
,
297 &dev_info
->mbi_version
);
299 qed_mcp_get_flash_size(QED_LEADING_HWFN(cdev
), ptt
,
300 &dev_info
->flash_size
);
302 qed_ptt_release(QED_LEADING_HWFN(cdev
), ptt
);
305 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev
), NULL
,
306 &dev_info
->mfw_rev
, NULL
);
309 dev_info
->mtu
= hw_info
->mtu
;
314 static void qed_free_cdev(struct qed_dev
*cdev
)
319 static struct qed_dev
*qed_alloc_cdev(struct pci_dev
*pdev
)
321 struct qed_dev
*cdev
;
323 cdev
= kzalloc(sizeof(*cdev
), GFP_KERNEL
);
327 qed_init_struct(cdev
);
332 /* Sets the requested power state */
333 static int qed_set_power_state(struct qed_dev
*cdev
, pci_power_t state
)
338 DP_VERBOSE(cdev
, NETIF_MSG_DRV
, "Omitting Power state change\n");
343 static struct qed_dev
*qed_probe(struct pci_dev
*pdev
,
344 struct qed_probe_params
*params
)
346 struct qed_dev
*cdev
;
349 cdev
= qed_alloc_cdev(pdev
);
353 cdev
->drv_type
= DRV_ID_DRV_TYPE_LINUX
;
354 cdev
->protocol
= params
->protocol
;
357 cdev
->b_is_vf
= true;
359 qed_init_dp(cdev
, params
->dp_module
, params
->dp_level
);
361 rc
= qed_init_pci(cdev
, pdev
);
363 DP_ERR(cdev
, "init pci failed\n");
366 DP_INFO(cdev
, "PCI init completed successfully\n");
368 rc
= qed_hw_prepare(cdev
, QED_PCI_DEFAULT
);
370 DP_ERR(cdev
, "hw prepare failed\n");
374 DP_INFO(cdev
, "qed_probe completed successffuly\n");
386 static void qed_remove(struct qed_dev
*cdev
)
395 qed_set_power_state(cdev
, PCI_D3hot
);
400 static void qed_disable_msix(struct qed_dev
*cdev
)
402 if (cdev
->int_params
.out
.int_mode
== QED_INT_MODE_MSIX
) {
403 pci_disable_msix(cdev
->pdev
);
404 kfree(cdev
->int_params
.msix_table
);
405 } else if (cdev
->int_params
.out
.int_mode
== QED_INT_MODE_MSI
) {
406 pci_disable_msi(cdev
->pdev
);
409 memset(&cdev
->int_params
.out
, 0, sizeof(struct qed_int_param
));
412 static int qed_enable_msix(struct qed_dev
*cdev
,
413 struct qed_int_params
*int_params
)
417 cnt
= int_params
->in
.num_vectors
;
419 for (i
= 0; i
< cnt
; i
++)
420 int_params
->msix_table
[i
].entry
= i
;
422 rc
= pci_enable_msix_range(cdev
->pdev
, int_params
->msix_table
,
423 int_params
->in
.min_msix_cnt
, cnt
);
424 if (rc
< cnt
&& rc
>= int_params
->in
.min_msix_cnt
&&
425 (rc
% cdev
->num_hwfns
)) {
426 pci_disable_msix(cdev
->pdev
);
428 /* If fastpath is initialized, we need at least one interrupt
429 * per hwfn [and the slow path interrupts]. New requested number
430 * should be a multiple of the number of hwfns.
432 cnt
= (rc
/ cdev
->num_hwfns
) * cdev
->num_hwfns
;
434 "Trying to enable MSI-X with less vectors (%d out of %d)\n",
435 cnt
, int_params
->in
.num_vectors
);
436 rc
= pci_enable_msix_exact(cdev
->pdev
, int_params
->msix_table
,
443 /* MSI-x configuration was achieved */
444 int_params
->out
.int_mode
= QED_INT_MODE_MSIX
;
445 int_params
->out
.num_vectors
= rc
;
449 "Failed to enable MSI-X [Requested %d vectors][rc %d]\n",
456 /* This function outputs the int mode and the number of enabled msix vector */
457 static int qed_set_int_mode(struct qed_dev
*cdev
, bool force_mode
)
459 struct qed_int_params
*int_params
= &cdev
->int_params
;
460 struct msix_entry
*tbl
;
463 switch (int_params
->in
.int_mode
) {
464 case QED_INT_MODE_MSIX
:
465 /* Allocate MSIX table */
466 cnt
= int_params
->in
.num_vectors
;
467 int_params
->msix_table
= kcalloc(cnt
, sizeof(*tbl
), GFP_KERNEL
);
468 if (!int_params
->msix_table
) {
474 rc
= qed_enable_msix(cdev
, int_params
);
478 DP_NOTICE(cdev
, "Failed to enable MSI-X\n");
479 kfree(int_params
->msix_table
);
484 case QED_INT_MODE_MSI
:
485 if (cdev
->num_hwfns
== 1) {
486 rc
= pci_enable_msi(cdev
->pdev
);
488 int_params
->out
.int_mode
= QED_INT_MODE_MSI
;
492 DP_NOTICE(cdev
, "Failed to enable MSI\n");
498 case QED_INT_MODE_INTA
:
499 int_params
->out
.int_mode
= QED_INT_MODE_INTA
;
503 DP_NOTICE(cdev
, "Unknown int_mode value %d\n",
504 int_params
->in
.int_mode
);
510 DP_INFO(cdev
, "Using %s interrupts\n",
511 int_params
->out
.int_mode
== QED_INT_MODE_INTA
?
512 "INTa" : int_params
->out
.int_mode
== QED_INT_MODE_MSI
?
514 cdev
->int_coalescing_mode
= QED_COAL_MODE_ENABLE
;
519 static void qed_simd_handler_config(struct qed_dev
*cdev
, void *token
,
520 int index
, void(*handler
)(void *))
522 struct qed_hwfn
*hwfn
= &cdev
->hwfns
[index
% cdev
->num_hwfns
];
523 int relative_idx
= index
/ cdev
->num_hwfns
;
525 hwfn
->simd_proto_handler
[relative_idx
].func
= handler
;
526 hwfn
->simd_proto_handler
[relative_idx
].token
= token
;
529 static void qed_simd_handler_clean(struct qed_dev
*cdev
, int index
)
531 struct qed_hwfn
*hwfn
= &cdev
->hwfns
[index
% cdev
->num_hwfns
];
532 int relative_idx
= index
/ cdev
->num_hwfns
;
534 memset(&hwfn
->simd_proto_handler
[relative_idx
], 0,
535 sizeof(struct qed_simd_fp_handler
));
538 static irqreturn_t
qed_msix_sp_int(int irq
, void *tasklet
)
540 tasklet_schedule((struct tasklet_struct
*)tasklet
);
544 static irqreturn_t
qed_single_int(int irq
, void *dev_instance
)
546 struct qed_dev
*cdev
= (struct qed_dev
*)dev_instance
;
547 struct qed_hwfn
*hwfn
;
548 irqreturn_t rc
= IRQ_NONE
;
552 for (i
= 0; i
< cdev
->num_hwfns
; i
++) {
553 status
= qed_int_igu_read_sisr_reg(&cdev
->hwfns
[i
]);
558 hwfn
= &cdev
->hwfns
[i
];
560 /* Slowpath interrupt */
561 if (unlikely(status
& 0x1)) {
562 tasklet_schedule(hwfn
->sp_dpc
);
567 /* Fastpath interrupts */
568 for (j
= 0; j
< 64; j
++) {
569 if ((0x2ULL
<< j
) & status
) {
570 struct qed_simd_fp_handler
*p_handler
=
571 &hwfn
->simd_proto_handler
[j
];
574 p_handler
->func(p_handler
->token
);
577 "Not calling fastpath handler as it is NULL [handler #%d, status 0x%llx]\n",
580 status
&= ~(0x2ULL
<< j
);
585 if (unlikely(status
))
586 DP_VERBOSE(hwfn
, NETIF_MSG_INTR
,
587 "got an unknown interrupt status 0x%llx\n",
594 int qed_slowpath_irq_req(struct qed_hwfn
*hwfn
)
596 struct qed_dev
*cdev
= hwfn
->cdev
;
601 int_mode
= cdev
->int_params
.out
.int_mode
;
602 if (int_mode
== QED_INT_MODE_MSIX
) {
604 snprintf(hwfn
->name
, NAME_SIZE
, "sp-%d-%02x:%02x.%02x",
605 id
, cdev
->pdev
->bus
->number
,
606 PCI_SLOT(cdev
->pdev
->devfn
), hwfn
->abs_pf_id
);
607 rc
= request_irq(cdev
->int_params
.msix_table
[id
].vector
,
608 qed_msix_sp_int
, 0, hwfn
->name
, hwfn
->sp_dpc
);
610 unsigned long flags
= 0;
612 snprintf(cdev
->name
, NAME_SIZE
, "%02x:%02x.%02x",
613 cdev
->pdev
->bus
->number
, PCI_SLOT(cdev
->pdev
->devfn
),
614 PCI_FUNC(cdev
->pdev
->devfn
));
616 if (cdev
->int_params
.out
.int_mode
== QED_INT_MODE_INTA
)
617 flags
|= IRQF_SHARED
;
619 rc
= request_irq(cdev
->pdev
->irq
, qed_single_int
,
620 flags
, cdev
->name
, cdev
);
624 DP_NOTICE(cdev
, "request_irq failed, rc = %d\n", rc
);
626 DP_VERBOSE(hwfn
, (NETIF_MSG_INTR
| QED_MSG_SP
),
627 "Requested slowpath %s\n",
628 (int_mode
== QED_INT_MODE_MSIX
) ? "MSI-X" : "IRQ");
633 static void qed_slowpath_tasklet_flush(struct qed_hwfn
*p_hwfn
)
635 /* Calling the disable function will make sure that any
636 * currently-running function is completed. The following call to the
637 * enable function makes this sequence a flush-like operation.
639 if (p_hwfn
->b_sp_dpc_enabled
) {
640 tasklet_disable(p_hwfn
->sp_dpc
);
641 tasklet_enable(p_hwfn
->sp_dpc
);
645 void qed_slowpath_irq_sync(struct qed_hwfn
*p_hwfn
)
647 struct qed_dev
*cdev
= p_hwfn
->cdev
;
648 u8 id
= p_hwfn
->my_id
;
651 int_mode
= cdev
->int_params
.out
.int_mode
;
652 if (int_mode
== QED_INT_MODE_MSIX
)
653 synchronize_irq(cdev
->int_params
.msix_table
[id
].vector
);
655 synchronize_irq(cdev
->pdev
->irq
);
657 qed_slowpath_tasklet_flush(p_hwfn
);
660 static void qed_slowpath_irq_free(struct qed_dev
*cdev
)
664 if (cdev
->int_params
.out
.int_mode
== QED_INT_MODE_MSIX
) {
665 for_each_hwfn(cdev
, i
) {
666 if (!cdev
->hwfns
[i
].b_int_requested
)
668 synchronize_irq(cdev
->int_params
.msix_table
[i
].vector
);
669 free_irq(cdev
->int_params
.msix_table
[i
].vector
,
670 cdev
->hwfns
[i
].sp_dpc
);
673 if (QED_LEADING_HWFN(cdev
)->b_int_requested
)
674 free_irq(cdev
->pdev
->irq
, cdev
);
676 qed_int_disable_post_isr_release(cdev
);
679 static int qed_nic_stop(struct qed_dev
*cdev
)
683 rc
= qed_hw_stop(cdev
);
685 for (i
= 0; i
< cdev
->num_hwfns
; i
++) {
686 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
688 if (p_hwfn
->b_sp_dpc_enabled
) {
689 tasklet_disable(p_hwfn
->sp_dpc
);
690 p_hwfn
->b_sp_dpc_enabled
= false;
691 DP_VERBOSE(cdev
, NETIF_MSG_IFDOWN
,
692 "Disabled sp tasklet [hwfn %d] at %p\n",
697 qed_dbg_pf_exit(cdev
);
702 static int qed_nic_setup(struct qed_dev
*cdev
)
706 /* Determine if interface is going to require LL2 */
707 if (QED_LEADING_HWFN(cdev
)->hw_info
.personality
!= QED_PCI_ETH
) {
708 for (i
= 0; i
< cdev
->num_hwfns
; i
++) {
709 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
711 p_hwfn
->using_ll2
= true;
715 rc
= qed_resc_alloc(cdev
);
719 DP_INFO(cdev
, "Allocated qed resources\n");
721 qed_resc_setup(cdev
);
726 static int qed_set_int_fp(struct qed_dev
*cdev
, u16 cnt
)
730 /* Mark the fastpath as free/used */
731 cdev
->int_params
.fp_initialized
= cnt
? true : false;
733 if (cdev
->int_params
.out
.int_mode
!= QED_INT_MODE_MSIX
)
734 limit
= cdev
->num_hwfns
* 63;
735 else if (cdev
->int_params
.fp_msix_cnt
)
736 limit
= cdev
->int_params
.fp_msix_cnt
;
741 return min_t(int, cnt
, limit
);
744 static int qed_get_int_fp(struct qed_dev
*cdev
, struct qed_int_info
*info
)
746 memset(info
, 0, sizeof(struct qed_int_info
));
748 if (!cdev
->int_params
.fp_initialized
) {
750 "Protocol driver requested interrupt information, but its support is not yet configured\n");
754 /* Need to expose only MSI-X information; Single IRQ is handled solely
757 if (cdev
->int_params
.out
.int_mode
== QED_INT_MODE_MSIX
) {
758 int msix_base
= cdev
->int_params
.fp_msix_base
;
760 info
->msix_cnt
= cdev
->int_params
.fp_msix_cnt
;
761 info
->msix
= &cdev
->int_params
.msix_table
[msix_base
];
767 static int qed_slowpath_setup_int(struct qed_dev
*cdev
,
768 enum qed_int_mode int_mode
)
770 struct qed_sb_cnt_info sb_cnt_info
;
771 int num_l2_queues
= 0;
775 if ((int_mode
== QED_INT_MODE_MSI
) && (cdev
->num_hwfns
> 1)) {
776 DP_NOTICE(cdev
, "MSI mode is not supported for CMT devices\n");
780 memset(&cdev
->int_params
, 0, sizeof(struct qed_int_params
));
781 cdev
->int_params
.in
.int_mode
= int_mode
;
782 for_each_hwfn(cdev
, i
) {
783 memset(&sb_cnt_info
, 0, sizeof(sb_cnt_info
));
784 qed_int_get_num_sbs(&cdev
->hwfns
[i
], &sb_cnt_info
);
785 cdev
->int_params
.in
.num_vectors
+= sb_cnt_info
.cnt
;
786 cdev
->int_params
.in
.num_vectors
++; /* slowpath */
789 /* We want a minimum of one slowpath and one fastpath vector per hwfn */
790 cdev
->int_params
.in
.min_msix_cnt
= cdev
->num_hwfns
* 2;
792 if (is_kdump_kernel()) {
794 "Kdump kernel: Limit the max number of requested MSI-X vectors to %hd\n",
795 cdev
->int_params
.in
.min_msix_cnt
);
796 cdev
->int_params
.in
.num_vectors
=
797 cdev
->int_params
.in
.min_msix_cnt
;
800 rc
= qed_set_int_mode(cdev
, false);
802 DP_ERR(cdev
, "qed_slowpath_setup_int ERR\n");
806 cdev
->int_params
.fp_msix_base
= cdev
->num_hwfns
;
807 cdev
->int_params
.fp_msix_cnt
= cdev
->int_params
.out
.num_vectors
-
810 if (!IS_ENABLED(CONFIG_QED_RDMA
) ||
811 !QED_IS_RDMA_PERSONALITY(QED_LEADING_HWFN(cdev
)))
814 for_each_hwfn(cdev
, i
)
815 num_l2_queues
+= FEAT_NUM(&cdev
->hwfns
[i
], QED_PF_L2_QUE
);
817 DP_VERBOSE(cdev
, QED_MSG_RDMA
,
818 "cdev->int_params.fp_msix_cnt=%d num_l2_queues=%d\n",
819 cdev
->int_params
.fp_msix_cnt
, num_l2_queues
);
821 if (cdev
->int_params
.fp_msix_cnt
> num_l2_queues
) {
822 cdev
->int_params
.rdma_msix_cnt
=
823 (cdev
->int_params
.fp_msix_cnt
- num_l2_queues
)
825 cdev
->int_params
.rdma_msix_base
=
826 cdev
->int_params
.fp_msix_base
+ num_l2_queues
;
827 cdev
->int_params
.fp_msix_cnt
= num_l2_queues
;
829 cdev
->int_params
.rdma_msix_cnt
= 0;
832 DP_VERBOSE(cdev
, QED_MSG_RDMA
, "roce_msix_cnt=%d roce_msix_base=%d\n",
833 cdev
->int_params
.rdma_msix_cnt
,
834 cdev
->int_params
.rdma_msix_base
);
839 static int qed_slowpath_vf_setup_int(struct qed_dev
*cdev
)
843 memset(&cdev
->int_params
, 0, sizeof(struct qed_int_params
));
844 cdev
->int_params
.in
.int_mode
= QED_INT_MODE_MSIX
;
846 qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev
),
847 &cdev
->int_params
.in
.num_vectors
);
848 if (cdev
->num_hwfns
> 1) {
851 qed_vf_get_num_rxqs(&cdev
->hwfns
[1], &vectors
);
852 cdev
->int_params
.in
.num_vectors
+= vectors
;
855 /* We want a minimum of one fastpath vector per vf hwfn */
856 cdev
->int_params
.in
.min_msix_cnt
= cdev
->num_hwfns
;
858 rc
= qed_set_int_mode(cdev
, true);
862 cdev
->int_params
.fp_msix_base
= 0;
863 cdev
->int_params
.fp_msix_cnt
= cdev
->int_params
.out
.num_vectors
;
868 u32
qed_unzip_data(struct qed_hwfn
*p_hwfn
, u32 input_len
,
869 u8
*input_buf
, u32 max_size
, u8
*unzip_buf
)
873 p_hwfn
->stream
->next_in
= input_buf
;
874 p_hwfn
->stream
->avail_in
= input_len
;
875 p_hwfn
->stream
->next_out
= unzip_buf
;
876 p_hwfn
->stream
->avail_out
= max_size
;
878 rc
= zlib_inflateInit2(p_hwfn
->stream
, MAX_WBITS
);
881 DP_VERBOSE(p_hwfn
, NETIF_MSG_DRV
, "zlib init failed, rc = %d\n",
886 rc
= zlib_inflate(p_hwfn
->stream
, Z_FINISH
);
887 zlib_inflateEnd(p_hwfn
->stream
);
889 if (rc
!= Z_OK
&& rc
!= Z_STREAM_END
) {
890 DP_VERBOSE(p_hwfn
, NETIF_MSG_DRV
, "FW unzip error: %s, rc=%d\n",
891 p_hwfn
->stream
->msg
, rc
);
895 return p_hwfn
->stream
->total_out
/ 4;
898 static int qed_alloc_stream_mem(struct qed_dev
*cdev
)
903 for_each_hwfn(cdev
, i
) {
904 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
906 p_hwfn
->stream
= kzalloc(sizeof(*p_hwfn
->stream
), GFP_KERNEL
);
910 workspace
= vzalloc(zlib_inflate_workspacesize());
913 p_hwfn
->stream
->workspace
= workspace
;
919 static void qed_free_stream_mem(struct qed_dev
*cdev
)
923 for_each_hwfn(cdev
, i
) {
924 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
929 vfree(p_hwfn
->stream
->workspace
);
930 kfree(p_hwfn
->stream
);
934 static void qed_update_pf_params(struct qed_dev
*cdev
,
935 struct qed_pf_params
*params
)
939 if (IS_ENABLED(CONFIG_QED_RDMA
)) {
940 params
->rdma_pf_params
.num_qps
= QED_ROCE_QPS
;
941 params
->rdma_pf_params
.min_dpis
= QED_ROCE_DPIS
;
942 params
->rdma_pf_params
.num_srqs
= QED_RDMA_SRQS
;
943 /* divide by 3 the MRs to avoid MF ILT overflow */
944 params
->rdma_pf_params
.gl_pi
= QED_ROCE_PROTOCOL_INDEX
;
947 if (cdev
->num_hwfns
> 1 || IS_VF(cdev
))
948 params
->eth_pf_params
.num_arfs_filters
= 0;
950 /* In case we might support RDMA, don't allow qede to be greedy
951 * with the L2 contexts. Allow for 64 queues [rx, tx, xdp] per hwfn.
953 if (QED_IS_RDMA_PERSONALITY(QED_LEADING_HWFN(cdev
))) {
956 num_cons
= ¶ms
->eth_pf_params
.num_cons
;
957 *num_cons
= min_t(u16
, *num_cons
, 192);
960 for (i
= 0; i
< cdev
->num_hwfns
; i
++) {
961 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
963 p_hwfn
->pf_params
= *params
;
967 static void qed_slowpath_wq_stop(struct qed_dev
*cdev
)
974 for_each_hwfn(cdev
, i
) {
975 if (!cdev
->hwfns
[i
].slowpath_wq
)
978 flush_workqueue(cdev
->hwfns
[i
].slowpath_wq
);
979 destroy_workqueue(cdev
->hwfns
[i
].slowpath_wq
);
983 static void qed_slowpath_task(struct work_struct
*work
)
985 struct qed_hwfn
*hwfn
= container_of(work
, struct qed_hwfn
,
987 struct qed_ptt
*ptt
= qed_ptt_acquire(hwfn
);
990 queue_delayed_work(hwfn
->slowpath_wq
, &hwfn
->slowpath_task
, 0);
994 if (test_and_clear_bit(QED_SLOWPATH_MFW_TLV_REQ
,
995 &hwfn
->slowpath_task_flags
))
996 qed_mfw_process_tlv_req(hwfn
, ptt
);
998 qed_ptt_release(hwfn
, ptt
);
1001 static int qed_slowpath_wq_start(struct qed_dev
*cdev
)
1003 struct qed_hwfn
*hwfn
;
1004 char name
[NAME_SIZE
];
1010 for_each_hwfn(cdev
, i
) {
1011 hwfn
= &cdev
->hwfns
[i
];
1013 snprintf(name
, NAME_SIZE
, "slowpath-%02x:%02x.%02x",
1014 cdev
->pdev
->bus
->number
,
1015 PCI_SLOT(cdev
->pdev
->devfn
), hwfn
->abs_pf_id
);
1017 hwfn
->slowpath_wq
= alloc_workqueue(name
, 0, 0);
1018 if (!hwfn
->slowpath_wq
) {
1019 DP_NOTICE(hwfn
, "Cannot create slowpath workqueue\n");
1023 INIT_DELAYED_WORK(&hwfn
->slowpath_task
, qed_slowpath_task
);
1029 static int qed_slowpath_start(struct qed_dev
*cdev
,
1030 struct qed_slowpath_params
*params
)
1032 struct qed_drv_load_params drv_load_params
;
1033 struct qed_hw_init_params hw_init_params
;
1034 struct qed_mcp_drv_version drv_version
;
1035 struct qed_tunnel_info tunn_info
;
1036 const u8
*data
= NULL
;
1037 struct qed_hwfn
*hwfn
;
1038 struct qed_ptt
*p_ptt
;
1041 if (qed_iov_wq_start(cdev
))
1044 if (qed_slowpath_wq_start(cdev
))
1048 rc
= request_firmware(&cdev
->firmware
, QED_FW_FILE_NAME
,
1052 "Failed to find fw file - /lib/firmware/%s\n",
1057 if (cdev
->num_hwfns
== 1) {
1058 p_ptt
= qed_ptt_acquire(QED_LEADING_HWFN(cdev
));
1060 QED_LEADING_HWFN(cdev
)->p_arfs_ptt
= p_ptt
;
1063 "Failed to acquire PTT for aRFS\n");
1069 cdev
->rx_coalesce_usecs
= QED_DEFAULT_RX_USECS
;
1070 rc
= qed_nic_setup(cdev
);
1075 rc
= qed_slowpath_setup_int(cdev
, params
->int_mode
);
1077 rc
= qed_slowpath_vf_setup_int(cdev
);
1082 /* Allocate stream for unzipping */
1083 rc
= qed_alloc_stream_mem(cdev
);
1087 /* First Dword used to differentiate between various sources */
1088 data
= cdev
->firmware
->data
+ sizeof(u32
);
1090 qed_dbg_pf_init(cdev
);
1093 /* Start the slowpath */
1094 memset(&hw_init_params
, 0, sizeof(hw_init_params
));
1095 memset(&tunn_info
, 0, sizeof(tunn_info
));
1096 tunn_info
.vxlan
.b_mode_enabled
= true;
1097 tunn_info
.l2_gre
.b_mode_enabled
= true;
1098 tunn_info
.ip_gre
.b_mode_enabled
= true;
1099 tunn_info
.l2_geneve
.b_mode_enabled
= true;
1100 tunn_info
.ip_geneve
.b_mode_enabled
= true;
1101 tunn_info
.vxlan
.tun_cls
= QED_TUNN_CLSS_MAC_VLAN
;
1102 tunn_info
.l2_gre
.tun_cls
= QED_TUNN_CLSS_MAC_VLAN
;
1103 tunn_info
.ip_gre
.tun_cls
= QED_TUNN_CLSS_MAC_VLAN
;
1104 tunn_info
.l2_geneve
.tun_cls
= QED_TUNN_CLSS_MAC_VLAN
;
1105 tunn_info
.ip_geneve
.tun_cls
= QED_TUNN_CLSS_MAC_VLAN
;
1106 hw_init_params
.p_tunn
= &tunn_info
;
1107 hw_init_params
.b_hw_start
= true;
1108 hw_init_params
.int_mode
= cdev
->int_params
.out
.int_mode
;
1109 hw_init_params
.allow_npar_tx_switch
= true;
1110 hw_init_params
.bin_fw_data
= data
;
1112 memset(&drv_load_params
, 0, sizeof(drv_load_params
));
1113 drv_load_params
.is_crash_kernel
= is_kdump_kernel();
1114 drv_load_params
.mfw_timeout_val
= QED_LOAD_REQ_LOCK_TO_DEFAULT
;
1115 drv_load_params
.avoid_eng_reset
= false;
1116 drv_load_params
.override_force_load
= QED_OVERRIDE_FORCE_LOAD_NONE
;
1117 hw_init_params
.p_drv_load_params
= &drv_load_params
;
1119 rc
= qed_hw_init(cdev
, &hw_init_params
);
1124 "HW initialization and function start completed successfully\n");
1127 cdev
->tunn_feature_mask
= (BIT(QED_MODE_VXLAN_TUNN
) |
1128 BIT(QED_MODE_L2GENEVE_TUNN
) |
1129 BIT(QED_MODE_IPGENEVE_TUNN
) |
1130 BIT(QED_MODE_L2GRE_TUNN
) |
1131 BIT(QED_MODE_IPGRE_TUNN
));
1134 /* Allocate LL2 interface if needed */
1135 if (QED_LEADING_HWFN(cdev
)->using_ll2
) {
1136 rc
= qed_ll2_alloc_if(cdev
);
1141 hwfn
= QED_LEADING_HWFN(cdev
);
1142 drv_version
.version
= (params
->drv_major
<< 24) |
1143 (params
->drv_minor
<< 16) |
1144 (params
->drv_rev
<< 8) |
1146 strlcpy(drv_version
.name
, params
->name
,
1147 MCP_DRV_VER_STR_SIZE
- 4);
1148 rc
= qed_mcp_send_drv_version(hwfn
, hwfn
->p_main_ptt
,
1151 DP_NOTICE(cdev
, "Failed sending drv version command\n");
1156 qed_reset_vport_stats(cdev
);
1163 qed_hw_timers_stop_all(cdev
);
1165 qed_slowpath_irq_free(cdev
);
1166 qed_free_stream_mem(cdev
);
1167 qed_disable_msix(cdev
);
1169 qed_resc_free(cdev
);
1172 release_firmware(cdev
->firmware
);
1174 if (IS_PF(cdev
) && (cdev
->num_hwfns
== 1) &&
1175 QED_LEADING_HWFN(cdev
)->p_arfs_ptt
)
1176 qed_ptt_release(QED_LEADING_HWFN(cdev
),
1177 QED_LEADING_HWFN(cdev
)->p_arfs_ptt
);
1179 qed_iov_wq_stop(cdev
, false);
1181 qed_slowpath_wq_stop(cdev
);
1186 static int qed_slowpath_stop(struct qed_dev
*cdev
)
1191 qed_slowpath_wq_stop(cdev
);
1193 qed_ll2_dealloc_if(cdev
);
1196 if (cdev
->num_hwfns
== 1)
1197 qed_ptt_release(QED_LEADING_HWFN(cdev
),
1198 QED_LEADING_HWFN(cdev
)->p_arfs_ptt
);
1199 qed_free_stream_mem(cdev
);
1200 if (IS_QED_ETH_IF(cdev
))
1201 qed_sriov_disable(cdev
, true);
1207 qed_slowpath_irq_free(cdev
);
1209 qed_disable_msix(cdev
);
1211 qed_resc_free(cdev
);
1213 qed_iov_wq_stop(cdev
, true);
1216 release_firmware(cdev
->firmware
);
1221 static void qed_set_name(struct qed_dev
*cdev
, char name
[NAME_SIZE
])
1225 memcpy(cdev
->name
, name
, NAME_SIZE
);
1226 for_each_hwfn(cdev
, i
)
1227 snprintf(cdev
->hwfns
[i
].name
, NAME_SIZE
, "%s-%d", name
, i
);
1230 static u32
qed_sb_init(struct qed_dev
*cdev
,
1231 struct qed_sb_info
*sb_info
,
1233 dma_addr_t sb_phy_addr
, u16 sb_id
,
1234 enum qed_sb_type type
)
1236 struct qed_hwfn
*p_hwfn
;
1237 struct qed_ptt
*p_ptt
;
1243 /* RoCE uses single engine and CMT uses two engines. When using both
1244 * we force only a single engine. Storage uses only engine 0 too.
1246 if (type
== QED_SB_TYPE_L2_QUEUE
)
1247 n_hwfns
= cdev
->num_hwfns
;
1251 hwfn_index
= sb_id
% n_hwfns
;
1252 p_hwfn
= &cdev
->hwfns
[hwfn_index
];
1253 rel_sb_id
= sb_id
/ n_hwfns
;
1255 DP_VERBOSE(cdev
, NETIF_MSG_INTR
,
1256 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
1257 hwfn_index
, rel_sb_id
, sb_id
);
1259 if (IS_PF(p_hwfn
->cdev
)) {
1260 p_ptt
= qed_ptt_acquire(p_hwfn
);
1264 rc
= qed_int_sb_init(p_hwfn
, p_ptt
, sb_info
, sb_virt_addr
,
1265 sb_phy_addr
, rel_sb_id
);
1266 qed_ptt_release(p_hwfn
, p_ptt
);
1268 rc
= qed_int_sb_init(p_hwfn
, NULL
, sb_info
, sb_virt_addr
,
1269 sb_phy_addr
, rel_sb_id
);
1275 static u32
qed_sb_release(struct qed_dev
*cdev
,
1276 struct qed_sb_info
*sb_info
, u16 sb_id
)
1278 struct qed_hwfn
*p_hwfn
;
1283 hwfn_index
= sb_id
% cdev
->num_hwfns
;
1284 p_hwfn
= &cdev
->hwfns
[hwfn_index
];
1285 rel_sb_id
= sb_id
/ cdev
->num_hwfns
;
1287 DP_VERBOSE(cdev
, NETIF_MSG_INTR
,
1288 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
1289 hwfn_index
, rel_sb_id
, sb_id
);
1291 rc
= qed_int_sb_release(p_hwfn
, sb_info
, rel_sb_id
);
1296 static bool qed_can_link_change(struct qed_dev
*cdev
)
1301 static int qed_set_link(struct qed_dev
*cdev
, struct qed_link_params
*params
)
1303 struct qed_hwfn
*hwfn
;
1304 struct qed_mcp_link_params
*link_params
;
1305 struct qed_ptt
*ptt
;
1311 /* The link should be set only once per PF */
1312 hwfn
= &cdev
->hwfns
[0];
1314 /* When VF wants to set link, force it to read the bulletin instead.
1315 * This mimics the PF behavior, where a noitification [both immediate
1316 * and possible later] would be generated when changing properties.
1319 qed_schedule_iov(hwfn
, QED_IOV_WQ_VF_FORCE_LINK_QUERY_FLAG
);
1323 ptt
= qed_ptt_acquire(hwfn
);
1327 link_params
= qed_mcp_get_link_params(hwfn
);
1328 if (params
->override_flags
& QED_LINK_OVERRIDE_SPEED_AUTONEG
)
1329 link_params
->speed
.autoneg
= params
->autoneg
;
1330 if (params
->override_flags
& QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS
) {
1331 link_params
->speed
.advertised_speeds
= 0;
1332 if ((params
->adv_speeds
& QED_LM_1000baseT_Half_BIT
) ||
1333 (params
->adv_speeds
& QED_LM_1000baseT_Full_BIT
))
1334 link_params
->speed
.advertised_speeds
|=
1335 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G
;
1336 if (params
->adv_speeds
& QED_LM_10000baseKR_Full_BIT
)
1337 link_params
->speed
.advertised_speeds
|=
1338 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G
;
1339 if (params
->adv_speeds
& QED_LM_25000baseKR_Full_BIT
)
1340 link_params
->speed
.advertised_speeds
|=
1341 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G
;
1342 if (params
->adv_speeds
& QED_LM_40000baseLR4_Full_BIT
)
1343 link_params
->speed
.advertised_speeds
|=
1344 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G
;
1345 if (params
->adv_speeds
& QED_LM_50000baseKR2_Full_BIT
)
1346 link_params
->speed
.advertised_speeds
|=
1347 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G
;
1348 if (params
->adv_speeds
& QED_LM_100000baseKR4_Full_BIT
)
1349 link_params
->speed
.advertised_speeds
|=
1350 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G
;
1352 if (params
->override_flags
& QED_LINK_OVERRIDE_SPEED_FORCED_SPEED
)
1353 link_params
->speed
.forced_speed
= params
->forced_speed
;
1354 if (params
->override_flags
& QED_LINK_OVERRIDE_PAUSE_CONFIG
) {
1355 if (params
->pause_config
& QED_LINK_PAUSE_AUTONEG_ENABLE
)
1356 link_params
->pause
.autoneg
= true;
1358 link_params
->pause
.autoneg
= false;
1359 if (params
->pause_config
& QED_LINK_PAUSE_RX_ENABLE
)
1360 link_params
->pause
.forced_rx
= true;
1362 link_params
->pause
.forced_rx
= false;
1363 if (params
->pause_config
& QED_LINK_PAUSE_TX_ENABLE
)
1364 link_params
->pause
.forced_tx
= true;
1366 link_params
->pause
.forced_tx
= false;
1368 if (params
->override_flags
& QED_LINK_OVERRIDE_LOOPBACK_MODE
) {
1369 switch (params
->loopback_mode
) {
1370 case QED_LINK_LOOPBACK_INT_PHY
:
1371 link_params
->loopback_mode
= ETH_LOOPBACK_INT_PHY
;
1373 case QED_LINK_LOOPBACK_EXT_PHY
:
1374 link_params
->loopback_mode
= ETH_LOOPBACK_EXT_PHY
;
1376 case QED_LINK_LOOPBACK_EXT
:
1377 link_params
->loopback_mode
= ETH_LOOPBACK_EXT
;
1379 case QED_LINK_LOOPBACK_MAC
:
1380 link_params
->loopback_mode
= ETH_LOOPBACK_MAC
;
1383 link_params
->loopback_mode
= ETH_LOOPBACK_NONE
;
1388 if (params
->override_flags
& QED_LINK_OVERRIDE_EEE_CONFIG
)
1389 memcpy(&link_params
->eee
, ¶ms
->eee
,
1390 sizeof(link_params
->eee
));
1392 rc
= qed_mcp_set_link(hwfn
, ptt
, params
->link_up
);
1394 qed_ptt_release(hwfn
, ptt
);
1399 static int qed_get_port_type(u32 media_type
)
1403 switch (media_type
) {
1404 case MEDIA_SFPP_10G_FIBER
:
1405 case MEDIA_SFP_1G_FIBER
:
1406 case MEDIA_XFP_FIBER
:
1407 case MEDIA_MODULE_FIBER
:
1409 port_type
= PORT_FIBRE
;
1411 case MEDIA_DA_TWINAX
:
1412 port_type
= PORT_DA
;
1415 port_type
= PORT_TP
;
1417 case MEDIA_NOT_PRESENT
:
1418 port_type
= PORT_NONE
;
1420 case MEDIA_UNSPECIFIED
:
1422 port_type
= PORT_OTHER
;
1428 static int qed_get_link_data(struct qed_hwfn
*hwfn
,
1429 struct qed_mcp_link_params
*params
,
1430 struct qed_mcp_link_state
*link
,
1431 struct qed_mcp_link_capabilities
*link_caps
)
1435 if (!IS_PF(hwfn
->cdev
)) {
1436 qed_vf_get_link_params(hwfn
, params
);
1437 qed_vf_get_link_state(hwfn
, link
);
1438 qed_vf_get_link_caps(hwfn
, link_caps
);
1443 p
= qed_mcp_get_link_params(hwfn
);
1446 memcpy(params
, p
, sizeof(*params
));
1448 p
= qed_mcp_get_link_state(hwfn
);
1451 memcpy(link
, p
, sizeof(*link
));
1453 p
= qed_mcp_get_link_capabilities(hwfn
);
1456 memcpy(link_caps
, p
, sizeof(*link_caps
));
1461 static void qed_fill_link(struct qed_hwfn
*hwfn
,
1462 struct qed_link_output
*if_link
)
1464 struct qed_mcp_link_params params
;
1465 struct qed_mcp_link_state link
;
1466 struct qed_mcp_link_capabilities link_caps
;
1469 memset(if_link
, 0, sizeof(*if_link
));
1471 /* Prepare source inputs */
1472 if (qed_get_link_data(hwfn
, ¶ms
, &link
, &link_caps
)) {
1473 dev_warn(&hwfn
->cdev
->pdev
->dev
, "no link data available\n");
1477 /* Set the link parameters to pass to protocol driver */
1479 if_link
->link_up
= true;
1481 /* TODO - at the moment assume supported and advertised speed equal */
1482 if_link
->supported_caps
= QED_LM_FIBRE_BIT
;
1483 if (link_caps
.default_speed_autoneg
)
1484 if_link
->supported_caps
|= QED_LM_Autoneg_BIT
;
1485 if (params
.pause
.autoneg
||
1486 (params
.pause
.forced_rx
&& params
.pause
.forced_tx
))
1487 if_link
->supported_caps
|= QED_LM_Asym_Pause_BIT
;
1488 if (params
.pause
.autoneg
|| params
.pause
.forced_rx
||
1489 params
.pause
.forced_tx
)
1490 if_link
->supported_caps
|= QED_LM_Pause_BIT
;
1492 if_link
->advertised_caps
= if_link
->supported_caps
;
1493 if (params
.speed
.autoneg
)
1494 if_link
->advertised_caps
|= QED_LM_Autoneg_BIT
;
1496 if_link
->advertised_caps
&= ~QED_LM_Autoneg_BIT
;
1497 if (params
.speed
.advertised_speeds
&
1498 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G
)
1499 if_link
->advertised_caps
|= QED_LM_1000baseT_Half_BIT
|
1500 QED_LM_1000baseT_Full_BIT
;
1501 if (params
.speed
.advertised_speeds
&
1502 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G
)
1503 if_link
->advertised_caps
|= QED_LM_10000baseKR_Full_BIT
;
1504 if (params
.speed
.advertised_speeds
&
1505 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G
)
1506 if_link
->advertised_caps
|= QED_LM_25000baseKR_Full_BIT
;
1507 if (params
.speed
.advertised_speeds
&
1508 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G
)
1509 if_link
->advertised_caps
|= QED_LM_40000baseLR4_Full_BIT
;
1510 if (params
.speed
.advertised_speeds
&
1511 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G
)
1512 if_link
->advertised_caps
|= QED_LM_50000baseKR2_Full_BIT
;
1513 if (params
.speed
.advertised_speeds
&
1514 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G
)
1515 if_link
->advertised_caps
|= QED_LM_100000baseKR4_Full_BIT
;
1517 if (link_caps
.speed_capabilities
&
1518 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G
)
1519 if_link
->supported_caps
|= QED_LM_1000baseT_Half_BIT
|
1520 QED_LM_1000baseT_Full_BIT
;
1521 if (link_caps
.speed_capabilities
&
1522 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G
)
1523 if_link
->supported_caps
|= QED_LM_10000baseKR_Full_BIT
;
1524 if (link_caps
.speed_capabilities
&
1525 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G
)
1526 if_link
->supported_caps
|= QED_LM_25000baseKR_Full_BIT
;
1527 if (link_caps
.speed_capabilities
&
1528 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G
)
1529 if_link
->supported_caps
|= QED_LM_40000baseLR4_Full_BIT
;
1530 if (link_caps
.speed_capabilities
&
1531 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G
)
1532 if_link
->supported_caps
|= QED_LM_50000baseKR2_Full_BIT
;
1533 if (link_caps
.speed_capabilities
&
1534 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G
)
1535 if_link
->supported_caps
|= QED_LM_100000baseKR4_Full_BIT
;
1538 if_link
->speed
= link
.speed
;
1540 /* TODO - fill duplex properly */
1541 if_link
->duplex
= DUPLEX_FULL
;
1542 qed_mcp_get_media_type(hwfn
->cdev
, &media_type
);
1543 if_link
->port
= qed_get_port_type(media_type
);
1545 if_link
->autoneg
= params
.speed
.autoneg
;
1547 if (params
.pause
.autoneg
)
1548 if_link
->pause_config
|= QED_LINK_PAUSE_AUTONEG_ENABLE
;
1549 if (params
.pause
.forced_rx
)
1550 if_link
->pause_config
|= QED_LINK_PAUSE_RX_ENABLE
;
1551 if (params
.pause
.forced_tx
)
1552 if_link
->pause_config
|= QED_LINK_PAUSE_TX_ENABLE
;
1554 /* Link partner capabilities */
1555 if (link
.partner_adv_speed
& QED_LINK_PARTNER_SPEED_1G_HD
)
1556 if_link
->lp_caps
|= QED_LM_1000baseT_Half_BIT
;
1557 if (link
.partner_adv_speed
& QED_LINK_PARTNER_SPEED_1G_FD
)
1558 if_link
->lp_caps
|= QED_LM_1000baseT_Full_BIT
;
1559 if (link
.partner_adv_speed
& QED_LINK_PARTNER_SPEED_10G
)
1560 if_link
->lp_caps
|= QED_LM_10000baseKR_Full_BIT
;
1561 if (link
.partner_adv_speed
& QED_LINK_PARTNER_SPEED_25G
)
1562 if_link
->lp_caps
|= QED_LM_25000baseKR_Full_BIT
;
1563 if (link
.partner_adv_speed
& QED_LINK_PARTNER_SPEED_40G
)
1564 if_link
->lp_caps
|= QED_LM_40000baseLR4_Full_BIT
;
1565 if (link
.partner_adv_speed
& QED_LINK_PARTNER_SPEED_50G
)
1566 if_link
->lp_caps
|= QED_LM_50000baseKR2_Full_BIT
;
1567 if (link
.partner_adv_speed
& QED_LINK_PARTNER_SPEED_100G
)
1568 if_link
->lp_caps
|= QED_LM_100000baseKR4_Full_BIT
;
1570 if (link
.an_complete
)
1571 if_link
->lp_caps
|= QED_LM_Autoneg_BIT
;
1573 if (link
.partner_adv_pause
)
1574 if_link
->lp_caps
|= QED_LM_Pause_BIT
;
1575 if (link
.partner_adv_pause
== QED_LINK_PARTNER_ASYMMETRIC_PAUSE
||
1576 link
.partner_adv_pause
== QED_LINK_PARTNER_BOTH_PAUSE
)
1577 if_link
->lp_caps
|= QED_LM_Asym_Pause_BIT
;
1579 if (link_caps
.default_eee
== QED_MCP_EEE_UNSUPPORTED
) {
1580 if_link
->eee_supported
= false;
1582 if_link
->eee_supported
= true;
1583 if_link
->eee_active
= link
.eee_active
;
1584 if_link
->sup_caps
= link_caps
.eee_speed_caps
;
1585 /* MFW clears adv_caps on eee disable; use configured value */
1586 if_link
->eee
.adv_caps
= link
.eee_adv_caps
? link
.eee_adv_caps
:
1587 params
.eee
.adv_caps
;
1588 if_link
->eee
.lp_adv_caps
= link
.eee_lp_adv_caps
;
1589 if_link
->eee
.enable
= params
.eee
.enable
;
1590 if_link
->eee
.tx_lpi_enable
= params
.eee
.tx_lpi_enable
;
1591 if_link
->eee
.tx_lpi_timer
= params
.eee
.tx_lpi_timer
;
1595 static void qed_get_current_link(struct qed_dev
*cdev
,
1596 struct qed_link_output
*if_link
)
1600 qed_fill_link(&cdev
->hwfns
[0], if_link
);
1602 for_each_hwfn(cdev
, i
)
1603 qed_inform_vf_link_state(&cdev
->hwfns
[i
]);
1606 void qed_link_update(struct qed_hwfn
*hwfn
)
1608 void *cookie
= hwfn
->cdev
->ops_cookie
;
1609 struct qed_common_cb_ops
*op
= hwfn
->cdev
->protocol_ops
.common
;
1610 struct qed_link_output if_link
;
1612 qed_fill_link(hwfn
, &if_link
);
1613 qed_inform_vf_link_state(hwfn
);
1615 if (IS_LEAD_HWFN(hwfn
) && cookie
)
1616 op
->link_update(cookie
, &if_link
);
1619 static int qed_drain(struct qed_dev
*cdev
)
1621 struct qed_hwfn
*hwfn
;
1622 struct qed_ptt
*ptt
;
1628 for_each_hwfn(cdev
, i
) {
1629 hwfn
= &cdev
->hwfns
[i
];
1630 ptt
= qed_ptt_acquire(hwfn
);
1632 DP_NOTICE(hwfn
, "Failed to drain NIG; No PTT\n");
1635 rc
= qed_mcp_drain(hwfn
, ptt
);
1638 qed_ptt_release(hwfn
, ptt
);
1644 static u32
qed_nvm_flash_image_access_crc(struct qed_dev
*cdev
,
1645 struct qed_nvm_image_att
*nvm_image
,
1652 /* Allocate a buffer for holding the nvram image */
1653 buf
= kzalloc(nvm_image
->length
, GFP_KERNEL
);
1657 /* Read image into buffer */
1658 rc
= qed_mcp_nvm_read(cdev
, nvm_image
->start_addr
,
1659 buf
, nvm_image
->length
);
1661 DP_ERR(cdev
, "Failed reading image from nvm\n");
1665 /* Convert the buffer into big-endian format (excluding the
1666 * closing 4 bytes of CRC).
1668 for (j
= 0; j
< nvm_image
->length
- 4; j
+= 4) {
1669 val
= cpu_to_be32(*(u32
*)&buf
[j
]);
1670 *(u32
*)&buf
[j
] = val
;
1673 /* Calc CRC for the "actual" image buffer, i.e. not including
1674 * the last 4 CRC bytes.
1676 *crc
= (~cpu_to_be32(crc32(0xffffffff, buf
, nvm_image
->length
- 4)));
1684 /* Binary file format -
1685 * /----------------------------------------------------------------------\
1686 * 0B | 0x4 [command index] |
1687 * 4B | image_type | Options | Number of register settings |
1691 * \----------------------------------------------------------------------/
1692 * There can be several Value-Mask-Offset sets as specified by 'Number of...'.
1693 * Options - 0'b - Calculate & Update CRC for image
1695 static int qed_nvm_flash_image_access(struct qed_dev
*cdev
, const u8
**data
,
1698 struct qed_nvm_image_att nvm_image
;
1699 struct qed_hwfn
*p_hwfn
;
1700 bool is_crc
= false;
1706 image_type
= **data
;
1707 p_hwfn
= QED_LEADING_HWFN(cdev
);
1708 for (i
= 0; i
< p_hwfn
->nvm_info
.num_images
; i
++)
1709 if (image_type
== p_hwfn
->nvm_info
.image_att
[i
].image_type
)
1711 if (i
== p_hwfn
->nvm_info
.num_images
) {
1712 DP_ERR(cdev
, "Failed to find nvram image of type %08x\n",
1717 nvm_image
.start_addr
= p_hwfn
->nvm_info
.image_att
[i
].nvm_start_addr
;
1718 nvm_image
.length
= p_hwfn
->nvm_info
.image_att
[i
].len
;
1720 DP_VERBOSE(cdev
, NETIF_MSG_DRV
,
1721 "Read image %02x; type = %08x; NVM [%08x,...,%08x]\n",
1722 **data
, image_type
, nvm_image
.start_addr
,
1723 nvm_image
.start_addr
+ nvm_image
.length
- 1);
1725 is_crc
= !!(**data
& BIT(0));
1727 len
= *((u16
*)*data
);
1732 rc
= qed_nvm_flash_image_access_crc(cdev
, &nvm_image
, &crc
);
1734 DP_ERR(cdev
, "Failed calculating CRC, rc = %d\n", rc
);
1738 rc
= qed_mcp_nvm_write(cdev
, QED_NVM_WRITE_NVRAM
,
1739 (nvm_image
.start_addr
+
1740 nvm_image
.length
- 4), (u8
*)&crc
, 4);
1742 DP_ERR(cdev
, "Failed writing to %08x, rc = %d\n",
1743 nvm_image
.start_addr
+ nvm_image
.length
- 4, rc
);
1747 /* Iterate over the values for setting */
1749 u32 offset
, mask
, value
, cur_value
;
1752 value
= *((u32
*)*data
);
1754 mask
= *((u32
*)*data
);
1756 offset
= *((u32
*)*data
);
1759 rc
= qed_mcp_nvm_read(cdev
, nvm_image
.start_addr
+ offset
, buf
,
1762 DP_ERR(cdev
, "Failed reading from %08x\n",
1763 nvm_image
.start_addr
+ offset
);
1767 cur_value
= le32_to_cpu(*((__le32
*)buf
));
1768 DP_VERBOSE(cdev
, NETIF_MSG_DRV
,
1769 "NVM %08x: %08x -> %08x [Value %08x Mask %08x]\n",
1770 nvm_image
.start_addr
+ offset
, cur_value
,
1771 (cur_value
& ~mask
) | (value
& mask
), value
, mask
);
1772 value
= (value
& mask
) | (cur_value
& ~mask
);
1773 rc
= qed_mcp_nvm_write(cdev
, QED_NVM_WRITE_NVRAM
,
1774 nvm_image
.start_addr
+ offset
,
1777 DP_ERR(cdev
, "Failed writing to %08x\n",
1778 nvm_image
.start_addr
+ offset
);
1788 /* Binary file format -
1789 * /----------------------------------------------------------------------\
1790 * 0B | 0x3 [command index] |
1791 * 4B | b'0: check_response? | b'1-31 reserved |
1792 * 8B | File-type | reserved |
1793 * \----------------------------------------------------------------------/
1794 * Start a new file of the provided type
1796 static int qed_nvm_flash_image_file_start(struct qed_dev
*cdev
,
1797 const u8
**data
, bool *check_resp
)
1802 *check_resp
= !!(**data
& BIT(0));
1805 DP_VERBOSE(cdev
, NETIF_MSG_DRV
,
1806 "About to start a new file of type %02x\n", **data
);
1807 rc
= qed_mcp_nvm_put_file_begin(cdev
, **data
);
1813 /* Binary file format -
1814 * /----------------------------------------------------------------------\
1815 * 0B | 0x2 [command index] |
1816 * 4B | Length in bytes |
1817 * 8B | b'0: check_response? | b'1-31 reserved |
1818 * 12B | Offset in bytes |
1820 * \----------------------------------------------------------------------/
1821 * Write data as part of a file that was previously started. Data should be
1822 * of length equal to that provided in the message
1824 static int qed_nvm_flash_image_file_data(struct qed_dev
*cdev
,
1825 const u8
**data
, bool *check_resp
)
1831 len
= *((u32
*)(*data
));
1833 *check_resp
= !!(**data
& BIT(0));
1835 offset
= *((u32
*)(*data
));
1838 DP_VERBOSE(cdev
, NETIF_MSG_DRV
,
1839 "About to write File-data: %08x bytes to offset %08x\n",
1842 rc
= qed_mcp_nvm_write(cdev
, QED_PUT_FILE_DATA
, offset
,
1843 (char *)(*data
), len
);
1849 /* Binary file format [General header] -
1850 * /----------------------------------------------------------------------\
1851 * 0B | QED_NVM_SIGNATURE |
1852 * 4B | Length in bytes |
1853 * 8B | Highest command in this batchfile | Reserved |
1854 * \----------------------------------------------------------------------/
1856 static int qed_nvm_flash_image_validate(struct qed_dev
*cdev
,
1857 const struct firmware
*image
,
1862 /* Check minimum size */
1863 if (image
->size
< 12) {
1864 DP_ERR(cdev
, "Image is too short [%08x]\n", (u32
)image
->size
);
1868 /* Check signature */
1869 signature
= *((u32
*)(*data
));
1870 if (signature
!= QED_NVM_SIGNATURE
) {
1871 DP_ERR(cdev
, "Wrong signature '%08x'\n", signature
);
1876 /* Validate internal size equals the image-size */
1877 len
= *((u32
*)(*data
));
1878 if (len
!= image
->size
) {
1879 DP_ERR(cdev
, "Size mismatch: internal = %08x image = %08x\n",
1880 len
, (u32
)image
->size
);
1885 /* Make sure driver familiar with all commands necessary for this */
1886 if (*((u16
*)(*data
)) >= QED_NVM_FLASH_CMD_NVM_MAX
) {
1887 DP_ERR(cdev
, "File contains unsupported commands [Need %04x]\n",
1897 static int qed_nvm_flash(struct qed_dev
*cdev
, const char *name
)
1899 const struct firmware
*image
;
1900 const u8
*data
, *data_end
;
1904 rc
= request_firmware(&image
, name
, &cdev
->pdev
->dev
);
1906 DP_ERR(cdev
, "Failed to find '%s'\n", name
);
1910 DP_VERBOSE(cdev
, NETIF_MSG_DRV
,
1911 "Flashing '%s' - firmware's data at %p, size is %08x\n",
1912 name
, image
->data
, (u32
)image
->size
);
1914 data_end
= data
+ image
->size
;
1916 rc
= qed_nvm_flash_image_validate(cdev
, image
, &data
);
1920 while (data
< data_end
) {
1921 bool check_resp
= false;
1923 /* Parse the actual command */
1924 cmd_type
= *((u32
*)data
);
1926 case QED_NVM_FLASH_CMD_FILE_DATA
:
1927 rc
= qed_nvm_flash_image_file_data(cdev
, &data
,
1930 case QED_NVM_FLASH_CMD_FILE_START
:
1931 rc
= qed_nvm_flash_image_file_start(cdev
, &data
,
1934 case QED_NVM_FLASH_CMD_NVM_CHANGE
:
1935 rc
= qed_nvm_flash_image_access(cdev
, &data
,
1939 DP_ERR(cdev
, "Unknown command %08x\n", cmd_type
);
1945 DP_ERR(cdev
, "Command %08x failed\n", cmd_type
);
1949 /* Check response if needed */
1951 u32 mcp_response
= 0;
1953 if (qed_mcp_nvm_resp(cdev
, (u8
*)&mcp_response
)) {
1954 DP_ERR(cdev
, "Failed getting MCP response\n");
1959 switch (mcp_response
& FW_MSG_CODE_MASK
) {
1960 case FW_MSG_CODE_OK
:
1961 case FW_MSG_CODE_NVM_OK
:
1962 case FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK
:
1963 case FW_MSG_CODE_PHY_OK
:
1966 DP_ERR(cdev
, "MFW returns error: %08x\n",
1975 release_firmware(image
);
1980 static int qed_nvm_get_image(struct qed_dev
*cdev
, enum qed_nvm_images type
,
1983 struct qed_hwfn
*hwfn
= QED_LEADING_HWFN(cdev
);
1985 return qed_mcp_get_nvm_image(hwfn
, type
, buf
, len
);
1988 static int qed_set_coalesce(struct qed_dev
*cdev
, u16 rx_coal
, u16 tx_coal
,
1991 return qed_set_queue_coalesce(rx_coal
, tx_coal
, handle
);
1994 static int qed_set_led(struct qed_dev
*cdev
, enum qed_led_mode mode
)
1996 struct qed_hwfn
*hwfn
= QED_LEADING_HWFN(cdev
);
1997 struct qed_ptt
*ptt
;
2000 ptt
= qed_ptt_acquire(hwfn
);
2004 status
= qed_mcp_set_led(hwfn
, ptt
, mode
);
2006 qed_ptt_release(hwfn
, ptt
);
2011 static int qed_update_wol(struct qed_dev
*cdev
, bool enabled
)
2013 struct qed_hwfn
*hwfn
= QED_LEADING_HWFN(cdev
);
2014 struct qed_ptt
*ptt
;
2020 ptt
= qed_ptt_acquire(hwfn
);
2024 rc
= qed_mcp_ov_update_wol(hwfn
, ptt
, enabled
? QED_OV_WOL_ENABLED
2025 : QED_OV_WOL_DISABLED
);
2028 rc
= qed_mcp_ov_update_current_config(hwfn
, ptt
, QED_OV_CLIENT_DRV
);
2031 qed_ptt_release(hwfn
, ptt
);
2035 static int qed_update_drv_state(struct qed_dev
*cdev
, bool active
)
2037 struct qed_hwfn
*hwfn
= QED_LEADING_HWFN(cdev
);
2038 struct qed_ptt
*ptt
;
2044 ptt
= qed_ptt_acquire(hwfn
);
2048 status
= qed_mcp_ov_update_driver_state(hwfn
, ptt
, active
?
2049 QED_OV_DRIVER_STATE_ACTIVE
:
2050 QED_OV_DRIVER_STATE_DISABLED
);
2052 qed_ptt_release(hwfn
, ptt
);
2057 static int qed_update_mac(struct qed_dev
*cdev
, u8
*mac
)
2059 struct qed_hwfn
*hwfn
= QED_LEADING_HWFN(cdev
);
2060 struct qed_ptt
*ptt
;
2066 ptt
= qed_ptt_acquire(hwfn
);
2070 status
= qed_mcp_ov_update_mac(hwfn
, ptt
, mac
);
2074 status
= qed_mcp_ov_update_current_config(hwfn
, ptt
, QED_OV_CLIENT_DRV
);
2077 qed_ptt_release(hwfn
, ptt
);
2081 static int qed_update_mtu(struct qed_dev
*cdev
, u16 mtu
)
2083 struct qed_hwfn
*hwfn
= QED_LEADING_HWFN(cdev
);
2084 struct qed_ptt
*ptt
;
2090 ptt
= qed_ptt_acquire(hwfn
);
2094 status
= qed_mcp_ov_update_mtu(hwfn
, ptt
, mtu
);
2098 status
= qed_mcp_ov_update_current_config(hwfn
, ptt
, QED_OV_CLIENT_DRV
);
2101 qed_ptt_release(hwfn
, ptt
);
2105 static struct qed_selftest_ops qed_selftest_ops_pass
= {
2106 .selftest_memory
= &qed_selftest_memory
,
2107 .selftest_interrupt
= &qed_selftest_interrupt
,
2108 .selftest_register
= &qed_selftest_register
,
2109 .selftest_clock
= &qed_selftest_clock
,
2110 .selftest_nvram
= &qed_selftest_nvram
,
2113 const struct qed_common_ops qed_common_ops_pass
= {
2114 .selftest
= &qed_selftest_ops_pass
,
2115 .probe
= &qed_probe
,
2116 .remove
= &qed_remove
,
2117 .set_power_state
= &qed_set_power_state
,
2118 .set_name
= &qed_set_name
,
2119 .update_pf_params
= &qed_update_pf_params
,
2120 .slowpath_start
= &qed_slowpath_start
,
2121 .slowpath_stop
= &qed_slowpath_stop
,
2122 .set_fp_int
= &qed_set_int_fp
,
2123 .get_fp_int
= &qed_get_int_fp
,
2124 .sb_init
= &qed_sb_init
,
2125 .sb_release
= &qed_sb_release
,
2126 .simd_handler_config
= &qed_simd_handler_config
,
2127 .simd_handler_clean
= &qed_simd_handler_clean
,
2128 .dbg_grc
= &qed_dbg_grc
,
2129 .dbg_grc_size
= &qed_dbg_grc_size
,
2130 .can_link_change
= &qed_can_link_change
,
2131 .set_link
= &qed_set_link
,
2132 .get_link
= &qed_get_current_link
,
2133 .drain
= &qed_drain
,
2134 .update_msglvl
= &qed_init_dp
,
2135 .dbg_all_data
= &qed_dbg_all_data
,
2136 .dbg_all_data_size
= &qed_dbg_all_data_size
,
2137 .chain_alloc
= &qed_chain_alloc
,
2138 .chain_free
= &qed_chain_free
,
2139 .nvm_flash
= &qed_nvm_flash
,
2140 .nvm_get_image
= &qed_nvm_get_image
,
2141 .set_coalesce
= &qed_set_coalesce
,
2142 .set_led
= &qed_set_led
,
2143 .update_drv_state
= &qed_update_drv_state
,
2144 .update_mac
= &qed_update_mac
,
2145 .update_mtu
= &qed_update_mtu
,
2146 .update_wol
= &qed_update_wol
,
2149 void qed_get_protocol_stats(struct qed_dev
*cdev
,
2150 enum qed_mcp_protocol_type type
,
2151 union qed_mcp_protocol_stats
*stats
)
2153 struct qed_eth_stats eth_stats
;
2155 memset(stats
, 0, sizeof(*stats
));
2158 case QED_MCP_LAN_STATS
:
2159 qed_get_vport_stats(cdev
, ð_stats
);
2160 stats
->lan_stats
.ucast_rx_pkts
=
2161 eth_stats
.common
.rx_ucast_pkts
;
2162 stats
->lan_stats
.ucast_tx_pkts
=
2163 eth_stats
.common
.tx_ucast_pkts
;
2164 stats
->lan_stats
.fcs_err
= -1;
2166 case QED_MCP_FCOE_STATS
:
2167 qed_get_protocol_stats_fcoe(cdev
, &stats
->fcoe_stats
);
2169 case QED_MCP_ISCSI_STATS
:
2170 qed_get_protocol_stats_iscsi(cdev
, &stats
->iscsi_stats
);
2173 DP_VERBOSE(cdev
, QED_MSG_SP
,
2174 "Invalid protocol type = %d\n", type
);
2179 int qed_mfw_tlv_req(struct qed_hwfn
*hwfn
)
2181 DP_VERBOSE(hwfn
->cdev
, NETIF_MSG_DRV
,
2182 "Scheduling slowpath task [Flag: %d]\n",
2183 QED_SLOWPATH_MFW_TLV_REQ
);
2184 smp_mb__before_atomic();
2185 set_bit(QED_SLOWPATH_MFW_TLV_REQ
, &hwfn
->slowpath_task_flags
);
2186 smp_mb__after_atomic();
2187 queue_delayed_work(hwfn
->slowpath_wq
, &hwfn
->slowpath_task
, 0);
2193 qed_fill_generic_tlv_data(struct qed_dev
*cdev
, struct qed_mfw_tlv_generic
*tlv
)
2195 struct qed_common_cb_ops
*op
= cdev
->protocol_ops
.common
;
2196 struct qed_eth_stats_common
*p_common
;
2197 struct qed_generic_tlvs gen_tlvs
;
2198 struct qed_eth_stats stats
;
2201 memset(&gen_tlvs
, 0, sizeof(gen_tlvs
));
2202 op
->get_generic_tlv_data(cdev
->ops_cookie
, &gen_tlvs
);
2204 if (gen_tlvs
.feat_flags
& QED_TLV_IP_CSUM
)
2205 tlv
->flags
.ipv4_csum_offload
= true;
2206 if (gen_tlvs
.feat_flags
& QED_TLV_LSO
)
2207 tlv
->flags
.lso_supported
= true;
2208 tlv
->flags
.b_set
= true;
2210 for (i
= 0; i
< QED_TLV_MAC_COUNT
; i
++) {
2211 if (is_valid_ether_addr(gen_tlvs
.mac
[i
])) {
2212 ether_addr_copy(tlv
->mac
[i
], gen_tlvs
.mac
[i
]);
2213 tlv
->mac_set
[i
] = true;
2217 qed_get_vport_stats(cdev
, &stats
);
2218 p_common
= &stats
.common
;
2219 tlv
->rx_frames
= p_common
->rx_ucast_pkts
+ p_common
->rx_mcast_pkts
+
2220 p_common
->rx_bcast_pkts
;
2221 tlv
->rx_frames_set
= true;
2222 tlv
->rx_bytes
= p_common
->rx_ucast_bytes
+ p_common
->rx_mcast_bytes
+
2223 p_common
->rx_bcast_bytes
;
2224 tlv
->rx_bytes_set
= true;
2225 tlv
->tx_frames
= p_common
->tx_ucast_pkts
+ p_common
->tx_mcast_pkts
+
2226 p_common
->tx_bcast_pkts
;
2227 tlv
->tx_frames_set
= true;
2228 tlv
->tx_bytes
= p_common
->tx_ucast_bytes
+ p_common
->tx_mcast_bytes
+
2229 p_common
->tx_bcast_bytes
;
2230 tlv
->rx_bytes_set
= true;
2233 int qed_mfw_fill_tlv_data(struct qed_hwfn
*hwfn
, enum qed_mfw_tlv_type type
,
2234 union qed_mfw_tlv_data
*tlv_buf
)
2236 struct qed_dev
*cdev
= hwfn
->cdev
;
2237 struct qed_common_cb_ops
*ops
;
2239 ops
= cdev
->protocol_ops
.common
;
2240 if (!ops
|| !ops
->get_protocol_tlv_data
|| !ops
->get_generic_tlv_data
) {
2241 DP_NOTICE(hwfn
, "Can't collect TLV management info\n");
2246 case QED_MFW_TLV_GENERIC
:
2247 qed_fill_generic_tlv_data(hwfn
->cdev
, &tlv_buf
->generic
);
2249 case QED_MFW_TLV_ETH
:
2250 ops
->get_protocol_tlv_data(cdev
->ops_cookie
, &tlv_buf
->eth
);
2252 case QED_MFW_TLV_FCOE
:
2253 ops
->get_protocol_tlv_data(cdev
->ops_cookie
, &tlv_buf
->fcoe
);
2255 case QED_MFW_TLV_ISCSI
:
2256 ops
->get_protocol_tlv_data(cdev
->ops_cookie
, &tlv_buf
->iscsi
);