drivers/net/ethernet/qlogic/qed/qed_reg_addr.h

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef REG_ADDR_H
  34 #define REG_ADDR_H
  35
  36 #define  CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT \
  37         0
  38
  39 #define  CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE           ( \
  40                 0xfff << 0)
  41
  42 #define  CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \
  43         12
  44
  45 #define  CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE            ( \
  46                 0xfff << 12)
  47
  48 #define  CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \
  49         24
  50
  51 #define  CDU_REG_CID_ADDR_PARAMS_NCIB                   ( \
  52                 0xff << 24)
  53
  54 #define CDU_REG_SEGMENT0_PARAMS \
  55         0x580904UL
  56 #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK \
  57         (0xfff << 0)
  58 #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT \
  59         0
  60 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE \
  61         (0xff << 16)
  62 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT \
  63         16
  64 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE \
  65         (0xff << 24)
  66 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT \
  67         24
  68 #define CDU_REG_SEGMENT1_PARAMS \
  69         0x580908UL
  70 #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK \
  71         (0xfff << 0)
  72 #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT \
  73         0
  74 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE \
  75         (0xff << 16)
  76 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT \
  77         16
  78 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE \
  79         (0xff << 24)
  80 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT \
  81         24
  82
  83 #define  XSDM_REG_OPERATION_GEN \
  84         0xf80408UL
  85 #define  NIG_REG_RX_BRB_OUT_EN \
  86         0x500e18UL
  87 #define  NIG_REG_STORM_OUT_EN \
  88         0x500e08UL
  89 #define  PSWRQ2_REG_L2P_VALIDATE_VFID \
  90         0x240c50UL
  91 #define  PGLUE_B_REG_USE_CLIENTID_IN_TAG        \
  92         0x2aae04UL
  93 #define  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER        \
  94         0x2aa16cUL
  95 #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR \
  96         0x2aa118UL
  97 #define PSWHST_REG_ZONE_PERMISSION_TABLE \
  98         0x2a0800UL
  99 #define  BAR0_MAP_REG_MSDM_RAM \
 100         0x1d00000UL
 101 #define  BAR0_MAP_REG_USDM_RAM \
 102         0x1d80000UL
 103 #define  BAR0_MAP_REG_PSDM_RAM \
 104         0x1f00000UL
 105 #define  BAR0_MAP_REG_TSDM_RAM \
 106         0x1c80000UL
 107 #define BAR0_MAP_REG_XSDM_RAM \
 108         0x1e00000UL
 109 #define BAR0_MAP_REG_YSDM_RAM \
 110         0x1e80000UL
 111 #define  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF \
 112         0x5011f4UL
 113 #define  PRS_REG_SEARCH_TCP \
 114         0x1f0400UL
 115 #define  PRS_REG_SEARCH_UDP \
 116         0x1f0404UL
 117 #define  PRS_REG_SEARCH_FCOE \
 118         0x1f0408UL
 119 #define  PRS_REG_SEARCH_ROCE \
 120         0x1f040cUL
 121 #define  PRS_REG_SEARCH_OPENFLOW        \
 122         0x1f0434UL
 123 #define  TM_REG_PF_ENABLE_CONN \
 124         0x2c043cUL
 125 #define  TM_REG_PF_ENABLE_TASK \
 126         0x2c0444UL
 127 #define  TM_REG_PF_SCAN_ACTIVE_CONN \
 128         0x2c04fcUL
 129 #define  TM_REG_PF_SCAN_ACTIVE_TASK \
 130         0x2c0500UL
 131 #define  IGU_REG_LEADING_EDGE_LATCH \
 132         0x18082cUL
 133 #define  IGU_REG_TRAILING_EDGE_LATCH \
 134         0x180830UL
 135 #define  QM_REG_USG_CNT_PF_TX \
 136         0x2f2eacUL
 137 #define  QM_REG_USG_CNT_PF_OTHER        \
 138         0x2f2eb0UL
 139 #define  DORQ_REG_PF_DB_ENABLE \
 140         0x100508UL
 141 #define DORQ_REG_VF_USAGE_CNT \
 142         0x1009c4UL
 143 #define  QM_REG_PF_EN \
 144         0x2f2ea4UL
 145 #define TCFC_REG_WEAK_ENABLE_VF \
 146         0x2d0704UL
 147 #define  TCFC_REG_STRONG_ENABLE_PF \
 148         0x2d0708UL
 149 #define  TCFC_REG_STRONG_ENABLE_VF \
 150         0x2d070cUL
 151 #define CCFC_REG_WEAK_ENABLE_VF \
 152         0x2e0704UL
 153 #define  CCFC_REG_STRONG_ENABLE_PF \
 154         0x2e0708UL
 155 #define  PGLUE_B_REG_PGL_ADDR_88_F0 \
 156         0x2aa404UL
 157 #define  PGLUE_B_REG_PGL_ADDR_8C_F0 \
 158         0x2aa408UL
 159 #define  PGLUE_B_REG_PGL_ADDR_90_F0 \
 160         0x2aa40cUL
 161 #define  PGLUE_B_REG_PGL_ADDR_94_F0 \
 162         0x2aa410UL
 163 #define  PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR \
 164         0x2aa138UL
 165 #define  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \
 166         0x2aa174UL
 167 #define  MISC_REG_GEN_PURP_CR0 \
 168         0x008c80UL
 169 #define  MCP_REG_SCRATCH        \
 170         0xe20000UL
 171 #define  CNIG_REG_NW_PORT_MODE_BB_B0 \
 172         0x218200UL
 173 #define  MISCS_REG_CHIP_NUM \
 174         0x00976cUL
 175 #define  MISCS_REG_CHIP_REV \
 176         0x009770UL
 177 #define  MISCS_REG_CMT_ENABLED_FOR_PAIR \
 178         0x00971cUL
 179 #define  MISCS_REG_CHIP_TEST_REG        \
 180         0x009778UL
 181 #define  MISCS_REG_CHIP_METAL \
 182         0x009774UL
 183 #define MISCS_REG_FUNCTION_HIDE \
 184         0x0096f0UL
 185 #define  BRB_REG_HEADER_SIZE \
 186         0x340804UL
 187 #define  BTB_REG_HEADER_SIZE \
 188         0xdb0804UL
 189 #define  CAU_REG_LONG_TIMEOUT_THRESHOLD \
 190         0x1c0708UL
 191 #define  CCFC_REG_ACTIVITY_COUNTER \
 192         0x2e8800UL
 193 #define CCFC_REG_STRONG_ENABLE_VF \
 194         0x2e070cUL
 195 #define  CDU_REG_CID_ADDR_PARAMS        \
 196         0x580900UL
 197 #define  DBG_REG_CLIENT_ENABLE \
 198         0x010004UL
 199 #define  DMAE_REG_INIT \
 200         0x00c000UL
 201 #define  DORQ_REG_IFEN \
 202         0x100040UL
 203 #define DORQ_REG_DB_DROP_REASON \
 204         0x100a2cUL
 205 #define DORQ_REG_DB_DROP_DETAILS \
 206         0x100a24UL
 207 #define DORQ_REG_DB_DROP_DETAILS_ADDRESS \
 208         0x100a1cUL
 209 #define  GRC_REG_TIMEOUT_EN \
 210         0x050404UL
 211 #define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID \
 212         0x050054UL
 213 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 \
 214         0x05004cUL
 215 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1 \
 216         0x050050UL
 217 #define  IGU_REG_BLOCK_CONFIGURATION \
 218         0x180040UL
 219 #define  MCM_REG_INIT \
 220         0x1200000UL
 221 #define  MCP2_REG_DBG_DWORD_ENABLE \
 222         0x052404UL
 223 #define  MISC_REG_PORT_MODE \
 224         0x008c00UL
 225 #define  MISCS_REG_CLK_100G_MODE        \
 226         0x009070UL
 227 #define  MSDM_REG_ENABLE_IN1 \
 228         0xfc0004UL
 229 #define  MSEM_REG_ENABLE_IN \
 230         0x1800004UL
 231 #define  NIG_REG_CM_HDR \
 232         0x500840UL
 233 #define NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR \
 234         0x50196cUL
 235 #define NIG_REG_LLH_CLS_TYPE_DUALMODE \
 236         0x501964UL
 237 #define NIG_REG_LLH_FUNC_FILTER_VALUE \
 238         0x501a00UL
 239 #define NIG_REG_LLH_FUNC_FILTER_VALUE_SIZE \
 240         32
 241 #define NIG_REG_LLH_FUNC_FILTER_EN \
 242         0x501a80UL
 243 #define NIG_REG_LLH_FUNC_FILTER_EN_SIZE \
 244         16
 245 #define NIG_REG_LLH_FUNC_FILTER_MODE \
 246         0x501ac0UL
 247 #define NIG_REG_LLH_FUNC_FILTER_MODE_SIZE \
 248         16
 249 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE \
 250         0x501b00UL
 251 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_SIZE \
 252         16
 253 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL \
 254         0x501b40UL
 255 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_SIZE \
 256         16
 257 #define  NCSI_REG_CONFIG        \
 258         0x040200UL
 259 #define  PBF_REG_INIT \
 260         0xd80000UL
 261 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0 \
 262         0xd806c8UL
 263 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 \
 264         0xd806ccUL
 265 #define  PTU_REG_ATC_INIT_ARRAY \
 266         0x560000UL
 267 #define  PCM_REG_INIT \
 268         0x1100000UL
 269 #define  PGLUE_B_REG_ADMIN_PER_PF_REGION        \
 270         0x2a9000UL
 271 #define PGLUE_B_REG_TX_ERR_WR_DETAILS2 \
 272         0x2aa150UL
 273 #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 \
 274         0x2aa144UL
 275 #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 \
 276         0x2aa148UL
 277 #define PGLUE_B_REG_TX_ERR_WR_DETAILS \
 278         0x2aa14cUL
 279 #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 \
 280         0x2aa154UL
 281 #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 \
 282         0x2aa158UL
 283 #define PGLUE_B_REG_TX_ERR_RD_DETAILS \
 284         0x2aa15cUL
 285 #define PGLUE_B_REG_TX_ERR_RD_DETAILS2 \
 286         0x2aa160UL
 287 #define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL \
 288         0x2aa164UL
 289 #define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS \
 290         0x2aa54cUL
 291 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0 \
 292         0x2aa544UL
 293 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32 \
 294         0x2aa548UL
 295 #define PGLUE_B_REG_VF_ILT_ERR_ADD_31_0 \
 296         0x2aae74UL
 297 #define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 \
 298         0x2aae78UL
 299 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS \
 300         0x2aae7cUL
 301 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS2 \
 302         0x2aae80UL
 303 #define PGLUE_B_REG_LATCHED_ERRORS_CLR \
 304         0x2aa3bcUL
 305 #define  PRM_REG_DISABLE_PRM \
 306         0x230000UL
 307 #define  PRS_REG_SOFT_RST \
 308         0x1f0000UL
 309 #define PRS_REG_MSG_INFO \
 310         0x1f0a1cUL
 311 #define PRS_REG_ROCE_DEST_QP_MAX_PF \
 312         0x1f0430UL
 313 #define PRS_REG_USE_LIGHT_L2 \
 314         0x1f096cUL
 315 #define  PSDM_REG_ENABLE_IN1 \
 316         0xfa0004UL
 317 #define  PSEM_REG_ENABLE_IN \
 318         0x1600004UL
 319 #define  PSWRQ_REG_DBG_SELECT \
 320         0x280020UL
 321 #define  PSWRQ2_REG_CDUT_P_SIZE \
 322         0x24000cUL
 323 #define PSWRQ2_REG_ILT_MEMORY \
 324         0x260000UL
 325 #define  PSWHST_REG_DISCARD_INTERNAL_WRITES \
 326         0x2a0040UL
 327 #define  PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \
 328         0x29e050UL
 329 #define PSWHST_REG_INCORRECT_ACCESS_VALID \
 330         0x2a0070UL
 331 #define PSWHST_REG_INCORRECT_ACCESS_ADDRESS \
 332         0x2a0074UL
 333 #define PSWHST_REG_INCORRECT_ACCESS_DATA \
 334         0x2a0068UL
 335 #define PSWHST_REG_INCORRECT_ACCESS_LENGTH \
 336         0x2a006cUL
 337 #define  PSWRD_REG_DBG_SELECT \
 338         0x29c040UL
 339 #define  PSWRD2_REG_CONF11 \
 340         0x29d064UL
 341 #define  PSWWR_REG_USDM_FULL_TH \
 342         0x29a040UL
 343 #define  PSWWR2_REG_CDU_FULL_TH2        \
 344         0x29b040UL
 345 #define  QM_REG_MAXPQSIZE_0 \
 346         0x2f0434UL
 347 #define  RSS_REG_RSS_INIT_EN \
 348         0x238804UL
 349 #define  RDIF_REG_STOP_ON_ERROR \
 350         0x300040UL
 351 #define  SRC_REG_SOFT_RST \
 352         0x23874cUL
 353 #define  TCFC_REG_ACTIVITY_COUNTER \
 354         0x2d8800UL
 355 #define  TCM_REG_INIT \
 356         0x1180000UL
 357 #define  TM_REG_PXP_READ_DATA_FIFO_INIT \
 358         0x2c0014UL
 359 #define  TSDM_REG_ENABLE_IN1 \
 360         0xfb0004UL
 361 #define  TSEM_REG_ENABLE_IN \
 362         0x1700004UL
 363 #define  TDIF_REG_STOP_ON_ERROR \
 364         0x310040UL
 365 #define  UCM_REG_INIT \
 366         0x1280000UL
 367 #define  UMAC_REG_IPG_HD_BKP_CNTL_BB_B0 \
 368         0x051004UL
 369 #define  USDM_REG_ENABLE_IN1 \
 370         0xfd0004UL
 371 #define  USEM_REG_ENABLE_IN \
 372         0x1900004UL
 373 #define  XCM_REG_INIT \
 374         0x1000000UL
 375 #define  XSDM_REG_ENABLE_IN1 \
 376         0xf80004UL
 377 #define  XSEM_REG_ENABLE_IN \
 378         0x1400004UL
 379 #define  YCM_REG_INIT \
 380         0x1080000UL
 381 #define  YSDM_REG_ENABLE_IN1 \
 382         0xf90004UL
 383 #define  YSEM_REG_ENABLE_IN \
 384         0x1500004UL
 385 #define  XYLD_REG_SCBD_STRICT_PRIO \
 386         0x4c0000UL
 387 #define  TMLD_REG_SCBD_STRICT_PRIO \
 388         0x4d0000UL
 389 #define  MULD_REG_SCBD_STRICT_PRIO \
 390         0x4e0000UL
 391 #define  YULD_REG_SCBD_STRICT_PRIO \
 392         0x4c8000UL
 393 #define  MISC_REG_SHARED_MEM_ADDR \
 394         0x008c20UL
 395 #define  DMAE_REG_GO_C0 \
 396         0x00c048UL
 397 #define  DMAE_REG_GO_C1 \
 398         0x00c04cUL
 399 #define  DMAE_REG_GO_C2 \
 400         0x00c050UL
 401 #define  DMAE_REG_GO_C3 \
 402         0x00c054UL
 403 #define  DMAE_REG_GO_C4 \
 404         0x00c058UL
 405 #define  DMAE_REG_GO_C5 \
 406         0x00c05cUL
 407 #define  DMAE_REG_GO_C6 \
 408         0x00c060UL
 409 #define  DMAE_REG_GO_C7 \
 410         0x00c064UL
 411 #define  DMAE_REG_GO_C8 \
 412         0x00c068UL
 413 #define  DMAE_REG_GO_C9 \
 414         0x00c06cUL
 415 #define  DMAE_REG_GO_C10        \
 416         0x00c070UL
 417 #define  DMAE_REG_GO_C11        \
 418         0x00c074UL
 419 #define  DMAE_REG_GO_C12        \
 420         0x00c078UL
 421 #define  DMAE_REG_GO_C13        \
 422         0x00c07cUL
 423 #define  DMAE_REG_GO_C14        \
 424         0x00c080UL
 425 #define  DMAE_REG_GO_C15        \
 426         0x00c084UL
 427 #define  DMAE_REG_GO_C16        \
 428         0x00c088UL
 429 #define  DMAE_REG_GO_C17        \
 430         0x00c08cUL
 431 #define  DMAE_REG_GO_C18        \
 432         0x00c090UL
 433 #define  DMAE_REG_GO_C19        \
 434         0x00c094UL
 435 #define  DMAE_REG_GO_C20        \
 436         0x00c098UL
 437 #define  DMAE_REG_GO_C21        \
 438         0x00c09cUL
 439 #define  DMAE_REG_GO_C22        \
 440         0x00c0a0UL
 441 #define  DMAE_REG_GO_C23        \
 442         0x00c0a4UL
 443 #define  DMAE_REG_GO_C24        \
 444         0x00c0a8UL
 445 #define  DMAE_REG_GO_C25        \
 446         0x00c0acUL
 447 #define  DMAE_REG_GO_C26        \
 448         0x00c0b0UL
 449 #define  DMAE_REG_GO_C27        \
 450         0x00c0b4UL
 451 #define  DMAE_REG_GO_C28        \
 452         0x00c0b8UL
 453 #define  DMAE_REG_GO_C29        \
 454         0x00c0bcUL
 455 #define  DMAE_REG_GO_C30        \
 456         0x00c0c0UL
 457 #define  DMAE_REG_GO_C31        \
 458         0x00c0c4UL
 459 #define  DMAE_REG_CMD_MEM \
 460         0x00c800UL
 461 #define  QM_REG_MAXPQSIZETXSEL_0        \
 462         0x2f0440UL
 463 #define  QM_REG_SDMCMDREADY \
 464         0x2f1e10UL
 465 #define  QM_REG_SDMCMDADDR \
 466         0x2f1e04UL
 467 #define  QM_REG_SDMCMDDATALSB \
 468         0x2f1e08UL
 469 #define  QM_REG_SDMCMDDATAMSB \
 470         0x2f1e0cUL
 471 #define  QM_REG_SDMCMDGO        \
 472         0x2f1e14UL
 473 #define  QM_REG_RLPFCRD \
 474         0x2f4d80UL
 475 #define  QM_REG_RLPFINCVAL \
 476         0x2f4c80UL
 477 #define  QM_REG_RLGLBLCRD \
 478         0x2f4400UL
 479 #define  QM_REG_RLGLBLINCVAL \
 480         0x2f3400UL
 481 #define  IGU_REG_ATTENTION_ENABLE \
 482         0x18083cUL
 483 #define  IGU_REG_ATTN_MSG_ADDR_L        \
 484         0x180820UL
 485 #define  IGU_REG_ATTN_MSG_ADDR_H        \
 486         0x180824UL
 487 #define  MISC_REG_AEU_GENERAL_ATTN_0 \
 488         0x008400UL
 489 #define  CAU_REG_SB_ADDR_MEMORY \
 490         0x1c8000UL
 491 #define  CAU_REG_SB_VAR_MEMORY \
 492         0x1c6000UL
 493 #define  CAU_REG_PI_MEMORY \
 494         0x1d0000UL
 495 #define  IGU_REG_PF_CONFIGURATION \
 496         0x180800UL
 497 #define IGU_REG_VF_CONFIGURATION \
 498         0x180804UL
 499 #define  MISC_REG_AEU_ENABLE1_IGU_OUT_0 \
 500         0x00849cUL
 501 #define MISC_REG_AEU_AFTER_INVERT_1_IGU \
 502         0x0087b4UL
 503 #define  MISC_REG_AEU_MASK_ATTN_IGU \
 504         0x008494UL
 505 #define  IGU_REG_CLEANUP_STATUS_0 \
 506         0x180980UL
 507 #define  IGU_REG_CLEANUP_STATUS_1 \
 508         0x180a00UL
 509 #define  IGU_REG_CLEANUP_STATUS_2 \
 510         0x180a80UL
 511 #define  IGU_REG_CLEANUP_STATUS_3 \
 512         0x180b00UL
 513 #define  IGU_REG_CLEANUP_STATUS_4 \
 514         0x180b80UL
 515 #define  IGU_REG_COMMAND_REG_32LSB_DATA \
 516         0x180840UL
 517 #define  IGU_REG_COMMAND_REG_CTRL \
 518         0x180848UL
 519 #define  IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN      ( \
 520                 0x1 << 1)
 521 #define  IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN       ( \
 522                 0x1 << 0)
 523 #define  IGU_REG_MAPPING_MEMORY \
 524         0x184000UL
 525 #define IGU_REG_STATISTIC_NUM_VF_MSG_SENT \
 526         0x180408UL
 527 #define IGU_REG_WRITE_DONE_PENDING \
 528         0x180900UL
 529 #define  MISCS_REG_GENERIC_POR_0        \
 530         0x0096d4UL
 531 #define  MCP_REG_NVM_CFG4 \
 532         0xe0642cUL
 533 #define  MCP_REG_NVM_CFG4_FLASH_SIZE    ( \
 534                 0x7 << 0)
 535 #define  MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \
 536         0
 537 #define MCP_REG_CPU_STATE \
 538         0xe05004UL
 539 #define MCP_REG_CPU_EVENT_MASK \
 540         0xe05008UL
 541 #define PGLUE_B_REG_PF_BAR0_SIZE \
 542         0x2aae60UL
 543 #define PGLUE_B_REG_PF_BAR1_SIZE \
 544         0x2aae64UL
 545 #define PRS_REG_ENCAPSULATION_TYPE_EN   0x1f0730UL
 546 #define PRS_REG_GRE_PROTOCOL            0x1f0734UL
 547 #define PRS_REG_VXLAN_PORT              0x1f0738UL
 548 #define PRS_REG_OUTPUT_FORMAT_4_0       0x1f099cUL
 549 #define NIG_REG_ENC_TYPE_ENABLE         0x501058UL
 550
 551 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE             (0x1 << 0)
 552 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT       0
 553 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE              (0x1 << 1)
 554 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT        1
 555 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE                    (0x1 << 2)
 556 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT              2
 557
 558 #define NIG_REG_VXLAN_CTRL              0x50105cUL
 559 #define PBF_REG_VXLAN_PORT              0xd80518UL
 560 #define PBF_REG_NGE_PORT                0xd8051cUL
 561 #define PRS_REG_NGE_PORT                0x1f086cUL
 562 #define NIG_REG_NGE_PORT                0x508b38UL
 563
 564 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN      0x10090cUL
 565 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN       0x100910UL
 566 #define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN        0x100914UL
 567 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN       0x10092cUL
 568 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN      0x100930UL
 569
 570 #define NIG_REG_NGE_IP_ENABLE                   0x508b28UL
 571 #define NIG_REG_NGE_ETH_ENABLE                  0x508b2cUL
 572 #define NIG_REG_NGE_COMP_VER                    0x508b30UL
 573 #define PBF_REG_NGE_COMP_VER                    0xd80524UL
 574 #define PRS_REG_NGE_COMP_VER                    0x1f0878UL
 575
 576 #define QM_REG_WFQPFWEIGHT      0x2f4e80UL
 577 #define QM_REG_WFQVPWEIGHT      0x2fa000UL
 578
 579 #define PGLCS_REG_DBG_SELECT \
 580         0x001d14UL
 581 #define PGLCS_REG_DBG_DWORD_ENABLE \
 582         0x001d18UL
 583 #define PGLCS_REG_DBG_SHIFT \
 584         0x001d1cUL
 585 #define PGLCS_REG_DBG_FORCE_VALID \
 586         0x001d20UL
 587 #define PGLCS_REG_DBG_FORCE_FRAME \
 588         0x001d24UL
 589 #define MISC_REG_RESET_PL_PDA_VMAIN_1 \
 590         0x008070UL
 591 #define MISC_REG_RESET_PL_PDA_VMAIN_2 \
 592         0x008080UL
 593 #define MISC_REG_RESET_PL_PDA_VAUX \
 594         0x008090UL
 595 #define MISCS_REG_RESET_PL_UA \
 596         0x009050UL
 597 #define MISCS_REG_RESET_PL_HV \
 598         0x009060UL
 599 #define MISCS_REG_RESET_PL_HV_2 \
 600         0x009150UL
 601 #define DMAE_REG_DBG_SELECT \
 602         0x00c510UL
 603 #define DMAE_REG_DBG_DWORD_ENABLE \
 604         0x00c514UL
 605 #define DMAE_REG_DBG_SHIFT \
 606         0x00c518UL
 607 #define DMAE_REG_DBG_FORCE_VALID \
 608         0x00c51cUL
 609 #define DMAE_REG_DBG_FORCE_FRAME \
 610         0x00c520UL
 611 #define NCSI_REG_DBG_SELECT \
 612         0x040474UL
 613 #define NCSI_REG_DBG_DWORD_ENABLE \
 614         0x040478UL
 615 #define NCSI_REG_DBG_SHIFT \
 616         0x04047cUL
 617 #define NCSI_REG_DBG_FORCE_VALID \
 618         0x040480UL
 619 #define NCSI_REG_DBG_FORCE_FRAME \
 620         0x040484UL
 621 #define GRC_REG_DBG_SELECT \
 622         0x0500a4UL
 623 #define GRC_REG_DBG_DWORD_ENABLE \
 624         0x0500a8UL
 625 #define GRC_REG_DBG_SHIFT \
 626         0x0500acUL
 627 #define GRC_REG_DBG_FORCE_VALID \
 628         0x0500b0UL
 629 #define GRC_REG_DBG_FORCE_FRAME \
 630         0x0500b4UL
 631 #define UMAC_REG_DBG_SELECT \
 632         0x051094UL
 633 #define UMAC_REG_DBG_DWORD_ENABLE \
 634         0x051098UL
 635 #define UMAC_REG_DBG_SHIFT \
 636         0x05109cUL
 637 #define UMAC_REG_DBG_FORCE_VALID \
 638         0x0510a0UL
 639 #define UMAC_REG_DBG_FORCE_FRAME \
 640         0x0510a4UL
 641 #define MCP2_REG_DBG_SELECT \
 642         0x052400UL
 643 #define MCP2_REG_DBG_DWORD_ENABLE \
 644         0x052404UL
 645 #define MCP2_REG_DBG_SHIFT \
 646         0x052408UL
 647 #define MCP2_REG_DBG_FORCE_VALID \
 648         0x052440UL
 649 #define MCP2_REG_DBG_FORCE_FRAME \
 650         0x052444UL
 651 #define PCIE_REG_DBG_SELECT \
 652         0x0547e8UL
 653 #define PCIE_REG_DBG_DWORD_ENABLE \
 654         0x0547ecUL
 655 #define PCIE_REG_DBG_SHIFT \
 656         0x0547f0UL
 657 #define PCIE_REG_DBG_FORCE_VALID \
 658         0x0547f4UL
 659 #define PCIE_REG_DBG_FORCE_FRAME \
 660         0x0547f8UL
 661 #define DORQ_REG_DBG_SELECT \
 662         0x100ad0UL
 663 #define DORQ_REG_DBG_DWORD_ENABLE \
 664         0x100ad4UL
 665 #define DORQ_REG_DBG_SHIFT \
 666         0x100ad8UL
 667 #define DORQ_REG_DBG_FORCE_VALID \
 668         0x100adcUL
 669 #define DORQ_REG_DBG_FORCE_FRAME \
 670         0x100ae0UL
 671 #define IGU_REG_DBG_SELECT \
 672         0x181578UL
 673 #define IGU_REG_DBG_DWORD_ENABLE \
 674         0x18157cUL
 675 #define IGU_REG_DBG_SHIFT \
 676         0x181580UL
 677 #define IGU_REG_DBG_FORCE_VALID \
 678         0x181584UL
 679 #define IGU_REG_DBG_FORCE_FRAME \
 680         0x181588UL
 681 #define CAU_REG_DBG_SELECT \
 682         0x1c0ea8UL
 683 #define CAU_REG_DBG_DWORD_ENABLE \
 684         0x1c0eacUL
 685 #define CAU_REG_DBG_SHIFT \
 686         0x1c0eb0UL
 687 #define CAU_REG_DBG_FORCE_VALID \
 688         0x1c0eb4UL
 689 #define CAU_REG_DBG_FORCE_FRAME \
 690         0x1c0eb8UL
 691 #define PRS_REG_DBG_SELECT \
 692         0x1f0b6cUL
 693 #define PRS_REG_DBG_DWORD_ENABLE \
 694         0x1f0b70UL
 695 #define PRS_REG_DBG_SHIFT \
 696         0x1f0b74UL
 697 #define PRS_REG_DBG_FORCE_VALID \
 698         0x1f0ba0UL
 699 #define PRS_REG_DBG_FORCE_FRAME \
 700         0x1f0ba4UL
 701 #define CNIG_REG_DBG_SELECT_K2 \
 702         0x218254UL
 703 #define CNIG_REG_DBG_DWORD_ENABLE_K2 \
 704         0x218258UL
 705 #define CNIG_REG_DBG_SHIFT_K2 \
 706         0x21825cUL
 707 #define CNIG_REG_DBG_FORCE_VALID_K2 \
 708         0x218260UL
 709 #define CNIG_REG_DBG_FORCE_FRAME_K2 \
 710         0x218264UL
 711 #define PRM_REG_DBG_SELECT \
 712         0x2306a8UL
 713 #define PRM_REG_DBG_DWORD_ENABLE \
 714         0x2306acUL
 715 #define PRM_REG_DBG_SHIFT \
 716         0x2306b0UL
 717 #define PRM_REG_DBG_FORCE_VALID \
 718         0x2306b4UL
 719 #define PRM_REG_DBG_FORCE_FRAME \
 720         0x2306b8UL
 721 #define SRC_REG_DBG_SELECT \
 722         0x238700UL
 723 #define SRC_REG_DBG_DWORD_ENABLE \
 724         0x238704UL
 725 #define SRC_REG_DBG_SHIFT \
 726         0x238708UL
 727 #define SRC_REG_DBG_FORCE_VALID \
 728         0x23870cUL
 729 #define SRC_REG_DBG_FORCE_FRAME \
 730         0x238710UL
 731 #define RSS_REG_DBG_SELECT \
 732         0x238c4cUL
 733 #define RSS_REG_DBG_DWORD_ENABLE \
 734         0x238c50UL
 735 #define RSS_REG_DBG_SHIFT \
 736         0x238c54UL
 737 #define RSS_REG_DBG_FORCE_VALID \
 738         0x238c58UL
 739 #define RSS_REG_DBG_FORCE_FRAME \
 740         0x238c5cUL
 741 #define RPB_REG_DBG_SELECT \
 742         0x23c728UL
 743 #define RPB_REG_DBG_DWORD_ENABLE \
 744         0x23c72cUL
 745 #define RPB_REG_DBG_SHIFT \
 746         0x23c730UL
 747 #define RPB_REG_DBG_FORCE_VALID \
 748         0x23c734UL
 749 #define RPB_REG_DBG_FORCE_FRAME \
 750         0x23c738UL
 751 #define PSWRQ2_REG_DBG_SELECT \
 752         0x240100UL
 753 #define PSWRQ2_REG_DBG_DWORD_ENABLE \
 754         0x240104UL
 755 #define PSWRQ2_REG_DBG_SHIFT \
 756         0x240108UL
 757 #define PSWRQ2_REG_DBG_FORCE_VALID \
 758         0x24010cUL
 759 #define PSWRQ2_REG_DBG_FORCE_FRAME \
 760         0x240110UL
 761 #define PSWRQ_REG_DBG_SELECT \
 762         0x280020UL
 763 #define PSWRQ_REG_DBG_DWORD_ENABLE \
 764         0x280024UL
 765 #define PSWRQ_REG_DBG_SHIFT \
 766         0x280028UL
 767 #define PSWRQ_REG_DBG_FORCE_VALID \
 768         0x28002cUL
 769 #define PSWRQ_REG_DBG_FORCE_FRAME \
 770         0x280030UL
 771 #define PSWWR_REG_DBG_SELECT \
 772         0x29a084UL
 773 #define PSWWR_REG_DBG_DWORD_ENABLE \
 774         0x29a088UL
 775 #define PSWWR_REG_DBG_SHIFT \
 776         0x29a08cUL
 777 #define PSWWR_REG_DBG_FORCE_VALID \
 778         0x29a090UL
 779 #define PSWWR_REG_DBG_FORCE_FRAME \
 780         0x29a094UL
 781 #define PSWRD_REG_DBG_SELECT \
 782         0x29c040UL
 783 #define PSWRD_REG_DBG_DWORD_ENABLE \
 784         0x29c044UL
 785 #define PSWRD_REG_DBG_SHIFT \
 786         0x29c048UL
 787 #define PSWRD_REG_DBG_FORCE_VALID \
 788         0x29c04cUL
 789 #define PSWRD_REG_DBG_FORCE_FRAME \
 790         0x29c050UL
 791 #define PSWRD2_REG_DBG_SELECT \
 792         0x29d400UL
 793 #define PSWRD2_REG_DBG_DWORD_ENABLE \
 794         0x29d404UL
 795 #define PSWRD2_REG_DBG_SHIFT \
 796         0x29d408UL
 797 #define PSWRD2_REG_DBG_FORCE_VALID \
 798         0x29d40cUL
 799 #define PSWRD2_REG_DBG_FORCE_FRAME \
 800         0x29d410UL
 801 #define PSWHST2_REG_DBG_SELECT \
 802         0x29e058UL
 803 #define PSWHST2_REG_DBG_DWORD_ENABLE \
 804         0x29e05cUL
 805 #define PSWHST2_REG_DBG_SHIFT \
 806         0x29e060UL
 807 #define PSWHST2_REG_DBG_FORCE_VALID \
 808         0x29e064UL
 809 #define PSWHST2_REG_DBG_FORCE_FRAME \
 810         0x29e068UL
 811 #define PSWHST_REG_DBG_SELECT \
 812         0x2a0100UL
 813 #define PSWHST_REG_DBG_DWORD_ENABLE \
 814         0x2a0104UL
 815 #define PSWHST_REG_DBG_SHIFT \
 816         0x2a0108UL
 817 #define PSWHST_REG_DBG_FORCE_VALID \
 818         0x2a010cUL
 819 #define PSWHST_REG_DBG_FORCE_FRAME \
 820         0x2a0110UL
 821 #define PGLUE_B_REG_DBG_SELECT \
 822         0x2a8400UL
 823 #define PGLUE_B_REG_DBG_DWORD_ENABLE \
 824         0x2a8404UL
 825 #define PGLUE_B_REG_DBG_SHIFT \
 826         0x2a8408UL
 827 #define PGLUE_B_REG_DBG_FORCE_VALID \
 828         0x2a840cUL
 829 #define PGLUE_B_REG_DBG_FORCE_FRAME \
 830         0x2a8410UL
 831 #define TM_REG_DBG_SELECT \
 832         0x2c07a8UL
 833 #define TM_REG_DBG_DWORD_ENABLE \
 834         0x2c07acUL
 835 #define TM_REG_DBG_SHIFT \
 836         0x2c07b0UL
 837 #define TM_REG_DBG_FORCE_VALID \
 838         0x2c07b4UL
 839 #define TM_REG_DBG_FORCE_FRAME \
 840         0x2c07b8UL
 841 #define TCFC_REG_DBG_SELECT \
 842         0x2d0500UL
 843 #define TCFC_REG_DBG_DWORD_ENABLE \
 844         0x2d0504UL
 845 #define TCFC_REG_DBG_SHIFT \
 846         0x2d0508UL
 847 #define TCFC_REG_DBG_FORCE_VALID \
 848         0x2d050cUL
 849 #define TCFC_REG_DBG_FORCE_FRAME \
 850         0x2d0510UL
 851 #define CCFC_REG_DBG_SELECT \
 852         0x2e0500UL
 853 #define CCFC_REG_DBG_DWORD_ENABLE \
 854         0x2e0504UL
 855 #define CCFC_REG_DBG_SHIFT \
 856         0x2e0508UL
 857 #define CCFC_REG_DBG_FORCE_VALID \
 858         0x2e050cUL
 859 #define CCFC_REG_DBG_FORCE_FRAME \
 860         0x2e0510UL
 861 #define QM_REG_DBG_SELECT \
 862         0x2f2e74UL
 863 #define QM_REG_DBG_DWORD_ENABLE \
 864         0x2f2e78UL
 865 #define QM_REG_DBG_SHIFT \
 866         0x2f2e7cUL
 867 #define QM_REG_DBG_FORCE_VALID \
 868         0x2f2e80UL
 869 #define QM_REG_DBG_FORCE_FRAME \
 870         0x2f2e84UL
 871 #define RDIF_REG_DBG_SELECT \
 872         0x300500UL
 873 #define RDIF_REG_DBG_DWORD_ENABLE \
 874         0x300504UL
 875 #define RDIF_REG_DBG_SHIFT \
 876         0x300508UL
 877 #define RDIF_REG_DBG_FORCE_VALID \
 878         0x30050cUL
 879 #define RDIF_REG_DBG_FORCE_FRAME \
 880         0x300510UL
 881 #define TDIF_REG_DBG_SELECT \
 882         0x310500UL
 883 #define TDIF_REG_DBG_DWORD_ENABLE \
 884         0x310504UL
 885 #define TDIF_REG_DBG_SHIFT \
 886         0x310508UL
 887 #define TDIF_REG_DBG_FORCE_VALID \
 888         0x31050cUL
 889 #define TDIF_REG_DBG_FORCE_FRAME \
 890         0x310510UL
 891 #define BRB_REG_DBG_SELECT \
 892         0x340ed0UL
 893 #define BRB_REG_DBG_DWORD_ENABLE \
 894         0x340ed4UL
 895 #define BRB_REG_DBG_SHIFT \
 896         0x340ed8UL
 897 #define BRB_REG_DBG_FORCE_VALID \
 898         0x340edcUL
 899 #define BRB_REG_DBG_FORCE_FRAME \
 900         0x340ee0UL
 901 #define XYLD_REG_DBG_SELECT \
 902         0x4c1600UL
 903 #define XYLD_REG_DBG_DWORD_ENABLE \
 904         0x4c1604UL
 905 #define XYLD_REG_DBG_SHIFT \
 906         0x4c1608UL
 907 #define XYLD_REG_DBG_FORCE_VALID \
 908         0x4c160cUL
 909 #define XYLD_REG_DBG_FORCE_FRAME \
 910         0x4c1610UL
 911 #define YULD_REG_DBG_SELECT \
 912         0x4c9600UL
 913 #define YULD_REG_DBG_DWORD_ENABLE \
 914         0x4c9604UL
 915 #define YULD_REG_DBG_SHIFT \
 916         0x4c9608UL
 917 #define YULD_REG_DBG_FORCE_VALID \
 918         0x4c960cUL
 919 #define YULD_REG_DBG_FORCE_FRAME \
 920         0x4c9610UL
 921 #define TMLD_REG_DBG_SELECT \
 922         0x4d1600UL
 923 #define TMLD_REG_DBG_DWORD_ENABLE \
 924         0x4d1604UL
 925 #define TMLD_REG_DBG_SHIFT \
 926         0x4d1608UL
 927 #define TMLD_REG_DBG_FORCE_VALID \
 928         0x4d160cUL
 929 #define TMLD_REG_DBG_FORCE_FRAME \
 930         0x4d1610UL
 931 #define MULD_REG_DBG_SELECT \
 932         0x4e1600UL
 933 #define MULD_REG_DBG_DWORD_ENABLE \
 934         0x4e1604UL
 935 #define MULD_REG_DBG_SHIFT \
 936         0x4e1608UL
 937 #define MULD_REG_DBG_FORCE_VALID \
 938         0x4e160cUL
 939 #define MULD_REG_DBG_FORCE_FRAME \
 940         0x4e1610UL
 941 #define NIG_REG_DBG_SELECT \
 942         0x502140UL
 943 #define NIG_REG_DBG_DWORD_ENABLE \
 944         0x502144UL
 945 #define NIG_REG_DBG_SHIFT \
 946         0x502148UL
 947 #define NIG_REG_DBG_FORCE_VALID \
 948         0x50214cUL
 949 #define NIG_REG_DBG_FORCE_FRAME \
 950         0x502150UL
 951 #define BMB_REG_DBG_SELECT \
 952         0x540a7cUL
 953 #define BMB_REG_DBG_DWORD_ENABLE \
 954         0x540a80UL
 955 #define BMB_REG_DBG_SHIFT \
 956         0x540a84UL
 957 #define BMB_REG_DBG_FORCE_VALID \
 958         0x540a88UL
 959 #define BMB_REG_DBG_FORCE_FRAME \
 960         0x540a8cUL
 961 #define PTU_REG_DBG_SELECT \
 962         0x560100UL
 963 #define PTU_REG_DBG_DWORD_ENABLE \
 964         0x560104UL
 965 #define PTU_REG_DBG_SHIFT \
 966         0x560108UL
 967 #define PTU_REG_DBG_FORCE_VALID \
 968         0x56010cUL
 969 #define PTU_REG_DBG_FORCE_FRAME \
 970         0x560110UL
 971 #define CDU_REG_DBG_SELECT \
 972         0x580704UL
 973 #define CDU_REG_DBG_DWORD_ENABLE \
 974         0x580708UL
 975 #define CDU_REG_DBG_SHIFT \
 976         0x58070cUL
 977 #define CDU_REG_DBG_FORCE_VALID \
 978         0x580710UL
 979 #define CDU_REG_DBG_FORCE_FRAME \
 980         0x580714UL
 981 #define WOL_REG_DBG_SELECT \
 982         0x600140UL
 983 #define WOL_REG_DBG_DWORD_ENABLE \
 984         0x600144UL
 985 #define WOL_REG_DBG_SHIFT \
 986         0x600148UL
 987 #define WOL_REG_DBG_FORCE_VALID \
 988         0x60014cUL
 989 #define WOL_REG_DBG_FORCE_FRAME \
 990         0x600150UL
 991 #define BMBN_REG_DBG_SELECT \
 992         0x610140UL
 993 #define BMBN_REG_DBG_DWORD_ENABLE \
 994         0x610144UL
 995 #define BMBN_REG_DBG_SHIFT \
 996         0x610148UL
 997 #define BMBN_REG_DBG_FORCE_VALID \
 998         0x61014cUL
 999 #define BMBN_REG_DBG_FORCE_FRAME \
1000         0x610150UL
1001 #define NWM_REG_DBG_SELECT \
1002         0x8000ecUL
1003 #define NWM_REG_DBG_DWORD_ENABLE \
1004         0x8000f0UL
1005 #define NWM_REG_DBG_SHIFT \
1006         0x8000f4UL
1007 #define NWM_REG_DBG_FORCE_VALID \
1008         0x8000f8UL
1009 #define NWM_REG_DBG_FORCE_FRAME \
1010         0x8000fcUL
1011 #define PBF_REG_DBG_SELECT \
1012         0xd80060UL
1013 #define PBF_REG_DBG_DWORD_ENABLE \
1014         0xd80064UL
1015 #define PBF_REG_DBG_SHIFT \
1016         0xd80068UL
1017 #define PBF_REG_DBG_FORCE_VALID \
1018         0xd8006cUL
1019 #define PBF_REG_DBG_FORCE_FRAME \
1020         0xd80070UL
1021 #define PBF_PB1_REG_DBG_SELECT \
1022         0xda0728UL
1023 #define PBF_PB1_REG_DBG_DWORD_ENABLE \
1024         0xda072cUL
1025 #define PBF_PB1_REG_DBG_SHIFT \
1026         0xda0730UL
1027 #define PBF_PB1_REG_DBG_FORCE_VALID \
1028         0xda0734UL
1029 #define PBF_PB1_REG_DBG_FORCE_FRAME \
1030         0xda0738UL
1031 #define PBF_PB2_REG_DBG_SELECT \
1032         0xda4728UL
1033 #define PBF_PB2_REG_DBG_DWORD_ENABLE \
1034         0xda472cUL
1035 #define PBF_PB2_REG_DBG_SHIFT \
1036         0xda4730UL
1037 #define PBF_PB2_REG_DBG_FORCE_VALID \
1038         0xda4734UL
1039 #define PBF_PB2_REG_DBG_FORCE_FRAME \
1040         0xda4738UL
1041 #define BTB_REG_DBG_SELECT \
1042         0xdb08c8UL
1043 #define BTB_REG_DBG_DWORD_ENABLE \
1044         0xdb08ccUL
1045 #define BTB_REG_DBG_SHIFT \
1046         0xdb08d0UL
1047 #define BTB_REG_DBG_FORCE_VALID \
1048         0xdb08d4UL
1049 #define BTB_REG_DBG_FORCE_FRAME \
1050         0xdb08d8UL
1051 #define XSDM_REG_DBG_SELECT \
1052         0xf80e28UL
1053 #define XSDM_REG_DBG_DWORD_ENABLE \
1054         0xf80e2cUL
1055 #define XSDM_REG_DBG_SHIFT \
1056         0xf80e30UL
1057 #define XSDM_REG_DBG_FORCE_VALID \
1058         0xf80e34UL
1059 #define XSDM_REG_DBG_FORCE_FRAME \
1060         0xf80e38UL
1061 #define YSDM_REG_DBG_SELECT \
1062         0xf90e28UL
1063 #define YSDM_REG_DBG_DWORD_ENABLE \
1064         0xf90e2cUL
1065 #define YSDM_REG_DBG_SHIFT \
1066         0xf90e30UL
1067 #define YSDM_REG_DBG_FORCE_VALID \
1068         0xf90e34UL
1069 #define YSDM_REG_DBG_FORCE_FRAME \
1070         0xf90e38UL
1071 #define PSDM_REG_DBG_SELECT \
1072         0xfa0e28UL
1073 #define PSDM_REG_DBG_DWORD_ENABLE \
1074         0xfa0e2cUL
1075 #define PSDM_REG_DBG_SHIFT \
1076         0xfa0e30UL
1077 #define PSDM_REG_DBG_FORCE_VALID \
1078         0xfa0e34UL
1079 #define PSDM_REG_DBG_FORCE_FRAME \
1080         0xfa0e38UL
1081 #define TSDM_REG_DBG_SELECT \
1082         0xfb0e28UL
1083 #define TSDM_REG_DBG_DWORD_ENABLE \
1084         0xfb0e2cUL
1085 #define TSDM_REG_DBG_SHIFT \
1086         0xfb0e30UL
1087 #define TSDM_REG_DBG_FORCE_VALID \
1088         0xfb0e34UL
1089 #define TSDM_REG_DBG_FORCE_FRAME \
1090         0xfb0e38UL
1091 #define MSDM_REG_DBG_SELECT \
1092         0xfc0e28UL
1093 #define MSDM_REG_DBG_DWORD_ENABLE \
1094         0xfc0e2cUL
1095 #define MSDM_REG_DBG_SHIFT \
1096         0xfc0e30UL
1097 #define MSDM_REG_DBG_FORCE_VALID \
1098         0xfc0e34UL
1099 #define MSDM_REG_DBG_FORCE_FRAME \
1100         0xfc0e38UL
1101 #define USDM_REG_DBG_SELECT \
1102         0xfd0e28UL
1103 #define USDM_REG_DBG_DWORD_ENABLE \
1104         0xfd0e2cUL
1105 #define USDM_REG_DBG_SHIFT \
1106         0xfd0e30UL
1107 #define USDM_REG_DBG_FORCE_VALID \
1108         0xfd0e34UL
1109 #define USDM_REG_DBG_FORCE_FRAME \
1110         0xfd0e38UL
1111 #define XCM_REG_DBG_SELECT \
1112         0x1000040UL
1113 #define XCM_REG_DBG_DWORD_ENABLE \
1114         0x1000044UL
1115 #define XCM_REG_DBG_SHIFT \
1116         0x1000048UL
1117 #define XCM_REG_DBG_FORCE_VALID \
1118         0x100004cUL
1119 #define XCM_REG_DBG_FORCE_FRAME \
1120         0x1000050UL
1121 #define YCM_REG_DBG_SELECT \
1122         0x1080040UL
1123 #define YCM_REG_DBG_DWORD_ENABLE \
1124         0x1080044UL
1125 #define YCM_REG_DBG_SHIFT \
1126         0x1080048UL
1127 #define YCM_REG_DBG_FORCE_VALID \
1128         0x108004cUL
1129 #define YCM_REG_DBG_FORCE_FRAME \
1130         0x1080050UL
1131 #define PCM_REG_DBG_SELECT \
1132         0x1100040UL
1133 #define PCM_REG_DBG_DWORD_ENABLE \
1134         0x1100044UL
1135 #define PCM_REG_DBG_SHIFT \
1136         0x1100048UL
1137 #define PCM_REG_DBG_FORCE_VALID \
1138         0x110004cUL
1139 #define PCM_REG_DBG_FORCE_FRAME \
1140         0x1100050UL
1141 #define TCM_REG_DBG_SELECT \
1142         0x1180040UL
1143 #define TCM_REG_DBG_DWORD_ENABLE \
1144         0x1180044UL
1145 #define TCM_REG_DBG_SHIFT \
1146         0x1180048UL
1147 #define TCM_REG_DBG_FORCE_VALID \
1148         0x118004cUL
1149 #define TCM_REG_DBG_FORCE_FRAME \
1150         0x1180050UL
1151 #define MCM_REG_DBG_SELECT \
1152         0x1200040UL
1153 #define MCM_REG_DBG_DWORD_ENABLE \
1154         0x1200044UL
1155 #define MCM_REG_DBG_SHIFT \
1156         0x1200048UL
1157 #define MCM_REG_DBG_FORCE_VALID \
1158         0x120004cUL
1159 #define MCM_REG_DBG_FORCE_FRAME \
1160         0x1200050UL
1161 #define UCM_REG_DBG_SELECT \
1162         0x1280050UL
1163 #define UCM_REG_DBG_DWORD_ENABLE \
1164         0x1280054UL
1165 #define UCM_REG_DBG_SHIFT \
1166         0x1280058UL
1167 #define UCM_REG_DBG_FORCE_VALID \
1168         0x128005cUL
1169 #define UCM_REG_DBG_FORCE_FRAME \
1170         0x1280060UL
1171 #define XSEM_REG_DBG_SELECT \
1172         0x1401528UL
1173 #define XSEM_REG_DBG_DWORD_ENABLE \
1174         0x140152cUL
1175 #define XSEM_REG_DBG_SHIFT \
1176         0x1401530UL
1177 #define XSEM_REG_DBG_FORCE_VALID \
1178         0x1401534UL
1179 #define XSEM_REG_DBG_FORCE_FRAME \
1180         0x1401538UL
1181 #define YSEM_REG_DBG_SELECT \
1182         0x1501528UL
1183 #define YSEM_REG_DBG_DWORD_ENABLE \
1184         0x150152cUL
1185 #define YSEM_REG_DBG_SHIFT \
1186         0x1501530UL
1187 #define YSEM_REG_DBG_FORCE_VALID \
1188         0x1501534UL
1189 #define YSEM_REG_DBG_FORCE_FRAME \
1190         0x1501538UL
1191 #define PSEM_REG_DBG_SELECT \
1192         0x1601528UL
1193 #define PSEM_REG_DBG_DWORD_ENABLE \
1194         0x160152cUL
1195 #define PSEM_REG_DBG_SHIFT \
1196         0x1601530UL
1197 #define PSEM_REG_DBG_FORCE_VALID \
1198         0x1601534UL
1199 #define PSEM_REG_DBG_FORCE_FRAME \
1200         0x1601538UL
1201 #define TSEM_REG_DBG_SELECT \
1202         0x1701528UL
1203 #define TSEM_REG_DBG_DWORD_ENABLE \
1204         0x170152cUL
1205 #define TSEM_REG_DBG_SHIFT \
1206         0x1701530UL
1207 #define TSEM_REG_DBG_FORCE_VALID \
1208         0x1701534UL
1209 #define TSEM_REG_DBG_FORCE_FRAME \
1210         0x1701538UL
1211 #define MSEM_REG_DBG_SELECT \
1212         0x1801528UL
1213 #define MSEM_REG_DBG_DWORD_ENABLE \
1214         0x180152cUL
1215 #define MSEM_REG_DBG_SHIFT \
1216         0x1801530UL
1217 #define MSEM_REG_DBG_FORCE_VALID \
1218         0x1801534UL
1219 #define MSEM_REG_DBG_FORCE_FRAME \
1220         0x1801538UL
1221 #define USEM_REG_DBG_SELECT \
1222         0x1901528UL
1223 #define USEM_REG_DBG_DWORD_ENABLE \
1224         0x190152cUL
1225 #define USEM_REG_DBG_SHIFT \
1226         0x1901530UL
1227 #define USEM_REG_DBG_FORCE_VALID \
1228         0x1901534UL
1229 #define USEM_REG_DBG_FORCE_FRAME \
1230         0x1901538UL
1231 #define PCIE_REG_DBG_COMMON_SELECT \
1232         0x054398UL
1233 #define PCIE_REG_DBG_COMMON_DWORD_ENABLE \
1234         0x05439cUL
1235 #define PCIE_REG_DBG_COMMON_SHIFT \
1236         0x0543a0UL
1237 #define PCIE_REG_DBG_COMMON_FORCE_VALID \
1238         0x0543a4UL
1239 #define PCIE_REG_DBG_COMMON_FORCE_FRAME \
1240         0x0543a8UL
1241 #define MISC_REG_RESET_PL_UA \
1242         0x008050UL
1243 #define MISC_REG_RESET_PL_HV \
1244         0x008060UL
1245 #define XCM_REG_CTX_RBC_ACCS \
1246         0x1001800UL
1247 #define XCM_REG_AGG_CON_CTX \
1248         0x1001804UL
1249 #define XCM_REG_SM_CON_CTX \
1250         0x1001808UL
1251 #define YCM_REG_CTX_RBC_ACCS \
1252         0x1081800UL
1253 #define YCM_REG_AGG_CON_CTX \
1254         0x1081804UL
1255 #define YCM_REG_AGG_TASK_CTX \
1256         0x1081808UL
1257 #define YCM_REG_SM_CON_CTX \
1258         0x108180cUL
1259 #define YCM_REG_SM_TASK_CTX \
1260         0x1081810UL
1261 #define PCM_REG_CTX_RBC_ACCS \
1262         0x1101440UL
1263 #define PCM_REG_SM_CON_CTX \
1264         0x1101444UL
1265 #define TCM_REG_CTX_RBC_ACCS \
1266         0x11814c0UL
1267 #define TCM_REG_AGG_CON_CTX \
1268         0x11814c4UL
1269 #define TCM_REG_AGG_TASK_CTX \
1270         0x11814c8UL
1271 #define TCM_REG_SM_CON_CTX \
1272         0x11814ccUL
1273 #define TCM_REG_SM_TASK_CTX \
1274         0x11814d0UL
1275 #define MCM_REG_CTX_RBC_ACCS \
1276         0x1201800UL
1277 #define MCM_REG_AGG_CON_CTX \
1278         0x1201804UL
1279 #define MCM_REG_AGG_TASK_CTX \
1280         0x1201808UL
1281 #define MCM_REG_SM_CON_CTX \
1282         0x120180cUL
1283 #define MCM_REG_SM_TASK_CTX \
1284         0x1201810UL
1285 #define UCM_REG_CTX_RBC_ACCS \
1286         0x1281700UL
1287 #define UCM_REG_AGG_CON_CTX \
1288         0x1281704UL
1289 #define UCM_REG_AGG_TASK_CTX \
1290         0x1281708UL
1291 #define UCM_REG_SM_CON_CTX \
1292         0x128170cUL
1293 #define UCM_REG_SM_TASK_CTX \
1294         0x1281710UL
1295 #define XSEM_REG_SLOW_DBG_EMPTY \
1296         0x1401140UL
1297 #define XSEM_REG_SYNC_DBG_EMPTY \
1298         0x1401160UL
1299 #define XSEM_REG_SLOW_DBG_ACTIVE \
1300         0x1401400UL
1301 #define XSEM_REG_SLOW_DBG_MODE \
1302         0x1401404UL
1303 #define XSEM_REG_DBG_FRAME_MODE \
1304         0x1401408UL
1305 #define XSEM_REG_DBG_MODE1_CFG \
1306         0x1401420UL
1307 #define XSEM_REG_FAST_MEMORY \
1308         0x1440000UL
1309 #define YSEM_REG_SYNC_DBG_EMPTY \
1310         0x1501160UL
1311 #define YSEM_REG_SLOW_DBG_ACTIVE \
1312         0x1501400UL
1313 #define YSEM_REG_SLOW_DBG_MODE \
1314         0x1501404UL
1315 #define YSEM_REG_DBG_FRAME_MODE \
1316         0x1501408UL
1317 #define YSEM_REG_DBG_MODE1_CFG \
1318         0x1501420UL
1319 #define YSEM_REG_FAST_MEMORY \
1320         0x1540000UL
1321 #define PSEM_REG_SLOW_DBG_EMPTY \
1322         0x1601140UL
1323 #define PSEM_REG_SYNC_DBG_EMPTY \
1324         0x1601160UL
1325 #define PSEM_REG_SLOW_DBG_ACTIVE \
1326         0x1601400UL
1327 #define PSEM_REG_SLOW_DBG_MODE \
1328         0x1601404UL
1329 #define PSEM_REG_DBG_FRAME_MODE \
1330         0x1601408UL
1331 #define PSEM_REG_DBG_MODE1_CFG \
1332         0x1601420UL
1333 #define PSEM_REG_FAST_MEMORY \
1334         0x1640000UL
1335 #define TSEM_REG_SLOW_DBG_EMPTY \
1336         0x1701140UL
1337 #define TSEM_REG_SYNC_DBG_EMPTY \
1338         0x1701160UL
1339 #define TSEM_REG_SLOW_DBG_ACTIVE \
1340         0x1701400UL
1341 #define TSEM_REG_SLOW_DBG_MODE \
1342         0x1701404UL
1343 #define TSEM_REG_DBG_FRAME_MODE \
1344         0x1701408UL
1345 #define TSEM_REG_DBG_MODE1_CFG \
1346         0x1701420UL
1347 #define TSEM_REG_FAST_MEMORY \
1348         0x1740000UL
1349 #define MSEM_REG_SLOW_DBG_EMPTY \
1350         0x1801140UL
1351 #define MSEM_REG_SYNC_DBG_EMPTY \
1352         0x1801160UL
1353 #define MSEM_REG_SLOW_DBG_ACTIVE \
1354         0x1801400UL
1355 #define MSEM_REG_SLOW_DBG_MODE \
1356         0x1801404UL
1357 #define MSEM_REG_DBG_FRAME_MODE \
1358         0x1801408UL
1359 #define MSEM_REG_DBG_MODE1_CFG \
1360         0x1801420UL
1361 #define MSEM_REG_FAST_MEMORY \
1362         0x1840000UL
1363 #define USEM_REG_SLOW_DBG_EMPTY \
1364         0x1901140UL
1365 #define USEM_REG_SYNC_DBG_EMPTY \
1366         0x1901160UL
1367 #define USEM_REG_SLOW_DBG_ACTIVE \
1368         0x1901400UL
1369 #define USEM_REG_SLOW_DBG_MODE \
1370         0x1901404UL
1371 #define USEM_REG_DBG_FRAME_MODE \
1372         0x1901408UL
1373 #define USEM_REG_DBG_MODE1_CFG \
1374         0x1901420UL
1375 #define USEM_REG_FAST_MEMORY \
1376         0x1940000UL
1377 #define SEM_FAST_REG_INT_RAM \
1378         0x020000UL
1379 #define SEM_FAST_REG_INT_RAM_SIZE \
1380         20480
1381 #define GRC_REG_TRACE_FIFO_VALID_DATA \
1382         0x050064UL
1383 #define GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW \
1384         0x05040cUL
1385 #define GRC_REG_PROTECTION_OVERRIDE_WINDOW \
1386         0x050500UL
1387 #define IGU_REG_ERROR_HANDLING_MEMORY \
1388         0x181520UL
1389 #define MCP_REG_CPU_MODE \
1390         0xe05000UL
1391 #define MCP_REG_CPU_MODE_SOFT_HALT \
1392                 (0x1 << 10)
1393 #define BRB_REG_BIG_RAM_ADDRESS \
1394         0x340800UL
1395 #define BRB_REG_BIG_RAM_DATA \
1396         0x341500UL
1397 #define SEM_FAST_REG_STALL_0 \
1398         0x000488UL
1399 #define SEM_FAST_REG_STALLED \
1400         0x000494UL
1401 #define BTB_REG_BIG_RAM_ADDRESS \
1402         0xdb0800UL
1403 #define BTB_REG_BIG_RAM_DATA \
1404         0xdb0c00UL
1405 #define BMB_REG_BIG_RAM_ADDRESS \
1406         0x540800UL
1407 #define BMB_REG_BIG_RAM_DATA \
1408         0x540f00UL
1409 #define SEM_FAST_REG_STORM_REG_FILE \
1410         0x008000UL
1411 #define RSS_REG_RSS_RAM_ADDR \
1412         0x238c30UL
1413 #define MISCS_REG_BLOCK_256B_EN \
1414         0x009074UL
1415 #define MCP_REG_SCRATCH_SIZE \
1416         57344
1417 #define MCP_REG_CPU_REG_FILE \
1418         0xe05200UL
1419 #define MCP_REG_CPU_REG_FILE_SIZE \
1420         32
1421 #define DBG_REG_DEBUG_TARGET \
1422         0x01005cUL
1423 #define DBG_REG_FULL_MODE \
1424         0x010060UL
1425 #define DBG_REG_CALENDAR_OUT_DATA \
1426         0x010480UL
1427 #define GRC_REG_TRACE_FIFO \
1428         0x050068UL
1429 #define IGU_REG_ERROR_HANDLING_DATA_VALID \
1430         0x181530UL
1431 #define DBG_REG_DBG_BLOCK_ON \
1432         0x010454UL
1433 #define DBG_REG_FRAMING_MODE \
1434         0x010058UL
1435 #define SEM_FAST_REG_VFC_DATA_WR \
1436         0x000b40UL
1437 #define SEM_FAST_REG_VFC_ADDR \
1438         0x000b44UL
1439 #define SEM_FAST_REG_VFC_DATA_RD \
1440         0x000b48UL
1441 #define RSS_REG_RSS_RAM_DATA \
1442         0x238c20UL
1443 #define MISC_REG_BLOCK_256B_EN \
1444         0x008c14UL
1445 #define NWS_REG_NWS_CMU \
1446         0x720000UL
1447 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0 \
1448         0x000680UL
1449 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8 \
1450         0x000684UL
1451 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0 \
1452         0x0006c0UL
1453 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8 \
1454         0x0006c4UL
1455 #define MS_REG_MS_CMU \
1456         0x6a4000UL
1457 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130 \
1458         0x000208UL
1459 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132 \
1460         0x000210UL
1461 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131 \
1462         0x00020cUL
1463 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133 \
1464         0x000214UL
1465 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130 \
1466         0x000208UL
1467 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131 \
1468         0x00020cUL
1469 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132 \
1470         0x000210UL
1471 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133 \
1472         0x000214UL
1473 #define PHY_PCIE_REG_PHY0 \
1474         0x620000UL
1475 #define PHY_PCIE_REG_PHY1 \
1476         0x624000UL
1477 #define NIG_REG_ROCE_DUPLICATE_TO_HOST 0x5088f0UL
1478 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN 0x1f0968UL
1479 #define NIG_REG_LLH_ENG_CLS_ENG_ID_TBL 0x501b90UL
1480 #define DORQ_REG_PF_DPM_ENABLE 0x100510UL
1481 #define DORQ_REG_PF_ICID_BIT_SHIFT_NORM 0x100448UL
1482 #define DORQ_REG_PF_MIN_ADDR_REG1 0x100400UL
1483 #define DORQ_REG_PF_DPI_BIT_SHIFT 0x100450UL
1484 #endif