drivers/net/ethernet/qlogic/qed/qed_reg_addr.h

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015 QLogic Corporation
   3  *
   4  * This software is available under the terms of the GNU General Public License
   5  * (GPL) Version 2, available from the file COPYING in the main directory of
   6  * this source tree.
   7  */
   8
   9 #ifndef REG_ADDR_H
  10 #define REG_ADDR_H
  11
  12 #define  CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT \
  13         0
  14
  15 #define  CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE           ( \
  16                 0xfff << 0)
  17
  18 #define  CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \
  19         12
  20
  21 #define  CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE            ( \
  22                 0xfff << 12)
  23
  24 #define  CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \
  25         24
  26
  27 #define  CDU_REG_CID_ADDR_PARAMS_NCIB                   ( \
  28                 0xff << 24)
  29
  30 #define  XSDM_REG_OPERATION_GEN \
  31         0xf80408UL
  32 #define  NIG_REG_RX_BRB_OUT_EN \
  33         0x500e18UL
  34 #define  NIG_REG_STORM_OUT_EN \
  35         0x500e08UL
  36 #define  PSWRQ2_REG_L2P_VALIDATE_VFID \
  37         0x240c50UL
  38 #define  PGLUE_B_REG_USE_CLIENTID_IN_TAG        \
  39         0x2aae04UL
  40 #define  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER        \
  41         0x2aa16cUL
  42 #define  BAR0_MAP_REG_MSDM_RAM \
  43         0x1d00000UL
  44 #define  BAR0_MAP_REG_USDM_RAM \
  45         0x1d80000UL
  46 #define  BAR0_MAP_REG_PSDM_RAM \
  47         0x1f00000UL
  48 #define  BAR0_MAP_REG_TSDM_RAM \
  49         0x1c80000UL
  50 #define  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF \
  51         0x5011f4UL
  52 #define  PRS_REG_SEARCH_TCP \
  53         0x1f0400UL
  54 #define  PRS_REG_SEARCH_UDP \
  55         0x1f0404UL
  56 #define  PRS_REG_SEARCH_FCOE \
  57         0x1f0408UL
  58 #define  PRS_REG_SEARCH_ROCE \
  59         0x1f040cUL
  60 #define  PRS_REG_SEARCH_OPENFLOW        \
  61         0x1f0434UL
  62 #define  TM_REG_PF_ENABLE_CONN \
  63         0x2c043cUL
  64 #define  TM_REG_PF_ENABLE_TASK \
  65         0x2c0444UL
  66 #define  TM_REG_PF_SCAN_ACTIVE_CONN \
  67         0x2c04fcUL
  68 #define  TM_REG_PF_SCAN_ACTIVE_TASK \
  69         0x2c0500UL
  70 #define  IGU_REG_LEADING_EDGE_LATCH \
  71         0x18082cUL
  72 #define  IGU_REG_TRAILING_EDGE_LATCH \
  73         0x180830UL
  74 #define  QM_REG_USG_CNT_PF_TX \
  75         0x2f2eacUL
  76 #define  QM_REG_USG_CNT_PF_OTHER        \
  77         0x2f2eb0UL
  78 #define  DORQ_REG_PF_DB_ENABLE \
  79         0x100508UL
  80 #define  QM_REG_PF_EN \
  81         0x2f2ea4UL
  82 #define  TCFC_REG_STRONG_ENABLE_PF \
  83         0x2d0708UL
  84 #define  CCFC_REG_STRONG_ENABLE_PF \
  85         0x2e0708UL
  86 #define  PGLUE_B_REG_PGL_ADDR_88_F0 \
  87         0x2aa404UL
  88 #define  PGLUE_B_REG_PGL_ADDR_8C_F0 \
  89         0x2aa408UL
  90 #define  PGLUE_B_REG_PGL_ADDR_90_F0 \
  91         0x2aa40cUL
  92 #define  PGLUE_B_REG_PGL_ADDR_94_F0 \
  93         0x2aa410UL
  94 #define  PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR \
  95         0x2aa138UL
  96 #define  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \
  97         0x2aa174UL
  98 #define  MISC_REG_GEN_PURP_CR0 \
  99         0x008c80UL
 100 #define  MCP_REG_SCRATCH        \
 101         0xe20000UL
 102 #define  CNIG_REG_NW_PORT_MODE_BB_B0 \
 103         0x218200UL
 104 #define  MISCS_REG_CHIP_NUM \
 105         0x00976cUL
 106 #define  MISCS_REG_CHIP_REV \
 107         0x009770UL
 108 #define  MISCS_REG_CMT_ENABLED_FOR_PAIR \
 109         0x00971cUL
 110 #define  MISCS_REG_CHIP_TEST_REG        \
 111         0x009778UL
 112 #define  MISCS_REG_CHIP_METAL \
 113         0x009774UL
 114 #define  BRB_REG_HEADER_SIZE \
 115         0x340804UL
 116 #define  BTB_REG_HEADER_SIZE \
 117         0xdb0804UL
 118 #define  CAU_REG_LONG_TIMEOUT_THRESHOLD \
 119         0x1c0708UL
 120 #define  CCFC_REG_ACTIVITY_COUNTER \
 121         0x2e8800UL
 122 #define  CDU_REG_CID_ADDR_PARAMS        \
 123         0x580900UL
 124 #define  DBG_REG_CLIENT_ENABLE \
 125         0x010004UL
 126 #define  DMAE_REG_INIT \
 127         0x00c000UL
 128 #define  DORQ_REG_IFEN \
 129         0x100040UL
 130 #define DORQ_REG_DB_DROP_REASON \
 131         0x100a2cUL
 132 #define DORQ_REG_DB_DROP_DETAILS \
 133         0x100a24UL
 134 #define DORQ_REG_DB_DROP_DETAILS_ADDRESS \
 135         0x100a1cUL
 136 #define  GRC_REG_TIMEOUT_EN \
 137         0x050404UL
 138 #define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID \
 139         0x050054UL
 140 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 \
 141         0x05004cUL
 142 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1 \
 143         0x050050UL
 144 #define  IGU_REG_BLOCK_CONFIGURATION \
 145         0x180040UL
 146 #define  MCM_REG_INIT \
 147         0x1200000UL
 148 #define  MCP2_REG_DBG_DWORD_ENABLE \
 149         0x052404UL
 150 #define  MISC_REG_PORT_MODE \
 151         0x008c00UL
 152 #define  MISCS_REG_CLK_100G_MODE        \
 153         0x009070UL
 154 #define  MSDM_REG_ENABLE_IN1 \
 155         0xfc0004UL
 156 #define  MSEM_REG_ENABLE_IN \
 157         0x1800004UL
 158 #define  NIG_REG_CM_HDR \
 159         0x500840UL
 160 #define  NCSI_REG_CONFIG        \
 161         0x040200UL
 162 #define  PBF_REG_INIT \
 163         0xd80000UL
 164 #define  PTU_REG_ATC_INIT_ARRAY \
 165         0x560000UL
 166 #define  PCM_REG_INIT \
 167         0x1100000UL
 168 #define  PGLUE_B_REG_ADMIN_PER_PF_REGION        \
 169         0x2a9000UL
 170 #define PGLUE_B_REG_TX_ERR_WR_DETAILS2 \
 171         0x2aa150UL
 172 #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 \
 173         0x2aa144UL
 174 #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 \
 175         0x2aa148UL
 176 #define PGLUE_B_REG_TX_ERR_WR_DETAILS \
 177         0x2aa14cUL
 178 #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 \
 179         0x2aa154UL
 180 #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 \
 181         0x2aa158UL
 182 #define PGLUE_B_REG_TX_ERR_RD_DETAILS \
 183         0x2aa15cUL
 184 #define PGLUE_B_REG_TX_ERR_RD_DETAILS2 \
 185         0x2aa160UL
 186 #define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL \
 187         0x2aa164UL
 188 #define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS \
 189         0x2aa54cUL
 190 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0 \
 191         0x2aa544UL
 192 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32 \
 193         0x2aa548UL
 194 #define PGLUE_B_REG_VF_ILT_ERR_ADD_31_0 \
 195         0x2aae74UL
 196 #define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 \
 197         0x2aae78UL
 198 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS \
 199         0x2aae7cUL
 200 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS2 \
 201         0x2aae80UL
 202 #define PGLUE_B_REG_LATCHED_ERRORS_CLR \
 203         0x2aa3bcUL
 204 #define  PRM_REG_DISABLE_PRM \
 205         0x230000UL
 206 #define  PRS_REG_SOFT_RST \
 207         0x1f0000UL
 208 #define  PSDM_REG_ENABLE_IN1 \
 209         0xfa0004UL
 210 #define  PSEM_REG_ENABLE_IN \
 211         0x1600004UL
 212 #define  PSWRQ_REG_DBG_SELECT \
 213         0x280020UL
 214 #define  PSWRQ2_REG_CDUT_P_SIZE \
 215         0x24000cUL
 216 #define  PSWHST_REG_DISCARD_INTERNAL_WRITES \
 217         0x2a0040UL
 218 #define  PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \
 219         0x29e050UL
 220 #define PSWHST_REG_INCORRECT_ACCESS_VALID \
 221         0x2a0070UL
 222 #define PSWHST_REG_INCORRECT_ACCESS_ADDRESS \
 223         0x2a0074UL
 224 #define PSWHST_REG_INCORRECT_ACCESS_DATA \
 225         0x2a0068UL
 226 #define PSWHST_REG_INCORRECT_ACCESS_LENGTH \
 227         0x2a006cUL
 228 #define  PSWRD_REG_DBG_SELECT \
 229         0x29c040UL
 230 #define  PSWRD2_REG_CONF11 \
 231         0x29d064UL
 232 #define  PSWWR_REG_USDM_FULL_TH \
 233         0x29a040UL
 234 #define  PSWWR2_REG_CDU_FULL_TH2        \
 235         0x29b040UL
 236 #define  QM_REG_MAXPQSIZE_0 \
 237         0x2f0434UL
 238 #define  RSS_REG_RSS_INIT_EN \
 239         0x238804UL
 240 #define  RDIF_REG_STOP_ON_ERROR \
 241         0x300040UL
 242 #define  SRC_REG_SOFT_RST \
 243         0x23874cUL
 244 #define  TCFC_REG_ACTIVITY_COUNTER \
 245         0x2d8800UL
 246 #define  TCM_REG_INIT \
 247         0x1180000UL
 248 #define  TM_REG_PXP_READ_DATA_FIFO_INIT \
 249         0x2c0014UL
 250 #define  TSDM_REG_ENABLE_IN1 \
 251         0xfb0004UL
 252 #define  TSEM_REG_ENABLE_IN \
 253         0x1700004UL
 254 #define  TDIF_REG_STOP_ON_ERROR \
 255         0x310040UL
 256 #define  UCM_REG_INIT \
 257         0x1280000UL
 258 #define  UMAC_REG_IPG_HD_BKP_CNTL_BB_B0 \
 259         0x051004UL
 260 #define  USDM_REG_ENABLE_IN1 \
 261         0xfd0004UL
 262 #define  USEM_REG_ENABLE_IN \
 263         0x1900004UL
 264 #define  XCM_REG_INIT \
 265         0x1000000UL
 266 #define  XSDM_REG_ENABLE_IN1 \
 267         0xf80004UL
 268 #define  XSEM_REG_ENABLE_IN \
 269         0x1400004UL
 270 #define  YCM_REG_INIT \
 271         0x1080000UL
 272 #define  YSDM_REG_ENABLE_IN1 \
 273         0xf90004UL
 274 #define  YSEM_REG_ENABLE_IN \
 275         0x1500004UL
 276 #define  XYLD_REG_SCBD_STRICT_PRIO \
 277         0x4c0000UL
 278 #define  TMLD_REG_SCBD_STRICT_PRIO \
 279         0x4d0000UL
 280 #define  MULD_REG_SCBD_STRICT_PRIO \
 281         0x4e0000UL
 282 #define  YULD_REG_SCBD_STRICT_PRIO \
 283         0x4c8000UL
 284 #define  MISC_REG_SHARED_MEM_ADDR \
 285         0x008c20UL
 286 #define  DMAE_REG_GO_C0 \
 287         0x00c048UL
 288 #define  DMAE_REG_GO_C1 \
 289         0x00c04cUL
 290 #define  DMAE_REG_GO_C2 \
 291         0x00c050UL
 292 #define  DMAE_REG_GO_C3 \
 293         0x00c054UL
 294 #define  DMAE_REG_GO_C4 \
 295         0x00c058UL
 296 #define  DMAE_REG_GO_C5 \
 297         0x00c05cUL
 298 #define  DMAE_REG_GO_C6 \
 299         0x00c060UL
 300 #define  DMAE_REG_GO_C7 \
 301         0x00c064UL
 302 #define  DMAE_REG_GO_C8 \
 303         0x00c068UL
 304 #define  DMAE_REG_GO_C9 \
 305         0x00c06cUL
 306 #define  DMAE_REG_GO_C10        \
 307         0x00c070UL
 308 #define  DMAE_REG_GO_C11        \
 309         0x00c074UL
 310 #define  DMAE_REG_GO_C12        \
 311         0x00c078UL
 312 #define  DMAE_REG_GO_C13        \
 313         0x00c07cUL
 314 #define  DMAE_REG_GO_C14        \
 315         0x00c080UL
 316 #define  DMAE_REG_GO_C15        \
 317         0x00c084UL
 318 #define  DMAE_REG_GO_C16        \
 319         0x00c088UL
 320 #define  DMAE_REG_GO_C17        \
 321         0x00c08cUL
 322 #define  DMAE_REG_GO_C18        \
 323         0x00c090UL
 324 #define  DMAE_REG_GO_C19        \
 325         0x00c094UL
 326 #define  DMAE_REG_GO_C20        \
 327         0x00c098UL
 328 #define  DMAE_REG_GO_C21        \
 329         0x00c09cUL
 330 #define  DMAE_REG_GO_C22        \
 331         0x00c0a0UL
 332 #define  DMAE_REG_GO_C23        \
 333         0x00c0a4UL
 334 #define  DMAE_REG_GO_C24        \
 335         0x00c0a8UL
 336 #define  DMAE_REG_GO_C25        \
 337         0x00c0acUL
 338 #define  DMAE_REG_GO_C26        \
 339         0x00c0b0UL
 340 #define  DMAE_REG_GO_C27        \
 341         0x00c0b4UL
 342 #define  DMAE_REG_GO_C28        \
 343         0x00c0b8UL
 344 #define  DMAE_REG_GO_C29        \
 345         0x00c0bcUL
 346 #define  DMAE_REG_GO_C30        \
 347         0x00c0c0UL
 348 #define  DMAE_REG_GO_C31        \
 349         0x00c0c4UL
 350 #define  DMAE_REG_CMD_MEM \
 351         0x00c800UL
 352 #define  QM_REG_MAXPQSIZETXSEL_0        \
 353         0x2f0440UL
 354 #define  QM_REG_SDMCMDREADY \
 355         0x2f1e10UL
 356 #define  QM_REG_SDMCMDADDR \
 357         0x2f1e04UL
 358 #define  QM_REG_SDMCMDDATALSB \
 359         0x2f1e08UL
 360 #define  QM_REG_SDMCMDDATAMSB \
 361         0x2f1e0cUL
 362 #define  QM_REG_SDMCMDGO        \
 363         0x2f1e14UL
 364 #define  QM_REG_RLPFCRD \
 365         0x2f4d80UL
 366 #define  QM_REG_RLPFINCVAL \
 367         0x2f4c80UL
 368 #define  QM_REG_RLGLBLCRD \
 369         0x2f4400UL
 370 #define  QM_REG_RLGLBLINCVAL \
 371         0x2f3400UL
 372 #define  IGU_REG_ATTENTION_ENABLE \
 373         0x18083cUL
 374 #define  IGU_REG_ATTN_MSG_ADDR_L        \
 375         0x180820UL
 376 #define  IGU_REG_ATTN_MSG_ADDR_H        \
 377         0x180824UL
 378 #define  MISC_REG_AEU_GENERAL_ATTN_0 \
 379         0x008400UL
 380 #define  CAU_REG_SB_ADDR_MEMORY \
 381         0x1c8000UL
 382 #define  CAU_REG_SB_VAR_MEMORY \
 383         0x1c6000UL
 384 #define  CAU_REG_PI_MEMORY \
 385         0x1d0000UL
 386 #define  IGU_REG_PF_CONFIGURATION \
 387         0x180800UL
 388 #define  MISC_REG_AEU_ENABLE1_IGU_OUT_0 \
 389         0x00849cUL
 390 #define MISC_REG_AEU_AFTER_INVERT_1_IGU \
 391         0x0087b4UL
 392 #define  MISC_REG_AEU_MASK_ATTN_IGU \
 393         0x008494UL
 394 #define  IGU_REG_CLEANUP_STATUS_0 \
 395         0x180980UL
 396 #define  IGU_REG_CLEANUP_STATUS_1 \
 397         0x180a00UL
 398 #define  IGU_REG_CLEANUP_STATUS_2 \
 399         0x180a80UL
 400 #define  IGU_REG_CLEANUP_STATUS_3 \
 401         0x180b00UL
 402 #define  IGU_REG_CLEANUP_STATUS_4 \
 403         0x180b80UL
 404 #define  IGU_REG_COMMAND_REG_32LSB_DATA \
 405         0x180840UL
 406 #define  IGU_REG_COMMAND_REG_CTRL \
 407         0x180848UL
 408 #define  IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN      ( \
 409                 0x1 << 1)
 410 #define  IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN       ( \
 411                 0x1 << 0)
 412 #define  IGU_REG_MAPPING_MEMORY \
 413         0x184000UL
 414 #define  MISCS_REG_GENERIC_POR_0        \
 415         0x0096d4UL
 416 #define  MCP_REG_NVM_CFG4 \
 417         0xe0642cUL
 418 #define  MCP_REG_NVM_CFG4_FLASH_SIZE    ( \
 419                 0x7 << 0)
 420 #define  MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \
 421         0
 422 #define MCP_REG_CPU_STATE \
 423         0xe05004UL
 424 #define MCP_REG_CPU_EVENT_MASK \
 425         0xe05008UL
 426 #define PGLUE_B_REG_PF_BAR0_SIZE \
 427         0x2aae60UL
 428 #define PGLUE_B_REG_PF_BAR1_SIZE \
 429         0x2aae64UL
 430 #define PRS_REG_ENCAPSULATION_TYPE_EN   0x1f0730UL
 431 #define PRS_REG_GRE_PROTOCOL            0x1f0734UL
 432 #define PRS_REG_VXLAN_PORT              0x1f0738UL
 433 #define PRS_REG_OUTPUT_FORMAT_4_0       0x1f099cUL
 434 #define NIG_REG_ENC_TYPE_ENABLE         0x501058UL
 435
 436 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE             (0x1 << 0)
 437 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT       0
 438 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE              (0x1 << 1)
 439 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT        1
 440 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE                    (0x1 << 2)
 441 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT              2
 442
 443 #define NIG_REG_VXLAN_PORT              0x50105cUL
 444 #define PBF_REG_VXLAN_PORT              0xd80518UL
 445 #define PBF_REG_NGE_PORT                0xd8051cUL
 446 #define PRS_REG_NGE_PORT                0x1f086cUL
 447 #define NIG_REG_NGE_PORT                0x508b38UL
 448
 449 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN      0x10090cUL
 450 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN       0x100910UL
 451 #define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN        0x100914UL
 452 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN       0x10092cUL
 453 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN      0x100930UL
 454
 455 #define NIG_REG_NGE_IP_ENABLE                   0x508b28UL
 456 #define NIG_REG_NGE_ETH_ENABLE                  0x508b2cUL
 457 #define NIG_REG_NGE_COMP_VER                    0x508b30UL
 458 #define PBF_REG_NGE_COMP_VER                    0xd80524UL
 459 #define PRS_REG_NGE_COMP_VER                    0x1f0878UL
 460
 461 #define QM_REG_WFQPFWEIGHT      0x2f4e80UL
 462 #define QM_REG_WFQVPWEIGHT      0x2fa000UL
 463 #endif