drivers/net/ethernet/qlogic/qed/qed_sp_commands.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015 QLogic Corporation
   3  *
   4  * This software is available under the terms of the GNU General Public License
   5  * (GPL) Version 2, available from the file COPYING in the main directory of
   6  * this source tree.
   7  */
   8
   9 #include <linux/types.h>
  10 #include <asm/byteorder.h>
  11 #include <linux/bitops.h>
  12 #include <linux/errno.h>
  13 #include <linux/kernel.h>
  14 #include <linux/string.h>
  15 #include "qed.h"
  16 #include <linux/qed/qed_chain.h>
  17 #include "qed_cxt.h"
  18 #include "qed_hsi.h"
  19 #include "qed_hw.h"
  20 #include "qed_int.h"
  21 #include "qed_reg_addr.h"
  22 #include "qed_sp.h"
  23 #include "qed_sriov.h"
  24
  25 int qed_sp_init_request(struct qed_hwfn *p_hwfn,
  26                         struct qed_spq_entry **pp_ent,
  27                         u8 cmd,
  28                         u8 protocol,
  29                         struct qed_sp_init_data *p_data)
  30 {
  31         u32 opaque_cid = p_data->opaque_fid << 16 | p_data->cid;
  32         struct qed_spq_entry *p_ent = NULL;
  33         int rc;
  34
  35         if (!pp_ent)
  36                 return -ENOMEM;
  37
  38         rc = qed_spq_get_entry(p_hwfn, pp_ent);
  39
  40         if (rc != 0)
  41                 return rc;
  42
  43         p_ent = *pp_ent;
  44
  45         p_ent->elem.hdr.cid             = cpu_to_le32(opaque_cid);
  46         p_ent->elem.hdr.cmd_id          = cmd;
  47         p_ent->elem.hdr.protocol_id     = protocol;
  48
  49         p_ent->priority         = QED_SPQ_PRIORITY_NORMAL;
  50         p_ent->comp_mode        = p_data->comp_mode;
  51         p_ent->comp_done.done   = 0;
  52
  53         switch (p_ent->comp_mode) {
  54         case QED_SPQ_MODE_EBLOCK:
  55                 p_ent->comp_cb.cookie = &p_ent->comp_done;
  56                 break;
  57
  58         case QED_SPQ_MODE_BLOCK:
  59                 if (!p_data->p_comp_data)
  60                         return -EINVAL;
  61
  62                 p_ent->comp_cb.cookie = p_data->p_comp_data->cookie;
  63                 break;
  64
  65         case QED_SPQ_MODE_CB:
  66                 if (!p_data->p_comp_data)
  67                         p_ent->comp_cb.function = NULL;
  68                 else
  69                         p_ent->comp_cb = *p_data->p_comp_data;
  70                 break;
  71
  72         default:
  73                 DP_NOTICE(p_hwfn, "Unknown SPQE completion mode %d\n",
  74                           p_ent->comp_mode);
  75                 return -EINVAL;
  76         }
  77
  78         DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
  79                    "Initialized: CID %08x cmd %02x protocol %02x data_addr %lu comp_mode [%s]\n",
  80                    opaque_cid, cmd, protocol,
  81                    (unsigned long)&p_ent->ramrod,
  82                    D_TRINE(p_ent->comp_mode, QED_SPQ_MODE_EBLOCK,
  83                            QED_SPQ_MODE_BLOCK, "MODE_EBLOCK", "MODE_BLOCK",
  84                            "MODE_CB"));
  85
  86         memset(&p_ent->ramrod, 0, sizeof(p_ent->ramrod));
  87
  88         return 0;
  89 }
  90
  91 static enum tunnel_clss qed_tunn_get_clss_type(u8 type)
  92 {
  93         switch (type) {
  94         case QED_TUNN_CLSS_MAC_VLAN:
  95                 return TUNNEL_CLSS_MAC_VLAN;
  96         case QED_TUNN_CLSS_MAC_VNI:
  97                 return TUNNEL_CLSS_MAC_VNI;
  98         case QED_TUNN_CLSS_INNER_MAC_VLAN:
  99                 return TUNNEL_CLSS_INNER_MAC_VLAN;
 100         case QED_TUNN_CLSS_INNER_MAC_VNI:
 101                 return TUNNEL_CLSS_INNER_MAC_VNI;
 102         default:
 103                 return TUNNEL_CLSS_MAC_VLAN;
 104         }
 105 }
 106
 107 static void
 108 qed_tunn_set_pf_fix_tunn_mode(struct qed_hwfn *p_hwfn,
 109                               struct qed_tunn_update_params *p_src,
 110                               struct pf_update_tunnel_config *p_tunn_cfg)
 111 {
 112         unsigned long cached_tunn_mode = p_hwfn->cdev->tunn_mode;
 113         unsigned long update_mask = p_src->tunn_mode_update_mask;
 114         unsigned long tunn_mode = p_src->tunn_mode;
 115         unsigned long new_tunn_mode = 0;
 116
 117         if (test_bit(QED_MODE_L2GRE_TUNN, &update_mask)) {
 118                 if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode))
 119                         __set_bit(QED_MODE_L2GRE_TUNN, &new_tunn_mode);
 120         } else {
 121                 if (test_bit(QED_MODE_L2GRE_TUNN, &cached_tunn_mode))
 122                         __set_bit(QED_MODE_L2GRE_TUNN, &new_tunn_mode);
 123         }
 124
 125         if (test_bit(QED_MODE_IPGRE_TUNN, &update_mask)) {
 126                 if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode))
 127                         __set_bit(QED_MODE_IPGRE_TUNN, &new_tunn_mode);
 128         } else {
 129                 if (test_bit(QED_MODE_IPGRE_TUNN, &cached_tunn_mode))
 130                         __set_bit(QED_MODE_IPGRE_TUNN, &new_tunn_mode);
 131         }
 132
 133         if (test_bit(QED_MODE_VXLAN_TUNN, &update_mask)) {
 134                 if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode))
 135                         __set_bit(QED_MODE_VXLAN_TUNN, &new_tunn_mode);
 136         } else {
 137                 if (test_bit(QED_MODE_VXLAN_TUNN, &cached_tunn_mode))
 138                         __set_bit(QED_MODE_VXLAN_TUNN, &new_tunn_mode);
 139         }
 140
 141         if (p_src->update_geneve_udp_port) {
 142                 p_tunn_cfg->set_geneve_udp_port_flg = 1;
 143                 p_tunn_cfg->geneve_udp_port =
 144                                 cpu_to_le16(p_src->geneve_udp_port);
 145         }
 146
 147         if (test_bit(QED_MODE_L2GENEVE_TUNN, &update_mask)) {
 148                 if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode))
 149                         __set_bit(QED_MODE_L2GENEVE_TUNN, &new_tunn_mode);
 150         } else {
 151                 if (test_bit(QED_MODE_L2GENEVE_TUNN, &cached_tunn_mode))
 152                         __set_bit(QED_MODE_L2GENEVE_TUNN, &new_tunn_mode);
 153         }
 154
 155         if (test_bit(QED_MODE_IPGENEVE_TUNN, &update_mask)) {
 156                 if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode))
 157                         __set_bit(QED_MODE_IPGENEVE_TUNN, &new_tunn_mode);
 158         } else {
 159                 if (test_bit(QED_MODE_IPGENEVE_TUNN, &cached_tunn_mode))
 160                         __set_bit(QED_MODE_IPGENEVE_TUNN, &new_tunn_mode);
 161         }
 162
 163         p_src->tunn_mode = new_tunn_mode;
 164 }
 165
 166 static void
 167 qed_tunn_set_pf_update_params(struct qed_hwfn *p_hwfn,
 168                               struct qed_tunn_update_params *p_src,
 169                               struct pf_update_tunnel_config *p_tunn_cfg)
 170 {
 171         unsigned long tunn_mode = p_src->tunn_mode;
 172         enum tunnel_clss type;
 173
 174         qed_tunn_set_pf_fix_tunn_mode(p_hwfn, p_src, p_tunn_cfg);
 175         p_tunn_cfg->update_rx_pf_clss = p_src->update_rx_pf_clss;
 176         p_tunn_cfg->update_tx_pf_clss = p_src->update_tx_pf_clss;
 177
 178         type = qed_tunn_get_clss_type(p_src->tunn_clss_vxlan);
 179         p_tunn_cfg->tunnel_clss_vxlan  = type;
 180
 181         type = qed_tunn_get_clss_type(p_src->tunn_clss_l2gre);
 182         p_tunn_cfg->tunnel_clss_l2gre = type;
 183
 184         type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgre);
 185         p_tunn_cfg->tunnel_clss_ipgre = type;
 186
 187         if (p_src->update_vxlan_udp_port) {
 188                 p_tunn_cfg->set_vxlan_udp_port_flg = 1;
 189                 p_tunn_cfg->vxlan_udp_port = cpu_to_le16(p_src->vxlan_udp_port);
 190         }
 191
 192         if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode))
 193                 p_tunn_cfg->tx_enable_l2gre = 1;
 194
 195         if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode))
 196                 p_tunn_cfg->tx_enable_ipgre = 1;
 197
 198         if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode))
 199                 p_tunn_cfg->tx_enable_vxlan = 1;
 200
 201         if (p_src->update_geneve_udp_port) {
 202                 p_tunn_cfg->set_geneve_udp_port_flg = 1;
 203                 p_tunn_cfg->geneve_udp_port =
 204                                 cpu_to_le16(p_src->geneve_udp_port);
 205         }
 206
 207         if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode))
 208                 p_tunn_cfg->tx_enable_l2geneve = 1;
 209
 210         if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode))
 211                 p_tunn_cfg->tx_enable_ipgeneve = 1;
 212
 213         type = qed_tunn_get_clss_type(p_src->tunn_clss_l2geneve);
 214         p_tunn_cfg->tunnel_clss_l2geneve = type;
 215
 216         type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgeneve);
 217         p_tunn_cfg->tunnel_clss_ipgeneve = type;
 218 }
 219
 220 static void qed_set_hw_tunn_mode(struct qed_hwfn *p_hwfn,
 221                                  struct qed_ptt *p_ptt,
 222                                  unsigned long tunn_mode)
 223 {
 224         u8 l2gre_enable = 0, ipgre_enable = 0, vxlan_enable = 0;
 225         u8 l2geneve_enable = 0, ipgeneve_enable = 0;
 226
 227         if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode))
 228                 l2gre_enable = 1;
 229
 230         if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode))
 231                 ipgre_enable = 1;
 232
 233         if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode))
 234                 vxlan_enable = 1;
 235
 236         qed_set_gre_enable(p_hwfn, p_ptt, l2gre_enable, ipgre_enable);
 237         qed_set_vxlan_enable(p_hwfn, p_ptt, vxlan_enable);
 238
 239         if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode))
 240                 l2geneve_enable = 1;
 241
 242         if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode))
 243                 ipgeneve_enable = 1;
 244
 245         qed_set_geneve_enable(p_hwfn, p_ptt, l2geneve_enable,
 246                               ipgeneve_enable);
 247 }
 248
 249 static void
 250 qed_tunn_set_pf_start_params(struct qed_hwfn *p_hwfn,
 251                              struct qed_tunn_start_params *p_src,
 252                              struct pf_start_tunnel_config *p_tunn_cfg)
 253 {
 254         unsigned long tunn_mode;
 255         enum tunnel_clss type;
 256
 257         if (!p_src)
 258                 return;
 259
 260         tunn_mode = p_src->tunn_mode;
 261         type = qed_tunn_get_clss_type(p_src->tunn_clss_vxlan);
 262         p_tunn_cfg->tunnel_clss_vxlan = type;
 263         type = qed_tunn_get_clss_type(p_src->tunn_clss_l2gre);
 264         p_tunn_cfg->tunnel_clss_l2gre = type;
 265         type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgre);
 266         p_tunn_cfg->tunnel_clss_ipgre = type;
 267
 268         if (p_src->update_vxlan_udp_port) {
 269                 p_tunn_cfg->set_vxlan_udp_port_flg = 1;
 270                 p_tunn_cfg->vxlan_udp_port = cpu_to_le16(p_src->vxlan_udp_port);
 271         }
 272
 273         if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode))
 274                 p_tunn_cfg->tx_enable_l2gre = 1;
 275
 276         if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode))
 277                 p_tunn_cfg->tx_enable_ipgre = 1;
 278
 279         if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode))
 280                 p_tunn_cfg->tx_enable_vxlan = 1;
 281
 282         if (p_src->update_geneve_udp_port) {
 283                 p_tunn_cfg->set_geneve_udp_port_flg = 1;
 284                 p_tunn_cfg->geneve_udp_port =
 285                                 cpu_to_le16(p_src->geneve_udp_port);
 286         }
 287
 288         if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode))
 289                 p_tunn_cfg->tx_enable_l2geneve = 1;
 290
 291         if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode))
 292                 p_tunn_cfg->tx_enable_ipgeneve = 1;
 293
 294         type = qed_tunn_get_clss_type(p_src->tunn_clss_l2geneve);
 295         p_tunn_cfg->tunnel_clss_l2geneve = type;
 296         type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgeneve);
 297         p_tunn_cfg->tunnel_clss_ipgeneve = type;
 298 }
 299
 300 int qed_sp_pf_start(struct qed_hwfn *p_hwfn,
 301                     struct qed_tunn_start_params *p_tunn,
 302                     enum qed_mf_mode mode, bool allow_npar_tx_switch)
 303 {
 304         struct pf_start_ramrod_data *p_ramrod = NULL;
 305         u16 sb = qed_int_get_sp_sb_id(p_hwfn);
 306         u8 sb_index = p_hwfn->p_eq->eq_sb_index;
 307         struct qed_spq_entry *p_ent = NULL;
 308         struct qed_sp_init_data init_data;
 309         int rc = -EINVAL;
 310
 311         /* update initial eq producer */
 312         qed_eq_prod_update(p_hwfn,
 313                            qed_chain_get_prod_idx(&p_hwfn->p_eq->chain));
 314
 315         memset(&init_data, 0, sizeof(init_data));
 316         init_data.cid = qed_spq_get_cid(p_hwfn);
 317         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 318         init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
 319
 320         rc = qed_sp_init_request(p_hwfn, &p_ent,
 321                                  COMMON_RAMROD_PF_START,
 322                                  PROTOCOLID_COMMON,
 323                                  &init_data);
 324         if (rc)
 325                 return rc;
 326
 327         p_ramrod = &p_ent->ramrod.pf_start;
 328
 329         p_ramrod->event_ring_sb_id      = cpu_to_le16(sb);
 330         p_ramrod->event_ring_sb_index   = sb_index;
 331         p_ramrod->path_id               = QED_PATH_ID(p_hwfn);
 332         p_ramrod->dont_log_ramrods      = 0;
 333         p_ramrod->log_type_mask         = cpu_to_le16(0xf);
 334         p_ramrod->mf_mode = mode;
 335         switch (mode) {
 336         case QED_MF_DEFAULT:
 337         case QED_MF_NPAR:
 338                 p_ramrod->mf_mode = MF_NPAR;
 339                 break;
 340         case QED_MF_OVLAN:
 341                 p_ramrod->mf_mode = MF_OVLAN;
 342                 break;
 343         default:
 344                 DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
 345                 p_ramrod->mf_mode = MF_NPAR;
 346         }
 347         p_ramrod->outer_tag = p_hwfn->hw_info.ovlan;
 348
 349         /* Place EQ address in RAMROD */
 350         DMA_REGPAIR_LE(p_ramrod->event_ring_pbl_addr,
 351                        p_hwfn->p_eq->chain.pbl.p_phys_table);
 352         p_ramrod->event_ring_num_pages = (u8)p_hwfn->p_eq->chain.page_cnt;
 353
 354         DMA_REGPAIR_LE(p_ramrod->consolid_q_pbl_addr,
 355                        p_hwfn->p_consq->chain.pbl.p_phys_table);
 356
 357         qed_tunn_set_pf_start_params(p_hwfn, p_tunn,
 358                                      &p_ramrod->tunnel_config);
 359         p_hwfn->hw_info.personality = PERSONALITY_ETH;
 360
 361         if (IS_MF_SI(p_hwfn))
 362                 p_ramrod->allow_npar_tx_switching = allow_npar_tx_switch;
 363
 364         if (p_hwfn->cdev->p_iov_info) {
 365                 struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
 366
 367                 p_ramrod->base_vf_id = (u8) p_iov->first_vf_in_pf;
 368                 p_ramrod->num_vfs = (u8) p_iov->total_vfs;
 369         }
 370
 371         DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
 372                    "Setting event_ring_sb [id %04x index %02x], outer_tag [%d]\n",
 373                    sb, sb_index,
 374                    p_ramrod->outer_tag);
 375
 376         rc = qed_spq_post(p_hwfn, p_ent, NULL);
 377
 378         if (p_tunn) {
 379                 qed_set_hw_tunn_mode(p_hwfn, p_hwfn->p_main_ptt,
 380                                      p_tunn->tunn_mode);
 381                 p_hwfn->cdev->tunn_mode = p_tunn->tunn_mode;
 382         }
 383
 384         return rc;
 385 }
 386
 387 /* Set pf update ramrod command params */
 388 int qed_sp_pf_update_tunn_cfg(struct qed_hwfn *p_hwfn,
 389                               struct qed_tunn_update_params *p_tunn,
 390                               enum spq_mode comp_mode,
 391                               struct qed_spq_comp_cb *p_comp_data)
 392 {
 393         struct qed_spq_entry *p_ent = NULL;
 394         struct qed_sp_init_data init_data;
 395         int rc = -EINVAL;
 396
 397         /* Get SPQ entry */
 398         memset(&init_data, 0, sizeof(init_data));
 399         init_data.cid = qed_spq_get_cid(p_hwfn);
 400         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 401         init_data.comp_mode = comp_mode;
 402         init_data.p_comp_data = p_comp_data;
 403
 404         rc = qed_sp_init_request(p_hwfn, &p_ent,
 405                                  COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
 406                                  &init_data);
 407         if (rc)
 408                 return rc;
 409
 410         qed_tunn_set_pf_update_params(p_hwfn, p_tunn,
 411                                       &p_ent->ramrod.pf_update.tunnel_config);
 412
 413         rc = qed_spq_post(p_hwfn, p_ent, NULL);
 414         if (rc)
 415                 return rc;
 416
 417         if (p_tunn->update_vxlan_udp_port)
 418                 qed_set_vxlan_dest_port(p_hwfn, p_hwfn->p_main_ptt,
 419                                         p_tunn->vxlan_udp_port);
 420         if (p_tunn->update_geneve_udp_port)
 421                 qed_set_geneve_dest_port(p_hwfn, p_hwfn->p_main_ptt,
 422                                          p_tunn->geneve_udp_port);
 423
 424         qed_set_hw_tunn_mode(p_hwfn, p_hwfn->p_main_ptt, p_tunn->tunn_mode);
 425         p_hwfn->cdev->tunn_mode = p_tunn->tunn_mode;
 426
 427         return rc;
 428 }
 429
 430 int qed_sp_pf_stop(struct qed_hwfn *p_hwfn)
 431 {
 432         struct qed_spq_entry *p_ent = NULL;
 433         struct qed_sp_init_data init_data;
 434         int rc = -EINVAL;
 435
 436         /* Get SPQ entry */
 437         memset(&init_data, 0, sizeof(init_data));
 438         init_data.cid = qed_spq_get_cid(p_hwfn);
 439         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 440         init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
 441
 442         rc = qed_sp_init_request(p_hwfn, &p_ent,
 443                                  COMMON_RAMROD_PF_STOP, PROTOCOLID_COMMON,
 444                                  &init_data);
 445         if (rc)
 446                 return rc;
 447
 448         return qed_spq_post(p_hwfn, p_ent, NULL);
 449 }
 450
 451 int qed_sp_heartbeat_ramrod(struct qed_hwfn *p_hwfn)
 452 {
 453         struct qed_spq_entry *p_ent = NULL;
 454         struct qed_sp_init_data init_data;
 455         int rc;
 456
 457         /* Get SPQ entry */
 458         memset(&init_data, 0, sizeof(init_data));
 459         init_data.cid = qed_spq_get_cid(p_hwfn);
 460         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 461         init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
 462
 463         rc = qed_sp_init_request(p_hwfn, &p_ent,
 464                                  COMMON_RAMROD_EMPTY, PROTOCOLID_COMMON,
 465                                  &init_data);
 466         if (rc)
 467                 return rc;
 468
 469         return qed_spq_post(p_hwfn, p_ent, NULL);
 470 }