1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
9 #include <linux/types.h>
10 #include <asm/byteorder.h>
11 #include <linux/bitops.h>
12 #include <linux/errno.h>
13 #include <linux/kernel.h>
14 #include <linux/string.h>
16 #include <linux/qed/qed_chain.h>
22 #include "qed_reg_addr.h"
24 #include "qed_sriov.h"
26 int qed_sp_init_request(struct qed_hwfn
*p_hwfn
,
27 struct qed_spq_entry
**pp_ent
,
28 u8 cmd
, u8 protocol
, struct qed_sp_init_data
*p_data
)
30 u32 opaque_cid
= p_data
->opaque_fid
<< 16 | p_data
->cid
;
31 struct qed_spq_entry
*p_ent
= NULL
;
37 rc
= qed_spq_get_entry(p_hwfn
, pp_ent
);
44 p_ent
->elem
.hdr
.cid
= cpu_to_le32(opaque_cid
);
45 p_ent
->elem
.hdr
.cmd_id
= cmd
;
46 p_ent
->elem
.hdr
.protocol_id
= protocol
;
48 p_ent
->priority
= QED_SPQ_PRIORITY_NORMAL
;
49 p_ent
->comp_mode
= p_data
->comp_mode
;
50 p_ent
->comp_done
.done
= 0;
52 switch (p_ent
->comp_mode
) {
53 case QED_SPQ_MODE_EBLOCK
:
54 p_ent
->comp_cb
.cookie
= &p_ent
->comp_done
;
57 case QED_SPQ_MODE_BLOCK
:
58 if (!p_data
->p_comp_data
)
61 p_ent
->comp_cb
.cookie
= p_data
->p_comp_data
->cookie
;
65 if (!p_data
->p_comp_data
)
66 p_ent
->comp_cb
.function
= NULL
;
68 p_ent
->comp_cb
= *p_data
->p_comp_data
;
72 DP_NOTICE(p_hwfn
, "Unknown SPQE completion mode %d\n",
77 DP_VERBOSE(p_hwfn
, QED_MSG_SPQ
,
78 "Initialized: CID %08x cmd %02x protocol %02x data_addr %lu comp_mode [%s]\n",
79 opaque_cid
, cmd
, protocol
,
80 (unsigned long)&p_ent
->ramrod
,
81 D_TRINE(p_ent
->comp_mode
, QED_SPQ_MODE_EBLOCK
,
82 QED_SPQ_MODE_BLOCK
, "MODE_EBLOCK", "MODE_BLOCK",
85 memset(&p_ent
->ramrod
, 0, sizeof(p_ent
->ramrod
));
90 static enum tunnel_clss
qed_tunn_get_clss_type(u8 type
)
93 case QED_TUNN_CLSS_MAC_VLAN
:
94 return TUNNEL_CLSS_MAC_VLAN
;
95 case QED_TUNN_CLSS_MAC_VNI
:
96 return TUNNEL_CLSS_MAC_VNI
;
97 case QED_TUNN_CLSS_INNER_MAC_VLAN
:
98 return TUNNEL_CLSS_INNER_MAC_VLAN
;
99 case QED_TUNN_CLSS_INNER_MAC_VNI
:
100 return TUNNEL_CLSS_INNER_MAC_VNI
;
102 return TUNNEL_CLSS_MAC_VLAN
;
107 qed_tunn_set_pf_fix_tunn_mode(struct qed_hwfn
*p_hwfn
,
108 struct qed_tunn_update_params
*p_src
,
109 struct pf_update_tunnel_config
*p_tunn_cfg
)
111 unsigned long cached_tunn_mode
= p_hwfn
->cdev
->tunn_mode
;
112 unsigned long update_mask
= p_src
->tunn_mode_update_mask
;
113 unsigned long tunn_mode
= p_src
->tunn_mode
;
114 unsigned long new_tunn_mode
= 0;
116 if (test_bit(QED_MODE_L2GRE_TUNN
, &update_mask
)) {
117 if (test_bit(QED_MODE_L2GRE_TUNN
, &tunn_mode
))
118 __set_bit(QED_MODE_L2GRE_TUNN
, &new_tunn_mode
);
120 if (test_bit(QED_MODE_L2GRE_TUNN
, &cached_tunn_mode
))
121 __set_bit(QED_MODE_L2GRE_TUNN
, &new_tunn_mode
);
124 if (test_bit(QED_MODE_IPGRE_TUNN
, &update_mask
)) {
125 if (test_bit(QED_MODE_IPGRE_TUNN
, &tunn_mode
))
126 __set_bit(QED_MODE_IPGRE_TUNN
, &new_tunn_mode
);
128 if (test_bit(QED_MODE_IPGRE_TUNN
, &cached_tunn_mode
))
129 __set_bit(QED_MODE_IPGRE_TUNN
, &new_tunn_mode
);
132 if (test_bit(QED_MODE_VXLAN_TUNN
, &update_mask
)) {
133 if (test_bit(QED_MODE_VXLAN_TUNN
, &tunn_mode
))
134 __set_bit(QED_MODE_VXLAN_TUNN
, &new_tunn_mode
);
136 if (test_bit(QED_MODE_VXLAN_TUNN
, &cached_tunn_mode
))
137 __set_bit(QED_MODE_VXLAN_TUNN
, &new_tunn_mode
);
140 if (p_src
->update_geneve_udp_port
) {
141 p_tunn_cfg
->set_geneve_udp_port_flg
= 1;
142 p_tunn_cfg
->geneve_udp_port
=
143 cpu_to_le16(p_src
->geneve_udp_port
);
146 if (test_bit(QED_MODE_L2GENEVE_TUNN
, &update_mask
)) {
147 if (test_bit(QED_MODE_L2GENEVE_TUNN
, &tunn_mode
))
148 __set_bit(QED_MODE_L2GENEVE_TUNN
, &new_tunn_mode
);
150 if (test_bit(QED_MODE_L2GENEVE_TUNN
, &cached_tunn_mode
))
151 __set_bit(QED_MODE_L2GENEVE_TUNN
, &new_tunn_mode
);
154 if (test_bit(QED_MODE_IPGENEVE_TUNN
, &update_mask
)) {
155 if (test_bit(QED_MODE_IPGENEVE_TUNN
, &tunn_mode
))
156 __set_bit(QED_MODE_IPGENEVE_TUNN
, &new_tunn_mode
);
158 if (test_bit(QED_MODE_IPGENEVE_TUNN
, &cached_tunn_mode
))
159 __set_bit(QED_MODE_IPGENEVE_TUNN
, &new_tunn_mode
);
162 p_src
->tunn_mode
= new_tunn_mode
;
166 qed_tunn_set_pf_update_params(struct qed_hwfn
*p_hwfn
,
167 struct qed_tunn_update_params
*p_src
,
168 struct pf_update_tunnel_config
*p_tunn_cfg
)
170 unsigned long tunn_mode
= p_src
->tunn_mode
;
171 enum tunnel_clss type
;
173 qed_tunn_set_pf_fix_tunn_mode(p_hwfn
, p_src
, p_tunn_cfg
);
174 p_tunn_cfg
->update_rx_pf_clss
= p_src
->update_rx_pf_clss
;
175 p_tunn_cfg
->update_tx_pf_clss
= p_src
->update_tx_pf_clss
;
177 type
= qed_tunn_get_clss_type(p_src
->tunn_clss_vxlan
);
178 p_tunn_cfg
->tunnel_clss_vxlan
= type
;
180 type
= qed_tunn_get_clss_type(p_src
->tunn_clss_l2gre
);
181 p_tunn_cfg
->tunnel_clss_l2gre
= type
;
183 type
= qed_tunn_get_clss_type(p_src
->tunn_clss_ipgre
);
184 p_tunn_cfg
->tunnel_clss_ipgre
= type
;
186 if (p_src
->update_vxlan_udp_port
) {
187 p_tunn_cfg
->set_vxlan_udp_port_flg
= 1;
188 p_tunn_cfg
->vxlan_udp_port
= cpu_to_le16(p_src
->vxlan_udp_port
);
191 if (test_bit(QED_MODE_L2GRE_TUNN
, &tunn_mode
))
192 p_tunn_cfg
->tx_enable_l2gre
= 1;
194 if (test_bit(QED_MODE_IPGRE_TUNN
, &tunn_mode
))
195 p_tunn_cfg
->tx_enable_ipgre
= 1;
197 if (test_bit(QED_MODE_VXLAN_TUNN
, &tunn_mode
))
198 p_tunn_cfg
->tx_enable_vxlan
= 1;
200 if (p_src
->update_geneve_udp_port
) {
201 p_tunn_cfg
->set_geneve_udp_port_flg
= 1;
202 p_tunn_cfg
->geneve_udp_port
=
203 cpu_to_le16(p_src
->geneve_udp_port
);
206 if (test_bit(QED_MODE_L2GENEVE_TUNN
, &tunn_mode
))
207 p_tunn_cfg
->tx_enable_l2geneve
= 1;
209 if (test_bit(QED_MODE_IPGENEVE_TUNN
, &tunn_mode
))
210 p_tunn_cfg
->tx_enable_ipgeneve
= 1;
212 type
= qed_tunn_get_clss_type(p_src
->tunn_clss_l2geneve
);
213 p_tunn_cfg
->tunnel_clss_l2geneve
= type
;
215 type
= qed_tunn_get_clss_type(p_src
->tunn_clss_ipgeneve
);
216 p_tunn_cfg
->tunnel_clss_ipgeneve
= type
;
219 static void qed_set_hw_tunn_mode(struct qed_hwfn
*p_hwfn
,
220 struct qed_ptt
*p_ptt
,
221 unsigned long tunn_mode
)
223 u8 l2gre_enable
= 0, ipgre_enable
= 0, vxlan_enable
= 0;
224 u8 l2geneve_enable
= 0, ipgeneve_enable
= 0;
226 if (test_bit(QED_MODE_L2GRE_TUNN
, &tunn_mode
))
229 if (test_bit(QED_MODE_IPGRE_TUNN
, &tunn_mode
))
232 if (test_bit(QED_MODE_VXLAN_TUNN
, &tunn_mode
))
235 qed_set_gre_enable(p_hwfn
, p_ptt
, l2gre_enable
, ipgre_enable
);
236 qed_set_vxlan_enable(p_hwfn
, p_ptt
, vxlan_enable
);
238 if (test_bit(QED_MODE_L2GENEVE_TUNN
, &tunn_mode
))
241 if (test_bit(QED_MODE_IPGENEVE_TUNN
, &tunn_mode
))
244 qed_set_geneve_enable(p_hwfn
, p_ptt
, l2geneve_enable
,
249 qed_tunn_set_pf_start_params(struct qed_hwfn
*p_hwfn
,
250 struct qed_tunn_start_params
*p_src
,
251 struct pf_start_tunnel_config
*p_tunn_cfg
)
253 unsigned long tunn_mode
;
254 enum tunnel_clss type
;
259 tunn_mode
= p_src
->tunn_mode
;
260 type
= qed_tunn_get_clss_type(p_src
->tunn_clss_vxlan
);
261 p_tunn_cfg
->tunnel_clss_vxlan
= type
;
262 type
= qed_tunn_get_clss_type(p_src
->tunn_clss_l2gre
);
263 p_tunn_cfg
->tunnel_clss_l2gre
= type
;
264 type
= qed_tunn_get_clss_type(p_src
->tunn_clss_ipgre
);
265 p_tunn_cfg
->tunnel_clss_ipgre
= type
;
267 if (p_src
->update_vxlan_udp_port
) {
268 p_tunn_cfg
->set_vxlan_udp_port_flg
= 1;
269 p_tunn_cfg
->vxlan_udp_port
= cpu_to_le16(p_src
->vxlan_udp_port
);
272 if (test_bit(QED_MODE_L2GRE_TUNN
, &tunn_mode
))
273 p_tunn_cfg
->tx_enable_l2gre
= 1;
275 if (test_bit(QED_MODE_IPGRE_TUNN
, &tunn_mode
))
276 p_tunn_cfg
->tx_enable_ipgre
= 1;
278 if (test_bit(QED_MODE_VXLAN_TUNN
, &tunn_mode
))
279 p_tunn_cfg
->tx_enable_vxlan
= 1;
281 if (p_src
->update_geneve_udp_port
) {
282 p_tunn_cfg
->set_geneve_udp_port_flg
= 1;
283 p_tunn_cfg
->geneve_udp_port
=
284 cpu_to_le16(p_src
->geneve_udp_port
);
287 if (test_bit(QED_MODE_L2GENEVE_TUNN
, &tunn_mode
))
288 p_tunn_cfg
->tx_enable_l2geneve
= 1;
290 if (test_bit(QED_MODE_IPGENEVE_TUNN
, &tunn_mode
))
291 p_tunn_cfg
->tx_enable_ipgeneve
= 1;
293 type
= qed_tunn_get_clss_type(p_src
->tunn_clss_l2geneve
);
294 p_tunn_cfg
->tunnel_clss_l2geneve
= type
;
295 type
= qed_tunn_get_clss_type(p_src
->tunn_clss_ipgeneve
);
296 p_tunn_cfg
->tunnel_clss_ipgeneve
= type
;
299 int qed_sp_pf_start(struct qed_hwfn
*p_hwfn
,
300 struct qed_tunn_start_params
*p_tunn
,
301 enum qed_mf_mode mode
, bool allow_npar_tx_switch
)
303 struct pf_start_ramrod_data
*p_ramrod
= NULL
;
304 u16 sb
= qed_int_get_sp_sb_id(p_hwfn
);
305 u8 sb_index
= p_hwfn
->p_eq
->eq_sb_index
;
306 struct qed_spq_entry
*p_ent
= NULL
;
307 struct qed_sp_init_data init_data
;
311 /* update initial eq producer */
312 qed_eq_prod_update(p_hwfn
,
313 qed_chain_get_prod_idx(&p_hwfn
->p_eq
->chain
));
315 memset(&init_data
, 0, sizeof(init_data
));
316 init_data
.cid
= qed_spq_get_cid(p_hwfn
);
317 init_data
.opaque_fid
= p_hwfn
->hw_info
.opaque_fid
;
318 init_data
.comp_mode
= QED_SPQ_MODE_EBLOCK
;
320 rc
= qed_sp_init_request(p_hwfn
, &p_ent
,
321 COMMON_RAMROD_PF_START
,
322 PROTOCOLID_COMMON
, &init_data
);
326 p_ramrod
= &p_ent
->ramrod
.pf_start
;
328 p_ramrod
->event_ring_sb_id
= cpu_to_le16(sb
);
329 p_ramrod
->event_ring_sb_index
= sb_index
;
330 p_ramrod
->path_id
= QED_PATH_ID(p_hwfn
);
331 p_ramrod
->dont_log_ramrods
= 0;
332 p_ramrod
->log_type_mask
= cpu_to_le16(0xf);
337 p_ramrod
->mf_mode
= MF_NPAR
;
340 p_ramrod
->mf_mode
= MF_OVLAN
;
343 DP_NOTICE(p_hwfn
, "Unsupported MF mode, init as DEFAULT\n");
344 p_ramrod
->mf_mode
= MF_NPAR
;
346 p_ramrod
->outer_tag
= p_hwfn
->hw_info
.ovlan
;
348 /* Place EQ address in RAMROD */
349 DMA_REGPAIR_LE(p_ramrod
->event_ring_pbl_addr
,
350 p_hwfn
->p_eq
->chain
.pbl_sp
.p_phys_table
);
351 page_cnt
= (u8
)qed_chain_get_page_cnt(&p_hwfn
->p_eq
->chain
);
352 p_ramrod
->event_ring_num_pages
= page_cnt
;
353 DMA_REGPAIR_LE(p_ramrod
->consolid_q_pbl_addr
,
354 p_hwfn
->p_consq
->chain
.pbl_sp
.p_phys_table
);
356 qed_tunn_set_pf_start_params(p_hwfn
, p_tunn
, &p_ramrod
->tunnel_config
);
358 if (IS_MF_SI(p_hwfn
))
359 p_ramrod
->allow_npar_tx_switching
= allow_npar_tx_switch
;
361 switch (p_hwfn
->hw_info
.personality
) {
363 p_ramrod
->personality
= PERSONALITY_ETH
;
366 p_ramrod
->personality
= PERSONALITY_ISCSI
;
368 case QED_PCI_ETH_ROCE
:
369 p_ramrod
->personality
= PERSONALITY_RDMA_AND_ETH
;
372 DP_NOTICE(p_hwfn
, "Unkown personality %d\n",
373 p_hwfn
->hw_info
.personality
);
374 p_ramrod
->personality
= PERSONALITY_ETH
;
377 if (p_hwfn
->cdev
->p_iov_info
) {
378 struct qed_hw_sriov_info
*p_iov
= p_hwfn
->cdev
->p_iov_info
;
380 p_ramrod
->base_vf_id
= (u8
) p_iov
->first_vf_in_pf
;
381 p_ramrod
->num_vfs
= (u8
) p_iov
->total_vfs
;
383 p_ramrod
->hsi_fp_ver
.major_ver_arr
[ETH_VER_KEY
] = ETH_HSI_VER_MAJOR
;
384 p_ramrod
->hsi_fp_ver
.minor_ver_arr
[ETH_VER_KEY
] = ETH_HSI_VER_MINOR
;
386 DP_VERBOSE(p_hwfn
, QED_MSG_SPQ
,
387 "Setting event_ring_sb [id %04x index %02x], outer_tag [%d]\n",
388 sb
, sb_index
, p_ramrod
->outer_tag
);
390 rc
= qed_spq_post(p_hwfn
, p_ent
, NULL
);
393 qed_set_hw_tunn_mode(p_hwfn
, p_hwfn
->p_main_ptt
,
395 p_hwfn
->cdev
->tunn_mode
= p_tunn
->tunn_mode
;
401 int qed_sp_pf_update(struct qed_hwfn
*p_hwfn
)
403 struct qed_spq_entry
*p_ent
= NULL
;
404 struct qed_sp_init_data init_data
;
408 memset(&init_data
, 0, sizeof(init_data
));
409 init_data
.cid
= qed_spq_get_cid(p_hwfn
);
410 init_data
.opaque_fid
= p_hwfn
->hw_info
.opaque_fid
;
411 init_data
.comp_mode
= QED_SPQ_MODE_CB
;
413 rc
= qed_sp_init_request(p_hwfn
, &p_ent
,
414 COMMON_RAMROD_PF_UPDATE
, PROTOCOLID_COMMON
,
419 qed_dcbx_set_pf_update_params(&p_hwfn
->p_dcbx_info
->results
,
420 &p_ent
->ramrod
.pf_update
);
422 return qed_spq_post(p_hwfn
, p_ent
, NULL
);
425 /* Set pf update ramrod command params */
426 int qed_sp_pf_update_tunn_cfg(struct qed_hwfn
*p_hwfn
,
427 struct qed_tunn_update_params
*p_tunn
,
428 enum spq_mode comp_mode
,
429 struct qed_spq_comp_cb
*p_comp_data
)
431 struct qed_spq_entry
*p_ent
= NULL
;
432 struct qed_sp_init_data init_data
;
436 memset(&init_data
, 0, sizeof(init_data
));
437 init_data
.cid
= qed_spq_get_cid(p_hwfn
);
438 init_data
.opaque_fid
= p_hwfn
->hw_info
.opaque_fid
;
439 init_data
.comp_mode
= comp_mode
;
440 init_data
.p_comp_data
= p_comp_data
;
442 rc
= qed_sp_init_request(p_hwfn
, &p_ent
,
443 COMMON_RAMROD_PF_UPDATE
, PROTOCOLID_COMMON
,
448 qed_tunn_set_pf_update_params(p_hwfn
, p_tunn
,
449 &p_ent
->ramrod
.pf_update
.tunnel_config
);
451 rc
= qed_spq_post(p_hwfn
, p_ent
, NULL
);
455 if (p_tunn
->update_vxlan_udp_port
)
456 qed_set_vxlan_dest_port(p_hwfn
, p_hwfn
->p_main_ptt
,
457 p_tunn
->vxlan_udp_port
);
458 if (p_tunn
->update_geneve_udp_port
)
459 qed_set_geneve_dest_port(p_hwfn
, p_hwfn
->p_main_ptt
,
460 p_tunn
->geneve_udp_port
);
462 qed_set_hw_tunn_mode(p_hwfn
, p_hwfn
->p_main_ptt
, p_tunn
->tunn_mode
);
463 p_hwfn
->cdev
->tunn_mode
= p_tunn
->tunn_mode
;
468 int qed_sp_pf_stop(struct qed_hwfn
*p_hwfn
)
470 struct qed_spq_entry
*p_ent
= NULL
;
471 struct qed_sp_init_data init_data
;
475 memset(&init_data
, 0, sizeof(init_data
));
476 init_data
.cid
= qed_spq_get_cid(p_hwfn
);
477 init_data
.opaque_fid
= p_hwfn
->hw_info
.opaque_fid
;
478 init_data
.comp_mode
= QED_SPQ_MODE_EBLOCK
;
480 rc
= qed_sp_init_request(p_hwfn
, &p_ent
,
481 COMMON_RAMROD_PF_STOP
, PROTOCOLID_COMMON
,
486 return qed_spq_post(p_hwfn
, p_ent
, NULL
);
489 int qed_sp_heartbeat_ramrod(struct qed_hwfn
*p_hwfn
)
491 struct qed_spq_entry
*p_ent
= NULL
;
492 struct qed_sp_init_data init_data
;
496 memset(&init_data
, 0, sizeof(init_data
));
497 init_data
.cid
= qed_spq_get_cid(p_hwfn
);
498 init_data
.opaque_fid
= p_hwfn
->hw_info
.opaque_fid
;
499 init_data
.comp_mode
= QED_SPQ_MODE_EBLOCK
;
501 rc
= qed_sp_init_request(p_hwfn
, &p_ent
,
502 COMMON_RAMROD_EMPTY
, PROTOCOLID_COMMON
,
507 return qed_spq_post(p_hwfn
, p_ent
, NULL
);