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[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic.h
1 /*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
8 #ifndef _QLCNIC_H_
9 #define _QLCNIC_H_
10
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/netdevice.h>
17 #include <linux/etherdevice.h>
18 #include <linux/ip.h>
19 #include <linux/in.h>
20 #include <linux/tcp.h>
21 #include <linux/skbuff.h>
22 #include <linux/firmware.h>
23 #include <linux/ethtool.h>
24 #include <linux/mii.h>
25 #include <linux/timer.h>
26
27 #include <linux/vmalloc.h>
28
29 #include <linux/io.h>
30 #include <asm/byteorder.h>
31 #include <linux/bitops.h>
32 #include <linux/if_vlan.h>
33
34 #include "qlcnic_hdr.h"
35 #include "qlcnic_hw.h"
36 #include "qlcnic_83xx_hw.h"
37 #include "qlcnic_dcb.h"
38
39 #define _QLCNIC_LINUX_MAJOR 5
40 #define _QLCNIC_LINUX_MINOR 3
41 #define _QLCNIC_LINUX_SUBVERSION 57
42 #define QLCNIC_LINUX_VERSIONID "5.3.57"
43 #define QLCNIC_DRV_IDC_VER 0x01
44 #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\
45 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION))
46
47 #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
48 #define _major(v) (((v) >> 24) & 0xff)
49 #define _minor(v) (((v) >> 16) & 0xff)
50 #define _build(v) ((v) & 0xffff)
51
52 /* version in image has weird encoding:
53 * 7:0 - major
54 * 15:8 - minor
55 * 31:16 - build (little endian)
56 */
57 #define QLCNIC_DECODE_VERSION(v) \
58 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
59
60 #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2)
61 #define QLCNIC_NUM_FLASH_SECTORS (64)
62 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024)
63 #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \
64 * QLCNIC_FLASH_SECTOR_SIZE)
65
66 #define RCV_DESC_RINGSIZE(rds_ring) \
67 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
68 #define RCV_BUFF_RINGSIZE(rds_ring) \
69 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc)
70 #define STATUS_DESC_RINGSIZE(sds_ring) \
71 (sizeof(struct status_desc) * (sds_ring)->num_desc)
72 #define TX_BUFF_RINGSIZE(tx_ring) \
73 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc)
74 #define TX_DESC_RINGSIZE(tx_ring) \
75 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
76
77 #define QLCNIC_P3P_A0 0x50
78 #define QLCNIC_P3P_C0 0x58
79
80 #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0)
81
82 #define FIRST_PAGE_GROUP_START 0
83 #define FIRST_PAGE_GROUP_END 0x100000
84
85 #define P3P_MAX_MTU (9600)
86 #define P3P_MIN_MTU (68)
87 #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */
88
89 #define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN)
90 #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU)
91 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048
92 #define QLCNIC_LRO_BUFFER_EXTRA 2048
93
94 /* Tx defines */
95 #define QLCNIC_MAX_FRAGS_PER_TX 14
96 #define MAX_TSO_HEADER_DESC 2
97 #define MGMT_CMD_DESC_RESV 4
98 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \
99 + MGMT_CMD_DESC_RESV)
100 #define QLCNIC_MAX_TX_TIMEOUTS 2
101
102 /* Driver will use 1 Tx ring in INT-x/MSI/SRIOV mode. */
103 #define QLCNIC_SINGLE_RING 1
104 #define QLCNIC_DEF_SDS_RINGS 4
105 #define QLCNIC_DEF_TX_RINGS 4
106 #define QLCNIC_MAX_VNIC_TX_RINGS 4
107 #define QLCNIC_MAX_VNIC_SDS_RINGS 4
108 #define QLCNIC_83XX_MINIMUM_VECTOR 3
109 #define QLCNIC_82XX_MINIMUM_VECTOR 2
110
111 enum qlcnic_queue_type {
112 QLCNIC_TX_QUEUE = 1,
113 QLCNIC_RX_QUEUE,
114 };
115
116 /* Operational mode for driver */
117 #define QLCNIC_VNIC_MODE 0xFF
118 #define QLCNIC_DEFAULT_MODE 0x0
119
120 /* Virtual NIC function count */
121 #define QLC_DEFAULT_VNIC_COUNT 8
122 #define QLC_84XX_VNIC_COUNT 16
123
124 /*
125 * Following are the states of the Phantom. Phantom will set them and
126 * Host will read to check if the fields are correct.
127 */
128 #define PHAN_INITIALIZE_FAILED 0xffff
129 #define PHAN_INITIALIZE_COMPLETE 0xff01
130
131 /* Host writes the following to notify that it has done the init-handshake */
132 #define PHAN_INITIALIZE_ACK 0xf00f
133 #define PHAN_PEG_RCV_INITIALIZED 0xff01
134
135 #define NUM_RCV_DESC_RINGS 3
136
137 #define RCV_RING_NORMAL 0
138 #define RCV_RING_JUMBO 1
139
140 #define MIN_CMD_DESCRIPTORS 64
141 #define MIN_RCV_DESCRIPTORS 64
142 #define MIN_JUMBO_DESCRIPTORS 32
143
144 #define MAX_CMD_DESCRIPTORS 1024
145 #define MAX_RCV_DESCRIPTORS_1G 4096
146 #define MAX_RCV_DESCRIPTORS_10G 8192
147 #define MAX_RCV_DESCRIPTORS_VF 2048
148 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
149 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
150
151 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
152 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
153 #define DEFAULT_RCV_DESCRIPTORS_VF 1024
154 #define MAX_RDS_RINGS 2
155
156 #define get_next_index(index, length) \
157 (((index) + 1) & ((length) - 1))
158
159 /*
160 * Following data structures describe the descriptors that will be used.
161 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
162 * we are doing LSO (above the 1500 size packet) only.
163 */
164 struct cmd_desc_type0 {
165 u8 tcp_hdr_offset; /* For LSO only */
166 u8 ip_hdr_offset; /* For LSO only */
167 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
168 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
169
170 __le64 addr_buffer2;
171
172 __le16 encap_descr; /* 15:10 offset of outer L3 header,
173 * 9:6 number of 32bit words in outer L3 header,
174 * 5 offload outer L4 checksum,
175 * 4 offload outer L3 checksum,
176 * 3 Inner L4 type, TCP=0, UDP=1,
177 * 2 Inner L3 type, IPv4=0, IPv6=1,
178 * 1 Outer L3 type,IPv4=0, IPv6=1,
179 * 0 type of encapsulation, GRE=0, VXLAN=1
180 */
181 __le16 mss;
182 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
183 u8 hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
184 u8 outer_hdr_length; /* Encapsulation only */
185 u8 rsvd1;
186
187 __le64 addr_buffer3;
188 __le64 addr_buffer1;
189
190 __le16 buffer_length[4];
191
192 __le64 addr_buffer4;
193
194 u8 eth_addr[ETH_ALEN];
195 __le16 vlan_TCI; /* In case of encapsulation,
196 * this is for outer VLAN
197 */
198
199 } __attribute__ ((aligned(64)));
200
201 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
202 struct rcv_desc {
203 __le16 reference_handle;
204 __le16 reserved;
205 __le32 buffer_length; /* allocated buffer length (usually 2K) */
206 __le64 addr_buffer;
207 } __packed;
208
209 struct status_desc {
210 __le64 status_desc_data[2];
211 } __attribute__ ((aligned(16)));
212
213 /* UNIFIED ROMIMAGE */
214 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000
215 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0
216 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6
217 #define QLCNIC_UNI_DIR_SECT_FW 0x7
218
219 /*Offsets */
220 #define QLCNIC_UNI_CHIP_REV_OFF 10
221 #define QLCNIC_UNI_FLAGS_OFF 11
222 #define QLCNIC_UNI_BIOS_VERSION_OFF 12
223 #define QLCNIC_UNI_BOOTLD_IDX_OFF 27
224 #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29
225
226 struct uni_table_desc{
227 __le32 findex;
228 __le32 num_entries;
229 __le32 entry_size;
230 __le32 reserved[5];
231 };
232
233 struct uni_data_desc{
234 __le32 findex;
235 __le32 size;
236 __le32 reserved[5];
237 };
238
239 /* Flash Defines and Structures */
240 #define QLCNIC_FLT_LOCATION 0x3F1000
241 #define QLCNIC_FDT_LOCATION 0x3F0000
242 #define QLCNIC_B0_FW_IMAGE_REGION 0x74
243 #define QLCNIC_C0_FW_IMAGE_REGION 0x97
244 #define QLCNIC_BOOTLD_REGION 0X72
245 struct qlcnic_flt_header {
246 u16 version;
247 u16 len;
248 u16 checksum;
249 u16 reserved;
250 };
251
252 struct qlcnic_flt_entry {
253 u8 region;
254 u8 reserved0;
255 u8 attrib;
256 u8 reserved1;
257 u32 size;
258 u32 start_addr;
259 u32 end_addr;
260 };
261
262 /* Flash Descriptor Table */
263 struct qlcnic_fdt {
264 u32 valid;
265 u16 ver;
266 u16 len;
267 u16 cksum;
268 u16 unused;
269 u8 model[16];
270 u16 mfg_id;
271 u16 id;
272 u8 flag;
273 u8 erase_cmd;
274 u8 alt_erase_cmd;
275 u8 write_enable_cmd;
276 u8 write_enable_bits;
277 u8 write_statusreg_cmd;
278 u8 unprotected_sec_cmd;
279 u8 read_manuf_cmd;
280 u32 block_size;
281 u32 alt_block_size;
282 u32 flash_size;
283 u32 write_enable_data;
284 u8 readid_addr_len;
285 u8 write_disable_bits;
286 u8 read_dev_id_len;
287 u8 chip_erase_cmd;
288 u16 read_timeo;
289 u8 protected_sec_cmd;
290 u8 resvd[65];
291 };
292 /* Magic number to let user know flash is programmed */
293 #define QLCNIC_BDINFO_MAGIC 0x12345678
294
295 #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021
296 #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022
297 #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023
298 #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024
299 #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025
300 #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026
301 #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027
302 #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028
303 #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029
304 #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a
305 #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b
306 #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031
307 #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032
308 #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080
309
310 #define QLCNIC_MSIX_TABLE_OFFSET 0x44
311
312 /* Flash memory map */
313 #define QLCNIC_BRDCFG_START 0x4000 /* board config */
314 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */
315 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */
316 #define QLCNIC_USER_START 0x3E8000 /* Firmare info */
317
318 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408)
319 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c)
320 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c)
321 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c)
322
323 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8)
324 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128)
325
326 #define QLCNIC_FW_MIN_SIZE (0x3fffff)
327 #define QLCNIC_UNIFIED_ROMIMAGE 0
328 #define QLCNIC_FLASH_ROMIMAGE 1
329 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff
330
331 #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
332 #define QLCNIC_FLASH_ROMIMAGE_NAME "flash"
333
334 extern char qlcnic_driver_name[];
335
336 extern int qlcnic_use_msi;
337 extern int qlcnic_use_msi_x;
338 extern int qlcnic_auto_fw_reset;
339 extern int qlcnic_load_fw_file;
340
341 /* Number of status descriptors to handle per interrupt */
342 #define MAX_STATUS_HANDLE (64)
343
344 /*
345 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This
346 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}.
347 */
348 struct qlcnic_skb_frag {
349 u64 dma;
350 u64 length;
351 };
352
353 /* Following defines are for the state of the buffers */
354 #define QLCNIC_BUFFER_FREE 0
355 #define QLCNIC_BUFFER_BUSY 1
356
357 /*
358 * There will be one qlcnic_buffer per skb packet. These will be
359 * used to save the dma info for pci_unmap_page()
360 */
361 struct qlcnic_cmd_buffer {
362 struct sk_buff *skb;
363 struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1];
364 u32 frag_count;
365 };
366
367 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
368 struct qlcnic_rx_buffer {
369 u16 ref_handle;
370 struct sk_buff *skb;
371 struct list_head list;
372 u64 dma;
373 };
374
375 /* Board types */
376 #define QLCNIC_GBE 0x01
377 #define QLCNIC_XGBE 0x02
378
379 /*
380 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
381 * adjusted based on configured MTU.
382 */
383 #define QLCNIC_INTR_COAL_TYPE_RX 1
384 #define QLCNIC_INTR_COAL_TYPE_TX 2
385 #define QLCNIC_INTR_COAL_TYPE_RX_TX 3
386
387 #define QLCNIC_DEF_INTR_COALESCE_RX_TIME_US 3
388 #define QLCNIC_DEF_INTR_COALESCE_RX_PACKETS 256
389
390 #define QLCNIC_DEF_INTR_COALESCE_TX_TIME_US 64
391 #define QLCNIC_DEF_INTR_COALESCE_TX_PACKETS 64
392
393 #define QLCNIC_INTR_DEFAULT 0x04
394 #define QLCNIC_CONFIG_INTR_COALESCE 3
395 #define QLCNIC_DEV_INFO_SIZE 2
396
397 struct qlcnic_nic_intr_coalesce {
398 u8 type;
399 u8 sts_ring_mask;
400 u16 rx_packets;
401 u16 rx_time_us;
402 u16 tx_packets;
403 u16 tx_time_us;
404 u16 flag;
405 u32 timer_out;
406 };
407
408 struct qlcnic_83xx_dump_template_hdr {
409 u32 type;
410 u32 offset;
411 u32 size;
412 u32 cap_mask;
413 u32 num_entries;
414 u32 version;
415 u32 timestamp;
416 u32 checksum;
417 u32 drv_cap_mask;
418 u32 sys_info[3];
419 u32 saved_state[16];
420 u32 cap_sizes[8];
421 u32 ocm_wnd_reg[16];
422 u32 rsvd[0];
423 };
424
425 struct qlcnic_82xx_dump_template_hdr {
426 u32 type;
427 u32 offset;
428 u32 size;
429 u32 cap_mask;
430 u32 num_entries;
431 u32 version;
432 u32 timestamp;
433 u32 checksum;
434 u32 drv_cap_mask;
435 u32 sys_info[3];
436 u32 saved_state[16];
437 u32 cap_sizes[8];
438 u32 rsvd[7];
439 u32 capabilities;
440 u32 rsvd1[0];
441 };
442
443 struct qlcnic_fw_dump {
444 u8 clr; /* flag to indicate if dump is cleared */
445 bool enable; /* enable/disable dump */
446 u32 size; /* total size of the dump */
447 u32 cap_mask; /* Current capture mask */
448 void *data; /* dump data area */
449 void *tmpl_hdr;
450 dma_addr_t phys_addr;
451 void *dma_buffer;
452 bool use_pex_dma;
453 /* Read only elements which are common between 82xx and 83xx
454 * template header. Update these values immediately after we read
455 * template header from Firmware
456 */
457 u32 tmpl_hdr_size;
458 u32 version;
459 u32 num_entries;
460 u32 offset;
461 };
462
463 /*
464 * One hardware_context{} per adapter
465 * contains interrupt info as well shared hardware info.
466 */
467 struct qlcnic_hardware_context {
468 void __iomem *pci_base0;
469 void __iomem *ocm_win_crb;
470
471 unsigned long pci_len0;
472
473 rwlock_t crb_lock;
474 struct mutex mem_lock;
475
476 u8 revision_id;
477 u8 pci_func;
478 u8 linkup;
479 u8 loopback_state;
480 u8 beacon_state;
481 u8 has_link_events;
482 u8 fw_type;
483 u8 physical_port;
484 u8 reset_context;
485 u8 msix_supported;
486 u8 max_mac_filters;
487 u8 mc_enabled;
488 u8 max_mc_count;
489 u8 diag_test;
490 u8 num_msix;
491 u8 nic_mode;
492 int diag_cnt;
493
494 u16 max_uc_count;
495 u16 port_type;
496 u16 board_type;
497 u16 supported_type;
498
499 u16 link_speed;
500 u16 link_duplex;
501 u16 link_autoneg;
502 u16 module_type;
503
504 u16 op_mode;
505 u16 switch_mode;
506 u16 max_tx_ques;
507 u16 max_rx_ques;
508 u16 max_mtu;
509 u32 msg_enable;
510 u16 total_nic_func;
511 u16 max_pci_func;
512 u32 max_vnic_func;
513 u32 total_pci_func;
514
515 u32 capabilities;
516 u32 extra_capability[3];
517 u32 temp;
518 u32 int_vec_bit;
519 u32 fw_hal_version;
520 u32 port_config;
521 struct qlcnic_hardware_ops *hw_ops;
522 struct qlcnic_nic_intr_coalesce coal;
523 struct qlcnic_fw_dump fw_dump;
524 struct qlcnic_fdt fdt;
525 struct qlc_83xx_reset reset;
526 struct qlc_83xx_idc idc;
527 struct qlc_83xx_fw_info *fw_info;
528 struct qlcnic_intrpt_config *intr_tbl;
529 struct qlcnic_sriov *sriov;
530 u32 *reg_tbl;
531 u32 *ext_reg_tbl;
532 u32 mbox_aen[QLC_83XX_MBX_AEN_CNT];
533 u32 mbox_reg[4];
534 struct qlcnic_mailbox *mailbox;
535 u8 extend_lb_time;
536 u8 phys_port_id[ETH_ALEN];
537 u8 lb_mode;
538 u16 vxlan_port;
539 };
540
541 struct qlcnic_adapter_stats {
542 u64 xmitcalled;
543 u64 xmitfinished;
544 u64 rxdropped;
545 u64 txdropped;
546 u64 csummed;
547 u64 rx_pkts;
548 u64 lro_pkts;
549 u64 rxbytes;
550 u64 txbytes;
551 u64 lrobytes;
552 u64 lso_frames;
553 u64 encap_lso_frames;
554 u64 encap_tx_csummed;
555 u64 encap_rx_csummed;
556 u64 xmit_on;
557 u64 xmit_off;
558 u64 skb_alloc_failure;
559 u64 null_rxbuf;
560 u64 rx_dma_map_error;
561 u64 tx_dma_map_error;
562 u64 spurious_intr;
563 u64 mac_filter_limit_overrun;
564 };
565
566 /*
567 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
568 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
569 */
570 struct qlcnic_host_rds_ring {
571 void __iomem *crb_rcv_producer;
572 struct rcv_desc *desc_head;
573 struct qlcnic_rx_buffer *rx_buf_arr;
574 u32 num_desc;
575 u32 producer;
576 u32 dma_size;
577 u32 skb_size;
578 u32 flags;
579 struct list_head free_list;
580 spinlock_t lock;
581 dma_addr_t phys_addr;
582 } ____cacheline_internodealigned_in_smp;
583
584 struct qlcnic_host_sds_ring {
585 u32 consumer;
586 u32 num_desc;
587 void __iomem *crb_sts_consumer;
588
589 struct qlcnic_host_tx_ring *tx_ring;
590 struct status_desc *desc_head;
591 struct qlcnic_adapter *adapter;
592 struct napi_struct napi;
593 struct list_head free_list[NUM_RCV_DESC_RINGS];
594
595 void __iomem *crb_intr_mask;
596 int irq;
597
598 dma_addr_t phys_addr;
599 char name[IFNAMSIZ + 12];
600 } ____cacheline_internodealigned_in_smp;
601
602 struct qlcnic_tx_queue_stats {
603 u64 xmit_on;
604 u64 xmit_off;
605 u64 xmit_called;
606 u64 xmit_finished;
607 u64 tx_bytes;
608 };
609
610 struct qlcnic_host_tx_ring {
611 int irq;
612 void __iomem *crb_intr_mask;
613 char name[IFNAMSIZ + 12];
614 u16 ctx_id;
615
616 u32 state;
617 u32 producer;
618 u32 sw_consumer;
619 u32 num_desc;
620
621 struct qlcnic_tx_queue_stats tx_stats;
622
623 void __iomem *crb_cmd_producer;
624 struct cmd_desc_type0 *desc_head;
625 struct qlcnic_adapter *adapter;
626 struct napi_struct napi;
627 struct qlcnic_cmd_buffer *cmd_buf_arr;
628 __le32 *hw_consumer;
629
630 dma_addr_t phys_addr;
631 dma_addr_t hw_cons_phys_addr;
632 struct netdev_queue *txq;
633 /* Lock to protect Tx descriptors cleanup */
634 spinlock_t tx_clean_lock;
635 } ____cacheline_internodealigned_in_smp;
636
637 /*
638 * Receive context. There is one such structure per instance of the
639 * receive processing. Any state information that is relevant to
640 * the receive, and is must be in this structure. The global data may be
641 * present elsewhere.
642 */
643 struct qlcnic_recv_context {
644 struct qlcnic_host_rds_ring *rds_rings;
645 struct qlcnic_host_sds_ring *sds_rings;
646 u32 state;
647 u16 context_id;
648 u16 virt_port;
649 };
650
651 /* HW context creation */
652
653 #define QLCNIC_OS_CRB_RETRY_COUNT 4000
654
655 #define QLCNIC_CDRP_CMD_BIT 0x80000000
656
657 /*
658 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared
659 * in the crb QLCNIC_CDRP_CRB_OFFSET.
660 */
661 #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp)
662 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0)
663
664 #define QLCNIC_CDRP_RSP_OK 0x00000001
665 #define QLCNIC_CDRP_RSP_FAIL 0x00000002
666 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003
667
668 /*
669 * All commands must have the QLCNIC_CDRP_CMD_BIT set in
670 * the crb QLCNIC_CDRP_CRB_OFFSET.
671 */
672 #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd))
673
674 #define QLCNIC_RCODE_SUCCESS 0
675 #define QLCNIC_RCODE_INVALID_ARGS 6
676 #define QLCNIC_RCODE_NOT_SUPPORTED 9
677 #define QLCNIC_RCODE_NOT_PERMITTED 10
678 #define QLCNIC_RCODE_NOT_IMPL 15
679 #define QLCNIC_RCODE_INVALID 16
680 #define QLCNIC_RCODE_TIMEOUT 17
681 #define QLCNIC_DESTROY_CTX_RESET 0
682
683 /*
684 * Capabilities Announced
685 */
686 #define QLCNIC_CAP0_LEGACY_CONTEXT (1)
687 #define QLCNIC_CAP0_LEGACY_MN (1 << 2)
688 #define QLCNIC_CAP0_LSO (1 << 6)
689 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7)
690 #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8)
691 #define QLCNIC_CAP0_VALIDOFF (1 << 11)
692 #define QLCNIC_CAP0_LRO_MSS (1 << 21)
693 #define QLCNIC_CAP0_TX_MULTI (1 << 22)
694
695 /*
696 * Context state
697 */
698 #define QLCNIC_HOST_CTX_STATE_FREED 0
699 #define QLCNIC_HOST_CTX_STATE_ACTIVE 2
700
701 /*
702 * Rx context
703 */
704
705 struct qlcnic_hostrq_sds_ring {
706 __le64 host_phys_addr; /* Ring base addr */
707 __le32 ring_size; /* Ring entries */
708 __le16 msi_index;
709 __le16 rsvd; /* Padding */
710 } __packed;
711
712 struct qlcnic_hostrq_rds_ring {
713 __le64 host_phys_addr; /* Ring base addr */
714 __le64 buff_size; /* Packet buffer size */
715 __le32 ring_size; /* Ring entries */
716 __le32 ring_kind; /* Class of ring */
717 } __packed;
718
719 struct qlcnic_hostrq_rx_ctx {
720 __le64 host_rsp_dma_addr; /* Response dma'd here */
721 __le32 capabilities[4]; /* Flag bit vector */
722 __le32 host_int_crb_mode; /* Interrupt crb usage */
723 __le32 host_rds_crb_mode; /* RDS crb usage */
724 /* These ring offsets are relative to data[0] below */
725 __le32 rds_ring_offset; /* Offset to RDS config */
726 __le32 sds_ring_offset; /* Offset to SDS config */
727 __le16 num_rds_rings; /* Count of RDS rings */
728 __le16 num_sds_rings; /* Count of SDS rings */
729 __le16 valid_field_offset;
730 u8 txrx_sds_binding;
731 u8 msix_handler;
732 u8 reserved[128]; /* reserve space for future expansion*/
733 /* MUST BE 64-bit aligned.
734 The following is packed:
735 - N hostrq_rds_rings
736 - N hostrq_sds_rings */
737 char data[0];
738 } __packed;
739
740 struct qlcnic_cardrsp_rds_ring{
741 __le32 host_producer_crb; /* Crb to use */
742 __le32 rsvd1; /* Padding */
743 } __packed;
744
745 struct qlcnic_cardrsp_sds_ring {
746 __le32 host_consumer_crb; /* Crb to use */
747 __le32 interrupt_crb; /* Crb to use */
748 } __packed;
749
750 struct qlcnic_cardrsp_rx_ctx {
751 /* These ring offsets are relative to data[0] below */
752 __le32 rds_ring_offset; /* Offset to RDS config */
753 __le32 sds_ring_offset; /* Offset to SDS config */
754 __le32 host_ctx_state; /* Starting State */
755 __le32 num_fn_per_port; /* How many PCI fn share the port */
756 __le16 num_rds_rings; /* Count of RDS rings */
757 __le16 num_sds_rings; /* Count of SDS rings */
758 __le16 context_id; /* Handle for context */
759 u8 phys_port; /* Physical id of port */
760 u8 virt_port; /* Virtual/Logical id of port */
761 u8 reserved[128]; /* save space for future expansion */
762 /* MUST BE 64-bit aligned.
763 The following is packed:
764 - N cardrsp_rds_rings
765 - N cardrs_sds_rings */
766 char data[0];
767 } __packed;
768
769 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
770 (sizeof(HOSTRQ_RX) + \
771 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \
772 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring)))
773
774 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
775 (sizeof(CARDRSP_RX) + \
776 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \
777 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring)))
778
779 /*
780 * Tx context
781 */
782
783 struct qlcnic_hostrq_cds_ring {
784 __le64 host_phys_addr; /* Ring base addr */
785 __le32 ring_size; /* Ring entries */
786 __le32 rsvd; /* Padding */
787 } __packed;
788
789 struct qlcnic_hostrq_tx_ctx {
790 __le64 host_rsp_dma_addr; /* Response dma'd here */
791 __le64 cmd_cons_dma_addr; /* */
792 __le64 dummy_dma_addr; /* */
793 __le32 capabilities[4]; /* Flag bit vector */
794 __le32 host_int_crb_mode; /* Interrupt crb usage */
795 __le32 rsvd1; /* Padding */
796 __le16 rsvd2; /* Padding */
797 __le16 interrupt_ctl;
798 __le16 msi_index;
799 __le16 rsvd3; /* Padding */
800 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */
801 u8 reserved[128]; /* future expansion */
802 } __packed;
803
804 struct qlcnic_cardrsp_cds_ring {
805 __le32 host_producer_crb; /* Crb to use */
806 __le32 interrupt_crb; /* Crb to use */
807 } __packed;
808
809 struct qlcnic_cardrsp_tx_ctx {
810 __le32 host_ctx_state; /* Starting state */
811 __le16 context_id; /* Handle for context */
812 u8 phys_port; /* Physical id of port */
813 u8 virt_port; /* Virtual/Logical id of port */
814 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */
815 u8 reserved[128]; /* future expansion */
816 } __packed;
817
818 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
819 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
820
821 /* CRB */
822
823 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0
824 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1
825 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2
826 #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3
827
828 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0
829 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1
830 #define QLCNIC_HOST_INT_CRB_MODE_NORX 2
831 #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3
832 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4
833
834
835 /* MAC */
836
837 #define MC_COUNT_P3P 38
838
839 #define QLCNIC_MAC_NOOP 0
840 #define QLCNIC_MAC_ADD 1
841 #define QLCNIC_MAC_DEL 2
842 #define QLCNIC_MAC_VLAN_ADD 3
843 #define QLCNIC_MAC_VLAN_DEL 4
844
845 struct qlcnic_mac_vlan_list {
846 struct list_head list;
847 uint8_t mac_addr[ETH_ALEN+2];
848 u16 vlan_id;
849 };
850
851 /* MAC Learn */
852 #define NO_MAC_LEARN 0
853 #define DRV_MAC_LEARN 1
854 #define FDB_MAC_LEARN 2
855
856 #define QLCNIC_HOST_REQUEST 0x13
857 #define QLCNIC_REQUEST 0x14
858
859 #define QLCNIC_MAC_EVENT 0x1
860
861 #define QLCNIC_IP_UP 2
862 #define QLCNIC_IP_DOWN 3
863
864 #define QLCNIC_ILB_MODE 0x1
865 #define QLCNIC_ELB_MODE 0x2
866 #define QLCNIC_LB_MODE_MASK 0x3
867
868 #define QLCNIC_LINKEVENT 0x1
869 #define QLCNIC_LB_RESPONSE 0x2
870 #define QLCNIC_IS_LB_CONFIGURED(VAL) \
871 (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE))
872
873 /*
874 * Driver --> Firmware
875 */
876 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1
877 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3
878 #define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4
879 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7
880 #define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc
881 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12
882
883 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15
884 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17
885 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18
886 #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 0x13
887
888 /*
889 * Firmware --> Driver
890 */
891
892 #define QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK 0x8f
893 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 0x8D
894 #define QLCNIC_C2H_OPCODE_GET_DCB_AEN 0x90
895
896 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
897 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
898 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
899
900 #define QLCNIC_LRO_REQUEST_CLEANUP 4
901
902 /* Capabilites received */
903 #define QLCNIC_FW_CAPABILITY_TSO BIT_1
904 #define QLCNIC_FW_CAPABILITY_BDG BIT_8
905 #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9
906 #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10
907 #define QLCNIC_FW_CAPABILITY_2_MULTI_TX BIT_4
908 #define QLCNIC_FW_CAPABILITY_MULTI_LOOPBACK BIT_27
909 #define QLCNIC_FW_CAPABILITY_MORE_CAPS BIT_31
910
911 #define QLCNIC_FW_CAPABILITY_2_LRO_MAX_TCP_SEG BIT_2
912 #define QLCNIC_FW_CAP2_HW_LRO_IPV6 BIT_3
913 #define QLCNIC_FW_CAPABILITY_SET_DRV_VER BIT_5
914 #define QLCNIC_FW_CAPABILITY_2_BEACON BIT_7
915 #define QLCNIC_FW_CAPABILITY_2_PER_PORT_ESWITCH_CFG BIT_9
916
917 #define QLCNIC_83XX_FW_CAPAB_ENCAP_RX_OFFLOAD BIT_0
918 #define QLCNIC_83XX_FW_CAPAB_ENCAP_TX_OFFLOAD BIT_1
919 #define QLCNIC_83XX_FW_CAPAB_ENCAP_CKO_OFFLOAD BIT_4
920
921 /* module types */
922 #define LINKEVENT_MODULE_NOT_PRESENT 1
923 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
924 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
925 #define LINKEVENT_MODULE_OPTICAL_LRM 4
926 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
927 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
928 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
929 #define LINKEVENT_MODULE_TWINAX 8
930
931 #define LINKSPEED_10GBPS 10000
932 #define LINKSPEED_1GBPS 1000
933 #define LINKSPEED_100MBPS 100
934 #define LINKSPEED_10MBPS 10
935
936 #define LINKSPEED_ENCODED_10MBPS 0
937 #define LINKSPEED_ENCODED_100MBPS 1
938 #define LINKSPEED_ENCODED_1GBPS 2
939
940 #define LINKEVENT_AUTONEG_DISABLED 0
941 #define LINKEVENT_AUTONEG_ENABLED 1
942
943 #define LINKEVENT_HALF_DUPLEX 0
944 #define LINKEVENT_FULL_DUPLEX 1
945
946 #define LINKEVENT_LINKSPEED_MBPS 0
947 #define LINKEVENT_LINKSPEED_ENCODED 1
948
949 /* firmware response header:
950 * 63:58 - message type
951 * 57:56 - owner
952 * 55:53 - desc count
953 * 52:48 - reserved
954 * 47:40 - completion id
955 * 39:32 - opcode
956 * 31:16 - error code
957 * 15:00 - reserved
958 */
959 #define qlcnic_get_nic_msg_opcode(msg_hdr) \
960 ((msg_hdr >> 32) & 0xFF)
961
962 struct qlcnic_fw_msg {
963 union {
964 struct {
965 u64 hdr;
966 u64 body[7];
967 };
968 u64 words[8];
969 };
970 };
971
972 struct qlcnic_nic_req {
973 __le64 qhdr;
974 __le64 req_hdr;
975 __le64 words[6];
976 } __packed;
977
978 struct qlcnic_mac_req {
979 u8 op;
980 u8 tag;
981 u8 mac_addr[6];
982 };
983
984 struct qlcnic_vlan_req {
985 __le16 vlan_id;
986 __le16 rsvd[3];
987 } __packed;
988
989 struct qlcnic_ipaddr {
990 __be32 ipv4;
991 __be32 ipv6[4];
992 };
993
994 #define QLCNIC_MSI_ENABLED 0x02
995 #define QLCNIC_MSIX_ENABLED 0x04
996 #define QLCNIC_LRO_ENABLED 0x01
997 #define QLCNIC_LRO_DISABLED 0x00
998 #define QLCNIC_BRIDGE_ENABLED 0X10
999 #define QLCNIC_DIAG_ENABLED 0x20
1000 #define QLCNIC_ESWITCH_ENABLED 0x40
1001 #define QLCNIC_ADAPTER_INITIALIZED 0x80
1002 #define QLCNIC_TAGGING_ENABLED 0x100
1003 #define QLCNIC_MACSPOOF 0x200
1004 #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400
1005 #define QLCNIC_PROMISC_DISABLED 0x800
1006 #define QLCNIC_NEED_FLR 0x1000
1007 #define QLCNIC_FW_RESET_OWNER 0x2000
1008 #define QLCNIC_FW_HANG 0x4000
1009 #define QLCNIC_FW_LRO_MSS_CAP 0x8000
1010 #define QLCNIC_TX_INTR_SHARED 0x10000
1011 #define QLCNIC_APP_CHANGED_FLAGS 0x20000
1012 #define QLCNIC_HAS_PHYS_PORT_ID 0x40000
1013 #define QLCNIC_TSS_RSS 0x80000
1014 #define QLCNIC_ADD_VXLAN_PORT 0x100000
1015 #define QLCNIC_DEL_VXLAN_PORT 0x200000
1016
1017 #define QLCNIC_IS_MSI_FAMILY(adapter) \
1018 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
1019 #define QLCNIC_IS_TSO_CAPABLE(adapter) \
1020 ((adapter)->ahw->capabilities & QLCNIC_FW_CAPABILITY_TSO)
1021
1022 #define QLCNIC_BEACON_EANBLE 0xC
1023 #define QLCNIC_BEACON_DISABLE 0xD
1024
1025 #define QLCNIC_BEACON_ON 2
1026 #define QLCNIC_BEACON_OFF 0
1027
1028 #define QLCNIC_MSIX_TBL_SPACE 8192
1029 #define QLCNIC_PCI_REG_MSIX_TBL 0x44
1030 #define QLCNIC_MSIX_TBL_PGSIZE 4096
1031
1032 #define QLCNIC_ADAPTER_UP_MAGIC 777
1033
1034 #define __QLCNIC_FW_ATTACHED 0
1035 #define __QLCNIC_DEV_UP 1
1036 #define __QLCNIC_RESETTING 2
1037 #define __QLCNIC_START_FW 4
1038 #define __QLCNIC_AER 5
1039 #define __QLCNIC_DIAG_RES_ALLOC 6
1040 #define __QLCNIC_LED_ENABLE 7
1041 #define __QLCNIC_ELB_INPROGRESS 8
1042 #define __QLCNIC_MULTI_TX_UNIQUE 9
1043 #define __QLCNIC_SRIOV_ENABLE 10
1044 #define __QLCNIC_SRIOV_CAPABLE 11
1045 #define __QLCNIC_MBX_POLL_ENABLE 12
1046 #define __QLCNIC_DIAG_MODE 13
1047 #define __QLCNIC_MAINTENANCE_MODE 16
1048
1049 #define QLCNIC_INTERRUPT_TEST 1
1050 #define QLCNIC_LOOPBACK_TEST 2
1051 #define QLCNIC_LED_TEST 3
1052
1053 #define QLCNIC_FILTER_AGE 80
1054 #define QLCNIC_READD_AGE 20
1055 #define QLCNIC_LB_MAX_FILTERS 64
1056 #define QLCNIC_LB_BUCKET_SIZE 32
1057 #define QLCNIC_ILB_MAX_RCV_LOOP 10
1058
1059 struct qlcnic_filter {
1060 struct hlist_node fnode;
1061 u8 faddr[ETH_ALEN];
1062 u16 vlan_id;
1063 unsigned long ftime;
1064 };
1065
1066 struct qlcnic_filter_hash {
1067 struct hlist_head *fhead;
1068 u8 fnum;
1069 u16 fmax;
1070 u16 fbucket_size;
1071 };
1072
1073 /* Mailbox specific data structures */
1074 struct qlcnic_mailbox {
1075 struct workqueue_struct *work_q;
1076 struct qlcnic_adapter *adapter;
1077 struct qlcnic_mbx_ops *ops;
1078 struct work_struct work;
1079 struct completion completion;
1080 struct list_head cmd_q;
1081 unsigned long status;
1082 spinlock_t queue_lock; /* Mailbox queue lock */
1083 spinlock_t aen_lock; /* Mailbox response/AEN lock */
1084 atomic_t rsp_status;
1085 u32 num_cmds;
1086 };
1087
1088 struct qlcnic_adapter {
1089 struct qlcnic_hardware_context *ahw;
1090 struct qlcnic_recv_context *recv_ctx;
1091 struct qlcnic_host_tx_ring *tx_ring;
1092 struct net_device *netdev;
1093 struct pci_dev *pdev;
1094
1095 unsigned long state;
1096 u32 flags;
1097
1098 u16 num_txd;
1099 u16 num_rxd;
1100 u16 num_jumbo_rxd;
1101 u16 max_rxd;
1102 u16 max_jumbo_rxd;
1103
1104 u8 max_rds_rings;
1105
1106 u8 max_sds_rings; /* max sds rings supported by adapter */
1107 u8 max_tx_rings; /* max tx rings supported by adapter */
1108
1109 u8 drv_tx_rings; /* max tx rings supported by driver */
1110 u8 drv_sds_rings; /* max sds rings supported by driver */
1111
1112 u8 drv_tss_rings; /* tss ring input */
1113 u8 drv_rss_rings; /* rss ring input */
1114
1115 u8 rx_csum;
1116 u8 portnum;
1117
1118 u8 fw_wait_cnt;
1119 u8 fw_fail_cnt;
1120 u8 tx_timeo_cnt;
1121 u8 need_fw_reset;
1122 u8 reset_ctx_cnt;
1123
1124 u16 is_up;
1125 u16 rx_pvid;
1126 u16 tx_pvid;
1127
1128 u32 irq;
1129 u32 heartbeat;
1130
1131 u8 dev_state;
1132 u8 reset_ack_timeo;
1133 u8 dev_init_timeo;
1134
1135 u8 mac_addr[ETH_ALEN];
1136
1137 u64 dev_rst_time;
1138 bool drv_mac_learn;
1139 bool fdb_mac_learn;
1140 bool rx_mac_learn;
1141 unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)];
1142 u8 flash_mfg_id;
1143 struct qlcnic_npar_info *npars;
1144 struct qlcnic_eswitch *eswitch;
1145 struct qlcnic_nic_template *nic_ops;
1146
1147 struct qlcnic_adapter_stats stats;
1148 struct list_head mac_list;
1149
1150 void __iomem *tgt_mask_reg;
1151 void __iomem *tgt_status_reg;
1152 void __iomem *crb_int_state_reg;
1153 void __iomem *isr_int_vec;
1154
1155 struct msix_entry *msix_entries;
1156 struct workqueue_struct *qlcnic_wq;
1157 struct delayed_work fw_work;
1158 struct delayed_work idc_aen_work;
1159 struct delayed_work mbx_poll_work;
1160 struct qlcnic_dcb *dcb;
1161
1162 struct qlcnic_filter_hash fhash;
1163 struct qlcnic_filter_hash rx_fhash;
1164 struct list_head vf_mc_list;
1165
1166 spinlock_t mac_learn_lock;
1167 /* spinlock for catching rcv filters for eswitch traffic */
1168 spinlock_t rx_mac_learn_lock;
1169 u32 file_prd_off; /*File fw product offset*/
1170 u32 fw_version;
1171 u32 offload_flags;
1172 const struct firmware *fw;
1173 };
1174
1175 struct qlcnic_info_le {
1176 __le16 pci_func;
1177 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */
1178 __le16 phys_port;
1179 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */
1180
1181 __le32 capabilities;
1182 u8 max_mac_filters;
1183 u8 reserved1;
1184 __le16 max_mtu;
1185
1186 __le16 max_tx_ques;
1187 __le16 max_rx_ques;
1188 __le16 min_tx_bw;
1189 __le16 max_tx_bw;
1190 __le32 op_type;
1191 __le16 max_bw_reg_offset;
1192 __le16 max_linkspeed_reg_offset;
1193 __le32 capability1;
1194 __le32 capability2;
1195 __le32 capability3;
1196 __le16 max_tx_mac_filters;
1197 __le16 max_rx_mcast_mac_filters;
1198 __le16 max_rx_ucast_mac_filters;
1199 __le16 max_rx_ip_addr;
1200 __le16 max_rx_lro_flow;
1201 __le16 max_rx_status_rings;
1202 __le16 max_rx_buf_rings;
1203 __le16 max_tx_vlan_keys;
1204 u8 total_pf;
1205 u8 total_rss_engines;
1206 __le16 max_vports;
1207 __le16 linkstate_reg_offset;
1208 __le16 bit_offsets;
1209 __le16 max_local_ipv6_addrs;
1210 __le16 max_remote_ipv6_addrs;
1211 u8 reserved2[56];
1212 } __packed;
1213
1214 struct qlcnic_info {
1215 u16 pci_func;
1216 u16 op_mode;
1217 u16 phys_port;
1218 u16 switch_mode;
1219 u32 capabilities;
1220 u8 max_mac_filters;
1221 u16 max_mtu;
1222 u16 max_tx_ques;
1223 u16 max_rx_ques;
1224 u16 min_tx_bw;
1225 u16 max_tx_bw;
1226 u32 op_type;
1227 u16 max_bw_reg_offset;
1228 u16 max_linkspeed_reg_offset;
1229 u32 capability1;
1230 u32 capability2;
1231 u32 capability3;
1232 u16 max_tx_mac_filters;
1233 u16 max_rx_mcast_mac_filters;
1234 u16 max_rx_ucast_mac_filters;
1235 u16 max_rx_ip_addr;
1236 u16 max_rx_lro_flow;
1237 u16 max_rx_status_rings;
1238 u16 max_rx_buf_rings;
1239 u16 max_tx_vlan_keys;
1240 u8 total_pf;
1241 u8 total_rss_engines;
1242 u16 max_vports;
1243 u16 linkstate_reg_offset;
1244 u16 bit_offsets;
1245 u16 max_local_ipv6_addrs;
1246 u16 max_remote_ipv6_addrs;
1247 };
1248
1249 struct qlcnic_pci_info_le {
1250 __le16 id; /* pci function id */
1251 __le16 active; /* 1 = Enabled */
1252 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */
1253 __le16 default_port; /* default port number */
1254
1255 __le16 tx_min_bw; /* Multiple of 100mbpc */
1256 __le16 tx_max_bw;
1257 __le16 reserved1[2];
1258
1259 u8 mac[ETH_ALEN];
1260 __le16 func_count;
1261 u8 reserved2[104];
1262
1263 } __packed;
1264
1265 struct qlcnic_pci_info {
1266 u16 id;
1267 u16 active;
1268 u16 type;
1269 u16 default_port;
1270 u16 tx_min_bw;
1271 u16 tx_max_bw;
1272 u8 mac[ETH_ALEN];
1273 u16 func_count;
1274 };
1275
1276 struct qlcnic_npar_info {
1277 bool eswitch_status;
1278 u16 pvid;
1279 u16 min_bw;
1280 u16 max_bw;
1281 u8 phy_port;
1282 u8 type;
1283 u8 active;
1284 u8 enable_pm;
1285 u8 dest_npar;
1286 u8 discard_tagged;
1287 u8 mac_override;
1288 u8 mac_anti_spoof;
1289 u8 promisc_mode;
1290 u8 offload_flags;
1291 u8 pci_func;
1292 u8 mac[ETH_ALEN];
1293 };
1294
1295 struct qlcnic_eswitch {
1296 u8 port;
1297 u8 active_vports;
1298 u8 active_vlans;
1299 u8 active_ucast_filters;
1300 u8 max_ucast_filters;
1301 u8 max_active_vlans;
1302
1303 u32 flags;
1304 #define QLCNIC_SWITCH_ENABLE BIT_1
1305 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2
1306 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3
1307 #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4
1308 };
1309
1310
1311 /* Return codes for Error handling */
1312 #define QL_STATUS_INVALID_PARAM -1
1313
1314 #define MAX_BW 100 /* % of link speed */
1315 #define MAX_VLAN_ID 4095
1316 #define MIN_VLAN_ID 2
1317 #define DEFAULT_MAC_LEARN 1
1318
1319 #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID)
1320 #define IS_VALID_BW(bw) (bw <= MAX_BW)
1321
1322 struct qlcnic_pci_func_cfg {
1323 u16 func_type;
1324 u16 min_bw;
1325 u16 max_bw;
1326 u16 port_num;
1327 u8 pci_func;
1328 u8 func_state;
1329 u8 def_mac_addr[ETH_ALEN];
1330 };
1331
1332 struct qlcnic_npar_func_cfg {
1333 u32 fw_capab;
1334 u16 port_num;
1335 u16 min_bw;
1336 u16 max_bw;
1337 u16 max_tx_queues;
1338 u16 max_rx_queues;
1339 u8 pci_func;
1340 u8 op_mode;
1341 };
1342
1343 struct qlcnic_pm_func_cfg {
1344 u8 pci_func;
1345 u8 action;
1346 u8 dest_npar;
1347 u8 reserved[5];
1348 };
1349
1350 struct qlcnic_esw_func_cfg {
1351 u16 vlan_id;
1352 u8 op_mode;
1353 u8 op_type;
1354 u8 pci_func;
1355 u8 host_vlan_tag;
1356 u8 promisc_mode;
1357 u8 discard_tagged;
1358 u8 mac_override;
1359 u8 mac_anti_spoof;
1360 u8 offload_flags;
1361 u8 reserved[5];
1362 };
1363
1364 #define QLCNIC_STATS_VERSION 1
1365 #define QLCNIC_STATS_PORT 1
1366 #define QLCNIC_STATS_ESWITCH 2
1367 #define QLCNIC_QUERY_RX_COUNTER 0
1368 #define QLCNIC_QUERY_TX_COUNTER 1
1369 #define QLCNIC_STATS_NOT_AVAIL 0xffffffffffffffffULL
1370 #define QLCNIC_FILL_STATS(VAL1) \
1371 (((VAL1) == QLCNIC_STATS_NOT_AVAIL) ? 0 : VAL1)
1372 #define QLCNIC_MAC_STATS 1
1373 #define QLCNIC_ESW_STATS 2
1374
1375 #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\
1376 do { \
1377 if (((VAL1) == QLCNIC_STATS_NOT_AVAIL) && \
1378 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \
1379 (VAL1) = (VAL2); \
1380 else if (((VAL1) != QLCNIC_STATS_NOT_AVAIL) && \
1381 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \
1382 (VAL1) += (VAL2); \
1383 } while (0)
1384
1385 struct qlcnic_mac_statistics_le {
1386 __le64 mac_tx_frames;
1387 __le64 mac_tx_bytes;
1388 __le64 mac_tx_mcast_pkts;
1389 __le64 mac_tx_bcast_pkts;
1390 __le64 mac_tx_pause_cnt;
1391 __le64 mac_tx_ctrl_pkt;
1392 __le64 mac_tx_lt_64b_pkts;
1393 __le64 mac_tx_lt_127b_pkts;
1394 __le64 mac_tx_lt_255b_pkts;
1395 __le64 mac_tx_lt_511b_pkts;
1396 __le64 mac_tx_lt_1023b_pkts;
1397 __le64 mac_tx_lt_1518b_pkts;
1398 __le64 mac_tx_gt_1518b_pkts;
1399 __le64 rsvd1[3];
1400
1401 __le64 mac_rx_frames;
1402 __le64 mac_rx_bytes;
1403 __le64 mac_rx_mcast_pkts;
1404 __le64 mac_rx_bcast_pkts;
1405 __le64 mac_rx_pause_cnt;
1406 __le64 mac_rx_ctrl_pkt;
1407 __le64 mac_rx_lt_64b_pkts;
1408 __le64 mac_rx_lt_127b_pkts;
1409 __le64 mac_rx_lt_255b_pkts;
1410 __le64 mac_rx_lt_511b_pkts;
1411 __le64 mac_rx_lt_1023b_pkts;
1412 __le64 mac_rx_lt_1518b_pkts;
1413 __le64 mac_rx_gt_1518b_pkts;
1414 __le64 rsvd2[3];
1415
1416 __le64 mac_rx_length_error;
1417 __le64 mac_rx_length_small;
1418 __le64 mac_rx_length_large;
1419 __le64 mac_rx_jabber;
1420 __le64 mac_rx_dropped;
1421 __le64 mac_rx_crc_error;
1422 __le64 mac_align_error;
1423 } __packed;
1424
1425 struct qlcnic_mac_statistics {
1426 u64 mac_tx_frames;
1427 u64 mac_tx_bytes;
1428 u64 mac_tx_mcast_pkts;
1429 u64 mac_tx_bcast_pkts;
1430 u64 mac_tx_pause_cnt;
1431 u64 mac_tx_ctrl_pkt;
1432 u64 mac_tx_lt_64b_pkts;
1433 u64 mac_tx_lt_127b_pkts;
1434 u64 mac_tx_lt_255b_pkts;
1435 u64 mac_tx_lt_511b_pkts;
1436 u64 mac_tx_lt_1023b_pkts;
1437 u64 mac_tx_lt_1518b_pkts;
1438 u64 mac_tx_gt_1518b_pkts;
1439 u64 rsvd1[3];
1440 u64 mac_rx_frames;
1441 u64 mac_rx_bytes;
1442 u64 mac_rx_mcast_pkts;
1443 u64 mac_rx_bcast_pkts;
1444 u64 mac_rx_pause_cnt;
1445 u64 mac_rx_ctrl_pkt;
1446 u64 mac_rx_lt_64b_pkts;
1447 u64 mac_rx_lt_127b_pkts;
1448 u64 mac_rx_lt_255b_pkts;
1449 u64 mac_rx_lt_511b_pkts;
1450 u64 mac_rx_lt_1023b_pkts;
1451 u64 mac_rx_lt_1518b_pkts;
1452 u64 mac_rx_gt_1518b_pkts;
1453 u64 rsvd2[3];
1454 u64 mac_rx_length_error;
1455 u64 mac_rx_length_small;
1456 u64 mac_rx_length_large;
1457 u64 mac_rx_jabber;
1458 u64 mac_rx_dropped;
1459 u64 mac_rx_crc_error;
1460 u64 mac_align_error;
1461 };
1462
1463 struct qlcnic_esw_stats_le {
1464 __le16 context_id;
1465 __le16 version;
1466 __le16 size;
1467 __le16 unused;
1468 __le64 unicast_frames;
1469 __le64 multicast_frames;
1470 __le64 broadcast_frames;
1471 __le64 dropped_frames;
1472 __le64 errors;
1473 __le64 local_frames;
1474 __le64 numbytes;
1475 __le64 rsvd[3];
1476 } __packed;
1477
1478 struct __qlcnic_esw_statistics {
1479 u16 context_id;
1480 u16 version;
1481 u16 size;
1482 u16 unused;
1483 u64 unicast_frames;
1484 u64 multicast_frames;
1485 u64 broadcast_frames;
1486 u64 dropped_frames;
1487 u64 errors;
1488 u64 local_frames;
1489 u64 numbytes;
1490 u64 rsvd[3];
1491 };
1492
1493 struct qlcnic_esw_statistics {
1494 struct __qlcnic_esw_statistics rx;
1495 struct __qlcnic_esw_statistics tx;
1496 };
1497
1498 #define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed
1499 #define QLCNIC_ENABLE_FW_DUMP 0xaddfeed
1500 #define QLCNIC_DISABLE_FW_DUMP 0xbadfeed
1501 #define QLCNIC_FORCE_FW_RESET 0xdeaddead
1502 #define QLCNIC_SET_QUIESCENT 0xadd00010
1503 #define QLCNIC_RESET_QUIESCENT 0xadd00020
1504
1505 struct _cdrp_cmd {
1506 u32 num;
1507 u32 *arg;
1508 };
1509
1510 struct qlcnic_cmd_args {
1511 struct completion completion;
1512 struct list_head list;
1513 struct _cdrp_cmd req;
1514 struct _cdrp_cmd rsp;
1515 atomic_t rsp_status;
1516 int pay_size;
1517 u32 rsp_opcode;
1518 u32 total_cmds;
1519 u32 op_type;
1520 u32 type;
1521 u32 cmd_op;
1522 u32 *hdr; /* Back channel message header */
1523 u32 *pay; /* Back channel message payload */
1524 u8 func_num;
1525 };
1526
1527 int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter);
1528 int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config);
1529 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data);
1530 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data);
1531
1532 #define ADDR_IN_RANGE(addr, low, high) \
1533 (((addr) < (high)) && ((addr) >= (low)))
1534
1535 #define QLCRD32(adapter, off, err) \
1536 (adapter->ahw->hw_ops->read_reg)(adapter, off, err)
1537
1538 #define QLCWR32(adapter, off, val) \
1539 adapter->ahw->hw_ops->write_reg(adapter, off, val)
1540
1541 int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32);
1542 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int);
1543
1544 #define qlcnic_rom_lock(a) \
1545 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID)
1546 #define qlcnic_rom_unlock(a) \
1547 qlcnic_pcie_sem_unlock((a), 2)
1548 #define qlcnic_phy_lock(a) \
1549 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID)
1550 #define qlcnic_phy_unlock(a) \
1551 qlcnic_pcie_sem_unlock((a), 3)
1552 #define qlcnic_sw_lock(a) \
1553 qlcnic_pcie_sem_lock((a), 6, 0)
1554 #define qlcnic_sw_unlock(a) \
1555 qlcnic_pcie_sem_unlock((a), 6)
1556 #define crb_win_lock(a) \
1557 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID)
1558 #define crb_win_unlock(a) \
1559 qlcnic_pcie_sem_unlock((a), 7)
1560
1561 #define __QLCNIC_MAX_LED_RATE 0xf
1562 #define __QLCNIC_MAX_LED_STATE 0x2
1563
1564 #define MAX_CTL_CHECK 1000
1565
1566 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter);
1567 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter);
1568 int qlcnic_dump_fw(struct qlcnic_adapter *);
1569 int qlcnic_enable_fw_dump_state(struct qlcnic_adapter *);
1570 bool qlcnic_check_fw_dump_state(struct qlcnic_adapter *);
1571
1572 /* Functions from qlcnic_init.c */
1573 void qlcnic_schedule_work(struct qlcnic_adapter *, work_func_t, int);
1574 int qlcnic_load_firmware(struct qlcnic_adapter *adapter);
1575 int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter);
1576 void qlcnic_request_firmware(struct qlcnic_adapter *adapter);
1577 void qlcnic_release_firmware(struct qlcnic_adapter *adapter);
1578 int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter);
1579 int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter);
1580 int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter);
1581
1582 int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp);
1583 int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
1584 u8 *bytes, size_t size);
1585 int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter);
1586 void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter);
1587
1588 void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *, u32);
1589
1590 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter);
1591 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter);
1592
1593 int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter);
1594 void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter);
1595
1596 void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter);
1597 void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter);
1598 void qlcnic_release_tx_buffers(struct qlcnic_adapter *,
1599 struct qlcnic_host_tx_ring *);
1600
1601 int qlcnic_check_fw_status(struct qlcnic_adapter *adapter);
1602 void qlcnic_watchdog_task(struct work_struct *work);
1603 void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter,
1604 struct qlcnic_host_rds_ring *rds_ring, u8 ring_id);
1605 void qlcnic_set_multi(struct net_device *netdev);
1606 int qlcnic_nic_add_mac(struct qlcnic_adapter *, const u8 *, u16);
1607 int qlcnic_nic_del_mac(struct qlcnic_adapter *, const u8 *);
1608 void qlcnic_82xx_free_mac_list(struct qlcnic_adapter *adapter);
1609 int qlcnic_82xx_read_phys_port_id(struct qlcnic_adapter *);
1610
1611 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu);
1612 int qlcnic_fw_cmd_set_drv_version(struct qlcnic_adapter *, u32);
1613 int qlcnic_change_mtu(struct net_device *netdev, int new_mtu);
1614 netdev_features_t qlcnic_fix_features(struct net_device *netdev,
1615 netdev_features_t features);
1616 int qlcnic_set_features(struct net_device *netdev, netdev_features_t features);
1617 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable);
1618 void qlcnic_update_cmd_producer(struct qlcnic_host_tx_ring *);
1619
1620 /* Functions from qlcnic_ethtool.c */
1621 int qlcnic_check_loopback_buff(unsigned char *, u8 []);
1622 int qlcnic_do_lb_test(struct qlcnic_adapter *, u8);
1623
1624 /* Functions from qlcnic_main.c */
1625 int qlcnic_reset_context(struct qlcnic_adapter *);
1626 void qlcnic_diag_free_res(struct net_device *netdev, int);
1627 int qlcnic_diag_alloc_res(struct net_device *netdev, int);
1628 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *, struct net_device *);
1629 void qlcnic_set_tx_ring_count(struct qlcnic_adapter *, u8);
1630 void qlcnic_set_sds_ring_count(struct qlcnic_adapter *, u8);
1631 int qlcnic_setup_rings(struct qlcnic_adapter *);
1632 int qlcnic_validate_rings(struct qlcnic_adapter *, __u32, int);
1633 void qlcnic_alloc_lb_filters_mem(struct qlcnic_adapter *adapter);
1634 int qlcnic_enable_msix(struct qlcnic_adapter *, u32);
1635 void qlcnic_set_drv_version(struct qlcnic_adapter *);
1636
1637 /* eSwitch management functions */
1638 int qlcnic_config_switch_port(struct qlcnic_adapter *,
1639 struct qlcnic_esw_func_cfg *);
1640
1641 int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *,
1642 struct qlcnic_esw_func_cfg *);
1643 int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8);
1644 int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8,
1645 struct __qlcnic_esw_statistics *);
1646 int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8,
1647 struct __qlcnic_esw_statistics *);
1648 int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8);
1649 int qlcnic_get_mac_stats(struct qlcnic_adapter *, struct qlcnic_mac_statistics *);
1650
1651 void qlcnic_free_mbx_args(struct qlcnic_cmd_args *cmd);
1652
1653 int qlcnic_alloc_sds_rings(struct qlcnic_recv_context *, int);
1654 void qlcnic_free_sds_rings(struct qlcnic_recv_context *);
1655 void qlcnic_advert_link_change(struct qlcnic_adapter *, int);
1656 void qlcnic_free_tx_rings(struct qlcnic_adapter *);
1657 int qlcnic_alloc_tx_rings(struct qlcnic_adapter *, struct net_device *);
1658 void qlcnic_dump_mbx(struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1659
1660 void qlcnic_create_sysfs_entries(struct qlcnic_adapter *adapter);
1661 void qlcnic_remove_sysfs_entries(struct qlcnic_adapter *adapter);
1662 void qlcnic_82xx_add_sysfs(struct qlcnic_adapter *adapter);
1663 void qlcnic_82xx_remove_sysfs(struct qlcnic_adapter *adapter);
1664
1665 int qlcnicvf_config_bridged_mode(struct qlcnic_adapter *, u32);
1666 int qlcnicvf_config_led(struct qlcnic_adapter *, u32, u32);
1667 void qlcnic_set_vlan_config(struct qlcnic_adapter *,
1668 struct qlcnic_esw_func_cfg *);
1669 void qlcnic_set_eswitch_port_features(struct qlcnic_adapter *,
1670 struct qlcnic_esw_func_cfg *);
1671 int qlcnic_setup_tss_rss_intr(struct qlcnic_adapter *);
1672 void qlcnic_down(struct qlcnic_adapter *, struct net_device *);
1673 int qlcnic_up(struct qlcnic_adapter *, struct net_device *);
1674 void __qlcnic_down(struct qlcnic_adapter *, struct net_device *);
1675 void qlcnic_detach(struct qlcnic_adapter *);
1676 void qlcnic_teardown_intr(struct qlcnic_adapter *);
1677 int qlcnic_attach(struct qlcnic_adapter *);
1678 int __qlcnic_up(struct qlcnic_adapter *, struct net_device *);
1679 void qlcnic_restore_indev_addr(struct net_device *, unsigned long);
1680
1681 int qlcnic_check_temp(struct qlcnic_adapter *);
1682 int qlcnic_init_pci_info(struct qlcnic_adapter *);
1683 int qlcnic_set_default_offload_settings(struct qlcnic_adapter *);
1684 int qlcnic_reset_npar_config(struct qlcnic_adapter *);
1685 int qlcnic_set_eswitch_port_config(struct qlcnic_adapter *);
1686 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter);
1687 int qlcnic_read_mac_addr(struct qlcnic_adapter *);
1688 int qlcnic_setup_netdev(struct qlcnic_adapter *, struct net_device *, int);
1689 void qlcnic_set_netdev_features(struct qlcnic_adapter *,
1690 struct qlcnic_esw_func_cfg *);
1691 void qlcnic_sriov_vf_schedule_multi(struct net_device *);
1692 int qlcnic_is_valid_nic_func(struct qlcnic_adapter *, u8);
1693 int qlcnic_get_pci_func_type(struct qlcnic_adapter *, u16, u16 *, u16 *,
1694 u16 *);
1695
1696 /*
1697 * QLOGIC Board information
1698 */
1699
1700 #define QLCNIC_MAX_BOARD_NAME_LEN 100
1701 struct qlcnic_board_info {
1702 unsigned short vendor;
1703 unsigned short device;
1704 unsigned short sub_vendor;
1705 unsigned short sub_device;
1706 char short_name[QLCNIC_MAX_BOARD_NAME_LEN];
1707 };
1708
1709 static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring)
1710 {
1711 if (likely(tx_ring->producer < tx_ring->sw_consumer))
1712 return tx_ring->sw_consumer - tx_ring->producer;
1713 else
1714 return tx_ring->sw_consumer + tx_ring->num_desc -
1715 tx_ring->producer;
1716 }
1717
1718 static inline int qlcnic_set_real_num_queues(struct qlcnic_adapter *adapter,
1719 struct net_device *netdev)
1720 {
1721 int err;
1722
1723 netdev->num_tx_queues = adapter->drv_tx_rings;
1724 netdev->real_num_tx_queues = adapter->drv_tx_rings;
1725
1726 err = netif_set_real_num_tx_queues(netdev, adapter->drv_tx_rings);
1727 if (err)
1728 netdev_err(netdev, "failed to set %d Tx queues\n",
1729 adapter->drv_tx_rings);
1730
1731 return err;
1732 }
1733
1734 struct qlcnic_nic_template {
1735 int (*config_bridged_mode) (struct qlcnic_adapter *, u32);
1736 int (*config_led) (struct qlcnic_adapter *, u32, u32);
1737 int (*start_firmware) (struct qlcnic_adapter *);
1738 int (*init_driver) (struct qlcnic_adapter *);
1739 void (*request_reset) (struct qlcnic_adapter *, u32);
1740 void (*cancel_idc_work) (struct qlcnic_adapter *);
1741 int (*napi_add)(struct qlcnic_adapter *, struct net_device *);
1742 void (*napi_del)(struct qlcnic_adapter *);
1743 void (*config_ipaddr)(struct qlcnic_adapter *, __be32, int);
1744 irqreturn_t (*clear_legacy_intr)(struct qlcnic_adapter *);
1745 int (*shutdown)(struct pci_dev *);
1746 int (*resume)(struct qlcnic_adapter *);
1747 };
1748
1749 struct qlcnic_mbx_ops {
1750 int (*enqueue_cmd) (struct qlcnic_adapter *,
1751 struct qlcnic_cmd_args *, unsigned long *);
1752 void (*dequeue_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1753 void (*decode_resp) (struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1754 void (*encode_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1755 void (*nofity_fw) (struct qlcnic_adapter *, u8);
1756 };
1757
1758 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *);
1759 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *);
1760 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx);
1761 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx);
1762 void qlcnic_update_stats(struct qlcnic_adapter *);
1763
1764 /* Adapter hardware abstraction */
1765 struct qlcnic_hardware_ops {
1766 void (*read_crb) (struct qlcnic_adapter *, char *, loff_t, size_t);
1767 void (*write_crb) (struct qlcnic_adapter *, char *, loff_t, size_t);
1768 int (*read_reg) (struct qlcnic_adapter *, ulong, int *);
1769 int (*write_reg) (struct qlcnic_adapter *, ulong, u32);
1770 void (*get_ocm_win) (struct qlcnic_hardware_context *);
1771 int (*get_mac_address) (struct qlcnic_adapter *, u8 *, u8);
1772 int (*setup_intr) (struct qlcnic_adapter *);
1773 int (*alloc_mbx_args)(struct qlcnic_cmd_args *,
1774 struct qlcnic_adapter *, u32);
1775 int (*mbx_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1776 void (*get_func_no) (struct qlcnic_adapter *);
1777 int (*api_lock) (struct qlcnic_adapter *);
1778 void (*api_unlock) (struct qlcnic_adapter *);
1779 void (*add_sysfs) (struct qlcnic_adapter *);
1780 void (*remove_sysfs) (struct qlcnic_adapter *);
1781 void (*process_lb_rcv_ring_diag) (struct qlcnic_host_sds_ring *);
1782 int (*create_rx_ctx) (struct qlcnic_adapter *);
1783 int (*create_tx_ctx) (struct qlcnic_adapter *,
1784 struct qlcnic_host_tx_ring *, int);
1785 void (*del_rx_ctx) (struct qlcnic_adapter *);
1786 void (*del_tx_ctx) (struct qlcnic_adapter *,
1787 struct qlcnic_host_tx_ring *);
1788 int (*setup_link_event) (struct qlcnic_adapter *, int);
1789 int (*get_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *, u8);
1790 int (*get_pci_info) (struct qlcnic_adapter *, struct qlcnic_pci_info *);
1791 int (*set_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *);
1792 int (*change_macvlan) (struct qlcnic_adapter *, u8*, u16, u8);
1793 void (*napi_enable) (struct qlcnic_adapter *);
1794 void (*napi_disable) (struct qlcnic_adapter *);
1795 int (*config_intr_coal) (struct qlcnic_adapter *,
1796 struct ethtool_coalesce *);
1797 int (*config_rss) (struct qlcnic_adapter *, int);
1798 int (*config_hw_lro) (struct qlcnic_adapter *, int);
1799 int (*config_loopback) (struct qlcnic_adapter *, u8);
1800 int (*clear_loopback) (struct qlcnic_adapter *, u8);
1801 int (*config_promisc_mode) (struct qlcnic_adapter *, u32);
1802 void (*change_l2_filter) (struct qlcnic_adapter *, u64 *, u16);
1803 int (*get_board_info) (struct qlcnic_adapter *);
1804 void (*set_mac_filter_count) (struct qlcnic_adapter *);
1805 void (*free_mac_list) (struct qlcnic_adapter *);
1806 int (*read_phys_port_id) (struct qlcnic_adapter *);
1807 pci_ers_result_t (*io_error_detected) (struct pci_dev *,
1808 pci_channel_state_t);
1809 pci_ers_result_t (*io_slot_reset) (struct pci_dev *);
1810 void (*io_resume) (struct pci_dev *);
1811 void (*get_beacon_state)(struct qlcnic_adapter *);
1812 void (*enable_sds_intr) (struct qlcnic_adapter *,
1813 struct qlcnic_host_sds_ring *);
1814 void (*disable_sds_intr) (struct qlcnic_adapter *,
1815 struct qlcnic_host_sds_ring *);
1816 void (*enable_tx_intr) (struct qlcnic_adapter *,
1817 struct qlcnic_host_tx_ring *);
1818 void (*disable_tx_intr) (struct qlcnic_adapter *,
1819 struct qlcnic_host_tx_ring *);
1820 u32 (*get_saved_state)(void *, u32);
1821 void (*set_saved_state)(void *, u32, u32);
1822 void (*cache_tmpl_hdr_values)(struct qlcnic_fw_dump *);
1823 u32 (*get_cap_size)(void *, int);
1824 void (*set_sys_info)(void *, int, u32);
1825 void (*store_cap_mask)(void *, u32);
1826 };
1827
1828 extern struct qlcnic_nic_template qlcnic_vf_ops;
1829
1830 static inline bool qlcnic_encap_tx_offload(struct qlcnic_adapter *adapter)
1831 {
1832 return adapter->ahw->extra_capability[0] &
1833 QLCNIC_83XX_FW_CAPAB_ENCAP_TX_OFFLOAD;
1834 }
1835
1836 static inline bool qlcnic_encap_rx_offload(struct qlcnic_adapter *adapter)
1837 {
1838 return adapter->ahw->extra_capability[0] &
1839 QLCNIC_83XX_FW_CAPAB_ENCAP_RX_OFFLOAD;
1840 }
1841
1842 static inline int qlcnic_start_firmware(struct qlcnic_adapter *adapter)
1843 {
1844 return adapter->nic_ops->start_firmware(adapter);
1845 }
1846
1847 static inline void qlcnic_read_crb(struct qlcnic_adapter *adapter, char *buf,
1848 loff_t offset, size_t size)
1849 {
1850 adapter->ahw->hw_ops->read_crb(adapter, buf, offset, size);
1851 }
1852
1853 static inline void qlcnic_write_crb(struct qlcnic_adapter *adapter, char *buf,
1854 loff_t offset, size_t size)
1855 {
1856 adapter->ahw->hw_ops->write_crb(adapter, buf, offset, size);
1857 }
1858
1859 static inline int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter,
1860 ulong off, u32 data)
1861 {
1862 return adapter->ahw->hw_ops->write_reg(adapter, off, data);
1863 }
1864
1865 static inline int qlcnic_get_mac_address(struct qlcnic_adapter *adapter,
1866 u8 *mac, u8 function)
1867 {
1868 return adapter->ahw->hw_ops->get_mac_address(adapter, mac, function);
1869 }
1870
1871 static inline int qlcnic_setup_intr(struct qlcnic_adapter *adapter)
1872 {
1873 return adapter->ahw->hw_ops->setup_intr(adapter);
1874 }
1875
1876 static inline int qlcnic_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
1877 struct qlcnic_adapter *adapter, u32 arg)
1878 {
1879 return adapter->ahw->hw_ops->alloc_mbx_args(mbx, adapter, arg);
1880 }
1881
1882 static inline int qlcnic_issue_cmd(struct qlcnic_adapter *adapter,
1883 struct qlcnic_cmd_args *cmd)
1884 {
1885 if (adapter->ahw->hw_ops->mbx_cmd)
1886 return adapter->ahw->hw_ops->mbx_cmd(adapter, cmd);
1887
1888 return -EIO;
1889 }
1890
1891 static inline void qlcnic_get_func_no(struct qlcnic_adapter *adapter)
1892 {
1893 adapter->ahw->hw_ops->get_func_no(adapter);
1894 }
1895
1896 static inline int qlcnic_api_lock(struct qlcnic_adapter *adapter)
1897 {
1898 return adapter->ahw->hw_ops->api_lock(adapter);
1899 }
1900
1901 static inline void qlcnic_api_unlock(struct qlcnic_adapter *adapter)
1902 {
1903 adapter->ahw->hw_ops->api_unlock(adapter);
1904 }
1905
1906 static inline void qlcnic_add_sysfs(struct qlcnic_adapter *adapter)
1907 {
1908 if (adapter->ahw->hw_ops->add_sysfs)
1909 adapter->ahw->hw_ops->add_sysfs(adapter);
1910 }
1911
1912 static inline void qlcnic_remove_sysfs(struct qlcnic_adapter *adapter)
1913 {
1914 if (adapter->ahw->hw_ops->remove_sysfs)
1915 adapter->ahw->hw_ops->remove_sysfs(adapter);
1916 }
1917
1918 static inline void
1919 qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring)
1920 {
1921 sds_ring->adapter->ahw->hw_ops->process_lb_rcv_ring_diag(sds_ring);
1922 }
1923
1924 static inline int qlcnic_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter)
1925 {
1926 return adapter->ahw->hw_ops->create_rx_ctx(adapter);
1927 }
1928
1929 static inline int qlcnic_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter,
1930 struct qlcnic_host_tx_ring *ptr,
1931 int ring)
1932 {
1933 return adapter->ahw->hw_ops->create_tx_ctx(adapter, ptr, ring);
1934 }
1935
1936 static inline void qlcnic_fw_cmd_del_rx_ctx(struct qlcnic_adapter *adapter)
1937 {
1938 return adapter->ahw->hw_ops->del_rx_ctx(adapter);
1939 }
1940
1941 static inline void qlcnic_fw_cmd_del_tx_ctx(struct qlcnic_adapter *adapter,
1942 struct qlcnic_host_tx_ring *ptr)
1943 {
1944 return adapter->ahw->hw_ops->del_tx_ctx(adapter, ptr);
1945 }
1946
1947 static inline int qlcnic_linkevent_request(struct qlcnic_adapter *adapter,
1948 int enable)
1949 {
1950 return adapter->ahw->hw_ops->setup_link_event(adapter, enable);
1951 }
1952
1953 static inline int qlcnic_get_nic_info(struct qlcnic_adapter *adapter,
1954 struct qlcnic_info *info, u8 id)
1955 {
1956 return adapter->ahw->hw_ops->get_nic_info(adapter, info, id);
1957 }
1958
1959 static inline int qlcnic_get_pci_info(struct qlcnic_adapter *adapter,
1960 struct qlcnic_pci_info *info)
1961 {
1962 return adapter->ahw->hw_ops->get_pci_info(adapter, info);
1963 }
1964
1965 static inline int qlcnic_set_nic_info(struct qlcnic_adapter *adapter,
1966 struct qlcnic_info *info)
1967 {
1968 return adapter->ahw->hw_ops->set_nic_info(adapter, info);
1969 }
1970
1971 static inline int qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter,
1972 u8 *addr, u16 id, u8 cmd)
1973 {
1974 return adapter->ahw->hw_ops->change_macvlan(adapter, addr, id, cmd);
1975 }
1976
1977 static inline int qlcnic_napi_add(struct qlcnic_adapter *adapter,
1978 struct net_device *netdev)
1979 {
1980 return adapter->nic_ops->napi_add(adapter, netdev);
1981 }
1982
1983 static inline void qlcnic_napi_del(struct qlcnic_adapter *adapter)
1984 {
1985 adapter->nic_ops->napi_del(adapter);
1986 }
1987
1988 static inline void qlcnic_napi_enable(struct qlcnic_adapter *adapter)
1989 {
1990 adapter->ahw->hw_ops->napi_enable(adapter);
1991 }
1992
1993 static inline int __qlcnic_shutdown(struct pci_dev *pdev)
1994 {
1995 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
1996
1997 return adapter->nic_ops->shutdown(pdev);
1998 }
1999
2000 static inline int __qlcnic_resume(struct qlcnic_adapter *adapter)
2001 {
2002 return adapter->nic_ops->resume(adapter);
2003 }
2004
2005 static inline void qlcnic_napi_disable(struct qlcnic_adapter *adapter)
2006 {
2007 adapter->ahw->hw_ops->napi_disable(adapter);
2008 }
2009
2010 static inline int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter,
2011 struct ethtool_coalesce *ethcoal)
2012 {
2013 return adapter->ahw->hw_ops->config_intr_coal(adapter, ethcoal);
2014 }
2015
2016 static inline int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable)
2017 {
2018 return adapter->ahw->hw_ops->config_rss(adapter, enable);
2019 }
2020
2021 static inline int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter,
2022 int enable)
2023 {
2024 return adapter->ahw->hw_ops->config_hw_lro(adapter, enable);
2025 }
2026
2027 static inline int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
2028 {
2029 return adapter->ahw->hw_ops->config_loopback(adapter, mode);
2030 }
2031
2032 static inline int qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
2033 {
2034 return adapter->ahw->hw_ops->clear_loopback(adapter, mode);
2035 }
2036
2037 static inline int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter,
2038 u32 mode)
2039 {
2040 return adapter->ahw->hw_ops->config_promisc_mode(adapter, mode);
2041 }
2042
2043 static inline void qlcnic_change_filter(struct qlcnic_adapter *adapter,
2044 u64 *addr, u16 id)
2045 {
2046 adapter->ahw->hw_ops->change_l2_filter(adapter, addr, id);
2047 }
2048
2049 static inline int qlcnic_get_board_info(struct qlcnic_adapter *adapter)
2050 {
2051 return adapter->ahw->hw_ops->get_board_info(adapter);
2052 }
2053
2054 static inline void qlcnic_free_mac_list(struct qlcnic_adapter *adapter)
2055 {
2056 return adapter->ahw->hw_ops->free_mac_list(adapter);
2057 }
2058
2059 static inline void qlcnic_set_mac_filter_count(struct qlcnic_adapter *adapter)
2060 {
2061 if (adapter->ahw->hw_ops->set_mac_filter_count)
2062 adapter->ahw->hw_ops->set_mac_filter_count(adapter);
2063 }
2064
2065 static inline void qlcnic_get_beacon_state(struct qlcnic_adapter *adapter)
2066 {
2067 adapter->ahw->hw_ops->get_beacon_state(adapter);
2068 }
2069
2070 static inline void qlcnic_read_phys_port_id(struct qlcnic_adapter *adapter)
2071 {
2072 if (adapter->ahw->hw_ops->read_phys_port_id)
2073 adapter->ahw->hw_ops->read_phys_port_id(adapter);
2074 }
2075
2076 static inline u32 qlcnic_get_saved_state(struct qlcnic_adapter *adapter,
2077 void *t_hdr, u32 index)
2078 {
2079 return adapter->ahw->hw_ops->get_saved_state(t_hdr, index);
2080 }
2081
2082 static inline void qlcnic_set_saved_state(struct qlcnic_adapter *adapter,
2083 void *t_hdr, u32 index, u32 value)
2084 {
2085 adapter->ahw->hw_ops->set_saved_state(t_hdr, index, value);
2086 }
2087
2088 static inline void qlcnic_cache_tmpl_hdr_values(struct qlcnic_adapter *adapter,
2089 struct qlcnic_fw_dump *fw_dump)
2090 {
2091 adapter->ahw->hw_ops->cache_tmpl_hdr_values(fw_dump);
2092 }
2093
2094 static inline u32 qlcnic_get_cap_size(struct qlcnic_adapter *adapter,
2095 void *tmpl_hdr, int index)
2096 {
2097 return adapter->ahw->hw_ops->get_cap_size(tmpl_hdr, index);
2098 }
2099
2100 static inline void qlcnic_set_sys_info(struct qlcnic_adapter *adapter,
2101 void *tmpl_hdr, int idx, u32 value)
2102 {
2103 adapter->ahw->hw_ops->set_sys_info(tmpl_hdr, idx, value);
2104 }
2105
2106 static inline void qlcnic_store_cap_mask(struct qlcnic_adapter *adapter,
2107 void *tmpl_hdr, u32 mask)
2108 {
2109 adapter->ahw->hw_ops->store_cap_mask(tmpl_hdr, mask);
2110 }
2111
2112 static inline void qlcnic_dev_request_reset(struct qlcnic_adapter *adapter,
2113 u32 key)
2114 {
2115 if (adapter->nic_ops->request_reset)
2116 adapter->nic_ops->request_reset(adapter, key);
2117 }
2118
2119 static inline void qlcnic_cancel_idc_work(struct qlcnic_adapter *adapter)
2120 {
2121 if (adapter->nic_ops->cancel_idc_work)
2122 adapter->nic_ops->cancel_idc_work(adapter);
2123 }
2124
2125 static inline irqreturn_t
2126 qlcnic_clear_legacy_intr(struct qlcnic_adapter *adapter)
2127 {
2128 return adapter->nic_ops->clear_legacy_intr(adapter);
2129 }
2130
2131 static inline int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state,
2132 u32 rate)
2133 {
2134 return adapter->nic_ops->config_led(adapter, state, rate);
2135 }
2136
2137 static inline void qlcnic_config_ipaddr(struct qlcnic_adapter *adapter,
2138 __be32 ip, int cmd)
2139 {
2140 adapter->nic_ops->config_ipaddr(adapter, ip, cmd);
2141 }
2142
2143 static inline bool qlcnic_check_multi_tx(struct qlcnic_adapter *adapter)
2144 {
2145 return test_bit(__QLCNIC_MULTI_TX_UNIQUE, &adapter->state);
2146 }
2147
2148 static inline void
2149 qlcnic_82xx_enable_tx_intr(struct qlcnic_adapter *adapter,
2150 struct qlcnic_host_tx_ring *tx_ring)
2151 {
2152 if (qlcnic_check_multi_tx(adapter) &&
2153 !adapter->ahw->diag_test)
2154 writel(0x0, tx_ring->crb_intr_mask);
2155 }
2156
2157 static inline void
2158 qlcnic_82xx_disable_tx_intr(struct qlcnic_adapter *adapter,
2159 struct qlcnic_host_tx_ring *tx_ring)
2160 {
2161 if (qlcnic_check_multi_tx(adapter) &&
2162 !adapter->ahw->diag_test)
2163 writel(1, tx_ring->crb_intr_mask);
2164 }
2165
2166 static inline void
2167 qlcnic_83xx_enable_tx_intr(struct qlcnic_adapter *adapter,
2168 struct qlcnic_host_tx_ring *tx_ring)
2169 {
2170 writel(0, tx_ring->crb_intr_mask);
2171 }
2172
2173 static inline void
2174 qlcnic_83xx_disable_tx_intr(struct qlcnic_adapter *adapter,
2175 struct qlcnic_host_tx_ring *tx_ring)
2176 {
2177 writel(1, tx_ring->crb_intr_mask);
2178 }
2179
2180 /* Enable MSI-x and INT-x interrupts */
2181 static inline void
2182 qlcnic_83xx_enable_sds_intr(struct qlcnic_adapter *adapter,
2183 struct qlcnic_host_sds_ring *sds_ring)
2184 {
2185 writel(0, sds_ring->crb_intr_mask);
2186 }
2187
2188 /* Disable MSI-x and INT-x interrupts */
2189 static inline void
2190 qlcnic_83xx_disable_sds_intr(struct qlcnic_adapter *adapter,
2191 struct qlcnic_host_sds_ring *sds_ring)
2192 {
2193 writel(1, sds_ring->crb_intr_mask);
2194 }
2195
2196 static inline void qlcnic_disable_multi_tx(struct qlcnic_adapter *adapter)
2197 {
2198 test_and_clear_bit(__QLCNIC_MULTI_TX_UNIQUE, &adapter->state);
2199 adapter->drv_tx_rings = QLCNIC_SINGLE_RING;
2200 }
2201
2202 /* When operating in a muti tx mode, driver needs to write 0x1
2203 * to src register, instead of 0x0 to disable receiving interrupt.
2204 */
2205 static inline void
2206 qlcnic_82xx_disable_sds_intr(struct qlcnic_adapter *adapter,
2207 struct qlcnic_host_sds_ring *sds_ring)
2208 {
2209 if (qlcnic_check_multi_tx(adapter) &&
2210 !adapter->ahw->diag_test &&
2211 (adapter->flags & QLCNIC_MSIX_ENABLED))
2212 writel(0x1, sds_ring->crb_intr_mask);
2213 else
2214 writel(0, sds_ring->crb_intr_mask);
2215 }
2216
2217 static inline void qlcnic_enable_sds_intr(struct qlcnic_adapter *adapter,
2218 struct qlcnic_host_sds_ring *sds_ring)
2219 {
2220 if (adapter->ahw->hw_ops->enable_sds_intr)
2221 adapter->ahw->hw_ops->enable_sds_intr(adapter, sds_ring);
2222 }
2223
2224 static inline void
2225 qlcnic_disable_sds_intr(struct qlcnic_adapter *adapter,
2226 struct qlcnic_host_sds_ring *sds_ring)
2227 {
2228 if (adapter->ahw->hw_ops->disable_sds_intr)
2229 adapter->ahw->hw_ops->disable_sds_intr(adapter, sds_ring);
2230 }
2231
2232 static inline void qlcnic_enable_tx_intr(struct qlcnic_adapter *adapter,
2233 struct qlcnic_host_tx_ring *tx_ring)
2234 {
2235 if (adapter->ahw->hw_ops->enable_tx_intr)
2236 adapter->ahw->hw_ops->enable_tx_intr(adapter, tx_ring);
2237 }
2238
2239 static inline void qlcnic_disable_tx_intr(struct qlcnic_adapter *adapter,
2240 struct qlcnic_host_tx_ring *tx_ring)
2241 {
2242 if (adapter->ahw->hw_ops->disable_tx_intr)
2243 adapter->ahw->hw_ops->disable_tx_intr(adapter, tx_ring);
2244 }
2245
2246 /* When operating in a muti tx mode, driver needs to write 0x0
2247 * to src register, instead of 0x1 to enable receiving interrupts.
2248 */
2249 static inline void
2250 qlcnic_82xx_enable_sds_intr(struct qlcnic_adapter *adapter,
2251 struct qlcnic_host_sds_ring *sds_ring)
2252 {
2253 if (qlcnic_check_multi_tx(adapter) &&
2254 !adapter->ahw->diag_test &&
2255 (adapter->flags & QLCNIC_MSIX_ENABLED))
2256 writel(0, sds_ring->crb_intr_mask);
2257 else
2258 writel(0x1, sds_ring->crb_intr_mask);
2259
2260 if (!QLCNIC_IS_MSI_FAMILY(adapter))
2261 writel(0xfbff, adapter->tgt_mask_reg);
2262 }
2263
2264 static inline int qlcnic_get_diag_lock(struct qlcnic_adapter *adapter)
2265 {
2266 return test_and_set_bit(__QLCNIC_DIAG_MODE, &adapter->state);
2267 }
2268
2269 static inline void qlcnic_release_diag_lock(struct qlcnic_adapter *adapter)
2270 {
2271 clear_bit(__QLCNIC_DIAG_MODE, &adapter->state);
2272 }
2273
2274 static inline int qlcnic_check_diag_status(struct qlcnic_adapter *adapter)
2275 {
2276 return test_bit(__QLCNIC_DIAG_MODE, &adapter->state);
2277 }
2278
2279 extern const struct ethtool_ops qlcnic_sriov_vf_ethtool_ops;
2280 extern const struct ethtool_ops qlcnic_ethtool_ops;
2281 extern const struct ethtool_ops qlcnic_ethtool_failed_ops;
2282
2283 #define QLCDB(adapter, lvl, _fmt, _args...) do { \
2284 if (NETIF_MSG_##lvl & adapter->ahw->msg_enable) \
2285 printk(KERN_INFO "%s: %s: " _fmt, \
2286 dev_name(&adapter->pdev->dev), \
2287 __func__, ##_args); \
2288 } while (0)
2289
2290 #define PCI_DEVICE_ID_QLOGIC_QLE824X 0x8020
2291 #define PCI_DEVICE_ID_QLOGIC_QLE834X 0x8030
2292 #define PCI_DEVICE_ID_QLOGIC_VF_QLE834X 0x8430
2293 #define PCI_DEVICE_ID_QLOGIC_QLE844X 0x8040
2294 #define PCI_DEVICE_ID_QLOGIC_VF_QLE844X 0x8440
2295
2296 static inline bool qlcnic_82xx_check(struct qlcnic_adapter *adapter)
2297 {
2298 unsigned short device = adapter->pdev->device;
2299 return (device == PCI_DEVICE_ID_QLOGIC_QLE824X) ? true : false;
2300 }
2301
2302 static inline bool qlcnic_84xx_check(struct qlcnic_adapter *adapter)
2303 {
2304 unsigned short device = adapter->pdev->device;
2305
2306 return ((device == PCI_DEVICE_ID_QLOGIC_QLE844X) ||
2307 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X)) ? true : false;
2308 }
2309
2310 static inline bool qlcnic_83xx_check(struct qlcnic_adapter *adapter)
2311 {
2312 unsigned short device = adapter->pdev->device;
2313 bool status;
2314
2315 status = ((device == PCI_DEVICE_ID_QLOGIC_QLE834X) ||
2316 (device == PCI_DEVICE_ID_QLOGIC_QLE844X) ||
2317 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X) ||
2318 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X)) ? true : false;
2319
2320 return status;
2321 }
2322
2323 static inline bool qlcnic_sriov_pf_check(struct qlcnic_adapter *adapter)
2324 {
2325 return (adapter->ahw->op_mode == QLCNIC_SRIOV_PF_FUNC) ? true : false;
2326 }
2327
2328 static inline bool qlcnic_sriov_vf_check(struct qlcnic_adapter *adapter)
2329 {
2330 unsigned short device = adapter->pdev->device;
2331 bool status;
2332
2333 status = ((device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X) ||
2334 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X)) ? true : false;
2335
2336 return status;
2337 }
2338
2339 static inline bool qlcnic_83xx_pf_check(struct qlcnic_adapter *adapter)
2340 {
2341 unsigned short device = adapter->pdev->device;
2342
2343 return (device == PCI_DEVICE_ID_QLOGIC_QLE834X) ? true : false;
2344 }
2345
2346 static inline bool qlcnic_83xx_vf_check(struct qlcnic_adapter *adapter)
2347 {
2348 unsigned short device = adapter->pdev->device;
2349
2350 return (device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X) ? true : false;
2351 }
2352
2353 static inline u32 qlcnic_get_vnic_func_count(struct qlcnic_adapter *adapter)
2354 {
2355 if (qlcnic_84xx_check(adapter))
2356 return QLC_84XX_VNIC_COUNT;
2357 else
2358 return QLC_DEFAULT_VNIC_COUNT;
2359 }
2360 #endif /* __QLCNIC_H_ */
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