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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic.h
1 /*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
8 #ifndef _QLCNIC_H_
9 #define _QLCNIC_H_
10
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/netdevice.h>
17 #include <linux/etherdevice.h>
18 #include <linux/ip.h>
19 #include <linux/in.h>
20 #include <linux/tcp.h>
21 #include <linux/skbuff.h>
22 #include <linux/firmware.h>
23 #include <linux/ethtool.h>
24 #include <linux/mii.h>
25 #include <linux/timer.h>
26
27 #include <linux/vmalloc.h>
28
29 #include <linux/io.h>
30 #include <asm/byteorder.h>
31 #include <linux/bitops.h>
32 #include <linux/if_vlan.h>
33
34 #include "qlcnic_hdr.h"
35 #include "qlcnic_hw.h"
36 #include "qlcnic_83xx_hw.h"
37 #include "qlcnic_dcb.h"
38
39 #define _QLCNIC_LINUX_MAJOR 5
40 #define _QLCNIC_LINUX_MINOR 3
41 #define _QLCNIC_LINUX_SUBVERSION 55
42 #define QLCNIC_LINUX_VERSIONID "5.3.55"
43 #define QLCNIC_DRV_IDC_VER 0x01
44 #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\
45 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION))
46
47 #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
48 #define _major(v) (((v) >> 24) & 0xff)
49 #define _minor(v) (((v) >> 16) & 0xff)
50 #define _build(v) ((v) & 0xffff)
51
52 /* version in image has weird encoding:
53 * 7:0 - major
54 * 15:8 - minor
55 * 31:16 - build (little endian)
56 */
57 #define QLCNIC_DECODE_VERSION(v) \
58 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
59
60 #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2)
61 #define QLCNIC_NUM_FLASH_SECTORS (64)
62 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024)
63 #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \
64 * QLCNIC_FLASH_SECTOR_SIZE)
65
66 #define RCV_DESC_RINGSIZE(rds_ring) \
67 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
68 #define RCV_BUFF_RINGSIZE(rds_ring) \
69 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc)
70 #define STATUS_DESC_RINGSIZE(sds_ring) \
71 (sizeof(struct status_desc) * (sds_ring)->num_desc)
72 #define TX_BUFF_RINGSIZE(tx_ring) \
73 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc)
74 #define TX_DESC_RINGSIZE(tx_ring) \
75 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
76
77 #define QLCNIC_P3P_A0 0x50
78 #define QLCNIC_P3P_C0 0x58
79
80 #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0)
81
82 #define FIRST_PAGE_GROUP_START 0
83 #define FIRST_PAGE_GROUP_END 0x100000
84
85 #define P3P_MAX_MTU (9600)
86 #define P3P_MIN_MTU (68)
87 #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */
88
89 #define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN)
90 #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU)
91 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048
92 #define QLCNIC_LRO_BUFFER_EXTRA 2048
93
94 /* Tx defines */
95 #define QLCNIC_MAX_FRAGS_PER_TX 14
96 #define MAX_TSO_HEADER_DESC 2
97 #define MGMT_CMD_DESC_RESV 4
98 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \
99 + MGMT_CMD_DESC_RESV)
100 #define QLCNIC_MAX_TX_TIMEOUTS 2
101
102 /* Driver will use 1 Tx ring in INT-x/MSI/SRIOV mode. */
103 #define QLCNIC_SINGLE_RING 1
104 #define QLCNIC_DEF_SDS_RINGS 4
105 #define QLCNIC_DEF_TX_RINGS 4
106 #define QLCNIC_MAX_VNIC_TX_RINGS 4
107 #define QLCNIC_MAX_VNIC_SDS_RINGS 4
108 #define QLCNIC_83XX_MINIMUM_VECTOR 3
109 #define QLCNIC_82XX_MINIMUM_VECTOR 2
110
111 enum qlcnic_queue_type {
112 QLCNIC_TX_QUEUE = 1,
113 QLCNIC_RX_QUEUE,
114 };
115
116 /* Operational mode for driver */
117 #define QLCNIC_VNIC_MODE 0xFF
118 #define QLCNIC_DEFAULT_MODE 0x0
119
120 /* Virtual NIC function count */
121 #define QLC_DEFAULT_VNIC_COUNT 8
122 #define QLC_84XX_VNIC_COUNT 16
123
124 /*
125 * Following are the states of the Phantom. Phantom will set them and
126 * Host will read to check if the fields are correct.
127 */
128 #define PHAN_INITIALIZE_FAILED 0xffff
129 #define PHAN_INITIALIZE_COMPLETE 0xff01
130
131 /* Host writes the following to notify that it has done the init-handshake */
132 #define PHAN_INITIALIZE_ACK 0xf00f
133 #define PHAN_PEG_RCV_INITIALIZED 0xff01
134
135 #define NUM_RCV_DESC_RINGS 3
136
137 #define RCV_RING_NORMAL 0
138 #define RCV_RING_JUMBO 1
139
140 #define MIN_CMD_DESCRIPTORS 64
141 #define MIN_RCV_DESCRIPTORS 64
142 #define MIN_JUMBO_DESCRIPTORS 32
143
144 #define MAX_CMD_DESCRIPTORS 1024
145 #define MAX_RCV_DESCRIPTORS_1G 4096
146 #define MAX_RCV_DESCRIPTORS_10G 8192
147 #define MAX_RCV_DESCRIPTORS_VF 2048
148 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
149 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
150
151 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
152 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
153 #define DEFAULT_RCV_DESCRIPTORS_VF 1024
154 #define MAX_RDS_RINGS 2
155
156 #define get_next_index(index, length) \
157 (((index) + 1) & ((length) - 1))
158
159 /*
160 * Following data structures describe the descriptors that will be used.
161 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
162 * we are doing LSO (above the 1500 size packet) only.
163 */
164 struct cmd_desc_type0 {
165 u8 tcp_hdr_offset; /* For LSO only */
166 u8 ip_hdr_offset; /* For LSO only */
167 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
168 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
169
170 __le64 addr_buffer2;
171
172 __le16 reference_handle;
173 __le16 mss;
174 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
175 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
176 __le16 conn_id; /* IPSec offoad only */
177
178 __le64 addr_buffer3;
179 __le64 addr_buffer1;
180
181 __le16 buffer_length[4];
182
183 __le64 addr_buffer4;
184
185 u8 eth_addr[ETH_ALEN];
186 __le16 vlan_TCI;
187
188 } __attribute__ ((aligned(64)));
189
190 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
191 struct rcv_desc {
192 __le16 reference_handle;
193 __le16 reserved;
194 __le32 buffer_length; /* allocated buffer length (usually 2K) */
195 __le64 addr_buffer;
196 } __packed;
197
198 struct status_desc {
199 __le64 status_desc_data[2];
200 } __attribute__ ((aligned(16)));
201
202 /* UNIFIED ROMIMAGE */
203 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000
204 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0
205 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6
206 #define QLCNIC_UNI_DIR_SECT_FW 0x7
207
208 /*Offsets */
209 #define QLCNIC_UNI_CHIP_REV_OFF 10
210 #define QLCNIC_UNI_FLAGS_OFF 11
211 #define QLCNIC_UNI_BIOS_VERSION_OFF 12
212 #define QLCNIC_UNI_BOOTLD_IDX_OFF 27
213 #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29
214
215 struct uni_table_desc{
216 __le32 findex;
217 __le32 num_entries;
218 __le32 entry_size;
219 __le32 reserved[5];
220 };
221
222 struct uni_data_desc{
223 __le32 findex;
224 __le32 size;
225 __le32 reserved[5];
226 };
227
228 /* Flash Defines and Structures */
229 #define QLCNIC_FLT_LOCATION 0x3F1000
230 #define QLCNIC_FDT_LOCATION 0x3F0000
231 #define QLCNIC_B0_FW_IMAGE_REGION 0x74
232 #define QLCNIC_C0_FW_IMAGE_REGION 0x97
233 #define QLCNIC_BOOTLD_REGION 0X72
234 struct qlcnic_flt_header {
235 u16 version;
236 u16 len;
237 u16 checksum;
238 u16 reserved;
239 };
240
241 struct qlcnic_flt_entry {
242 u8 region;
243 u8 reserved0;
244 u8 attrib;
245 u8 reserved1;
246 u32 size;
247 u32 start_addr;
248 u32 end_addr;
249 };
250
251 /* Flash Descriptor Table */
252 struct qlcnic_fdt {
253 u32 valid;
254 u16 ver;
255 u16 len;
256 u16 cksum;
257 u16 unused;
258 u8 model[16];
259 u16 mfg_id;
260 u16 id;
261 u8 flag;
262 u8 erase_cmd;
263 u8 alt_erase_cmd;
264 u8 write_enable_cmd;
265 u8 write_enable_bits;
266 u8 write_statusreg_cmd;
267 u8 unprotected_sec_cmd;
268 u8 read_manuf_cmd;
269 u32 block_size;
270 u32 alt_block_size;
271 u32 flash_size;
272 u32 write_enable_data;
273 u8 readid_addr_len;
274 u8 write_disable_bits;
275 u8 read_dev_id_len;
276 u8 chip_erase_cmd;
277 u16 read_timeo;
278 u8 protected_sec_cmd;
279 u8 resvd[65];
280 };
281 /* Magic number to let user know flash is programmed */
282 #define QLCNIC_BDINFO_MAGIC 0x12345678
283
284 #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021
285 #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022
286 #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023
287 #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024
288 #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025
289 #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026
290 #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027
291 #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028
292 #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029
293 #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a
294 #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b
295 #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031
296 #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032
297 #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080
298
299 #define QLCNIC_MSIX_TABLE_OFFSET 0x44
300
301 /* Flash memory map */
302 #define QLCNIC_BRDCFG_START 0x4000 /* board config */
303 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */
304 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */
305 #define QLCNIC_USER_START 0x3E8000 /* Firmare info */
306
307 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408)
308 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c)
309 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c)
310 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c)
311
312 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8)
313 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128)
314
315 #define QLCNIC_FW_MIN_SIZE (0x3fffff)
316 #define QLCNIC_UNIFIED_ROMIMAGE 0
317 #define QLCNIC_FLASH_ROMIMAGE 1
318 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff
319
320 #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
321 #define QLCNIC_FLASH_ROMIMAGE_NAME "flash"
322
323 extern char qlcnic_driver_name[];
324
325 extern int qlcnic_use_msi;
326 extern int qlcnic_use_msi_x;
327 extern int qlcnic_auto_fw_reset;
328 extern int qlcnic_load_fw_file;
329
330 /* Number of status descriptors to handle per interrupt */
331 #define MAX_STATUS_HANDLE (64)
332
333 /*
334 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This
335 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}.
336 */
337 struct qlcnic_skb_frag {
338 u64 dma;
339 u64 length;
340 };
341
342 /* Following defines are for the state of the buffers */
343 #define QLCNIC_BUFFER_FREE 0
344 #define QLCNIC_BUFFER_BUSY 1
345
346 /*
347 * There will be one qlcnic_buffer per skb packet. These will be
348 * used to save the dma info for pci_unmap_page()
349 */
350 struct qlcnic_cmd_buffer {
351 struct sk_buff *skb;
352 struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1];
353 u32 frag_count;
354 };
355
356 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
357 struct qlcnic_rx_buffer {
358 u16 ref_handle;
359 struct sk_buff *skb;
360 struct list_head list;
361 u64 dma;
362 };
363
364 /* Board types */
365 #define QLCNIC_GBE 0x01
366 #define QLCNIC_XGBE 0x02
367
368 /*
369 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
370 * adjusted based on configured MTU.
371 */
372 #define QLCNIC_INTR_COAL_TYPE_RX 1
373 #define QLCNIC_INTR_COAL_TYPE_TX 2
374 #define QLCNIC_INTR_COAL_TYPE_RX_TX 3
375
376 #define QLCNIC_DEF_INTR_COALESCE_RX_TIME_US 3
377 #define QLCNIC_DEF_INTR_COALESCE_RX_PACKETS 256
378
379 #define QLCNIC_DEF_INTR_COALESCE_TX_TIME_US 64
380 #define QLCNIC_DEF_INTR_COALESCE_TX_PACKETS 64
381
382 #define QLCNIC_INTR_DEFAULT 0x04
383 #define QLCNIC_CONFIG_INTR_COALESCE 3
384 #define QLCNIC_DEV_INFO_SIZE 2
385
386 struct qlcnic_nic_intr_coalesce {
387 u8 type;
388 u8 sts_ring_mask;
389 u16 rx_packets;
390 u16 rx_time_us;
391 u16 tx_packets;
392 u16 tx_time_us;
393 u16 flag;
394 u32 timer_out;
395 };
396
397 struct qlcnic_dump_template_hdr {
398 u32 type;
399 u32 offset;
400 u32 size;
401 u32 cap_mask;
402 u32 num_entries;
403 u32 version;
404 u32 timestamp;
405 u32 checksum;
406 u32 drv_cap_mask;
407 u32 sys_info[3];
408 u32 saved_state[16];
409 u32 cap_sizes[8];
410 u32 ocm_wnd_reg[16];
411 u32 rsvd[0];
412 };
413
414 struct qlcnic_fw_dump {
415 u8 clr; /* flag to indicate if dump is cleared */
416 bool enable; /* enable/disable dump */
417 u32 size; /* total size of the dump */
418 void *data; /* dump data area */
419 struct qlcnic_dump_template_hdr *tmpl_hdr;
420 dma_addr_t phys_addr;
421 void *dma_buffer;
422 bool use_pex_dma;
423 };
424
425 /*
426 * One hardware_context{} per adapter
427 * contains interrupt info as well shared hardware info.
428 */
429 struct qlcnic_hardware_context {
430 void __iomem *pci_base0;
431 void __iomem *ocm_win_crb;
432
433 unsigned long pci_len0;
434
435 rwlock_t crb_lock;
436 struct mutex mem_lock;
437
438 u8 revision_id;
439 u8 pci_func;
440 u8 linkup;
441 u8 loopback_state;
442 u8 beacon_state;
443 u8 has_link_events;
444 u8 fw_type;
445 u8 physical_port;
446 u8 reset_context;
447 u8 msix_supported;
448 u8 max_mac_filters;
449 u8 mc_enabled;
450 u8 max_mc_count;
451 u8 diag_test;
452 u8 num_msix;
453 u8 nic_mode;
454 int diag_cnt;
455
456 u16 max_uc_count;
457 u16 port_type;
458 u16 board_type;
459 u16 supported_type;
460
461 u16 link_speed;
462 u16 link_duplex;
463 u16 link_autoneg;
464 u16 module_type;
465
466 u16 op_mode;
467 u16 switch_mode;
468 u16 max_tx_ques;
469 u16 max_rx_ques;
470 u16 max_mtu;
471 u32 msg_enable;
472 u16 total_nic_func;
473 u16 max_pci_func;
474 u32 max_vnic_func;
475 u32 total_pci_func;
476
477 u32 capabilities;
478 u32 extra_capability[3];
479 u32 temp;
480 u32 int_vec_bit;
481 u32 fw_hal_version;
482 u32 port_config;
483 struct qlcnic_hardware_ops *hw_ops;
484 struct qlcnic_nic_intr_coalesce coal;
485 struct qlcnic_fw_dump fw_dump;
486 struct qlcnic_fdt fdt;
487 struct qlc_83xx_reset reset;
488 struct qlc_83xx_idc idc;
489 struct qlc_83xx_fw_info *fw_info;
490 struct qlcnic_intrpt_config *intr_tbl;
491 struct qlcnic_sriov *sriov;
492 u32 *reg_tbl;
493 u32 *ext_reg_tbl;
494 u32 mbox_aen[QLC_83XX_MBX_AEN_CNT];
495 u32 mbox_reg[4];
496 struct qlcnic_mailbox *mailbox;
497 u8 extend_lb_time;
498 u8 phys_port_id[ETH_ALEN];
499 u8 lb_mode;
500 };
501
502 struct qlcnic_adapter_stats {
503 u64 xmitcalled;
504 u64 xmitfinished;
505 u64 rxdropped;
506 u64 txdropped;
507 u64 csummed;
508 u64 rx_pkts;
509 u64 lro_pkts;
510 u64 rxbytes;
511 u64 txbytes;
512 u64 lrobytes;
513 u64 lso_frames;
514 u64 xmit_on;
515 u64 xmit_off;
516 u64 skb_alloc_failure;
517 u64 null_rxbuf;
518 u64 rx_dma_map_error;
519 u64 tx_dma_map_error;
520 u64 spurious_intr;
521 u64 mac_filter_limit_overrun;
522 };
523
524 /*
525 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
526 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
527 */
528 struct qlcnic_host_rds_ring {
529 void __iomem *crb_rcv_producer;
530 struct rcv_desc *desc_head;
531 struct qlcnic_rx_buffer *rx_buf_arr;
532 u32 num_desc;
533 u32 producer;
534 u32 dma_size;
535 u32 skb_size;
536 u32 flags;
537 struct list_head free_list;
538 spinlock_t lock;
539 dma_addr_t phys_addr;
540 } ____cacheline_internodealigned_in_smp;
541
542 struct qlcnic_host_sds_ring {
543 u32 consumer;
544 u32 num_desc;
545 void __iomem *crb_sts_consumer;
546
547 struct qlcnic_host_tx_ring *tx_ring;
548 struct status_desc *desc_head;
549 struct qlcnic_adapter *adapter;
550 struct napi_struct napi;
551 struct list_head free_list[NUM_RCV_DESC_RINGS];
552
553 void __iomem *crb_intr_mask;
554 int irq;
555
556 dma_addr_t phys_addr;
557 char name[IFNAMSIZ + 12];
558 } ____cacheline_internodealigned_in_smp;
559
560 struct qlcnic_tx_queue_stats {
561 u64 xmit_on;
562 u64 xmit_off;
563 u64 xmit_called;
564 u64 xmit_finished;
565 u64 tx_bytes;
566 };
567
568 struct qlcnic_host_tx_ring {
569 int irq;
570 void __iomem *crb_intr_mask;
571 char name[IFNAMSIZ + 12];
572 u16 ctx_id;
573
574 u32 state;
575 u32 producer;
576 u32 sw_consumer;
577 u32 num_desc;
578
579 struct qlcnic_tx_queue_stats tx_stats;
580
581 void __iomem *crb_cmd_producer;
582 struct cmd_desc_type0 *desc_head;
583 struct qlcnic_adapter *adapter;
584 struct napi_struct napi;
585 struct qlcnic_cmd_buffer *cmd_buf_arr;
586 __le32 *hw_consumer;
587
588 dma_addr_t phys_addr;
589 dma_addr_t hw_cons_phys_addr;
590 struct netdev_queue *txq;
591 /* Lock to protect Tx descriptors cleanup */
592 spinlock_t tx_clean_lock;
593 } ____cacheline_internodealigned_in_smp;
594
595 /*
596 * Receive context. There is one such structure per instance of the
597 * receive processing. Any state information that is relevant to
598 * the receive, and is must be in this structure. The global data may be
599 * present elsewhere.
600 */
601 struct qlcnic_recv_context {
602 struct qlcnic_host_rds_ring *rds_rings;
603 struct qlcnic_host_sds_ring *sds_rings;
604 u32 state;
605 u16 context_id;
606 u16 virt_port;
607 };
608
609 /* HW context creation */
610
611 #define QLCNIC_OS_CRB_RETRY_COUNT 4000
612
613 #define QLCNIC_CDRP_CMD_BIT 0x80000000
614
615 /*
616 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared
617 * in the crb QLCNIC_CDRP_CRB_OFFSET.
618 */
619 #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp)
620 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0)
621
622 #define QLCNIC_CDRP_RSP_OK 0x00000001
623 #define QLCNIC_CDRP_RSP_FAIL 0x00000002
624 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003
625
626 /*
627 * All commands must have the QLCNIC_CDRP_CMD_BIT set in
628 * the crb QLCNIC_CDRP_CRB_OFFSET.
629 */
630 #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd))
631
632 #define QLCNIC_RCODE_SUCCESS 0
633 #define QLCNIC_RCODE_INVALID_ARGS 6
634 #define QLCNIC_RCODE_NOT_SUPPORTED 9
635 #define QLCNIC_RCODE_NOT_PERMITTED 10
636 #define QLCNIC_RCODE_NOT_IMPL 15
637 #define QLCNIC_RCODE_INVALID 16
638 #define QLCNIC_RCODE_TIMEOUT 17
639 #define QLCNIC_DESTROY_CTX_RESET 0
640
641 /*
642 * Capabilities Announced
643 */
644 #define QLCNIC_CAP0_LEGACY_CONTEXT (1)
645 #define QLCNIC_CAP0_LEGACY_MN (1 << 2)
646 #define QLCNIC_CAP0_LSO (1 << 6)
647 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7)
648 #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8)
649 #define QLCNIC_CAP0_VALIDOFF (1 << 11)
650 #define QLCNIC_CAP0_LRO_MSS (1 << 21)
651 #define QLCNIC_CAP0_TX_MULTI (1 << 22)
652
653 /*
654 * Context state
655 */
656 #define QLCNIC_HOST_CTX_STATE_FREED 0
657 #define QLCNIC_HOST_CTX_STATE_ACTIVE 2
658
659 /*
660 * Rx context
661 */
662
663 struct qlcnic_hostrq_sds_ring {
664 __le64 host_phys_addr; /* Ring base addr */
665 __le32 ring_size; /* Ring entries */
666 __le16 msi_index;
667 __le16 rsvd; /* Padding */
668 } __packed;
669
670 struct qlcnic_hostrq_rds_ring {
671 __le64 host_phys_addr; /* Ring base addr */
672 __le64 buff_size; /* Packet buffer size */
673 __le32 ring_size; /* Ring entries */
674 __le32 ring_kind; /* Class of ring */
675 } __packed;
676
677 struct qlcnic_hostrq_rx_ctx {
678 __le64 host_rsp_dma_addr; /* Response dma'd here */
679 __le32 capabilities[4]; /* Flag bit vector */
680 __le32 host_int_crb_mode; /* Interrupt crb usage */
681 __le32 host_rds_crb_mode; /* RDS crb usage */
682 /* These ring offsets are relative to data[0] below */
683 __le32 rds_ring_offset; /* Offset to RDS config */
684 __le32 sds_ring_offset; /* Offset to SDS config */
685 __le16 num_rds_rings; /* Count of RDS rings */
686 __le16 num_sds_rings; /* Count of SDS rings */
687 __le16 valid_field_offset;
688 u8 txrx_sds_binding;
689 u8 msix_handler;
690 u8 reserved[128]; /* reserve space for future expansion*/
691 /* MUST BE 64-bit aligned.
692 The following is packed:
693 - N hostrq_rds_rings
694 - N hostrq_sds_rings */
695 char data[0];
696 } __packed;
697
698 struct qlcnic_cardrsp_rds_ring{
699 __le32 host_producer_crb; /* Crb to use */
700 __le32 rsvd1; /* Padding */
701 } __packed;
702
703 struct qlcnic_cardrsp_sds_ring {
704 __le32 host_consumer_crb; /* Crb to use */
705 __le32 interrupt_crb; /* Crb to use */
706 } __packed;
707
708 struct qlcnic_cardrsp_rx_ctx {
709 /* These ring offsets are relative to data[0] below */
710 __le32 rds_ring_offset; /* Offset to RDS config */
711 __le32 sds_ring_offset; /* Offset to SDS config */
712 __le32 host_ctx_state; /* Starting State */
713 __le32 num_fn_per_port; /* How many PCI fn share the port */
714 __le16 num_rds_rings; /* Count of RDS rings */
715 __le16 num_sds_rings; /* Count of SDS rings */
716 __le16 context_id; /* Handle for context */
717 u8 phys_port; /* Physical id of port */
718 u8 virt_port; /* Virtual/Logical id of port */
719 u8 reserved[128]; /* save space for future expansion */
720 /* MUST BE 64-bit aligned.
721 The following is packed:
722 - N cardrsp_rds_rings
723 - N cardrs_sds_rings */
724 char data[0];
725 } __packed;
726
727 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
728 (sizeof(HOSTRQ_RX) + \
729 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \
730 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring)))
731
732 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
733 (sizeof(CARDRSP_RX) + \
734 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \
735 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring)))
736
737 /*
738 * Tx context
739 */
740
741 struct qlcnic_hostrq_cds_ring {
742 __le64 host_phys_addr; /* Ring base addr */
743 __le32 ring_size; /* Ring entries */
744 __le32 rsvd; /* Padding */
745 } __packed;
746
747 struct qlcnic_hostrq_tx_ctx {
748 __le64 host_rsp_dma_addr; /* Response dma'd here */
749 __le64 cmd_cons_dma_addr; /* */
750 __le64 dummy_dma_addr; /* */
751 __le32 capabilities[4]; /* Flag bit vector */
752 __le32 host_int_crb_mode; /* Interrupt crb usage */
753 __le32 rsvd1; /* Padding */
754 __le16 rsvd2; /* Padding */
755 __le16 interrupt_ctl;
756 __le16 msi_index;
757 __le16 rsvd3; /* Padding */
758 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */
759 u8 reserved[128]; /* future expansion */
760 } __packed;
761
762 struct qlcnic_cardrsp_cds_ring {
763 __le32 host_producer_crb; /* Crb to use */
764 __le32 interrupt_crb; /* Crb to use */
765 } __packed;
766
767 struct qlcnic_cardrsp_tx_ctx {
768 __le32 host_ctx_state; /* Starting state */
769 __le16 context_id; /* Handle for context */
770 u8 phys_port; /* Physical id of port */
771 u8 virt_port; /* Virtual/Logical id of port */
772 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */
773 u8 reserved[128]; /* future expansion */
774 } __packed;
775
776 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
777 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
778
779 /* CRB */
780
781 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0
782 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1
783 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2
784 #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3
785
786 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0
787 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1
788 #define QLCNIC_HOST_INT_CRB_MODE_NORX 2
789 #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3
790 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4
791
792
793 /* MAC */
794
795 #define MC_COUNT_P3P 38
796
797 #define QLCNIC_MAC_NOOP 0
798 #define QLCNIC_MAC_ADD 1
799 #define QLCNIC_MAC_DEL 2
800 #define QLCNIC_MAC_VLAN_ADD 3
801 #define QLCNIC_MAC_VLAN_DEL 4
802
803 struct qlcnic_mac_vlan_list {
804 struct list_head list;
805 uint8_t mac_addr[ETH_ALEN+2];
806 u16 vlan_id;
807 };
808
809 /* MAC Learn */
810 #define NO_MAC_LEARN 0
811 #define DRV_MAC_LEARN 1
812 #define FDB_MAC_LEARN 2
813
814 #define QLCNIC_HOST_REQUEST 0x13
815 #define QLCNIC_REQUEST 0x14
816
817 #define QLCNIC_MAC_EVENT 0x1
818
819 #define QLCNIC_IP_UP 2
820 #define QLCNIC_IP_DOWN 3
821
822 #define QLCNIC_ILB_MODE 0x1
823 #define QLCNIC_ELB_MODE 0x2
824 #define QLCNIC_LB_MODE_MASK 0x3
825
826 #define QLCNIC_LINKEVENT 0x1
827 #define QLCNIC_LB_RESPONSE 0x2
828 #define QLCNIC_IS_LB_CONFIGURED(VAL) \
829 (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE))
830
831 /*
832 * Driver --> Firmware
833 */
834 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1
835 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3
836 #define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4
837 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7
838 #define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc
839 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12
840
841 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15
842 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17
843 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18
844 #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 0x13
845
846 /*
847 * Firmware --> Driver
848 */
849
850 #define QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK 0x8f
851 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 0x8D
852 #define QLCNIC_C2H_OPCODE_GET_DCB_AEN 0x90
853
854 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
855 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
856 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
857
858 #define QLCNIC_LRO_REQUEST_CLEANUP 4
859
860 /* Capabilites received */
861 #define QLCNIC_FW_CAPABILITY_TSO BIT_1
862 #define QLCNIC_FW_CAPABILITY_BDG BIT_8
863 #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9
864 #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10
865 #define QLCNIC_FW_CAPABILITY_2_MULTI_TX BIT_4
866 #define QLCNIC_FW_CAPABILITY_MULTI_LOOPBACK BIT_27
867 #define QLCNIC_FW_CAPABILITY_MORE_CAPS BIT_31
868
869 #define QLCNIC_FW_CAPABILITY_2_LRO_MAX_TCP_SEG BIT_2
870 #define QLCNIC_FW_CAP2_HW_LRO_IPV6 BIT_3
871 #define QLCNIC_FW_CAPABILITY_SET_DRV_VER BIT_5
872 #define QLCNIC_FW_CAPABILITY_2_BEACON BIT_7
873 #define QLCNIC_FW_CAPABILITY_2_PER_PORT_ESWITCH_CFG BIT_9
874
875 /* module types */
876 #define LINKEVENT_MODULE_NOT_PRESENT 1
877 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
878 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
879 #define LINKEVENT_MODULE_OPTICAL_LRM 4
880 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
881 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
882 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
883 #define LINKEVENT_MODULE_TWINAX 8
884
885 #define LINKSPEED_10GBPS 10000
886 #define LINKSPEED_1GBPS 1000
887 #define LINKSPEED_100MBPS 100
888 #define LINKSPEED_10MBPS 10
889
890 #define LINKSPEED_ENCODED_10MBPS 0
891 #define LINKSPEED_ENCODED_100MBPS 1
892 #define LINKSPEED_ENCODED_1GBPS 2
893
894 #define LINKEVENT_AUTONEG_DISABLED 0
895 #define LINKEVENT_AUTONEG_ENABLED 1
896
897 #define LINKEVENT_HALF_DUPLEX 0
898 #define LINKEVENT_FULL_DUPLEX 1
899
900 #define LINKEVENT_LINKSPEED_MBPS 0
901 #define LINKEVENT_LINKSPEED_ENCODED 1
902
903 /* firmware response header:
904 * 63:58 - message type
905 * 57:56 - owner
906 * 55:53 - desc count
907 * 52:48 - reserved
908 * 47:40 - completion id
909 * 39:32 - opcode
910 * 31:16 - error code
911 * 15:00 - reserved
912 */
913 #define qlcnic_get_nic_msg_opcode(msg_hdr) \
914 ((msg_hdr >> 32) & 0xFF)
915
916 struct qlcnic_fw_msg {
917 union {
918 struct {
919 u64 hdr;
920 u64 body[7];
921 };
922 u64 words[8];
923 };
924 };
925
926 struct qlcnic_nic_req {
927 __le64 qhdr;
928 __le64 req_hdr;
929 __le64 words[6];
930 } __packed;
931
932 struct qlcnic_mac_req {
933 u8 op;
934 u8 tag;
935 u8 mac_addr[6];
936 };
937
938 struct qlcnic_vlan_req {
939 __le16 vlan_id;
940 __le16 rsvd[3];
941 } __packed;
942
943 struct qlcnic_ipaddr {
944 __be32 ipv4;
945 __be32 ipv6[4];
946 };
947
948 #define QLCNIC_MSI_ENABLED 0x02
949 #define QLCNIC_MSIX_ENABLED 0x04
950 #define QLCNIC_LRO_ENABLED 0x01
951 #define QLCNIC_LRO_DISABLED 0x00
952 #define QLCNIC_BRIDGE_ENABLED 0X10
953 #define QLCNIC_DIAG_ENABLED 0x20
954 #define QLCNIC_ESWITCH_ENABLED 0x40
955 #define QLCNIC_ADAPTER_INITIALIZED 0x80
956 #define QLCNIC_TAGGING_ENABLED 0x100
957 #define QLCNIC_MACSPOOF 0x200
958 #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400
959 #define QLCNIC_PROMISC_DISABLED 0x800
960 #define QLCNIC_NEED_FLR 0x1000
961 #define QLCNIC_FW_RESET_OWNER 0x2000
962 #define QLCNIC_FW_HANG 0x4000
963 #define QLCNIC_FW_LRO_MSS_CAP 0x8000
964 #define QLCNIC_TX_INTR_SHARED 0x10000
965 #define QLCNIC_APP_CHANGED_FLAGS 0x20000
966 #define QLCNIC_HAS_PHYS_PORT_ID 0x40000
967 #define QLCNIC_TSS_RSS 0x80000
968
969 #define QLCNIC_IS_MSI_FAMILY(adapter) \
970 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
971 #define QLCNIC_IS_TSO_CAPABLE(adapter) \
972 ((adapter)->ahw->capabilities & QLCNIC_FW_CAPABILITY_TSO)
973
974 #define QLCNIC_BEACON_EANBLE 0xC
975 #define QLCNIC_BEACON_DISABLE 0xD
976
977 #define QLCNIC_BEACON_ON 2
978 #define QLCNIC_BEACON_OFF 0
979
980 #define QLCNIC_MSIX_TBL_SPACE 8192
981 #define QLCNIC_PCI_REG_MSIX_TBL 0x44
982 #define QLCNIC_MSIX_TBL_PGSIZE 4096
983
984 #define QLCNIC_ADAPTER_UP_MAGIC 777
985
986 #define __QLCNIC_FW_ATTACHED 0
987 #define __QLCNIC_DEV_UP 1
988 #define __QLCNIC_RESETTING 2
989 #define __QLCNIC_START_FW 4
990 #define __QLCNIC_AER 5
991 #define __QLCNIC_DIAG_RES_ALLOC 6
992 #define __QLCNIC_LED_ENABLE 7
993 #define __QLCNIC_ELB_INPROGRESS 8
994 #define __QLCNIC_MULTI_TX_UNIQUE 9
995 #define __QLCNIC_SRIOV_ENABLE 10
996 #define __QLCNIC_SRIOV_CAPABLE 11
997 #define __QLCNIC_MBX_POLL_ENABLE 12
998 #define __QLCNIC_DIAG_MODE 13
999 #define __QLCNIC_MAINTENANCE_MODE 16
1000
1001 #define QLCNIC_INTERRUPT_TEST 1
1002 #define QLCNIC_LOOPBACK_TEST 2
1003 #define QLCNIC_LED_TEST 3
1004
1005 #define QLCNIC_FILTER_AGE 80
1006 #define QLCNIC_READD_AGE 20
1007 #define QLCNIC_LB_MAX_FILTERS 64
1008 #define QLCNIC_LB_BUCKET_SIZE 32
1009 #define QLCNIC_ILB_MAX_RCV_LOOP 10
1010
1011 struct qlcnic_filter {
1012 struct hlist_node fnode;
1013 u8 faddr[ETH_ALEN];
1014 u16 vlan_id;
1015 unsigned long ftime;
1016 };
1017
1018 struct qlcnic_filter_hash {
1019 struct hlist_head *fhead;
1020 u8 fnum;
1021 u16 fmax;
1022 u16 fbucket_size;
1023 };
1024
1025 /* Mailbox specific data structures */
1026 struct qlcnic_mailbox {
1027 struct workqueue_struct *work_q;
1028 struct qlcnic_adapter *adapter;
1029 struct qlcnic_mbx_ops *ops;
1030 struct work_struct work;
1031 struct completion completion;
1032 struct list_head cmd_q;
1033 unsigned long status;
1034 spinlock_t queue_lock; /* Mailbox queue lock */
1035 spinlock_t aen_lock; /* Mailbox response/AEN lock */
1036 atomic_t rsp_status;
1037 u32 num_cmds;
1038 };
1039
1040 struct qlcnic_adapter {
1041 struct qlcnic_hardware_context *ahw;
1042 struct qlcnic_recv_context *recv_ctx;
1043 struct qlcnic_host_tx_ring *tx_ring;
1044 struct net_device *netdev;
1045 struct pci_dev *pdev;
1046
1047 unsigned long state;
1048 u32 flags;
1049
1050 u16 num_txd;
1051 u16 num_rxd;
1052 u16 num_jumbo_rxd;
1053 u16 max_rxd;
1054 u16 max_jumbo_rxd;
1055
1056 u8 max_rds_rings;
1057
1058 u8 max_sds_rings; /* max sds rings supported by adapter */
1059 u8 max_tx_rings; /* max tx rings supported by adapter */
1060
1061 u8 drv_tx_rings; /* max tx rings supported by driver */
1062 u8 drv_sds_rings; /* max sds rings supported by driver */
1063
1064 u8 drv_tss_rings; /* tss ring input */
1065 u8 drv_rss_rings; /* rss ring input */
1066
1067 u8 rx_csum;
1068 u8 portnum;
1069
1070 u8 fw_wait_cnt;
1071 u8 fw_fail_cnt;
1072 u8 tx_timeo_cnt;
1073 u8 need_fw_reset;
1074 u8 reset_ctx_cnt;
1075
1076 u16 is_up;
1077 u16 rx_pvid;
1078 u16 tx_pvid;
1079
1080 u32 irq;
1081 u32 heartbeat;
1082
1083 u8 dev_state;
1084 u8 reset_ack_timeo;
1085 u8 dev_init_timeo;
1086
1087 u8 mac_addr[ETH_ALEN];
1088
1089 u64 dev_rst_time;
1090 bool drv_mac_learn;
1091 bool fdb_mac_learn;
1092 bool rx_mac_learn;
1093 unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)];
1094 u8 flash_mfg_id;
1095 struct qlcnic_npar_info *npars;
1096 struct qlcnic_eswitch *eswitch;
1097 struct qlcnic_nic_template *nic_ops;
1098
1099 struct qlcnic_adapter_stats stats;
1100 struct list_head mac_list;
1101
1102 void __iomem *tgt_mask_reg;
1103 void __iomem *tgt_status_reg;
1104 void __iomem *crb_int_state_reg;
1105 void __iomem *isr_int_vec;
1106
1107 struct msix_entry *msix_entries;
1108 struct workqueue_struct *qlcnic_wq;
1109 struct delayed_work fw_work;
1110 struct delayed_work idc_aen_work;
1111 struct delayed_work mbx_poll_work;
1112 struct qlcnic_dcb *dcb;
1113
1114 struct qlcnic_filter_hash fhash;
1115 struct qlcnic_filter_hash rx_fhash;
1116 struct list_head vf_mc_list;
1117
1118 spinlock_t mac_learn_lock;
1119 /* spinlock for catching rcv filters for eswitch traffic */
1120 spinlock_t rx_mac_learn_lock;
1121 u32 file_prd_off; /*File fw product offset*/
1122 u32 fw_version;
1123 u32 offload_flags;
1124 const struct firmware *fw;
1125 };
1126
1127 struct qlcnic_info_le {
1128 __le16 pci_func;
1129 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */
1130 __le16 phys_port;
1131 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */
1132
1133 __le32 capabilities;
1134 u8 max_mac_filters;
1135 u8 reserved1;
1136 __le16 max_mtu;
1137
1138 __le16 max_tx_ques;
1139 __le16 max_rx_ques;
1140 __le16 min_tx_bw;
1141 __le16 max_tx_bw;
1142 __le32 op_type;
1143 __le16 max_bw_reg_offset;
1144 __le16 max_linkspeed_reg_offset;
1145 __le32 capability1;
1146 __le32 capability2;
1147 __le32 capability3;
1148 __le16 max_tx_mac_filters;
1149 __le16 max_rx_mcast_mac_filters;
1150 __le16 max_rx_ucast_mac_filters;
1151 __le16 max_rx_ip_addr;
1152 __le16 max_rx_lro_flow;
1153 __le16 max_rx_status_rings;
1154 __le16 max_rx_buf_rings;
1155 __le16 max_tx_vlan_keys;
1156 u8 total_pf;
1157 u8 total_rss_engines;
1158 __le16 max_vports;
1159 __le16 linkstate_reg_offset;
1160 __le16 bit_offsets;
1161 __le16 max_local_ipv6_addrs;
1162 __le16 max_remote_ipv6_addrs;
1163 u8 reserved2[56];
1164 } __packed;
1165
1166 struct qlcnic_info {
1167 u16 pci_func;
1168 u16 op_mode;
1169 u16 phys_port;
1170 u16 switch_mode;
1171 u32 capabilities;
1172 u8 max_mac_filters;
1173 u16 max_mtu;
1174 u16 max_tx_ques;
1175 u16 max_rx_ques;
1176 u16 min_tx_bw;
1177 u16 max_tx_bw;
1178 u32 op_type;
1179 u16 max_bw_reg_offset;
1180 u16 max_linkspeed_reg_offset;
1181 u32 capability1;
1182 u32 capability2;
1183 u32 capability3;
1184 u16 max_tx_mac_filters;
1185 u16 max_rx_mcast_mac_filters;
1186 u16 max_rx_ucast_mac_filters;
1187 u16 max_rx_ip_addr;
1188 u16 max_rx_lro_flow;
1189 u16 max_rx_status_rings;
1190 u16 max_rx_buf_rings;
1191 u16 max_tx_vlan_keys;
1192 u8 total_pf;
1193 u8 total_rss_engines;
1194 u16 max_vports;
1195 u16 linkstate_reg_offset;
1196 u16 bit_offsets;
1197 u16 max_local_ipv6_addrs;
1198 u16 max_remote_ipv6_addrs;
1199 };
1200
1201 struct qlcnic_pci_info_le {
1202 __le16 id; /* pci function id */
1203 __le16 active; /* 1 = Enabled */
1204 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */
1205 __le16 default_port; /* default port number */
1206
1207 __le16 tx_min_bw; /* Multiple of 100mbpc */
1208 __le16 tx_max_bw;
1209 __le16 reserved1[2];
1210
1211 u8 mac[ETH_ALEN];
1212 __le16 func_count;
1213 u8 reserved2[104];
1214
1215 } __packed;
1216
1217 struct qlcnic_pci_info {
1218 u16 id;
1219 u16 active;
1220 u16 type;
1221 u16 default_port;
1222 u16 tx_min_bw;
1223 u16 tx_max_bw;
1224 u8 mac[ETH_ALEN];
1225 u16 func_count;
1226 };
1227
1228 struct qlcnic_npar_info {
1229 bool eswitch_status;
1230 u16 pvid;
1231 u16 min_bw;
1232 u16 max_bw;
1233 u8 phy_port;
1234 u8 type;
1235 u8 active;
1236 u8 enable_pm;
1237 u8 dest_npar;
1238 u8 discard_tagged;
1239 u8 mac_override;
1240 u8 mac_anti_spoof;
1241 u8 promisc_mode;
1242 u8 offload_flags;
1243 u8 pci_func;
1244 u8 mac[ETH_ALEN];
1245 };
1246
1247 struct qlcnic_eswitch {
1248 u8 port;
1249 u8 active_vports;
1250 u8 active_vlans;
1251 u8 active_ucast_filters;
1252 u8 max_ucast_filters;
1253 u8 max_active_vlans;
1254
1255 u32 flags;
1256 #define QLCNIC_SWITCH_ENABLE BIT_1
1257 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2
1258 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3
1259 #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4
1260 };
1261
1262
1263 /* Return codes for Error handling */
1264 #define QL_STATUS_INVALID_PARAM -1
1265
1266 #define MAX_BW 100 /* % of link speed */
1267 #define MAX_VLAN_ID 4095
1268 #define MIN_VLAN_ID 2
1269 #define DEFAULT_MAC_LEARN 1
1270
1271 #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID)
1272 #define IS_VALID_BW(bw) (bw <= MAX_BW)
1273
1274 struct qlcnic_pci_func_cfg {
1275 u16 func_type;
1276 u16 min_bw;
1277 u16 max_bw;
1278 u16 port_num;
1279 u8 pci_func;
1280 u8 func_state;
1281 u8 def_mac_addr[ETH_ALEN];
1282 };
1283
1284 struct qlcnic_npar_func_cfg {
1285 u32 fw_capab;
1286 u16 port_num;
1287 u16 min_bw;
1288 u16 max_bw;
1289 u16 max_tx_queues;
1290 u16 max_rx_queues;
1291 u8 pci_func;
1292 u8 op_mode;
1293 };
1294
1295 struct qlcnic_pm_func_cfg {
1296 u8 pci_func;
1297 u8 action;
1298 u8 dest_npar;
1299 u8 reserved[5];
1300 };
1301
1302 struct qlcnic_esw_func_cfg {
1303 u16 vlan_id;
1304 u8 op_mode;
1305 u8 op_type;
1306 u8 pci_func;
1307 u8 host_vlan_tag;
1308 u8 promisc_mode;
1309 u8 discard_tagged;
1310 u8 mac_override;
1311 u8 mac_anti_spoof;
1312 u8 offload_flags;
1313 u8 reserved[5];
1314 };
1315
1316 #define QLCNIC_STATS_VERSION 1
1317 #define QLCNIC_STATS_PORT 1
1318 #define QLCNIC_STATS_ESWITCH 2
1319 #define QLCNIC_QUERY_RX_COUNTER 0
1320 #define QLCNIC_QUERY_TX_COUNTER 1
1321 #define QLCNIC_STATS_NOT_AVAIL 0xffffffffffffffffULL
1322 #define QLCNIC_FILL_STATS(VAL1) \
1323 (((VAL1) == QLCNIC_STATS_NOT_AVAIL) ? 0 : VAL1)
1324 #define QLCNIC_MAC_STATS 1
1325 #define QLCNIC_ESW_STATS 2
1326
1327 #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\
1328 do { \
1329 if (((VAL1) == QLCNIC_STATS_NOT_AVAIL) && \
1330 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \
1331 (VAL1) = (VAL2); \
1332 else if (((VAL1) != QLCNIC_STATS_NOT_AVAIL) && \
1333 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \
1334 (VAL1) += (VAL2); \
1335 } while (0)
1336
1337 struct qlcnic_mac_statistics_le {
1338 __le64 mac_tx_frames;
1339 __le64 mac_tx_bytes;
1340 __le64 mac_tx_mcast_pkts;
1341 __le64 mac_tx_bcast_pkts;
1342 __le64 mac_tx_pause_cnt;
1343 __le64 mac_tx_ctrl_pkt;
1344 __le64 mac_tx_lt_64b_pkts;
1345 __le64 mac_tx_lt_127b_pkts;
1346 __le64 mac_tx_lt_255b_pkts;
1347 __le64 mac_tx_lt_511b_pkts;
1348 __le64 mac_tx_lt_1023b_pkts;
1349 __le64 mac_tx_lt_1518b_pkts;
1350 __le64 mac_tx_gt_1518b_pkts;
1351 __le64 rsvd1[3];
1352
1353 __le64 mac_rx_frames;
1354 __le64 mac_rx_bytes;
1355 __le64 mac_rx_mcast_pkts;
1356 __le64 mac_rx_bcast_pkts;
1357 __le64 mac_rx_pause_cnt;
1358 __le64 mac_rx_ctrl_pkt;
1359 __le64 mac_rx_lt_64b_pkts;
1360 __le64 mac_rx_lt_127b_pkts;
1361 __le64 mac_rx_lt_255b_pkts;
1362 __le64 mac_rx_lt_511b_pkts;
1363 __le64 mac_rx_lt_1023b_pkts;
1364 __le64 mac_rx_lt_1518b_pkts;
1365 __le64 mac_rx_gt_1518b_pkts;
1366 __le64 rsvd2[3];
1367
1368 __le64 mac_rx_length_error;
1369 __le64 mac_rx_length_small;
1370 __le64 mac_rx_length_large;
1371 __le64 mac_rx_jabber;
1372 __le64 mac_rx_dropped;
1373 __le64 mac_rx_crc_error;
1374 __le64 mac_align_error;
1375 } __packed;
1376
1377 struct qlcnic_mac_statistics {
1378 u64 mac_tx_frames;
1379 u64 mac_tx_bytes;
1380 u64 mac_tx_mcast_pkts;
1381 u64 mac_tx_bcast_pkts;
1382 u64 mac_tx_pause_cnt;
1383 u64 mac_tx_ctrl_pkt;
1384 u64 mac_tx_lt_64b_pkts;
1385 u64 mac_tx_lt_127b_pkts;
1386 u64 mac_tx_lt_255b_pkts;
1387 u64 mac_tx_lt_511b_pkts;
1388 u64 mac_tx_lt_1023b_pkts;
1389 u64 mac_tx_lt_1518b_pkts;
1390 u64 mac_tx_gt_1518b_pkts;
1391 u64 rsvd1[3];
1392 u64 mac_rx_frames;
1393 u64 mac_rx_bytes;
1394 u64 mac_rx_mcast_pkts;
1395 u64 mac_rx_bcast_pkts;
1396 u64 mac_rx_pause_cnt;
1397 u64 mac_rx_ctrl_pkt;
1398 u64 mac_rx_lt_64b_pkts;
1399 u64 mac_rx_lt_127b_pkts;
1400 u64 mac_rx_lt_255b_pkts;
1401 u64 mac_rx_lt_511b_pkts;
1402 u64 mac_rx_lt_1023b_pkts;
1403 u64 mac_rx_lt_1518b_pkts;
1404 u64 mac_rx_gt_1518b_pkts;
1405 u64 rsvd2[3];
1406 u64 mac_rx_length_error;
1407 u64 mac_rx_length_small;
1408 u64 mac_rx_length_large;
1409 u64 mac_rx_jabber;
1410 u64 mac_rx_dropped;
1411 u64 mac_rx_crc_error;
1412 u64 mac_align_error;
1413 };
1414
1415 struct qlcnic_esw_stats_le {
1416 __le16 context_id;
1417 __le16 version;
1418 __le16 size;
1419 __le16 unused;
1420 __le64 unicast_frames;
1421 __le64 multicast_frames;
1422 __le64 broadcast_frames;
1423 __le64 dropped_frames;
1424 __le64 errors;
1425 __le64 local_frames;
1426 __le64 numbytes;
1427 __le64 rsvd[3];
1428 } __packed;
1429
1430 struct __qlcnic_esw_statistics {
1431 u16 context_id;
1432 u16 version;
1433 u16 size;
1434 u16 unused;
1435 u64 unicast_frames;
1436 u64 multicast_frames;
1437 u64 broadcast_frames;
1438 u64 dropped_frames;
1439 u64 errors;
1440 u64 local_frames;
1441 u64 numbytes;
1442 u64 rsvd[3];
1443 };
1444
1445 struct qlcnic_esw_statistics {
1446 struct __qlcnic_esw_statistics rx;
1447 struct __qlcnic_esw_statistics tx;
1448 };
1449
1450 #define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed
1451 #define QLCNIC_ENABLE_FW_DUMP 0xaddfeed
1452 #define QLCNIC_DISABLE_FW_DUMP 0xbadfeed
1453 #define QLCNIC_FORCE_FW_RESET 0xdeaddead
1454 #define QLCNIC_SET_QUIESCENT 0xadd00010
1455 #define QLCNIC_RESET_QUIESCENT 0xadd00020
1456
1457 struct _cdrp_cmd {
1458 u32 num;
1459 u32 *arg;
1460 };
1461
1462 struct qlcnic_cmd_args {
1463 struct completion completion;
1464 struct list_head list;
1465 struct _cdrp_cmd req;
1466 struct _cdrp_cmd rsp;
1467 atomic_t rsp_status;
1468 int pay_size;
1469 u32 rsp_opcode;
1470 u32 total_cmds;
1471 u32 op_type;
1472 u32 type;
1473 u32 cmd_op;
1474 u32 *hdr; /* Back channel message header */
1475 u32 *pay; /* Back channel message payload */
1476 u8 func_num;
1477 };
1478
1479 int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter);
1480 int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config);
1481 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data);
1482 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data);
1483
1484 #define ADDR_IN_RANGE(addr, low, high) \
1485 (((addr) < (high)) && ((addr) >= (low)))
1486
1487 #define QLCRD32(adapter, off, err) \
1488 (adapter->ahw->hw_ops->read_reg)(adapter, off, err)
1489
1490 #define QLCWR32(adapter, off, val) \
1491 adapter->ahw->hw_ops->write_reg(adapter, off, val)
1492
1493 int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32);
1494 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int);
1495
1496 #define qlcnic_rom_lock(a) \
1497 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID)
1498 #define qlcnic_rom_unlock(a) \
1499 qlcnic_pcie_sem_unlock((a), 2)
1500 #define qlcnic_phy_lock(a) \
1501 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID)
1502 #define qlcnic_phy_unlock(a) \
1503 qlcnic_pcie_sem_unlock((a), 3)
1504 #define qlcnic_sw_lock(a) \
1505 qlcnic_pcie_sem_lock((a), 6, 0)
1506 #define qlcnic_sw_unlock(a) \
1507 qlcnic_pcie_sem_unlock((a), 6)
1508 #define crb_win_lock(a) \
1509 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID)
1510 #define crb_win_unlock(a) \
1511 qlcnic_pcie_sem_unlock((a), 7)
1512
1513 #define __QLCNIC_MAX_LED_RATE 0xf
1514 #define __QLCNIC_MAX_LED_STATE 0x2
1515
1516 #define MAX_CTL_CHECK 1000
1517
1518 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter);
1519 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter);
1520 int qlcnic_dump_fw(struct qlcnic_adapter *);
1521 int qlcnic_enable_fw_dump_state(struct qlcnic_adapter *);
1522 bool qlcnic_check_fw_dump_state(struct qlcnic_adapter *);
1523
1524 /* Functions from qlcnic_init.c */
1525 void qlcnic_schedule_work(struct qlcnic_adapter *, work_func_t, int);
1526 int qlcnic_load_firmware(struct qlcnic_adapter *adapter);
1527 int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter);
1528 void qlcnic_request_firmware(struct qlcnic_adapter *adapter);
1529 void qlcnic_release_firmware(struct qlcnic_adapter *adapter);
1530 int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter);
1531 int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter);
1532 int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter);
1533
1534 int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp);
1535 int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
1536 u8 *bytes, size_t size);
1537 int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter);
1538 void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter);
1539
1540 void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *, u32);
1541
1542 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter);
1543 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter);
1544
1545 int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter);
1546 void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter);
1547
1548 void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter);
1549 void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter);
1550 void qlcnic_release_tx_buffers(struct qlcnic_adapter *,
1551 struct qlcnic_host_tx_ring *);
1552
1553 int qlcnic_check_fw_status(struct qlcnic_adapter *adapter);
1554 void qlcnic_watchdog_task(struct work_struct *work);
1555 void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter,
1556 struct qlcnic_host_rds_ring *rds_ring, u8 ring_id);
1557 void qlcnic_set_multi(struct net_device *netdev);
1558 int qlcnic_nic_add_mac(struct qlcnic_adapter *, const u8 *, u16);
1559 int qlcnic_nic_del_mac(struct qlcnic_adapter *, const u8 *);
1560 void qlcnic_82xx_free_mac_list(struct qlcnic_adapter *adapter);
1561 int qlcnic_82xx_read_phys_port_id(struct qlcnic_adapter *);
1562
1563 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu);
1564 int qlcnic_fw_cmd_set_drv_version(struct qlcnic_adapter *, u32);
1565 int qlcnic_change_mtu(struct net_device *netdev, int new_mtu);
1566 netdev_features_t qlcnic_fix_features(struct net_device *netdev,
1567 netdev_features_t features);
1568 int qlcnic_set_features(struct net_device *netdev, netdev_features_t features);
1569 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable);
1570 void qlcnic_update_cmd_producer(struct qlcnic_host_tx_ring *);
1571
1572 /* Functions from qlcnic_ethtool.c */
1573 int qlcnic_check_loopback_buff(unsigned char *, u8 []);
1574 int qlcnic_do_lb_test(struct qlcnic_adapter *, u8);
1575
1576 /* Functions from qlcnic_main.c */
1577 int qlcnic_reset_context(struct qlcnic_adapter *);
1578 void qlcnic_diag_free_res(struct net_device *netdev, int);
1579 int qlcnic_diag_alloc_res(struct net_device *netdev, int);
1580 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *, struct net_device *);
1581 void qlcnic_set_tx_ring_count(struct qlcnic_adapter *, u8);
1582 void qlcnic_set_sds_ring_count(struct qlcnic_adapter *, u8);
1583 int qlcnic_setup_rings(struct qlcnic_adapter *);
1584 int qlcnic_validate_rings(struct qlcnic_adapter *, __u32, int);
1585 void qlcnic_alloc_lb_filters_mem(struct qlcnic_adapter *adapter);
1586 int qlcnic_enable_msix(struct qlcnic_adapter *, u32);
1587 void qlcnic_set_drv_version(struct qlcnic_adapter *);
1588
1589 /* eSwitch management functions */
1590 int qlcnic_config_switch_port(struct qlcnic_adapter *,
1591 struct qlcnic_esw_func_cfg *);
1592
1593 int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *,
1594 struct qlcnic_esw_func_cfg *);
1595 int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8);
1596 int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8,
1597 struct __qlcnic_esw_statistics *);
1598 int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8,
1599 struct __qlcnic_esw_statistics *);
1600 int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8);
1601 int qlcnic_get_mac_stats(struct qlcnic_adapter *, struct qlcnic_mac_statistics *);
1602
1603 void qlcnic_free_mbx_args(struct qlcnic_cmd_args *cmd);
1604
1605 int qlcnic_alloc_sds_rings(struct qlcnic_recv_context *, int);
1606 void qlcnic_free_sds_rings(struct qlcnic_recv_context *);
1607 void qlcnic_advert_link_change(struct qlcnic_adapter *, int);
1608 void qlcnic_free_tx_rings(struct qlcnic_adapter *);
1609 int qlcnic_alloc_tx_rings(struct qlcnic_adapter *, struct net_device *);
1610 void qlcnic_dump_mbx(struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1611
1612 void qlcnic_create_sysfs_entries(struct qlcnic_adapter *adapter);
1613 void qlcnic_remove_sysfs_entries(struct qlcnic_adapter *adapter);
1614 void qlcnic_82xx_add_sysfs(struct qlcnic_adapter *adapter);
1615 void qlcnic_82xx_remove_sysfs(struct qlcnic_adapter *adapter);
1616
1617 int qlcnicvf_config_bridged_mode(struct qlcnic_adapter *, u32);
1618 int qlcnicvf_config_led(struct qlcnic_adapter *, u32, u32);
1619 void qlcnic_set_vlan_config(struct qlcnic_adapter *,
1620 struct qlcnic_esw_func_cfg *);
1621 void qlcnic_set_eswitch_port_features(struct qlcnic_adapter *,
1622 struct qlcnic_esw_func_cfg *);
1623 int qlcnic_setup_tss_rss_intr(struct qlcnic_adapter *);
1624 void qlcnic_down(struct qlcnic_adapter *, struct net_device *);
1625 int qlcnic_up(struct qlcnic_adapter *, struct net_device *);
1626 void __qlcnic_down(struct qlcnic_adapter *, struct net_device *);
1627 void qlcnic_detach(struct qlcnic_adapter *);
1628 void qlcnic_teardown_intr(struct qlcnic_adapter *);
1629 int qlcnic_attach(struct qlcnic_adapter *);
1630 int __qlcnic_up(struct qlcnic_adapter *, struct net_device *);
1631 void qlcnic_restore_indev_addr(struct net_device *, unsigned long);
1632
1633 int qlcnic_check_temp(struct qlcnic_adapter *);
1634 int qlcnic_init_pci_info(struct qlcnic_adapter *);
1635 int qlcnic_set_default_offload_settings(struct qlcnic_adapter *);
1636 int qlcnic_reset_npar_config(struct qlcnic_adapter *);
1637 int qlcnic_set_eswitch_port_config(struct qlcnic_adapter *);
1638 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter);
1639 int qlcnic_read_mac_addr(struct qlcnic_adapter *);
1640 int qlcnic_setup_netdev(struct qlcnic_adapter *, struct net_device *, int);
1641 void qlcnic_set_netdev_features(struct qlcnic_adapter *,
1642 struct qlcnic_esw_func_cfg *);
1643 void qlcnic_sriov_vf_schedule_multi(struct net_device *);
1644 int qlcnic_is_valid_nic_func(struct qlcnic_adapter *, u8);
1645 int qlcnic_get_pci_func_type(struct qlcnic_adapter *, u16, u16 *, u16 *,
1646 u16 *);
1647
1648 /*
1649 * QLOGIC Board information
1650 */
1651
1652 #define QLCNIC_MAX_BOARD_NAME_LEN 100
1653 struct qlcnic_board_info {
1654 unsigned short vendor;
1655 unsigned short device;
1656 unsigned short sub_vendor;
1657 unsigned short sub_device;
1658 char short_name[QLCNIC_MAX_BOARD_NAME_LEN];
1659 };
1660
1661 static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring)
1662 {
1663 if (likely(tx_ring->producer < tx_ring->sw_consumer))
1664 return tx_ring->sw_consumer - tx_ring->producer;
1665 else
1666 return tx_ring->sw_consumer + tx_ring->num_desc -
1667 tx_ring->producer;
1668 }
1669
1670 static inline int qlcnic_set_real_num_queues(struct qlcnic_adapter *adapter,
1671 struct net_device *netdev)
1672 {
1673 int err;
1674
1675 netdev->num_tx_queues = adapter->drv_tx_rings;
1676 netdev->real_num_tx_queues = adapter->drv_tx_rings;
1677
1678 err = netif_set_real_num_tx_queues(netdev, adapter->drv_tx_rings);
1679 if (err)
1680 netdev_err(netdev, "failed to set %d Tx queues\n",
1681 adapter->drv_tx_rings);
1682
1683 return err;
1684 }
1685
1686 struct qlcnic_nic_template {
1687 int (*config_bridged_mode) (struct qlcnic_adapter *, u32);
1688 int (*config_led) (struct qlcnic_adapter *, u32, u32);
1689 int (*start_firmware) (struct qlcnic_adapter *);
1690 int (*init_driver) (struct qlcnic_adapter *);
1691 void (*request_reset) (struct qlcnic_adapter *, u32);
1692 void (*cancel_idc_work) (struct qlcnic_adapter *);
1693 int (*napi_add)(struct qlcnic_adapter *, struct net_device *);
1694 void (*napi_del)(struct qlcnic_adapter *);
1695 void (*config_ipaddr)(struct qlcnic_adapter *, __be32, int);
1696 irqreturn_t (*clear_legacy_intr)(struct qlcnic_adapter *);
1697 int (*shutdown)(struct pci_dev *);
1698 int (*resume)(struct qlcnic_adapter *);
1699 };
1700
1701 struct qlcnic_mbx_ops {
1702 int (*enqueue_cmd) (struct qlcnic_adapter *,
1703 struct qlcnic_cmd_args *, unsigned long *);
1704 void (*dequeue_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1705 void (*decode_resp) (struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1706 void (*encode_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1707 void (*nofity_fw) (struct qlcnic_adapter *, u8);
1708 };
1709
1710 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *);
1711 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *);
1712 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx);
1713 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx);
1714 void qlcnic_update_stats(struct qlcnic_adapter *);
1715
1716 /* Adapter hardware abstraction */
1717 struct qlcnic_hardware_ops {
1718 void (*read_crb) (struct qlcnic_adapter *, char *, loff_t, size_t);
1719 void (*write_crb) (struct qlcnic_adapter *, char *, loff_t, size_t);
1720 int (*read_reg) (struct qlcnic_adapter *, ulong, int *);
1721 int (*write_reg) (struct qlcnic_adapter *, ulong, u32);
1722 void (*get_ocm_win) (struct qlcnic_hardware_context *);
1723 int (*get_mac_address) (struct qlcnic_adapter *, u8 *, u8);
1724 int (*setup_intr) (struct qlcnic_adapter *);
1725 int (*alloc_mbx_args)(struct qlcnic_cmd_args *,
1726 struct qlcnic_adapter *, u32);
1727 int (*mbx_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1728 void (*get_func_no) (struct qlcnic_adapter *);
1729 int (*api_lock) (struct qlcnic_adapter *);
1730 void (*api_unlock) (struct qlcnic_adapter *);
1731 void (*add_sysfs) (struct qlcnic_adapter *);
1732 void (*remove_sysfs) (struct qlcnic_adapter *);
1733 void (*process_lb_rcv_ring_diag) (struct qlcnic_host_sds_ring *);
1734 int (*create_rx_ctx) (struct qlcnic_adapter *);
1735 int (*create_tx_ctx) (struct qlcnic_adapter *,
1736 struct qlcnic_host_tx_ring *, int);
1737 void (*del_rx_ctx) (struct qlcnic_adapter *);
1738 void (*del_tx_ctx) (struct qlcnic_adapter *,
1739 struct qlcnic_host_tx_ring *);
1740 int (*setup_link_event) (struct qlcnic_adapter *, int);
1741 int (*get_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *, u8);
1742 int (*get_pci_info) (struct qlcnic_adapter *, struct qlcnic_pci_info *);
1743 int (*set_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *);
1744 int (*change_macvlan) (struct qlcnic_adapter *, u8*, u16, u8);
1745 void (*napi_enable) (struct qlcnic_adapter *);
1746 void (*napi_disable) (struct qlcnic_adapter *);
1747 int (*config_intr_coal) (struct qlcnic_adapter *,
1748 struct ethtool_coalesce *);
1749 int (*config_rss) (struct qlcnic_adapter *, int);
1750 int (*config_hw_lro) (struct qlcnic_adapter *, int);
1751 int (*config_loopback) (struct qlcnic_adapter *, u8);
1752 int (*clear_loopback) (struct qlcnic_adapter *, u8);
1753 int (*config_promisc_mode) (struct qlcnic_adapter *, u32);
1754 void (*change_l2_filter) (struct qlcnic_adapter *, u64 *, u16);
1755 int (*get_board_info) (struct qlcnic_adapter *);
1756 void (*set_mac_filter_count) (struct qlcnic_adapter *);
1757 void (*free_mac_list) (struct qlcnic_adapter *);
1758 int (*read_phys_port_id) (struct qlcnic_adapter *);
1759 pci_ers_result_t (*io_error_detected) (struct pci_dev *,
1760 pci_channel_state_t);
1761 pci_ers_result_t (*io_slot_reset) (struct pci_dev *);
1762 void (*io_resume) (struct pci_dev *);
1763 void (*get_beacon_state)(struct qlcnic_adapter *);
1764 void (*enable_sds_intr) (struct qlcnic_adapter *,
1765 struct qlcnic_host_sds_ring *);
1766 void (*disable_sds_intr) (struct qlcnic_adapter *,
1767 struct qlcnic_host_sds_ring *);
1768 void (*enable_tx_intr) (struct qlcnic_adapter *,
1769 struct qlcnic_host_tx_ring *);
1770 void (*disable_tx_intr) (struct qlcnic_adapter *,
1771 struct qlcnic_host_tx_ring *);
1772 };
1773
1774 extern struct qlcnic_nic_template qlcnic_vf_ops;
1775
1776 static inline int qlcnic_start_firmware(struct qlcnic_adapter *adapter)
1777 {
1778 return adapter->nic_ops->start_firmware(adapter);
1779 }
1780
1781 static inline void qlcnic_read_crb(struct qlcnic_adapter *adapter, char *buf,
1782 loff_t offset, size_t size)
1783 {
1784 adapter->ahw->hw_ops->read_crb(adapter, buf, offset, size);
1785 }
1786
1787 static inline void qlcnic_write_crb(struct qlcnic_adapter *adapter, char *buf,
1788 loff_t offset, size_t size)
1789 {
1790 adapter->ahw->hw_ops->write_crb(adapter, buf, offset, size);
1791 }
1792
1793 static inline int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter,
1794 ulong off, u32 data)
1795 {
1796 return adapter->ahw->hw_ops->write_reg(adapter, off, data);
1797 }
1798
1799 static inline int qlcnic_get_mac_address(struct qlcnic_adapter *adapter,
1800 u8 *mac, u8 function)
1801 {
1802 return adapter->ahw->hw_ops->get_mac_address(adapter, mac, function);
1803 }
1804
1805 static inline int qlcnic_setup_intr(struct qlcnic_adapter *adapter)
1806 {
1807 return adapter->ahw->hw_ops->setup_intr(adapter);
1808 }
1809
1810 static inline int qlcnic_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
1811 struct qlcnic_adapter *adapter, u32 arg)
1812 {
1813 return adapter->ahw->hw_ops->alloc_mbx_args(mbx, adapter, arg);
1814 }
1815
1816 static inline int qlcnic_issue_cmd(struct qlcnic_adapter *adapter,
1817 struct qlcnic_cmd_args *cmd)
1818 {
1819 if (adapter->ahw->hw_ops->mbx_cmd)
1820 return adapter->ahw->hw_ops->mbx_cmd(adapter, cmd);
1821
1822 return -EIO;
1823 }
1824
1825 static inline void qlcnic_get_func_no(struct qlcnic_adapter *adapter)
1826 {
1827 adapter->ahw->hw_ops->get_func_no(adapter);
1828 }
1829
1830 static inline int qlcnic_api_lock(struct qlcnic_adapter *adapter)
1831 {
1832 return adapter->ahw->hw_ops->api_lock(adapter);
1833 }
1834
1835 static inline void qlcnic_api_unlock(struct qlcnic_adapter *adapter)
1836 {
1837 adapter->ahw->hw_ops->api_unlock(adapter);
1838 }
1839
1840 static inline void qlcnic_add_sysfs(struct qlcnic_adapter *adapter)
1841 {
1842 if (adapter->ahw->hw_ops->add_sysfs)
1843 adapter->ahw->hw_ops->add_sysfs(adapter);
1844 }
1845
1846 static inline void qlcnic_remove_sysfs(struct qlcnic_adapter *adapter)
1847 {
1848 if (adapter->ahw->hw_ops->remove_sysfs)
1849 adapter->ahw->hw_ops->remove_sysfs(adapter);
1850 }
1851
1852 static inline void
1853 qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring)
1854 {
1855 sds_ring->adapter->ahw->hw_ops->process_lb_rcv_ring_diag(sds_ring);
1856 }
1857
1858 static inline int qlcnic_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter)
1859 {
1860 return adapter->ahw->hw_ops->create_rx_ctx(adapter);
1861 }
1862
1863 static inline int qlcnic_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter,
1864 struct qlcnic_host_tx_ring *ptr,
1865 int ring)
1866 {
1867 return adapter->ahw->hw_ops->create_tx_ctx(adapter, ptr, ring);
1868 }
1869
1870 static inline void qlcnic_fw_cmd_del_rx_ctx(struct qlcnic_adapter *adapter)
1871 {
1872 return adapter->ahw->hw_ops->del_rx_ctx(adapter);
1873 }
1874
1875 static inline void qlcnic_fw_cmd_del_tx_ctx(struct qlcnic_adapter *adapter,
1876 struct qlcnic_host_tx_ring *ptr)
1877 {
1878 return adapter->ahw->hw_ops->del_tx_ctx(adapter, ptr);
1879 }
1880
1881 static inline int qlcnic_linkevent_request(struct qlcnic_adapter *adapter,
1882 int enable)
1883 {
1884 return adapter->ahw->hw_ops->setup_link_event(adapter, enable);
1885 }
1886
1887 static inline int qlcnic_get_nic_info(struct qlcnic_adapter *adapter,
1888 struct qlcnic_info *info, u8 id)
1889 {
1890 return adapter->ahw->hw_ops->get_nic_info(adapter, info, id);
1891 }
1892
1893 static inline int qlcnic_get_pci_info(struct qlcnic_adapter *adapter,
1894 struct qlcnic_pci_info *info)
1895 {
1896 return adapter->ahw->hw_ops->get_pci_info(adapter, info);
1897 }
1898
1899 static inline int qlcnic_set_nic_info(struct qlcnic_adapter *adapter,
1900 struct qlcnic_info *info)
1901 {
1902 return adapter->ahw->hw_ops->set_nic_info(adapter, info);
1903 }
1904
1905 static inline int qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter,
1906 u8 *addr, u16 id, u8 cmd)
1907 {
1908 return adapter->ahw->hw_ops->change_macvlan(adapter, addr, id, cmd);
1909 }
1910
1911 static inline int qlcnic_napi_add(struct qlcnic_adapter *adapter,
1912 struct net_device *netdev)
1913 {
1914 return adapter->nic_ops->napi_add(adapter, netdev);
1915 }
1916
1917 static inline void qlcnic_napi_del(struct qlcnic_adapter *adapter)
1918 {
1919 adapter->nic_ops->napi_del(adapter);
1920 }
1921
1922 static inline void qlcnic_napi_enable(struct qlcnic_adapter *adapter)
1923 {
1924 adapter->ahw->hw_ops->napi_enable(adapter);
1925 }
1926
1927 static inline int __qlcnic_shutdown(struct pci_dev *pdev)
1928 {
1929 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
1930
1931 return adapter->nic_ops->shutdown(pdev);
1932 }
1933
1934 static inline int __qlcnic_resume(struct qlcnic_adapter *adapter)
1935 {
1936 return adapter->nic_ops->resume(adapter);
1937 }
1938
1939 static inline void qlcnic_napi_disable(struct qlcnic_adapter *adapter)
1940 {
1941 adapter->ahw->hw_ops->napi_disable(adapter);
1942 }
1943
1944 static inline int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter,
1945 struct ethtool_coalesce *ethcoal)
1946 {
1947 return adapter->ahw->hw_ops->config_intr_coal(adapter, ethcoal);
1948 }
1949
1950 static inline int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable)
1951 {
1952 return adapter->ahw->hw_ops->config_rss(adapter, enable);
1953 }
1954
1955 static inline int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter,
1956 int enable)
1957 {
1958 return adapter->ahw->hw_ops->config_hw_lro(adapter, enable);
1959 }
1960
1961 static inline int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1962 {
1963 return adapter->ahw->hw_ops->config_loopback(adapter, mode);
1964 }
1965
1966 static inline int qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1967 {
1968 return adapter->ahw->hw_ops->clear_loopback(adapter, mode);
1969 }
1970
1971 static inline int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter,
1972 u32 mode)
1973 {
1974 return adapter->ahw->hw_ops->config_promisc_mode(adapter, mode);
1975 }
1976
1977 static inline void qlcnic_change_filter(struct qlcnic_adapter *adapter,
1978 u64 *addr, u16 id)
1979 {
1980 adapter->ahw->hw_ops->change_l2_filter(adapter, addr, id);
1981 }
1982
1983 static inline int qlcnic_get_board_info(struct qlcnic_adapter *adapter)
1984 {
1985 return adapter->ahw->hw_ops->get_board_info(adapter);
1986 }
1987
1988 static inline void qlcnic_free_mac_list(struct qlcnic_adapter *adapter)
1989 {
1990 return adapter->ahw->hw_ops->free_mac_list(adapter);
1991 }
1992
1993 static inline void qlcnic_set_mac_filter_count(struct qlcnic_adapter *adapter)
1994 {
1995 if (adapter->ahw->hw_ops->set_mac_filter_count)
1996 adapter->ahw->hw_ops->set_mac_filter_count(adapter);
1997 }
1998
1999 static inline void qlcnic_get_beacon_state(struct qlcnic_adapter *adapter)
2000 {
2001 adapter->ahw->hw_ops->get_beacon_state(adapter);
2002 }
2003
2004 static inline void qlcnic_read_phys_port_id(struct qlcnic_adapter *adapter)
2005 {
2006 if (adapter->ahw->hw_ops->read_phys_port_id)
2007 adapter->ahw->hw_ops->read_phys_port_id(adapter);
2008 }
2009
2010 static inline void qlcnic_dev_request_reset(struct qlcnic_adapter *adapter,
2011 u32 key)
2012 {
2013 if (adapter->nic_ops->request_reset)
2014 adapter->nic_ops->request_reset(adapter, key);
2015 }
2016
2017 static inline void qlcnic_cancel_idc_work(struct qlcnic_adapter *adapter)
2018 {
2019 if (adapter->nic_ops->cancel_idc_work)
2020 adapter->nic_ops->cancel_idc_work(adapter);
2021 }
2022
2023 static inline irqreturn_t
2024 qlcnic_clear_legacy_intr(struct qlcnic_adapter *adapter)
2025 {
2026 return adapter->nic_ops->clear_legacy_intr(adapter);
2027 }
2028
2029 static inline int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state,
2030 u32 rate)
2031 {
2032 return adapter->nic_ops->config_led(adapter, state, rate);
2033 }
2034
2035 static inline void qlcnic_config_ipaddr(struct qlcnic_adapter *adapter,
2036 __be32 ip, int cmd)
2037 {
2038 adapter->nic_ops->config_ipaddr(adapter, ip, cmd);
2039 }
2040
2041 static inline bool qlcnic_check_multi_tx(struct qlcnic_adapter *adapter)
2042 {
2043 return test_bit(__QLCNIC_MULTI_TX_UNIQUE, &adapter->state);
2044 }
2045
2046 static inline void
2047 qlcnic_82xx_enable_tx_intr(struct qlcnic_adapter *adapter,
2048 struct qlcnic_host_tx_ring *tx_ring)
2049 {
2050 if (qlcnic_check_multi_tx(adapter) &&
2051 !adapter->ahw->diag_test)
2052 writel(0x0, tx_ring->crb_intr_mask);
2053 }
2054
2055 static inline void
2056 qlcnic_82xx_disable_tx_intr(struct qlcnic_adapter *adapter,
2057 struct qlcnic_host_tx_ring *tx_ring)
2058 {
2059 if (qlcnic_check_multi_tx(adapter) &&
2060 !adapter->ahw->diag_test)
2061 writel(1, tx_ring->crb_intr_mask);
2062 }
2063
2064 static inline void
2065 qlcnic_83xx_enable_tx_intr(struct qlcnic_adapter *adapter,
2066 struct qlcnic_host_tx_ring *tx_ring)
2067 {
2068 writel(0, tx_ring->crb_intr_mask);
2069 }
2070
2071 static inline void
2072 qlcnic_83xx_disable_tx_intr(struct qlcnic_adapter *adapter,
2073 struct qlcnic_host_tx_ring *tx_ring)
2074 {
2075 writel(1, tx_ring->crb_intr_mask);
2076 }
2077
2078 /* Enable MSI-x and INT-x interrupts */
2079 static inline void
2080 qlcnic_83xx_enable_sds_intr(struct qlcnic_adapter *adapter,
2081 struct qlcnic_host_sds_ring *sds_ring)
2082 {
2083 writel(0, sds_ring->crb_intr_mask);
2084 }
2085
2086 /* Disable MSI-x and INT-x interrupts */
2087 static inline void
2088 qlcnic_83xx_disable_sds_intr(struct qlcnic_adapter *adapter,
2089 struct qlcnic_host_sds_ring *sds_ring)
2090 {
2091 writel(1, sds_ring->crb_intr_mask);
2092 }
2093
2094 static inline void qlcnic_disable_multi_tx(struct qlcnic_adapter *adapter)
2095 {
2096 test_and_clear_bit(__QLCNIC_MULTI_TX_UNIQUE, &adapter->state);
2097 adapter->drv_tx_rings = QLCNIC_SINGLE_RING;
2098 }
2099
2100 /* When operating in a muti tx mode, driver needs to write 0x1
2101 * to src register, instead of 0x0 to disable receiving interrupt.
2102 */
2103 static inline void
2104 qlcnic_82xx_disable_sds_intr(struct qlcnic_adapter *adapter,
2105 struct qlcnic_host_sds_ring *sds_ring)
2106 {
2107 if (qlcnic_check_multi_tx(adapter) &&
2108 !adapter->ahw->diag_test &&
2109 (adapter->flags & QLCNIC_MSIX_ENABLED))
2110 writel(0x1, sds_ring->crb_intr_mask);
2111 else
2112 writel(0, sds_ring->crb_intr_mask);
2113 }
2114
2115 static inline void qlcnic_enable_sds_intr(struct qlcnic_adapter *adapter,
2116 struct qlcnic_host_sds_ring *sds_ring)
2117 {
2118 if (adapter->ahw->hw_ops->enable_sds_intr)
2119 adapter->ahw->hw_ops->enable_sds_intr(adapter, sds_ring);
2120 }
2121
2122 static inline void
2123 qlcnic_disable_sds_intr(struct qlcnic_adapter *adapter,
2124 struct qlcnic_host_sds_ring *sds_ring)
2125 {
2126 if (adapter->ahw->hw_ops->disable_sds_intr)
2127 adapter->ahw->hw_ops->disable_sds_intr(adapter, sds_ring);
2128 }
2129
2130 static inline void qlcnic_enable_tx_intr(struct qlcnic_adapter *adapter,
2131 struct qlcnic_host_tx_ring *tx_ring)
2132 {
2133 if (adapter->ahw->hw_ops->enable_tx_intr)
2134 adapter->ahw->hw_ops->enable_tx_intr(adapter, tx_ring);
2135 }
2136
2137 static inline void qlcnic_disable_tx_intr(struct qlcnic_adapter *adapter,
2138 struct qlcnic_host_tx_ring *tx_ring)
2139 {
2140 if (adapter->ahw->hw_ops->disable_tx_intr)
2141 adapter->ahw->hw_ops->disable_tx_intr(adapter, tx_ring);
2142 }
2143
2144 /* When operating in a muti tx mode, driver needs to write 0x0
2145 * to src register, instead of 0x1 to enable receiving interrupts.
2146 */
2147 static inline void
2148 qlcnic_82xx_enable_sds_intr(struct qlcnic_adapter *adapter,
2149 struct qlcnic_host_sds_ring *sds_ring)
2150 {
2151 if (qlcnic_check_multi_tx(adapter) &&
2152 !adapter->ahw->diag_test &&
2153 (adapter->flags & QLCNIC_MSIX_ENABLED))
2154 writel(0, sds_ring->crb_intr_mask);
2155 else
2156 writel(0x1, sds_ring->crb_intr_mask);
2157
2158 if (!QLCNIC_IS_MSI_FAMILY(adapter))
2159 writel(0xfbff, adapter->tgt_mask_reg);
2160 }
2161
2162 static inline int qlcnic_get_diag_lock(struct qlcnic_adapter *adapter)
2163 {
2164 return test_and_set_bit(__QLCNIC_DIAG_MODE, &adapter->state);
2165 }
2166
2167 static inline void qlcnic_release_diag_lock(struct qlcnic_adapter *adapter)
2168 {
2169 clear_bit(__QLCNIC_DIAG_MODE, &adapter->state);
2170 }
2171
2172 static inline int qlcnic_check_diag_status(struct qlcnic_adapter *adapter)
2173 {
2174 return test_bit(__QLCNIC_DIAG_MODE, &adapter->state);
2175 }
2176
2177 extern const struct ethtool_ops qlcnic_sriov_vf_ethtool_ops;
2178 extern const struct ethtool_ops qlcnic_ethtool_ops;
2179 extern const struct ethtool_ops qlcnic_ethtool_failed_ops;
2180
2181 #define QLCDB(adapter, lvl, _fmt, _args...) do { \
2182 if (NETIF_MSG_##lvl & adapter->ahw->msg_enable) \
2183 printk(KERN_INFO "%s: %s: " _fmt, \
2184 dev_name(&adapter->pdev->dev), \
2185 __func__, ##_args); \
2186 } while (0)
2187
2188 #define PCI_DEVICE_ID_QLOGIC_QLE824X 0x8020
2189 #define PCI_DEVICE_ID_QLOGIC_QLE834X 0x8030
2190 #define PCI_DEVICE_ID_QLOGIC_VF_QLE834X 0x8430
2191 #define PCI_DEVICE_ID_QLOGIC_QLE844X 0x8040
2192 #define PCI_DEVICE_ID_QLOGIC_VF_QLE844X 0x8440
2193
2194 static inline bool qlcnic_82xx_check(struct qlcnic_adapter *adapter)
2195 {
2196 unsigned short device = adapter->pdev->device;
2197 return (device == PCI_DEVICE_ID_QLOGIC_QLE824X) ? true : false;
2198 }
2199
2200 static inline bool qlcnic_84xx_check(struct qlcnic_adapter *adapter)
2201 {
2202 unsigned short device = adapter->pdev->device;
2203
2204 return ((device == PCI_DEVICE_ID_QLOGIC_QLE844X) ||
2205 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X)) ? true : false;
2206 }
2207
2208 static inline bool qlcnic_83xx_check(struct qlcnic_adapter *adapter)
2209 {
2210 unsigned short device = adapter->pdev->device;
2211 bool status;
2212
2213 status = ((device == PCI_DEVICE_ID_QLOGIC_QLE834X) ||
2214 (device == PCI_DEVICE_ID_QLOGIC_QLE844X) ||
2215 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X) ||
2216 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X)) ? true : false;
2217
2218 return status;
2219 }
2220
2221 static inline bool qlcnic_sriov_pf_check(struct qlcnic_adapter *adapter)
2222 {
2223 return (adapter->ahw->op_mode == QLCNIC_SRIOV_PF_FUNC) ? true : false;
2224 }
2225
2226 static inline bool qlcnic_sriov_vf_check(struct qlcnic_adapter *adapter)
2227 {
2228 unsigned short device = adapter->pdev->device;
2229 bool status;
2230
2231 status = ((device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X) ||
2232 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X)) ? true : false;
2233
2234 return status;
2235 }
2236
2237 static inline bool qlcnic_83xx_pf_check(struct qlcnic_adapter *adapter)
2238 {
2239 unsigned short device = adapter->pdev->device;
2240
2241 return (device == PCI_DEVICE_ID_QLOGIC_QLE834X) ? true : false;
2242 }
2243
2244 static inline bool qlcnic_83xx_vf_check(struct qlcnic_adapter *adapter)
2245 {
2246 unsigned short device = adapter->pdev->device;
2247
2248 return (device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X) ? true : false;
2249 }
2250
2251 static inline u32 qlcnic_get_vnic_func_count(struct qlcnic_adapter *adapter)
2252 {
2253 if (qlcnic_84xx_check(adapter))
2254 return QLC_84XX_VNIC_COUNT;
2255 else
2256 return QLC_DEFAULT_VNIC_COUNT;
2257 }
2258 #endif /* __QLCNIC_H_ */
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