2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
5 * See LICENSE.qlcnic for copyright and licensing details.
9 #include "qlcnic_sriov.h"
10 #include <linux/if_vlan.h>
11 #include <linux/ipv6.h>
12 #include <linux/ethtool.h>
13 #include <linux/interrupt.h>
15 #define QLCNIC_MAX_TX_QUEUES 1
16 #define RSS_HASHTYPE_IP_TCP 0x3
17 #define QLC_83XX_FW_MBX_CMD 0
19 static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl
[] = {
20 {QLCNIC_CMD_CONFIGURE_IP_ADDR
, 6, 1},
21 {QLCNIC_CMD_CONFIG_INTRPT
, 18, 34},
22 {QLCNIC_CMD_CREATE_RX_CTX
, 136, 27},
23 {QLCNIC_CMD_DESTROY_RX_CTX
, 2, 1},
24 {QLCNIC_CMD_CREATE_TX_CTX
, 54, 18},
25 {QLCNIC_CMD_DESTROY_TX_CTX
, 2, 1},
26 {QLCNIC_CMD_CONFIGURE_MAC_LEARNING
, 2, 1},
27 {QLCNIC_CMD_INTRPT_TEST
, 22, 12},
28 {QLCNIC_CMD_SET_MTU
, 3, 1},
29 {QLCNIC_CMD_READ_PHY
, 4, 2},
30 {QLCNIC_CMD_WRITE_PHY
, 5, 1},
31 {QLCNIC_CMD_READ_HW_REG
, 4, 1},
32 {QLCNIC_CMD_GET_FLOW_CTL
, 4, 2},
33 {QLCNIC_CMD_SET_FLOW_CTL
, 4, 1},
34 {QLCNIC_CMD_READ_MAX_MTU
, 4, 2},
35 {QLCNIC_CMD_READ_MAX_LRO
, 4, 2},
36 {QLCNIC_CMD_MAC_ADDRESS
, 4, 3},
37 {QLCNIC_CMD_GET_PCI_INFO
, 1, 66},
38 {QLCNIC_CMD_GET_NIC_INFO
, 2, 19},
39 {QLCNIC_CMD_SET_NIC_INFO
, 32, 1},
40 {QLCNIC_CMD_GET_ESWITCH_CAPABILITY
, 4, 3},
41 {QLCNIC_CMD_TOGGLE_ESWITCH
, 4, 1},
42 {QLCNIC_CMD_GET_ESWITCH_STATUS
, 4, 3},
43 {QLCNIC_CMD_SET_PORTMIRRORING
, 4, 1},
44 {QLCNIC_CMD_CONFIGURE_ESWITCH
, 4, 1},
45 {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG
, 4, 3},
46 {QLCNIC_CMD_GET_ESWITCH_STATS
, 5, 1},
47 {QLCNIC_CMD_CONFIG_PORT
, 4, 1},
48 {QLCNIC_CMD_TEMP_SIZE
, 1, 4},
49 {QLCNIC_CMD_GET_TEMP_HDR
, 5, 5},
50 {QLCNIC_CMD_GET_LINK_EVENT
, 2, 1},
51 {QLCNIC_CMD_CONFIG_MAC_VLAN
, 4, 3},
52 {QLCNIC_CMD_CONFIG_INTR_COAL
, 6, 1},
53 {QLCNIC_CMD_CONFIGURE_RSS
, 14, 1},
54 {QLCNIC_CMD_CONFIGURE_LED
, 2, 1},
55 {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE
, 2, 1},
56 {QLCNIC_CMD_CONFIGURE_HW_LRO
, 2, 1},
57 {QLCNIC_CMD_GET_STATISTICS
, 2, 80},
58 {QLCNIC_CMD_SET_PORT_CONFIG
, 2, 1},
59 {QLCNIC_CMD_GET_PORT_CONFIG
, 2, 2},
60 {QLCNIC_CMD_GET_LINK_STATUS
, 2, 4},
61 {QLCNIC_CMD_IDC_ACK
, 5, 1},
62 {QLCNIC_CMD_INIT_NIC_FUNC
, 2, 1},
63 {QLCNIC_CMD_STOP_NIC_FUNC
, 2, 1},
64 {QLCNIC_CMD_SET_LED_CONFIG
, 5, 1},
65 {QLCNIC_CMD_GET_LED_CONFIG
, 1, 5},
66 {QLCNIC_CMD_83XX_SET_DRV_VER
, 4, 1},
67 {QLCNIC_CMD_ADD_RCV_RINGS
, 130, 26},
68 {QLCNIC_CMD_CONFIG_VPORT
, 4, 4},
69 {QLCNIC_CMD_BC_EVENT_SETUP
, 2, 1},
72 const u32 qlcnic_83xx_ext_reg_tbl
[] = {
73 0x38CC, /* Global Reset */
74 0x38F0, /* Wildcard */
75 0x38FC, /* Informant */
76 0x3038, /* Host MBX ctrl */
77 0x303C, /* FW MBX ctrl */
78 0x355C, /* BOOT LOADER ADDRESS REG */
79 0x3560, /* BOOT LOADER SIZE REG */
80 0x3564, /* FW IMAGE ADDR REG */
81 0x1000, /* MBX intr enable */
82 0x1200, /* Default Intr mask */
83 0x1204, /* Default Interrupt ID */
84 0x3780, /* QLC_83XX_IDC_MAJ_VERSION */
85 0x3784, /* QLC_83XX_IDC_DEV_STATE */
86 0x3788, /* QLC_83XX_IDC_DRV_PRESENCE */
87 0x378C, /* QLC_83XX_IDC_DRV_ACK */
88 0x3790, /* QLC_83XX_IDC_CTRL */
89 0x3794, /* QLC_83XX_IDC_DRV_AUDIT */
90 0x3798, /* QLC_83XX_IDC_MIN_VERSION */
91 0x379C, /* QLC_83XX_RECOVER_DRV_LOCK */
92 0x37A0, /* QLC_83XX_IDC_PF_0 */
93 0x37A4, /* QLC_83XX_IDC_PF_1 */
94 0x37A8, /* QLC_83XX_IDC_PF_2 */
95 0x37AC, /* QLC_83XX_IDC_PF_3 */
96 0x37B0, /* QLC_83XX_IDC_PF_4 */
97 0x37B4, /* QLC_83XX_IDC_PF_5 */
98 0x37B8, /* QLC_83XX_IDC_PF_6 */
99 0x37BC, /* QLC_83XX_IDC_PF_7 */
100 0x37C0, /* QLC_83XX_IDC_PF_8 */
101 0x37C4, /* QLC_83XX_IDC_PF_9 */
102 0x37C8, /* QLC_83XX_IDC_PF_10 */
103 0x37CC, /* QLC_83XX_IDC_PF_11 */
104 0x37D0, /* QLC_83XX_IDC_PF_12 */
105 0x37D4, /* QLC_83XX_IDC_PF_13 */
106 0x37D8, /* QLC_83XX_IDC_PF_14 */
107 0x37DC, /* QLC_83XX_IDC_PF_15 */
108 0x37E0, /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */
109 0x37E4, /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */
110 0x37F0, /* QLC_83XX_DRV_OP_MODE */
111 0x37F4, /* QLC_83XX_VNIC_STATE */
112 0x3868, /* QLC_83XX_DRV_LOCK */
113 0x386C, /* QLC_83XX_DRV_UNLOCK */
114 0x3504, /* QLC_83XX_DRV_LOCK_ID */
115 0x34A4, /* QLC_83XX_ASIC_TEMP */
118 const u32 qlcnic_83xx_reg_tbl
[] = {
119 0x34A8, /* PEG_HALT_STAT1 */
120 0x34AC, /* PEG_HALT_STAT2 */
121 0x34B0, /* FW_HEARTBEAT */
122 0x3500, /* FLASH LOCK_ID */
123 0x3528, /* FW_CAPABILITIES */
124 0x3538, /* Driver active, DRV_REG0 */
125 0x3540, /* Device state, DRV_REG1 */
126 0x3544, /* Driver state, DRV_REG2 */
127 0x3548, /* Driver scratch, DRV_REG3 */
128 0x354C, /* Device partiton info, DRV_REG4 */
129 0x3524, /* Driver IDC ver, DRV_REG5 */
130 0x3550, /* FW_VER_MAJOR */
131 0x3554, /* FW_VER_MINOR */
132 0x3558, /* FW_VER_SUB */
133 0x359C, /* NPAR STATE */
134 0x35FC, /* FW_IMG_VALID */
135 0x3650, /* CMD_PEG_STATE */
136 0x373C, /* RCV_PEG_STATE */
137 0x37B4, /* ASIC TEMP */
139 0x3570, /* DRV OP MODE */
140 0x3850, /* FLASH LOCK */
141 0x3854, /* FLASH UNLOCK */
144 static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops
= {
145 .read_crb
= qlcnic_83xx_read_crb
,
146 .write_crb
= qlcnic_83xx_write_crb
,
147 .read_reg
= qlcnic_83xx_rd_reg_indirect
,
148 .write_reg
= qlcnic_83xx_wrt_reg_indirect
,
149 .get_mac_address
= qlcnic_83xx_get_mac_address
,
150 .setup_intr
= qlcnic_83xx_setup_intr
,
151 .alloc_mbx_args
= qlcnic_83xx_alloc_mbx_args
,
152 .mbx_cmd
= qlcnic_83xx_issue_cmd
,
153 .get_func_no
= qlcnic_83xx_get_func_no
,
154 .api_lock
= qlcnic_83xx_cam_lock
,
155 .api_unlock
= qlcnic_83xx_cam_unlock
,
156 .add_sysfs
= qlcnic_83xx_add_sysfs
,
157 .remove_sysfs
= qlcnic_83xx_remove_sysfs
,
158 .process_lb_rcv_ring_diag
= qlcnic_83xx_process_rcv_ring_diag
,
159 .create_rx_ctx
= qlcnic_83xx_create_rx_ctx
,
160 .create_tx_ctx
= qlcnic_83xx_create_tx_ctx
,
161 .del_rx_ctx
= qlcnic_83xx_del_rx_ctx
,
162 .del_tx_ctx
= qlcnic_83xx_del_tx_ctx
,
163 .setup_link_event
= qlcnic_83xx_setup_link_event
,
164 .get_nic_info
= qlcnic_83xx_get_nic_info
,
165 .get_pci_info
= qlcnic_83xx_get_pci_info
,
166 .set_nic_info
= qlcnic_83xx_set_nic_info
,
167 .change_macvlan
= qlcnic_83xx_sre_macaddr_change
,
168 .napi_enable
= qlcnic_83xx_napi_enable
,
169 .napi_disable
= qlcnic_83xx_napi_disable
,
170 .config_intr_coal
= qlcnic_83xx_config_intr_coal
,
171 .config_rss
= qlcnic_83xx_config_rss
,
172 .config_hw_lro
= qlcnic_83xx_config_hw_lro
,
173 .config_promisc_mode
= qlcnic_83xx_nic_set_promisc
,
174 .change_l2_filter
= qlcnic_83xx_change_l2_filter
,
175 .get_board_info
= qlcnic_83xx_get_port_info
,
176 .set_mac_filter_count
= qlcnic_83xx_set_mac_filter_count
,
177 .free_mac_list
= qlcnic_82xx_free_mac_list
,
180 static struct qlcnic_nic_template qlcnic_83xx_ops
= {
181 .config_bridged_mode
= qlcnic_config_bridged_mode
,
182 .config_led
= qlcnic_config_led
,
183 .request_reset
= qlcnic_83xx_idc_request_reset
,
184 .cancel_idc_work
= qlcnic_83xx_idc_exit
,
185 .napi_add
= qlcnic_83xx_napi_add
,
186 .napi_del
= qlcnic_83xx_napi_del
,
187 .config_ipaddr
= qlcnic_83xx_config_ipaddr
,
188 .clear_legacy_intr
= qlcnic_83xx_clear_legacy_intr
,
189 .shutdown
= qlcnic_83xx_shutdown
,
190 .resume
= qlcnic_83xx_resume
,
193 void qlcnic_83xx_register_map(struct qlcnic_hardware_context
*ahw
)
195 ahw
->hw_ops
= &qlcnic_83xx_hw_ops
;
196 ahw
->reg_tbl
= (u32
*)qlcnic_83xx_reg_tbl
;
197 ahw
->ext_reg_tbl
= (u32
*)qlcnic_83xx_ext_reg_tbl
;
200 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter
*adapter
)
202 u32 fw_major
, fw_minor
, fw_build
;
203 struct pci_dev
*pdev
= adapter
->pdev
;
205 fw_major
= QLC_SHARED_REG_RD32(adapter
, QLCNIC_FW_VERSION_MAJOR
);
206 fw_minor
= QLC_SHARED_REG_RD32(adapter
, QLCNIC_FW_VERSION_MINOR
);
207 fw_build
= QLC_SHARED_REG_RD32(adapter
, QLCNIC_FW_VERSION_SUB
);
208 adapter
->fw_version
= QLCNIC_VERSION_CODE(fw_major
, fw_minor
, fw_build
);
210 dev_info(&pdev
->dev
, "Driver v%s, firmware version %d.%d.%d\n",
211 QLCNIC_LINUX_VERSIONID
, fw_major
, fw_minor
, fw_build
);
213 return adapter
->fw_version
;
216 static int __qlcnic_set_win_base(struct qlcnic_adapter
*adapter
, u32 addr
)
221 base
= adapter
->ahw
->pci_base0
+
222 QLC_83XX_CRB_WIN_FUNC(adapter
->ahw
->pci_func
);
231 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter
*adapter
, ulong addr
)
234 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
236 ret
= __qlcnic_set_win_base(adapter
, (u32
) addr
);
238 return QLCRDX(ahw
, QLCNIC_WILDCARD
);
240 dev_err(&adapter
->pdev
->dev
,
241 "%s failed, addr = 0x%x\n", __func__
, (int)addr
);
246 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter
*adapter
, ulong addr
,
250 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
252 err
= __qlcnic_set_win_base(adapter
, (u32
) addr
);
254 QLCWRX(ahw
, QLCNIC_WILDCARD
, data
);
257 dev_err(&adapter
->pdev
->dev
,
258 "%s failed, addr = 0x%x data = 0x%x\n",
259 __func__
, (int)addr
, data
);
264 int qlcnic_83xx_setup_intr(struct qlcnic_adapter
*adapter
, u8 num_intr
)
266 int err
, i
, num_msix
;
267 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
270 num_intr
= QLCNIC_DEF_NUM_STS_DESC_RINGS
;
271 num_msix
= rounddown_pow_of_two(min_t(int, num_online_cpus(),
273 /* account for AEN interrupt MSI-X based interrupts */
276 if (!(adapter
->flags
& QLCNIC_TX_INTR_SHARED
))
277 num_msix
+= adapter
->max_drv_tx_rings
;
279 err
= qlcnic_enable_msix(adapter
, num_msix
);
282 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
283 num_msix
= adapter
->ahw
->num_msix
;
285 if (qlcnic_sriov_vf_check(adapter
))
289 /* setup interrupt mapping table for fw */
290 ahw
->intr_tbl
= vzalloc(num_msix
*
291 sizeof(struct qlcnic_intrpt_config
));
294 if (!(adapter
->flags
& QLCNIC_MSIX_ENABLED
)) {
295 /* MSI-X enablement failed, use legacy interrupt */
296 adapter
->tgt_status_reg
= ahw
->pci_base0
+ QLC_83XX_INTX_PTR
;
297 adapter
->tgt_mask_reg
= ahw
->pci_base0
+ QLC_83XX_INTX_MASK
;
298 adapter
->isr_int_vec
= ahw
->pci_base0
+ QLC_83XX_INTX_TRGR
;
299 adapter
->msix_entries
[0].vector
= adapter
->pdev
->irq
;
300 dev_info(&adapter
->pdev
->dev
, "using legacy interrupt\n");
303 for (i
= 0; i
< num_msix
; i
++) {
304 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
305 ahw
->intr_tbl
[i
].type
= QLCNIC_INTRPT_MSIX
;
307 ahw
->intr_tbl
[i
].type
= QLCNIC_INTRPT_INTX
;
308 ahw
->intr_tbl
[i
].id
= i
;
309 ahw
->intr_tbl
[i
].src
= 0;
314 inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter
*adapter
)
316 writel(0, adapter
->tgt_mask_reg
);
319 inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter
*adapter
)
321 writel(1, adapter
->tgt_mask_reg
);
324 /* Enable MSI-x and INT-x interrupts */
325 void qlcnic_83xx_enable_intr(struct qlcnic_adapter
*adapter
,
326 struct qlcnic_host_sds_ring
*sds_ring
)
328 writel(0, sds_ring
->crb_intr_mask
);
331 /* Disable MSI-x and INT-x interrupts */
332 void qlcnic_83xx_disable_intr(struct qlcnic_adapter
*adapter
,
333 struct qlcnic_host_sds_ring
*sds_ring
)
335 writel(1, sds_ring
->crb_intr_mask
);
338 inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
343 /* Mailbox in MSI-x mode and Legacy Interrupt share the same
344 * source register. We could be here before contexts are created
345 * and sds_ring->crb_intr_mask has not been initialized, calculate
346 * BAR offset for Interrupt Source Register
348 mask
= QLCRDX(adapter
->ahw
, QLCNIC_DEF_INT_MASK
);
349 writel(0, adapter
->ahw
->pci_base0
+ mask
);
352 void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter
*adapter
)
356 mask
= QLCRDX(adapter
->ahw
, QLCNIC_DEF_INT_MASK
);
357 writel(1, adapter
->ahw
->pci_base0
+ mask
);
358 QLCWRX(adapter
->ahw
, QLCNIC_MBX_INTR_ENBL
, 0);
361 static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter
*adapter
,
362 struct qlcnic_cmd_args
*cmd
)
365 for (i
= 0; i
< cmd
->rsp
.num
; i
++)
366 cmd
->rsp
.arg
[i
] = readl(QLCNIC_MBX_FW(adapter
->ahw
, i
));
369 irqreturn_t
qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter
*adapter
)
372 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
375 intr_val
= readl(adapter
->tgt_status_reg
);
377 if (!QLC_83XX_VALID_INTX_BIT31(intr_val
))
380 if (QLC_83XX_INTX_FUNC(intr_val
) != adapter
->ahw
->pci_func
) {
381 adapter
->stats
.spurious_intr
++;
384 /* The barrier is required to ensure writes to the registers */
387 /* clear the interrupt trigger control register */
388 writel(0, adapter
->isr_int_vec
);
389 intr_val
= readl(adapter
->isr_int_vec
);
391 intr_val
= readl(adapter
->tgt_status_reg
);
392 if (QLC_83XX_INTX_FUNC(intr_val
) != ahw
->pci_func
)
395 } while (QLC_83XX_VALID_INTX_BIT30(intr_val
) &&
396 (retries
< QLC_83XX_LEGACY_INTX_MAX_RETRY
));
401 static inline void qlcnic_83xx_notify_mbx_response(struct qlcnic_mailbox
*mbx
)
403 atomic_set(&mbx
->rsp_status
, QLC_83XX_MBX_RESPONSE_ARRIVED
);
404 complete(&mbx
->completion
);
407 static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter
*adapter
)
412 spin_lock_irqsave(&adapter
->ahw
->mbx_lock
, flags
);
414 resp
= QLCRDX(adapter
->ahw
, QLCNIC_FW_MBX_CTRL
);
415 if (!(resp
& QLCNIC_SET_OWNER
))
418 event
= readl(QLCNIC_MBX_FW(adapter
->ahw
, 0));
419 if (event
& QLCNIC_MBX_ASYNC_EVENT
)
420 __qlcnic_83xx_process_aen(adapter
);
423 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter
);
424 spin_unlock_irqrestore(&adapter
->ahw
->mbx_lock
, flags
);
427 irqreturn_t
qlcnic_83xx_intr(int irq
, void *data
)
429 struct qlcnic_adapter
*adapter
= data
;
430 struct qlcnic_host_sds_ring
*sds_ring
;
431 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
433 if (qlcnic_83xx_clear_legacy_intr(adapter
) == IRQ_NONE
)
436 qlcnic_83xx_poll_process_aen(adapter
);
438 if (ahw
->diag_test
== QLCNIC_INTERRUPT_TEST
) {
440 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter
);
444 if (!test_bit(__QLCNIC_DEV_UP
, &adapter
->state
)) {
445 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter
);
447 sds_ring
= &adapter
->recv_ctx
->sds_rings
[0];
448 napi_schedule(&sds_ring
->napi
);
454 irqreturn_t
qlcnic_83xx_tmp_intr(int irq
, void *data
)
456 struct qlcnic_host_sds_ring
*sds_ring
= data
;
457 struct qlcnic_adapter
*adapter
= sds_ring
->adapter
;
459 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
462 if (adapter
->nic_ops
->clear_legacy_intr(adapter
) == IRQ_NONE
)
466 adapter
->ahw
->diag_cnt
++;
467 qlcnic_83xx_enable_intr(adapter
, sds_ring
);
472 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter
*adapter
)
476 if (!(adapter
->flags
& QLCNIC_MSIX_ENABLED
))
477 qlcnic_83xx_set_legacy_intr_mask(adapter
);
479 qlcnic_83xx_disable_mbx_intr(adapter
);
481 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
482 num_msix
= adapter
->ahw
->num_msix
- 1;
487 synchronize_irq(adapter
->msix_entries
[num_msix
].vector
);
488 free_irq(adapter
->msix_entries
[num_msix
].vector
, adapter
);
491 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter
*adapter
)
493 irq_handler_t handler
;
496 unsigned long flags
= 0;
498 if (!(adapter
->flags
& QLCNIC_MSI_ENABLED
) &&
499 !(adapter
->flags
& QLCNIC_MSIX_ENABLED
))
500 flags
|= IRQF_SHARED
;
502 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
) {
503 handler
= qlcnic_83xx_handle_aen
;
504 val
= adapter
->msix_entries
[adapter
->ahw
->num_msix
- 1].vector
;
505 err
= request_irq(val
, handler
, flags
, "qlcnic-MB", adapter
);
507 dev_err(&adapter
->pdev
->dev
,
508 "failed to register MBX interrupt\n");
512 handler
= qlcnic_83xx_intr
;
513 val
= adapter
->msix_entries
[0].vector
;
514 err
= request_irq(val
, handler
, flags
, "qlcnic", adapter
);
516 dev_err(&adapter
->pdev
->dev
,
517 "failed to register INTx interrupt\n");
520 qlcnic_83xx_clear_legacy_intr_mask(adapter
);
523 /* Enable mailbox interrupt */
524 qlcnic_83xx_enable_mbx_interrupt(adapter
);
529 void qlcnic_83xx_get_func_no(struct qlcnic_adapter
*adapter
)
531 u32 val
= QLCRDX(adapter
->ahw
, QLCNIC_INFORMANT
);
532 adapter
->ahw
->pci_func
= (val
>> 24) & 0xff;
535 int qlcnic_83xx_cam_lock(struct qlcnic_adapter
*adapter
)
540 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
542 addr
= ahw
->pci_base0
+ QLC_83XX_SEM_LOCK_FUNC(ahw
->pci_func
);
546 /* write the function number to register */
547 QLC_SHARED_REG_WR32(adapter
, QLCNIC_FLASH_LOCK_OWNER
,
551 usleep_range(1000, 2000);
552 } while (++limit
<= QLCNIC_PCIE_SEM_TIMEOUT
);
557 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter
*adapter
)
561 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
563 addr
= ahw
->pci_base0
+ QLC_83XX_SEM_UNLOCK_FUNC(ahw
->pci_func
);
567 void qlcnic_83xx_read_crb(struct qlcnic_adapter
*adapter
, char *buf
,
568 loff_t offset
, size_t size
)
573 if (qlcnic_api_lock(adapter
)) {
574 dev_err(&adapter
->pdev
->dev
,
575 "%s: failed to acquire lock. addr offset 0x%x\n",
576 __func__
, (u32
)offset
);
580 ret
= qlcnic_83xx_rd_reg_indirect(adapter
, (u32
) offset
);
581 qlcnic_api_unlock(adapter
);
584 dev_err(&adapter
->pdev
->dev
,
585 "%s: failed. addr offset 0x%x\n",
586 __func__
, (u32
)offset
);
590 memcpy(buf
, &data
, size
);
593 void qlcnic_83xx_write_crb(struct qlcnic_adapter
*adapter
, char *buf
,
594 loff_t offset
, size_t size
)
598 memcpy(&data
, buf
, size
);
599 qlcnic_83xx_wrt_reg_indirect(adapter
, (u32
) offset
, data
);
602 int qlcnic_83xx_get_port_info(struct qlcnic_adapter
*adapter
)
606 status
= qlcnic_83xx_get_port_config(adapter
);
608 dev_err(&adapter
->pdev
->dev
,
609 "Get Port Info failed\n");
611 if (QLC_83XX_SFP_10G_CAPABLE(adapter
->ahw
->port_config
))
612 adapter
->ahw
->port_type
= QLCNIC_XGBE
;
614 adapter
->ahw
->port_type
= QLCNIC_GBE
;
616 if (QLC_83XX_AUTONEG(adapter
->ahw
->port_config
))
617 adapter
->ahw
->link_autoneg
= AUTONEG_ENABLE
;
622 void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter
*adapter
)
624 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
625 u16 act_pci_fn
= ahw
->act_pci_func
;
628 ahw
->max_mc_count
= QLC_83XX_MAX_MC_COUNT
;
630 count
= (QLC_83XX_MAX_UC_COUNT
- QLC_83XX_MAX_MC_COUNT
) /
633 count
= (QLC_83XX_LB_MAX_FILTERS
- QLC_83XX_MAX_MC_COUNT
) /
635 ahw
->max_uc_count
= count
;
638 void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter
*adapter
)
642 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
643 val
= BIT_2
| ((adapter
->ahw
->num_msix
- 1) << 8);
647 QLCWRX(adapter
->ahw
, QLCNIC_MBX_INTR_ENBL
, val
);
648 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter
);
651 void qlcnic_83xx_check_vf(struct qlcnic_adapter
*adapter
,
652 const struct pci_device_id
*ent
)
654 u32 op_mode
, priv_level
;
655 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
657 ahw
->fw_hal_version
= 2;
658 qlcnic_get_func_no(adapter
);
660 if (qlcnic_sriov_vf_check(adapter
)) {
661 qlcnic_sriov_vf_set_ops(adapter
);
665 /* Determine function privilege level */
666 op_mode
= QLCRDX(adapter
->ahw
, QLC_83XX_DRV_OP_MODE
);
667 if (op_mode
== QLC_83XX_DEFAULT_OPMODE
)
668 priv_level
= QLCNIC_MGMT_FUNC
;
670 priv_level
= QLC_83XX_GET_FUNC_PRIVILEGE(op_mode
,
673 if (priv_level
== QLCNIC_NON_PRIV_FUNC
) {
674 ahw
->op_mode
= QLCNIC_NON_PRIV_FUNC
;
675 dev_info(&adapter
->pdev
->dev
,
676 "HAL Version: %d Non Privileged function\n",
677 ahw
->fw_hal_version
);
678 adapter
->nic_ops
= &qlcnic_vf_ops
;
680 if (pci_find_ext_capability(adapter
->pdev
,
681 PCI_EXT_CAP_ID_SRIOV
))
682 set_bit(__QLCNIC_SRIOV_CAPABLE
, &adapter
->state
);
683 adapter
->nic_ops
= &qlcnic_83xx_ops
;
687 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter
*adapter
,
689 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter
*adapter
,
692 static void qlcnic_dump_mbx(struct qlcnic_adapter
*adapter
,
693 struct qlcnic_cmd_args
*cmd
)
697 dev_info(&adapter
->pdev
->dev
,
698 "Host MBX regs(%d)\n", cmd
->req
.num
);
699 for (i
= 0; i
< cmd
->req
.num
; i
++) {
702 pr_info("%08x ", cmd
->req
.arg
[i
]);
705 dev_info(&adapter
->pdev
->dev
,
706 "FW MBX regs(%d)\n", cmd
->rsp
.num
);
707 for (i
= 0; i
< cmd
->rsp
.num
; i
++) {
710 pr_info("%08x ", cmd
->rsp
.arg
[i
]);
715 /* Mailbox response for mac rcode */
716 u32
qlcnic_83xx_mac_rcode(struct qlcnic_adapter
*adapter
)
721 fw_data
= readl(QLCNIC_MBX_FW(adapter
->ahw
, 2));
722 mac_cmd_rcode
= (u8
)fw_data
;
723 if (mac_cmd_rcode
== QLC_83XX_NO_NIC_RESOURCE
||
724 mac_cmd_rcode
== QLC_83XX_MAC_PRESENT
||
725 mac_cmd_rcode
== QLC_83XX_MAC_ABSENT
)
726 return QLCNIC_RCODE_SUCCESS
;
730 u32
qlcnic_83xx_mbx_poll(struct qlcnic_adapter
*adapter
, u32
*wait_time
)
733 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
734 /* wait for mailbox completion */
736 data
= QLCRDX(ahw
, QLCNIC_FW_MBX_CTRL
);
737 if (++(*wait_time
) > QLCNIC_MBX_TIMEOUT
) {
738 data
= QLCNIC_RCODE_TIMEOUT
;
746 int qlcnic_83xx_issue_cmd(struct qlcnic_adapter
*adapter
,
747 struct qlcnic_cmd_args
*cmd
)
753 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
754 u32 rsp
, mbx_val
, fw_data
, rsp_num
, mbx_cmd
, wait_time
= 0;
756 opcode
= LSW(cmd
->req
.arg
[0]);
757 if (!test_bit(QLC_83XX_MBX_READY
, &adapter
->ahw
->idc
.status
)) {
758 dev_info(&adapter
->pdev
->dev
,
759 "Mailbox cmd attempted, 0x%x\n", opcode
);
760 dev_info(&adapter
->pdev
->dev
, "Mailbox detached\n");
764 spin_lock_irqsave(&adapter
->ahw
->mbx_lock
, flags
);
765 mbx_val
= QLCRDX(ahw
, QLCNIC_HOST_MBX_CTRL
);
769 "Mailbox cmd attempted, 0x%x\n", opcode
);
771 "Mailbox not available, 0x%x, collect FW dump\n",
773 cmd
->rsp
.arg
[0] = QLCNIC_RCODE_TIMEOUT
;
774 spin_unlock_irqrestore(&adapter
->ahw
->mbx_lock
, flags
);
775 return cmd
->rsp
.arg
[0];
778 /* Fill in mailbox registers */
779 mbx_cmd
= cmd
->req
.arg
[0];
780 writel(mbx_cmd
, QLCNIC_MBX_HOST(ahw
, 0));
781 for (i
= 1; i
< cmd
->req
.num
; i
++)
782 writel(cmd
->req
.arg
[i
], QLCNIC_MBX_HOST(ahw
, i
));
784 /* Signal FW about the impending command */
785 QLCWRX(ahw
, QLCNIC_HOST_MBX_CTRL
, QLCNIC_SET_OWNER
);
787 rsp
= qlcnic_83xx_mbx_poll(adapter
, &wait_time
);
788 if (rsp
!= QLCNIC_RCODE_TIMEOUT
) {
789 /* Get the FW response data */
790 fw_data
= readl(QLCNIC_MBX_FW(ahw
, 0));
791 if (fw_data
& QLCNIC_MBX_ASYNC_EVENT
) {
792 __qlcnic_83xx_process_aen(adapter
);
795 mbx_err_code
= QLCNIC_MBX_STATUS(fw_data
);
796 rsp_num
= QLCNIC_MBX_NUM_REGS(fw_data
);
797 opcode
= QLCNIC_MBX_RSP(fw_data
);
798 qlcnic_83xx_get_mbx_data(adapter
, cmd
);
800 switch (mbx_err_code
) {
801 case QLCNIC_MBX_RSP_OK
:
802 case QLCNIC_MBX_PORT_RSP_OK
:
803 rsp
= QLCNIC_RCODE_SUCCESS
;
806 if (opcode
== QLCNIC_CMD_CONFIG_MAC_VLAN
) {
807 rsp
= qlcnic_83xx_mac_rcode(adapter
);
811 dev_err(&adapter
->pdev
->dev
,
812 "MBX command 0x%x failed with err:0x%x\n",
813 opcode
, mbx_err_code
);
815 qlcnic_dump_mbx(adapter
, cmd
);
821 dev_err(&adapter
->pdev
->dev
, "MBX command 0x%x timed out\n",
822 QLCNIC_MBX_RSP(mbx_cmd
));
823 rsp
= QLCNIC_RCODE_TIMEOUT
;
825 /* clear fw mbx control register */
826 QLCWRX(ahw
, QLCNIC_FW_MBX_CTRL
, QLCNIC_CLR_OWNER
);
827 spin_unlock_irqrestore(&adapter
->ahw
->mbx_lock
, flags
);
831 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args
*mbx
,
832 struct qlcnic_adapter
*adapter
, u32 type
)
836 const struct qlcnic_mailbox_metadata
*mbx_tbl
;
838 memset(mbx
, 0, sizeof(struct qlcnic_cmd_args
));
839 mbx_tbl
= qlcnic_83xx_mbx_tbl
;
840 size
= ARRAY_SIZE(qlcnic_83xx_mbx_tbl
);
841 for (i
= 0; i
< size
; i
++) {
842 if (type
== mbx_tbl
[i
].cmd
) {
843 mbx
->op_type
= QLC_83XX_FW_MBX_CMD
;
844 mbx
->req
.num
= mbx_tbl
[i
].in_args
;
845 mbx
->rsp
.num
= mbx_tbl
[i
].out_args
;
846 mbx
->req
.arg
= kcalloc(mbx
->req
.num
, sizeof(u32
),
850 mbx
->rsp
.arg
= kcalloc(mbx
->rsp
.num
, sizeof(u32
),
857 memset(mbx
->req
.arg
, 0, sizeof(u32
) * mbx
->req
.num
);
858 memset(mbx
->rsp
.arg
, 0, sizeof(u32
) * mbx
->rsp
.num
);
859 temp
= adapter
->ahw
->fw_hal_version
<< 29;
860 mbx
->req
.arg
[0] = (type
| (mbx
->req
.num
<< 16) | temp
);
867 void qlcnic_83xx_idc_aen_work(struct work_struct
*work
)
869 struct qlcnic_adapter
*adapter
;
870 struct qlcnic_cmd_args cmd
;
873 adapter
= container_of(work
, struct qlcnic_adapter
, idc_aen_work
.work
);
874 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_IDC_ACK
);
878 for (i
= 1; i
< QLC_83XX_MBX_AEN_CNT
; i
++)
879 cmd
.req
.arg
[i
] = adapter
->ahw
->mbox_aen
[i
];
881 err
= qlcnic_issue_cmd(adapter
, &cmd
);
883 dev_info(&adapter
->pdev
->dev
,
884 "%s: Mailbox IDC ACK failed.\n", __func__
);
885 qlcnic_free_mbx_args(&cmd
);
888 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter
*adapter
,
891 dev_dbg(&adapter
->pdev
->dev
, "Completion AEN:0x%x.\n",
892 QLCNIC_MBX_RSP(data
[0]));
893 clear_bit(QLC_83XX_IDC_COMP_AEN
, &adapter
->ahw
->idc
.status
);
897 void __qlcnic_83xx_process_aen(struct qlcnic_adapter
*adapter
)
899 u32 event
[QLC_83XX_MBX_AEN_CNT
];
901 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
903 for (i
= 0; i
< QLC_83XX_MBX_AEN_CNT
; i
++)
904 event
[i
] = readl(QLCNIC_MBX_FW(ahw
, i
));
906 switch (QLCNIC_MBX_RSP(event
[0])) {
908 case QLCNIC_MBX_LINK_EVENT
:
909 qlcnic_83xx_handle_link_aen(adapter
, event
);
911 case QLCNIC_MBX_COMP_EVENT
:
912 qlcnic_83xx_handle_idc_comp_aen(adapter
, event
);
914 case QLCNIC_MBX_REQUEST_EVENT
:
915 for (i
= 0; i
< QLC_83XX_MBX_AEN_CNT
; i
++)
916 adapter
->ahw
->mbox_aen
[i
] = QLCNIC_MBX_RSP(event
[i
]);
917 queue_delayed_work(adapter
->qlcnic_wq
,
918 &adapter
->idc_aen_work
, 0);
920 case QLCNIC_MBX_TIME_EXTEND_EVENT
:
922 case QLCNIC_MBX_BC_EVENT
:
923 qlcnic_sriov_handle_bc_event(adapter
, event
[1]);
925 case QLCNIC_MBX_SFP_INSERT_EVENT
:
926 dev_info(&adapter
->pdev
->dev
, "SFP+ Insert AEN:0x%x.\n",
927 QLCNIC_MBX_RSP(event
[0]));
929 case QLCNIC_MBX_SFP_REMOVE_EVENT
:
930 dev_info(&adapter
->pdev
->dev
, "SFP Removed AEN:0x%x.\n",
931 QLCNIC_MBX_RSP(event
[0]));
934 dev_dbg(&adapter
->pdev
->dev
, "Unsupported AEN:0x%x.\n",
935 QLCNIC_MBX_RSP(event
[0]));
939 QLCWRX(ahw
, QLCNIC_FW_MBX_CTRL
, QLCNIC_CLR_OWNER
);
942 static void qlcnic_83xx_process_aen(struct qlcnic_adapter
*adapter
)
944 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
948 spin_lock_irqsave(&ahw
->mbx_lock
, flags
);
950 resp
= QLCRDX(ahw
, QLCNIC_FW_MBX_CTRL
);
951 if (resp
& QLCNIC_SET_OWNER
) {
952 event
= readl(QLCNIC_MBX_FW(ahw
, 0));
953 if (event
& QLCNIC_MBX_ASYNC_EVENT
)
954 __qlcnic_83xx_process_aen(adapter
);
957 spin_unlock_irqrestore(&ahw
->mbx_lock
, flags
);
960 static void qlcnic_83xx_mbx_poll_work(struct work_struct
*work
)
962 struct qlcnic_adapter
*adapter
;
964 adapter
= container_of(work
, struct qlcnic_adapter
, mbx_poll_work
.work
);
966 if (!test_bit(__QLCNIC_MBX_POLL_ENABLE
, &adapter
->state
))
969 qlcnic_83xx_process_aen(adapter
);
970 queue_delayed_work(adapter
->qlcnic_wq
, &adapter
->mbx_poll_work
,
974 void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter
*adapter
)
976 if (test_and_set_bit(__QLCNIC_MBX_POLL_ENABLE
, &adapter
->state
))
979 INIT_DELAYED_WORK(&adapter
->mbx_poll_work
, qlcnic_83xx_mbx_poll_work
);
982 void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter
*adapter
)
984 if (!test_and_clear_bit(__QLCNIC_MBX_POLL_ENABLE
, &adapter
->state
))
986 cancel_delayed_work_sync(&adapter
->mbx_poll_work
);
989 static int qlcnic_83xx_add_rings(struct qlcnic_adapter
*adapter
)
991 int index
, i
, err
, sds_mbx_size
;
992 u32
*buf
, intrpt_id
, intr_mask
;
995 struct qlcnic_cmd_args cmd
;
996 struct qlcnic_host_sds_ring
*sds
;
997 struct qlcnic_sds_mbx sds_mbx
;
998 struct qlcnic_add_rings_mbx_out
*mbx_out
;
999 struct qlcnic_recv_context
*recv_ctx
= adapter
->recv_ctx
;
1000 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
1002 sds_mbx_size
= sizeof(struct qlcnic_sds_mbx
);
1003 context_id
= recv_ctx
->context_id
;
1004 num_sds
= (adapter
->max_sds_rings
- QLCNIC_MAX_RING_SETS
);
1005 ahw
->hw_ops
->alloc_mbx_args(&cmd
, adapter
,
1006 QLCNIC_CMD_ADD_RCV_RINGS
);
1007 cmd
.req
.arg
[1] = 0 | (num_sds
<< 8) | (context_id
<< 16);
1009 /* set up status rings, mbx 2-81 */
1011 for (i
= 8; i
< adapter
->max_sds_rings
; i
++) {
1012 memset(&sds_mbx
, 0, sds_mbx_size
);
1013 sds
= &recv_ctx
->sds_rings
[i
];
1015 memset(sds
->desc_head
, 0, STATUS_DESC_RINGSIZE(sds
));
1016 sds_mbx
.phy_addr_low
= LSD(sds
->phys_addr
);
1017 sds_mbx
.phy_addr_high
= MSD(sds
->phys_addr
);
1018 sds_mbx
.sds_ring_size
= sds
->num_desc
;
1020 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
1021 intrpt_id
= ahw
->intr_tbl
[i
].id
;
1023 intrpt_id
= QLCRDX(ahw
, QLCNIC_DEF_INT_ID
);
1025 if (adapter
->ahw
->diag_test
!= QLCNIC_LOOPBACK_TEST
)
1026 sds_mbx
.intrpt_id
= intrpt_id
;
1028 sds_mbx
.intrpt_id
= 0xffff;
1029 sds_mbx
.intrpt_val
= 0;
1030 buf
= &cmd
.req
.arg
[index
];
1031 memcpy(buf
, &sds_mbx
, sds_mbx_size
);
1032 index
+= sds_mbx_size
/ sizeof(u32
);
1035 /* send the mailbox command */
1036 err
= ahw
->hw_ops
->mbx_cmd(adapter
, &cmd
);
1038 dev_err(&adapter
->pdev
->dev
,
1039 "Failed to add rings %d\n", err
);
1043 mbx_out
= (struct qlcnic_add_rings_mbx_out
*)&cmd
.rsp
.arg
[1];
1045 /* status descriptor ring */
1046 for (i
= 8; i
< adapter
->max_sds_rings
; i
++) {
1047 sds
= &recv_ctx
->sds_rings
[i
];
1048 sds
->crb_sts_consumer
= ahw
->pci_base0
+
1049 mbx_out
->host_csmr
[index
];
1050 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
1051 intr_mask
= ahw
->intr_tbl
[i
].src
;
1053 intr_mask
= QLCRDX(ahw
, QLCNIC_DEF_INT_MASK
);
1055 sds
->crb_intr_mask
= ahw
->pci_base0
+ intr_mask
;
1059 qlcnic_free_mbx_args(&cmd
);
1063 void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter
*adapter
)
1067 struct qlcnic_cmd_args cmd
;
1068 struct qlcnic_recv_context
*recv_ctx
= adapter
->recv_ctx
;
1070 if (qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_DESTROY_RX_CTX
))
1073 if (qlcnic_sriov_pf_check(adapter
) || qlcnic_sriov_vf_check(adapter
))
1074 cmd
.req
.arg
[0] |= (0x3 << 29);
1076 if (qlcnic_sriov_pf_check(adapter
))
1077 qlcnic_pf_set_interface_id_del_rx_ctx(adapter
, &temp
);
1079 cmd
.req
.arg
[1] = recv_ctx
->context_id
| temp
;
1080 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1082 dev_err(&adapter
->pdev
->dev
,
1083 "Failed to destroy rx ctx in firmware\n");
1085 recv_ctx
->state
= QLCNIC_HOST_CTX_STATE_FREED
;
1086 qlcnic_free_mbx_args(&cmd
);
1089 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter
*adapter
)
1091 int i
, err
, index
, sds_mbx_size
, rds_mbx_size
;
1092 u8 num_sds
, num_rds
;
1093 u32
*buf
, intrpt_id
, intr_mask
, cap
= 0;
1094 struct qlcnic_host_sds_ring
*sds
;
1095 struct qlcnic_host_rds_ring
*rds
;
1096 struct qlcnic_sds_mbx sds_mbx
;
1097 struct qlcnic_rds_mbx rds_mbx
;
1098 struct qlcnic_cmd_args cmd
;
1099 struct qlcnic_rcv_mbx_out
*mbx_out
;
1100 struct qlcnic_recv_context
*recv_ctx
= adapter
->recv_ctx
;
1101 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
1102 num_rds
= adapter
->max_rds_rings
;
1104 if (adapter
->max_sds_rings
<= QLCNIC_MAX_RING_SETS
)
1105 num_sds
= adapter
->max_sds_rings
;
1107 num_sds
= QLCNIC_MAX_RING_SETS
;
1109 sds_mbx_size
= sizeof(struct qlcnic_sds_mbx
);
1110 rds_mbx_size
= sizeof(struct qlcnic_rds_mbx
);
1111 cap
= QLCNIC_CAP0_LEGACY_CONTEXT
;
1113 if (adapter
->flags
& QLCNIC_FW_LRO_MSS_CAP
)
1114 cap
|= QLC_83XX_FW_CAP_LRO_MSS
;
1116 /* set mailbox hdr and capabilities */
1117 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
1118 QLCNIC_CMD_CREATE_RX_CTX
);
1122 if (qlcnic_sriov_pf_check(adapter
) || qlcnic_sriov_vf_check(adapter
))
1123 cmd
.req
.arg
[0] |= (0x3 << 29);
1125 cmd
.req
.arg
[1] = cap
;
1126 cmd
.req
.arg
[5] = 1 | (num_rds
<< 5) | (num_sds
<< 8) |
1127 (QLC_83XX_HOST_RDS_MODE_UNIQUE
<< 16);
1129 if (qlcnic_sriov_pf_check(adapter
))
1130 qlcnic_pf_set_interface_id_create_rx_ctx(adapter
,
1132 /* set up status rings, mbx 8-57/87 */
1133 index
= QLC_83XX_HOST_SDS_MBX_IDX
;
1134 for (i
= 0; i
< num_sds
; i
++) {
1135 memset(&sds_mbx
, 0, sds_mbx_size
);
1136 sds
= &recv_ctx
->sds_rings
[i
];
1138 memset(sds
->desc_head
, 0, STATUS_DESC_RINGSIZE(sds
));
1139 sds_mbx
.phy_addr_low
= LSD(sds
->phys_addr
);
1140 sds_mbx
.phy_addr_high
= MSD(sds
->phys_addr
);
1141 sds_mbx
.sds_ring_size
= sds
->num_desc
;
1142 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
1143 intrpt_id
= ahw
->intr_tbl
[i
].id
;
1145 intrpt_id
= QLCRDX(ahw
, QLCNIC_DEF_INT_ID
);
1146 if (adapter
->ahw
->diag_test
!= QLCNIC_LOOPBACK_TEST
)
1147 sds_mbx
.intrpt_id
= intrpt_id
;
1149 sds_mbx
.intrpt_id
= 0xffff;
1150 sds_mbx
.intrpt_val
= 0;
1151 buf
= &cmd
.req
.arg
[index
];
1152 memcpy(buf
, &sds_mbx
, sds_mbx_size
);
1153 index
+= sds_mbx_size
/ sizeof(u32
);
1155 /* set up receive rings, mbx 88-111/135 */
1156 index
= QLCNIC_HOST_RDS_MBX_IDX
;
1157 rds
= &recv_ctx
->rds_rings
[0];
1159 memset(&rds_mbx
, 0, rds_mbx_size
);
1160 rds_mbx
.phy_addr_reg_low
= LSD(rds
->phys_addr
);
1161 rds_mbx
.phy_addr_reg_high
= MSD(rds
->phys_addr
);
1162 rds_mbx
.reg_ring_sz
= rds
->dma_size
;
1163 rds_mbx
.reg_ring_len
= rds
->num_desc
;
1165 rds
= &recv_ctx
->rds_rings
[1];
1167 rds_mbx
.phy_addr_jmb_low
= LSD(rds
->phys_addr
);
1168 rds_mbx
.phy_addr_jmb_high
= MSD(rds
->phys_addr
);
1169 rds_mbx
.jmb_ring_sz
= rds
->dma_size
;
1170 rds_mbx
.jmb_ring_len
= rds
->num_desc
;
1171 buf
= &cmd
.req
.arg
[index
];
1172 memcpy(buf
, &rds_mbx
, rds_mbx_size
);
1174 /* send the mailbox command */
1175 err
= ahw
->hw_ops
->mbx_cmd(adapter
, &cmd
);
1177 dev_err(&adapter
->pdev
->dev
,
1178 "Failed to create Rx ctx in firmware%d\n", err
);
1181 mbx_out
= (struct qlcnic_rcv_mbx_out
*)&cmd
.rsp
.arg
[1];
1182 recv_ctx
->context_id
= mbx_out
->ctx_id
;
1183 recv_ctx
->state
= mbx_out
->state
;
1184 recv_ctx
->virt_port
= mbx_out
->vport_id
;
1185 dev_info(&adapter
->pdev
->dev
, "Rx Context[%d] Created, state:0x%x\n",
1186 recv_ctx
->context_id
, recv_ctx
->state
);
1187 /* Receive descriptor ring */
1189 rds
= &recv_ctx
->rds_rings
[0];
1190 rds
->crb_rcv_producer
= ahw
->pci_base0
+
1191 mbx_out
->host_prod
[0].reg_buf
;
1193 rds
= &recv_ctx
->rds_rings
[1];
1194 rds
->crb_rcv_producer
= ahw
->pci_base0
+
1195 mbx_out
->host_prod
[0].jmb_buf
;
1196 /* status descriptor ring */
1197 for (i
= 0; i
< num_sds
; i
++) {
1198 sds
= &recv_ctx
->sds_rings
[i
];
1199 sds
->crb_sts_consumer
= ahw
->pci_base0
+
1200 mbx_out
->host_csmr
[i
];
1201 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
1202 intr_mask
= ahw
->intr_tbl
[i
].src
;
1204 intr_mask
= QLCRDX(ahw
, QLCNIC_DEF_INT_MASK
);
1205 sds
->crb_intr_mask
= ahw
->pci_base0
+ intr_mask
;
1208 if (adapter
->max_sds_rings
> QLCNIC_MAX_RING_SETS
)
1209 err
= qlcnic_83xx_add_rings(adapter
);
1211 qlcnic_free_mbx_args(&cmd
);
1215 void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter
*adapter
,
1216 struct qlcnic_host_tx_ring
*tx_ring
)
1218 struct qlcnic_cmd_args cmd
;
1221 if (qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_DESTROY_TX_CTX
))
1224 if (qlcnic_sriov_pf_check(adapter
) || qlcnic_sriov_vf_check(adapter
))
1225 cmd
.req
.arg
[0] |= (0x3 << 29);
1227 if (qlcnic_sriov_pf_check(adapter
))
1228 qlcnic_pf_set_interface_id_del_tx_ctx(adapter
, &temp
);
1230 cmd
.req
.arg
[1] = tx_ring
->ctx_id
| temp
;
1231 if (qlcnic_issue_cmd(adapter
, &cmd
))
1232 dev_err(&adapter
->pdev
->dev
,
1233 "Failed to destroy tx ctx in firmware\n");
1234 qlcnic_free_mbx_args(&cmd
);
1237 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter
*adapter
,
1238 struct qlcnic_host_tx_ring
*tx
, int ring
)
1242 u32
*buf
, intr_mask
, temp
= 0;
1243 struct qlcnic_cmd_args cmd
;
1244 struct qlcnic_tx_mbx mbx
;
1245 struct qlcnic_tx_mbx_out
*mbx_out
;
1246 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
1249 /* Reset host resources */
1251 tx
->sw_consumer
= 0;
1252 *(tx
->hw_consumer
) = 0;
1254 memset(&mbx
, 0, sizeof(struct qlcnic_tx_mbx
));
1256 /* setup mailbox inbox registerss */
1257 mbx
.phys_addr_low
= LSD(tx
->phys_addr
);
1258 mbx
.phys_addr_high
= MSD(tx
->phys_addr
);
1259 mbx
.cnsmr_index_low
= LSD(tx
->hw_cons_phys_addr
);
1260 mbx
.cnsmr_index_high
= MSD(tx
->hw_cons_phys_addr
);
1261 mbx
.size
= tx
->num_desc
;
1262 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
) {
1263 if (!(adapter
->flags
& QLCNIC_TX_INTR_SHARED
))
1264 msix_vector
= adapter
->max_sds_rings
+ ring
;
1266 msix_vector
= adapter
->max_sds_rings
- 1;
1267 msix_id
= ahw
->intr_tbl
[msix_vector
].id
;
1269 msix_id
= QLCRDX(ahw
, QLCNIC_DEF_INT_ID
);
1272 if (adapter
->ahw
->diag_test
!= QLCNIC_LOOPBACK_TEST
)
1273 mbx
.intr_id
= msix_id
;
1275 mbx
.intr_id
= 0xffff;
1278 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_CREATE_TX_CTX
);
1282 if (qlcnic_sriov_pf_check(adapter
) || qlcnic_sriov_vf_check(adapter
))
1283 cmd
.req
.arg
[0] |= (0x3 << 29);
1285 if (qlcnic_sriov_pf_check(adapter
))
1286 qlcnic_pf_set_interface_id_create_tx_ctx(adapter
, &temp
);
1288 cmd
.req
.arg
[1] = QLCNIC_CAP0_LEGACY_CONTEXT
;
1289 cmd
.req
.arg
[5] = QLCNIC_MAX_TX_QUEUES
| temp
;
1290 buf
= &cmd
.req
.arg
[6];
1291 memcpy(buf
, &mbx
, sizeof(struct qlcnic_tx_mbx
));
1292 /* send the mailbox command*/
1293 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1295 dev_err(&adapter
->pdev
->dev
,
1296 "Failed to create Tx ctx in firmware 0x%x\n", err
);
1299 mbx_out
= (struct qlcnic_tx_mbx_out
*)&cmd
.rsp
.arg
[2];
1300 tx
->crb_cmd_producer
= ahw
->pci_base0
+ mbx_out
->host_prod
;
1301 tx
->ctx_id
= mbx_out
->ctx_id
;
1302 if ((adapter
->flags
& QLCNIC_MSIX_ENABLED
) &&
1303 !(adapter
->flags
& QLCNIC_TX_INTR_SHARED
)) {
1304 intr_mask
= ahw
->intr_tbl
[adapter
->max_sds_rings
+ ring
].src
;
1305 tx
->crb_intr_mask
= ahw
->pci_base0
+ intr_mask
;
1307 dev_info(&adapter
->pdev
->dev
, "Tx Context[0x%x] Created, state:0x%x\n",
1308 tx
->ctx_id
, mbx_out
->state
);
1310 qlcnic_free_mbx_args(&cmd
);
1314 static int qlcnic_83xx_diag_alloc_res(struct net_device
*netdev
, int test
,
1317 struct qlcnic_adapter
*adapter
= netdev_priv(netdev
);
1318 struct qlcnic_host_sds_ring
*sds_ring
;
1319 struct qlcnic_host_rds_ring
*rds_ring
;
1320 u16 adapter_state
= adapter
->is_up
;
1324 netif_device_detach(netdev
);
1326 if (netif_running(netdev
))
1327 __qlcnic_down(adapter
, netdev
);
1329 qlcnic_detach(adapter
);
1331 adapter
->max_sds_rings
= 1;
1332 adapter
->ahw
->diag_test
= test
;
1333 adapter
->ahw
->linkup
= 0;
1335 ret
= qlcnic_attach(adapter
);
1337 netif_device_attach(netdev
);
1341 ret
= qlcnic_fw_create_ctx(adapter
);
1343 qlcnic_detach(adapter
);
1344 if (adapter_state
== QLCNIC_ADAPTER_UP_MAGIC
) {
1345 adapter
->max_sds_rings
= num_sds_ring
;
1346 qlcnic_attach(adapter
);
1348 netif_device_attach(netdev
);
1352 for (ring
= 0; ring
< adapter
->max_rds_rings
; ring
++) {
1353 rds_ring
= &adapter
->recv_ctx
->rds_rings
[ring
];
1354 qlcnic_post_rx_buffers(adapter
, rds_ring
, ring
);
1357 if (adapter
->ahw
->diag_test
== QLCNIC_INTERRUPT_TEST
) {
1358 for (ring
= 0; ring
< adapter
->max_sds_rings
; ring
++) {
1359 sds_ring
= &adapter
->recv_ctx
->sds_rings
[ring
];
1360 qlcnic_83xx_enable_intr(adapter
, sds_ring
);
1364 if (adapter
->ahw
->diag_test
== QLCNIC_LOOPBACK_TEST
) {
1365 /* disable and free mailbox interrupt */
1366 if (!(adapter
->flags
& QLCNIC_MSIX_ENABLED
))
1367 qlcnic_83xx_free_mbx_intr(adapter
);
1368 adapter
->ahw
->loopback_state
= 0;
1369 adapter
->ahw
->hw_ops
->setup_link_event(adapter
, 1);
1372 set_bit(__QLCNIC_DEV_UP
, &adapter
->state
);
1376 static void qlcnic_83xx_diag_free_res(struct net_device
*netdev
,
1379 struct qlcnic_adapter
*adapter
= netdev_priv(netdev
);
1380 struct qlcnic_host_sds_ring
*sds_ring
;
1383 clear_bit(__QLCNIC_DEV_UP
, &adapter
->state
);
1384 if (adapter
->ahw
->diag_test
== QLCNIC_INTERRUPT_TEST
) {
1385 for (ring
= 0; ring
< adapter
->max_sds_rings
; ring
++) {
1386 sds_ring
= &adapter
->recv_ctx
->sds_rings
[ring
];
1387 qlcnic_83xx_disable_intr(adapter
, sds_ring
);
1391 qlcnic_fw_destroy_ctx(adapter
);
1392 qlcnic_detach(adapter
);
1394 if (adapter
->ahw
->diag_test
== QLCNIC_LOOPBACK_TEST
) {
1395 if (!(adapter
->flags
& QLCNIC_MSIX_ENABLED
)) {
1396 err
= qlcnic_83xx_setup_mbx_intr(adapter
);
1398 dev_err(&adapter
->pdev
->dev
,
1399 "%s: failed to setup mbx interrupt\n",
1405 adapter
->ahw
->diag_test
= 0;
1406 adapter
->max_sds_rings
= max_sds_rings
;
1408 if (qlcnic_attach(adapter
))
1411 if (netif_running(netdev
))
1412 __qlcnic_up(adapter
, netdev
);
1414 netif_device_attach(netdev
);
1417 int qlcnic_83xx_config_led(struct qlcnic_adapter
*adapter
, u32 state
,
1420 struct qlcnic_cmd_args cmd
;
1425 /* Get LED configuration */
1426 status
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
1427 QLCNIC_CMD_GET_LED_CONFIG
);
1431 status
= qlcnic_issue_cmd(adapter
, &cmd
);
1433 dev_err(&adapter
->pdev
->dev
,
1434 "Get led config failed.\n");
1437 for (i
= 0; i
< 4; i
++)
1438 adapter
->ahw
->mbox_reg
[i
] = cmd
.rsp
.arg
[i
+1];
1440 qlcnic_free_mbx_args(&cmd
);
1441 /* Set LED Configuration */
1442 mbx_in
= (LSW(QLC_83XX_LED_CONFIG
) << 16) |
1443 LSW(QLC_83XX_LED_CONFIG
);
1444 status
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
1445 QLCNIC_CMD_SET_LED_CONFIG
);
1449 cmd
.req
.arg
[1] = mbx_in
;
1450 cmd
.req
.arg
[2] = mbx_in
;
1451 cmd
.req
.arg
[3] = mbx_in
;
1453 cmd
.req
.arg
[4] = QLC_83XX_ENABLE_BEACON
;
1454 status
= qlcnic_issue_cmd(adapter
, &cmd
);
1456 dev_err(&adapter
->pdev
->dev
,
1457 "Set led config failed.\n");
1460 qlcnic_free_mbx_args(&cmd
);
1464 /* Restoring default LED configuration */
1465 status
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
1466 QLCNIC_CMD_SET_LED_CONFIG
);
1470 cmd
.req
.arg
[1] = adapter
->ahw
->mbox_reg
[0];
1471 cmd
.req
.arg
[2] = adapter
->ahw
->mbox_reg
[1];
1472 cmd
.req
.arg
[3] = adapter
->ahw
->mbox_reg
[2];
1474 cmd
.req
.arg
[4] = adapter
->ahw
->mbox_reg
[3];
1475 status
= qlcnic_issue_cmd(adapter
, &cmd
);
1477 dev_err(&adapter
->pdev
->dev
,
1478 "Restoring led config failed.\n");
1479 qlcnic_free_mbx_args(&cmd
);
1484 int qlcnic_83xx_set_led(struct net_device
*netdev
,
1485 enum ethtool_phys_id_state state
)
1487 struct qlcnic_adapter
*adapter
= netdev_priv(netdev
);
1488 int err
= -EIO
, active
= 1;
1490 if (adapter
->ahw
->op_mode
== QLCNIC_NON_PRIV_FUNC
) {
1492 "LED test is not supported in non-privileged mode\n");
1497 case ETHTOOL_ID_ACTIVE
:
1498 if (test_and_set_bit(__QLCNIC_LED_ENABLE
, &adapter
->state
))
1501 if (test_bit(__QLCNIC_RESETTING
, &adapter
->state
))
1504 err
= qlcnic_83xx_config_led(adapter
, active
, 0);
1506 netdev_err(netdev
, "Failed to set LED blink state\n");
1508 case ETHTOOL_ID_INACTIVE
:
1511 if (test_bit(__QLCNIC_RESETTING
, &adapter
->state
))
1514 err
= qlcnic_83xx_config_led(adapter
, active
, 0);
1516 netdev_err(netdev
, "Failed to reset LED blink state\n");
1524 clear_bit(__QLCNIC_LED_ENABLE
, &adapter
->state
);
1529 void qlcnic_83xx_register_nic_idc_func(struct qlcnic_adapter
*adapter
,
1532 struct qlcnic_cmd_args cmd
;
1535 if (qlcnic_sriov_vf_check(adapter
))
1539 status
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
1540 QLCNIC_CMD_INIT_NIC_FUNC
);
1544 cmd
.req
.arg
[1] = BIT_0
| BIT_31
;
1546 status
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
1547 QLCNIC_CMD_STOP_NIC_FUNC
);
1551 cmd
.req
.arg
[1] = BIT_0
| BIT_31
;
1553 status
= qlcnic_issue_cmd(adapter
, &cmd
);
1555 dev_err(&adapter
->pdev
->dev
,
1556 "Failed to %s in NIC IDC function event.\n",
1557 (enable
? "register" : "unregister"));
1559 qlcnic_free_mbx_args(&cmd
);
1562 int qlcnic_83xx_set_port_config(struct qlcnic_adapter
*adapter
)
1564 struct qlcnic_cmd_args cmd
;
1567 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_SET_PORT_CONFIG
);
1571 cmd
.req
.arg
[1] = adapter
->ahw
->port_config
;
1572 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1574 dev_info(&adapter
->pdev
->dev
, "Set Port Config failed.\n");
1575 qlcnic_free_mbx_args(&cmd
);
1579 int qlcnic_83xx_get_port_config(struct qlcnic_adapter
*adapter
)
1581 struct qlcnic_cmd_args cmd
;
1584 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_GET_PORT_CONFIG
);
1588 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1590 dev_info(&adapter
->pdev
->dev
, "Get Port config failed\n");
1592 adapter
->ahw
->port_config
= cmd
.rsp
.arg
[1];
1593 qlcnic_free_mbx_args(&cmd
);
1597 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter
*adapter
, int enable
)
1601 struct qlcnic_cmd_args cmd
;
1603 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_GET_LINK_EVENT
);
1607 temp
= adapter
->recv_ctx
->context_id
<< 16;
1608 cmd
.req
.arg
[1] = (enable
? 1 : 0) | BIT_8
| temp
;
1609 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1611 dev_info(&adapter
->pdev
->dev
,
1612 "Setup linkevent mailbox failed\n");
1613 qlcnic_free_mbx_args(&cmd
);
1617 static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter
*adapter
,
1620 if (qlcnic_sriov_pf_check(adapter
)) {
1621 qlcnic_pf_set_interface_id_promisc(adapter
, interface_id
);
1623 if (!qlcnic_sriov_vf_check(adapter
))
1624 *interface_id
= adapter
->recv_ctx
->context_id
<< 16;
1628 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter
*adapter
, u32 mode
)
1632 struct qlcnic_cmd_args cmd
;
1634 if (adapter
->recv_ctx
->state
== QLCNIC_HOST_CTX_STATE_FREED
)
1637 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
1638 QLCNIC_CMD_CONFIGURE_MAC_RX_MODE
);
1642 qlcnic_83xx_set_interface_id_promisc(adapter
, &temp
);
1643 cmd
.req
.arg
[1] = (mode
? 1 : 0) | temp
;
1644 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1646 dev_info(&adapter
->pdev
->dev
,
1647 "Promiscous mode config failed\n");
1649 qlcnic_free_mbx_args(&cmd
);
1653 int qlcnic_83xx_loopback_test(struct net_device
*netdev
, u8 mode
)
1655 struct qlcnic_adapter
*adapter
= netdev_priv(netdev
);
1656 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
1657 int ret
= 0, loop
= 0, max_sds_rings
= adapter
->max_sds_rings
;
1659 if (ahw
->op_mode
== QLCNIC_NON_PRIV_FUNC
) {
1661 "Loopback test not supported in non privileged mode\n");
1665 if (test_bit(__QLCNIC_RESETTING
, &adapter
->state
)) {
1666 netdev_info(netdev
, "Device is resetting\n");
1670 if (qlcnic_get_diag_lock(adapter
)) {
1671 netdev_info(netdev
, "Device is in diagnostics mode\n");
1675 netdev_info(netdev
, "%s loopback test in progress\n",
1676 mode
== QLCNIC_ILB_MODE
? "internal" : "external");
1678 ret
= qlcnic_83xx_diag_alloc_res(netdev
, QLCNIC_LOOPBACK_TEST
,
1681 goto fail_diag_alloc
;
1683 ret
= qlcnic_83xx_set_lb_mode(adapter
, mode
);
1687 /* Poll for link up event before running traffic */
1689 msleep(QLC_83XX_LB_MSLEEP_COUNT
);
1690 if (!(adapter
->flags
& QLCNIC_MSIX_ENABLED
))
1691 qlcnic_83xx_process_aen(adapter
);
1693 if (test_bit(__QLCNIC_RESETTING
, &adapter
->state
)) {
1695 "Device is resetting, free LB test resources\n");
1699 if (loop
++ > QLC_83XX_LB_WAIT_COUNT
) {
1701 "Firmware didn't sent link up event to loopback request\n");
1703 qlcnic_83xx_clear_lb_mode(adapter
, mode
);
1706 } while ((adapter
->ahw
->linkup
&& ahw
->has_link_events
) != 1);
1708 /* Make sure carrier is off and queue is stopped during loopback */
1709 if (netif_running(netdev
)) {
1710 netif_carrier_off(netdev
);
1711 netif_stop_queue(netdev
);
1714 ret
= qlcnic_do_lb_test(adapter
, mode
);
1716 qlcnic_83xx_clear_lb_mode(adapter
, mode
);
1719 qlcnic_83xx_diag_free_res(netdev
, max_sds_rings
);
1722 adapter
->max_sds_rings
= max_sds_rings
;
1723 qlcnic_release_diag_lock(adapter
);
1727 int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter
*adapter
, u8 mode
)
1729 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
1730 struct net_device
*netdev
= adapter
->netdev
;
1731 int status
= 0, loop
= 0;
1734 status
= qlcnic_83xx_get_port_config(adapter
);
1738 config
= ahw
->port_config
;
1740 /* Check if port is already in loopback mode */
1741 if ((config
& QLC_83XX_CFG_LOOPBACK_HSS
) ||
1742 (config
& QLC_83XX_CFG_LOOPBACK_EXT
)) {
1744 "Port already in Loopback mode.\n");
1745 return -EINPROGRESS
;
1748 set_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
);
1750 if (mode
== QLCNIC_ILB_MODE
)
1751 ahw
->port_config
|= QLC_83XX_CFG_LOOPBACK_HSS
;
1752 if (mode
== QLCNIC_ELB_MODE
)
1753 ahw
->port_config
|= QLC_83XX_CFG_LOOPBACK_EXT
;
1755 status
= qlcnic_83xx_set_port_config(adapter
);
1758 "Failed to Set Loopback Mode = 0x%x.\n",
1760 ahw
->port_config
= config
;
1761 clear_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
);
1765 /* Wait for Link and IDC Completion AEN */
1767 msleep(QLC_83XX_LB_MSLEEP_COUNT
);
1768 if (!(adapter
->flags
& QLCNIC_MSIX_ENABLED
))
1769 qlcnic_83xx_process_aen(adapter
);
1771 if (test_bit(__QLCNIC_RESETTING
, &adapter
->state
)) {
1773 "Device is resetting, free LB test resources\n");
1774 clear_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
);
1777 if (loop
++ > QLC_83XX_LB_WAIT_COUNT
) {
1779 "Did not receive IDC completion AEN\n");
1780 clear_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
);
1781 qlcnic_83xx_clear_lb_mode(adapter
, mode
);
1784 } while (test_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
));
1786 qlcnic_sre_macaddr_change(adapter
, adapter
->mac_addr
, 0,
1791 int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter
*adapter
, u8 mode
)
1793 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
1794 struct net_device
*netdev
= adapter
->netdev
;
1795 int status
= 0, loop
= 0;
1796 u32 config
= ahw
->port_config
;
1798 set_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
);
1799 if (mode
== QLCNIC_ILB_MODE
)
1800 ahw
->port_config
&= ~QLC_83XX_CFG_LOOPBACK_HSS
;
1801 if (mode
== QLCNIC_ELB_MODE
)
1802 ahw
->port_config
&= ~QLC_83XX_CFG_LOOPBACK_EXT
;
1804 status
= qlcnic_83xx_set_port_config(adapter
);
1807 "Failed to Clear Loopback Mode = 0x%x.\n",
1809 ahw
->port_config
= config
;
1810 clear_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
);
1814 /* Wait for Link and IDC Completion AEN */
1816 msleep(QLC_83XX_LB_MSLEEP_COUNT
);
1817 if (!(adapter
->flags
& QLCNIC_MSIX_ENABLED
))
1818 qlcnic_83xx_process_aen(adapter
);
1820 if (test_bit(__QLCNIC_RESETTING
, &adapter
->state
)) {
1822 "Device is resetting, free LB test resources\n");
1823 clear_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
);
1827 if (loop
++ > QLC_83XX_LB_WAIT_COUNT
) {
1829 "Did not receive IDC completion AEN\n");
1830 clear_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
);
1833 } while (test_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
));
1835 qlcnic_sre_macaddr_change(adapter
, adapter
->mac_addr
, 0,
1840 static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter
*adapter
,
1843 if (qlcnic_sriov_pf_check(adapter
)) {
1844 qlcnic_pf_set_interface_id_ipaddr(adapter
, interface_id
);
1846 if (!qlcnic_sriov_vf_check(adapter
))
1847 *interface_id
= adapter
->recv_ctx
->context_id
<< 16;
1851 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter
*adapter
, __be32 ip
,
1855 u32 temp
= 0, temp_ip
;
1856 struct qlcnic_cmd_args cmd
;
1858 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
1859 QLCNIC_CMD_CONFIGURE_IP_ADDR
);
1863 qlcnic_83xx_set_interface_id_ipaddr(adapter
, &temp
);
1865 if (mode
== QLCNIC_IP_UP
)
1866 cmd
.req
.arg
[1] = 1 | temp
;
1868 cmd
.req
.arg
[1] = 2 | temp
;
1871 * Adapter needs IP address in network byte order.
1872 * But hardware mailbox registers go through writel(), hence IP address
1873 * gets swapped on big endian architecture.
1874 * To negate swapping of writel() on big endian architecture
1875 * use swab32(value).
1878 temp_ip
= swab32(ntohl(ip
));
1879 memcpy(&cmd
.req
.arg
[2], &temp_ip
, sizeof(u32
));
1880 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1881 if (err
!= QLCNIC_RCODE_SUCCESS
)
1882 dev_err(&adapter
->netdev
->dev
,
1883 "could not notify %s IP 0x%x request\n",
1884 (mode
== QLCNIC_IP_UP
) ? "Add" : "Remove", ip
);
1886 qlcnic_free_mbx_args(&cmd
);
1889 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter
*adapter
, int mode
)
1893 struct qlcnic_cmd_args cmd
;
1896 lro_bit_mask
= (mode
? (BIT_0
| BIT_1
| BIT_2
| BIT_3
) : 0);
1898 if (adapter
->recv_ctx
->state
== QLCNIC_HOST_CTX_STATE_FREED
)
1901 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_CONFIGURE_HW_LRO
);
1905 temp
= adapter
->recv_ctx
->context_id
<< 16;
1906 arg1
= lro_bit_mask
| temp
;
1907 cmd
.req
.arg
[1] = arg1
;
1909 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1911 dev_info(&adapter
->pdev
->dev
, "LRO config failed\n");
1912 qlcnic_free_mbx_args(&cmd
);
1917 int qlcnic_83xx_config_rss(struct qlcnic_adapter
*adapter
, int enable
)
1921 struct qlcnic_cmd_args cmd
;
1922 const u64 key
[] = { 0xbeac01fa6a42b73bULL
, 0x8030f20c77cb2da3ULL
,
1923 0xae7b30b4d0ca2bcbULL
, 0x43a38fb04167253dULL
,
1924 0x255b0ec26d5a56daULL
};
1926 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_CONFIGURE_RSS
);
1932 * 5-4: hash_type_ipv4
1933 * 7-6: hash_type_ipv6
1935 * 9: use indirection table
1936 * 16-31: indirection table mask
1938 word
= ((u32
)(RSS_HASHTYPE_IP_TCP
& 0x3) << 4) |
1939 ((u32
)(RSS_HASHTYPE_IP_TCP
& 0x3) << 6) |
1940 ((u32
)(enable
& 0x1) << 8) |
1942 cmd
.req
.arg
[1] = (adapter
->recv_ctx
->context_id
);
1943 cmd
.req
.arg
[2] = word
;
1944 memcpy(&cmd
.req
.arg
[4], key
, sizeof(key
));
1946 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1949 dev_info(&adapter
->pdev
->dev
, "RSS config failed\n");
1950 qlcnic_free_mbx_args(&cmd
);
1956 static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter
*adapter
,
1959 if (qlcnic_sriov_pf_check(adapter
)) {
1960 qlcnic_pf_set_interface_id_macaddr(adapter
, interface_id
);
1962 if (!qlcnic_sriov_vf_check(adapter
))
1963 *interface_id
= adapter
->recv_ctx
->context_id
<< 16;
1967 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter
*adapter
, u8
*addr
,
1972 struct qlcnic_cmd_args cmd
;
1973 struct qlcnic_macvlan_mbx mv
;
1975 if (adapter
->recv_ctx
->state
== QLCNIC_HOST_CTX_STATE_FREED
)
1978 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_CONFIG_MAC_VLAN
);
1983 op
= (op
== QLCNIC_MAC_ADD
|| op
== QLCNIC_MAC_VLAN_ADD
) ?
1984 QLCNIC_MAC_VLAN_ADD
: QLCNIC_MAC_VLAN_DEL
;
1986 cmd
.req
.arg
[1] = op
| (1 << 8);
1987 qlcnic_83xx_set_interface_id_macaddr(adapter
, &temp
);
1988 cmd
.req
.arg
[1] |= temp
;
1990 mv
.mac_addr0
= addr
[0];
1991 mv
.mac_addr1
= addr
[1];
1992 mv
.mac_addr2
= addr
[2];
1993 mv
.mac_addr3
= addr
[3];
1994 mv
.mac_addr4
= addr
[4];
1995 mv
.mac_addr5
= addr
[5];
1996 buf
= &cmd
.req
.arg
[2];
1997 memcpy(buf
, &mv
, sizeof(struct qlcnic_macvlan_mbx
));
1998 err
= qlcnic_issue_cmd(adapter
, &cmd
);
2000 dev_err(&adapter
->pdev
->dev
,
2001 "MAC-VLAN %s to CAM failed, err=%d.\n",
2002 ((op
== 1) ? "add " : "delete "), err
);
2003 qlcnic_free_mbx_args(&cmd
);
2007 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter
*adapter
, u64
*addr
,
2011 memcpy(&mac
, addr
, ETH_ALEN
);
2012 qlcnic_83xx_sre_macaddr_change(adapter
, mac
, vlan_id
, QLCNIC_MAC_ADD
);
2015 void qlcnic_83xx_configure_mac(struct qlcnic_adapter
*adapter
, u8
*mac
,
2016 u8 type
, struct qlcnic_cmd_args
*cmd
)
2019 case QLCNIC_SET_STATION_MAC
:
2020 case QLCNIC_SET_FAC_DEF_MAC
:
2021 memcpy(&cmd
->req
.arg
[2], mac
, sizeof(u32
));
2022 memcpy(&cmd
->req
.arg
[3], &mac
[4], sizeof(u16
));
2025 cmd
->req
.arg
[1] = type
;
2028 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter
*adapter
, u8
*mac
)
2031 struct qlcnic_cmd_args cmd
;
2032 u32 mac_low
, mac_high
;
2034 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_MAC_ADDRESS
);
2038 qlcnic_83xx_configure_mac(adapter
, mac
, QLCNIC_GET_CURRENT_MAC
, &cmd
);
2039 err
= qlcnic_issue_cmd(adapter
, &cmd
);
2041 if (err
== QLCNIC_RCODE_SUCCESS
) {
2042 mac_low
= cmd
.rsp
.arg
[1];
2043 mac_high
= cmd
.rsp
.arg
[2];
2045 for (i
= 0; i
< 2; i
++)
2046 mac
[i
] = (u8
) (mac_high
>> ((1 - i
) * 8));
2047 for (i
= 2; i
< 6; i
++)
2048 mac
[i
] = (u8
) (mac_low
>> ((5 - i
) * 8));
2050 dev_err(&adapter
->pdev
->dev
, "Failed to get mac address%d\n",
2054 qlcnic_free_mbx_args(&cmd
);
2058 void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter
*adapter
)
2062 struct qlcnic_cmd_args cmd
;
2063 struct qlcnic_nic_intr_coalesce
*coal
= &adapter
->ahw
->coal
;
2065 if (adapter
->recv_ctx
->state
== QLCNIC_HOST_CTX_STATE_FREED
)
2068 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_CONFIG_INTR_COAL
);
2072 if (coal
->type
== QLCNIC_INTR_COAL_TYPE_RX
) {
2073 temp
= adapter
->recv_ctx
->context_id
;
2074 cmd
.req
.arg
[1] = QLCNIC_INTR_COAL_TYPE_RX
| temp
<< 16;
2075 temp
= coal
->rx_time_us
;
2076 cmd
.req
.arg
[2] = coal
->rx_packets
| temp
<< 16;
2077 } else if (coal
->type
== QLCNIC_INTR_COAL_TYPE_TX
) {
2078 temp
= adapter
->tx_ring
->ctx_id
;
2079 cmd
.req
.arg
[1] = QLCNIC_INTR_COAL_TYPE_TX
| temp
<< 16;
2080 temp
= coal
->tx_time_us
;
2081 cmd
.req
.arg
[2] = coal
->tx_packets
| temp
<< 16;
2083 cmd
.req
.arg
[3] = coal
->flag
;
2084 err
= qlcnic_issue_cmd(adapter
, &cmd
);
2085 if (err
!= QLCNIC_RCODE_SUCCESS
)
2086 dev_info(&adapter
->pdev
->dev
,
2087 "Failed to send interrupt coalescence parameters\n");
2088 qlcnic_free_mbx_args(&cmd
);
2091 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter
*adapter
,
2094 u8 link_status
, duplex
;
2096 link_status
= LSB(data
[3]) & 1;
2097 adapter
->ahw
->link_speed
= MSW(data
[2]);
2098 adapter
->ahw
->link_autoneg
= MSB(MSW(data
[3]));
2099 adapter
->ahw
->module_type
= MSB(LSW(data
[3]));
2100 duplex
= LSB(MSW(data
[3]));
2102 adapter
->ahw
->link_duplex
= DUPLEX_FULL
;
2104 adapter
->ahw
->link_duplex
= DUPLEX_HALF
;
2105 adapter
->ahw
->has_link_events
= 1;
2106 qlcnic_advert_link_change(adapter
, link_status
);
2109 irqreturn_t
qlcnic_83xx_handle_aen(int irq
, void *data
)
2111 struct qlcnic_adapter
*adapter
= data
;
2112 unsigned long flags
;
2113 u32 mask
, resp
, event
;
2115 spin_lock_irqsave(&adapter
->ahw
->mbx_lock
, flags
);
2116 resp
= QLCRDX(adapter
->ahw
, QLCNIC_FW_MBX_CTRL
);
2117 if (!(resp
& QLCNIC_SET_OWNER
))
2120 event
= readl(QLCNIC_MBX_FW(adapter
->ahw
, 0));
2121 if (event
& QLCNIC_MBX_ASYNC_EVENT
)
2122 __qlcnic_83xx_process_aen(adapter
);
2124 mask
= QLCRDX(adapter
->ahw
, QLCNIC_DEF_INT_MASK
);
2125 writel(0, adapter
->ahw
->pci_base0
+ mask
);
2126 spin_unlock_irqrestore(&adapter
->ahw
->mbx_lock
, flags
);
2131 int qlcnic_enable_eswitch(struct qlcnic_adapter
*adapter
, u8 port
, u8 enable
)
2134 struct qlcnic_cmd_args cmd
;
2136 if (adapter
->ahw
->op_mode
!= QLCNIC_MGMT_FUNC
) {
2137 dev_err(&adapter
->pdev
->dev
,
2138 "%s: Error, invoked by non management func\n",
2143 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_TOGGLE_ESWITCH
);
2147 cmd
.req
.arg
[1] = (port
& 0xf) | BIT_4
;
2148 err
= qlcnic_issue_cmd(adapter
, &cmd
);
2150 if (err
!= QLCNIC_RCODE_SUCCESS
) {
2151 dev_err(&adapter
->pdev
->dev
, "Failed to enable eswitch%d\n",
2155 qlcnic_free_mbx_args(&cmd
);
2161 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter
*adapter
,
2162 struct qlcnic_info
*nic
)
2165 struct qlcnic_cmd_args cmd
;
2167 if (adapter
->ahw
->op_mode
!= QLCNIC_MGMT_FUNC
) {
2168 dev_err(&adapter
->pdev
->dev
,
2169 "%s: Error, invoked by non management func\n",
2174 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_SET_NIC_INFO
);
2178 cmd
.req
.arg
[1] = (nic
->pci_func
<< 16);
2179 cmd
.req
.arg
[2] = 0x1 << 16;
2180 cmd
.req
.arg
[3] = nic
->phys_port
| (nic
->switch_mode
<< 16);
2181 cmd
.req
.arg
[4] = nic
->capabilities
;
2182 cmd
.req
.arg
[5] = (nic
->max_mac_filters
& 0xFF) | ((nic
->max_mtu
) << 16);
2183 cmd
.req
.arg
[6] = (nic
->max_tx_ques
) | ((nic
->max_rx_ques
) << 16);
2184 cmd
.req
.arg
[7] = (nic
->min_tx_bw
) | ((nic
->max_tx_bw
) << 16);
2185 for (i
= 8; i
< 32; i
++)
2188 err
= qlcnic_issue_cmd(adapter
, &cmd
);
2190 if (err
!= QLCNIC_RCODE_SUCCESS
) {
2191 dev_err(&adapter
->pdev
->dev
, "Failed to set nic info%d\n",
2196 qlcnic_free_mbx_args(&cmd
);
2201 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter
*adapter
,
2202 struct qlcnic_info
*npar_info
, u8 func_id
)
2207 struct qlcnic_cmd_args cmd
;
2208 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
2210 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_GET_NIC_INFO
);
2214 if (func_id
!= ahw
->pci_func
) {
2215 temp
= func_id
<< 16;
2216 cmd
.req
.arg
[1] = op
| BIT_31
| temp
;
2218 cmd
.req
.arg
[1] = ahw
->pci_func
<< 16;
2220 err
= qlcnic_issue_cmd(adapter
, &cmd
);
2222 dev_info(&adapter
->pdev
->dev
,
2223 "Failed to get nic info %d\n", err
);
2227 npar_info
->op_type
= cmd
.rsp
.arg
[1];
2228 npar_info
->pci_func
= cmd
.rsp
.arg
[2] & 0xFFFF;
2229 npar_info
->op_mode
= (cmd
.rsp
.arg
[2] & 0xFFFF0000) >> 16;
2230 npar_info
->phys_port
= cmd
.rsp
.arg
[3] & 0xFFFF;
2231 npar_info
->switch_mode
= (cmd
.rsp
.arg
[3] & 0xFFFF0000) >> 16;
2232 npar_info
->capabilities
= cmd
.rsp
.arg
[4];
2233 npar_info
->max_mac_filters
= cmd
.rsp
.arg
[5] & 0xFF;
2234 npar_info
->max_mtu
= (cmd
.rsp
.arg
[5] & 0xFFFF0000) >> 16;
2235 npar_info
->max_tx_ques
= cmd
.rsp
.arg
[6] & 0xFFFF;
2236 npar_info
->max_rx_ques
= (cmd
.rsp
.arg
[6] & 0xFFFF0000) >> 16;
2237 npar_info
->min_tx_bw
= cmd
.rsp
.arg
[7] & 0xFFFF;
2238 npar_info
->max_tx_bw
= (cmd
.rsp
.arg
[7] & 0xFFFF0000) >> 16;
2239 if (cmd
.rsp
.arg
[8] & 0x1)
2240 npar_info
->max_bw_reg_offset
= (cmd
.rsp
.arg
[8] & 0x7FFE) >> 1;
2241 if (cmd
.rsp
.arg
[8] & 0x10000) {
2242 temp
= (cmd
.rsp
.arg
[8] & 0x7FFE0000) >> 17;
2243 npar_info
->max_linkspeed_reg_offset
= temp
;
2245 if (npar_info
->capabilities
& QLCNIC_FW_CAPABILITY_MORE_CAPS
)
2246 memcpy(ahw
->extra_capability
, &cmd
.rsp
.arg
[16],
2247 sizeof(ahw
->extra_capability
));
2250 qlcnic_free_mbx_args(&cmd
);
2254 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter
*adapter
,
2255 struct qlcnic_pci_info
*pci_info
)
2257 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
2258 struct device
*dev
= &adapter
->pdev
->dev
;
2259 struct qlcnic_cmd_args cmd
;
2260 int i
, err
= 0, j
= 0;
2263 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_GET_PCI_INFO
);
2267 err
= qlcnic_issue_cmd(adapter
, &cmd
);
2269 ahw
->act_pci_func
= 0;
2270 if (err
== QLCNIC_RCODE_SUCCESS
) {
2271 ahw
->max_pci_func
= cmd
.rsp
.arg
[1] & 0xFF;
2272 for (i
= 2, j
= 0; j
< QLCNIC_MAX_PCI_FUNC
; j
++, pci_info
++) {
2273 pci_info
->id
= cmd
.rsp
.arg
[i
] & 0xFFFF;
2274 pci_info
->active
= (cmd
.rsp
.arg
[i
] & 0xFFFF0000) >> 16;
2276 pci_info
->type
= cmd
.rsp
.arg
[i
] & 0xFFFF;
2277 if (pci_info
->type
== QLCNIC_TYPE_NIC
)
2278 ahw
->act_pci_func
++;
2279 temp
= (cmd
.rsp
.arg
[i
] & 0xFFFF0000) >> 16;
2280 pci_info
->default_port
= temp
;
2282 pci_info
->tx_min_bw
= cmd
.rsp
.arg
[i
] & 0xFFFF;
2283 temp
= (cmd
.rsp
.arg
[i
] & 0xFFFF0000) >> 16;
2284 pci_info
->tx_max_bw
= temp
;
2286 memcpy(pci_info
->mac
, &cmd
.rsp
.arg
[i
], ETH_ALEN
- 2);
2288 memcpy(pci_info
->mac
+ sizeof(u32
), &cmd
.rsp
.arg
[i
], 2);
2290 if (ahw
->op_mode
== QLCNIC_MGMT_FUNC
)
2291 dev_info(dev
, "id = %d active = %d type = %d\n"
2292 "\tport = %d min bw = %d max bw = %d\n"
2293 "\tmac_addr = %pM\n", pci_info
->id
,
2294 pci_info
->active
, pci_info
->type
,
2295 pci_info
->default_port
,
2296 pci_info
->tx_min_bw
,
2297 pci_info
->tx_max_bw
, pci_info
->mac
);
2299 if (ahw
->op_mode
== QLCNIC_MGMT_FUNC
)
2300 dev_info(dev
, "Max vNIC functions = %d, active vNIC functions = %d\n",
2301 ahw
->max_pci_func
, ahw
->act_pci_func
);
2304 dev_err(dev
, "Failed to get PCI Info, error = %d\n", err
);
2308 qlcnic_free_mbx_args(&cmd
);
2313 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter
*adapter
, bool op_type
)
2317 u32 val
, temp
, type
;
2318 struct qlcnic_cmd_args cmd
;
2320 max_ints
= adapter
->ahw
->num_msix
- 1;
2321 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_CONFIG_INTRPT
);
2325 cmd
.req
.arg
[1] = max_ints
;
2327 if (qlcnic_sriov_vf_check(adapter
))
2328 cmd
.req
.arg
[1] |= (adapter
->ahw
->pci_func
<< 8) | BIT_16
;
2330 for (i
= 0, index
= 2; i
< max_ints
; i
++) {
2331 type
= op_type
? QLCNIC_INTRPT_ADD
: QLCNIC_INTRPT_DEL
;
2332 val
= type
| (adapter
->ahw
->intr_tbl
[i
].type
<< 4);
2333 if (adapter
->ahw
->intr_tbl
[i
].type
== QLCNIC_INTRPT_MSIX
)
2334 val
|= (adapter
->ahw
->intr_tbl
[i
].id
<< 16);
2335 cmd
.req
.arg
[index
++] = val
;
2337 err
= qlcnic_issue_cmd(adapter
, &cmd
);
2339 dev_err(&adapter
->pdev
->dev
,
2340 "Failed to configure interrupts 0x%x\n", err
);
2344 max_ints
= cmd
.rsp
.arg
[1];
2345 for (i
= 0, index
= 2; i
< max_ints
; i
++, index
+= 2) {
2346 val
= cmd
.rsp
.arg
[index
];
2348 dev_info(&adapter
->pdev
->dev
,
2349 "Can't configure interrupt %d\n",
2350 adapter
->ahw
->intr_tbl
[i
].id
);
2354 adapter
->ahw
->intr_tbl
[i
].id
= MSW(val
);
2355 adapter
->ahw
->intr_tbl
[i
].enabled
= 1;
2356 temp
= cmd
.rsp
.arg
[index
+ 1];
2357 adapter
->ahw
->intr_tbl
[i
].src
= temp
;
2359 adapter
->ahw
->intr_tbl
[i
].id
= i
;
2360 adapter
->ahw
->intr_tbl
[i
].enabled
= 0;
2361 adapter
->ahw
->intr_tbl
[i
].src
= 0;
2365 qlcnic_free_mbx_args(&cmd
);
2369 int qlcnic_83xx_lock_flash(struct qlcnic_adapter
*adapter
)
2371 int id
, timeout
= 0;
2374 while (status
== 0) {
2375 status
= QLC_SHARED_REG_RD32(adapter
, QLCNIC_FLASH_LOCK
);
2379 if (++timeout
>= QLC_83XX_FLASH_LOCK_TIMEOUT
) {
2380 id
= QLC_SHARED_REG_RD32(adapter
,
2381 QLCNIC_FLASH_LOCK_OWNER
);
2382 dev_err(&adapter
->pdev
->dev
,
2383 "%s: failed, lock held by %d\n", __func__
, id
);
2386 usleep_range(1000, 2000);
2389 QLC_SHARED_REG_WR32(adapter
, QLCNIC_FLASH_LOCK_OWNER
, adapter
->portnum
);
2393 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter
*adapter
)
2395 QLC_SHARED_REG_RD32(adapter
, QLCNIC_FLASH_UNLOCK
);
2396 QLC_SHARED_REG_WR32(adapter
, QLCNIC_FLASH_LOCK_OWNER
, 0xFF);
2399 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter
*adapter
,
2400 u32 flash_addr
, u8
*p_data
,
2404 u32 word
, range
, flash_offset
, addr
= flash_addr
;
2405 ulong indirect_add
, direct_window
;
2407 flash_offset
= addr
& (QLCNIC_FLASH_SECTOR_SIZE
- 1);
2409 dev_err(&adapter
->pdev
->dev
, "Illegal addr = 0x%x\n", addr
);
2413 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_DIRECT_WINDOW
,
2416 range
= flash_offset
+ (count
* sizeof(u32
));
2417 /* Check if data is spread across multiple sectors */
2418 if (range
> (QLCNIC_FLASH_SECTOR_SIZE
- 1)) {
2420 /* Multi sector read */
2421 for (i
= 0; i
< count
; i
++) {
2422 indirect_add
= QLC_83XX_FLASH_DIRECT_DATA(addr
);
2423 ret
= qlcnic_83xx_rd_reg_indirect(adapter
,
2429 *(u32
*)p_data
= word
;
2430 p_data
= p_data
+ 4;
2432 flash_offset
= flash_offset
+ 4;
2434 if (flash_offset
> (QLCNIC_FLASH_SECTOR_SIZE
- 1)) {
2435 direct_window
= QLC_83XX_FLASH_DIRECT_WINDOW
;
2436 /* This write is needed once for each sector */
2437 qlcnic_83xx_wrt_reg_indirect(adapter
,
2444 /* Single sector read */
2445 for (i
= 0; i
< count
; i
++) {
2446 indirect_add
= QLC_83XX_FLASH_DIRECT_DATA(addr
);
2447 ret
= qlcnic_83xx_rd_reg_indirect(adapter
,
2453 *(u32
*)p_data
= word
;
2454 p_data
= p_data
+ 4;
2462 static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter
*adapter
)
2465 int retries
= QLC_83XX_FLASH_READ_RETRY_COUNT
;
2468 status
= qlcnic_83xx_rd_reg_indirect(adapter
,
2469 QLC_83XX_FLASH_STATUS
);
2470 if ((status
& QLC_83XX_FLASH_STATUS_READY
) ==
2471 QLC_83XX_FLASH_STATUS_READY
)
2474 msleep(QLC_83XX_FLASH_STATUS_REG_POLL_DELAY
);
2475 } while (--retries
);
2483 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter
*adapter
)
2487 cmd
= adapter
->ahw
->fdt
.write_statusreg_cmd
;
2488 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
,
2489 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG
| cmd
));
2490 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_WRDATA
,
2491 adapter
->ahw
->fdt
.write_enable_bits
);
2492 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
2493 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL
);
2494 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2501 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter
*adapter
)
2505 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
,
2506 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG
|
2507 adapter
->ahw
->fdt
.write_statusreg_cmd
));
2508 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_WRDATA
,
2509 adapter
->ahw
->fdt
.write_disable_bits
);
2510 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
2511 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL
);
2512 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2519 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter
*adapter
)
2523 if (qlcnic_83xx_lock_flash(adapter
))
2526 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
,
2527 QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL
);
2528 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
2529 QLC_83XX_FLASH_READ_CTRL
);
2530 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2532 qlcnic_83xx_unlock_flash(adapter
);
2536 mfg_id
= qlcnic_83xx_rd_reg_indirect(adapter
, QLC_83XX_FLASH_RDDATA
);
2540 adapter
->flash_mfg_id
= (mfg_id
& 0xFF);
2541 qlcnic_83xx_unlock_flash(adapter
);
2546 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter
*adapter
)
2548 int count
, fdt_size
, ret
= 0;
2550 fdt_size
= sizeof(struct qlcnic_fdt
);
2551 count
= fdt_size
/ sizeof(u32
);
2553 if (qlcnic_83xx_lock_flash(adapter
))
2556 memset(&adapter
->ahw
->fdt
, 0, fdt_size
);
2557 ret
= qlcnic_83xx_lockless_flash_read32(adapter
, QLCNIC_FDT_LOCATION
,
2558 (u8
*)&adapter
->ahw
->fdt
,
2561 qlcnic_83xx_unlock_flash(adapter
);
2565 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter
*adapter
,
2566 u32 sector_start_addr
)
2568 u32 reversed_addr
, addr1
, addr2
, cmd
;
2571 if (qlcnic_83xx_lock_flash(adapter
) != 0)
2574 if (adapter
->ahw
->fdt
.mfg_id
== adapter
->flash_mfg_id
) {
2575 ret
= qlcnic_83xx_enable_flash_write(adapter
);
2577 qlcnic_83xx_unlock_flash(adapter
);
2578 dev_err(&adapter
->pdev
->dev
,
2579 "%s failed at %d\n",
2580 __func__
, __LINE__
);
2585 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2587 qlcnic_83xx_unlock_flash(adapter
);
2588 dev_err(&adapter
->pdev
->dev
,
2589 "%s: failed at %d\n", __func__
, __LINE__
);
2593 addr1
= (sector_start_addr
& 0xFF) << 16;
2594 addr2
= (sector_start_addr
& 0xFF0000) >> 16;
2595 reversed_addr
= addr1
| addr2
;
2597 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_WRDATA
,
2599 cmd
= QLC_83XX_FLASH_FDT_ERASE_DEF_SIG
| adapter
->ahw
->fdt
.erase_cmd
;
2600 if (adapter
->ahw
->fdt
.mfg_id
== adapter
->flash_mfg_id
)
2601 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
, cmd
);
2603 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
,
2604 QLC_83XX_FLASH_OEM_ERASE_SIG
);
2605 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
2606 QLC_83XX_FLASH_LAST_ERASE_MS_VAL
);
2608 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2610 qlcnic_83xx_unlock_flash(adapter
);
2611 dev_err(&adapter
->pdev
->dev
,
2612 "%s: failed at %d\n", __func__
, __LINE__
);
2616 if (adapter
->ahw
->fdt
.mfg_id
== adapter
->flash_mfg_id
) {
2617 ret
= qlcnic_83xx_disable_flash_write(adapter
);
2619 qlcnic_83xx_unlock_flash(adapter
);
2620 dev_err(&adapter
->pdev
->dev
,
2621 "%s: failed at %d\n", __func__
, __LINE__
);
2626 qlcnic_83xx_unlock_flash(adapter
);
2631 int qlcnic_83xx_flash_write32(struct qlcnic_adapter
*adapter
, u32 addr
,
2635 u32 addr1
= 0x00800000 | (addr
>> 2);
2637 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
, addr1
);
2638 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_WRDATA
, *p_data
);
2639 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
2640 QLC_83XX_FLASH_LAST_ERASE_MS_VAL
);
2641 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2643 dev_err(&adapter
->pdev
->dev
,
2644 "%s: failed at %d\n", __func__
, __LINE__
);
2651 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter
*adapter
, u32 addr
,
2652 u32
*p_data
, int count
)
2657 if ((count
< QLC_83XX_FLASH_WRITE_MIN
) ||
2658 (count
> QLC_83XX_FLASH_WRITE_MAX
)) {
2659 dev_err(&adapter
->pdev
->dev
,
2660 "%s: Invalid word count\n", __func__
);
2664 temp
= qlcnic_83xx_rd_reg_indirect(adapter
,
2665 QLC_83XX_FLASH_SPI_CONTROL
);
2666 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_SPI_CONTROL
,
2667 (temp
| QLC_83XX_FLASH_SPI_CTRL
));
2668 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
,
2669 QLC_83XX_FLASH_ADDR_TEMP_VAL
);
2671 /* First DWORD write */
2672 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_WRDATA
, *p_data
++);
2673 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
2674 QLC_83XX_FLASH_FIRST_MS_PATTERN
);
2675 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2677 dev_err(&adapter
->pdev
->dev
,
2678 "%s: failed at %d\n", __func__
, __LINE__
);
2683 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
,
2684 QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL
);
2685 /* Second to N-1 DWORD writes */
2686 while (count
!= 1) {
2687 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_WRDATA
,
2689 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
2690 QLC_83XX_FLASH_SECOND_MS_PATTERN
);
2691 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2693 dev_err(&adapter
->pdev
->dev
,
2694 "%s: failed at %d\n", __func__
, __LINE__
);
2700 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
,
2701 QLC_83XX_FLASH_ADDR_TEMP_VAL
|
2703 /* Last DWORD write */
2704 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_WRDATA
, *p_data
++);
2705 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
2706 QLC_83XX_FLASH_LAST_MS_PATTERN
);
2707 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2709 dev_err(&adapter
->pdev
->dev
,
2710 "%s: failed at %d\n", __func__
, __LINE__
);
2714 ret
= qlcnic_83xx_rd_reg_indirect(adapter
, QLC_83XX_FLASH_SPI_STATUS
);
2715 if ((ret
& QLC_83XX_FLASH_SPI_CTRL
) == QLC_83XX_FLASH_SPI_CTRL
) {
2716 dev_err(&adapter
->pdev
->dev
, "%s: failed at %d\n",
2717 __func__
, __LINE__
);
2718 /* Operation failed, clear error bit */
2719 temp
= qlcnic_83xx_rd_reg_indirect(adapter
,
2720 QLC_83XX_FLASH_SPI_CONTROL
);
2721 qlcnic_83xx_wrt_reg_indirect(adapter
,
2722 QLC_83XX_FLASH_SPI_CONTROL
,
2723 (temp
| QLC_83XX_FLASH_SPI_CTRL
));
2729 static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter
*adapter
)
2733 val
= QLCRDX(adapter
->ahw
, QLC_83XX_RECOVER_DRV_LOCK
);
2735 /* Check if recovery need to be performed by the calling function */
2736 if ((val
& QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK
) == 0) {
2738 val
= val
| ((adapter
->portnum
<< 2) |
2739 QLC_83XX_NEED_DRV_LOCK_RECOVERY
);
2740 QLCWRX(adapter
->ahw
, QLC_83XX_RECOVER_DRV_LOCK
, val
);
2741 dev_info(&adapter
->pdev
->dev
,
2742 "%s: lock recovery initiated\n", __func__
);
2743 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY
);
2744 val
= QLCRDX(adapter
->ahw
, QLC_83XX_RECOVER_DRV_LOCK
);
2745 id
= ((val
>> 2) & 0xF);
2746 if (id
== adapter
->portnum
) {
2747 val
= val
& ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK
;
2748 val
= val
| QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS
;
2749 QLCWRX(adapter
->ahw
, QLC_83XX_RECOVER_DRV_LOCK
, val
);
2750 /* Force release the lock */
2751 QLCRDX(adapter
->ahw
, QLC_83XX_DRV_UNLOCK
);
2752 /* Clear recovery bits */
2754 QLCWRX(adapter
->ahw
, QLC_83XX_RECOVER_DRV_LOCK
, val
);
2755 dev_info(&adapter
->pdev
->dev
,
2756 "%s: lock recovery completed\n", __func__
);
2758 dev_info(&adapter
->pdev
->dev
,
2759 "%s: func %d to resume lock recovery process\n",
2763 dev_info(&adapter
->pdev
->dev
,
2764 "%s: lock recovery initiated by other functions\n",
2769 int qlcnic_83xx_lock_driver(struct qlcnic_adapter
*adapter
)
2771 u32 lock_alive_counter
, val
, id
, i
= 0, status
= 0, temp
= 0;
2772 int max_attempt
= 0;
2774 while (status
== 0) {
2775 status
= QLCRDX(adapter
->ahw
, QLC_83XX_DRV_LOCK
);
2779 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY
);
2783 temp
= QLCRDX(adapter
->ahw
, QLC_83XX_DRV_LOCK_ID
);
2785 if (i
== QLC_83XX_DRV_LOCK_WAIT_COUNTER
) {
2786 val
= QLCRDX(adapter
->ahw
, QLC_83XX_DRV_LOCK_ID
);
2789 dev_info(&adapter
->pdev
->dev
,
2790 "%s: lock to be recovered from %d\n",
2792 qlcnic_83xx_recover_driver_lock(adapter
);
2796 dev_err(&adapter
->pdev
->dev
,
2797 "%s: failed to get lock\n", __func__
);
2802 /* Force exit from while loop after few attempts */
2803 if (max_attempt
== QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT
) {
2804 dev_err(&adapter
->pdev
->dev
,
2805 "%s: failed to get lock\n", __func__
);
2810 val
= QLCRDX(adapter
->ahw
, QLC_83XX_DRV_LOCK_ID
);
2811 lock_alive_counter
= val
>> 8;
2812 lock_alive_counter
++;
2813 val
= lock_alive_counter
<< 8 | adapter
->portnum
;
2814 QLCWRX(adapter
->ahw
, QLC_83XX_DRV_LOCK_ID
, val
);
2819 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter
*adapter
)
2821 u32 val
, lock_alive_counter
, id
;
2823 val
= QLCRDX(adapter
->ahw
, QLC_83XX_DRV_LOCK_ID
);
2825 lock_alive_counter
= val
>> 8;
2827 if (id
!= adapter
->portnum
)
2828 dev_err(&adapter
->pdev
->dev
,
2829 "%s:Warning func %d is unlocking lock owned by %d\n",
2830 __func__
, adapter
->portnum
, id
);
2832 val
= (lock_alive_counter
<< 8) | 0xFF;
2833 QLCWRX(adapter
->ahw
, QLC_83XX_DRV_LOCK_ID
, val
);
2834 QLCRDX(adapter
->ahw
, QLC_83XX_DRV_UNLOCK
);
2837 int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter
*adapter
, u64 addr
,
2838 u32
*data
, u32 count
)
2843 /* Check alignment */
2847 mutex_lock(&adapter
->ahw
->mem_lock
);
2848 qlcnic_83xx_wrt_reg_indirect(adapter
, QLCNIC_MS_ADDR_HI
, 0);
2850 for (i
= 0; i
< count
; i
++, addr
+= 16) {
2851 if (!((ADDR_IN_RANGE(addr
, QLCNIC_ADDR_QDR_NET
,
2852 QLCNIC_ADDR_QDR_NET_MAX
)) ||
2853 (ADDR_IN_RANGE(addr
, QLCNIC_ADDR_DDR_NET
,
2854 QLCNIC_ADDR_DDR_NET_MAX
)))) {
2855 mutex_unlock(&adapter
->ahw
->mem_lock
);
2859 qlcnic_83xx_wrt_reg_indirect(adapter
, QLCNIC_MS_ADDR_LO
, addr
);
2860 qlcnic_83xx_wrt_reg_indirect(adapter
, QLCNIC_MS_WRTDATA_LO
,
2862 qlcnic_83xx_wrt_reg_indirect(adapter
, QLCNIC_MS_WRTDATA_HI
,
2864 qlcnic_83xx_wrt_reg_indirect(adapter
, QLCNIC_MS_WRTDATA_ULO
,
2866 qlcnic_83xx_wrt_reg_indirect(adapter
, QLCNIC_MS_WRTDATA_UHI
,
2868 qlcnic_83xx_wrt_reg_indirect(adapter
, QLCNIC_MS_CTRL
,
2869 QLCNIC_TA_WRITE_ENABLE
);
2870 qlcnic_83xx_wrt_reg_indirect(adapter
, QLCNIC_MS_CTRL
,
2871 QLCNIC_TA_WRITE_START
);
2873 for (j
= 0; j
< MAX_CTL_CHECK
; j
++) {
2874 temp
= qlcnic_83xx_rd_reg_indirect(adapter
,
2876 if ((temp
& TA_CTL_BUSY
) == 0)
2880 /* Status check failure */
2881 if (j
>= MAX_CTL_CHECK
) {
2882 printk_ratelimited(KERN_WARNING
2883 "MS memory write failed\n");
2884 mutex_unlock(&adapter
->ahw
->mem_lock
);
2889 mutex_unlock(&adapter
->ahw
->mem_lock
);
2894 int qlcnic_83xx_flash_read32(struct qlcnic_adapter
*adapter
, u32 flash_addr
,
2895 u8
*p_data
, int count
)
2898 u32 word
, addr
= flash_addr
;
2899 ulong indirect_addr
;
2901 if (qlcnic_83xx_lock_flash(adapter
) != 0)
2905 dev_err(&adapter
->pdev
->dev
, "Illegal addr = 0x%x\n", addr
);
2906 qlcnic_83xx_unlock_flash(adapter
);
2910 for (i
= 0; i
< count
; i
++) {
2911 if (qlcnic_83xx_wrt_reg_indirect(adapter
,
2912 QLC_83XX_FLASH_DIRECT_WINDOW
,
2914 qlcnic_83xx_unlock_flash(adapter
);
2918 indirect_addr
= QLC_83XX_FLASH_DIRECT_DATA(addr
);
2919 ret
= qlcnic_83xx_rd_reg_indirect(adapter
,
2924 *(u32
*)p_data
= word
;
2925 p_data
= p_data
+ 4;
2929 qlcnic_83xx_unlock_flash(adapter
);
2934 int qlcnic_83xx_test_link(struct qlcnic_adapter
*adapter
)
2938 u32 config
= 0, state
;
2939 struct qlcnic_cmd_args cmd
;
2940 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
2942 if (qlcnic_sriov_vf_check(adapter
))
2943 pci_func
= adapter
->portnum
;
2945 pci_func
= ahw
->pci_func
;
2947 state
= readl(ahw
->pci_base0
+ QLC_83XX_LINK_STATE(pci_func
));
2948 if (!QLC_83xx_FUNC_VAL(state
, pci_func
)) {
2949 dev_info(&adapter
->pdev
->dev
, "link state down\n");
2953 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_GET_LINK_STATUS
);
2957 err
= qlcnic_issue_cmd(adapter
, &cmd
);
2959 dev_info(&adapter
->pdev
->dev
,
2960 "Get Link Status Command failed: 0x%x\n", err
);
2963 config
= cmd
.rsp
.arg
[1];
2964 switch (QLC_83XX_CURRENT_LINK_SPEED(config
)) {
2965 case QLC_83XX_10M_LINK
:
2966 ahw
->link_speed
= SPEED_10
;
2968 case QLC_83XX_100M_LINK
:
2969 ahw
->link_speed
= SPEED_100
;
2971 case QLC_83XX_1G_LINK
:
2972 ahw
->link_speed
= SPEED_1000
;
2974 case QLC_83XX_10G_LINK
:
2975 ahw
->link_speed
= SPEED_10000
;
2978 ahw
->link_speed
= 0;
2981 config
= cmd
.rsp
.arg
[3];
2982 if (QLC_83XX_SFP_PRESENT(config
)) {
2983 switch (ahw
->module_type
) {
2984 case LINKEVENT_MODULE_OPTICAL_UNKNOWN
:
2985 case LINKEVENT_MODULE_OPTICAL_SRLR
:
2986 case LINKEVENT_MODULE_OPTICAL_LRM
:
2987 case LINKEVENT_MODULE_OPTICAL_SFP_1G
:
2988 ahw
->supported_type
= PORT_FIBRE
;
2990 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE
:
2991 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN
:
2992 case LINKEVENT_MODULE_TWINAX
:
2993 ahw
->supported_type
= PORT_TP
;
2996 ahw
->supported_type
= PORT_OTHER
;
3003 qlcnic_free_mbx_args(&cmd
);
3007 int qlcnic_83xx_get_settings(struct qlcnic_adapter
*adapter
,
3008 struct ethtool_cmd
*ecmd
)
3012 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3014 /* Get port configuration info */
3015 status
= qlcnic_83xx_get_port_info(adapter
);
3016 /* Get Link Status related info */
3017 config
= qlcnic_83xx_test_link(adapter
);
3018 ahw
->module_type
= QLC_83XX_SFP_MODULE_TYPE(config
);
3019 /* hard code until there is a way to get it from flash */
3020 ahw
->board_type
= QLCNIC_BRDTYPE_83XX_10G
;
3022 if (netif_running(adapter
->netdev
) && ahw
->has_link_events
) {
3023 ethtool_cmd_speed_set(ecmd
, ahw
->link_speed
);
3024 ecmd
->duplex
= ahw
->link_duplex
;
3025 ecmd
->autoneg
= ahw
->link_autoneg
;
3027 ethtool_cmd_speed_set(ecmd
, SPEED_UNKNOWN
);
3028 ecmd
->duplex
= DUPLEX_UNKNOWN
;
3029 ecmd
->autoneg
= AUTONEG_DISABLE
;
3032 if (ahw
->port_type
== QLCNIC_XGBE
) {
3033 ecmd
->supported
= SUPPORTED_1000baseT_Full
;
3034 ecmd
->advertising
= ADVERTISED_1000baseT_Full
;
3036 ecmd
->supported
= (SUPPORTED_10baseT_Half
|
3037 SUPPORTED_10baseT_Full
|
3038 SUPPORTED_100baseT_Half
|
3039 SUPPORTED_100baseT_Full
|
3040 SUPPORTED_1000baseT_Half
|
3041 SUPPORTED_1000baseT_Full
);
3042 ecmd
->advertising
= (ADVERTISED_100baseT_Half
|
3043 ADVERTISED_100baseT_Full
|
3044 ADVERTISED_1000baseT_Half
|
3045 ADVERTISED_1000baseT_Full
);
3048 switch (ahw
->supported_type
) {
3050 ecmd
->supported
|= SUPPORTED_FIBRE
;
3051 ecmd
->advertising
|= ADVERTISED_FIBRE
;
3052 ecmd
->port
= PORT_FIBRE
;
3053 ecmd
->transceiver
= XCVR_EXTERNAL
;
3056 ecmd
->supported
|= SUPPORTED_TP
;
3057 ecmd
->advertising
|= ADVERTISED_TP
;
3058 ecmd
->port
= PORT_TP
;
3059 ecmd
->transceiver
= XCVR_INTERNAL
;
3062 ecmd
->supported
|= SUPPORTED_FIBRE
;
3063 ecmd
->advertising
|= ADVERTISED_FIBRE
;
3064 ecmd
->port
= PORT_OTHER
;
3065 ecmd
->transceiver
= XCVR_EXTERNAL
;
3068 ecmd
->phy_address
= ahw
->physical_port
;
3072 int qlcnic_83xx_set_settings(struct qlcnic_adapter
*adapter
,
3073 struct ethtool_cmd
*ecmd
)
3076 u32 config
= adapter
->ahw
->port_config
;
3079 adapter
->ahw
->port_config
|= BIT_15
;
3081 switch (ethtool_cmd_speed(ecmd
)) {
3083 adapter
->ahw
->port_config
|= BIT_8
;
3086 adapter
->ahw
->port_config
|= BIT_9
;
3089 adapter
->ahw
->port_config
|= BIT_10
;
3092 adapter
->ahw
->port_config
|= BIT_11
;
3098 status
= qlcnic_83xx_set_port_config(adapter
);
3100 dev_info(&adapter
->pdev
->dev
,
3101 "Faild to Set Link Speed and autoneg.\n");
3102 adapter
->ahw
->port_config
= config
;
3107 static inline u64
*qlcnic_83xx_copy_stats(struct qlcnic_cmd_args
*cmd
,
3108 u64
*data
, int index
)
3113 low
= cmd
->rsp
.arg
[index
];
3114 hi
= cmd
->rsp
.arg
[index
+ 1];
3115 val
= (((u64
) low
) | (((u64
) hi
) << 32));
3120 static u64
*qlcnic_83xx_fill_stats(struct qlcnic_adapter
*adapter
,
3121 struct qlcnic_cmd_args
*cmd
, u64
*data
,
3124 int err
, k
, total_regs
;
3127 err
= qlcnic_issue_cmd(adapter
, cmd
);
3128 if (err
!= QLCNIC_RCODE_SUCCESS
) {
3129 dev_info(&adapter
->pdev
->dev
,
3130 "Error in get statistics mailbox command\n");
3134 total_regs
= cmd
->rsp
.num
;
3136 case QLC_83XX_STAT_MAC
:
3137 /* fill in MAC tx counters */
3138 for (k
= 2; k
< 28; k
+= 2)
3139 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3140 /* skip 24 bytes of reserved area */
3141 /* fill in MAC rx counters */
3142 for (k
+= 6; k
< 60; k
+= 2)
3143 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3144 /* skip 24 bytes of reserved area */
3145 /* fill in MAC rx frame stats */
3146 for (k
+= 6; k
< 80; k
+= 2)
3147 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3148 /* fill in eSwitch stats */
3149 for (; k
< total_regs
; k
+= 2)
3150 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3152 case QLC_83XX_STAT_RX
:
3153 for (k
= 2; k
< 8; k
+= 2)
3154 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3155 /* skip 8 bytes of reserved data */
3156 for (k
+= 2; k
< 24; k
+= 2)
3157 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3158 /* skip 8 bytes containing RE1FBQ error data */
3159 for (k
+= 2; k
< total_regs
; k
+= 2)
3160 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3162 case QLC_83XX_STAT_TX
:
3163 for (k
= 2; k
< 10; k
+= 2)
3164 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3165 /* skip 8 bytes of reserved data */
3166 for (k
+= 2; k
< total_regs
; k
+= 2)
3167 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3170 dev_warn(&adapter
->pdev
->dev
, "Unknown get statistics mode\n");
3176 void qlcnic_83xx_get_stats(struct qlcnic_adapter
*adapter
, u64
*data
)
3178 struct qlcnic_cmd_args cmd
;
3179 struct net_device
*netdev
= adapter
->netdev
;
3182 ret
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_GET_STATISTICS
);
3186 cmd
.req
.arg
[1] = BIT_1
| (adapter
->tx_ring
->ctx_id
<< 16);
3187 cmd
.rsp
.num
= QLC_83XX_TX_STAT_REGS
;
3188 data
= qlcnic_83xx_fill_stats(adapter
, &cmd
, data
,
3189 QLC_83XX_STAT_TX
, &ret
);
3191 netdev_err(netdev
, "Error getting Tx stats\n");
3195 cmd
.req
.arg
[1] = BIT_2
| (adapter
->portnum
<< 16);
3196 cmd
.rsp
.num
= QLC_83XX_MAC_STAT_REGS
;
3197 memset(cmd
.rsp
.arg
, 0, sizeof(u32
) * cmd
.rsp
.num
);
3198 data
= qlcnic_83xx_fill_stats(adapter
, &cmd
, data
,
3199 QLC_83XX_STAT_MAC
, &ret
);
3201 netdev_err(netdev
, "Error getting MAC stats\n");
3205 cmd
.req
.arg
[1] = adapter
->recv_ctx
->context_id
<< 16;
3206 cmd
.rsp
.num
= QLC_83XX_RX_STAT_REGS
;
3207 memset(cmd
.rsp
.arg
, 0, sizeof(u32
) * cmd
.rsp
.num
);
3208 data
= qlcnic_83xx_fill_stats(adapter
, &cmd
, data
,
3209 QLC_83XX_STAT_RX
, &ret
);
3211 netdev_err(netdev
, "Error getting Rx stats\n");
3213 qlcnic_free_mbx_args(&cmd
);
3216 int qlcnic_83xx_reg_test(struct qlcnic_adapter
*adapter
)
3218 u32 major
, minor
, sub
;
3220 major
= QLC_SHARED_REG_RD32(adapter
, QLCNIC_FW_VERSION_MAJOR
);
3221 minor
= QLC_SHARED_REG_RD32(adapter
, QLCNIC_FW_VERSION_MINOR
);
3222 sub
= QLC_SHARED_REG_RD32(adapter
, QLCNIC_FW_VERSION_SUB
);
3224 if (adapter
->fw_version
!= QLCNIC_VERSION_CODE(major
, minor
, sub
)) {
3225 dev_info(&adapter
->pdev
->dev
, "%s: Reg test failed\n",
3232 int qlcnic_83xx_get_regs_len(struct qlcnic_adapter
*adapter
)
3234 return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl
) *
3235 sizeof(adapter
->ahw
->ext_reg_tbl
)) +
3236 (ARRAY_SIZE(qlcnic_83xx_reg_tbl
) +
3237 sizeof(adapter
->ahw
->reg_tbl
));
3240 int qlcnic_83xx_get_registers(struct qlcnic_adapter
*adapter
, u32
*regs_buff
)
3244 for (i
= QLCNIC_DEV_INFO_SIZE
+ 1;
3245 j
< ARRAY_SIZE(qlcnic_83xx_reg_tbl
); i
++, j
++)
3246 regs_buff
[i
] = QLC_SHARED_REG_RD32(adapter
, j
);
3248 for (j
= 0; j
< ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl
); j
++)
3249 regs_buff
[i
++] = QLCRDX(adapter
->ahw
, j
);
3253 int qlcnic_83xx_interrupt_test(struct net_device
*netdev
)
3255 struct qlcnic_adapter
*adapter
= netdev_priv(netdev
);
3256 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3257 struct qlcnic_cmd_args cmd
;
3261 int ret
, max_sds_rings
= adapter
->max_sds_rings
;
3263 if (qlcnic_get_diag_lock(adapter
)) {
3264 netdev_info(netdev
, "Device in diagnostics mode\n");
3268 ret
= qlcnic_83xx_diag_alloc_res(netdev
, QLCNIC_INTERRUPT_TEST
,
3274 ret
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_INTRPT_TEST
);
3278 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
3279 intrpt_id
= ahw
->intr_tbl
[0].id
;
3281 intrpt_id
= QLCRDX(ahw
, QLCNIC_DEF_INT_ID
);
3284 cmd
.req
.arg
[2] = intrpt_id
;
3285 cmd
.req
.arg
[3] = BIT_0
;
3287 ret
= qlcnic_issue_cmd(adapter
, &cmd
);
3288 data
= cmd
.rsp
.arg
[2];
3290 val
= LSB(MSW(data
));
3291 if (id
!= intrpt_id
)
3292 dev_info(&adapter
->pdev
->dev
,
3293 "Interrupt generated: 0x%x, requested:0x%x\n",
3296 dev_err(&adapter
->pdev
->dev
,
3297 "Interrupt test error: 0x%x\n", val
);
3302 ret
= !ahw
->diag_cnt
;
3305 qlcnic_free_mbx_args(&cmd
);
3306 qlcnic_83xx_diag_free_res(netdev
, max_sds_rings
);
3309 adapter
->max_sds_rings
= max_sds_rings
;
3310 qlcnic_release_diag_lock(adapter
);
3314 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter
*adapter
,
3315 struct ethtool_pauseparam
*pause
)
3317 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3321 status
= qlcnic_83xx_get_port_config(adapter
);
3323 dev_err(&adapter
->pdev
->dev
,
3324 "%s: Get Pause Config failed\n", __func__
);
3327 config
= ahw
->port_config
;
3328 if (config
& QLC_83XX_CFG_STD_PAUSE
) {
3329 if (config
& QLC_83XX_CFG_STD_TX_PAUSE
)
3330 pause
->tx_pause
= 1;
3331 if (config
& QLC_83XX_CFG_STD_RX_PAUSE
)
3332 pause
->rx_pause
= 1;
3335 if (QLC_83XX_AUTONEG(config
))
3339 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter
*adapter
,
3340 struct ethtool_pauseparam
*pause
)
3342 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3346 status
= qlcnic_83xx_get_port_config(adapter
);
3348 dev_err(&adapter
->pdev
->dev
,
3349 "%s: Get Pause Config failed.\n", __func__
);
3352 config
= ahw
->port_config
;
3354 if (ahw
->port_type
== QLCNIC_GBE
) {
3356 ahw
->port_config
|= QLC_83XX_ENABLE_AUTONEG
;
3357 if (!pause
->autoneg
)
3358 ahw
->port_config
&= ~QLC_83XX_ENABLE_AUTONEG
;
3359 } else if ((ahw
->port_type
== QLCNIC_XGBE
) && (pause
->autoneg
)) {
3363 if (!(config
& QLC_83XX_CFG_STD_PAUSE
))
3364 ahw
->port_config
|= QLC_83XX_CFG_STD_PAUSE
;
3366 if (pause
->rx_pause
&& pause
->tx_pause
) {
3367 ahw
->port_config
|= QLC_83XX_CFG_STD_TX_RX_PAUSE
;
3368 } else if (pause
->rx_pause
&& !pause
->tx_pause
) {
3369 ahw
->port_config
&= ~QLC_83XX_CFG_STD_TX_PAUSE
;
3370 ahw
->port_config
|= QLC_83XX_CFG_STD_RX_PAUSE
;
3371 } else if (pause
->tx_pause
&& !pause
->rx_pause
) {
3372 ahw
->port_config
&= ~QLC_83XX_CFG_STD_RX_PAUSE
;
3373 ahw
->port_config
|= QLC_83XX_CFG_STD_TX_PAUSE
;
3374 } else if (!pause
->rx_pause
&& !pause
->tx_pause
) {
3375 ahw
->port_config
&= ~QLC_83XX_CFG_STD_TX_RX_PAUSE
;
3377 status
= qlcnic_83xx_set_port_config(adapter
);
3379 dev_err(&adapter
->pdev
->dev
,
3380 "%s: Set Pause Config failed.\n", __func__
);
3381 ahw
->port_config
= config
;
3386 static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter
*adapter
)
3390 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
,
3391 QLC_83XX_FLASH_OEM_READ_SIG
);
3392 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
3393 QLC_83XX_FLASH_READ_CTRL
);
3394 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
3398 ret
= qlcnic_83xx_rd_reg_indirect(adapter
, QLC_83XX_FLASH_RDDATA
);
3402 int qlcnic_83xx_flash_test(struct qlcnic_adapter
*adapter
)
3406 status
= qlcnic_83xx_read_flash_status_reg(adapter
);
3407 if (status
== -EIO
) {
3408 dev_info(&adapter
->pdev
->dev
, "%s: EEPROM test failed.\n",
3415 int qlcnic_83xx_shutdown(struct pci_dev
*pdev
)
3417 struct qlcnic_adapter
*adapter
= pci_get_drvdata(pdev
);
3418 struct net_device
*netdev
= adapter
->netdev
;
3421 netif_device_detach(netdev
);
3422 qlcnic_cancel_idc_work(adapter
);
3424 if (netif_running(netdev
))
3425 qlcnic_down(adapter
, netdev
);
3427 qlcnic_83xx_disable_mbx_intr(adapter
);
3428 cancel_delayed_work_sync(&adapter
->idc_aen_work
);
3430 retval
= pci_save_state(pdev
);
3437 int qlcnic_83xx_resume(struct qlcnic_adapter
*adapter
)
3439 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3440 struct qlc_83xx_idc
*idc
= &ahw
->idc
;
3443 err
= qlcnic_83xx_idc_init(adapter
);
3447 if (ahw
->nic_mode
== QLC_83XX_VIRTUAL_NIC_MODE
) {
3448 if (ahw
->op_mode
== QLCNIC_MGMT_FUNC
) {
3449 qlcnic_83xx_set_vnic_opmode(adapter
);
3451 err
= qlcnic_83xx_check_vnic_state(adapter
);
3457 err
= qlcnic_83xx_idc_reattach_driver(adapter
);
3461 qlcnic_schedule_work(adapter
, qlcnic_83xx_idc_poll_dev_state
,
3466 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox
*mbx
)
3468 INIT_COMPLETION(mbx
->completion
);
3469 set_bit(QLC_83XX_MBX_READY
, &mbx
->status
);
3472 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox
*mbx
)
3474 destroy_workqueue(mbx
->work_q
);
3479 qlcnic_83xx_notify_cmd_completion(struct qlcnic_adapter
*adapter
,
3480 struct qlcnic_cmd_args
*cmd
)
3482 atomic_set(&cmd
->rsp_status
, QLC_83XX_MBX_RESPONSE_ARRIVED
);
3484 if (cmd
->type
== QLC_83XX_MBX_CMD_NO_WAIT
) {
3485 qlcnic_free_mbx_args(cmd
);
3489 complete(&cmd
->completion
);
3492 static inline void qlcnic_83xx_flush_mbx_queue(struct qlcnic_adapter
*adapter
)
3494 struct qlcnic_mailbox
*mbx
= adapter
->ahw
->mailbox
;
3495 struct list_head
*head
= &mbx
->cmd_q
;
3496 struct qlcnic_cmd_args
*cmd
= NULL
;
3498 spin_lock(&mbx
->queue_lock
);
3500 while (!list_empty(head
)) {
3501 cmd
= list_entry(head
->next
, struct qlcnic_cmd_args
, list
);
3502 list_del(&cmd
->list
);
3504 qlcnic_83xx_notify_cmd_completion(adapter
, cmd
);
3507 spin_unlock(&mbx
->queue_lock
);
3510 static inline int qlcnic_83xx_check_mbx_status(struct qlcnic_adapter
*adapter
)
3512 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3513 struct qlcnic_mailbox
*mbx
= ahw
->mailbox
;
3516 if (!test_bit(QLC_83XX_MBX_READY
, &mbx
->status
))
3519 host_mbx_ctrl
= QLCRDX(ahw
, QLCNIC_HOST_MBX_CTRL
);
3520 if (host_mbx_ctrl
) {
3521 ahw
->idc
.collect_dump
= 1;
3528 static inline void qlcnic_83xx_signal_mbx_cmd(struct qlcnic_adapter
*adapter
,
3532 QLCWRX(adapter
->ahw
, QLCNIC_HOST_MBX_CTRL
, QLCNIC_SET_OWNER
);
3534 QLCWRX(adapter
->ahw
, QLCNIC_FW_MBX_CTRL
, QLCNIC_CLR_OWNER
);
3537 static inline void qlcnic_83xx_dequeue_mbx_cmd(struct qlcnic_adapter
*adapter
,
3538 struct qlcnic_cmd_args
*cmd
)
3540 struct qlcnic_mailbox
*mbx
= adapter
->ahw
->mailbox
;
3542 spin_lock(&mbx
->queue_lock
);
3544 list_del(&cmd
->list
);
3547 spin_unlock(&mbx
->queue_lock
);
3549 qlcnic_83xx_notify_cmd_completion(adapter
, cmd
);
3552 static void qlcnic_83xx_encode_mbx_cmd(struct qlcnic_adapter
*adapter
,
3553 struct qlcnic_cmd_args
*cmd
)
3555 u32 mbx_cmd
, fw_hal_version
, hdr_size
, total_size
, tmp
;
3556 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3559 if (cmd
->op_type
!= QLC_83XX_MBX_POST_BC_OP
) {
3560 mbx_cmd
= cmd
->req
.arg
[0];
3561 writel(mbx_cmd
, QLCNIC_MBX_HOST(ahw
, 0));
3562 for (i
= 1; i
< cmd
->req
.num
; i
++)
3563 writel(cmd
->req
.arg
[i
], QLCNIC_MBX_HOST(ahw
, i
));
3565 fw_hal_version
= ahw
->fw_hal_version
;
3566 hdr_size
= sizeof(struct qlcnic_bc_hdr
) / sizeof(u32
);
3567 total_size
= cmd
->pay_size
+ hdr_size
;
3568 tmp
= QLCNIC_CMD_BC_EVENT_SETUP
| total_size
<< 16;
3569 mbx_cmd
= tmp
| fw_hal_version
<< 29;
3570 writel(mbx_cmd
, QLCNIC_MBX_HOST(ahw
, 0));
3572 /* Back channel specific operations bits */
3573 mbx_cmd
= 0x1 | 1 << 4;
3575 if (qlcnic_sriov_pf_check(adapter
))
3576 mbx_cmd
|= cmd
->func_num
<< 5;
3578 writel(mbx_cmd
, QLCNIC_MBX_HOST(ahw
, 1));
3580 for (i
= 2, j
= 0; j
< hdr_size
; i
++, j
++)
3581 writel(*(cmd
->hdr
++), QLCNIC_MBX_HOST(ahw
, i
));
3582 for (j
= 0; j
< cmd
->pay_size
; j
++, i
++)
3583 writel(*(cmd
->pay
++), QLCNIC_MBX_HOST(ahw
, i
));
3587 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter
*adapter
)
3589 struct qlcnic_mailbox
*mbx
= adapter
->ahw
->mailbox
;
3591 clear_bit(QLC_83XX_MBX_READY
, &mbx
->status
);
3592 complete(&mbx
->completion
);
3593 cancel_work_sync(&mbx
->work
);
3594 flush_workqueue(mbx
->work_q
);
3595 qlcnic_83xx_flush_mbx_queue(adapter
);
3598 static inline int qlcnic_83xx_enqueue_mbx_cmd(struct qlcnic_adapter
*adapter
,
3599 struct qlcnic_cmd_args
*cmd
,
3600 unsigned long *timeout
)
3602 struct qlcnic_mailbox
*mbx
= adapter
->ahw
->mailbox
;
3604 if (test_bit(QLC_83XX_MBX_READY
, &mbx
->status
)) {
3605 atomic_set(&cmd
->rsp_status
, QLC_83XX_MBX_RESPONSE_WAIT
);
3606 init_completion(&cmd
->completion
);
3607 cmd
->rsp_opcode
= QLC_83XX_MBX_RESPONSE_UNKNOWN
;
3609 spin_lock(&mbx
->queue_lock
);
3611 list_add_tail(&cmd
->list
, &mbx
->cmd_q
);
3613 cmd
->total_cmds
= mbx
->num_cmds
;
3614 *timeout
= cmd
->total_cmds
* QLC_83XX_MBX_TIMEOUT
;
3615 queue_work(mbx
->work_q
, &mbx
->work
);
3617 spin_unlock(&mbx
->queue_lock
);
3625 static inline int qlcnic_83xx_check_mac_rcode(struct qlcnic_adapter
*adapter
,
3626 struct qlcnic_cmd_args
*cmd
)
3631 if (cmd
->cmd_op
== QLCNIC_CMD_CONFIG_MAC_VLAN
) {
3632 fw_data
= readl(QLCNIC_MBX_FW(adapter
->ahw
, 2));
3633 mac_cmd_rcode
= (u8
)fw_data
;
3634 if (mac_cmd_rcode
== QLC_83XX_NO_NIC_RESOURCE
||
3635 mac_cmd_rcode
== QLC_83XX_MAC_PRESENT
||
3636 mac_cmd_rcode
== QLC_83XX_MAC_ABSENT
) {
3637 cmd
->rsp_opcode
= QLCNIC_RCODE_SUCCESS
;
3638 return QLCNIC_RCODE_SUCCESS
;
3645 static void qlcnic_83xx_decode_mbx_rsp(struct qlcnic_adapter
*adapter
,
3646 struct qlcnic_cmd_args
*cmd
)
3648 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3649 struct device
*dev
= &adapter
->pdev
->dev
;
3653 fw_data
= readl(QLCNIC_MBX_FW(ahw
, 0));
3654 mbx_err_code
= QLCNIC_MBX_STATUS(fw_data
);
3655 qlcnic_83xx_get_mbx_data(adapter
, cmd
);
3657 switch (mbx_err_code
) {
3658 case QLCNIC_MBX_RSP_OK
:
3659 case QLCNIC_MBX_PORT_RSP_OK
:
3660 cmd
->rsp_opcode
= QLCNIC_RCODE_SUCCESS
;
3663 if (!qlcnic_83xx_check_mac_rcode(adapter
, cmd
))
3666 dev_err(dev
, "%s: Mailbox command failed, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x, error=0x%x\n",
3667 __func__
, cmd
->cmd_op
, cmd
->type
, ahw
->pci_func
,
3668 ahw
->op_mode
, mbx_err_code
);
3669 cmd
->rsp_opcode
= QLC_83XX_MBX_RESPONSE_FAILED
;
3670 qlcnic_dump_mbx(adapter
, cmd
);
3676 static void qlcnic_83xx_mailbox_worker(struct work_struct
*work
)
3678 struct qlcnic_mailbox
*mbx
= container_of(work
, struct qlcnic_mailbox
,
3680 struct qlcnic_adapter
*adapter
= mbx
->adapter
;
3681 struct qlcnic_mbx_ops
*mbx_ops
= mbx
->ops
;
3682 struct device
*dev
= &adapter
->pdev
->dev
;
3683 atomic_t
*rsp_status
= &mbx
->rsp_status
;
3684 struct list_head
*head
= &mbx
->cmd_q
;
3685 struct qlcnic_hardware_context
*ahw
;
3686 struct qlcnic_cmd_args
*cmd
= NULL
;
3691 if (qlcnic_83xx_check_mbx_status(adapter
))
3694 atomic_set(rsp_status
, QLC_83XX_MBX_RESPONSE_WAIT
);
3696 spin_lock(&mbx
->queue_lock
);
3698 if (list_empty(head
)) {
3699 spin_unlock(&mbx
->queue_lock
);
3702 cmd
= list_entry(head
->next
, struct qlcnic_cmd_args
, list
);
3704 spin_unlock(&mbx
->queue_lock
);
3706 mbx_ops
->encode_cmd(adapter
, cmd
);
3707 mbx_ops
->nofity_fw(adapter
, QLC_83XX_MBX_REQUEST
);
3709 if (wait_for_completion_timeout(&mbx
->completion
,
3710 QLC_83XX_MBX_TIMEOUT
)) {
3711 mbx_ops
->decode_resp(adapter
, cmd
);
3712 mbx_ops
->nofity_fw(adapter
, QLC_83XX_MBX_COMPLETION
);
3714 dev_err(dev
, "%s: Mailbox command timeout, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x\n",
3715 __func__
, cmd
->cmd_op
, cmd
->type
, ahw
->pci_func
,
3717 clear_bit(QLC_83XX_MBX_READY
, &mbx
->status
);
3718 qlcnic_83xx_idc_request_reset(adapter
,
3719 QLCNIC_FORCE_FW_DUMP_KEY
);
3720 cmd
->rsp_opcode
= QLCNIC_RCODE_TIMEOUT
;
3722 mbx_ops
->dequeue_cmd(adapter
, cmd
);
3726 static struct qlcnic_mbx_ops qlcnic_83xx_mbx_ops
= {
3727 .enqueue_cmd
= qlcnic_83xx_enqueue_mbx_cmd
,
3728 .dequeue_cmd
= qlcnic_83xx_dequeue_mbx_cmd
,
3729 .decode_resp
= qlcnic_83xx_decode_mbx_rsp
,
3730 .encode_cmd
= qlcnic_83xx_encode_mbx_cmd
,
3731 .nofity_fw
= qlcnic_83xx_signal_mbx_cmd
,
3734 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter
*adapter
)
3736 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3737 struct qlcnic_mailbox
*mbx
;
3739 ahw
->mailbox
= kzalloc(sizeof(*mbx
), GFP_KERNEL
);
3744 mbx
->ops
= &qlcnic_83xx_mbx_ops
;
3745 mbx
->adapter
= adapter
;
3747 spin_lock_init(&mbx
->queue_lock
);
3748 spin_lock_init(&mbx
->aen_lock
);
3749 INIT_LIST_HEAD(&mbx
->cmd_q
);
3750 init_completion(&mbx
->completion
);
3752 mbx
->work_q
= create_singlethread_workqueue("qlcnic_mailbox");
3753 if (mbx
->work_q
== NULL
) {
3758 INIT_WORK(&mbx
->work
, qlcnic_83xx_mailbox_worker
);
3759 set_bit(QLC_83XX_MBX_READY
, &mbx
->status
);