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[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic_83xx_hw.c
1 /*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
8 #include "qlcnic.h"
9 #include "qlcnic_sriov.h"
10 #include <linux/if_vlan.h>
11 #include <linux/ipv6.h>
12 #include <linux/ethtool.h>
13 #include <linux/interrupt.h>
14
15 #define QLCNIC_MAX_TX_QUEUES 1
16 #define RSS_HASHTYPE_IP_TCP 0x3
17 #define QLC_83XX_FW_MBX_CMD 0
18
19 static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = {
20 {QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1},
21 {QLCNIC_CMD_CONFIG_INTRPT, 18, 34},
22 {QLCNIC_CMD_CREATE_RX_CTX, 136, 27},
23 {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
24 {QLCNIC_CMD_CREATE_TX_CTX, 54, 18},
25 {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
26 {QLCNIC_CMD_CONFIGURE_MAC_LEARNING, 2, 1},
27 {QLCNIC_CMD_INTRPT_TEST, 22, 12},
28 {QLCNIC_CMD_SET_MTU, 3, 1},
29 {QLCNIC_CMD_READ_PHY, 4, 2},
30 {QLCNIC_CMD_WRITE_PHY, 5, 1},
31 {QLCNIC_CMD_READ_HW_REG, 4, 1},
32 {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
33 {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
34 {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
35 {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
36 {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
37 {QLCNIC_CMD_GET_PCI_INFO, 1, 66},
38 {QLCNIC_CMD_GET_NIC_INFO, 2, 19},
39 {QLCNIC_CMD_SET_NIC_INFO, 32, 1},
40 {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
41 {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
42 {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
43 {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
44 {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
45 {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
46 {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
47 {QLCNIC_CMD_CONFIG_PORT, 4, 1},
48 {QLCNIC_CMD_TEMP_SIZE, 1, 4},
49 {QLCNIC_CMD_GET_TEMP_HDR, 5, 5},
50 {QLCNIC_CMD_GET_LINK_EVENT, 2, 1},
51 {QLCNIC_CMD_CONFIG_MAC_VLAN, 4, 3},
52 {QLCNIC_CMD_CONFIG_INTR_COAL, 6, 1},
53 {QLCNIC_CMD_CONFIGURE_RSS, 14, 1},
54 {QLCNIC_CMD_CONFIGURE_LED, 2, 1},
55 {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE, 2, 1},
56 {QLCNIC_CMD_CONFIGURE_HW_LRO, 2, 1},
57 {QLCNIC_CMD_GET_STATISTICS, 2, 80},
58 {QLCNIC_CMD_SET_PORT_CONFIG, 2, 1},
59 {QLCNIC_CMD_GET_PORT_CONFIG, 2, 2},
60 {QLCNIC_CMD_GET_LINK_STATUS, 2, 4},
61 {QLCNIC_CMD_IDC_ACK, 5, 1},
62 {QLCNIC_CMD_INIT_NIC_FUNC, 2, 1},
63 {QLCNIC_CMD_STOP_NIC_FUNC, 2, 1},
64 {QLCNIC_CMD_SET_LED_CONFIG, 5, 1},
65 {QLCNIC_CMD_GET_LED_CONFIG, 1, 5},
66 {QLCNIC_CMD_83XX_SET_DRV_VER, 4, 1},
67 {QLCNIC_CMD_ADD_RCV_RINGS, 130, 26},
68 {QLCNIC_CMD_CONFIG_VPORT, 4, 4},
69 {QLCNIC_CMD_BC_EVENT_SETUP, 2, 1},
70 };
71
72 const u32 qlcnic_83xx_ext_reg_tbl[] = {
73 0x38CC, /* Global Reset */
74 0x38F0, /* Wildcard */
75 0x38FC, /* Informant */
76 0x3038, /* Host MBX ctrl */
77 0x303C, /* FW MBX ctrl */
78 0x355C, /* BOOT LOADER ADDRESS REG */
79 0x3560, /* BOOT LOADER SIZE REG */
80 0x3564, /* FW IMAGE ADDR REG */
81 0x1000, /* MBX intr enable */
82 0x1200, /* Default Intr mask */
83 0x1204, /* Default Interrupt ID */
84 0x3780, /* QLC_83XX_IDC_MAJ_VERSION */
85 0x3784, /* QLC_83XX_IDC_DEV_STATE */
86 0x3788, /* QLC_83XX_IDC_DRV_PRESENCE */
87 0x378C, /* QLC_83XX_IDC_DRV_ACK */
88 0x3790, /* QLC_83XX_IDC_CTRL */
89 0x3794, /* QLC_83XX_IDC_DRV_AUDIT */
90 0x3798, /* QLC_83XX_IDC_MIN_VERSION */
91 0x379C, /* QLC_83XX_RECOVER_DRV_LOCK */
92 0x37A0, /* QLC_83XX_IDC_PF_0 */
93 0x37A4, /* QLC_83XX_IDC_PF_1 */
94 0x37A8, /* QLC_83XX_IDC_PF_2 */
95 0x37AC, /* QLC_83XX_IDC_PF_3 */
96 0x37B0, /* QLC_83XX_IDC_PF_4 */
97 0x37B4, /* QLC_83XX_IDC_PF_5 */
98 0x37B8, /* QLC_83XX_IDC_PF_6 */
99 0x37BC, /* QLC_83XX_IDC_PF_7 */
100 0x37C0, /* QLC_83XX_IDC_PF_8 */
101 0x37C4, /* QLC_83XX_IDC_PF_9 */
102 0x37C8, /* QLC_83XX_IDC_PF_10 */
103 0x37CC, /* QLC_83XX_IDC_PF_11 */
104 0x37D0, /* QLC_83XX_IDC_PF_12 */
105 0x37D4, /* QLC_83XX_IDC_PF_13 */
106 0x37D8, /* QLC_83XX_IDC_PF_14 */
107 0x37DC, /* QLC_83XX_IDC_PF_15 */
108 0x37E0, /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */
109 0x37E4, /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */
110 0x37F0, /* QLC_83XX_DRV_OP_MODE */
111 0x37F4, /* QLC_83XX_VNIC_STATE */
112 0x3868, /* QLC_83XX_DRV_LOCK */
113 0x386C, /* QLC_83XX_DRV_UNLOCK */
114 0x3504, /* QLC_83XX_DRV_LOCK_ID */
115 0x34A4, /* QLC_83XX_ASIC_TEMP */
116 };
117
118 const u32 qlcnic_83xx_reg_tbl[] = {
119 0x34A8, /* PEG_HALT_STAT1 */
120 0x34AC, /* PEG_HALT_STAT2 */
121 0x34B0, /* FW_HEARTBEAT */
122 0x3500, /* FLASH LOCK_ID */
123 0x3528, /* FW_CAPABILITIES */
124 0x3538, /* Driver active, DRV_REG0 */
125 0x3540, /* Device state, DRV_REG1 */
126 0x3544, /* Driver state, DRV_REG2 */
127 0x3548, /* Driver scratch, DRV_REG3 */
128 0x354C, /* Device partiton info, DRV_REG4 */
129 0x3524, /* Driver IDC ver, DRV_REG5 */
130 0x3550, /* FW_VER_MAJOR */
131 0x3554, /* FW_VER_MINOR */
132 0x3558, /* FW_VER_SUB */
133 0x359C, /* NPAR STATE */
134 0x35FC, /* FW_IMG_VALID */
135 0x3650, /* CMD_PEG_STATE */
136 0x373C, /* RCV_PEG_STATE */
137 0x37B4, /* ASIC TEMP */
138 0x356C, /* FW API */
139 0x3570, /* DRV OP MODE */
140 0x3850, /* FLASH LOCK */
141 0x3854, /* FLASH UNLOCK */
142 };
143
144 static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = {
145 .read_crb = qlcnic_83xx_read_crb,
146 .write_crb = qlcnic_83xx_write_crb,
147 .read_reg = qlcnic_83xx_rd_reg_indirect,
148 .write_reg = qlcnic_83xx_wrt_reg_indirect,
149 .get_mac_address = qlcnic_83xx_get_mac_address,
150 .setup_intr = qlcnic_83xx_setup_intr,
151 .alloc_mbx_args = qlcnic_83xx_alloc_mbx_args,
152 .mbx_cmd = qlcnic_83xx_issue_cmd,
153 .get_func_no = qlcnic_83xx_get_func_no,
154 .api_lock = qlcnic_83xx_cam_lock,
155 .api_unlock = qlcnic_83xx_cam_unlock,
156 .add_sysfs = qlcnic_83xx_add_sysfs,
157 .remove_sysfs = qlcnic_83xx_remove_sysfs,
158 .process_lb_rcv_ring_diag = qlcnic_83xx_process_rcv_ring_diag,
159 .create_rx_ctx = qlcnic_83xx_create_rx_ctx,
160 .create_tx_ctx = qlcnic_83xx_create_tx_ctx,
161 .del_rx_ctx = qlcnic_83xx_del_rx_ctx,
162 .del_tx_ctx = qlcnic_83xx_del_tx_ctx,
163 .setup_link_event = qlcnic_83xx_setup_link_event,
164 .get_nic_info = qlcnic_83xx_get_nic_info,
165 .get_pci_info = qlcnic_83xx_get_pci_info,
166 .set_nic_info = qlcnic_83xx_set_nic_info,
167 .change_macvlan = qlcnic_83xx_sre_macaddr_change,
168 .napi_enable = qlcnic_83xx_napi_enable,
169 .napi_disable = qlcnic_83xx_napi_disable,
170 .config_intr_coal = qlcnic_83xx_config_intr_coal,
171 .config_rss = qlcnic_83xx_config_rss,
172 .config_hw_lro = qlcnic_83xx_config_hw_lro,
173 .config_promisc_mode = qlcnic_83xx_nic_set_promisc,
174 .change_l2_filter = qlcnic_83xx_change_l2_filter,
175 .get_board_info = qlcnic_83xx_get_port_info,
176 .set_mac_filter_count = qlcnic_83xx_set_mac_filter_count,
177 .free_mac_list = qlcnic_82xx_free_mac_list,
178 };
179
180 static struct qlcnic_nic_template qlcnic_83xx_ops = {
181 .config_bridged_mode = qlcnic_config_bridged_mode,
182 .config_led = qlcnic_config_led,
183 .request_reset = qlcnic_83xx_idc_request_reset,
184 .cancel_idc_work = qlcnic_83xx_idc_exit,
185 .napi_add = qlcnic_83xx_napi_add,
186 .napi_del = qlcnic_83xx_napi_del,
187 .config_ipaddr = qlcnic_83xx_config_ipaddr,
188 .clear_legacy_intr = qlcnic_83xx_clear_legacy_intr,
189 .shutdown = qlcnic_83xx_shutdown,
190 .resume = qlcnic_83xx_resume,
191 };
192
193 void qlcnic_83xx_register_map(struct qlcnic_hardware_context *ahw)
194 {
195 ahw->hw_ops = &qlcnic_83xx_hw_ops;
196 ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl;
197 ahw->ext_reg_tbl = (u32 *)qlcnic_83xx_ext_reg_tbl;
198 }
199
200 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *adapter)
201 {
202 u32 fw_major, fw_minor, fw_build;
203 struct pci_dev *pdev = adapter->pdev;
204
205 fw_major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
206 fw_minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
207 fw_build = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
208 adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build);
209
210 dev_info(&pdev->dev, "Driver v%s, firmware version %d.%d.%d\n",
211 QLCNIC_LINUX_VERSIONID, fw_major, fw_minor, fw_build);
212
213 return adapter->fw_version;
214 }
215
216 static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr)
217 {
218 void __iomem *base;
219 u32 val;
220
221 base = adapter->ahw->pci_base0 +
222 QLC_83XX_CRB_WIN_FUNC(adapter->ahw->pci_func);
223 writel(addr, base);
224 val = readl(base);
225 if (val != addr)
226 return -EIO;
227
228 return 0;
229 }
230
231 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr)
232 {
233 int ret;
234 struct qlcnic_hardware_context *ahw = adapter->ahw;
235
236 ret = __qlcnic_set_win_base(adapter, (u32) addr);
237 if (!ret) {
238 return QLCRDX(ahw, QLCNIC_WILDCARD);
239 } else {
240 dev_err(&adapter->pdev->dev,
241 "%s failed, addr = 0x%x\n", __func__, (int)addr);
242 return -EIO;
243 }
244 }
245
246 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
247 u32 data)
248 {
249 int err;
250 struct qlcnic_hardware_context *ahw = adapter->ahw;
251
252 err = __qlcnic_set_win_base(adapter, (u32) addr);
253 if (!err) {
254 QLCWRX(ahw, QLCNIC_WILDCARD, data);
255 return 0;
256 } else {
257 dev_err(&adapter->pdev->dev,
258 "%s failed, addr = 0x%x data = 0x%x\n",
259 __func__, (int)addr, data);
260 return err;
261 }
262 }
263
264 int qlcnic_83xx_setup_intr(struct qlcnic_adapter *adapter, u8 num_intr)
265 {
266 int err, i, num_msix;
267 struct qlcnic_hardware_context *ahw = adapter->ahw;
268
269 if (!num_intr)
270 num_intr = QLCNIC_DEF_NUM_STS_DESC_RINGS;
271 num_msix = rounddown_pow_of_two(min_t(int, num_online_cpus(),
272 num_intr));
273 /* account for AEN interrupt MSI-X based interrupts */
274 num_msix += 1;
275
276 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
277 num_msix += adapter->max_drv_tx_rings;
278
279 err = qlcnic_enable_msix(adapter, num_msix);
280 if (err == -ENOMEM)
281 return err;
282 if (adapter->flags & QLCNIC_MSIX_ENABLED)
283 num_msix = adapter->ahw->num_msix;
284 else {
285 if (qlcnic_sriov_vf_check(adapter))
286 return -EINVAL;
287 num_msix = 1;
288 }
289 /* setup interrupt mapping table for fw */
290 ahw->intr_tbl = vzalloc(num_msix *
291 sizeof(struct qlcnic_intrpt_config));
292 if (!ahw->intr_tbl)
293 return -ENOMEM;
294 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
295 /* MSI-X enablement failed, use legacy interrupt */
296 adapter->tgt_status_reg = ahw->pci_base0 + QLC_83XX_INTX_PTR;
297 adapter->tgt_mask_reg = ahw->pci_base0 + QLC_83XX_INTX_MASK;
298 adapter->isr_int_vec = ahw->pci_base0 + QLC_83XX_INTX_TRGR;
299 adapter->msix_entries[0].vector = adapter->pdev->irq;
300 dev_info(&adapter->pdev->dev, "using legacy interrupt\n");
301 }
302
303 for (i = 0; i < num_msix; i++) {
304 if (adapter->flags & QLCNIC_MSIX_ENABLED)
305 ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX;
306 else
307 ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX;
308 ahw->intr_tbl[i].id = i;
309 ahw->intr_tbl[i].src = 0;
310 }
311 return 0;
312 }
313
314 inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter)
315 {
316 writel(0, adapter->tgt_mask_reg);
317 }
318
319 inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter *adapter)
320 {
321 writel(1, adapter->tgt_mask_reg);
322 }
323
324 /* Enable MSI-x and INT-x interrupts */
325 void qlcnic_83xx_enable_intr(struct qlcnic_adapter *adapter,
326 struct qlcnic_host_sds_ring *sds_ring)
327 {
328 writel(0, sds_ring->crb_intr_mask);
329 }
330
331 /* Disable MSI-x and INT-x interrupts */
332 void qlcnic_83xx_disable_intr(struct qlcnic_adapter *adapter,
333 struct qlcnic_host_sds_ring *sds_ring)
334 {
335 writel(1, sds_ring->crb_intr_mask);
336 }
337
338 inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
339 *adapter)
340 {
341 u32 mask;
342
343 /* Mailbox in MSI-x mode and Legacy Interrupt share the same
344 * source register. We could be here before contexts are created
345 * and sds_ring->crb_intr_mask has not been initialized, calculate
346 * BAR offset for Interrupt Source Register
347 */
348 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
349 writel(0, adapter->ahw->pci_base0 + mask);
350 }
351
352 void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter)
353 {
354 u32 mask;
355
356 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
357 writel(1, adapter->ahw->pci_base0 + mask);
358 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0);
359 }
360
361 static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter,
362 struct qlcnic_cmd_args *cmd)
363 {
364 int i;
365 for (i = 0; i < cmd->rsp.num; i++)
366 cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i));
367 }
368
369 irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter)
370 {
371 u32 intr_val;
372 struct qlcnic_hardware_context *ahw = adapter->ahw;
373 int retries = 0;
374
375 intr_val = readl(adapter->tgt_status_reg);
376
377 if (!QLC_83XX_VALID_INTX_BIT31(intr_val))
378 return IRQ_NONE;
379
380 if (QLC_83XX_INTX_FUNC(intr_val) != adapter->ahw->pci_func) {
381 adapter->stats.spurious_intr++;
382 return IRQ_NONE;
383 }
384 /* The barrier is required to ensure writes to the registers */
385 wmb();
386
387 /* clear the interrupt trigger control register */
388 writel(0, adapter->isr_int_vec);
389 intr_val = readl(adapter->isr_int_vec);
390 do {
391 intr_val = readl(adapter->tgt_status_reg);
392 if (QLC_83XX_INTX_FUNC(intr_val) != ahw->pci_func)
393 break;
394 retries++;
395 } while (QLC_83XX_VALID_INTX_BIT30(intr_val) &&
396 (retries < QLC_83XX_LEGACY_INTX_MAX_RETRY));
397
398 return IRQ_HANDLED;
399 }
400
401 static inline void qlcnic_83xx_notify_mbx_response(struct qlcnic_mailbox *mbx)
402 {
403 atomic_set(&mbx->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
404 complete(&mbx->completion);
405 }
406
407 static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter *adapter)
408 {
409 u32 resp, event;
410 unsigned long flags;
411
412 spin_lock_irqsave(&adapter->ahw->mbx_lock, flags);
413
414 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
415 if (!(resp & QLCNIC_SET_OWNER))
416 goto out;
417
418 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
419 if (event & QLCNIC_MBX_ASYNC_EVENT)
420 __qlcnic_83xx_process_aen(adapter);
421
422 out:
423 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
424 spin_unlock_irqrestore(&adapter->ahw->mbx_lock, flags);
425 }
426
427 irqreturn_t qlcnic_83xx_intr(int irq, void *data)
428 {
429 struct qlcnic_adapter *adapter = data;
430 struct qlcnic_host_sds_ring *sds_ring;
431 struct qlcnic_hardware_context *ahw = adapter->ahw;
432
433 if (qlcnic_83xx_clear_legacy_intr(adapter) == IRQ_NONE)
434 return IRQ_NONE;
435
436 qlcnic_83xx_poll_process_aen(adapter);
437
438 if (ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
439 ahw->diag_cnt++;
440 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
441 return IRQ_HANDLED;
442 }
443
444 if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
445 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
446 } else {
447 sds_ring = &adapter->recv_ctx->sds_rings[0];
448 napi_schedule(&sds_ring->napi);
449 }
450
451 return IRQ_HANDLED;
452 }
453
454 irqreturn_t qlcnic_83xx_tmp_intr(int irq, void *data)
455 {
456 struct qlcnic_host_sds_ring *sds_ring = data;
457 struct qlcnic_adapter *adapter = sds_ring->adapter;
458
459 if (adapter->flags & QLCNIC_MSIX_ENABLED)
460 goto done;
461
462 if (adapter->nic_ops->clear_legacy_intr(adapter) == IRQ_NONE)
463 return IRQ_NONE;
464
465 done:
466 adapter->ahw->diag_cnt++;
467 qlcnic_83xx_enable_intr(adapter, sds_ring);
468
469 return IRQ_HANDLED;
470 }
471
472 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *adapter)
473 {
474 u32 num_msix;
475
476 if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
477 qlcnic_83xx_set_legacy_intr_mask(adapter);
478
479 qlcnic_83xx_disable_mbx_intr(adapter);
480
481 if (adapter->flags & QLCNIC_MSIX_ENABLED)
482 num_msix = adapter->ahw->num_msix - 1;
483 else
484 num_msix = 0;
485
486 msleep(20);
487 synchronize_irq(adapter->msix_entries[num_msix].vector);
488 free_irq(adapter->msix_entries[num_msix].vector, adapter);
489 }
490
491 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *adapter)
492 {
493 irq_handler_t handler;
494 u32 val;
495 int err = 0;
496 unsigned long flags = 0;
497
498 if (!(adapter->flags & QLCNIC_MSI_ENABLED) &&
499 !(adapter->flags & QLCNIC_MSIX_ENABLED))
500 flags |= IRQF_SHARED;
501
502 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
503 handler = qlcnic_83xx_handle_aen;
504 val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector;
505 err = request_irq(val, handler, flags, "qlcnic-MB", adapter);
506 if (err) {
507 dev_err(&adapter->pdev->dev,
508 "failed to register MBX interrupt\n");
509 return err;
510 }
511 } else {
512 handler = qlcnic_83xx_intr;
513 val = adapter->msix_entries[0].vector;
514 err = request_irq(val, handler, flags, "qlcnic", adapter);
515 if (err) {
516 dev_err(&adapter->pdev->dev,
517 "failed to register INTx interrupt\n");
518 return err;
519 }
520 qlcnic_83xx_clear_legacy_intr_mask(adapter);
521 }
522
523 /* Enable mailbox interrupt */
524 qlcnic_83xx_enable_mbx_interrupt(adapter);
525
526 return err;
527 }
528
529 void qlcnic_83xx_get_func_no(struct qlcnic_adapter *adapter)
530 {
531 u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT);
532 adapter->ahw->pci_func = (val >> 24) & 0xff;
533 }
534
535 int qlcnic_83xx_cam_lock(struct qlcnic_adapter *adapter)
536 {
537 void __iomem *addr;
538 u32 val, limit = 0;
539
540 struct qlcnic_hardware_context *ahw = adapter->ahw;
541
542 addr = ahw->pci_base0 + QLC_83XX_SEM_LOCK_FUNC(ahw->pci_func);
543 do {
544 val = readl(addr);
545 if (val) {
546 /* write the function number to register */
547 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER,
548 ahw->pci_func);
549 return 0;
550 }
551 usleep_range(1000, 2000);
552 } while (++limit <= QLCNIC_PCIE_SEM_TIMEOUT);
553
554 return -EIO;
555 }
556
557 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter)
558 {
559 void __iomem *addr;
560 u32 val;
561 struct qlcnic_hardware_context *ahw = adapter->ahw;
562
563 addr = ahw->pci_base0 + QLC_83XX_SEM_UNLOCK_FUNC(ahw->pci_func);
564 val = readl(addr);
565 }
566
567 void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
568 loff_t offset, size_t size)
569 {
570 int ret;
571 u32 data;
572
573 if (qlcnic_api_lock(adapter)) {
574 dev_err(&adapter->pdev->dev,
575 "%s: failed to acquire lock. addr offset 0x%x\n",
576 __func__, (u32)offset);
577 return;
578 }
579
580 ret = qlcnic_83xx_rd_reg_indirect(adapter, (u32) offset);
581 qlcnic_api_unlock(adapter);
582
583 if (ret == -EIO) {
584 dev_err(&adapter->pdev->dev,
585 "%s: failed. addr offset 0x%x\n",
586 __func__, (u32)offset);
587 return;
588 }
589 data = ret;
590 memcpy(buf, &data, size);
591 }
592
593 void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
594 loff_t offset, size_t size)
595 {
596 u32 data;
597
598 memcpy(&data, buf, size);
599 qlcnic_83xx_wrt_reg_indirect(adapter, (u32) offset, data);
600 }
601
602 int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter)
603 {
604 int status;
605
606 status = qlcnic_83xx_get_port_config(adapter);
607 if (status) {
608 dev_err(&adapter->pdev->dev,
609 "Get Port Info failed\n");
610 } else {
611 if (QLC_83XX_SFP_10G_CAPABLE(adapter->ahw->port_config))
612 adapter->ahw->port_type = QLCNIC_XGBE;
613 else
614 adapter->ahw->port_type = QLCNIC_GBE;
615
616 if (QLC_83XX_AUTONEG(adapter->ahw->port_config))
617 adapter->ahw->link_autoneg = AUTONEG_ENABLE;
618 }
619 return status;
620 }
621
622 void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *adapter)
623 {
624 struct qlcnic_hardware_context *ahw = adapter->ahw;
625 u16 act_pci_fn = ahw->act_pci_func;
626 u16 count;
627
628 ahw->max_mc_count = QLC_83XX_MAX_MC_COUNT;
629 if (act_pci_fn <= 2)
630 count = (QLC_83XX_MAX_UC_COUNT - QLC_83XX_MAX_MC_COUNT) /
631 act_pci_fn;
632 else
633 count = (QLC_83XX_LB_MAX_FILTERS - QLC_83XX_MAX_MC_COUNT) /
634 act_pci_fn;
635 ahw->max_uc_count = count;
636 }
637
638 void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *adapter)
639 {
640 u32 val;
641
642 if (adapter->flags & QLCNIC_MSIX_ENABLED)
643 val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8);
644 else
645 val = BIT_2;
646
647 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val);
648 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
649 }
650
651 void qlcnic_83xx_check_vf(struct qlcnic_adapter *adapter,
652 const struct pci_device_id *ent)
653 {
654 u32 op_mode, priv_level;
655 struct qlcnic_hardware_context *ahw = adapter->ahw;
656
657 ahw->fw_hal_version = 2;
658 qlcnic_get_func_no(adapter);
659
660 if (qlcnic_sriov_vf_check(adapter)) {
661 qlcnic_sriov_vf_set_ops(adapter);
662 return;
663 }
664
665 /* Determine function privilege level */
666 op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE);
667 if (op_mode == QLC_83XX_DEFAULT_OPMODE)
668 priv_level = QLCNIC_MGMT_FUNC;
669 else
670 priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode,
671 ahw->pci_func);
672
673 if (priv_level == QLCNIC_NON_PRIV_FUNC) {
674 ahw->op_mode = QLCNIC_NON_PRIV_FUNC;
675 dev_info(&adapter->pdev->dev,
676 "HAL Version: %d Non Privileged function\n",
677 ahw->fw_hal_version);
678 adapter->nic_ops = &qlcnic_vf_ops;
679 } else {
680 if (pci_find_ext_capability(adapter->pdev,
681 PCI_EXT_CAP_ID_SRIOV))
682 set_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state);
683 adapter->nic_ops = &qlcnic_83xx_ops;
684 }
685 }
686
687 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
688 u32 data[]);
689 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
690 u32 data[]);
691
692 static void qlcnic_dump_mbx(struct qlcnic_adapter *adapter,
693 struct qlcnic_cmd_args *cmd)
694 {
695 int i;
696
697 dev_info(&adapter->pdev->dev,
698 "Host MBX regs(%d)\n", cmd->req.num);
699 for (i = 0; i < cmd->req.num; i++) {
700 if (i && !(i % 8))
701 pr_info("\n");
702 pr_info("%08x ", cmd->req.arg[i]);
703 }
704 pr_info("\n");
705 dev_info(&adapter->pdev->dev,
706 "FW MBX regs(%d)\n", cmd->rsp.num);
707 for (i = 0; i < cmd->rsp.num; i++) {
708 if (i && !(i % 8))
709 pr_info("\n");
710 pr_info("%08x ", cmd->rsp.arg[i]);
711 }
712 pr_info("\n");
713 }
714
715 /* Mailbox response for mac rcode */
716 u32 qlcnic_83xx_mac_rcode(struct qlcnic_adapter *adapter)
717 {
718 u32 fw_data;
719 u8 mac_cmd_rcode;
720
721 fw_data = readl(QLCNIC_MBX_FW(adapter->ahw, 2));
722 mac_cmd_rcode = (u8)fw_data;
723 if (mac_cmd_rcode == QLC_83XX_NO_NIC_RESOURCE ||
724 mac_cmd_rcode == QLC_83XX_MAC_PRESENT ||
725 mac_cmd_rcode == QLC_83XX_MAC_ABSENT)
726 return QLCNIC_RCODE_SUCCESS;
727 return 1;
728 }
729
730 u32 qlcnic_83xx_mbx_poll(struct qlcnic_adapter *adapter, u32 *wait_time)
731 {
732 u32 data;
733 struct qlcnic_hardware_context *ahw = adapter->ahw;
734 /* wait for mailbox completion */
735 do {
736 data = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL);
737 if (++(*wait_time) > QLCNIC_MBX_TIMEOUT) {
738 data = QLCNIC_RCODE_TIMEOUT;
739 break;
740 }
741 mdelay(1);
742 } while (!data);
743 return data;
744 }
745
746 int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *adapter,
747 struct qlcnic_cmd_args *cmd)
748 {
749 int i;
750 u16 opcode;
751 u8 mbx_err_code;
752 unsigned long flags;
753 struct qlcnic_hardware_context *ahw = adapter->ahw;
754 u32 rsp, mbx_val, fw_data, rsp_num, mbx_cmd, wait_time = 0;
755
756 opcode = LSW(cmd->req.arg[0]);
757 if (!test_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status)) {
758 dev_info(&adapter->pdev->dev,
759 "Mailbox cmd attempted, 0x%x\n", opcode);
760 dev_info(&adapter->pdev->dev, "Mailbox detached\n");
761 return 0;
762 }
763
764 spin_lock_irqsave(&adapter->ahw->mbx_lock, flags);
765 mbx_val = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
766
767 if (mbx_val) {
768 QLCDB(adapter, DRV,
769 "Mailbox cmd attempted, 0x%x\n", opcode);
770 QLCDB(adapter, DRV,
771 "Mailbox not available, 0x%x, collect FW dump\n",
772 mbx_val);
773 cmd->rsp.arg[0] = QLCNIC_RCODE_TIMEOUT;
774 spin_unlock_irqrestore(&adapter->ahw->mbx_lock, flags);
775 return cmd->rsp.arg[0];
776 }
777
778 /* Fill in mailbox registers */
779 mbx_cmd = cmd->req.arg[0];
780 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
781 for (i = 1; i < cmd->req.num; i++)
782 writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i));
783
784 /* Signal FW about the impending command */
785 QLCWRX(ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER);
786 poll:
787 rsp = qlcnic_83xx_mbx_poll(adapter, &wait_time);
788 if (rsp != QLCNIC_RCODE_TIMEOUT) {
789 /* Get the FW response data */
790 fw_data = readl(QLCNIC_MBX_FW(ahw, 0));
791 if (fw_data & QLCNIC_MBX_ASYNC_EVENT) {
792 __qlcnic_83xx_process_aen(adapter);
793 goto poll;
794 }
795 mbx_err_code = QLCNIC_MBX_STATUS(fw_data);
796 rsp_num = QLCNIC_MBX_NUM_REGS(fw_data);
797 opcode = QLCNIC_MBX_RSP(fw_data);
798 qlcnic_83xx_get_mbx_data(adapter, cmd);
799
800 switch (mbx_err_code) {
801 case QLCNIC_MBX_RSP_OK:
802 case QLCNIC_MBX_PORT_RSP_OK:
803 rsp = QLCNIC_RCODE_SUCCESS;
804 break;
805 default:
806 if (opcode == QLCNIC_CMD_CONFIG_MAC_VLAN) {
807 rsp = qlcnic_83xx_mac_rcode(adapter);
808 if (!rsp)
809 goto out;
810 }
811 dev_err(&adapter->pdev->dev,
812 "MBX command 0x%x failed with err:0x%x\n",
813 opcode, mbx_err_code);
814 rsp = mbx_err_code;
815 qlcnic_dump_mbx(adapter, cmd);
816 break;
817 }
818 goto out;
819 }
820
821 dev_err(&adapter->pdev->dev, "MBX command 0x%x timed out\n",
822 QLCNIC_MBX_RSP(mbx_cmd));
823 rsp = QLCNIC_RCODE_TIMEOUT;
824 out:
825 /* clear fw mbx control register */
826 QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
827 spin_unlock_irqrestore(&adapter->ahw->mbx_lock, flags);
828 return rsp;
829 }
830
831 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
832 struct qlcnic_adapter *adapter, u32 type)
833 {
834 int i, size;
835 u32 temp;
836 const struct qlcnic_mailbox_metadata *mbx_tbl;
837
838 memset(mbx, 0, sizeof(struct qlcnic_cmd_args));
839 mbx_tbl = qlcnic_83xx_mbx_tbl;
840 size = ARRAY_SIZE(qlcnic_83xx_mbx_tbl);
841 for (i = 0; i < size; i++) {
842 if (type == mbx_tbl[i].cmd) {
843 mbx->op_type = QLC_83XX_FW_MBX_CMD;
844 mbx->req.num = mbx_tbl[i].in_args;
845 mbx->rsp.num = mbx_tbl[i].out_args;
846 mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
847 GFP_ATOMIC);
848 if (!mbx->req.arg)
849 return -ENOMEM;
850 mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
851 GFP_ATOMIC);
852 if (!mbx->rsp.arg) {
853 kfree(mbx->req.arg);
854 mbx->req.arg = NULL;
855 return -ENOMEM;
856 }
857 memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
858 memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
859 temp = adapter->ahw->fw_hal_version << 29;
860 mbx->req.arg[0] = (type | (mbx->req.num << 16) | temp);
861 return 0;
862 }
863 }
864 return -EINVAL;
865 }
866
867 void qlcnic_83xx_idc_aen_work(struct work_struct *work)
868 {
869 struct qlcnic_adapter *adapter;
870 struct qlcnic_cmd_args cmd;
871 int i, err = 0;
872
873 adapter = container_of(work, struct qlcnic_adapter, idc_aen_work.work);
874 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_IDC_ACK);
875 if (err)
876 return;
877
878 for (i = 1; i < QLC_83XX_MBX_AEN_CNT; i++)
879 cmd.req.arg[i] = adapter->ahw->mbox_aen[i];
880
881 err = qlcnic_issue_cmd(adapter, &cmd);
882 if (err)
883 dev_info(&adapter->pdev->dev,
884 "%s: Mailbox IDC ACK failed.\n", __func__);
885 qlcnic_free_mbx_args(&cmd);
886 }
887
888 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
889 u32 data[])
890 {
891 dev_dbg(&adapter->pdev->dev, "Completion AEN:0x%x.\n",
892 QLCNIC_MBX_RSP(data[0]));
893 clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status);
894 return;
895 }
896
897 void __qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
898 {
899 u32 event[QLC_83XX_MBX_AEN_CNT];
900 int i;
901 struct qlcnic_hardware_context *ahw = adapter->ahw;
902
903 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
904 event[i] = readl(QLCNIC_MBX_FW(ahw, i));
905
906 switch (QLCNIC_MBX_RSP(event[0])) {
907
908 case QLCNIC_MBX_LINK_EVENT:
909 qlcnic_83xx_handle_link_aen(adapter, event);
910 break;
911 case QLCNIC_MBX_COMP_EVENT:
912 qlcnic_83xx_handle_idc_comp_aen(adapter, event);
913 break;
914 case QLCNIC_MBX_REQUEST_EVENT:
915 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
916 adapter->ahw->mbox_aen[i] = QLCNIC_MBX_RSP(event[i]);
917 queue_delayed_work(adapter->qlcnic_wq,
918 &adapter->idc_aen_work, 0);
919 break;
920 case QLCNIC_MBX_TIME_EXTEND_EVENT:
921 break;
922 case QLCNIC_MBX_BC_EVENT:
923 qlcnic_sriov_handle_bc_event(adapter, event[1]);
924 break;
925 case QLCNIC_MBX_SFP_INSERT_EVENT:
926 dev_info(&adapter->pdev->dev, "SFP+ Insert AEN:0x%x.\n",
927 QLCNIC_MBX_RSP(event[0]));
928 break;
929 case QLCNIC_MBX_SFP_REMOVE_EVENT:
930 dev_info(&adapter->pdev->dev, "SFP Removed AEN:0x%x.\n",
931 QLCNIC_MBX_RSP(event[0]));
932 break;
933 default:
934 dev_dbg(&adapter->pdev->dev, "Unsupported AEN:0x%x.\n",
935 QLCNIC_MBX_RSP(event[0]));
936 break;
937 }
938
939 QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
940 }
941
942 static void qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
943 {
944 struct qlcnic_hardware_context *ahw = adapter->ahw;
945 u32 resp, event;
946 unsigned long flags;
947
948 spin_lock_irqsave(&ahw->mbx_lock, flags);
949
950 resp = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL);
951 if (resp & QLCNIC_SET_OWNER) {
952 event = readl(QLCNIC_MBX_FW(ahw, 0));
953 if (event & QLCNIC_MBX_ASYNC_EVENT)
954 __qlcnic_83xx_process_aen(adapter);
955 }
956
957 spin_unlock_irqrestore(&ahw->mbx_lock, flags);
958 }
959
960 static void qlcnic_83xx_mbx_poll_work(struct work_struct *work)
961 {
962 struct qlcnic_adapter *adapter;
963
964 adapter = container_of(work, struct qlcnic_adapter, mbx_poll_work.work);
965
966 if (!test_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
967 return;
968
969 qlcnic_83xx_process_aen(adapter);
970 queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work,
971 (HZ / 10));
972 }
973
974 void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *adapter)
975 {
976 if (test_and_set_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
977 return;
978
979 INIT_DELAYED_WORK(&adapter->mbx_poll_work, qlcnic_83xx_mbx_poll_work);
980 }
981
982 void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *adapter)
983 {
984 if (!test_and_clear_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
985 return;
986 cancel_delayed_work_sync(&adapter->mbx_poll_work);
987 }
988
989 static int qlcnic_83xx_add_rings(struct qlcnic_adapter *adapter)
990 {
991 int index, i, err, sds_mbx_size;
992 u32 *buf, intrpt_id, intr_mask;
993 u16 context_id;
994 u8 num_sds;
995 struct qlcnic_cmd_args cmd;
996 struct qlcnic_host_sds_ring *sds;
997 struct qlcnic_sds_mbx sds_mbx;
998 struct qlcnic_add_rings_mbx_out *mbx_out;
999 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1000 struct qlcnic_hardware_context *ahw = adapter->ahw;
1001
1002 sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1003 context_id = recv_ctx->context_id;
1004 num_sds = (adapter->max_sds_rings - QLCNIC_MAX_RING_SETS);
1005 ahw->hw_ops->alloc_mbx_args(&cmd, adapter,
1006 QLCNIC_CMD_ADD_RCV_RINGS);
1007 cmd.req.arg[1] = 0 | (num_sds << 8) | (context_id << 16);
1008
1009 /* set up status rings, mbx 2-81 */
1010 index = 2;
1011 for (i = 8; i < adapter->max_sds_rings; i++) {
1012 memset(&sds_mbx, 0, sds_mbx_size);
1013 sds = &recv_ctx->sds_rings[i];
1014 sds->consumer = 0;
1015 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1016 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1017 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1018 sds_mbx.sds_ring_size = sds->num_desc;
1019
1020 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1021 intrpt_id = ahw->intr_tbl[i].id;
1022 else
1023 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1024
1025 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1026 sds_mbx.intrpt_id = intrpt_id;
1027 else
1028 sds_mbx.intrpt_id = 0xffff;
1029 sds_mbx.intrpt_val = 0;
1030 buf = &cmd.req.arg[index];
1031 memcpy(buf, &sds_mbx, sds_mbx_size);
1032 index += sds_mbx_size / sizeof(u32);
1033 }
1034
1035 /* send the mailbox command */
1036 err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1037 if (err) {
1038 dev_err(&adapter->pdev->dev,
1039 "Failed to add rings %d\n", err);
1040 goto out;
1041 }
1042
1043 mbx_out = (struct qlcnic_add_rings_mbx_out *)&cmd.rsp.arg[1];
1044 index = 0;
1045 /* status descriptor ring */
1046 for (i = 8; i < adapter->max_sds_rings; i++) {
1047 sds = &recv_ctx->sds_rings[i];
1048 sds->crb_sts_consumer = ahw->pci_base0 +
1049 mbx_out->host_csmr[index];
1050 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1051 intr_mask = ahw->intr_tbl[i].src;
1052 else
1053 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1054
1055 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1056 index++;
1057 }
1058 out:
1059 qlcnic_free_mbx_args(&cmd);
1060 return err;
1061 }
1062
1063 void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *adapter)
1064 {
1065 int err;
1066 u32 temp = 0;
1067 struct qlcnic_cmd_args cmd;
1068 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1069
1070 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX))
1071 return;
1072
1073 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1074 cmd.req.arg[0] |= (0x3 << 29);
1075
1076 if (qlcnic_sriov_pf_check(adapter))
1077 qlcnic_pf_set_interface_id_del_rx_ctx(adapter, &temp);
1078
1079 cmd.req.arg[1] = recv_ctx->context_id | temp;
1080 err = qlcnic_issue_cmd(adapter, &cmd);
1081 if (err)
1082 dev_err(&adapter->pdev->dev,
1083 "Failed to destroy rx ctx in firmware\n");
1084
1085 recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
1086 qlcnic_free_mbx_args(&cmd);
1087 }
1088
1089 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter)
1090 {
1091 int i, err, index, sds_mbx_size, rds_mbx_size;
1092 u8 num_sds, num_rds;
1093 u32 *buf, intrpt_id, intr_mask, cap = 0;
1094 struct qlcnic_host_sds_ring *sds;
1095 struct qlcnic_host_rds_ring *rds;
1096 struct qlcnic_sds_mbx sds_mbx;
1097 struct qlcnic_rds_mbx rds_mbx;
1098 struct qlcnic_cmd_args cmd;
1099 struct qlcnic_rcv_mbx_out *mbx_out;
1100 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1101 struct qlcnic_hardware_context *ahw = adapter->ahw;
1102 num_rds = adapter->max_rds_rings;
1103
1104 if (adapter->max_sds_rings <= QLCNIC_MAX_RING_SETS)
1105 num_sds = adapter->max_sds_rings;
1106 else
1107 num_sds = QLCNIC_MAX_RING_SETS;
1108
1109 sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1110 rds_mbx_size = sizeof(struct qlcnic_rds_mbx);
1111 cap = QLCNIC_CAP0_LEGACY_CONTEXT;
1112
1113 if (adapter->flags & QLCNIC_FW_LRO_MSS_CAP)
1114 cap |= QLC_83XX_FW_CAP_LRO_MSS;
1115
1116 /* set mailbox hdr and capabilities */
1117 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1118 QLCNIC_CMD_CREATE_RX_CTX);
1119 if (err)
1120 return err;
1121
1122 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1123 cmd.req.arg[0] |= (0x3 << 29);
1124
1125 cmd.req.arg[1] = cap;
1126 cmd.req.arg[5] = 1 | (num_rds << 5) | (num_sds << 8) |
1127 (QLC_83XX_HOST_RDS_MODE_UNIQUE << 16);
1128
1129 if (qlcnic_sriov_pf_check(adapter))
1130 qlcnic_pf_set_interface_id_create_rx_ctx(adapter,
1131 &cmd.req.arg[6]);
1132 /* set up status rings, mbx 8-57/87 */
1133 index = QLC_83XX_HOST_SDS_MBX_IDX;
1134 for (i = 0; i < num_sds; i++) {
1135 memset(&sds_mbx, 0, sds_mbx_size);
1136 sds = &recv_ctx->sds_rings[i];
1137 sds->consumer = 0;
1138 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1139 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1140 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1141 sds_mbx.sds_ring_size = sds->num_desc;
1142 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1143 intrpt_id = ahw->intr_tbl[i].id;
1144 else
1145 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1146 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1147 sds_mbx.intrpt_id = intrpt_id;
1148 else
1149 sds_mbx.intrpt_id = 0xffff;
1150 sds_mbx.intrpt_val = 0;
1151 buf = &cmd.req.arg[index];
1152 memcpy(buf, &sds_mbx, sds_mbx_size);
1153 index += sds_mbx_size / sizeof(u32);
1154 }
1155 /* set up receive rings, mbx 88-111/135 */
1156 index = QLCNIC_HOST_RDS_MBX_IDX;
1157 rds = &recv_ctx->rds_rings[0];
1158 rds->producer = 0;
1159 memset(&rds_mbx, 0, rds_mbx_size);
1160 rds_mbx.phy_addr_reg_low = LSD(rds->phys_addr);
1161 rds_mbx.phy_addr_reg_high = MSD(rds->phys_addr);
1162 rds_mbx.reg_ring_sz = rds->dma_size;
1163 rds_mbx.reg_ring_len = rds->num_desc;
1164 /* Jumbo ring */
1165 rds = &recv_ctx->rds_rings[1];
1166 rds->producer = 0;
1167 rds_mbx.phy_addr_jmb_low = LSD(rds->phys_addr);
1168 rds_mbx.phy_addr_jmb_high = MSD(rds->phys_addr);
1169 rds_mbx.jmb_ring_sz = rds->dma_size;
1170 rds_mbx.jmb_ring_len = rds->num_desc;
1171 buf = &cmd.req.arg[index];
1172 memcpy(buf, &rds_mbx, rds_mbx_size);
1173
1174 /* send the mailbox command */
1175 err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1176 if (err) {
1177 dev_err(&adapter->pdev->dev,
1178 "Failed to create Rx ctx in firmware%d\n", err);
1179 goto out;
1180 }
1181 mbx_out = (struct qlcnic_rcv_mbx_out *)&cmd.rsp.arg[1];
1182 recv_ctx->context_id = mbx_out->ctx_id;
1183 recv_ctx->state = mbx_out->state;
1184 recv_ctx->virt_port = mbx_out->vport_id;
1185 dev_info(&adapter->pdev->dev, "Rx Context[%d] Created, state:0x%x\n",
1186 recv_ctx->context_id, recv_ctx->state);
1187 /* Receive descriptor ring */
1188 /* Standard ring */
1189 rds = &recv_ctx->rds_rings[0];
1190 rds->crb_rcv_producer = ahw->pci_base0 +
1191 mbx_out->host_prod[0].reg_buf;
1192 /* Jumbo ring */
1193 rds = &recv_ctx->rds_rings[1];
1194 rds->crb_rcv_producer = ahw->pci_base0 +
1195 mbx_out->host_prod[0].jmb_buf;
1196 /* status descriptor ring */
1197 for (i = 0; i < num_sds; i++) {
1198 sds = &recv_ctx->sds_rings[i];
1199 sds->crb_sts_consumer = ahw->pci_base0 +
1200 mbx_out->host_csmr[i];
1201 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1202 intr_mask = ahw->intr_tbl[i].src;
1203 else
1204 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1205 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1206 }
1207
1208 if (adapter->max_sds_rings > QLCNIC_MAX_RING_SETS)
1209 err = qlcnic_83xx_add_rings(adapter);
1210 out:
1211 qlcnic_free_mbx_args(&cmd);
1212 return err;
1213 }
1214
1215 void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *adapter,
1216 struct qlcnic_host_tx_ring *tx_ring)
1217 {
1218 struct qlcnic_cmd_args cmd;
1219 u32 temp = 0;
1220
1221 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX))
1222 return;
1223
1224 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1225 cmd.req.arg[0] |= (0x3 << 29);
1226
1227 if (qlcnic_sriov_pf_check(adapter))
1228 qlcnic_pf_set_interface_id_del_tx_ctx(adapter, &temp);
1229
1230 cmd.req.arg[1] = tx_ring->ctx_id | temp;
1231 if (qlcnic_issue_cmd(adapter, &cmd))
1232 dev_err(&adapter->pdev->dev,
1233 "Failed to destroy tx ctx in firmware\n");
1234 qlcnic_free_mbx_args(&cmd);
1235 }
1236
1237 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *adapter,
1238 struct qlcnic_host_tx_ring *tx, int ring)
1239 {
1240 int err;
1241 u16 msix_id;
1242 u32 *buf, intr_mask, temp = 0;
1243 struct qlcnic_cmd_args cmd;
1244 struct qlcnic_tx_mbx mbx;
1245 struct qlcnic_tx_mbx_out *mbx_out;
1246 struct qlcnic_hardware_context *ahw = adapter->ahw;
1247 u32 msix_vector;
1248
1249 /* Reset host resources */
1250 tx->producer = 0;
1251 tx->sw_consumer = 0;
1252 *(tx->hw_consumer) = 0;
1253
1254 memset(&mbx, 0, sizeof(struct qlcnic_tx_mbx));
1255
1256 /* setup mailbox inbox registerss */
1257 mbx.phys_addr_low = LSD(tx->phys_addr);
1258 mbx.phys_addr_high = MSD(tx->phys_addr);
1259 mbx.cnsmr_index_low = LSD(tx->hw_cons_phys_addr);
1260 mbx.cnsmr_index_high = MSD(tx->hw_cons_phys_addr);
1261 mbx.size = tx->num_desc;
1262 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
1263 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
1264 msix_vector = adapter->max_sds_rings + ring;
1265 else
1266 msix_vector = adapter->max_sds_rings - 1;
1267 msix_id = ahw->intr_tbl[msix_vector].id;
1268 } else {
1269 msix_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1270 }
1271
1272 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1273 mbx.intr_id = msix_id;
1274 else
1275 mbx.intr_id = 0xffff;
1276 mbx.src = 0;
1277
1278 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
1279 if (err)
1280 return err;
1281
1282 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1283 cmd.req.arg[0] |= (0x3 << 29);
1284
1285 if (qlcnic_sriov_pf_check(adapter))
1286 qlcnic_pf_set_interface_id_create_tx_ctx(adapter, &temp);
1287
1288 cmd.req.arg[1] = QLCNIC_CAP0_LEGACY_CONTEXT;
1289 cmd.req.arg[5] = QLCNIC_MAX_TX_QUEUES | temp;
1290 buf = &cmd.req.arg[6];
1291 memcpy(buf, &mbx, sizeof(struct qlcnic_tx_mbx));
1292 /* send the mailbox command*/
1293 err = qlcnic_issue_cmd(adapter, &cmd);
1294 if (err) {
1295 dev_err(&adapter->pdev->dev,
1296 "Failed to create Tx ctx in firmware 0x%x\n", err);
1297 goto out;
1298 }
1299 mbx_out = (struct qlcnic_tx_mbx_out *)&cmd.rsp.arg[2];
1300 tx->crb_cmd_producer = ahw->pci_base0 + mbx_out->host_prod;
1301 tx->ctx_id = mbx_out->ctx_id;
1302 if ((adapter->flags & QLCNIC_MSIX_ENABLED) &&
1303 !(adapter->flags & QLCNIC_TX_INTR_SHARED)) {
1304 intr_mask = ahw->intr_tbl[adapter->max_sds_rings + ring].src;
1305 tx->crb_intr_mask = ahw->pci_base0 + intr_mask;
1306 }
1307 dev_info(&adapter->pdev->dev, "Tx Context[0x%x] Created, state:0x%x\n",
1308 tx->ctx_id, mbx_out->state);
1309 out:
1310 qlcnic_free_mbx_args(&cmd);
1311 return err;
1312 }
1313
1314 static int qlcnic_83xx_diag_alloc_res(struct net_device *netdev, int test,
1315 int num_sds_ring)
1316 {
1317 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1318 struct qlcnic_host_sds_ring *sds_ring;
1319 struct qlcnic_host_rds_ring *rds_ring;
1320 u16 adapter_state = adapter->is_up;
1321 u8 ring;
1322 int ret;
1323
1324 netif_device_detach(netdev);
1325
1326 if (netif_running(netdev))
1327 __qlcnic_down(adapter, netdev);
1328
1329 qlcnic_detach(adapter);
1330
1331 adapter->max_sds_rings = 1;
1332 adapter->ahw->diag_test = test;
1333 adapter->ahw->linkup = 0;
1334
1335 ret = qlcnic_attach(adapter);
1336 if (ret) {
1337 netif_device_attach(netdev);
1338 return ret;
1339 }
1340
1341 ret = qlcnic_fw_create_ctx(adapter);
1342 if (ret) {
1343 qlcnic_detach(adapter);
1344 if (adapter_state == QLCNIC_ADAPTER_UP_MAGIC) {
1345 adapter->max_sds_rings = num_sds_ring;
1346 qlcnic_attach(adapter);
1347 }
1348 netif_device_attach(netdev);
1349 return ret;
1350 }
1351
1352 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1353 rds_ring = &adapter->recv_ctx->rds_rings[ring];
1354 qlcnic_post_rx_buffers(adapter, rds_ring, ring);
1355 }
1356
1357 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1358 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
1359 sds_ring = &adapter->recv_ctx->sds_rings[ring];
1360 qlcnic_83xx_enable_intr(adapter, sds_ring);
1361 }
1362 }
1363
1364 if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1365 /* disable and free mailbox interrupt */
1366 if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
1367 qlcnic_83xx_free_mbx_intr(adapter);
1368 adapter->ahw->loopback_state = 0;
1369 adapter->ahw->hw_ops->setup_link_event(adapter, 1);
1370 }
1371
1372 set_bit(__QLCNIC_DEV_UP, &adapter->state);
1373 return 0;
1374 }
1375
1376 static void qlcnic_83xx_diag_free_res(struct net_device *netdev,
1377 int max_sds_rings)
1378 {
1379 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1380 struct qlcnic_host_sds_ring *sds_ring;
1381 int ring, err;
1382
1383 clear_bit(__QLCNIC_DEV_UP, &adapter->state);
1384 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1385 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
1386 sds_ring = &adapter->recv_ctx->sds_rings[ring];
1387 qlcnic_83xx_disable_intr(adapter, sds_ring);
1388 }
1389 }
1390
1391 qlcnic_fw_destroy_ctx(adapter);
1392 qlcnic_detach(adapter);
1393
1394 if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1395 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
1396 err = qlcnic_83xx_setup_mbx_intr(adapter);
1397 if (err) {
1398 dev_err(&adapter->pdev->dev,
1399 "%s: failed to setup mbx interrupt\n",
1400 __func__);
1401 goto out;
1402 }
1403 }
1404 }
1405 adapter->ahw->diag_test = 0;
1406 adapter->max_sds_rings = max_sds_rings;
1407
1408 if (qlcnic_attach(adapter))
1409 goto out;
1410
1411 if (netif_running(netdev))
1412 __qlcnic_up(adapter, netdev);
1413 out:
1414 netif_device_attach(netdev);
1415 }
1416
1417 int qlcnic_83xx_config_led(struct qlcnic_adapter *adapter, u32 state,
1418 u32 beacon)
1419 {
1420 struct qlcnic_cmd_args cmd;
1421 u32 mbx_in;
1422 int i, status = 0;
1423
1424 if (state) {
1425 /* Get LED configuration */
1426 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1427 QLCNIC_CMD_GET_LED_CONFIG);
1428 if (status)
1429 return status;
1430
1431 status = qlcnic_issue_cmd(adapter, &cmd);
1432 if (status) {
1433 dev_err(&adapter->pdev->dev,
1434 "Get led config failed.\n");
1435 goto mbx_err;
1436 } else {
1437 for (i = 0; i < 4; i++)
1438 adapter->ahw->mbox_reg[i] = cmd.rsp.arg[i+1];
1439 }
1440 qlcnic_free_mbx_args(&cmd);
1441 /* Set LED Configuration */
1442 mbx_in = (LSW(QLC_83XX_LED_CONFIG) << 16) |
1443 LSW(QLC_83XX_LED_CONFIG);
1444 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1445 QLCNIC_CMD_SET_LED_CONFIG);
1446 if (status)
1447 return status;
1448
1449 cmd.req.arg[1] = mbx_in;
1450 cmd.req.arg[2] = mbx_in;
1451 cmd.req.arg[3] = mbx_in;
1452 if (beacon)
1453 cmd.req.arg[4] = QLC_83XX_ENABLE_BEACON;
1454 status = qlcnic_issue_cmd(adapter, &cmd);
1455 if (status) {
1456 dev_err(&adapter->pdev->dev,
1457 "Set led config failed.\n");
1458 }
1459 mbx_err:
1460 qlcnic_free_mbx_args(&cmd);
1461 return status;
1462
1463 } else {
1464 /* Restoring default LED configuration */
1465 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1466 QLCNIC_CMD_SET_LED_CONFIG);
1467 if (status)
1468 return status;
1469
1470 cmd.req.arg[1] = adapter->ahw->mbox_reg[0];
1471 cmd.req.arg[2] = adapter->ahw->mbox_reg[1];
1472 cmd.req.arg[3] = adapter->ahw->mbox_reg[2];
1473 if (beacon)
1474 cmd.req.arg[4] = adapter->ahw->mbox_reg[3];
1475 status = qlcnic_issue_cmd(adapter, &cmd);
1476 if (status)
1477 dev_err(&adapter->pdev->dev,
1478 "Restoring led config failed.\n");
1479 qlcnic_free_mbx_args(&cmd);
1480 return status;
1481 }
1482 }
1483
1484 int qlcnic_83xx_set_led(struct net_device *netdev,
1485 enum ethtool_phys_id_state state)
1486 {
1487 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1488 int err = -EIO, active = 1;
1489
1490 if (adapter->ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1491 netdev_warn(netdev,
1492 "LED test is not supported in non-privileged mode\n");
1493 return -EOPNOTSUPP;
1494 }
1495
1496 switch (state) {
1497 case ETHTOOL_ID_ACTIVE:
1498 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state))
1499 return -EBUSY;
1500
1501 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1502 break;
1503
1504 err = qlcnic_83xx_config_led(adapter, active, 0);
1505 if (err)
1506 netdev_err(netdev, "Failed to set LED blink state\n");
1507 break;
1508 case ETHTOOL_ID_INACTIVE:
1509 active = 0;
1510
1511 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1512 break;
1513
1514 err = qlcnic_83xx_config_led(adapter, active, 0);
1515 if (err)
1516 netdev_err(netdev, "Failed to reset LED blink state\n");
1517 break;
1518
1519 default:
1520 return -EINVAL;
1521 }
1522
1523 if (!active || err)
1524 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state);
1525
1526 return err;
1527 }
1528
1529 void qlcnic_83xx_register_nic_idc_func(struct qlcnic_adapter *adapter,
1530 int enable)
1531 {
1532 struct qlcnic_cmd_args cmd;
1533 int status;
1534
1535 if (qlcnic_sriov_vf_check(adapter))
1536 return;
1537
1538 if (enable) {
1539 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1540 QLCNIC_CMD_INIT_NIC_FUNC);
1541 if (status)
1542 return;
1543
1544 cmd.req.arg[1] = BIT_0 | BIT_31;
1545 } else {
1546 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1547 QLCNIC_CMD_STOP_NIC_FUNC);
1548 if (status)
1549 return;
1550
1551 cmd.req.arg[1] = BIT_0 | BIT_31;
1552 }
1553 status = qlcnic_issue_cmd(adapter, &cmd);
1554 if (status)
1555 dev_err(&adapter->pdev->dev,
1556 "Failed to %s in NIC IDC function event.\n",
1557 (enable ? "register" : "unregister"));
1558
1559 qlcnic_free_mbx_args(&cmd);
1560 }
1561
1562 int qlcnic_83xx_set_port_config(struct qlcnic_adapter *adapter)
1563 {
1564 struct qlcnic_cmd_args cmd;
1565 int err;
1566
1567 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_PORT_CONFIG);
1568 if (err)
1569 return err;
1570
1571 cmd.req.arg[1] = adapter->ahw->port_config;
1572 err = qlcnic_issue_cmd(adapter, &cmd);
1573 if (err)
1574 dev_info(&adapter->pdev->dev, "Set Port Config failed.\n");
1575 qlcnic_free_mbx_args(&cmd);
1576 return err;
1577 }
1578
1579 int qlcnic_83xx_get_port_config(struct qlcnic_adapter *adapter)
1580 {
1581 struct qlcnic_cmd_args cmd;
1582 int err;
1583
1584 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PORT_CONFIG);
1585 if (err)
1586 return err;
1587
1588 err = qlcnic_issue_cmd(adapter, &cmd);
1589 if (err)
1590 dev_info(&adapter->pdev->dev, "Get Port config failed\n");
1591 else
1592 adapter->ahw->port_config = cmd.rsp.arg[1];
1593 qlcnic_free_mbx_args(&cmd);
1594 return err;
1595 }
1596
1597 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *adapter, int enable)
1598 {
1599 int err;
1600 u32 temp;
1601 struct qlcnic_cmd_args cmd;
1602
1603 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_EVENT);
1604 if (err)
1605 return err;
1606
1607 temp = adapter->recv_ctx->context_id << 16;
1608 cmd.req.arg[1] = (enable ? 1 : 0) | BIT_8 | temp;
1609 err = qlcnic_issue_cmd(adapter, &cmd);
1610 if (err)
1611 dev_info(&adapter->pdev->dev,
1612 "Setup linkevent mailbox failed\n");
1613 qlcnic_free_mbx_args(&cmd);
1614 return err;
1615 }
1616
1617 static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter *adapter,
1618 u32 *interface_id)
1619 {
1620 if (qlcnic_sriov_pf_check(adapter)) {
1621 qlcnic_pf_set_interface_id_promisc(adapter, interface_id);
1622 } else {
1623 if (!qlcnic_sriov_vf_check(adapter))
1624 *interface_id = adapter->recv_ctx->context_id << 16;
1625 }
1626 }
1627
1628 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
1629 {
1630 int err;
1631 u32 temp = 0;
1632 struct qlcnic_cmd_args cmd;
1633
1634 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1635 return -EIO;
1636
1637 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1638 QLCNIC_CMD_CONFIGURE_MAC_RX_MODE);
1639 if (err)
1640 return err;
1641
1642 qlcnic_83xx_set_interface_id_promisc(adapter, &temp);
1643 cmd.req.arg[1] = (mode ? 1 : 0) | temp;
1644 err = qlcnic_issue_cmd(adapter, &cmd);
1645 if (err)
1646 dev_info(&adapter->pdev->dev,
1647 "Promiscous mode config failed\n");
1648
1649 qlcnic_free_mbx_args(&cmd);
1650 return err;
1651 }
1652
1653 int qlcnic_83xx_loopback_test(struct net_device *netdev, u8 mode)
1654 {
1655 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1656 struct qlcnic_hardware_context *ahw = adapter->ahw;
1657 int ret = 0, loop = 0, max_sds_rings = adapter->max_sds_rings;
1658
1659 if (ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1660 netdev_warn(netdev,
1661 "Loopback test not supported in non privileged mode\n");
1662 return -ENOTSUPP;
1663 }
1664
1665 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1666 netdev_info(netdev, "Device is resetting\n");
1667 return -EBUSY;
1668 }
1669
1670 if (qlcnic_get_diag_lock(adapter)) {
1671 netdev_info(netdev, "Device is in diagnostics mode\n");
1672 return -EBUSY;
1673 }
1674
1675 netdev_info(netdev, "%s loopback test in progress\n",
1676 mode == QLCNIC_ILB_MODE ? "internal" : "external");
1677
1678 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST,
1679 max_sds_rings);
1680 if (ret)
1681 goto fail_diag_alloc;
1682
1683 ret = qlcnic_83xx_set_lb_mode(adapter, mode);
1684 if (ret)
1685 goto free_diag_res;
1686
1687 /* Poll for link up event before running traffic */
1688 do {
1689 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1690 if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
1691 qlcnic_83xx_process_aen(adapter);
1692
1693 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1694 netdev_info(netdev,
1695 "Device is resetting, free LB test resources\n");
1696 ret = -EBUSY;
1697 goto free_diag_res;
1698 }
1699 if (loop++ > QLC_83XX_LB_WAIT_COUNT) {
1700 netdev_info(netdev,
1701 "Firmware didn't sent link up event to loopback request\n");
1702 ret = -ETIMEDOUT;
1703 qlcnic_83xx_clear_lb_mode(adapter, mode);
1704 goto free_diag_res;
1705 }
1706 } while ((adapter->ahw->linkup && ahw->has_link_events) != 1);
1707
1708 /* Make sure carrier is off and queue is stopped during loopback */
1709 if (netif_running(netdev)) {
1710 netif_carrier_off(netdev);
1711 netif_stop_queue(netdev);
1712 }
1713
1714 ret = qlcnic_do_lb_test(adapter, mode);
1715
1716 qlcnic_83xx_clear_lb_mode(adapter, mode);
1717
1718 free_diag_res:
1719 qlcnic_83xx_diag_free_res(netdev, max_sds_rings);
1720
1721 fail_diag_alloc:
1722 adapter->max_sds_rings = max_sds_rings;
1723 qlcnic_release_diag_lock(adapter);
1724 return ret;
1725 }
1726
1727 int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1728 {
1729 struct qlcnic_hardware_context *ahw = adapter->ahw;
1730 struct net_device *netdev = adapter->netdev;
1731 int status = 0, loop = 0;
1732 u32 config;
1733
1734 status = qlcnic_83xx_get_port_config(adapter);
1735 if (status)
1736 return status;
1737
1738 config = ahw->port_config;
1739
1740 /* Check if port is already in loopback mode */
1741 if ((config & QLC_83XX_CFG_LOOPBACK_HSS) ||
1742 (config & QLC_83XX_CFG_LOOPBACK_EXT)) {
1743 netdev_err(netdev,
1744 "Port already in Loopback mode.\n");
1745 return -EINPROGRESS;
1746 }
1747
1748 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1749
1750 if (mode == QLCNIC_ILB_MODE)
1751 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_HSS;
1752 if (mode == QLCNIC_ELB_MODE)
1753 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_EXT;
1754
1755 status = qlcnic_83xx_set_port_config(adapter);
1756 if (status) {
1757 netdev_err(netdev,
1758 "Failed to Set Loopback Mode = 0x%x.\n",
1759 ahw->port_config);
1760 ahw->port_config = config;
1761 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1762 return status;
1763 }
1764
1765 /* Wait for Link and IDC Completion AEN */
1766 do {
1767 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1768 if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
1769 qlcnic_83xx_process_aen(adapter);
1770
1771 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1772 netdev_info(netdev,
1773 "Device is resetting, free LB test resources\n");
1774 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1775 return -EBUSY;
1776 }
1777 if (loop++ > QLC_83XX_LB_WAIT_COUNT) {
1778 netdev_err(netdev,
1779 "Did not receive IDC completion AEN\n");
1780 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1781 qlcnic_83xx_clear_lb_mode(adapter, mode);
1782 return -ETIMEDOUT;
1783 }
1784 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1785
1786 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1787 QLCNIC_MAC_ADD);
1788 return status;
1789 }
1790
1791 int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1792 {
1793 struct qlcnic_hardware_context *ahw = adapter->ahw;
1794 struct net_device *netdev = adapter->netdev;
1795 int status = 0, loop = 0;
1796 u32 config = ahw->port_config;
1797
1798 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1799 if (mode == QLCNIC_ILB_MODE)
1800 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_HSS;
1801 if (mode == QLCNIC_ELB_MODE)
1802 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_EXT;
1803
1804 status = qlcnic_83xx_set_port_config(adapter);
1805 if (status) {
1806 netdev_err(netdev,
1807 "Failed to Clear Loopback Mode = 0x%x.\n",
1808 ahw->port_config);
1809 ahw->port_config = config;
1810 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1811 return status;
1812 }
1813
1814 /* Wait for Link and IDC Completion AEN */
1815 do {
1816 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1817 if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
1818 qlcnic_83xx_process_aen(adapter);
1819
1820 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1821 netdev_info(netdev,
1822 "Device is resetting, free LB test resources\n");
1823 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1824 return -EBUSY;
1825 }
1826
1827 if (loop++ > QLC_83XX_LB_WAIT_COUNT) {
1828 netdev_err(netdev,
1829 "Did not receive IDC completion AEN\n");
1830 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1831 return -ETIMEDOUT;
1832 }
1833 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1834
1835 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1836 QLCNIC_MAC_DEL);
1837 return status;
1838 }
1839
1840 static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter *adapter,
1841 u32 *interface_id)
1842 {
1843 if (qlcnic_sriov_pf_check(adapter)) {
1844 qlcnic_pf_set_interface_id_ipaddr(adapter, interface_id);
1845 } else {
1846 if (!qlcnic_sriov_vf_check(adapter))
1847 *interface_id = adapter->recv_ctx->context_id << 16;
1848 }
1849 }
1850
1851 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip,
1852 int mode)
1853 {
1854 int err;
1855 u32 temp = 0, temp_ip;
1856 struct qlcnic_cmd_args cmd;
1857
1858 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1859 QLCNIC_CMD_CONFIGURE_IP_ADDR);
1860 if (err)
1861 return;
1862
1863 qlcnic_83xx_set_interface_id_ipaddr(adapter, &temp);
1864
1865 if (mode == QLCNIC_IP_UP)
1866 cmd.req.arg[1] = 1 | temp;
1867 else
1868 cmd.req.arg[1] = 2 | temp;
1869
1870 /*
1871 * Adapter needs IP address in network byte order.
1872 * But hardware mailbox registers go through writel(), hence IP address
1873 * gets swapped on big endian architecture.
1874 * To negate swapping of writel() on big endian architecture
1875 * use swab32(value).
1876 */
1877
1878 temp_ip = swab32(ntohl(ip));
1879 memcpy(&cmd.req.arg[2], &temp_ip, sizeof(u32));
1880 err = qlcnic_issue_cmd(adapter, &cmd);
1881 if (err != QLCNIC_RCODE_SUCCESS)
1882 dev_err(&adapter->netdev->dev,
1883 "could not notify %s IP 0x%x request\n",
1884 (mode == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
1885
1886 qlcnic_free_mbx_args(&cmd);
1887 }
1888
1889 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *adapter, int mode)
1890 {
1891 int err;
1892 u32 temp, arg1;
1893 struct qlcnic_cmd_args cmd;
1894 int lro_bit_mask;
1895
1896 lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0);
1897
1898 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1899 return 0;
1900
1901 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_HW_LRO);
1902 if (err)
1903 return err;
1904
1905 temp = adapter->recv_ctx->context_id << 16;
1906 arg1 = lro_bit_mask | temp;
1907 cmd.req.arg[1] = arg1;
1908
1909 err = qlcnic_issue_cmd(adapter, &cmd);
1910 if (err)
1911 dev_info(&adapter->pdev->dev, "LRO config failed\n");
1912 qlcnic_free_mbx_args(&cmd);
1913
1914 return err;
1915 }
1916
1917 int qlcnic_83xx_config_rss(struct qlcnic_adapter *adapter, int enable)
1918 {
1919 int err;
1920 u32 word;
1921 struct qlcnic_cmd_args cmd;
1922 const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
1923 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
1924 0x255b0ec26d5a56daULL };
1925
1926 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_RSS);
1927 if (err)
1928 return err;
1929 /*
1930 * RSS request:
1931 * bits 3-0: Rsvd
1932 * 5-4: hash_type_ipv4
1933 * 7-6: hash_type_ipv6
1934 * 8: enable
1935 * 9: use indirection table
1936 * 16-31: indirection table mask
1937 */
1938 word = ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
1939 ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
1940 ((u32)(enable & 0x1) << 8) |
1941 ((0x7ULL) << 16);
1942 cmd.req.arg[1] = (adapter->recv_ctx->context_id);
1943 cmd.req.arg[2] = word;
1944 memcpy(&cmd.req.arg[4], key, sizeof(key));
1945
1946 err = qlcnic_issue_cmd(adapter, &cmd);
1947
1948 if (err)
1949 dev_info(&adapter->pdev->dev, "RSS config failed\n");
1950 qlcnic_free_mbx_args(&cmd);
1951
1952 return err;
1953
1954 }
1955
1956 static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter *adapter,
1957 u32 *interface_id)
1958 {
1959 if (qlcnic_sriov_pf_check(adapter)) {
1960 qlcnic_pf_set_interface_id_macaddr(adapter, interface_id);
1961 } else {
1962 if (!qlcnic_sriov_vf_check(adapter))
1963 *interface_id = adapter->recv_ctx->context_id << 16;
1964 }
1965 }
1966
1967 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
1968 u16 vlan_id, u8 op)
1969 {
1970 int err;
1971 u32 *buf, temp = 0;
1972 struct qlcnic_cmd_args cmd;
1973 struct qlcnic_macvlan_mbx mv;
1974
1975 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1976 return -EIO;
1977
1978 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_MAC_VLAN);
1979 if (err)
1980 return err;
1981
1982 if (vlan_id)
1983 op = (op == QLCNIC_MAC_ADD || op == QLCNIC_MAC_VLAN_ADD) ?
1984 QLCNIC_MAC_VLAN_ADD : QLCNIC_MAC_VLAN_DEL;
1985
1986 cmd.req.arg[1] = op | (1 << 8);
1987 qlcnic_83xx_set_interface_id_macaddr(adapter, &temp);
1988 cmd.req.arg[1] |= temp;
1989 mv.vlan = vlan_id;
1990 mv.mac_addr0 = addr[0];
1991 mv.mac_addr1 = addr[1];
1992 mv.mac_addr2 = addr[2];
1993 mv.mac_addr3 = addr[3];
1994 mv.mac_addr4 = addr[4];
1995 mv.mac_addr5 = addr[5];
1996 buf = &cmd.req.arg[2];
1997 memcpy(buf, &mv, sizeof(struct qlcnic_macvlan_mbx));
1998 err = qlcnic_issue_cmd(adapter, &cmd);
1999 if (err)
2000 dev_err(&adapter->pdev->dev,
2001 "MAC-VLAN %s to CAM failed, err=%d.\n",
2002 ((op == 1) ? "add " : "delete "), err);
2003 qlcnic_free_mbx_args(&cmd);
2004 return err;
2005 }
2006
2007 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr,
2008 u16 vlan_id)
2009 {
2010 u8 mac[ETH_ALEN];
2011 memcpy(&mac, addr, ETH_ALEN);
2012 qlcnic_83xx_sre_macaddr_change(adapter, mac, vlan_id, QLCNIC_MAC_ADD);
2013 }
2014
2015 void qlcnic_83xx_configure_mac(struct qlcnic_adapter *adapter, u8 *mac,
2016 u8 type, struct qlcnic_cmd_args *cmd)
2017 {
2018 switch (type) {
2019 case QLCNIC_SET_STATION_MAC:
2020 case QLCNIC_SET_FAC_DEF_MAC:
2021 memcpy(&cmd->req.arg[2], mac, sizeof(u32));
2022 memcpy(&cmd->req.arg[3], &mac[4], sizeof(u16));
2023 break;
2024 }
2025 cmd->req.arg[1] = type;
2026 }
2027
2028 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac)
2029 {
2030 int err, i;
2031 struct qlcnic_cmd_args cmd;
2032 u32 mac_low, mac_high;
2033
2034 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
2035 if (err)
2036 return err;
2037
2038 qlcnic_83xx_configure_mac(adapter, mac, QLCNIC_GET_CURRENT_MAC, &cmd);
2039 err = qlcnic_issue_cmd(adapter, &cmd);
2040
2041 if (err == QLCNIC_RCODE_SUCCESS) {
2042 mac_low = cmd.rsp.arg[1];
2043 mac_high = cmd.rsp.arg[2];
2044
2045 for (i = 0; i < 2; i++)
2046 mac[i] = (u8) (mac_high >> ((1 - i) * 8));
2047 for (i = 2; i < 6; i++)
2048 mac[i] = (u8) (mac_low >> ((5 - i) * 8));
2049 } else {
2050 dev_err(&adapter->pdev->dev, "Failed to get mac address%d\n",
2051 err);
2052 err = -EIO;
2053 }
2054 qlcnic_free_mbx_args(&cmd);
2055 return err;
2056 }
2057
2058 void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *adapter)
2059 {
2060 int err;
2061 u16 temp;
2062 struct qlcnic_cmd_args cmd;
2063 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2064
2065 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2066 return;
2067
2068 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
2069 if (err)
2070 return;
2071
2072 if (coal->type == QLCNIC_INTR_COAL_TYPE_RX) {
2073 temp = adapter->recv_ctx->context_id;
2074 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_RX | temp << 16;
2075 temp = coal->rx_time_us;
2076 cmd.req.arg[2] = coal->rx_packets | temp << 16;
2077 } else if (coal->type == QLCNIC_INTR_COAL_TYPE_TX) {
2078 temp = adapter->tx_ring->ctx_id;
2079 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_TX | temp << 16;
2080 temp = coal->tx_time_us;
2081 cmd.req.arg[2] = coal->tx_packets | temp << 16;
2082 }
2083 cmd.req.arg[3] = coal->flag;
2084 err = qlcnic_issue_cmd(adapter, &cmd);
2085 if (err != QLCNIC_RCODE_SUCCESS)
2086 dev_info(&adapter->pdev->dev,
2087 "Failed to send interrupt coalescence parameters\n");
2088 qlcnic_free_mbx_args(&cmd);
2089 }
2090
2091 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
2092 u32 data[])
2093 {
2094 u8 link_status, duplex;
2095 /* link speed */
2096 link_status = LSB(data[3]) & 1;
2097 adapter->ahw->link_speed = MSW(data[2]);
2098 adapter->ahw->link_autoneg = MSB(MSW(data[3]));
2099 adapter->ahw->module_type = MSB(LSW(data[3]));
2100 duplex = LSB(MSW(data[3]));
2101 if (duplex)
2102 adapter->ahw->link_duplex = DUPLEX_FULL;
2103 else
2104 adapter->ahw->link_duplex = DUPLEX_HALF;
2105 adapter->ahw->has_link_events = 1;
2106 qlcnic_advert_link_change(adapter, link_status);
2107 }
2108
2109 irqreturn_t qlcnic_83xx_handle_aen(int irq, void *data)
2110 {
2111 struct qlcnic_adapter *adapter = data;
2112 unsigned long flags;
2113 u32 mask, resp, event;
2114
2115 spin_lock_irqsave(&adapter->ahw->mbx_lock, flags);
2116 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
2117 if (!(resp & QLCNIC_SET_OWNER))
2118 goto out;
2119
2120 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
2121 if (event & QLCNIC_MBX_ASYNC_EVENT)
2122 __qlcnic_83xx_process_aen(adapter);
2123 out:
2124 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
2125 writel(0, adapter->ahw->pci_base0 + mask);
2126 spin_unlock_irqrestore(&adapter->ahw->mbx_lock, flags);
2127
2128 return IRQ_HANDLED;
2129 }
2130
2131 int qlcnic_enable_eswitch(struct qlcnic_adapter *adapter, u8 port, u8 enable)
2132 {
2133 int err = -EIO;
2134 struct qlcnic_cmd_args cmd;
2135
2136 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2137 dev_err(&adapter->pdev->dev,
2138 "%s: Error, invoked by non management func\n",
2139 __func__);
2140 return err;
2141 }
2142
2143 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_TOGGLE_ESWITCH);
2144 if (err)
2145 return err;
2146
2147 cmd.req.arg[1] = (port & 0xf) | BIT_4;
2148 err = qlcnic_issue_cmd(adapter, &cmd);
2149
2150 if (err != QLCNIC_RCODE_SUCCESS) {
2151 dev_err(&adapter->pdev->dev, "Failed to enable eswitch%d\n",
2152 err);
2153 err = -EIO;
2154 }
2155 qlcnic_free_mbx_args(&cmd);
2156
2157 return err;
2158
2159 }
2160
2161 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *adapter,
2162 struct qlcnic_info *nic)
2163 {
2164 int i, err = -EIO;
2165 struct qlcnic_cmd_args cmd;
2166
2167 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2168 dev_err(&adapter->pdev->dev,
2169 "%s: Error, invoked by non management func\n",
2170 __func__);
2171 return err;
2172 }
2173
2174 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
2175 if (err)
2176 return err;
2177
2178 cmd.req.arg[1] = (nic->pci_func << 16);
2179 cmd.req.arg[2] = 0x1 << 16;
2180 cmd.req.arg[3] = nic->phys_port | (nic->switch_mode << 16);
2181 cmd.req.arg[4] = nic->capabilities;
2182 cmd.req.arg[5] = (nic->max_mac_filters & 0xFF) | ((nic->max_mtu) << 16);
2183 cmd.req.arg[6] = (nic->max_tx_ques) | ((nic->max_rx_ques) << 16);
2184 cmd.req.arg[7] = (nic->min_tx_bw) | ((nic->max_tx_bw) << 16);
2185 for (i = 8; i < 32; i++)
2186 cmd.req.arg[i] = 0;
2187
2188 err = qlcnic_issue_cmd(adapter, &cmd);
2189
2190 if (err != QLCNIC_RCODE_SUCCESS) {
2191 dev_err(&adapter->pdev->dev, "Failed to set nic info%d\n",
2192 err);
2193 err = -EIO;
2194 }
2195
2196 qlcnic_free_mbx_args(&cmd);
2197
2198 return err;
2199 }
2200
2201 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *adapter,
2202 struct qlcnic_info *npar_info, u8 func_id)
2203 {
2204 int err;
2205 u32 temp;
2206 u8 op = 0;
2207 struct qlcnic_cmd_args cmd;
2208 struct qlcnic_hardware_context *ahw = adapter->ahw;
2209
2210 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
2211 if (err)
2212 return err;
2213
2214 if (func_id != ahw->pci_func) {
2215 temp = func_id << 16;
2216 cmd.req.arg[1] = op | BIT_31 | temp;
2217 } else {
2218 cmd.req.arg[1] = ahw->pci_func << 16;
2219 }
2220 err = qlcnic_issue_cmd(adapter, &cmd);
2221 if (err) {
2222 dev_info(&adapter->pdev->dev,
2223 "Failed to get nic info %d\n", err);
2224 goto out;
2225 }
2226
2227 npar_info->op_type = cmd.rsp.arg[1];
2228 npar_info->pci_func = cmd.rsp.arg[2] & 0xFFFF;
2229 npar_info->op_mode = (cmd.rsp.arg[2] & 0xFFFF0000) >> 16;
2230 npar_info->phys_port = cmd.rsp.arg[3] & 0xFFFF;
2231 npar_info->switch_mode = (cmd.rsp.arg[3] & 0xFFFF0000) >> 16;
2232 npar_info->capabilities = cmd.rsp.arg[4];
2233 npar_info->max_mac_filters = cmd.rsp.arg[5] & 0xFF;
2234 npar_info->max_mtu = (cmd.rsp.arg[5] & 0xFFFF0000) >> 16;
2235 npar_info->max_tx_ques = cmd.rsp.arg[6] & 0xFFFF;
2236 npar_info->max_rx_ques = (cmd.rsp.arg[6] & 0xFFFF0000) >> 16;
2237 npar_info->min_tx_bw = cmd.rsp.arg[7] & 0xFFFF;
2238 npar_info->max_tx_bw = (cmd.rsp.arg[7] & 0xFFFF0000) >> 16;
2239 if (cmd.rsp.arg[8] & 0x1)
2240 npar_info->max_bw_reg_offset = (cmd.rsp.arg[8] & 0x7FFE) >> 1;
2241 if (cmd.rsp.arg[8] & 0x10000) {
2242 temp = (cmd.rsp.arg[8] & 0x7FFE0000) >> 17;
2243 npar_info->max_linkspeed_reg_offset = temp;
2244 }
2245 if (npar_info->capabilities & QLCNIC_FW_CAPABILITY_MORE_CAPS)
2246 memcpy(ahw->extra_capability, &cmd.rsp.arg[16],
2247 sizeof(ahw->extra_capability));
2248
2249 out:
2250 qlcnic_free_mbx_args(&cmd);
2251 return err;
2252 }
2253
2254 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *adapter,
2255 struct qlcnic_pci_info *pci_info)
2256 {
2257 struct qlcnic_hardware_context *ahw = adapter->ahw;
2258 struct device *dev = &adapter->pdev->dev;
2259 struct qlcnic_cmd_args cmd;
2260 int i, err = 0, j = 0;
2261 u32 temp;
2262
2263 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
2264 if (err)
2265 return err;
2266
2267 err = qlcnic_issue_cmd(adapter, &cmd);
2268
2269 ahw->act_pci_func = 0;
2270 if (err == QLCNIC_RCODE_SUCCESS) {
2271 ahw->max_pci_func = cmd.rsp.arg[1] & 0xFF;
2272 for (i = 2, j = 0; j < QLCNIC_MAX_PCI_FUNC; j++, pci_info++) {
2273 pci_info->id = cmd.rsp.arg[i] & 0xFFFF;
2274 pci_info->active = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2275 i++;
2276 pci_info->type = cmd.rsp.arg[i] & 0xFFFF;
2277 if (pci_info->type == QLCNIC_TYPE_NIC)
2278 ahw->act_pci_func++;
2279 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2280 pci_info->default_port = temp;
2281 i++;
2282 pci_info->tx_min_bw = cmd.rsp.arg[i] & 0xFFFF;
2283 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2284 pci_info->tx_max_bw = temp;
2285 i = i + 2;
2286 memcpy(pci_info->mac, &cmd.rsp.arg[i], ETH_ALEN - 2);
2287 i++;
2288 memcpy(pci_info->mac + sizeof(u32), &cmd.rsp.arg[i], 2);
2289 i = i + 3;
2290 if (ahw->op_mode == QLCNIC_MGMT_FUNC)
2291 dev_info(dev, "id = %d active = %d type = %d\n"
2292 "\tport = %d min bw = %d max bw = %d\n"
2293 "\tmac_addr = %pM\n", pci_info->id,
2294 pci_info->active, pci_info->type,
2295 pci_info->default_port,
2296 pci_info->tx_min_bw,
2297 pci_info->tx_max_bw, pci_info->mac);
2298 }
2299 if (ahw->op_mode == QLCNIC_MGMT_FUNC)
2300 dev_info(dev, "Max vNIC functions = %d, active vNIC functions = %d\n",
2301 ahw->max_pci_func, ahw->act_pci_func);
2302
2303 } else {
2304 dev_err(dev, "Failed to get PCI Info, error = %d\n", err);
2305 err = -EIO;
2306 }
2307
2308 qlcnic_free_mbx_args(&cmd);
2309
2310 return err;
2311 }
2312
2313 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *adapter, bool op_type)
2314 {
2315 int i, index, err;
2316 u8 max_ints;
2317 u32 val, temp, type;
2318 struct qlcnic_cmd_args cmd;
2319
2320 max_ints = adapter->ahw->num_msix - 1;
2321 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTRPT);
2322 if (err)
2323 return err;
2324
2325 cmd.req.arg[1] = max_ints;
2326
2327 if (qlcnic_sriov_vf_check(adapter))
2328 cmd.req.arg[1] |= (adapter->ahw->pci_func << 8) | BIT_16;
2329
2330 for (i = 0, index = 2; i < max_ints; i++) {
2331 type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
2332 val = type | (adapter->ahw->intr_tbl[i].type << 4);
2333 if (adapter->ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
2334 val |= (adapter->ahw->intr_tbl[i].id << 16);
2335 cmd.req.arg[index++] = val;
2336 }
2337 err = qlcnic_issue_cmd(adapter, &cmd);
2338 if (err) {
2339 dev_err(&adapter->pdev->dev,
2340 "Failed to configure interrupts 0x%x\n", err);
2341 goto out;
2342 }
2343
2344 max_ints = cmd.rsp.arg[1];
2345 for (i = 0, index = 2; i < max_ints; i++, index += 2) {
2346 val = cmd.rsp.arg[index];
2347 if (LSB(val)) {
2348 dev_info(&adapter->pdev->dev,
2349 "Can't configure interrupt %d\n",
2350 adapter->ahw->intr_tbl[i].id);
2351 continue;
2352 }
2353 if (op_type) {
2354 adapter->ahw->intr_tbl[i].id = MSW(val);
2355 adapter->ahw->intr_tbl[i].enabled = 1;
2356 temp = cmd.rsp.arg[index + 1];
2357 adapter->ahw->intr_tbl[i].src = temp;
2358 } else {
2359 adapter->ahw->intr_tbl[i].id = i;
2360 adapter->ahw->intr_tbl[i].enabled = 0;
2361 adapter->ahw->intr_tbl[i].src = 0;
2362 }
2363 }
2364 out:
2365 qlcnic_free_mbx_args(&cmd);
2366 return err;
2367 }
2368
2369 int qlcnic_83xx_lock_flash(struct qlcnic_adapter *adapter)
2370 {
2371 int id, timeout = 0;
2372 u32 status = 0;
2373
2374 while (status == 0) {
2375 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK);
2376 if (status)
2377 break;
2378
2379 if (++timeout >= QLC_83XX_FLASH_LOCK_TIMEOUT) {
2380 id = QLC_SHARED_REG_RD32(adapter,
2381 QLCNIC_FLASH_LOCK_OWNER);
2382 dev_err(&adapter->pdev->dev,
2383 "%s: failed, lock held by %d\n", __func__, id);
2384 return -EIO;
2385 }
2386 usleep_range(1000, 2000);
2387 }
2388
2389 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, adapter->portnum);
2390 return 0;
2391 }
2392
2393 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *adapter)
2394 {
2395 QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK);
2396 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 0xFF);
2397 }
2398
2399 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter,
2400 u32 flash_addr, u8 *p_data,
2401 int count)
2402 {
2403 int i, ret;
2404 u32 word, range, flash_offset, addr = flash_addr;
2405 ulong indirect_add, direct_window;
2406
2407 flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1);
2408 if (addr & 0x3) {
2409 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2410 return -EIO;
2411 }
2412
2413 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_DIRECT_WINDOW,
2414 (addr));
2415
2416 range = flash_offset + (count * sizeof(u32));
2417 /* Check if data is spread across multiple sectors */
2418 if (range > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2419
2420 /* Multi sector read */
2421 for (i = 0; i < count; i++) {
2422 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2423 ret = qlcnic_83xx_rd_reg_indirect(adapter,
2424 indirect_add);
2425 if (ret == -EIO)
2426 return -EIO;
2427
2428 word = ret;
2429 *(u32 *)p_data = word;
2430 p_data = p_data + 4;
2431 addr = addr + 4;
2432 flash_offset = flash_offset + 4;
2433
2434 if (flash_offset > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2435 direct_window = QLC_83XX_FLASH_DIRECT_WINDOW;
2436 /* This write is needed once for each sector */
2437 qlcnic_83xx_wrt_reg_indirect(adapter,
2438 direct_window,
2439 (addr));
2440 flash_offset = 0;
2441 }
2442 }
2443 } else {
2444 /* Single sector read */
2445 for (i = 0; i < count; i++) {
2446 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2447 ret = qlcnic_83xx_rd_reg_indirect(adapter,
2448 indirect_add);
2449 if (ret == -EIO)
2450 return -EIO;
2451
2452 word = ret;
2453 *(u32 *)p_data = word;
2454 p_data = p_data + 4;
2455 addr = addr + 4;
2456 }
2457 }
2458
2459 return 0;
2460 }
2461
2462 static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter)
2463 {
2464 u32 status;
2465 int retries = QLC_83XX_FLASH_READ_RETRY_COUNT;
2466
2467 do {
2468 status = qlcnic_83xx_rd_reg_indirect(adapter,
2469 QLC_83XX_FLASH_STATUS);
2470 if ((status & QLC_83XX_FLASH_STATUS_READY) ==
2471 QLC_83XX_FLASH_STATUS_READY)
2472 break;
2473
2474 msleep(QLC_83XX_FLASH_STATUS_REG_POLL_DELAY);
2475 } while (--retries);
2476
2477 if (!retries)
2478 return -EIO;
2479
2480 return 0;
2481 }
2482
2483 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *adapter)
2484 {
2485 int ret;
2486 u32 cmd;
2487 cmd = adapter->ahw->fdt.write_statusreg_cmd;
2488 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2489 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | cmd));
2490 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2491 adapter->ahw->fdt.write_enable_bits);
2492 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2493 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2494 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2495 if (ret)
2496 return -EIO;
2497
2498 return 0;
2499 }
2500
2501 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *adapter)
2502 {
2503 int ret;
2504
2505 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2506 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG |
2507 adapter->ahw->fdt.write_statusreg_cmd));
2508 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2509 adapter->ahw->fdt.write_disable_bits);
2510 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2511 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2512 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2513 if (ret)
2514 return -EIO;
2515
2516 return 0;
2517 }
2518
2519 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter)
2520 {
2521 int ret, mfg_id;
2522
2523 if (qlcnic_83xx_lock_flash(adapter))
2524 return -EIO;
2525
2526 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2527 QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL);
2528 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2529 QLC_83XX_FLASH_READ_CTRL);
2530 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2531 if (ret) {
2532 qlcnic_83xx_unlock_flash(adapter);
2533 return -EIO;
2534 }
2535
2536 mfg_id = qlcnic_83xx_rd_reg_indirect(adapter, QLC_83XX_FLASH_RDDATA);
2537 if (mfg_id == -EIO)
2538 return -EIO;
2539
2540 adapter->flash_mfg_id = (mfg_id & 0xFF);
2541 qlcnic_83xx_unlock_flash(adapter);
2542
2543 return 0;
2544 }
2545
2546 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *adapter)
2547 {
2548 int count, fdt_size, ret = 0;
2549
2550 fdt_size = sizeof(struct qlcnic_fdt);
2551 count = fdt_size / sizeof(u32);
2552
2553 if (qlcnic_83xx_lock_flash(adapter))
2554 return -EIO;
2555
2556 memset(&adapter->ahw->fdt, 0, fdt_size);
2557 ret = qlcnic_83xx_lockless_flash_read32(adapter, QLCNIC_FDT_LOCATION,
2558 (u8 *)&adapter->ahw->fdt,
2559 count);
2560
2561 qlcnic_83xx_unlock_flash(adapter);
2562 return ret;
2563 }
2564
2565 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *adapter,
2566 u32 sector_start_addr)
2567 {
2568 u32 reversed_addr, addr1, addr2, cmd;
2569 int ret = -EIO;
2570
2571 if (qlcnic_83xx_lock_flash(adapter) != 0)
2572 return -EIO;
2573
2574 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2575 ret = qlcnic_83xx_enable_flash_write(adapter);
2576 if (ret) {
2577 qlcnic_83xx_unlock_flash(adapter);
2578 dev_err(&adapter->pdev->dev,
2579 "%s failed at %d\n",
2580 __func__, __LINE__);
2581 return ret;
2582 }
2583 }
2584
2585 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2586 if (ret) {
2587 qlcnic_83xx_unlock_flash(adapter);
2588 dev_err(&adapter->pdev->dev,
2589 "%s: failed at %d\n", __func__, __LINE__);
2590 return -EIO;
2591 }
2592
2593 addr1 = (sector_start_addr & 0xFF) << 16;
2594 addr2 = (sector_start_addr & 0xFF0000) >> 16;
2595 reversed_addr = addr1 | addr2;
2596
2597 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2598 reversed_addr);
2599 cmd = QLC_83XX_FLASH_FDT_ERASE_DEF_SIG | adapter->ahw->fdt.erase_cmd;
2600 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id)
2601 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, cmd);
2602 else
2603 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2604 QLC_83XX_FLASH_OEM_ERASE_SIG);
2605 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2606 QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2607
2608 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2609 if (ret) {
2610 qlcnic_83xx_unlock_flash(adapter);
2611 dev_err(&adapter->pdev->dev,
2612 "%s: failed at %d\n", __func__, __LINE__);
2613 return -EIO;
2614 }
2615
2616 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2617 ret = qlcnic_83xx_disable_flash_write(adapter);
2618 if (ret) {
2619 qlcnic_83xx_unlock_flash(adapter);
2620 dev_err(&adapter->pdev->dev,
2621 "%s: failed at %d\n", __func__, __LINE__);
2622 return ret;
2623 }
2624 }
2625
2626 qlcnic_83xx_unlock_flash(adapter);
2627
2628 return 0;
2629 }
2630
2631 int qlcnic_83xx_flash_write32(struct qlcnic_adapter *adapter, u32 addr,
2632 u32 *p_data)
2633 {
2634 int ret = -EIO;
2635 u32 addr1 = 0x00800000 | (addr >> 2);
2636
2637 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, addr1);
2638 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data);
2639 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2640 QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2641 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2642 if (ret) {
2643 dev_err(&adapter->pdev->dev,
2644 "%s: failed at %d\n", __func__, __LINE__);
2645 return -EIO;
2646 }
2647
2648 return 0;
2649 }
2650
2651 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr,
2652 u32 *p_data, int count)
2653 {
2654 u32 temp;
2655 int ret = -EIO;
2656
2657 if ((count < QLC_83XX_FLASH_WRITE_MIN) ||
2658 (count > QLC_83XX_FLASH_WRITE_MAX)) {
2659 dev_err(&adapter->pdev->dev,
2660 "%s: Invalid word count\n", __func__);
2661 return -EIO;
2662 }
2663
2664 temp = qlcnic_83xx_rd_reg_indirect(adapter,
2665 QLC_83XX_FLASH_SPI_CONTROL);
2666 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL,
2667 (temp | QLC_83XX_FLASH_SPI_CTRL));
2668 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2669 QLC_83XX_FLASH_ADDR_TEMP_VAL);
2670
2671 /* First DWORD write */
2672 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2673 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2674 QLC_83XX_FLASH_FIRST_MS_PATTERN);
2675 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2676 if (ret) {
2677 dev_err(&adapter->pdev->dev,
2678 "%s: failed at %d\n", __func__, __LINE__);
2679 return -EIO;
2680 }
2681
2682 count--;
2683 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2684 QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL);
2685 /* Second to N-1 DWORD writes */
2686 while (count != 1) {
2687 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2688 *p_data++);
2689 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2690 QLC_83XX_FLASH_SECOND_MS_PATTERN);
2691 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2692 if (ret) {
2693 dev_err(&adapter->pdev->dev,
2694 "%s: failed at %d\n", __func__, __LINE__);
2695 return -EIO;
2696 }
2697 count--;
2698 }
2699
2700 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2701 QLC_83XX_FLASH_ADDR_TEMP_VAL |
2702 (addr >> 2));
2703 /* Last DWORD write */
2704 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2705 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2706 QLC_83XX_FLASH_LAST_MS_PATTERN);
2707 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2708 if (ret) {
2709 dev_err(&adapter->pdev->dev,
2710 "%s: failed at %d\n", __func__, __LINE__);
2711 return -EIO;
2712 }
2713
2714 ret = qlcnic_83xx_rd_reg_indirect(adapter, QLC_83XX_FLASH_SPI_STATUS);
2715 if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) {
2716 dev_err(&adapter->pdev->dev, "%s: failed at %d\n",
2717 __func__, __LINE__);
2718 /* Operation failed, clear error bit */
2719 temp = qlcnic_83xx_rd_reg_indirect(adapter,
2720 QLC_83XX_FLASH_SPI_CONTROL);
2721 qlcnic_83xx_wrt_reg_indirect(adapter,
2722 QLC_83XX_FLASH_SPI_CONTROL,
2723 (temp | QLC_83XX_FLASH_SPI_CTRL));
2724 }
2725
2726 return 0;
2727 }
2728
2729 static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter *adapter)
2730 {
2731 u32 val, id;
2732
2733 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2734
2735 /* Check if recovery need to be performed by the calling function */
2736 if ((val & QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK) == 0) {
2737 val = val & ~0x3F;
2738 val = val | ((adapter->portnum << 2) |
2739 QLC_83XX_NEED_DRV_LOCK_RECOVERY);
2740 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2741 dev_info(&adapter->pdev->dev,
2742 "%s: lock recovery initiated\n", __func__);
2743 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY);
2744 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2745 id = ((val >> 2) & 0xF);
2746 if (id == adapter->portnum) {
2747 val = val & ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK;
2748 val = val | QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS;
2749 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2750 /* Force release the lock */
2751 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2752 /* Clear recovery bits */
2753 val = val & ~0x3F;
2754 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2755 dev_info(&adapter->pdev->dev,
2756 "%s: lock recovery completed\n", __func__);
2757 } else {
2758 dev_info(&adapter->pdev->dev,
2759 "%s: func %d to resume lock recovery process\n",
2760 __func__, id);
2761 }
2762 } else {
2763 dev_info(&adapter->pdev->dev,
2764 "%s: lock recovery initiated by other functions\n",
2765 __func__);
2766 }
2767 }
2768
2769 int qlcnic_83xx_lock_driver(struct qlcnic_adapter *adapter)
2770 {
2771 u32 lock_alive_counter, val, id, i = 0, status = 0, temp = 0;
2772 int max_attempt = 0;
2773
2774 while (status == 0) {
2775 status = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK);
2776 if (status)
2777 break;
2778
2779 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY);
2780 i++;
2781
2782 if (i == 1)
2783 temp = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2784
2785 if (i == QLC_83XX_DRV_LOCK_WAIT_COUNTER) {
2786 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2787 if (val == temp) {
2788 id = val & 0xFF;
2789 dev_info(&adapter->pdev->dev,
2790 "%s: lock to be recovered from %d\n",
2791 __func__, id);
2792 qlcnic_83xx_recover_driver_lock(adapter);
2793 i = 0;
2794 max_attempt++;
2795 } else {
2796 dev_err(&adapter->pdev->dev,
2797 "%s: failed to get lock\n", __func__);
2798 return -EIO;
2799 }
2800 }
2801
2802 /* Force exit from while loop after few attempts */
2803 if (max_attempt == QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT) {
2804 dev_err(&adapter->pdev->dev,
2805 "%s: failed to get lock\n", __func__);
2806 return -EIO;
2807 }
2808 }
2809
2810 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2811 lock_alive_counter = val >> 8;
2812 lock_alive_counter++;
2813 val = lock_alive_counter << 8 | adapter->portnum;
2814 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2815
2816 return 0;
2817 }
2818
2819 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *adapter)
2820 {
2821 u32 val, lock_alive_counter, id;
2822
2823 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2824 id = val & 0xFF;
2825 lock_alive_counter = val >> 8;
2826
2827 if (id != adapter->portnum)
2828 dev_err(&adapter->pdev->dev,
2829 "%s:Warning func %d is unlocking lock owned by %d\n",
2830 __func__, adapter->portnum, id);
2831
2832 val = (lock_alive_counter << 8) | 0xFF;
2833 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2834 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2835 }
2836
2837 int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr,
2838 u32 *data, u32 count)
2839 {
2840 int i, j, ret = 0;
2841 u32 temp;
2842
2843 /* Check alignment */
2844 if (addr & 0xF)
2845 return -EIO;
2846
2847 mutex_lock(&adapter->ahw->mem_lock);
2848 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_HI, 0);
2849
2850 for (i = 0; i < count; i++, addr += 16) {
2851 if (!((ADDR_IN_RANGE(addr, QLCNIC_ADDR_QDR_NET,
2852 QLCNIC_ADDR_QDR_NET_MAX)) ||
2853 (ADDR_IN_RANGE(addr, QLCNIC_ADDR_DDR_NET,
2854 QLCNIC_ADDR_DDR_NET_MAX)))) {
2855 mutex_unlock(&adapter->ahw->mem_lock);
2856 return -EIO;
2857 }
2858
2859 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_LO, addr);
2860 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_LO,
2861 *data++);
2862 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_HI,
2863 *data++);
2864 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_ULO,
2865 *data++);
2866 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_UHI,
2867 *data++);
2868 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2869 QLCNIC_TA_WRITE_ENABLE);
2870 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2871 QLCNIC_TA_WRITE_START);
2872
2873 for (j = 0; j < MAX_CTL_CHECK; j++) {
2874 temp = qlcnic_83xx_rd_reg_indirect(adapter,
2875 QLCNIC_MS_CTRL);
2876 if ((temp & TA_CTL_BUSY) == 0)
2877 break;
2878 }
2879
2880 /* Status check failure */
2881 if (j >= MAX_CTL_CHECK) {
2882 printk_ratelimited(KERN_WARNING
2883 "MS memory write failed\n");
2884 mutex_unlock(&adapter->ahw->mem_lock);
2885 return -EIO;
2886 }
2887 }
2888
2889 mutex_unlock(&adapter->ahw->mem_lock);
2890
2891 return ret;
2892 }
2893
2894 int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr,
2895 u8 *p_data, int count)
2896 {
2897 int i, ret;
2898 u32 word, addr = flash_addr;
2899 ulong indirect_addr;
2900
2901 if (qlcnic_83xx_lock_flash(adapter) != 0)
2902 return -EIO;
2903
2904 if (addr & 0x3) {
2905 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2906 qlcnic_83xx_unlock_flash(adapter);
2907 return -EIO;
2908 }
2909
2910 for (i = 0; i < count; i++) {
2911 if (qlcnic_83xx_wrt_reg_indirect(adapter,
2912 QLC_83XX_FLASH_DIRECT_WINDOW,
2913 (addr))) {
2914 qlcnic_83xx_unlock_flash(adapter);
2915 return -EIO;
2916 }
2917
2918 indirect_addr = QLC_83XX_FLASH_DIRECT_DATA(addr);
2919 ret = qlcnic_83xx_rd_reg_indirect(adapter,
2920 indirect_addr);
2921 if (ret == -EIO)
2922 return -EIO;
2923 word = ret;
2924 *(u32 *)p_data = word;
2925 p_data = p_data + 4;
2926 addr = addr + 4;
2927 }
2928
2929 qlcnic_83xx_unlock_flash(adapter);
2930
2931 return 0;
2932 }
2933
2934 int qlcnic_83xx_test_link(struct qlcnic_adapter *adapter)
2935 {
2936 u8 pci_func;
2937 int err;
2938 u32 config = 0, state;
2939 struct qlcnic_cmd_args cmd;
2940 struct qlcnic_hardware_context *ahw = adapter->ahw;
2941
2942 if (qlcnic_sriov_vf_check(adapter))
2943 pci_func = adapter->portnum;
2944 else
2945 pci_func = ahw->pci_func;
2946
2947 state = readl(ahw->pci_base0 + QLC_83XX_LINK_STATE(pci_func));
2948 if (!QLC_83xx_FUNC_VAL(state, pci_func)) {
2949 dev_info(&adapter->pdev->dev, "link state down\n");
2950 return config;
2951 }
2952
2953 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS);
2954 if (err)
2955 return err;
2956
2957 err = qlcnic_issue_cmd(adapter, &cmd);
2958 if (err) {
2959 dev_info(&adapter->pdev->dev,
2960 "Get Link Status Command failed: 0x%x\n", err);
2961 goto out;
2962 } else {
2963 config = cmd.rsp.arg[1];
2964 switch (QLC_83XX_CURRENT_LINK_SPEED(config)) {
2965 case QLC_83XX_10M_LINK:
2966 ahw->link_speed = SPEED_10;
2967 break;
2968 case QLC_83XX_100M_LINK:
2969 ahw->link_speed = SPEED_100;
2970 break;
2971 case QLC_83XX_1G_LINK:
2972 ahw->link_speed = SPEED_1000;
2973 break;
2974 case QLC_83XX_10G_LINK:
2975 ahw->link_speed = SPEED_10000;
2976 break;
2977 default:
2978 ahw->link_speed = 0;
2979 break;
2980 }
2981 config = cmd.rsp.arg[3];
2982 if (QLC_83XX_SFP_PRESENT(config)) {
2983 switch (ahw->module_type) {
2984 case LINKEVENT_MODULE_OPTICAL_UNKNOWN:
2985 case LINKEVENT_MODULE_OPTICAL_SRLR:
2986 case LINKEVENT_MODULE_OPTICAL_LRM:
2987 case LINKEVENT_MODULE_OPTICAL_SFP_1G:
2988 ahw->supported_type = PORT_FIBRE;
2989 break;
2990 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE:
2991 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN:
2992 case LINKEVENT_MODULE_TWINAX:
2993 ahw->supported_type = PORT_TP;
2994 break;
2995 default:
2996 ahw->supported_type = PORT_OTHER;
2997 }
2998 }
2999 if (config & 1)
3000 err = 1;
3001 }
3002 out:
3003 qlcnic_free_mbx_args(&cmd);
3004 return config;
3005 }
3006
3007 int qlcnic_83xx_get_settings(struct qlcnic_adapter *adapter,
3008 struct ethtool_cmd *ecmd)
3009 {
3010 u32 config = 0;
3011 int status = 0;
3012 struct qlcnic_hardware_context *ahw = adapter->ahw;
3013
3014 /* Get port configuration info */
3015 status = qlcnic_83xx_get_port_info(adapter);
3016 /* Get Link Status related info */
3017 config = qlcnic_83xx_test_link(adapter);
3018 ahw->module_type = QLC_83XX_SFP_MODULE_TYPE(config);
3019 /* hard code until there is a way to get it from flash */
3020 ahw->board_type = QLCNIC_BRDTYPE_83XX_10G;
3021
3022 if (netif_running(adapter->netdev) && ahw->has_link_events) {
3023 ethtool_cmd_speed_set(ecmd, ahw->link_speed);
3024 ecmd->duplex = ahw->link_duplex;
3025 ecmd->autoneg = ahw->link_autoneg;
3026 } else {
3027 ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN);
3028 ecmd->duplex = DUPLEX_UNKNOWN;
3029 ecmd->autoneg = AUTONEG_DISABLE;
3030 }
3031
3032 if (ahw->port_type == QLCNIC_XGBE) {
3033 ecmd->supported = SUPPORTED_1000baseT_Full;
3034 ecmd->advertising = ADVERTISED_1000baseT_Full;
3035 } else {
3036 ecmd->supported = (SUPPORTED_10baseT_Half |
3037 SUPPORTED_10baseT_Full |
3038 SUPPORTED_100baseT_Half |
3039 SUPPORTED_100baseT_Full |
3040 SUPPORTED_1000baseT_Half |
3041 SUPPORTED_1000baseT_Full);
3042 ecmd->advertising = (ADVERTISED_100baseT_Half |
3043 ADVERTISED_100baseT_Full |
3044 ADVERTISED_1000baseT_Half |
3045 ADVERTISED_1000baseT_Full);
3046 }
3047
3048 switch (ahw->supported_type) {
3049 case PORT_FIBRE:
3050 ecmd->supported |= SUPPORTED_FIBRE;
3051 ecmd->advertising |= ADVERTISED_FIBRE;
3052 ecmd->port = PORT_FIBRE;
3053 ecmd->transceiver = XCVR_EXTERNAL;
3054 break;
3055 case PORT_TP:
3056 ecmd->supported |= SUPPORTED_TP;
3057 ecmd->advertising |= ADVERTISED_TP;
3058 ecmd->port = PORT_TP;
3059 ecmd->transceiver = XCVR_INTERNAL;
3060 break;
3061 default:
3062 ecmd->supported |= SUPPORTED_FIBRE;
3063 ecmd->advertising |= ADVERTISED_FIBRE;
3064 ecmd->port = PORT_OTHER;
3065 ecmd->transceiver = XCVR_EXTERNAL;
3066 break;
3067 }
3068 ecmd->phy_address = ahw->physical_port;
3069 return status;
3070 }
3071
3072 int qlcnic_83xx_set_settings(struct qlcnic_adapter *adapter,
3073 struct ethtool_cmd *ecmd)
3074 {
3075 int status = 0;
3076 u32 config = adapter->ahw->port_config;
3077
3078 if (ecmd->autoneg)
3079 adapter->ahw->port_config |= BIT_15;
3080
3081 switch (ethtool_cmd_speed(ecmd)) {
3082 case SPEED_10:
3083 adapter->ahw->port_config |= BIT_8;
3084 break;
3085 case SPEED_100:
3086 adapter->ahw->port_config |= BIT_9;
3087 break;
3088 case SPEED_1000:
3089 adapter->ahw->port_config |= BIT_10;
3090 break;
3091 case SPEED_10000:
3092 adapter->ahw->port_config |= BIT_11;
3093 break;
3094 default:
3095 return -EINVAL;
3096 }
3097
3098 status = qlcnic_83xx_set_port_config(adapter);
3099 if (status) {
3100 dev_info(&adapter->pdev->dev,
3101 "Faild to Set Link Speed and autoneg.\n");
3102 adapter->ahw->port_config = config;
3103 }
3104 return status;
3105 }
3106
3107 static inline u64 *qlcnic_83xx_copy_stats(struct qlcnic_cmd_args *cmd,
3108 u64 *data, int index)
3109 {
3110 u32 low, hi;
3111 u64 val;
3112
3113 low = cmd->rsp.arg[index];
3114 hi = cmd->rsp.arg[index + 1];
3115 val = (((u64) low) | (((u64) hi) << 32));
3116 *data++ = val;
3117 return data;
3118 }
3119
3120 static u64 *qlcnic_83xx_fill_stats(struct qlcnic_adapter *adapter,
3121 struct qlcnic_cmd_args *cmd, u64 *data,
3122 int type, int *ret)
3123 {
3124 int err, k, total_regs;
3125
3126 *ret = 0;
3127 err = qlcnic_issue_cmd(adapter, cmd);
3128 if (err != QLCNIC_RCODE_SUCCESS) {
3129 dev_info(&adapter->pdev->dev,
3130 "Error in get statistics mailbox command\n");
3131 *ret = -EIO;
3132 return data;
3133 }
3134 total_regs = cmd->rsp.num;
3135 switch (type) {
3136 case QLC_83XX_STAT_MAC:
3137 /* fill in MAC tx counters */
3138 for (k = 2; k < 28; k += 2)
3139 data = qlcnic_83xx_copy_stats(cmd, data, k);
3140 /* skip 24 bytes of reserved area */
3141 /* fill in MAC rx counters */
3142 for (k += 6; k < 60; k += 2)
3143 data = qlcnic_83xx_copy_stats(cmd, data, k);
3144 /* skip 24 bytes of reserved area */
3145 /* fill in MAC rx frame stats */
3146 for (k += 6; k < 80; k += 2)
3147 data = qlcnic_83xx_copy_stats(cmd, data, k);
3148 /* fill in eSwitch stats */
3149 for (; k < total_regs; k += 2)
3150 data = qlcnic_83xx_copy_stats(cmd, data, k);
3151 break;
3152 case QLC_83XX_STAT_RX:
3153 for (k = 2; k < 8; k += 2)
3154 data = qlcnic_83xx_copy_stats(cmd, data, k);
3155 /* skip 8 bytes of reserved data */
3156 for (k += 2; k < 24; k += 2)
3157 data = qlcnic_83xx_copy_stats(cmd, data, k);
3158 /* skip 8 bytes containing RE1FBQ error data */
3159 for (k += 2; k < total_regs; k += 2)
3160 data = qlcnic_83xx_copy_stats(cmd, data, k);
3161 break;
3162 case QLC_83XX_STAT_TX:
3163 for (k = 2; k < 10; k += 2)
3164 data = qlcnic_83xx_copy_stats(cmd, data, k);
3165 /* skip 8 bytes of reserved data */
3166 for (k += 2; k < total_regs; k += 2)
3167 data = qlcnic_83xx_copy_stats(cmd, data, k);
3168 break;
3169 default:
3170 dev_warn(&adapter->pdev->dev, "Unknown get statistics mode\n");
3171 *ret = -EIO;
3172 }
3173 return data;
3174 }
3175
3176 void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data)
3177 {
3178 struct qlcnic_cmd_args cmd;
3179 struct net_device *netdev = adapter->netdev;
3180 int ret = 0;
3181
3182 ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_STATISTICS);
3183 if (ret)
3184 return;
3185 /* Get Tx stats */
3186 cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16);
3187 cmd.rsp.num = QLC_83XX_TX_STAT_REGS;
3188 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3189 QLC_83XX_STAT_TX, &ret);
3190 if (ret) {
3191 netdev_err(netdev, "Error getting Tx stats\n");
3192 goto out;
3193 }
3194 /* Get MAC stats */
3195 cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16);
3196 cmd.rsp.num = QLC_83XX_MAC_STAT_REGS;
3197 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3198 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3199 QLC_83XX_STAT_MAC, &ret);
3200 if (ret) {
3201 netdev_err(netdev, "Error getting MAC stats\n");
3202 goto out;
3203 }
3204 /* Get Rx stats */
3205 cmd.req.arg[1] = adapter->recv_ctx->context_id << 16;
3206 cmd.rsp.num = QLC_83XX_RX_STAT_REGS;
3207 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3208 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3209 QLC_83XX_STAT_RX, &ret);
3210 if (ret)
3211 netdev_err(netdev, "Error getting Rx stats\n");
3212 out:
3213 qlcnic_free_mbx_args(&cmd);
3214 }
3215
3216 int qlcnic_83xx_reg_test(struct qlcnic_adapter *adapter)
3217 {
3218 u32 major, minor, sub;
3219
3220 major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
3221 minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
3222 sub = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
3223
3224 if (adapter->fw_version != QLCNIC_VERSION_CODE(major, minor, sub)) {
3225 dev_info(&adapter->pdev->dev, "%s: Reg test failed\n",
3226 __func__);
3227 return 1;
3228 }
3229 return 0;
3230 }
3231
3232 int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *adapter)
3233 {
3234 return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl) *
3235 sizeof(adapter->ahw->ext_reg_tbl)) +
3236 (ARRAY_SIZE(qlcnic_83xx_reg_tbl) +
3237 sizeof(adapter->ahw->reg_tbl));
3238 }
3239
3240 int qlcnic_83xx_get_registers(struct qlcnic_adapter *adapter, u32 *regs_buff)
3241 {
3242 int i, j = 0;
3243
3244 for (i = QLCNIC_DEV_INFO_SIZE + 1;
3245 j < ARRAY_SIZE(qlcnic_83xx_reg_tbl); i++, j++)
3246 regs_buff[i] = QLC_SHARED_REG_RD32(adapter, j);
3247
3248 for (j = 0; j < ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl); j++)
3249 regs_buff[i++] = QLCRDX(adapter->ahw, j);
3250 return i;
3251 }
3252
3253 int qlcnic_83xx_interrupt_test(struct net_device *netdev)
3254 {
3255 struct qlcnic_adapter *adapter = netdev_priv(netdev);
3256 struct qlcnic_hardware_context *ahw = adapter->ahw;
3257 struct qlcnic_cmd_args cmd;
3258 u32 data;
3259 u16 intrpt_id, id;
3260 u8 val;
3261 int ret, max_sds_rings = adapter->max_sds_rings;
3262
3263 if (qlcnic_get_diag_lock(adapter)) {
3264 netdev_info(netdev, "Device in diagnostics mode\n");
3265 return -EBUSY;
3266 }
3267
3268 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_INTERRUPT_TEST,
3269 max_sds_rings);
3270 if (ret)
3271 goto fail_diag_irq;
3272
3273 ahw->diag_cnt = 0;
3274 ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INTRPT_TEST);
3275 if (ret)
3276 goto fail_diag_irq;
3277
3278 if (adapter->flags & QLCNIC_MSIX_ENABLED)
3279 intrpt_id = ahw->intr_tbl[0].id;
3280 else
3281 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
3282
3283 cmd.req.arg[1] = 1;
3284 cmd.req.arg[2] = intrpt_id;
3285 cmd.req.arg[3] = BIT_0;
3286
3287 ret = qlcnic_issue_cmd(adapter, &cmd);
3288 data = cmd.rsp.arg[2];
3289 id = LSW(data);
3290 val = LSB(MSW(data));
3291 if (id != intrpt_id)
3292 dev_info(&adapter->pdev->dev,
3293 "Interrupt generated: 0x%x, requested:0x%x\n",
3294 id, intrpt_id);
3295 if (val)
3296 dev_err(&adapter->pdev->dev,
3297 "Interrupt test error: 0x%x\n", val);
3298 if (ret)
3299 goto done;
3300
3301 msleep(20);
3302 ret = !ahw->diag_cnt;
3303
3304 done:
3305 qlcnic_free_mbx_args(&cmd);
3306 qlcnic_83xx_diag_free_res(netdev, max_sds_rings);
3307
3308 fail_diag_irq:
3309 adapter->max_sds_rings = max_sds_rings;
3310 qlcnic_release_diag_lock(adapter);
3311 return ret;
3312 }
3313
3314 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *adapter,
3315 struct ethtool_pauseparam *pause)
3316 {
3317 struct qlcnic_hardware_context *ahw = adapter->ahw;
3318 int status = 0;
3319 u32 config;
3320
3321 status = qlcnic_83xx_get_port_config(adapter);
3322 if (status) {
3323 dev_err(&adapter->pdev->dev,
3324 "%s: Get Pause Config failed\n", __func__);
3325 return;
3326 }
3327 config = ahw->port_config;
3328 if (config & QLC_83XX_CFG_STD_PAUSE) {
3329 if (config & QLC_83XX_CFG_STD_TX_PAUSE)
3330 pause->tx_pause = 1;
3331 if (config & QLC_83XX_CFG_STD_RX_PAUSE)
3332 pause->rx_pause = 1;
3333 }
3334
3335 if (QLC_83XX_AUTONEG(config))
3336 pause->autoneg = 1;
3337 }
3338
3339 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *adapter,
3340 struct ethtool_pauseparam *pause)
3341 {
3342 struct qlcnic_hardware_context *ahw = adapter->ahw;
3343 int status = 0;
3344 u32 config;
3345
3346 status = qlcnic_83xx_get_port_config(adapter);
3347 if (status) {
3348 dev_err(&adapter->pdev->dev,
3349 "%s: Get Pause Config failed.\n", __func__);
3350 return status;
3351 }
3352 config = ahw->port_config;
3353
3354 if (ahw->port_type == QLCNIC_GBE) {
3355 if (pause->autoneg)
3356 ahw->port_config |= QLC_83XX_ENABLE_AUTONEG;
3357 if (!pause->autoneg)
3358 ahw->port_config &= ~QLC_83XX_ENABLE_AUTONEG;
3359 } else if ((ahw->port_type == QLCNIC_XGBE) && (pause->autoneg)) {
3360 return -EOPNOTSUPP;
3361 }
3362
3363 if (!(config & QLC_83XX_CFG_STD_PAUSE))
3364 ahw->port_config |= QLC_83XX_CFG_STD_PAUSE;
3365
3366 if (pause->rx_pause && pause->tx_pause) {
3367 ahw->port_config |= QLC_83XX_CFG_STD_TX_RX_PAUSE;
3368 } else if (pause->rx_pause && !pause->tx_pause) {
3369 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_PAUSE;
3370 ahw->port_config |= QLC_83XX_CFG_STD_RX_PAUSE;
3371 } else if (pause->tx_pause && !pause->rx_pause) {
3372 ahw->port_config &= ~QLC_83XX_CFG_STD_RX_PAUSE;
3373 ahw->port_config |= QLC_83XX_CFG_STD_TX_PAUSE;
3374 } else if (!pause->rx_pause && !pause->tx_pause) {
3375 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_RX_PAUSE;
3376 }
3377 status = qlcnic_83xx_set_port_config(adapter);
3378 if (status) {
3379 dev_err(&adapter->pdev->dev,
3380 "%s: Set Pause Config failed.\n", __func__);
3381 ahw->port_config = config;
3382 }
3383 return status;
3384 }
3385
3386 static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter)
3387 {
3388 int ret;
3389
3390 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
3391 QLC_83XX_FLASH_OEM_READ_SIG);
3392 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
3393 QLC_83XX_FLASH_READ_CTRL);
3394 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
3395 if (ret)
3396 return -EIO;
3397
3398 ret = qlcnic_83xx_rd_reg_indirect(adapter, QLC_83XX_FLASH_RDDATA);
3399 return ret & 0xFF;
3400 }
3401
3402 int qlcnic_83xx_flash_test(struct qlcnic_adapter *adapter)
3403 {
3404 int status;
3405
3406 status = qlcnic_83xx_read_flash_status_reg(adapter);
3407 if (status == -EIO) {
3408 dev_info(&adapter->pdev->dev, "%s: EEPROM test failed.\n",
3409 __func__);
3410 return 1;
3411 }
3412 return 0;
3413 }
3414
3415 int qlcnic_83xx_shutdown(struct pci_dev *pdev)
3416 {
3417 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3418 struct net_device *netdev = adapter->netdev;
3419 int retval;
3420
3421 netif_device_detach(netdev);
3422 qlcnic_cancel_idc_work(adapter);
3423
3424 if (netif_running(netdev))
3425 qlcnic_down(adapter, netdev);
3426
3427 qlcnic_83xx_disable_mbx_intr(adapter);
3428 cancel_delayed_work_sync(&adapter->idc_aen_work);
3429
3430 retval = pci_save_state(pdev);
3431 if (retval)
3432 return retval;
3433
3434 return 0;
3435 }
3436
3437 int qlcnic_83xx_resume(struct qlcnic_adapter *adapter)
3438 {
3439 struct qlcnic_hardware_context *ahw = adapter->ahw;
3440 struct qlc_83xx_idc *idc = &ahw->idc;
3441 int err = 0;
3442
3443 err = qlcnic_83xx_idc_init(adapter);
3444 if (err)
3445 return err;
3446
3447 if (ahw->nic_mode == QLC_83XX_VIRTUAL_NIC_MODE) {
3448 if (ahw->op_mode == QLCNIC_MGMT_FUNC) {
3449 qlcnic_83xx_set_vnic_opmode(adapter);
3450 } else {
3451 err = qlcnic_83xx_check_vnic_state(adapter);
3452 if (err)
3453 return err;
3454 }
3455 }
3456
3457 err = qlcnic_83xx_idc_reattach_driver(adapter);
3458 if (err)
3459 return err;
3460
3461 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
3462 idc->delay);
3463 return err;
3464 }
3465
3466 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx)
3467 {
3468 INIT_COMPLETION(mbx->completion);
3469 set_bit(QLC_83XX_MBX_READY, &mbx->status);
3470 }
3471
3472 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx)
3473 {
3474 destroy_workqueue(mbx->work_q);
3475 kfree(mbx);
3476 }
3477
3478 static inline void
3479 qlcnic_83xx_notify_cmd_completion(struct qlcnic_adapter *adapter,
3480 struct qlcnic_cmd_args *cmd)
3481 {
3482 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
3483
3484 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
3485 qlcnic_free_mbx_args(cmd);
3486 kfree(cmd);
3487 return;
3488 }
3489 complete(&cmd->completion);
3490 }
3491
3492 static inline void qlcnic_83xx_flush_mbx_queue(struct qlcnic_adapter *adapter)
3493 {
3494 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3495 struct list_head *head = &mbx->cmd_q;
3496 struct qlcnic_cmd_args *cmd = NULL;
3497
3498 spin_lock(&mbx->queue_lock);
3499
3500 while (!list_empty(head)) {
3501 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3502 list_del(&cmd->list);
3503 mbx->num_cmds--;
3504 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3505 }
3506
3507 spin_unlock(&mbx->queue_lock);
3508 }
3509
3510 static inline int qlcnic_83xx_check_mbx_status(struct qlcnic_adapter *adapter)
3511 {
3512 struct qlcnic_hardware_context *ahw = adapter->ahw;
3513 struct qlcnic_mailbox *mbx = ahw->mailbox;
3514 u32 host_mbx_ctrl;
3515
3516 if (!test_bit(QLC_83XX_MBX_READY, &mbx->status))
3517 return -EBUSY;
3518
3519 host_mbx_ctrl = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
3520 if (host_mbx_ctrl) {
3521 ahw->idc.collect_dump = 1;
3522 return -EIO;
3523 }
3524
3525 return 0;
3526 }
3527
3528 static inline void qlcnic_83xx_signal_mbx_cmd(struct qlcnic_adapter *adapter,
3529 u8 issue_cmd)
3530 {
3531 if (issue_cmd)
3532 QLCWRX(adapter->ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER);
3533 else
3534 QLCWRX(adapter->ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
3535 }
3536
3537 static inline void qlcnic_83xx_dequeue_mbx_cmd(struct qlcnic_adapter *adapter,
3538 struct qlcnic_cmd_args *cmd)
3539 {
3540 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3541
3542 spin_lock(&mbx->queue_lock);
3543
3544 list_del(&cmd->list);
3545 mbx->num_cmds--;
3546
3547 spin_unlock(&mbx->queue_lock);
3548
3549 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3550 }
3551
3552 static void qlcnic_83xx_encode_mbx_cmd(struct qlcnic_adapter *adapter,
3553 struct qlcnic_cmd_args *cmd)
3554 {
3555 u32 mbx_cmd, fw_hal_version, hdr_size, total_size, tmp;
3556 struct qlcnic_hardware_context *ahw = adapter->ahw;
3557 int i, j;
3558
3559 if (cmd->op_type != QLC_83XX_MBX_POST_BC_OP) {
3560 mbx_cmd = cmd->req.arg[0];
3561 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3562 for (i = 1; i < cmd->req.num; i++)
3563 writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i));
3564 } else {
3565 fw_hal_version = ahw->fw_hal_version;
3566 hdr_size = sizeof(struct qlcnic_bc_hdr) / sizeof(u32);
3567 total_size = cmd->pay_size + hdr_size;
3568 tmp = QLCNIC_CMD_BC_EVENT_SETUP | total_size << 16;
3569 mbx_cmd = tmp | fw_hal_version << 29;
3570 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3571
3572 /* Back channel specific operations bits */
3573 mbx_cmd = 0x1 | 1 << 4;
3574
3575 if (qlcnic_sriov_pf_check(adapter))
3576 mbx_cmd |= cmd->func_num << 5;
3577
3578 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 1));
3579
3580 for (i = 2, j = 0; j < hdr_size; i++, j++)
3581 writel(*(cmd->hdr++), QLCNIC_MBX_HOST(ahw, i));
3582 for (j = 0; j < cmd->pay_size; j++, i++)
3583 writel(*(cmd->pay++), QLCNIC_MBX_HOST(ahw, i));
3584 }
3585 }
3586
3587 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *adapter)
3588 {
3589 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3590
3591 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3592 complete(&mbx->completion);
3593 cancel_work_sync(&mbx->work);
3594 flush_workqueue(mbx->work_q);
3595 qlcnic_83xx_flush_mbx_queue(adapter);
3596 }
3597
3598 static inline int qlcnic_83xx_enqueue_mbx_cmd(struct qlcnic_adapter *adapter,
3599 struct qlcnic_cmd_args *cmd,
3600 unsigned long *timeout)
3601 {
3602 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3603
3604 if (test_bit(QLC_83XX_MBX_READY, &mbx->status)) {
3605 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3606 init_completion(&cmd->completion);
3607 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_UNKNOWN;
3608
3609 spin_lock(&mbx->queue_lock);
3610
3611 list_add_tail(&cmd->list, &mbx->cmd_q);
3612 mbx->num_cmds++;
3613 cmd->total_cmds = mbx->num_cmds;
3614 *timeout = cmd->total_cmds * QLC_83XX_MBX_TIMEOUT;
3615 queue_work(mbx->work_q, &mbx->work);
3616
3617 spin_unlock(&mbx->queue_lock);
3618
3619 return 0;
3620 }
3621
3622 return -EBUSY;
3623 }
3624
3625 static inline int qlcnic_83xx_check_mac_rcode(struct qlcnic_adapter *adapter,
3626 struct qlcnic_cmd_args *cmd)
3627 {
3628 u8 mac_cmd_rcode;
3629 u32 fw_data;
3630
3631 if (cmd->cmd_op == QLCNIC_CMD_CONFIG_MAC_VLAN) {
3632 fw_data = readl(QLCNIC_MBX_FW(adapter->ahw, 2));
3633 mac_cmd_rcode = (u8)fw_data;
3634 if (mac_cmd_rcode == QLC_83XX_NO_NIC_RESOURCE ||
3635 mac_cmd_rcode == QLC_83XX_MAC_PRESENT ||
3636 mac_cmd_rcode == QLC_83XX_MAC_ABSENT) {
3637 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3638 return QLCNIC_RCODE_SUCCESS;
3639 }
3640 }
3641
3642 return -EINVAL;
3643 }
3644
3645 static void qlcnic_83xx_decode_mbx_rsp(struct qlcnic_adapter *adapter,
3646 struct qlcnic_cmd_args *cmd)
3647 {
3648 struct qlcnic_hardware_context *ahw = adapter->ahw;
3649 struct device *dev = &adapter->pdev->dev;
3650 u8 mbx_err_code;
3651 u32 fw_data;
3652
3653 fw_data = readl(QLCNIC_MBX_FW(ahw, 0));
3654 mbx_err_code = QLCNIC_MBX_STATUS(fw_data);
3655 qlcnic_83xx_get_mbx_data(adapter, cmd);
3656
3657 switch (mbx_err_code) {
3658 case QLCNIC_MBX_RSP_OK:
3659 case QLCNIC_MBX_PORT_RSP_OK:
3660 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3661 break;
3662 default:
3663 if (!qlcnic_83xx_check_mac_rcode(adapter, cmd))
3664 break;
3665
3666 dev_err(dev, "%s: Mailbox command failed, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x, error=0x%x\n",
3667 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
3668 ahw->op_mode, mbx_err_code);
3669 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_FAILED;
3670 qlcnic_dump_mbx(adapter, cmd);
3671 }
3672
3673 return;
3674 }
3675
3676 static void qlcnic_83xx_mailbox_worker(struct work_struct *work)
3677 {
3678 struct qlcnic_mailbox *mbx = container_of(work, struct qlcnic_mailbox,
3679 work);
3680 struct qlcnic_adapter *adapter = mbx->adapter;
3681 struct qlcnic_mbx_ops *mbx_ops = mbx->ops;
3682 struct device *dev = &adapter->pdev->dev;
3683 atomic_t *rsp_status = &mbx->rsp_status;
3684 struct list_head *head = &mbx->cmd_q;
3685 struct qlcnic_hardware_context *ahw;
3686 struct qlcnic_cmd_args *cmd = NULL;
3687
3688 ahw = adapter->ahw;
3689
3690 while (true) {
3691 if (qlcnic_83xx_check_mbx_status(adapter))
3692 return;
3693
3694 atomic_set(rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3695
3696 spin_lock(&mbx->queue_lock);
3697
3698 if (list_empty(head)) {
3699 spin_unlock(&mbx->queue_lock);
3700 return;
3701 }
3702 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3703
3704 spin_unlock(&mbx->queue_lock);
3705
3706 mbx_ops->encode_cmd(adapter, cmd);
3707 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_REQUEST);
3708
3709 if (wait_for_completion_timeout(&mbx->completion,
3710 QLC_83XX_MBX_TIMEOUT)) {
3711 mbx_ops->decode_resp(adapter, cmd);
3712 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_COMPLETION);
3713 } else {
3714 dev_err(dev, "%s: Mailbox command timeout, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x\n",
3715 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
3716 ahw->op_mode);
3717 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3718 qlcnic_83xx_idc_request_reset(adapter,
3719 QLCNIC_FORCE_FW_DUMP_KEY);
3720 cmd->rsp_opcode = QLCNIC_RCODE_TIMEOUT;
3721 }
3722 mbx_ops->dequeue_cmd(adapter, cmd);
3723 }
3724 }
3725
3726 static struct qlcnic_mbx_ops qlcnic_83xx_mbx_ops = {
3727 .enqueue_cmd = qlcnic_83xx_enqueue_mbx_cmd,
3728 .dequeue_cmd = qlcnic_83xx_dequeue_mbx_cmd,
3729 .decode_resp = qlcnic_83xx_decode_mbx_rsp,
3730 .encode_cmd = qlcnic_83xx_encode_mbx_cmd,
3731 .nofity_fw = qlcnic_83xx_signal_mbx_cmd,
3732 };
3733
3734 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *adapter)
3735 {
3736 struct qlcnic_hardware_context *ahw = adapter->ahw;
3737 struct qlcnic_mailbox *mbx;
3738
3739 ahw->mailbox = kzalloc(sizeof(*mbx), GFP_KERNEL);
3740 if (!ahw->mailbox)
3741 return -ENOMEM;
3742
3743 mbx = ahw->mailbox;
3744 mbx->ops = &qlcnic_83xx_mbx_ops;
3745 mbx->adapter = adapter;
3746
3747 spin_lock_init(&mbx->queue_lock);
3748 spin_lock_init(&mbx->aen_lock);
3749 INIT_LIST_HEAD(&mbx->cmd_q);
3750 init_completion(&mbx->completion);
3751
3752 mbx->work_q = create_singlethread_workqueue("qlcnic_mailbox");
3753 if (mbx->work_q == NULL) {
3754 kfree(mbx);
3755 return -ENOMEM;
3756 }
3757
3758 INIT_WORK(&mbx->work, qlcnic_83xx_mailbox_worker);
3759 set_bit(QLC_83XX_MBX_READY, &mbx->status);
3760 return 0;
3761 }
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