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qlcnic: Replace poll mode mailbox interface with interrupt based mailbox interface
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic_83xx_hw.c
1 /*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
8 #include "qlcnic.h"
9 #include "qlcnic_sriov.h"
10 #include <linux/if_vlan.h>
11 #include <linux/ipv6.h>
12 #include <linux/ethtool.h>
13 #include <linux/interrupt.h>
14
15 #define QLCNIC_MAX_TX_QUEUES 1
16 #define RSS_HASHTYPE_IP_TCP 0x3
17 #define QLC_83XX_FW_MBX_CMD 0
18
19 static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = {
20 {QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1},
21 {QLCNIC_CMD_CONFIG_INTRPT, 18, 34},
22 {QLCNIC_CMD_CREATE_RX_CTX, 136, 27},
23 {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
24 {QLCNIC_CMD_CREATE_TX_CTX, 54, 18},
25 {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
26 {QLCNIC_CMD_CONFIGURE_MAC_LEARNING, 2, 1},
27 {QLCNIC_CMD_INTRPT_TEST, 22, 12},
28 {QLCNIC_CMD_SET_MTU, 3, 1},
29 {QLCNIC_CMD_READ_PHY, 4, 2},
30 {QLCNIC_CMD_WRITE_PHY, 5, 1},
31 {QLCNIC_CMD_READ_HW_REG, 4, 1},
32 {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
33 {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
34 {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
35 {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
36 {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
37 {QLCNIC_CMD_GET_PCI_INFO, 1, 66},
38 {QLCNIC_CMD_GET_NIC_INFO, 2, 19},
39 {QLCNIC_CMD_SET_NIC_INFO, 32, 1},
40 {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
41 {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
42 {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
43 {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
44 {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
45 {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
46 {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
47 {QLCNIC_CMD_CONFIG_PORT, 4, 1},
48 {QLCNIC_CMD_TEMP_SIZE, 1, 4},
49 {QLCNIC_CMD_GET_TEMP_HDR, 5, 5},
50 {QLCNIC_CMD_GET_LINK_EVENT, 2, 1},
51 {QLCNIC_CMD_CONFIG_MAC_VLAN, 4, 3},
52 {QLCNIC_CMD_CONFIG_INTR_COAL, 6, 1},
53 {QLCNIC_CMD_CONFIGURE_RSS, 14, 1},
54 {QLCNIC_CMD_CONFIGURE_LED, 2, 1},
55 {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE, 2, 1},
56 {QLCNIC_CMD_CONFIGURE_HW_LRO, 2, 1},
57 {QLCNIC_CMD_GET_STATISTICS, 2, 80},
58 {QLCNIC_CMD_SET_PORT_CONFIG, 2, 1},
59 {QLCNIC_CMD_GET_PORT_CONFIG, 2, 2},
60 {QLCNIC_CMD_GET_LINK_STATUS, 2, 4},
61 {QLCNIC_CMD_IDC_ACK, 5, 1},
62 {QLCNIC_CMD_INIT_NIC_FUNC, 2, 1},
63 {QLCNIC_CMD_STOP_NIC_FUNC, 2, 1},
64 {QLCNIC_CMD_SET_LED_CONFIG, 5, 1},
65 {QLCNIC_CMD_GET_LED_CONFIG, 1, 5},
66 {QLCNIC_CMD_83XX_SET_DRV_VER, 4, 1},
67 {QLCNIC_CMD_ADD_RCV_RINGS, 130, 26},
68 {QLCNIC_CMD_CONFIG_VPORT, 4, 4},
69 {QLCNIC_CMD_BC_EVENT_SETUP, 2, 1},
70 };
71
72 const u32 qlcnic_83xx_ext_reg_tbl[] = {
73 0x38CC, /* Global Reset */
74 0x38F0, /* Wildcard */
75 0x38FC, /* Informant */
76 0x3038, /* Host MBX ctrl */
77 0x303C, /* FW MBX ctrl */
78 0x355C, /* BOOT LOADER ADDRESS REG */
79 0x3560, /* BOOT LOADER SIZE REG */
80 0x3564, /* FW IMAGE ADDR REG */
81 0x1000, /* MBX intr enable */
82 0x1200, /* Default Intr mask */
83 0x1204, /* Default Interrupt ID */
84 0x3780, /* QLC_83XX_IDC_MAJ_VERSION */
85 0x3784, /* QLC_83XX_IDC_DEV_STATE */
86 0x3788, /* QLC_83XX_IDC_DRV_PRESENCE */
87 0x378C, /* QLC_83XX_IDC_DRV_ACK */
88 0x3790, /* QLC_83XX_IDC_CTRL */
89 0x3794, /* QLC_83XX_IDC_DRV_AUDIT */
90 0x3798, /* QLC_83XX_IDC_MIN_VERSION */
91 0x379C, /* QLC_83XX_RECOVER_DRV_LOCK */
92 0x37A0, /* QLC_83XX_IDC_PF_0 */
93 0x37A4, /* QLC_83XX_IDC_PF_1 */
94 0x37A8, /* QLC_83XX_IDC_PF_2 */
95 0x37AC, /* QLC_83XX_IDC_PF_3 */
96 0x37B0, /* QLC_83XX_IDC_PF_4 */
97 0x37B4, /* QLC_83XX_IDC_PF_5 */
98 0x37B8, /* QLC_83XX_IDC_PF_6 */
99 0x37BC, /* QLC_83XX_IDC_PF_7 */
100 0x37C0, /* QLC_83XX_IDC_PF_8 */
101 0x37C4, /* QLC_83XX_IDC_PF_9 */
102 0x37C8, /* QLC_83XX_IDC_PF_10 */
103 0x37CC, /* QLC_83XX_IDC_PF_11 */
104 0x37D0, /* QLC_83XX_IDC_PF_12 */
105 0x37D4, /* QLC_83XX_IDC_PF_13 */
106 0x37D8, /* QLC_83XX_IDC_PF_14 */
107 0x37DC, /* QLC_83XX_IDC_PF_15 */
108 0x37E0, /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */
109 0x37E4, /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */
110 0x37F0, /* QLC_83XX_DRV_OP_MODE */
111 0x37F4, /* QLC_83XX_VNIC_STATE */
112 0x3868, /* QLC_83XX_DRV_LOCK */
113 0x386C, /* QLC_83XX_DRV_UNLOCK */
114 0x3504, /* QLC_83XX_DRV_LOCK_ID */
115 0x34A4, /* QLC_83XX_ASIC_TEMP */
116 };
117
118 const u32 qlcnic_83xx_reg_tbl[] = {
119 0x34A8, /* PEG_HALT_STAT1 */
120 0x34AC, /* PEG_HALT_STAT2 */
121 0x34B0, /* FW_HEARTBEAT */
122 0x3500, /* FLASH LOCK_ID */
123 0x3528, /* FW_CAPABILITIES */
124 0x3538, /* Driver active, DRV_REG0 */
125 0x3540, /* Device state, DRV_REG1 */
126 0x3544, /* Driver state, DRV_REG2 */
127 0x3548, /* Driver scratch, DRV_REG3 */
128 0x354C, /* Device partiton info, DRV_REG4 */
129 0x3524, /* Driver IDC ver, DRV_REG5 */
130 0x3550, /* FW_VER_MAJOR */
131 0x3554, /* FW_VER_MINOR */
132 0x3558, /* FW_VER_SUB */
133 0x359C, /* NPAR STATE */
134 0x35FC, /* FW_IMG_VALID */
135 0x3650, /* CMD_PEG_STATE */
136 0x373C, /* RCV_PEG_STATE */
137 0x37B4, /* ASIC TEMP */
138 0x356C, /* FW API */
139 0x3570, /* DRV OP MODE */
140 0x3850, /* FLASH LOCK */
141 0x3854, /* FLASH UNLOCK */
142 };
143
144 static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = {
145 .read_crb = qlcnic_83xx_read_crb,
146 .write_crb = qlcnic_83xx_write_crb,
147 .read_reg = qlcnic_83xx_rd_reg_indirect,
148 .write_reg = qlcnic_83xx_wrt_reg_indirect,
149 .get_mac_address = qlcnic_83xx_get_mac_address,
150 .setup_intr = qlcnic_83xx_setup_intr,
151 .alloc_mbx_args = qlcnic_83xx_alloc_mbx_args,
152 .mbx_cmd = qlcnic_83xx_issue_cmd,
153 .get_func_no = qlcnic_83xx_get_func_no,
154 .api_lock = qlcnic_83xx_cam_lock,
155 .api_unlock = qlcnic_83xx_cam_unlock,
156 .add_sysfs = qlcnic_83xx_add_sysfs,
157 .remove_sysfs = qlcnic_83xx_remove_sysfs,
158 .process_lb_rcv_ring_diag = qlcnic_83xx_process_rcv_ring_diag,
159 .create_rx_ctx = qlcnic_83xx_create_rx_ctx,
160 .create_tx_ctx = qlcnic_83xx_create_tx_ctx,
161 .del_rx_ctx = qlcnic_83xx_del_rx_ctx,
162 .del_tx_ctx = qlcnic_83xx_del_tx_ctx,
163 .setup_link_event = qlcnic_83xx_setup_link_event,
164 .get_nic_info = qlcnic_83xx_get_nic_info,
165 .get_pci_info = qlcnic_83xx_get_pci_info,
166 .set_nic_info = qlcnic_83xx_set_nic_info,
167 .change_macvlan = qlcnic_83xx_sre_macaddr_change,
168 .napi_enable = qlcnic_83xx_napi_enable,
169 .napi_disable = qlcnic_83xx_napi_disable,
170 .config_intr_coal = qlcnic_83xx_config_intr_coal,
171 .config_rss = qlcnic_83xx_config_rss,
172 .config_hw_lro = qlcnic_83xx_config_hw_lro,
173 .config_promisc_mode = qlcnic_83xx_nic_set_promisc,
174 .change_l2_filter = qlcnic_83xx_change_l2_filter,
175 .get_board_info = qlcnic_83xx_get_port_info,
176 .set_mac_filter_count = qlcnic_83xx_set_mac_filter_count,
177 .free_mac_list = qlcnic_82xx_free_mac_list,
178 };
179
180 static struct qlcnic_nic_template qlcnic_83xx_ops = {
181 .config_bridged_mode = qlcnic_config_bridged_mode,
182 .config_led = qlcnic_config_led,
183 .request_reset = qlcnic_83xx_idc_request_reset,
184 .cancel_idc_work = qlcnic_83xx_idc_exit,
185 .napi_add = qlcnic_83xx_napi_add,
186 .napi_del = qlcnic_83xx_napi_del,
187 .config_ipaddr = qlcnic_83xx_config_ipaddr,
188 .clear_legacy_intr = qlcnic_83xx_clear_legacy_intr,
189 .shutdown = qlcnic_83xx_shutdown,
190 .resume = qlcnic_83xx_resume,
191 };
192
193 void qlcnic_83xx_register_map(struct qlcnic_hardware_context *ahw)
194 {
195 ahw->hw_ops = &qlcnic_83xx_hw_ops;
196 ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl;
197 ahw->ext_reg_tbl = (u32 *)qlcnic_83xx_ext_reg_tbl;
198 }
199
200 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *adapter)
201 {
202 u32 fw_major, fw_minor, fw_build;
203 struct pci_dev *pdev = adapter->pdev;
204
205 fw_major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
206 fw_minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
207 fw_build = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
208 adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build);
209
210 dev_info(&pdev->dev, "Driver v%s, firmware version %d.%d.%d\n",
211 QLCNIC_LINUX_VERSIONID, fw_major, fw_minor, fw_build);
212
213 return adapter->fw_version;
214 }
215
216 static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr)
217 {
218 void __iomem *base;
219 u32 val;
220
221 base = adapter->ahw->pci_base0 +
222 QLC_83XX_CRB_WIN_FUNC(adapter->ahw->pci_func);
223 writel(addr, base);
224 val = readl(base);
225 if (val != addr)
226 return -EIO;
227
228 return 0;
229 }
230
231 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr)
232 {
233 int ret;
234 struct qlcnic_hardware_context *ahw = adapter->ahw;
235
236 ret = __qlcnic_set_win_base(adapter, (u32) addr);
237 if (!ret) {
238 return QLCRDX(ahw, QLCNIC_WILDCARD);
239 } else {
240 dev_err(&adapter->pdev->dev,
241 "%s failed, addr = 0x%x\n", __func__, (int)addr);
242 return -EIO;
243 }
244 }
245
246 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
247 u32 data)
248 {
249 int err;
250 struct qlcnic_hardware_context *ahw = adapter->ahw;
251
252 err = __qlcnic_set_win_base(adapter, (u32) addr);
253 if (!err) {
254 QLCWRX(ahw, QLCNIC_WILDCARD, data);
255 return 0;
256 } else {
257 dev_err(&adapter->pdev->dev,
258 "%s failed, addr = 0x%x data = 0x%x\n",
259 __func__, (int)addr, data);
260 return err;
261 }
262 }
263
264 int qlcnic_83xx_setup_intr(struct qlcnic_adapter *adapter, u8 num_intr)
265 {
266 int err, i, num_msix;
267 struct qlcnic_hardware_context *ahw = adapter->ahw;
268
269 if (!num_intr)
270 num_intr = QLCNIC_DEF_NUM_STS_DESC_RINGS;
271 num_msix = rounddown_pow_of_two(min_t(int, num_online_cpus(),
272 num_intr));
273 /* account for AEN interrupt MSI-X based interrupts */
274 num_msix += 1;
275
276 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
277 num_msix += adapter->max_drv_tx_rings;
278
279 err = qlcnic_enable_msix(adapter, num_msix);
280 if (err == -ENOMEM)
281 return err;
282 if (adapter->flags & QLCNIC_MSIX_ENABLED)
283 num_msix = adapter->ahw->num_msix;
284 else {
285 if (qlcnic_sriov_vf_check(adapter))
286 return -EINVAL;
287 num_msix = 1;
288 }
289 /* setup interrupt mapping table for fw */
290 ahw->intr_tbl = vzalloc(num_msix *
291 sizeof(struct qlcnic_intrpt_config));
292 if (!ahw->intr_tbl)
293 return -ENOMEM;
294 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
295 /* MSI-X enablement failed, use legacy interrupt */
296 adapter->tgt_status_reg = ahw->pci_base0 + QLC_83XX_INTX_PTR;
297 adapter->tgt_mask_reg = ahw->pci_base0 + QLC_83XX_INTX_MASK;
298 adapter->isr_int_vec = ahw->pci_base0 + QLC_83XX_INTX_TRGR;
299 adapter->msix_entries[0].vector = adapter->pdev->irq;
300 dev_info(&adapter->pdev->dev, "using legacy interrupt\n");
301 }
302
303 for (i = 0; i < num_msix; i++) {
304 if (adapter->flags & QLCNIC_MSIX_ENABLED)
305 ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX;
306 else
307 ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX;
308 ahw->intr_tbl[i].id = i;
309 ahw->intr_tbl[i].src = 0;
310 }
311 return 0;
312 }
313
314 inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter)
315 {
316 writel(0, adapter->tgt_mask_reg);
317 }
318
319 inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter *adapter)
320 {
321 writel(1, adapter->tgt_mask_reg);
322 }
323
324 /* Enable MSI-x and INT-x interrupts */
325 void qlcnic_83xx_enable_intr(struct qlcnic_adapter *adapter,
326 struct qlcnic_host_sds_ring *sds_ring)
327 {
328 writel(0, sds_ring->crb_intr_mask);
329 }
330
331 /* Disable MSI-x and INT-x interrupts */
332 void qlcnic_83xx_disable_intr(struct qlcnic_adapter *adapter,
333 struct qlcnic_host_sds_ring *sds_ring)
334 {
335 writel(1, sds_ring->crb_intr_mask);
336 }
337
338 inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
339 *adapter)
340 {
341 u32 mask;
342
343 /* Mailbox in MSI-x mode and Legacy Interrupt share the same
344 * source register. We could be here before contexts are created
345 * and sds_ring->crb_intr_mask has not been initialized, calculate
346 * BAR offset for Interrupt Source Register
347 */
348 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
349 writel(0, adapter->ahw->pci_base0 + mask);
350 }
351
352 void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter)
353 {
354 u32 mask;
355
356 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
357 writel(1, adapter->ahw->pci_base0 + mask);
358 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0);
359 }
360
361 static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter,
362 struct qlcnic_cmd_args *cmd)
363 {
364 int i;
365
366 if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
367 return;
368
369 for (i = 0; i < cmd->rsp.num; i++)
370 cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i));
371 }
372
373 irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter)
374 {
375 u32 intr_val;
376 struct qlcnic_hardware_context *ahw = adapter->ahw;
377 int retries = 0;
378
379 intr_val = readl(adapter->tgt_status_reg);
380
381 if (!QLC_83XX_VALID_INTX_BIT31(intr_val))
382 return IRQ_NONE;
383
384 if (QLC_83XX_INTX_FUNC(intr_val) != adapter->ahw->pci_func) {
385 adapter->stats.spurious_intr++;
386 return IRQ_NONE;
387 }
388 /* The barrier is required to ensure writes to the registers */
389 wmb();
390
391 /* clear the interrupt trigger control register */
392 writel(0, adapter->isr_int_vec);
393 intr_val = readl(adapter->isr_int_vec);
394 do {
395 intr_val = readl(adapter->tgt_status_reg);
396 if (QLC_83XX_INTX_FUNC(intr_val) != ahw->pci_func)
397 break;
398 retries++;
399 } while (QLC_83XX_VALID_INTX_BIT30(intr_val) &&
400 (retries < QLC_83XX_LEGACY_INTX_MAX_RETRY));
401
402 return IRQ_HANDLED;
403 }
404
405 static inline void qlcnic_83xx_notify_mbx_response(struct qlcnic_mailbox *mbx)
406 {
407 atomic_set(&mbx->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
408 complete(&mbx->completion);
409 }
410
411 static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter *adapter)
412 {
413 u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
414 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
415 unsigned long flags;
416
417 spin_lock_irqsave(&mbx->aen_lock, flags);
418 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
419 if (!(resp & QLCNIC_SET_OWNER))
420 goto out;
421
422 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
423 if (event & QLCNIC_MBX_ASYNC_EVENT) {
424 __qlcnic_83xx_process_aen(adapter);
425 } else {
426 if (atomic_read(&mbx->rsp_status) != rsp_status)
427 qlcnic_83xx_notify_mbx_response(mbx);
428 }
429 out:
430 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
431 spin_unlock_irqrestore(&mbx->aen_lock, flags);
432 }
433
434 irqreturn_t qlcnic_83xx_intr(int irq, void *data)
435 {
436 struct qlcnic_adapter *adapter = data;
437 struct qlcnic_host_sds_ring *sds_ring;
438 struct qlcnic_hardware_context *ahw = adapter->ahw;
439
440 if (qlcnic_83xx_clear_legacy_intr(adapter) == IRQ_NONE)
441 return IRQ_NONE;
442
443 qlcnic_83xx_poll_process_aen(adapter);
444
445 if (ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
446 ahw->diag_cnt++;
447 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
448 return IRQ_HANDLED;
449 }
450
451 if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
452 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
453 } else {
454 sds_ring = &adapter->recv_ctx->sds_rings[0];
455 napi_schedule(&sds_ring->napi);
456 }
457
458 return IRQ_HANDLED;
459 }
460
461 irqreturn_t qlcnic_83xx_tmp_intr(int irq, void *data)
462 {
463 struct qlcnic_host_sds_ring *sds_ring = data;
464 struct qlcnic_adapter *adapter = sds_ring->adapter;
465
466 if (adapter->flags & QLCNIC_MSIX_ENABLED)
467 goto done;
468
469 if (adapter->nic_ops->clear_legacy_intr(adapter) == IRQ_NONE)
470 return IRQ_NONE;
471
472 done:
473 adapter->ahw->diag_cnt++;
474 qlcnic_83xx_enable_intr(adapter, sds_ring);
475
476 return IRQ_HANDLED;
477 }
478
479 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *adapter)
480 {
481 u32 num_msix;
482
483 if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
484 qlcnic_83xx_set_legacy_intr_mask(adapter);
485
486 qlcnic_83xx_disable_mbx_intr(adapter);
487
488 if (adapter->flags & QLCNIC_MSIX_ENABLED)
489 num_msix = adapter->ahw->num_msix - 1;
490 else
491 num_msix = 0;
492
493 msleep(20);
494 synchronize_irq(adapter->msix_entries[num_msix].vector);
495 free_irq(adapter->msix_entries[num_msix].vector, adapter);
496 }
497
498 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *adapter)
499 {
500 irq_handler_t handler;
501 u32 val;
502 int err = 0;
503 unsigned long flags = 0;
504
505 if (!(adapter->flags & QLCNIC_MSI_ENABLED) &&
506 !(adapter->flags & QLCNIC_MSIX_ENABLED))
507 flags |= IRQF_SHARED;
508
509 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
510 handler = qlcnic_83xx_handle_aen;
511 val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector;
512 err = request_irq(val, handler, flags, "qlcnic-MB", adapter);
513 if (err) {
514 dev_err(&adapter->pdev->dev,
515 "failed to register MBX interrupt\n");
516 return err;
517 }
518 } else {
519 handler = qlcnic_83xx_intr;
520 val = adapter->msix_entries[0].vector;
521 err = request_irq(val, handler, flags, "qlcnic", adapter);
522 if (err) {
523 dev_err(&adapter->pdev->dev,
524 "failed to register INTx interrupt\n");
525 return err;
526 }
527 qlcnic_83xx_clear_legacy_intr_mask(adapter);
528 }
529
530 /* Enable mailbox interrupt */
531 qlcnic_83xx_enable_mbx_interrupt(adapter);
532
533 return err;
534 }
535
536 void qlcnic_83xx_get_func_no(struct qlcnic_adapter *adapter)
537 {
538 u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT);
539 adapter->ahw->pci_func = (val >> 24) & 0xff;
540 }
541
542 int qlcnic_83xx_cam_lock(struct qlcnic_adapter *adapter)
543 {
544 void __iomem *addr;
545 u32 val, limit = 0;
546
547 struct qlcnic_hardware_context *ahw = adapter->ahw;
548
549 addr = ahw->pci_base0 + QLC_83XX_SEM_LOCK_FUNC(ahw->pci_func);
550 do {
551 val = readl(addr);
552 if (val) {
553 /* write the function number to register */
554 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER,
555 ahw->pci_func);
556 return 0;
557 }
558 usleep_range(1000, 2000);
559 } while (++limit <= QLCNIC_PCIE_SEM_TIMEOUT);
560
561 return -EIO;
562 }
563
564 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter)
565 {
566 void __iomem *addr;
567 u32 val;
568 struct qlcnic_hardware_context *ahw = adapter->ahw;
569
570 addr = ahw->pci_base0 + QLC_83XX_SEM_UNLOCK_FUNC(ahw->pci_func);
571 val = readl(addr);
572 }
573
574 void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
575 loff_t offset, size_t size)
576 {
577 int ret;
578 u32 data;
579
580 if (qlcnic_api_lock(adapter)) {
581 dev_err(&adapter->pdev->dev,
582 "%s: failed to acquire lock. addr offset 0x%x\n",
583 __func__, (u32)offset);
584 return;
585 }
586
587 ret = qlcnic_83xx_rd_reg_indirect(adapter, (u32) offset);
588 qlcnic_api_unlock(adapter);
589
590 if (ret == -EIO) {
591 dev_err(&adapter->pdev->dev,
592 "%s: failed. addr offset 0x%x\n",
593 __func__, (u32)offset);
594 return;
595 }
596 data = ret;
597 memcpy(buf, &data, size);
598 }
599
600 void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
601 loff_t offset, size_t size)
602 {
603 u32 data;
604
605 memcpy(&data, buf, size);
606 qlcnic_83xx_wrt_reg_indirect(adapter, (u32) offset, data);
607 }
608
609 int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter)
610 {
611 int status;
612
613 status = qlcnic_83xx_get_port_config(adapter);
614 if (status) {
615 dev_err(&adapter->pdev->dev,
616 "Get Port Info failed\n");
617 } else {
618 if (QLC_83XX_SFP_10G_CAPABLE(adapter->ahw->port_config))
619 adapter->ahw->port_type = QLCNIC_XGBE;
620 else
621 adapter->ahw->port_type = QLCNIC_GBE;
622
623 if (QLC_83XX_AUTONEG(adapter->ahw->port_config))
624 adapter->ahw->link_autoneg = AUTONEG_ENABLE;
625 }
626 return status;
627 }
628
629 void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *adapter)
630 {
631 struct qlcnic_hardware_context *ahw = adapter->ahw;
632 u16 act_pci_fn = ahw->act_pci_func;
633 u16 count;
634
635 ahw->max_mc_count = QLC_83XX_MAX_MC_COUNT;
636 if (act_pci_fn <= 2)
637 count = (QLC_83XX_MAX_UC_COUNT - QLC_83XX_MAX_MC_COUNT) /
638 act_pci_fn;
639 else
640 count = (QLC_83XX_LB_MAX_FILTERS - QLC_83XX_MAX_MC_COUNT) /
641 act_pci_fn;
642 ahw->max_uc_count = count;
643 }
644
645 void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *adapter)
646 {
647 u32 val;
648
649 if (adapter->flags & QLCNIC_MSIX_ENABLED)
650 val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8);
651 else
652 val = BIT_2;
653
654 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val);
655 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
656 }
657
658 void qlcnic_83xx_check_vf(struct qlcnic_adapter *adapter,
659 const struct pci_device_id *ent)
660 {
661 u32 op_mode, priv_level;
662 struct qlcnic_hardware_context *ahw = adapter->ahw;
663
664 ahw->fw_hal_version = 2;
665 qlcnic_get_func_no(adapter);
666
667 if (qlcnic_sriov_vf_check(adapter)) {
668 qlcnic_sriov_vf_set_ops(adapter);
669 return;
670 }
671
672 /* Determine function privilege level */
673 op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE);
674 if (op_mode == QLC_83XX_DEFAULT_OPMODE)
675 priv_level = QLCNIC_MGMT_FUNC;
676 else
677 priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode,
678 ahw->pci_func);
679
680 if (priv_level == QLCNIC_NON_PRIV_FUNC) {
681 ahw->op_mode = QLCNIC_NON_PRIV_FUNC;
682 dev_info(&adapter->pdev->dev,
683 "HAL Version: %d Non Privileged function\n",
684 ahw->fw_hal_version);
685 adapter->nic_ops = &qlcnic_vf_ops;
686 } else {
687 if (pci_find_ext_capability(adapter->pdev,
688 PCI_EXT_CAP_ID_SRIOV))
689 set_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state);
690 adapter->nic_ops = &qlcnic_83xx_ops;
691 }
692 }
693
694 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
695 u32 data[]);
696 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
697 u32 data[]);
698
699 static void qlcnic_dump_mbx(struct qlcnic_adapter *adapter,
700 struct qlcnic_cmd_args *cmd)
701 {
702 int i;
703
704 if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
705 return;
706
707 dev_info(&adapter->pdev->dev,
708 "Host MBX regs(%d)\n", cmd->req.num);
709 for (i = 0; i < cmd->req.num; i++) {
710 if (i && !(i % 8))
711 pr_info("\n");
712 pr_info("%08x ", cmd->req.arg[i]);
713 }
714 pr_info("\n");
715 dev_info(&adapter->pdev->dev,
716 "FW MBX regs(%d)\n", cmd->rsp.num);
717 for (i = 0; i < cmd->rsp.num; i++) {
718 if (i && !(i % 8))
719 pr_info("\n");
720 pr_info("%08x ", cmd->rsp.arg[i]);
721 }
722 pr_info("\n");
723 }
724
725 static inline void
726 qlcnic_83xx_poll_for_mbx_completion(struct qlcnic_adapter *adapter,
727 struct qlcnic_cmd_args *cmd)
728 {
729 struct qlcnic_hardware_context *ahw = adapter->ahw;
730 int opcode = LSW(cmd->req.arg[0]);
731 unsigned long max_loops;
732
733 max_loops = cmd->total_cmds * QLC_83XX_MBX_CMD_LOOP;
734
735 for (; max_loops; max_loops--) {
736 if (atomic_read(&cmd->rsp_status) ==
737 QLC_83XX_MBX_RESPONSE_ARRIVED)
738 return;
739
740 udelay(1);
741 }
742
743 dev_err(&adapter->pdev->dev,
744 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
745 __func__, opcode, cmd->type, ahw->pci_func, ahw->op_mode);
746 flush_workqueue(ahw->mailbox->work_q);
747 return;
748 }
749
750 int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *adapter,
751 struct qlcnic_cmd_args *cmd)
752 {
753 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
754 struct qlcnic_hardware_context *ahw = adapter->ahw;
755 int cmd_type, err, opcode;
756 unsigned long timeout;
757
758 opcode = LSW(cmd->req.arg[0]);
759 cmd_type = cmd->type;
760 err = mbx->ops->enqueue_cmd(adapter, cmd, &timeout);
761 if (err) {
762 dev_err(&adapter->pdev->dev,
763 "%s: Mailbox not available, cmd_op=0x%x, cmd_context=0x%x, pci_func=0x%x, op_mode=0x%x\n",
764 __func__, opcode, cmd->type, ahw->pci_func,
765 ahw->op_mode);
766 return err;
767 }
768
769 switch (cmd_type) {
770 case QLC_83XX_MBX_CMD_WAIT:
771 if (!wait_for_completion_timeout(&cmd->completion, timeout)) {
772 dev_err(&adapter->pdev->dev,
773 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
774 __func__, opcode, cmd_type, ahw->pci_func,
775 ahw->op_mode);
776 flush_workqueue(mbx->work_q);
777 }
778 break;
779 case QLC_83XX_MBX_CMD_NO_WAIT:
780 return 0;
781 case QLC_83XX_MBX_CMD_BUSY_WAIT:
782 qlcnic_83xx_poll_for_mbx_completion(adapter, cmd);
783 break;
784 default:
785 dev_err(&adapter->pdev->dev,
786 "%s: Invalid mailbox command, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
787 __func__, opcode, cmd_type, ahw->pci_func,
788 ahw->op_mode);
789 qlcnic_83xx_detach_mailbox_work(adapter);
790 }
791
792 return cmd->rsp_opcode;
793 }
794
795 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
796 struct qlcnic_adapter *adapter, u32 type)
797 {
798 int i, size;
799 u32 temp;
800 const struct qlcnic_mailbox_metadata *mbx_tbl;
801
802 memset(mbx, 0, sizeof(struct qlcnic_cmd_args));
803 mbx_tbl = qlcnic_83xx_mbx_tbl;
804 size = ARRAY_SIZE(qlcnic_83xx_mbx_tbl);
805 for (i = 0; i < size; i++) {
806 if (type == mbx_tbl[i].cmd) {
807 mbx->op_type = QLC_83XX_FW_MBX_CMD;
808 mbx->req.num = mbx_tbl[i].in_args;
809 mbx->rsp.num = mbx_tbl[i].out_args;
810 mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
811 GFP_ATOMIC);
812 if (!mbx->req.arg)
813 return -ENOMEM;
814 mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
815 GFP_ATOMIC);
816 if (!mbx->rsp.arg) {
817 kfree(mbx->req.arg);
818 mbx->req.arg = NULL;
819 return -ENOMEM;
820 }
821 memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
822 memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
823 temp = adapter->ahw->fw_hal_version << 29;
824 mbx->req.arg[0] = (type | (mbx->req.num << 16) | temp);
825 mbx->cmd_op = type;
826 return 0;
827 }
828 }
829 return -EINVAL;
830 }
831
832 void qlcnic_83xx_idc_aen_work(struct work_struct *work)
833 {
834 struct qlcnic_adapter *adapter;
835 struct qlcnic_cmd_args cmd;
836 int i, err = 0;
837
838 adapter = container_of(work, struct qlcnic_adapter, idc_aen_work.work);
839 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_IDC_ACK);
840 if (err)
841 return;
842
843 for (i = 1; i < QLC_83XX_MBX_AEN_CNT; i++)
844 cmd.req.arg[i] = adapter->ahw->mbox_aen[i];
845
846 err = qlcnic_issue_cmd(adapter, &cmd);
847 if (err)
848 dev_info(&adapter->pdev->dev,
849 "%s: Mailbox IDC ACK failed.\n", __func__);
850 qlcnic_free_mbx_args(&cmd);
851 }
852
853 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
854 u32 data[])
855 {
856 dev_dbg(&adapter->pdev->dev, "Completion AEN:0x%x.\n",
857 QLCNIC_MBX_RSP(data[0]));
858 clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status);
859 return;
860 }
861
862 void __qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
863 {
864 u32 event[QLC_83XX_MBX_AEN_CNT];
865 int i;
866 struct qlcnic_hardware_context *ahw = adapter->ahw;
867
868 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
869 event[i] = readl(QLCNIC_MBX_FW(ahw, i));
870
871 switch (QLCNIC_MBX_RSP(event[0])) {
872
873 case QLCNIC_MBX_LINK_EVENT:
874 qlcnic_83xx_handle_link_aen(adapter, event);
875 break;
876 case QLCNIC_MBX_COMP_EVENT:
877 qlcnic_83xx_handle_idc_comp_aen(adapter, event);
878 break;
879 case QLCNIC_MBX_REQUEST_EVENT:
880 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
881 adapter->ahw->mbox_aen[i] = QLCNIC_MBX_RSP(event[i]);
882 queue_delayed_work(adapter->qlcnic_wq,
883 &adapter->idc_aen_work, 0);
884 break;
885 case QLCNIC_MBX_TIME_EXTEND_EVENT:
886 break;
887 case QLCNIC_MBX_BC_EVENT:
888 qlcnic_sriov_handle_bc_event(adapter, event[1]);
889 break;
890 case QLCNIC_MBX_SFP_INSERT_EVENT:
891 dev_info(&adapter->pdev->dev, "SFP+ Insert AEN:0x%x.\n",
892 QLCNIC_MBX_RSP(event[0]));
893 break;
894 case QLCNIC_MBX_SFP_REMOVE_EVENT:
895 dev_info(&adapter->pdev->dev, "SFP Removed AEN:0x%x.\n",
896 QLCNIC_MBX_RSP(event[0]));
897 break;
898 default:
899 dev_dbg(&adapter->pdev->dev, "Unsupported AEN:0x%x.\n",
900 QLCNIC_MBX_RSP(event[0]));
901 break;
902 }
903
904 QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
905 }
906
907 static void qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
908 {
909 u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
910 struct qlcnic_hardware_context *ahw = adapter->ahw;
911 struct qlcnic_mailbox *mbx = ahw->mailbox;
912 unsigned long flags;
913
914 spin_lock_irqsave(&mbx->aen_lock, flags);
915 resp = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL);
916 if (resp & QLCNIC_SET_OWNER) {
917 event = readl(QLCNIC_MBX_FW(ahw, 0));
918 if (event & QLCNIC_MBX_ASYNC_EVENT) {
919 __qlcnic_83xx_process_aen(adapter);
920 } else {
921 if (atomic_read(&mbx->rsp_status) != rsp_status)
922 qlcnic_83xx_notify_mbx_response(mbx);
923 }
924 }
925 spin_unlock_irqrestore(&mbx->aen_lock, flags);
926 }
927
928 static void qlcnic_83xx_mbx_poll_work(struct work_struct *work)
929 {
930 struct qlcnic_adapter *adapter;
931
932 adapter = container_of(work, struct qlcnic_adapter, mbx_poll_work.work);
933
934 if (!test_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
935 return;
936
937 qlcnic_83xx_process_aen(adapter);
938 queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work,
939 (HZ / 10));
940 }
941
942 void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *adapter)
943 {
944 if (test_and_set_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
945 return;
946
947 INIT_DELAYED_WORK(&adapter->mbx_poll_work, qlcnic_83xx_mbx_poll_work);
948 }
949
950 void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *adapter)
951 {
952 if (!test_and_clear_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
953 return;
954 cancel_delayed_work_sync(&adapter->mbx_poll_work);
955 }
956
957 static int qlcnic_83xx_add_rings(struct qlcnic_adapter *adapter)
958 {
959 int index, i, err, sds_mbx_size;
960 u32 *buf, intrpt_id, intr_mask;
961 u16 context_id;
962 u8 num_sds;
963 struct qlcnic_cmd_args cmd;
964 struct qlcnic_host_sds_ring *sds;
965 struct qlcnic_sds_mbx sds_mbx;
966 struct qlcnic_add_rings_mbx_out *mbx_out;
967 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
968 struct qlcnic_hardware_context *ahw = adapter->ahw;
969
970 sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
971 context_id = recv_ctx->context_id;
972 num_sds = (adapter->max_sds_rings - QLCNIC_MAX_RING_SETS);
973 ahw->hw_ops->alloc_mbx_args(&cmd, adapter,
974 QLCNIC_CMD_ADD_RCV_RINGS);
975 cmd.req.arg[1] = 0 | (num_sds << 8) | (context_id << 16);
976
977 /* set up status rings, mbx 2-81 */
978 index = 2;
979 for (i = 8; i < adapter->max_sds_rings; i++) {
980 memset(&sds_mbx, 0, sds_mbx_size);
981 sds = &recv_ctx->sds_rings[i];
982 sds->consumer = 0;
983 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
984 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
985 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
986 sds_mbx.sds_ring_size = sds->num_desc;
987
988 if (adapter->flags & QLCNIC_MSIX_ENABLED)
989 intrpt_id = ahw->intr_tbl[i].id;
990 else
991 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
992
993 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
994 sds_mbx.intrpt_id = intrpt_id;
995 else
996 sds_mbx.intrpt_id = 0xffff;
997 sds_mbx.intrpt_val = 0;
998 buf = &cmd.req.arg[index];
999 memcpy(buf, &sds_mbx, sds_mbx_size);
1000 index += sds_mbx_size / sizeof(u32);
1001 }
1002
1003 /* send the mailbox command */
1004 err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1005 if (err) {
1006 dev_err(&adapter->pdev->dev,
1007 "Failed to add rings %d\n", err);
1008 goto out;
1009 }
1010
1011 mbx_out = (struct qlcnic_add_rings_mbx_out *)&cmd.rsp.arg[1];
1012 index = 0;
1013 /* status descriptor ring */
1014 for (i = 8; i < adapter->max_sds_rings; i++) {
1015 sds = &recv_ctx->sds_rings[i];
1016 sds->crb_sts_consumer = ahw->pci_base0 +
1017 mbx_out->host_csmr[index];
1018 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1019 intr_mask = ahw->intr_tbl[i].src;
1020 else
1021 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1022
1023 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1024 index++;
1025 }
1026 out:
1027 qlcnic_free_mbx_args(&cmd);
1028 return err;
1029 }
1030
1031 void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *adapter)
1032 {
1033 int err;
1034 u32 temp = 0;
1035 struct qlcnic_cmd_args cmd;
1036 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1037
1038 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX))
1039 return;
1040
1041 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1042 cmd.req.arg[0] |= (0x3 << 29);
1043
1044 if (qlcnic_sriov_pf_check(adapter))
1045 qlcnic_pf_set_interface_id_del_rx_ctx(adapter, &temp);
1046
1047 cmd.req.arg[1] = recv_ctx->context_id | temp;
1048 err = qlcnic_issue_cmd(adapter, &cmd);
1049 if (err)
1050 dev_err(&adapter->pdev->dev,
1051 "Failed to destroy rx ctx in firmware\n");
1052
1053 recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
1054 qlcnic_free_mbx_args(&cmd);
1055 }
1056
1057 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter)
1058 {
1059 int i, err, index, sds_mbx_size, rds_mbx_size;
1060 u8 num_sds, num_rds;
1061 u32 *buf, intrpt_id, intr_mask, cap = 0;
1062 struct qlcnic_host_sds_ring *sds;
1063 struct qlcnic_host_rds_ring *rds;
1064 struct qlcnic_sds_mbx sds_mbx;
1065 struct qlcnic_rds_mbx rds_mbx;
1066 struct qlcnic_cmd_args cmd;
1067 struct qlcnic_rcv_mbx_out *mbx_out;
1068 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1069 struct qlcnic_hardware_context *ahw = adapter->ahw;
1070 num_rds = adapter->max_rds_rings;
1071
1072 if (adapter->max_sds_rings <= QLCNIC_MAX_RING_SETS)
1073 num_sds = adapter->max_sds_rings;
1074 else
1075 num_sds = QLCNIC_MAX_RING_SETS;
1076
1077 sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1078 rds_mbx_size = sizeof(struct qlcnic_rds_mbx);
1079 cap = QLCNIC_CAP0_LEGACY_CONTEXT;
1080
1081 if (adapter->flags & QLCNIC_FW_LRO_MSS_CAP)
1082 cap |= QLC_83XX_FW_CAP_LRO_MSS;
1083
1084 /* set mailbox hdr and capabilities */
1085 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1086 QLCNIC_CMD_CREATE_RX_CTX);
1087 if (err)
1088 return err;
1089
1090 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1091 cmd.req.arg[0] |= (0x3 << 29);
1092
1093 cmd.req.arg[1] = cap;
1094 cmd.req.arg[5] = 1 | (num_rds << 5) | (num_sds << 8) |
1095 (QLC_83XX_HOST_RDS_MODE_UNIQUE << 16);
1096
1097 if (qlcnic_sriov_pf_check(adapter))
1098 qlcnic_pf_set_interface_id_create_rx_ctx(adapter,
1099 &cmd.req.arg[6]);
1100 /* set up status rings, mbx 8-57/87 */
1101 index = QLC_83XX_HOST_SDS_MBX_IDX;
1102 for (i = 0; i < num_sds; i++) {
1103 memset(&sds_mbx, 0, sds_mbx_size);
1104 sds = &recv_ctx->sds_rings[i];
1105 sds->consumer = 0;
1106 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1107 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1108 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1109 sds_mbx.sds_ring_size = sds->num_desc;
1110 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1111 intrpt_id = ahw->intr_tbl[i].id;
1112 else
1113 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1114 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1115 sds_mbx.intrpt_id = intrpt_id;
1116 else
1117 sds_mbx.intrpt_id = 0xffff;
1118 sds_mbx.intrpt_val = 0;
1119 buf = &cmd.req.arg[index];
1120 memcpy(buf, &sds_mbx, sds_mbx_size);
1121 index += sds_mbx_size / sizeof(u32);
1122 }
1123 /* set up receive rings, mbx 88-111/135 */
1124 index = QLCNIC_HOST_RDS_MBX_IDX;
1125 rds = &recv_ctx->rds_rings[0];
1126 rds->producer = 0;
1127 memset(&rds_mbx, 0, rds_mbx_size);
1128 rds_mbx.phy_addr_reg_low = LSD(rds->phys_addr);
1129 rds_mbx.phy_addr_reg_high = MSD(rds->phys_addr);
1130 rds_mbx.reg_ring_sz = rds->dma_size;
1131 rds_mbx.reg_ring_len = rds->num_desc;
1132 /* Jumbo ring */
1133 rds = &recv_ctx->rds_rings[1];
1134 rds->producer = 0;
1135 rds_mbx.phy_addr_jmb_low = LSD(rds->phys_addr);
1136 rds_mbx.phy_addr_jmb_high = MSD(rds->phys_addr);
1137 rds_mbx.jmb_ring_sz = rds->dma_size;
1138 rds_mbx.jmb_ring_len = rds->num_desc;
1139 buf = &cmd.req.arg[index];
1140 memcpy(buf, &rds_mbx, rds_mbx_size);
1141
1142 /* send the mailbox command */
1143 err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1144 if (err) {
1145 dev_err(&adapter->pdev->dev,
1146 "Failed to create Rx ctx in firmware%d\n", err);
1147 goto out;
1148 }
1149 mbx_out = (struct qlcnic_rcv_mbx_out *)&cmd.rsp.arg[1];
1150 recv_ctx->context_id = mbx_out->ctx_id;
1151 recv_ctx->state = mbx_out->state;
1152 recv_ctx->virt_port = mbx_out->vport_id;
1153 dev_info(&adapter->pdev->dev, "Rx Context[%d] Created, state:0x%x\n",
1154 recv_ctx->context_id, recv_ctx->state);
1155 /* Receive descriptor ring */
1156 /* Standard ring */
1157 rds = &recv_ctx->rds_rings[0];
1158 rds->crb_rcv_producer = ahw->pci_base0 +
1159 mbx_out->host_prod[0].reg_buf;
1160 /* Jumbo ring */
1161 rds = &recv_ctx->rds_rings[1];
1162 rds->crb_rcv_producer = ahw->pci_base0 +
1163 mbx_out->host_prod[0].jmb_buf;
1164 /* status descriptor ring */
1165 for (i = 0; i < num_sds; i++) {
1166 sds = &recv_ctx->sds_rings[i];
1167 sds->crb_sts_consumer = ahw->pci_base0 +
1168 mbx_out->host_csmr[i];
1169 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1170 intr_mask = ahw->intr_tbl[i].src;
1171 else
1172 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1173 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1174 }
1175
1176 if (adapter->max_sds_rings > QLCNIC_MAX_RING_SETS)
1177 err = qlcnic_83xx_add_rings(adapter);
1178 out:
1179 qlcnic_free_mbx_args(&cmd);
1180 return err;
1181 }
1182
1183 void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *adapter,
1184 struct qlcnic_host_tx_ring *tx_ring)
1185 {
1186 struct qlcnic_cmd_args cmd;
1187 u32 temp = 0;
1188
1189 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX))
1190 return;
1191
1192 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1193 cmd.req.arg[0] |= (0x3 << 29);
1194
1195 if (qlcnic_sriov_pf_check(adapter))
1196 qlcnic_pf_set_interface_id_del_tx_ctx(adapter, &temp);
1197
1198 cmd.req.arg[1] = tx_ring->ctx_id | temp;
1199 if (qlcnic_issue_cmd(adapter, &cmd))
1200 dev_err(&adapter->pdev->dev,
1201 "Failed to destroy tx ctx in firmware\n");
1202 qlcnic_free_mbx_args(&cmd);
1203 }
1204
1205 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *adapter,
1206 struct qlcnic_host_tx_ring *tx, int ring)
1207 {
1208 int err;
1209 u16 msix_id;
1210 u32 *buf, intr_mask, temp = 0;
1211 struct qlcnic_cmd_args cmd;
1212 struct qlcnic_tx_mbx mbx;
1213 struct qlcnic_tx_mbx_out *mbx_out;
1214 struct qlcnic_hardware_context *ahw = adapter->ahw;
1215 u32 msix_vector;
1216
1217 /* Reset host resources */
1218 tx->producer = 0;
1219 tx->sw_consumer = 0;
1220 *(tx->hw_consumer) = 0;
1221
1222 memset(&mbx, 0, sizeof(struct qlcnic_tx_mbx));
1223
1224 /* setup mailbox inbox registerss */
1225 mbx.phys_addr_low = LSD(tx->phys_addr);
1226 mbx.phys_addr_high = MSD(tx->phys_addr);
1227 mbx.cnsmr_index_low = LSD(tx->hw_cons_phys_addr);
1228 mbx.cnsmr_index_high = MSD(tx->hw_cons_phys_addr);
1229 mbx.size = tx->num_desc;
1230 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
1231 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
1232 msix_vector = adapter->max_sds_rings + ring;
1233 else
1234 msix_vector = adapter->max_sds_rings - 1;
1235 msix_id = ahw->intr_tbl[msix_vector].id;
1236 } else {
1237 msix_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1238 }
1239
1240 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1241 mbx.intr_id = msix_id;
1242 else
1243 mbx.intr_id = 0xffff;
1244 mbx.src = 0;
1245
1246 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
1247 if (err)
1248 return err;
1249
1250 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1251 cmd.req.arg[0] |= (0x3 << 29);
1252
1253 if (qlcnic_sriov_pf_check(adapter))
1254 qlcnic_pf_set_interface_id_create_tx_ctx(adapter, &temp);
1255
1256 cmd.req.arg[1] = QLCNIC_CAP0_LEGACY_CONTEXT;
1257 cmd.req.arg[5] = QLCNIC_MAX_TX_QUEUES | temp;
1258 buf = &cmd.req.arg[6];
1259 memcpy(buf, &mbx, sizeof(struct qlcnic_tx_mbx));
1260 /* send the mailbox command*/
1261 err = qlcnic_issue_cmd(adapter, &cmd);
1262 if (err) {
1263 dev_err(&adapter->pdev->dev,
1264 "Failed to create Tx ctx in firmware 0x%x\n", err);
1265 goto out;
1266 }
1267 mbx_out = (struct qlcnic_tx_mbx_out *)&cmd.rsp.arg[2];
1268 tx->crb_cmd_producer = ahw->pci_base0 + mbx_out->host_prod;
1269 tx->ctx_id = mbx_out->ctx_id;
1270 if ((adapter->flags & QLCNIC_MSIX_ENABLED) &&
1271 !(adapter->flags & QLCNIC_TX_INTR_SHARED)) {
1272 intr_mask = ahw->intr_tbl[adapter->max_sds_rings + ring].src;
1273 tx->crb_intr_mask = ahw->pci_base0 + intr_mask;
1274 }
1275 dev_info(&adapter->pdev->dev, "Tx Context[0x%x] Created, state:0x%x\n",
1276 tx->ctx_id, mbx_out->state);
1277 out:
1278 qlcnic_free_mbx_args(&cmd);
1279 return err;
1280 }
1281
1282 static int qlcnic_83xx_diag_alloc_res(struct net_device *netdev, int test,
1283 int num_sds_ring)
1284 {
1285 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1286 struct qlcnic_host_sds_ring *sds_ring;
1287 struct qlcnic_host_rds_ring *rds_ring;
1288 u16 adapter_state = adapter->is_up;
1289 u8 ring;
1290 int ret;
1291
1292 netif_device_detach(netdev);
1293
1294 if (netif_running(netdev))
1295 __qlcnic_down(adapter, netdev);
1296
1297 qlcnic_detach(adapter);
1298
1299 adapter->max_sds_rings = 1;
1300 adapter->ahw->diag_test = test;
1301 adapter->ahw->linkup = 0;
1302
1303 ret = qlcnic_attach(adapter);
1304 if (ret) {
1305 netif_device_attach(netdev);
1306 return ret;
1307 }
1308
1309 ret = qlcnic_fw_create_ctx(adapter);
1310 if (ret) {
1311 qlcnic_detach(adapter);
1312 if (adapter_state == QLCNIC_ADAPTER_UP_MAGIC) {
1313 adapter->max_sds_rings = num_sds_ring;
1314 qlcnic_attach(adapter);
1315 }
1316 netif_device_attach(netdev);
1317 return ret;
1318 }
1319
1320 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1321 rds_ring = &adapter->recv_ctx->rds_rings[ring];
1322 qlcnic_post_rx_buffers(adapter, rds_ring, ring);
1323 }
1324
1325 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1326 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
1327 sds_ring = &adapter->recv_ctx->sds_rings[ring];
1328 qlcnic_83xx_enable_intr(adapter, sds_ring);
1329 }
1330 }
1331
1332 if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1333 /* disable and free mailbox interrupt */
1334 if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
1335 qlcnic_83xx_free_mbx_intr(adapter);
1336 adapter->ahw->loopback_state = 0;
1337 adapter->ahw->hw_ops->setup_link_event(adapter, 1);
1338 }
1339
1340 set_bit(__QLCNIC_DEV_UP, &adapter->state);
1341 return 0;
1342 }
1343
1344 static void qlcnic_83xx_diag_free_res(struct net_device *netdev,
1345 int max_sds_rings)
1346 {
1347 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1348 struct qlcnic_host_sds_ring *sds_ring;
1349 int ring, err;
1350
1351 clear_bit(__QLCNIC_DEV_UP, &adapter->state);
1352 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1353 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
1354 sds_ring = &adapter->recv_ctx->sds_rings[ring];
1355 qlcnic_83xx_disable_intr(adapter, sds_ring);
1356 }
1357 }
1358
1359 qlcnic_fw_destroy_ctx(adapter);
1360 qlcnic_detach(adapter);
1361
1362 if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1363 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
1364 err = qlcnic_83xx_setup_mbx_intr(adapter);
1365 if (err) {
1366 dev_err(&adapter->pdev->dev,
1367 "%s: failed to setup mbx interrupt\n",
1368 __func__);
1369 goto out;
1370 }
1371 }
1372 }
1373 adapter->ahw->diag_test = 0;
1374 adapter->max_sds_rings = max_sds_rings;
1375
1376 if (qlcnic_attach(adapter))
1377 goto out;
1378
1379 if (netif_running(netdev))
1380 __qlcnic_up(adapter, netdev);
1381 out:
1382 netif_device_attach(netdev);
1383 }
1384
1385 int qlcnic_83xx_config_led(struct qlcnic_adapter *adapter, u32 state,
1386 u32 beacon)
1387 {
1388 struct qlcnic_cmd_args cmd;
1389 u32 mbx_in;
1390 int i, status = 0;
1391
1392 if (state) {
1393 /* Get LED configuration */
1394 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1395 QLCNIC_CMD_GET_LED_CONFIG);
1396 if (status)
1397 return status;
1398
1399 status = qlcnic_issue_cmd(adapter, &cmd);
1400 if (status) {
1401 dev_err(&adapter->pdev->dev,
1402 "Get led config failed.\n");
1403 goto mbx_err;
1404 } else {
1405 for (i = 0; i < 4; i++)
1406 adapter->ahw->mbox_reg[i] = cmd.rsp.arg[i+1];
1407 }
1408 qlcnic_free_mbx_args(&cmd);
1409 /* Set LED Configuration */
1410 mbx_in = (LSW(QLC_83XX_LED_CONFIG) << 16) |
1411 LSW(QLC_83XX_LED_CONFIG);
1412 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1413 QLCNIC_CMD_SET_LED_CONFIG);
1414 if (status)
1415 return status;
1416
1417 cmd.req.arg[1] = mbx_in;
1418 cmd.req.arg[2] = mbx_in;
1419 cmd.req.arg[3] = mbx_in;
1420 if (beacon)
1421 cmd.req.arg[4] = QLC_83XX_ENABLE_BEACON;
1422 status = qlcnic_issue_cmd(adapter, &cmd);
1423 if (status) {
1424 dev_err(&adapter->pdev->dev,
1425 "Set led config failed.\n");
1426 }
1427 mbx_err:
1428 qlcnic_free_mbx_args(&cmd);
1429 return status;
1430
1431 } else {
1432 /* Restoring default LED configuration */
1433 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1434 QLCNIC_CMD_SET_LED_CONFIG);
1435 if (status)
1436 return status;
1437
1438 cmd.req.arg[1] = adapter->ahw->mbox_reg[0];
1439 cmd.req.arg[2] = adapter->ahw->mbox_reg[1];
1440 cmd.req.arg[3] = adapter->ahw->mbox_reg[2];
1441 if (beacon)
1442 cmd.req.arg[4] = adapter->ahw->mbox_reg[3];
1443 status = qlcnic_issue_cmd(adapter, &cmd);
1444 if (status)
1445 dev_err(&adapter->pdev->dev,
1446 "Restoring led config failed.\n");
1447 qlcnic_free_mbx_args(&cmd);
1448 return status;
1449 }
1450 }
1451
1452 int qlcnic_83xx_set_led(struct net_device *netdev,
1453 enum ethtool_phys_id_state state)
1454 {
1455 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1456 int err = -EIO, active = 1;
1457
1458 if (adapter->ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1459 netdev_warn(netdev,
1460 "LED test is not supported in non-privileged mode\n");
1461 return -EOPNOTSUPP;
1462 }
1463
1464 switch (state) {
1465 case ETHTOOL_ID_ACTIVE:
1466 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state))
1467 return -EBUSY;
1468
1469 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1470 break;
1471
1472 err = qlcnic_83xx_config_led(adapter, active, 0);
1473 if (err)
1474 netdev_err(netdev, "Failed to set LED blink state\n");
1475 break;
1476 case ETHTOOL_ID_INACTIVE:
1477 active = 0;
1478
1479 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1480 break;
1481
1482 err = qlcnic_83xx_config_led(adapter, active, 0);
1483 if (err)
1484 netdev_err(netdev, "Failed to reset LED blink state\n");
1485 break;
1486
1487 default:
1488 return -EINVAL;
1489 }
1490
1491 if (!active || err)
1492 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state);
1493
1494 return err;
1495 }
1496
1497 void qlcnic_83xx_register_nic_idc_func(struct qlcnic_adapter *adapter,
1498 int enable)
1499 {
1500 struct qlcnic_cmd_args cmd;
1501 int status;
1502
1503 if (qlcnic_sriov_vf_check(adapter))
1504 return;
1505
1506 if (enable) {
1507 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1508 QLCNIC_CMD_INIT_NIC_FUNC);
1509 if (status)
1510 return;
1511
1512 cmd.req.arg[1] = BIT_0 | BIT_31;
1513 } else {
1514 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1515 QLCNIC_CMD_STOP_NIC_FUNC);
1516 if (status)
1517 return;
1518
1519 cmd.req.arg[1] = BIT_0 | BIT_31;
1520 }
1521 status = qlcnic_issue_cmd(adapter, &cmd);
1522 if (status)
1523 dev_err(&adapter->pdev->dev,
1524 "Failed to %s in NIC IDC function event.\n",
1525 (enable ? "register" : "unregister"));
1526
1527 qlcnic_free_mbx_args(&cmd);
1528 }
1529
1530 int qlcnic_83xx_set_port_config(struct qlcnic_adapter *adapter)
1531 {
1532 struct qlcnic_cmd_args cmd;
1533 int err;
1534
1535 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_PORT_CONFIG);
1536 if (err)
1537 return err;
1538
1539 cmd.req.arg[1] = adapter->ahw->port_config;
1540 err = qlcnic_issue_cmd(adapter, &cmd);
1541 if (err)
1542 dev_info(&adapter->pdev->dev, "Set Port Config failed.\n");
1543 qlcnic_free_mbx_args(&cmd);
1544 return err;
1545 }
1546
1547 int qlcnic_83xx_get_port_config(struct qlcnic_adapter *adapter)
1548 {
1549 struct qlcnic_cmd_args cmd;
1550 int err;
1551
1552 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PORT_CONFIG);
1553 if (err)
1554 return err;
1555
1556 err = qlcnic_issue_cmd(adapter, &cmd);
1557 if (err)
1558 dev_info(&adapter->pdev->dev, "Get Port config failed\n");
1559 else
1560 adapter->ahw->port_config = cmd.rsp.arg[1];
1561 qlcnic_free_mbx_args(&cmd);
1562 return err;
1563 }
1564
1565 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *adapter, int enable)
1566 {
1567 int err;
1568 u32 temp;
1569 struct qlcnic_cmd_args cmd;
1570
1571 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_EVENT);
1572 if (err)
1573 return err;
1574
1575 temp = adapter->recv_ctx->context_id << 16;
1576 cmd.req.arg[1] = (enable ? 1 : 0) | BIT_8 | temp;
1577 err = qlcnic_issue_cmd(adapter, &cmd);
1578 if (err)
1579 dev_info(&adapter->pdev->dev,
1580 "Setup linkevent mailbox failed\n");
1581 qlcnic_free_mbx_args(&cmd);
1582 return err;
1583 }
1584
1585 static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter *adapter,
1586 u32 *interface_id)
1587 {
1588 if (qlcnic_sriov_pf_check(adapter)) {
1589 qlcnic_pf_set_interface_id_promisc(adapter, interface_id);
1590 } else {
1591 if (!qlcnic_sriov_vf_check(adapter))
1592 *interface_id = adapter->recv_ctx->context_id << 16;
1593 }
1594 }
1595
1596 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
1597 {
1598 struct qlcnic_cmd_args *cmd = NULL;
1599 u32 temp = 0;
1600 int err;
1601
1602 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1603 return -EIO;
1604
1605 cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
1606 if (!cmd)
1607 return -ENOMEM;
1608
1609 err = qlcnic_alloc_mbx_args(cmd, adapter,
1610 QLCNIC_CMD_CONFIGURE_MAC_RX_MODE);
1611 if (err)
1612 goto out;
1613
1614 cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
1615 qlcnic_83xx_set_interface_id_promisc(adapter, &temp);
1616 cmd->req.arg[1] = (mode ? 1 : 0) | temp;
1617 err = qlcnic_issue_cmd(adapter, cmd);
1618 if (!err)
1619 return err;
1620
1621 qlcnic_free_mbx_args(cmd);
1622
1623 out:
1624 kfree(cmd);
1625 return err;
1626 }
1627
1628 int qlcnic_83xx_loopback_test(struct net_device *netdev, u8 mode)
1629 {
1630 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1631 struct qlcnic_hardware_context *ahw = adapter->ahw;
1632 int ret = 0, loop = 0, max_sds_rings = adapter->max_sds_rings;
1633
1634 if (ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1635 netdev_warn(netdev,
1636 "Loopback test not supported in non privileged mode\n");
1637 return -ENOTSUPP;
1638 }
1639
1640 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1641 netdev_info(netdev, "Device is resetting\n");
1642 return -EBUSY;
1643 }
1644
1645 if (qlcnic_get_diag_lock(adapter)) {
1646 netdev_info(netdev, "Device is in diagnostics mode\n");
1647 return -EBUSY;
1648 }
1649
1650 netdev_info(netdev, "%s loopback test in progress\n",
1651 mode == QLCNIC_ILB_MODE ? "internal" : "external");
1652
1653 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST,
1654 max_sds_rings);
1655 if (ret)
1656 goto fail_diag_alloc;
1657
1658 ret = qlcnic_83xx_set_lb_mode(adapter, mode);
1659 if (ret)
1660 goto free_diag_res;
1661
1662 /* Poll for link up event before running traffic */
1663 do {
1664 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1665 if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
1666 qlcnic_83xx_process_aen(adapter);
1667
1668 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1669 netdev_info(netdev,
1670 "Device is resetting, free LB test resources\n");
1671 ret = -EBUSY;
1672 goto free_diag_res;
1673 }
1674 if (loop++ > QLC_83XX_LB_WAIT_COUNT) {
1675 netdev_info(netdev,
1676 "Firmware didn't sent link up event to loopback request\n");
1677 ret = -ETIMEDOUT;
1678 qlcnic_83xx_clear_lb_mode(adapter, mode);
1679 goto free_diag_res;
1680 }
1681 } while ((adapter->ahw->linkup && ahw->has_link_events) != 1);
1682
1683 /* Make sure carrier is off and queue is stopped during loopback */
1684 if (netif_running(netdev)) {
1685 netif_carrier_off(netdev);
1686 netif_stop_queue(netdev);
1687 }
1688
1689 ret = qlcnic_do_lb_test(adapter, mode);
1690
1691 qlcnic_83xx_clear_lb_mode(adapter, mode);
1692
1693 free_diag_res:
1694 qlcnic_83xx_diag_free_res(netdev, max_sds_rings);
1695
1696 fail_diag_alloc:
1697 adapter->max_sds_rings = max_sds_rings;
1698 qlcnic_release_diag_lock(adapter);
1699 return ret;
1700 }
1701
1702 int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1703 {
1704 struct qlcnic_hardware_context *ahw = adapter->ahw;
1705 struct net_device *netdev = adapter->netdev;
1706 int status = 0, loop = 0;
1707 u32 config;
1708
1709 status = qlcnic_83xx_get_port_config(adapter);
1710 if (status)
1711 return status;
1712
1713 config = ahw->port_config;
1714
1715 /* Check if port is already in loopback mode */
1716 if ((config & QLC_83XX_CFG_LOOPBACK_HSS) ||
1717 (config & QLC_83XX_CFG_LOOPBACK_EXT)) {
1718 netdev_err(netdev,
1719 "Port already in Loopback mode.\n");
1720 return -EINPROGRESS;
1721 }
1722
1723 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1724
1725 if (mode == QLCNIC_ILB_MODE)
1726 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_HSS;
1727 if (mode == QLCNIC_ELB_MODE)
1728 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_EXT;
1729
1730 status = qlcnic_83xx_set_port_config(adapter);
1731 if (status) {
1732 netdev_err(netdev,
1733 "Failed to Set Loopback Mode = 0x%x.\n",
1734 ahw->port_config);
1735 ahw->port_config = config;
1736 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1737 return status;
1738 }
1739
1740 /* Wait for Link and IDC Completion AEN */
1741 do {
1742 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1743 if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
1744 qlcnic_83xx_process_aen(adapter);
1745
1746 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1747 netdev_info(netdev,
1748 "Device is resetting, free LB test resources\n");
1749 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1750 return -EBUSY;
1751 }
1752 if (loop++ > QLC_83XX_LB_WAIT_COUNT) {
1753 netdev_err(netdev,
1754 "Did not receive IDC completion AEN\n");
1755 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1756 qlcnic_83xx_clear_lb_mode(adapter, mode);
1757 return -ETIMEDOUT;
1758 }
1759 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1760
1761 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1762 QLCNIC_MAC_ADD);
1763 return status;
1764 }
1765
1766 int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1767 {
1768 struct qlcnic_hardware_context *ahw = adapter->ahw;
1769 struct net_device *netdev = adapter->netdev;
1770 int status = 0, loop = 0;
1771 u32 config = ahw->port_config;
1772
1773 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1774 if (mode == QLCNIC_ILB_MODE)
1775 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_HSS;
1776 if (mode == QLCNIC_ELB_MODE)
1777 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_EXT;
1778
1779 status = qlcnic_83xx_set_port_config(adapter);
1780 if (status) {
1781 netdev_err(netdev,
1782 "Failed to Clear Loopback Mode = 0x%x.\n",
1783 ahw->port_config);
1784 ahw->port_config = config;
1785 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1786 return status;
1787 }
1788
1789 /* Wait for Link and IDC Completion AEN */
1790 do {
1791 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1792 if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
1793 qlcnic_83xx_process_aen(adapter);
1794
1795 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1796 netdev_info(netdev,
1797 "Device is resetting, free LB test resources\n");
1798 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1799 return -EBUSY;
1800 }
1801
1802 if (loop++ > QLC_83XX_LB_WAIT_COUNT) {
1803 netdev_err(netdev,
1804 "Did not receive IDC completion AEN\n");
1805 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1806 return -ETIMEDOUT;
1807 }
1808 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1809
1810 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1811 QLCNIC_MAC_DEL);
1812 return status;
1813 }
1814
1815 static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter *adapter,
1816 u32 *interface_id)
1817 {
1818 if (qlcnic_sriov_pf_check(adapter)) {
1819 qlcnic_pf_set_interface_id_ipaddr(adapter, interface_id);
1820 } else {
1821 if (!qlcnic_sriov_vf_check(adapter))
1822 *interface_id = adapter->recv_ctx->context_id << 16;
1823 }
1824 }
1825
1826 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip,
1827 int mode)
1828 {
1829 int err;
1830 u32 temp = 0, temp_ip;
1831 struct qlcnic_cmd_args cmd;
1832
1833 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1834 QLCNIC_CMD_CONFIGURE_IP_ADDR);
1835 if (err)
1836 return;
1837
1838 qlcnic_83xx_set_interface_id_ipaddr(adapter, &temp);
1839
1840 if (mode == QLCNIC_IP_UP)
1841 cmd.req.arg[1] = 1 | temp;
1842 else
1843 cmd.req.arg[1] = 2 | temp;
1844
1845 /*
1846 * Adapter needs IP address in network byte order.
1847 * But hardware mailbox registers go through writel(), hence IP address
1848 * gets swapped on big endian architecture.
1849 * To negate swapping of writel() on big endian architecture
1850 * use swab32(value).
1851 */
1852
1853 temp_ip = swab32(ntohl(ip));
1854 memcpy(&cmd.req.arg[2], &temp_ip, sizeof(u32));
1855 err = qlcnic_issue_cmd(adapter, &cmd);
1856 if (err != QLCNIC_RCODE_SUCCESS)
1857 dev_err(&adapter->netdev->dev,
1858 "could not notify %s IP 0x%x request\n",
1859 (mode == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
1860
1861 qlcnic_free_mbx_args(&cmd);
1862 }
1863
1864 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *adapter, int mode)
1865 {
1866 int err;
1867 u32 temp, arg1;
1868 struct qlcnic_cmd_args cmd;
1869 int lro_bit_mask;
1870
1871 lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0);
1872
1873 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1874 return 0;
1875
1876 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_HW_LRO);
1877 if (err)
1878 return err;
1879
1880 temp = adapter->recv_ctx->context_id << 16;
1881 arg1 = lro_bit_mask | temp;
1882 cmd.req.arg[1] = arg1;
1883
1884 err = qlcnic_issue_cmd(adapter, &cmd);
1885 if (err)
1886 dev_info(&adapter->pdev->dev, "LRO config failed\n");
1887 qlcnic_free_mbx_args(&cmd);
1888
1889 return err;
1890 }
1891
1892 int qlcnic_83xx_config_rss(struct qlcnic_adapter *adapter, int enable)
1893 {
1894 int err;
1895 u32 word;
1896 struct qlcnic_cmd_args cmd;
1897 const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
1898 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
1899 0x255b0ec26d5a56daULL };
1900
1901 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_RSS);
1902 if (err)
1903 return err;
1904 /*
1905 * RSS request:
1906 * bits 3-0: Rsvd
1907 * 5-4: hash_type_ipv4
1908 * 7-6: hash_type_ipv6
1909 * 8: enable
1910 * 9: use indirection table
1911 * 16-31: indirection table mask
1912 */
1913 word = ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
1914 ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
1915 ((u32)(enable & 0x1) << 8) |
1916 ((0x7ULL) << 16);
1917 cmd.req.arg[1] = (adapter->recv_ctx->context_id);
1918 cmd.req.arg[2] = word;
1919 memcpy(&cmd.req.arg[4], key, sizeof(key));
1920
1921 err = qlcnic_issue_cmd(adapter, &cmd);
1922
1923 if (err)
1924 dev_info(&adapter->pdev->dev, "RSS config failed\n");
1925 qlcnic_free_mbx_args(&cmd);
1926
1927 return err;
1928
1929 }
1930
1931 static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter *adapter,
1932 u32 *interface_id)
1933 {
1934 if (qlcnic_sriov_pf_check(adapter)) {
1935 qlcnic_pf_set_interface_id_macaddr(adapter, interface_id);
1936 } else {
1937 if (!qlcnic_sriov_vf_check(adapter))
1938 *interface_id = adapter->recv_ctx->context_id << 16;
1939 }
1940 }
1941
1942 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
1943 u16 vlan_id, u8 op)
1944 {
1945 struct qlcnic_cmd_args *cmd = NULL;
1946 struct qlcnic_macvlan_mbx mv;
1947 u32 *buf, temp = 0;
1948 int err;
1949
1950 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1951 return -EIO;
1952
1953 cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
1954 if (!cmd)
1955 return -ENOMEM;
1956
1957 err = qlcnic_alloc_mbx_args(cmd, adapter, QLCNIC_CMD_CONFIG_MAC_VLAN);
1958 if (err)
1959 goto out;
1960
1961 cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
1962
1963 if (vlan_id)
1964 op = (op == QLCNIC_MAC_ADD || op == QLCNIC_MAC_VLAN_ADD) ?
1965 QLCNIC_MAC_VLAN_ADD : QLCNIC_MAC_VLAN_DEL;
1966
1967 cmd->req.arg[1] = op | (1 << 8);
1968 qlcnic_83xx_set_interface_id_macaddr(adapter, &temp);
1969 cmd->req.arg[1] |= temp;
1970 mv.vlan = vlan_id;
1971 mv.mac_addr0 = addr[0];
1972 mv.mac_addr1 = addr[1];
1973 mv.mac_addr2 = addr[2];
1974 mv.mac_addr3 = addr[3];
1975 mv.mac_addr4 = addr[4];
1976 mv.mac_addr5 = addr[5];
1977 buf = &cmd->req.arg[2];
1978 memcpy(buf, &mv, sizeof(struct qlcnic_macvlan_mbx));
1979 err = qlcnic_issue_cmd(adapter, cmd);
1980 if (!err)
1981 return err;
1982
1983 qlcnic_free_mbx_args(cmd);
1984 out:
1985 kfree(cmd);
1986 return err;
1987 }
1988
1989 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr,
1990 u16 vlan_id)
1991 {
1992 u8 mac[ETH_ALEN];
1993 memcpy(&mac, addr, ETH_ALEN);
1994 qlcnic_83xx_sre_macaddr_change(adapter, mac, vlan_id, QLCNIC_MAC_ADD);
1995 }
1996
1997 void qlcnic_83xx_configure_mac(struct qlcnic_adapter *adapter, u8 *mac,
1998 u8 type, struct qlcnic_cmd_args *cmd)
1999 {
2000 switch (type) {
2001 case QLCNIC_SET_STATION_MAC:
2002 case QLCNIC_SET_FAC_DEF_MAC:
2003 memcpy(&cmd->req.arg[2], mac, sizeof(u32));
2004 memcpy(&cmd->req.arg[3], &mac[4], sizeof(u16));
2005 break;
2006 }
2007 cmd->req.arg[1] = type;
2008 }
2009
2010 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac)
2011 {
2012 int err, i;
2013 struct qlcnic_cmd_args cmd;
2014 u32 mac_low, mac_high;
2015
2016 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
2017 if (err)
2018 return err;
2019
2020 qlcnic_83xx_configure_mac(adapter, mac, QLCNIC_GET_CURRENT_MAC, &cmd);
2021 err = qlcnic_issue_cmd(adapter, &cmd);
2022
2023 if (err == QLCNIC_RCODE_SUCCESS) {
2024 mac_low = cmd.rsp.arg[1];
2025 mac_high = cmd.rsp.arg[2];
2026
2027 for (i = 0; i < 2; i++)
2028 mac[i] = (u8) (mac_high >> ((1 - i) * 8));
2029 for (i = 2; i < 6; i++)
2030 mac[i] = (u8) (mac_low >> ((5 - i) * 8));
2031 } else {
2032 dev_err(&adapter->pdev->dev, "Failed to get mac address%d\n",
2033 err);
2034 err = -EIO;
2035 }
2036 qlcnic_free_mbx_args(&cmd);
2037 return err;
2038 }
2039
2040 void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *adapter)
2041 {
2042 int err;
2043 u16 temp;
2044 struct qlcnic_cmd_args cmd;
2045 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2046
2047 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2048 return;
2049
2050 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
2051 if (err)
2052 return;
2053
2054 if (coal->type == QLCNIC_INTR_COAL_TYPE_RX) {
2055 temp = adapter->recv_ctx->context_id;
2056 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_RX | temp << 16;
2057 temp = coal->rx_time_us;
2058 cmd.req.arg[2] = coal->rx_packets | temp << 16;
2059 } else if (coal->type == QLCNIC_INTR_COAL_TYPE_TX) {
2060 temp = adapter->tx_ring->ctx_id;
2061 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_TX | temp << 16;
2062 temp = coal->tx_time_us;
2063 cmd.req.arg[2] = coal->tx_packets | temp << 16;
2064 }
2065 cmd.req.arg[3] = coal->flag;
2066 err = qlcnic_issue_cmd(adapter, &cmd);
2067 if (err != QLCNIC_RCODE_SUCCESS)
2068 dev_info(&adapter->pdev->dev,
2069 "Failed to send interrupt coalescence parameters\n");
2070 qlcnic_free_mbx_args(&cmd);
2071 }
2072
2073 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
2074 u32 data[])
2075 {
2076 u8 link_status, duplex;
2077 /* link speed */
2078 link_status = LSB(data[3]) & 1;
2079 adapter->ahw->link_speed = MSW(data[2]);
2080 adapter->ahw->link_autoneg = MSB(MSW(data[3]));
2081 adapter->ahw->module_type = MSB(LSW(data[3]));
2082 duplex = LSB(MSW(data[3]));
2083 if (duplex)
2084 adapter->ahw->link_duplex = DUPLEX_FULL;
2085 else
2086 adapter->ahw->link_duplex = DUPLEX_HALF;
2087 adapter->ahw->has_link_events = 1;
2088 qlcnic_advert_link_change(adapter, link_status);
2089 }
2090
2091 irqreturn_t qlcnic_83xx_handle_aen(int irq, void *data)
2092 {
2093 struct qlcnic_adapter *adapter = data;
2094 struct qlcnic_mailbox *mbx;
2095 u32 mask, resp, event;
2096 unsigned long flags;
2097
2098 mbx = adapter->ahw->mailbox;
2099 spin_lock_irqsave(&mbx->aen_lock, flags);
2100 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
2101 if (!(resp & QLCNIC_SET_OWNER))
2102 goto out;
2103
2104 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
2105 if (event & QLCNIC_MBX_ASYNC_EVENT)
2106 __qlcnic_83xx_process_aen(adapter);
2107 else
2108 qlcnic_83xx_notify_mbx_response(mbx);
2109
2110 out:
2111 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
2112 writel(0, adapter->ahw->pci_base0 + mask);
2113 spin_unlock_irqrestore(&mbx->aen_lock, flags);
2114 return IRQ_HANDLED;
2115 }
2116
2117 int qlcnic_enable_eswitch(struct qlcnic_adapter *adapter, u8 port, u8 enable)
2118 {
2119 int err = -EIO;
2120 struct qlcnic_cmd_args cmd;
2121
2122 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2123 dev_err(&adapter->pdev->dev,
2124 "%s: Error, invoked by non management func\n",
2125 __func__);
2126 return err;
2127 }
2128
2129 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_TOGGLE_ESWITCH);
2130 if (err)
2131 return err;
2132
2133 cmd.req.arg[1] = (port & 0xf) | BIT_4;
2134 err = qlcnic_issue_cmd(adapter, &cmd);
2135
2136 if (err != QLCNIC_RCODE_SUCCESS) {
2137 dev_err(&adapter->pdev->dev, "Failed to enable eswitch%d\n",
2138 err);
2139 err = -EIO;
2140 }
2141 qlcnic_free_mbx_args(&cmd);
2142
2143 return err;
2144
2145 }
2146
2147 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *adapter,
2148 struct qlcnic_info *nic)
2149 {
2150 int i, err = -EIO;
2151 struct qlcnic_cmd_args cmd;
2152
2153 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2154 dev_err(&adapter->pdev->dev,
2155 "%s: Error, invoked by non management func\n",
2156 __func__);
2157 return err;
2158 }
2159
2160 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
2161 if (err)
2162 return err;
2163
2164 cmd.req.arg[1] = (nic->pci_func << 16);
2165 cmd.req.arg[2] = 0x1 << 16;
2166 cmd.req.arg[3] = nic->phys_port | (nic->switch_mode << 16);
2167 cmd.req.arg[4] = nic->capabilities;
2168 cmd.req.arg[5] = (nic->max_mac_filters & 0xFF) | ((nic->max_mtu) << 16);
2169 cmd.req.arg[6] = (nic->max_tx_ques) | ((nic->max_rx_ques) << 16);
2170 cmd.req.arg[7] = (nic->min_tx_bw) | ((nic->max_tx_bw) << 16);
2171 for (i = 8; i < 32; i++)
2172 cmd.req.arg[i] = 0;
2173
2174 err = qlcnic_issue_cmd(adapter, &cmd);
2175
2176 if (err != QLCNIC_RCODE_SUCCESS) {
2177 dev_err(&adapter->pdev->dev, "Failed to set nic info%d\n",
2178 err);
2179 err = -EIO;
2180 }
2181
2182 qlcnic_free_mbx_args(&cmd);
2183
2184 return err;
2185 }
2186
2187 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *adapter,
2188 struct qlcnic_info *npar_info, u8 func_id)
2189 {
2190 int err;
2191 u32 temp;
2192 u8 op = 0;
2193 struct qlcnic_cmd_args cmd;
2194 struct qlcnic_hardware_context *ahw = adapter->ahw;
2195
2196 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
2197 if (err)
2198 return err;
2199
2200 if (func_id != ahw->pci_func) {
2201 temp = func_id << 16;
2202 cmd.req.arg[1] = op | BIT_31 | temp;
2203 } else {
2204 cmd.req.arg[1] = ahw->pci_func << 16;
2205 }
2206 err = qlcnic_issue_cmd(adapter, &cmd);
2207 if (err) {
2208 dev_info(&adapter->pdev->dev,
2209 "Failed to get nic info %d\n", err);
2210 goto out;
2211 }
2212
2213 npar_info->op_type = cmd.rsp.arg[1];
2214 npar_info->pci_func = cmd.rsp.arg[2] & 0xFFFF;
2215 npar_info->op_mode = (cmd.rsp.arg[2] & 0xFFFF0000) >> 16;
2216 npar_info->phys_port = cmd.rsp.arg[3] & 0xFFFF;
2217 npar_info->switch_mode = (cmd.rsp.arg[3] & 0xFFFF0000) >> 16;
2218 npar_info->capabilities = cmd.rsp.arg[4];
2219 npar_info->max_mac_filters = cmd.rsp.arg[5] & 0xFF;
2220 npar_info->max_mtu = (cmd.rsp.arg[5] & 0xFFFF0000) >> 16;
2221 npar_info->max_tx_ques = cmd.rsp.arg[6] & 0xFFFF;
2222 npar_info->max_rx_ques = (cmd.rsp.arg[6] & 0xFFFF0000) >> 16;
2223 npar_info->min_tx_bw = cmd.rsp.arg[7] & 0xFFFF;
2224 npar_info->max_tx_bw = (cmd.rsp.arg[7] & 0xFFFF0000) >> 16;
2225 if (cmd.rsp.arg[8] & 0x1)
2226 npar_info->max_bw_reg_offset = (cmd.rsp.arg[8] & 0x7FFE) >> 1;
2227 if (cmd.rsp.arg[8] & 0x10000) {
2228 temp = (cmd.rsp.arg[8] & 0x7FFE0000) >> 17;
2229 npar_info->max_linkspeed_reg_offset = temp;
2230 }
2231 if (npar_info->capabilities & QLCNIC_FW_CAPABILITY_MORE_CAPS)
2232 memcpy(ahw->extra_capability, &cmd.rsp.arg[16],
2233 sizeof(ahw->extra_capability));
2234
2235 out:
2236 qlcnic_free_mbx_args(&cmd);
2237 return err;
2238 }
2239
2240 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *adapter,
2241 struct qlcnic_pci_info *pci_info)
2242 {
2243 struct qlcnic_hardware_context *ahw = adapter->ahw;
2244 struct device *dev = &adapter->pdev->dev;
2245 struct qlcnic_cmd_args cmd;
2246 int i, err = 0, j = 0;
2247 u32 temp;
2248
2249 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
2250 if (err)
2251 return err;
2252
2253 err = qlcnic_issue_cmd(adapter, &cmd);
2254
2255 ahw->act_pci_func = 0;
2256 if (err == QLCNIC_RCODE_SUCCESS) {
2257 ahw->max_pci_func = cmd.rsp.arg[1] & 0xFF;
2258 for (i = 2, j = 0; j < QLCNIC_MAX_PCI_FUNC; j++, pci_info++) {
2259 pci_info->id = cmd.rsp.arg[i] & 0xFFFF;
2260 pci_info->active = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2261 i++;
2262 pci_info->type = cmd.rsp.arg[i] & 0xFFFF;
2263 if (pci_info->type == QLCNIC_TYPE_NIC)
2264 ahw->act_pci_func++;
2265 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2266 pci_info->default_port = temp;
2267 i++;
2268 pci_info->tx_min_bw = cmd.rsp.arg[i] & 0xFFFF;
2269 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2270 pci_info->tx_max_bw = temp;
2271 i = i + 2;
2272 memcpy(pci_info->mac, &cmd.rsp.arg[i], ETH_ALEN - 2);
2273 i++;
2274 memcpy(pci_info->mac + sizeof(u32), &cmd.rsp.arg[i], 2);
2275 i = i + 3;
2276 if (ahw->op_mode == QLCNIC_MGMT_FUNC)
2277 dev_info(dev, "id = %d active = %d type = %d\n"
2278 "\tport = %d min bw = %d max bw = %d\n"
2279 "\tmac_addr = %pM\n", pci_info->id,
2280 pci_info->active, pci_info->type,
2281 pci_info->default_port,
2282 pci_info->tx_min_bw,
2283 pci_info->tx_max_bw, pci_info->mac);
2284 }
2285 if (ahw->op_mode == QLCNIC_MGMT_FUNC)
2286 dev_info(dev, "Max vNIC functions = %d, active vNIC functions = %d\n",
2287 ahw->max_pci_func, ahw->act_pci_func);
2288
2289 } else {
2290 dev_err(dev, "Failed to get PCI Info, error = %d\n", err);
2291 err = -EIO;
2292 }
2293
2294 qlcnic_free_mbx_args(&cmd);
2295
2296 return err;
2297 }
2298
2299 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *adapter, bool op_type)
2300 {
2301 int i, index, err;
2302 u8 max_ints;
2303 u32 val, temp, type;
2304 struct qlcnic_cmd_args cmd;
2305
2306 max_ints = adapter->ahw->num_msix - 1;
2307 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTRPT);
2308 if (err)
2309 return err;
2310
2311 cmd.req.arg[1] = max_ints;
2312
2313 if (qlcnic_sriov_vf_check(adapter))
2314 cmd.req.arg[1] |= (adapter->ahw->pci_func << 8) | BIT_16;
2315
2316 for (i = 0, index = 2; i < max_ints; i++) {
2317 type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
2318 val = type | (adapter->ahw->intr_tbl[i].type << 4);
2319 if (adapter->ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
2320 val |= (adapter->ahw->intr_tbl[i].id << 16);
2321 cmd.req.arg[index++] = val;
2322 }
2323 err = qlcnic_issue_cmd(adapter, &cmd);
2324 if (err) {
2325 dev_err(&adapter->pdev->dev,
2326 "Failed to configure interrupts 0x%x\n", err);
2327 goto out;
2328 }
2329
2330 max_ints = cmd.rsp.arg[1];
2331 for (i = 0, index = 2; i < max_ints; i++, index += 2) {
2332 val = cmd.rsp.arg[index];
2333 if (LSB(val)) {
2334 dev_info(&adapter->pdev->dev,
2335 "Can't configure interrupt %d\n",
2336 adapter->ahw->intr_tbl[i].id);
2337 continue;
2338 }
2339 if (op_type) {
2340 adapter->ahw->intr_tbl[i].id = MSW(val);
2341 adapter->ahw->intr_tbl[i].enabled = 1;
2342 temp = cmd.rsp.arg[index + 1];
2343 adapter->ahw->intr_tbl[i].src = temp;
2344 } else {
2345 adapter->ahw->intr_tbl[i].id = i;
2346 adapter->ahw->intr_tbl[i].enabled = 0;
2347 adapter->ahw->intr_tbl[i].src = 0;
2348 }
2349 }
2350 out:
2351 qlcnic_free_mbx_args(&cmd);
2352 return err;
2353 }
2354
2355 int qlcnic_83xx_lock_flash(struct qlcnic_adapter *adapter)
2356 {
2357 int id, timeout = 0;
2358 u32 status = 0;
2359
2360 while (status == 0) {
2361 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK);
2362 if (status)
2363 break;
2364
2365 if (++timeout >= QLC_83XX_FLASH_LOCK_TIMEOUT) {
2366 id = QLC_SHARED_REG_RD32(adapter,
2367 QLCNIC_FLASH_LOCK_OWNER);
2368 dev_err(&adapter->pdev->dev,
2369 "%s: failed, lock held by %d\n", __func__, id);
2370 return -EIO;
2371 }
2372 usleep_range(1000, 2000);
2373 }
2374
2375 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, adapter->portnum);
2376 return 0;
2377 }
2378
2379 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *adapter)
2380 {
2381 QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK);
2382 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 0xFF);
2383 }
2384
2385 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter,
2386 u32 flash_addr, u8 *p_data,
2387 int count)
2388 {
2389 int i, ret;
2390 u32 word, range, flash_offset, addr = flash_addr;
2391 ulong indirect_add, direct_window;
2392
2393 flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1);
2394 if (addr & 0x3) {
2395 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2396 return -EIO;
2397 }
2398
2399 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_DIRECT_WINDOW,
2400 (addr));
2401
2402 range = flash_offset + (count * sizeof(u32));
2403 /* Check if data is spread across multiple sectors */
2404 if (range > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2405
2406 /* Multi sector read */
2407 for (i = 0; i < count; i++) {
2408 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2409 ret = qlcnic_83xx_rd_reg_indirect(adapter,
2410 indirect_add);
2411 if (ret == -EIO)
2412 return -EIO;
2413
2414 word = ret;
2415 *(u32 *)p_data = word;
2416 p_data = p_data + 4;
2417 addr = addr + 4;
2418 flash_offset = flash_offset + 4;
2419
2420 if (flash_offset > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2421 direct_window = QLC_83XX_FLASH_DIRECT_WINDOW;
2422 /* This write is needed once for each sector */
2423 qlcnic_83xx_wrt_reg_indirect(adapter,
2424 direct_window,
2425 (addr));
2426 flash_offset = 0;
2427 }
2428 }
2429 } else {
2430 /* Single sector read */
2431 for (i = 0; i < count; i++) {
2432 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2433 ret = qlcnic_83xx_rd_reg_indirect(adapter,
2434 indirect_add);
2435 if (ret == -EIO)
2436 return -EIO;
2437
2438 word = ret;
2439 *(u32 *)p_data = word;
2440 p_data = p_data + 4;
2441 addr = addr + 4;
2442 }
2443 }
2444
2445 return 0;
2446 }
2447
2448 static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter)
2449 {
2450 u32 status;
2451 int retries = QLC_83XX_FLASH_READ_RETRY_COUNT;
2452
2453 do {
2454 status = qlcnic_83xx_rd_reg_indirect(adapter,
2455 QLC_83XX_FLASH_STATUS);
2456 if ((status & QLC_83XX_FLASH_STATUS_READY) ==
2457 QLC_83XX_FLASH_STATUS_READY)
2458 break;
2459
2460 msleep(QLC_83XX_FLASH_STATUS_REG_POLL_DELAY);
2461 } while (--retries);
2462
2463 if (!retries)
2464 return -EIO;
2465
2466 return 0;
2467 }
2468
2469 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *adapter)
2470 {
2471 int ret;
2472 u32 cmd;
2473 cmd = adapter->ahw->fdt.write_statusreg_cmd;
2474 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2475 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | cmd));
2476 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2477 adapter->ahw->fdt.write_enable_bits);
2478 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2479 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2480 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2481 if (ret)
2482 return -EIO;
2483
2484 return 0;
2485 }
2486
2487 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *adapter)
2488 {
2489 int ret;
2490
2491 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2492 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG |
2493 adapter->ahw->fdt.write_statusreg_cmd));
2494 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2495 adapter->ahw->fdt.write_disable_bits);
2496 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2497 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2498 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2499 if (ret)
2500 return -EIO;
2501
2502 return 0;
2503 }
2504
2505 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter)
2506 {
2507 int ret, mfg_id;
2508
2509 if (qlcnic_83xx_lock_flash(adapter))
2510 return -EIO;
2511
2512 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2513 QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL);
2514 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2515 QLC_83XX_FLASH_READ_CTRL);
2516 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2517 if (ret) {
2518 qlcnic_83xx_unlock_flash(adapter);
2519 return -EIO;
2520 }
2521
2522 mfg_id = qlcnic_83xx_rd_reg_indirect(adapter, QLC_83XX_FLASH_RDDATA);
2523 if (mfg_id == -EIO)
2524 return -EIO;
2525
2526 adapter->flash_mfg_id = (mfg_id & 0xFF);
2527 qlcnic_83xx_unlock_flash(adapter);
2528
2529 return 0;
2530 }
2531
2532 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *adapter)
2533 {
2534 int count, fdt_size, ret = 0;
2535
2536 fdt_size = sizeof(struct qlcnic_fdt);
2537 count = fdt_size / sizeof(u32);
2538
2539 if (qlcnic_83xx_lock_flash(adapter))
2540 return -EIO;
2541
2542 memset(&adapter->ahw->fdt, 0, fdt_size);
2543 ret = qlcnic_83xx_lockless_flash_read32(adapter, QLCNIC_FDT_LOCATION,
2544 (u8 *)&adapter->ahw->fdt,
2545 count);
2546
2547 qlcnic_83xx_unlock_flash(adapter);
2548 return ret;
2549 }
2550
2551 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *adapter,
2552 u32 sector_start_addr)
2553 {
2554 u32 reversed_addr, addr1, addr2, cmd;
2555 int ret = -EIO;
2556
2557 if (qlcnic_83xx_lock_flash(adapter) != 0)
2558 return -EIO;
2559
2560 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2561 ret = qlcnic_83xx_enable_flash_write(adapter);
2562 if (ret) {
2563 qlcnic_83xx_unlock_flash(adapter);
2564 dev_err(&adapter->pdev->dev,
2565 "%s failed at %d\n",
2566 __func__, __LINE__);
2567 return ret;
2568 }
2569 }
2570
2571 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2572 if (ret) {
2573 qlcnic_83xx_unlock_flash(adapter);
2574 dev_err(&adapter->pdev->dev,
2575 "%s: failed at %d\n", __func__, __LINE__);
2576 return -EIO;
2577 }
2578
2579 addr1 = (sector_start_addr & 0xFF) << 16;
2580 addr2 = (sector_start_addr & 0xFF0000) >> 16;
2581 reversed_addr = addr1 | addr2;
2582
2583 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2584 reversed_addr);
2585 cmd = QLC_83XX_FLASH_FDT_ERASE_DEF_SIG | adapter->ahw->fdt.erase_cmd;
2586 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id)
2587 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, cmd);
2588 else
2589 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2590 QLC_83XX_FLASH_OEM_ERASE_SIG);
2591 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2592 QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2593
2594 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2595 if (ret) {
2596 qlcnic_83xx_unlock_flash(adapter);
2597 dev_err(&adapter->pdev->dev,
2598 "%s: failed at %d\n", __func__, __LINE__);
2599 return -EIO;
2600 }
2601
2602 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2603 ret = qlcnic_83xx_disable_flash_write(adapter);
2604 if (ret) {
2605 qlcnic_83xx_unlock_flash(adapter);
2606 dev_err(&adapter->pdev->dev,
2607 "%s: failed at %d\n", __func__, __LINE__);
2608 return ret;
2609 }
2610 }
2611
2612 qlcnic_83xx_unlock_flash(adapter);
2613
2614 return 0;
2615 }
2616
2617 int qlcnic_83xx_flash_write32(struct qlcnic_adapter *adapter, u32 addr,
2618 u32 *p_data)
2619 {
2620 int ret = -EIO;
2621 u32 addr1 = 0x00800000 | (addr >> 2);
2622
2623 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, addr1);
2624 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data);
2625 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2626 QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2627 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2628 if (ret) {
2629 dev_err(&adapter->pdev->dev,
2630 "%s: failed at %d\n", __func__, __LINE__);
2631 return -EIO;
2632 }
2633
2634 return 0;
2635 }
2636
2637 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr,
2638 u32 *p_data, int count)
2639 {
2640 u32 temp;
2641 int ret = -EIO;
2642
2643 if ((count < QLC_83XX_FLASH_WRITE_MIN) ||
2644 (count > QLC_83XX_FLASH_WRITE_MAX)) {
2645 dev_err(&adapter->pdev->dev,
2646 "%s: Invalid word count\n", __func__);
2647 return -EIO;
2648 }
2649
2650 temp = qlcnic_83xx_rd_reg_indirect(adapter,
2651 QLC_83XX_FLASH_SPI_CONTROL);
2652 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL,
2653 (temp | QLC_83XX_FLASH_SPI_CTRL));
2654 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2655 QLC_83XX_FLASH_ADDR_TEMP_VAL);
2656
2657 /* First DWORD write */
2658 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2659 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2660 QLC_83XX_FLASH_FIRST_MS_PATTERN);
2661 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2662 if (ret) {
2663 dev_err(&adapter->pdev->dev,
2664 "%s: failed at %d\n", __func__, __LINE__);
2665 return -EIO;
2666 }
2667
2668 count--;
2669 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2670 QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL);
2671 /* Second to N-1 DWORD writes */
2672 while (count != 1) {
2673 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2674 *p_data++);
2675 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2676 QLC_83XX_FLASH_SECOND_MS_PATTERN);
2677 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2678 if (ret) {
2679 dev_err(&adapter->pdev->dev,
2680 "%s: failed at %d\n", __func__, __LINE__);
2681 return -EIO;
2682 }
2683 count--;
2684 }
2685
2686 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2687 QLC_83XX_FLASH_ADDR_TEMP_VAL |
2688 (addr >> 2));
2689 /* Last DWORD write */
2690 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2691 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2692 QLC_83XX_FLASH_LAST_MS_PATTERN);
2693 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2694 if (ret) {
2695 dev_err(&adapter->pdev->dev,
2696 "%s: failed at %d\n", __func__, __LINE__);
2697 return -EIO;
2698 }
2699
2700 ret = qlcnic_83xx_rd_reg_indirect(adapter, QLC_83XX_FLASH_SPI_STATUS);
2701 if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) {
2702 dev_err(&adapter->pdev->dev, "%s: failed at %d\n",
2703 __func__, __LINE__);
2704 /* Operation failed, clear error bit */
2705 temp = qlcnic_83xx_rd_reg_indirect(adapter,
2706 QLC_83XX_FLASH_SPI_CONTROL);
2707 qlcnic_83xx_wrt_reg_indirect(adapter,
2708 QLC_83XX_FLASH_SPI_CONTROL,
2709 (temp | QLC_83XX_FLASH_SPI_CTRL));
2710 }
2711
2712 return 0;
2713 }
2714
2715 static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter *adapter)
2716 {
2717 u32 val, id;
2718
2719 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2720
2721 /* Check if recovery need to be performed by the calling function */
2722 if ((val & QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK) == 0) {
2723 val = val & ~0x3F;
2724 val = val | ((adapter->portnum << 2) |
2725 QLC_83XX_NEED_DRV_LOCK_RECOVERY);
2726 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2727 dev_info(&adapter->pdev->dev,
2728 "%s: lock recovery initiated\n", __func__);
2729 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY);
2730 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2731 id = ((val >> 2) & 0xF);
2732 if (id == adapter->portnum) {
2733 val = val & ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK;
2734 val = val | QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS;
2735 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2736 /* Force release the lock */
2737 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2738 /* Clear recovery bits */
2739 val = val & ~0x3F;
2740 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2741 dev_info(&adapter->pdev->dev,
2742 "%s: lock recovery completed\n", __func__);
2743 } else {
2744 dev_info(&adapter->pdev->dev,
2745 "%s: func %d to resume lock recovery process\n",
2746 __func__, id);
2747 }
2748 } else {
2749 dev_info(&adapter->pdev->dev,
2750 "%s: lock recovery initiated by other functions\n",
2751 __func__);
2752 }
2753 }
2754
2755 int qlcnic_83xx_lock_driver(struct qlcnic_adapter *adapter)
2756 {
2757 u32 lock_alive_counter, val, id, i = 0, status = 0, temp = 0;
2758 int max_attempt = 0;
2759
2760 while (status == 0) {
2761 status = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK);
2762 if (status)
2763 break;
2764
2765 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY);
2766 i++;
2767
2768 if (i == 1)
2769 temp = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2770
2771 if (i == QLC_83XX_DRV_LOCK_WAIT_COUNTER) {
2772 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2773 if (val == temp) {
2774 id = val & 0xFF;
2775 dev_info(&adapter->pdev->dev,
2776 "%s: lock to be recovered from %d\n",
2777 __func__, id);
2778 qlcnic_83xx_recover_driver_lock(adapter);
2779 i = 0;
2780 max_attempt++;
2781 } else {
2782 dev_err(&adapter->pdev->dev,
2783 "%s: failed to get lock\n", __func__);
2784 return -EIO;
2785 }
2786 }
2787
2788 /* Force exit from while loop after few attempts */
2789 if (max_attempt == QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT) {
2790 dev_err(&adapter->pdev->dev,
2791 "%s: failed to get lock\n", __func__);
2792 return -EIO;
2793 }
2794 }
2795
2796 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2797 lock_alive_counter = val >> 8;
2798 lock_alive_counter++;
2799 val = lock_alive_counter << 8 | adapter->portnum;
2800 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2801
2802 return 0;
2803 }
2804
2805 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *adapter)
2806 {
2807 u32 val, lock_alive_counter, id;
2808
2809 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2810 id = val & 0xFF;
2811 lock_alive_counter = val >> 8;
2812
2813 if (id != adapter->portnum)
2814 dev_err(&adapter->pdev->dev,
2815 "%s:Warning func %d is unlocking lock owned by %d\n",
2816 __func__, adapter->portnum, id);
2817
2818 val = (lock_alive_counter << 8) | 0xFF;
2819 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2820 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2821 }
2822
2823 int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr,
2824 u32 *data, u32 count)
2825 {
2826 int i, j, ret = 0;
2827 u32 temp;
2828
2829 /* Check alignment */
2830 if (addr & 0xF)
2831 return -EIO;
2832
2833 mutex_lock(&adapter->ahw->mem_lock);
2834 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_HI, 0);
2835
2836 for (i = 0; i < count; i++, addr += 16) {
2837 if (!((ADDR_IN_RANGE(addr, QLCNIC_ADDR_QDR_NET,
2838 QLCNIC_ADDR_QDR_NET_MAX)) ||
2839 (ADDR_IN_RANGE(addr, QLCNIC_ADDR_DDR_NET,
2840 QLCNIC_ADDR_DDR_NET_MAX)))) {
2841 mutex_unlock(&adapter->ahw->mem_lock);
2842 return -EIO;
2843 }
2844
2845 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_LO, addr);
2846 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_LO,
2847 *data++);
2848 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_HI,
2849 *data++);
2850 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_ULO,
2851 *data++);
2852 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_UHI,
2853 *data++);
2854 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2855 QLCNIC_TA_WRITE_ENABLE);
2856 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2857 QLCNIC_TA_WRITE_START);
2858
2859 for (j = 0; j < MAX_CTL_CHECK; j++) {
2860 temp = qlcnic_83xx_rd_reg_indirect(adapter,
2861 QLCNIC_MS_CTRL);
2862 if ((temp & TA_CTL_BUSY) == 0)
2863 break;
2864 }
2865
2866 /* Status check failure */
2867 if (j >= MAX_CTL_CHECK) {
2868 printk_ratelimited(KERN_WARNING
2869 "MS memory write failed\n");
2870 mutex_unlock(&adapter->ahw->mem_lock);
2871 return -EIO;
2872 }
2873 }
2874
2875 mutex_unlock(&adapter->ahw->mem_lock);
2876
2877 return ret;
2878 }
2879
2880 int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr,
2881 u8 *p_data, int count)
2882 {
2883 int i, ret;
2884 u32 word, addr = flash_addr;
2885 ulong indirect_addr;
2886
2887 if (qlcnic_83xx_lock_flash(adapter) != 0)
2888 return -EIO;
2889
2890 if (addr & 0x3) {
2891 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2892 qlcnic_83xx_unlock_flash(adapter);
2893 return -EIO;
2894 }
2895
2896 for (i = 0; i < count; i++) {
2897 if (qlcnic_83xx_wrt_reg_indirect(adapter,
2898 QLC_83XX_FLASH_DIRECT_WINDOW,
2899 (addr))) {
2900 qlcnic_83xx_unlock_flash(adapter);
2901 return -EIO;
2902 }
2903
2904 indirect_addr = QLC_83XX_FLASH_DIRECT_DATA(addr);
2905 ret = qlcnic_83xx_rd_reg_indirect(adapter,
2906 indirect_addr);
2907 if (ret == -EIO)
2908 return -EIO;
2909 word = ret;
2910 *(u32 *)p_data = word;
2911 p_data = p_data + 4;
2912 addr = addr + 4;
2913 }
2914
2915 qlcnic_83xx_unlock_flash(adapter);
2916
2917 return 0;
2918 }
2919
2920 int qlcnic_83xx_test_link(struct qlcnic_adapter *adapter)
2921 {
2922 u8 pci_func;
2923 int err;
2924 u32 config = 0, state;
2925 struct qlcnic_cmd_args cmd;
2926 struct qlcnic_hardware_context *ahw = adapter->ahw;
2927
2928 if (qlcnic_sriov_vf_check(adapter))
2929 pci_func = adapter->portnum;
2930 else
2931 pci_func = ahw->pci_func;
2932
2933 state = readl(ahw->pci_base0 + QLC_83XX_LINK_STATE(pci_func));
2934 if (!QLC_83xx_FUNC_VAL(state, pci_func)) {
2935 dev_info(&adapter->pdev->dev, "link state down\n");
2936 return config;
2937 }
2938
2939 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS);
2940 if (err)
2941 return err;
2942
2943 err = qlcnic_issue_cmd(adapter, &cmd);
2944 if (err) {
2945 dev_info(&adapter->pdev->dev,
2946 "Get Link Status Command failed: 0x%x\n", err);
2947 goto out;
2948 } else {
2949 config = cmd.rsp.arg[1];
2950 switch (QLC_83XX_CURRENT_LINK_SPEED(config)) {
2951 case QLC_83XX_10M_LINK:
2952 ahw->link_speed = SPEED_10;
2953 break;
2954 case QLC_83XX_100M_LINK:
2955 ahw->link_speed = SPEED_100;
2956 break;
2957 case QLC_83XX_1G_LINK:
2958 ahw->link_speed = SPEED_1000;
2959 break;
2960 case QLC_83XX_10G_LINK:
2961 ahw->link_speed = SPEED_10000;
2962 break;
2963 default:
2964 ahw->link_speed = 0;
2965 break;
2966 }
2967 config = cmd.rsp.arg[3];
2968 if (QLC_83XX_SFP_PRESENT(config)) {
2969 switch (ahw->module_type) {
2970 case LINKEVENT_MODULE_OPTICAL_UNKNOWN:
2971 case LINKEVENT_MODULE_OPTICAL_SRLR:
2972 case LINKEVENT_MODULE_OPTICAL_LRM:
2973 case LINKEVENT_MODULE_OPTICAL_SFP_1G:
2974 ahw->supported_type = PORT_FIBRE;
2975 break;
2976 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE:
2977 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN:
2978 case LINKEVENT_MODULE_TWINAX:
2979 ahw->supported_type = PORT_TP;
2980 break;
2981 default:
2982 ahw->supported_type = PORT_OTHER;
2983 }
2984 }
2985 if (config & 1)
2986 err = 1;
2987 }
2988 out:
2989 qlcnic_free_mbx_args(&cmd);
2990 return config;
2991 }
2992
2993 int qlcnic_83xx_get_settings(struct qlcnic_adapter *adapter,
2994 struct ethtool_cmd *ecmd)
2995 {
2996 u32 config = 0;
2997 int status = 0;
2998 struct qlcnic_hardware_context *ahw = adapter->ahw;
2999
3000 /* Get port configuration info */
3001 status = qlcnic_83xx_get_port_info(adapter);
3002 /* Get Link Status related info */
3003 config = qlcnic_83xx_test_link(adapter);
3004 ahw->module_type = QLC_83XX_SFP_MODULE_TYPE(config);
3005 /* hard code until there is a way to get it from flash */
3006 ahw->board_type = QLCNIC_BRDTYPE_83XX_10G;
3007
3008 if (netif_running(adapter->netdev) && ahw->has_link_events) {
3009 ethtool_cmd_speed_set(ecmd, ahw->link_speed);
3010 ecmd->duplex = ahw->link_duplex;
3011 ecmd->autoneg = ahw->link_autoneg;
3012 } else {
3013 ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN);
3014 ecmd->duplex = DUPLEX_UNKNOWN;
3015 ecmd->autoneg = AUTONEG_DISABLE;
3016 }
3017
3018 if (ahw->port_type == QLCNIC_XGBE) {
3019 ecmd->supported = SUPPORTED_1000baseT_Full;
3020 ecmd->advertising = ADVERTISED_1000baseT_Full;
3021 } else {
3022 ecmd->supported = (SUPPORTED_10baseT_Half |
3023 SUPPORTED_10baseT_Full |
3024 SUPPORTED_100baseT_Half |
3025 SUPPORTED_100baseT_Full |
3026 SUPPORTED_1000baseT_Half |
3027 SUPPORTED_1000baseT_Full);
3028 ecmd->advertising = (ADVERTISED_100baseT_Half |
3029 ADVERTISED_100baseT_Full |
3030 ADVERTISED_1000baseT_Half |
3031 ADVERTISED_1000baseT_Full);
3032 }
3033
3034 switch (ahw->supported_type) {
3035 case PORT_FIBRE:
3036 ecmd->supported |= SUPPORTED_FIBRE;
3037 ecmd->advertising |= ADVERTISED_FIBRE;
3038 ecmd->port = PORT_FIBRE;
3039 ecmd->transceiver = XCVR_EXTERNAL;
3040 break;
3041 case PORT_TP:
3042 ecmd->supported |= SUPPORTED_TP;
3043 ecmd->advertising |= ADVERTISED_TP;
3044 ecmd->port = PORT_TP;
3045 ecmd->transceiver = XCVR_INTERNAL;
3046 break;
3047 default:
3048 ecmd->supported |= SUPPORTED_FIBRE;
3049 ecmd->advertising |= ADVERTISED_FIBRE;
3050 ecmd->port = PORT_OTHER;
3051 ecmd->transceiver = XCVR_EXTERNAL;
3052 break;
3053 }
3054 ecmd->phy_address = ahw->physical_port;
3055 return status;
3056 }
3057
3058 int qlcnic_83xx_set_settings(struct qlcnic_adapter *adapter,
3059 struct ethtool_cmd *ecmd)
3060 {
3061 int status = 0;
3062 u32 config = adapter->ahw->port_config;
3063
3064 if (ecmd->autoneg)
3065 adapter->ahw->port_config |= BIT_15;
3066
3067 switch (ethtool_cmd_speed(ecmd)) {
3068 case SPEED_10:
3069 adapter->ahw->port_config |= BIT_8;
3070 break;
3071 case SPEED_100:
3072 adapter->ahw->port_config |= BIT_9;
3073 break;
3074 case SPEED_1000:
3075 adapter->ahw->port_config |= BIT_10;
3076 break;
3077 case SPEED_10000:
3078 adapter->ahw->port_config |= BIT_11;
3079 break;
3080 default:
3081 return -EINVAL;
3082 }
3083
3084 status = qlcnic_83xx_set_port_config(adapter);
3085 if (status) {
3086 dev_info(&adapter->pdev->dev,
3087 "Faild to Set Link Speed and autoneg.\n");
3088 adapter->ahw->port_config = config;
3089 }
3090 return status;
3091 }
3092
3093 static inline u64 *qlcnic_83xx_copy_stats(struct qlcnic_cmd_args *cmd,
3094 u64 *data, int index)
3095 {
3096 u32 low, hi;
3097 u64 val;
3098
3099 low = cmd->rsp.arg[index];
3100 hi = cmd->rsp.arg[index + 1];
3101 val = (((u64) low) | (((u64) hi) << 32));
3102 *data++ = val;
3103 return data;
3104 }
3105
3106 static u64 *qlcnic_83xx_fill_stats(struct qlcnic_adapter *adapter,
3107 struct qlcnic_cmd_args *cmd, u64 *data,
3108 int type, int *ret)
3109 {
3110 int err, k, total_regs;
3111
3112 *ret = 0;
3113 err = qlcnic_issue_cmd(adapter, cmd);
3114 if (err != QLCNIC_RCODE_SUCCESS) {
3115 dev_info(&adapter->pdev->dev,
3116 "Error in get statistics mailbox command\n");
3117 *ret = -EIO;
3118 return data;
3119 }
3120 total_regs = cmd->rsp.num;
3121 switch (type) {
3122 case QLC_83XX_STAT_MAC:
3123 /* fill in MAC tx counters */
3124 for (k = 2; k < 28; k += 2)
3125 data = qlcnic_83xx_copy_stats(cmd, data, k);
3126 /* skip 24 bytes of reserved area */
3127 /* fill in MAC rx counters */
3128 for (k += 6; k < 60; k += 2)
3129 data = qlcnic_83xx_copy_stats(cmd, data, k);
3130 /* skip 24 bytes of reserved area */
3131 /* fill in MAC rx frame stats */
3132 for (k += 6; k < 80; k += 2)
3133 data = qlcnic_83xx_copy_stats(cmd, data, k);
3134 /* fill in eSwitch stats */
3135 for (; k < total_regs; k += 2)
3136 data = qlcnic_83xx_copy_stats(cmd, data, k);
3137 break;
3138 case QLC_83XX_STAT_RX:
3139 for (k = 2; k < 8; k += 2)
3140 data = qlcnic_83xx_copy_stats(cmd, data, k);
3141 /* skip 8 bytes of reserved data */
3142 for (k += 2; k < 24; k += 2)
3143 data = qlcnic_83xx_copy_stats(cmd, data, k);
3144 /* skip 8 bytes containing RE1FBQ error data */
3145 for (k += 2; k < total_regs; k += 2)
3146 data = qlcnic_83xx_copy_stats(cmd, data, k);
3147 break;
3148 case QLC_83XX_STAT_TX:
3149 for (k = 2; k < 10; k += 2)
3150 data = qlcnic_83xx_copy_stats(cmd, data, k);
3151 /* skip 8 bytes of reserved data */
3152 for (k += 2; k < total_regs; k += 2)
3153 data = qlcnic_83xx_copy_stats(cmd, data, k);
3154 break;
3155 default:
3156 dev_warn(&adapter->pdev->dev, "Unknown get statistics mode\n");
3157 *ret = -EIO;
3158 }
3159 return data;
3160 }
3161
3162 void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data)
3163 {
3164 struct qlcnic_cmd_args cmd;
3165 struct net_device *netdev = adapter->netdev;
3166 int ret = 0;
3167
3168 ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_STATISTICS);
3169 if (ret)
3170 return;
3171 /* Get Tx stats */
3172 cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16);
3173 cmd.rsp.num = QLC_83XX_TX_STAT_REGS;
3174 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3175 QLC_83XX_STAT_TX, &ret);
3176 if (ret) {
3177 netdev_err(netdev, "Error getting Tx stats\n");
3178 goto out;
3179 }
3180 /* Get MAC stats */
3181 cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16);
3182 cmd.rsp.num = QLC_83XX_MAC_STAT_REGS;
3183 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3184 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3185 QLC_83XX_STAT_MAC, &ret);
3186 if (ret) {
3187 netdev_err(netdev, "Error getting MAC stats\n");
3188 goto out;
3189 }
3190 /* Get Rx stats */
3191 cmd.req.arg[1] = adapter->recv_ctx->context_id << 16;
3192 cmd.rsp.num = QLC_83XX_RX_STAT_REGS;
3193 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3194 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3195 QLC_83XX_STAT_RX, &ret);
3196 if (ret)
3197 netdev_err(netdev, "Error getting Rx stats\n");
3198 out:
3199 qlcnic_free_mbx_args(&cmd);
3200 }
3201
3202 int qlcnic_83xx_reg_test(struct qlcnic_adapter *adapter)
3203 {
3204 u32 major, minor, sub;
3205
3206 major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
3207 minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
3208 sub = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
3209
3210 if (adapter->fw_version != QLCNIC_VERSION_CODE(major, minor, sub)) {
3211 dev_info(&adapter->pdev->dev, "%s: Reg test failed\n",
3212 __func__);
3213 return 1;
3214 }
3215 return 0;
3216 }
3217
3218 int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *adapter)
3219 {
3220 return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl) *
3221 sizeof(adapter->ahw->ext_reg_tbl)) +
3222 (ARRAY_SIZE(qlcnic_83xx_reg_tbl) +
3223 sizeof(adapter->ahw->reg_tbl));
3224 }
3225
3226 int qlcnic_83xx_get_registers(struct qlcnic_adapter *adapter, u32 *regs_buff)
3227 {
3228 int i, j = 0;
3229
3230 for (i = QLCNIC_DEV_INFO_SIZE + 1;
3231 j < ARRAY_SIZE(qlcnic_83xx_reg_tbl); i++, j++)
3232 regs_buff[i] = QLC_SHARED_REG_RD32(adapter, j);
3233
3234 for (j = 0; j < ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl); j++)
3235 regs_buff[i++] = QLCRDX(adapter->ahw, j);
3236 return i;
3237 }
3238
3239 int qlcnic_83xx_interrupt_test(struct net_device *netdev)
3240 {
3241 struct qlcnic_adapter *adapter = netdev_priv(netdev);
3242 struct qlcnic_hardware_context *ahw = adapter->ahw;
3243 struct qlcnic_cmd_args cmd;
3244 u32 data;
3245 u16 intrpt_id, id;
3246 u8 val;
3247 int ret, max_sds_rings = adapter->max_sds_rings;
3248
3249 if (qlcnic_get_diag_lock(adapter)) {
3250 netdev_info(netdev, "Device in diagnostics mode\n");
3251 return -EBUSY;
3252 }
3253
3254 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_INTERRUPT_TEST,
3255 max_sds_rings);
3256 if (ret)
3257 goto fail_diag_irq;
3258
3259 ahw->diag_cnt = 0;
3260 ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INTRPT_TEST);
3261 if (ret)
3262 goto fail_diag_irq;
3263
3264 if (adapter->flags & QLCNIC_MSIX_ENABLED)
3265 intrpt_id = ahw->intr_tbl[0].id;
3266 else
3267 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
3268
3269 cmd.req.arg[1] = 1;
3270 cmd.req.arg[2] = intrpt_id;
3271 cmd.req.arg[3] = BIT_0;
3272
3273 ret = qlcnic_issue_cmd(adapter, &cmd);
3274 data = cmd.rsp.arg[2];
3275 id = LSW(data);
3276 val = LSB(MSW(data));
3277 if (id != intrpt_id)
3278 dev_info(&adapter->pdev->dev,
3279 "Interrupt generated: 0x%x, requested:0x%x\n",
3280 id, intrpt_id);
3281 if (val)
3282 dev_err(&adapter->pdev->dev,
3283 "Interrupt test error: 0x%x\n", val);
3284 if (ret)
3285 goto done;
3286
3287 msleep(20);
3288 ret = !ahw->diag_cnt;
3289
3290 done:
3291 qlcnic_free_mbx_args(&cmd);
3292 qlcnic_83xx_diag_free_res(netdev, max_sds_rings);
3293
3294 fail_diag_irq:
3295 adapter->max_sds_rings = max_sds_rings;
3296 qlcnic_release_diag_lock(adapter);
3297 return ret;
3298 }
3299
3300 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *adapter,
3301 struct ethtool_pauseparam *pause)
3302 {
3303 struct qlcnic_hardware_context *ahw = adapter->ahw;
3304 int status = 0;
3305 u32 config;
3306
3307 status = qlcnic_83xx_get_port_config(adapter);
3308 if (status) {
3309 dev_err(&adapter->pdev->dev,
3310 "%s: Get Pause Config failed\n", __func__);
3311 return;
3312 }
3313 config = ahw->port_config;
3314 if (config & QLC_83XX_CFG_STD_PAUSE) {
3315 if (config & QLC_83XX_CFG_STD_TX_PAUSE)
3316 pause->tx_pause = 1;
3317 if (config & QLC_83XX_CFG_STD_RX_PAUSE)
3318 pause->rx_pause = 1;
3319 }
3320
3321 if (QLC_83XX_AUTONEG(config))
3322 pause->autoneg = 1;
3323 }
3324
3325 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *adapter,
3326 struct ethtool_pauseparam *pause)
3327 {
3328 struct qlcnic_hardware_context *ahw = adapter->ahw;
3329 int status = 0;
3330 u32 config;
3331
3332 status = qlcnic_83xx_get_port_config(adapter);
3333 if (status) {
3334 dev_err(&adapter->pdev->dev,
3335 "%s: Get Pause Config failed.\n", __func__);
3336 return status;
3337 }
3338 config = ahw->port_config;
3339
3340 if (ahw->port_type == QLCNIC_GBE) {
3341 if (pause->autoneg)
3342 ahw->port_config |= QLC_83XX_ENABLE_AUTONEG;
3343 if (!pause->autoneg)
3344 ahw->port_config &= ~QLC_83XX_ENABLE_AUTONEG;
3345 } else if ((ahw->port_type == QLCNIC_XGBE) && (pause->autoneg)) {
3346 return -EOPNOTSUPP;
3347 }
3348
3349 if (!(config & QLC_83XX_CFG_STD_PAUSE))
3350 ahw->port_config |= QLC_83XX_CFG_STD_PAUSE;
3351
3352 if (pause->rx_pause && pause->tx_pause) {
3353 ahw->port_config |= QLC_83XX_CFG_STD_TX_RX_PAUSE;
3354 } else if (pause->rx_pause && !pause->tx_pause) {
3355 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_PAUSE;
3356 ahw->port_config |= QLC_83XX_CFG_STD_RX_PAUSE;
3357 } else if (pause->tx_pause && !pause->rx_pause) {
3358 ahw->port_config &= ~QLC_83XX_CFG_STD_RX_PAUSE;
3359 ahw->port_config |= QLC_83XX_CFG_STD_TX_PAUSE;
3360 } else if (!pause->rx_pause && !pause->tx_pause) {
3361 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_RX_PAUSE;
3362 }
3363 status = qlcnic_83xx_set_port_config(adapter);
3364 if (status) {
3365 dev_err(&adapter->pdev->dev,
3366 "%s: Set Pause Config failed.\n", __func__);
3367 ahw->port_config = config;
3368 }
3369 return status;
3370 }
3371
3372 static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter)
3373 {
3374 int ret;
3375
3376 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
3377 QLC_83XX_FLASH_OEM_READ_SIG);
3378 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
3379 QLC_83XX_FLASH_READ_CTRL);
3380 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
3381 if (ret)
3382 return -EIO;
3383
3384 ret = qlcnic_83xx_rd_reg_indirect(adapter, QLC_83XX_FLASH_RDDATA);
3385 return ret & 0xFF;
3386 }
3387
3388 int qlcnic_83xx_flash_test(struct qlcnic_adapter *adapter)
3389 {
3390 int status;
3391
3392 status = qlcnic_83xx_read_flash_status_reg(adapter);
3393 if (status == -EIO) {
3394 dev_info(&adapter->pdev->dev, "%s: EEPROM test failed.\n",
3395 __func__);
3396 return 1;
3397 }
3398 return 0;
3399 }
3400
3401 int qlcnic_83xx_shutdown(struct pci_dev *pdev)
3402 {
3403 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3404 struct net_device *netdev = adapter->netdev;
3405 int retval;
3406
3407 netif_device_detach(netdev);
3408 qlcnic_cancel_idc_work(adapter);
3409
3410 if (netif_running(netdev))
3411 qlcnic_down(adapter, netdev);
3412
3413 qlcnic_83xx_disable_mbx_intr(adapter);
3414 cancel_delayed_work_sync(&adapter->idc_aen_work);
3415
3416 retval = pci_save_state(pdev);
3417 if (retval)
3418 return retval;
3419
3420 return 0;
3421 }
3422
3423 int qlcnic_83xx_resume(struct qlcnic_adapter *adapter)
3424 {
3425 struct qlcnic_hardware_context *ahw = adapter->ahw;
3426 struct qlc_83xx_idc *idc = &ahw->idc;
3427 int err = 0;
3428
3429 err = qlcnic_83xx_idc_init(adapter);
3430 if (err)
3431 return err;
3432
3433 if (ahw->nic_mode == QLC_83XX_VIRTUAL_NIC_MODE) {
3434 if (ahw->op_mode == QLCNIC_MGMT_FUNC) {
3435 qlcnic_83xx_set_vnic_opmode(adapter);
3436 } else {
3437 err = qlcnic_83xx_check_vnic_state(adapter);
3438 if (err)
3439 return err;
3440 }
3441 }
3442
3443 err = qlcnic_83xx_idc_reattach_driver(adapter);
3444 if (err)
3445 return err;
3446
3447 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
3448 idc->delay);
3449 return err;
3450 }
3451
3452 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx)
3453 {
3454 INIT_COMPLETION(mbx->completion);
3455 set_bit(QLC_83XX_MBX_READY, &mbx->status);
3456 }
3457
3458 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx)
3459 {
3460 destroy_workqueue(mbx->work_q);
3461 kfree(mbx);
3462 }
3463
3464 static inline void
3465 qlcnic_83xx_notify_cmd_completion(struct qlcnic_adapter *adapter,
3466 struct qlcnic_cmd_args *cmd)
3467 {
3468 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
3469
3470 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
3471 qlcnic_free_mbx_args(cmd);
3472 kfree(cmd);
3473 return;
3474 }
3475 complete(&cmd->completion);
3476 }
3477
3478 static inline void qlcnic_83xx_flush_mbx_queue(struct qlcnic_adapter *adapter)
3479 {
3480 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3481 struct list_head *head = &mbx->cmd_q;
3482 struct qlcnic_cmd_args *cmd = NULL;
3483
3484 spin_lock(&mbx->queue_lock);
3485
3486 while (!list_empty(head)) {
3487 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3488 list_del(&cmd->list);
3489 mbx->num_cmds--;
3490 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3491 }
3492
3493 spin_unlock(&mbx->queue_lock);
3494 }
3495
3496 static inline int qlcnic_83xx_check_mbx_status(struct qlcnic_adapter *adapter)
3497 {
3498 struct qlcnic_hardware_context *ahw = adapter->ahw;
3499 struct qlcnic_mailbox *mbx = ahw->mailbox;
3500 u32 host_mbx_ctrl;
3501
3502 if (!test_bit(QLC_83XX_MBX_READY, &mbx->status))
3503 return -EBUSY;
3504
3505 host_mbx_ctrl = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
3506 if (host_mbx_ctrl) {
3507 ahw->idc.collect_dump = 1;
3508 return -EIO;
3509 }
3510
3511 return 0;
3512 }
3513
3514 static inline void qlcnic_83xx_signal_mbx_cmd(struct qlcnic_adapter *adapter,
3515 u8 issue_cmd)
3516 {
3517 if (issue_cmd)
3518 QLCWRX(adapter->ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER);
3519 else
3520 QLCWRX(adapter->ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
3521 }
3522
3523 static inline void qlcnic_83xx_dequeue_mbx_cmd(struct qlcnic_adapter *adapter,
3524 struct qlcnic_cmd_args *cmd)
3525 {
3526 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3527
3528 spin_lock(&mbx->queue_lock);
3529
3530 list_del(&cmd->list);
3531 mbx->num_cmds--;
3532
3533 spin_unlock(&mbx->queue_lock);
3534
3535 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3536 }
3537
3538 static void qlcnic_83xx_encode_mbx_cmd(struct qlcnic_adapter *adapter,
3539 struct qlcnic_cmd_args *cmd)
3540 {
3541 u32 mbx_cmd, fw_hal_version, hdr_size, total_size, tmp;
3542 struct qlcnic_hardware_context *ahw = adapter->ahw;
3543 int i, j;
3544
3545 if (cmd->op_type != QLC_83XX_MBX_POST_BC_OP) {
3546 mbx_cmd = cmd->req.arg[0];
3547 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3548 for (i = 1; i < cmd->req.num; i++)
3549 writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i));
3550 } else {
3551 fw_hal_version = ahw->fw_hal_version;
3552 hdr_size = sizeof(struct qlcnic_bc_hdr) / sizeof(u32);
3553 total_size = cmd->pay_size + hdr_size;
3554 tmp = QLCNIC_CMD_BC_EVENT_SETUP | total_size << 16;
3555 mbx_cmd = tmp | fw_hal_version << 29;
3556 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3557
3558 /* Back channel specific operations bits */
3559 mbx_cmd = 0x1 | 1 << 4;
3560
3561 if (qlcnic_sriov_pf_check(adapter))
3562 mbx_cmd |= cmd->func_num << 5;
3563
3564 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 1));
3565
3566 for (i = 2, j = 0; j < hdr_size; i++, j++)
3567 writel(*(cmd->hdr++), QLCNIC_MBX_HOST(ahw, i));
3568 for (j = 0; j < cmd->pay_size; j++, i++)
3569 writel(*(cmd->pay++), QLCNIC_MBX_HOST(ahw, i));
3570 }
3571 }
3572
3573 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *adapter)
3574 {
3575 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3576
3577 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3578 complete(&mbx->completion);
3579 cancel_work_sync(&mbx->work);
3580 flush_workqueue(mbx->work_q);
3581 qlcnic_83xx_flush_mbx_queue(adapter);
3582 }
3583
3584 static inline int qlcnic_83xx_enqueue_mbx_cmd(struct qlcnic_adapter *adapter,
3585 struct qlcnic_cmd_args *cmd,
3586 unsigned long *timeout)
3587 {
3588 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3589
3590 if (test_bit(QLC_83XX_MBX_READY, &mbx->status)) {
3591 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3592 init_completion(&cmd->completion);
3593 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_UNKNOWN;
3594
3595 spin_lock(&mbx->queue_lock);
3596
3597 list_add_tail(&cmd->list, &mbx->cmd_q);
3598 mbx->num_cmds++;
3599 cmd->total_cmds = mbx->num_cmds;
3600 *timeout = cmd->total_cmds * QLC_83XX_MBX_TIMEOUT;
3601 queue_work(mbx->work_q, &mbx->work);
3602
3603 spin_unlock(&mbx->queue_lock);
3604
3605 return 0;
3606 }
3607
3608 return -EBUSY;
3609 }
3610
3611 static inline int qlcnic_83xx_check_mac_rcode(struct qlcnic_adapter *adapter,
3612 struct qlcnic_cmd_args *cmd)
3613 {
3614 u8 mac_cmd_rcode;
3615 u32 fw_data;
3616
3617 if (cmd->cmd_op == QLCNIC_CMD_CONFIG_MAC_VLAN) {
3618 fw_data = readl(QLCNIC_MBX_FW(adapter->ahw, 2));
3619 mac_cmd_rcode = (u8)fw_data;
3620 if (mac_cmd_rcode == QLC_83XX_NO_NIC_RESOURCE ||
3621 mac_cmd_rcode == QLC_83XX_MAC_PRESENT ||
3622 mac_cmd_rcode == QLC_83XX_MAC_ABSENT) {
3623 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3624 return QLCNIC_RCODE_SUCCESS;
3625 }
3626 }
3627
3628 return -EINVAL;
3629 }
3630
3631 static void qlcnic_83xx_decode_mbx_rsp(struct qlcnic_adapter *adapter,
3632 struct qlcnic_cmd_args *cmd)
3633 {
3634 struct qlcnic_hardware_context *ahw = adapter->ahw;
3635 struct device *dev = &adapter->pdev->dev;
3636 u8 mbx_err_code;
3637 u32 fw_data;
3638
3639 fw_data = readl(QLCNIC_MBX_FW(ahw, 0));
3640 mbx_err_code = QLCNIC_MBX_STATUS(fw_data);
3641 qlcnic_83xx_get_mbx_data(adapter, cmd);
3642
3643 switch (mbx_err_code) {
3644 case QLCNIC_MBX_RSP_OK:
3645 case QLCNIC_MBX_PORT_RSP_OK:
3646 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3647 break;
3648 default:
3649 if (!qlcnic_83xx_check_mac_rcode(adapter, cmd))
3650 break;
3651
3652 dev_err(dev, "%s: Mailbox command failed, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x, error=0x%x\n",
3653 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
3654 ahw->op_mode, mbx_err_code);
3655 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_FAILED;
3656 qlcnic_dump_mbx(adapter, cmd);
3657 }
3658
3659 return;
3660 }
3661
3662 static void qlcnic_83xx_mailbox_worker(struct work_struct *work)
3663 {
3664 struct qlcnic_mailbox *mbx = container_of(work, struct qlcnic_mailbox,
3665 work);
3666 struct qlcnic_adapter *adapter = mbx->adapter;
3667 struct qlcnic_mbx_ops *mbx_ops = mbx->ops;
3668 struct device *dev = &adapter->pdev->dev;
3669 atomic_t *rsp_status = &mbx->rsp_status;
3670 struct list_head *head = &mbx->cmd_q;
3671 struct qlcnic_hardware_context *ahw;
3672 struct qlcnic_cmd_args *cmd = NULL;
3673
3674 ahw = adapter->ahw;
3675
3676 while (true) {
3677 if (qlcnic_83xx_check_mbx_status(adapter))
3678 return;
3679
3680 atomic_set(rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3681
3682 spin_lock(&mbx->queue_lock);
3683
3684 if (list_empty(head)) {
3685 spin_unlock(&mbx->queue_lock);
3686 return;
3687 }
3688 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3689
3690 spin_unlock(&mbx->queue_lock);
3691
3692 mbx_ops->encode_cmd(adapter, cmd);
3693 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_REQUEST);
3694
3695 if (wait_for_completion_timeout(&mbx->completion,
3696 QLC_83XX_MBX_TIMEOUT)) {
3697 mbx_ops->decode_resp(adapter, cmd);
3698 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_COMPLETION);
3699 } else {
3700 dev_err(dev, "%s: Mailbox command timeout, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x\n",
3701 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
3702 ahw->op_mode);
3703 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3704 qlcnic_83xx_idc_request_reset(adapter,
3705 QLCNIC_FORCE_FW_DUMP_KEY);
3706 cmd->rsp_opcode = QLCNIC_RCODE_TIMEOUT;
3707 }
3708 mbx_ops->dequeue_cmd(adapter, cmd);
3709 }
3710 }
3711
3712 static struct qlcnic_mbx_ops qlcnic_83xx_mbx_ops = {
3713 .enqueue_cmd = qlcnic_83xx_enqueue_mbx_cmd,
3714 .dequeue_cmd = qlcnic_83xx_dequeue_mbx_cmd,
3715 .decode_resp = qlcnic_83xx_decode_mbx_rsp,
3716 .encode_cmd = qlcnic_83xx_encode_mbx_cmd,
3717 .nofity_fw = qlcnic_83xx_signal_mbx_cmd,
3718 };
3719
3720 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *adapter)
3721 {
3722 struct qlcnic_hardware_context *ahw = adapter->ahw;
3723 struct qlcnic_mailbox *mbx;
3724
3725 ahw->mailbox = kzalloc(sizeof(*mbx), GFP_KERNEL);
3726 if (!ahw->mailbox)
3727 return -ENOMEM;
3728
3729 mbx = ahw->mailbox;
3730 mbx->ops = &qlcnic_83xx_mbx_ops;
3731 mbx->adapter = adapter;
3732
3733 spin_lock_init(&mbx->queue_lock);
3734 spin_lock_init(&mbx->aen_lock);
3735 INIT_LIST_HEAD(&mbx->cmd_q);
3736 init_completion(&mbx->completion);
3737
3738 mbx->work_q = create_singlethread_workqueue("qlcnic_mailbox");
3739 if (mbx->work_q == NULL) {
3740 kfree(mbx);
3741 return -ENOMEM;
3742 }
3743
3744 INIT_WORK(&mbx->work, qlcnic_83xx_mailbox_worker);
3745 set_bit(QLC_83XX_MBX_READY, &mbx->status);
3746 return 0;
3747 }
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