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qlcnic: Register netdev in FAILED state for 83xx/84xx
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic_83xx_hw.c
1 /*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
8 #include "qlcnic.h"
9 #include "qlcnic_sriov.h"
10 #include <linux/if_vlan.h>
11 #include <linux/ipv6.h>
12 #include <linux/ethtool.h>
13 #include <linux/interrupt.h>
14 #include <linux/aer.h>
15
16 #define QLCNIC_MAX_TX_QUEUES 1
17 #define RSS_HASHTYPE_IP_TCP 0x3
18 #define QLC_83XX_FW_MBX_CMD 0
19
20 static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = {
21 {QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1},
22 {QLCNIC_CMD_CONFIG_INTRPT, 18, 34},
23 {QLCNIC_CMD_CREATE_RX_CTX, 136, 27},
24 {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
25 {QLCNIC_CMD_CREATE_TX_CTX, 54, 18},
26 {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
27 {QLCNIC_CMD_CONFIGURE_MAC_LEARNING, 2, 1},
28 {QLCNIC_CMD_INTRPT_TEST, 22, 12},
29 {QLCNIC_CMD_SET_MTU, 3, 1},
30 {QLCNIC_CMD_READ_PHY, 4, 2},
31 {QLCNIC_CMD_WRITE_PHY, 5, 1},
32 {QLCNIC_CMD_READ_HW_REG, 4, 1},
33 {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
34 {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
35 {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
36 {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
37 {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
38 {QLCNIC_CMD_GET_PCI_INFO, 1, 66},
39 {QLCNIC_CMD_GET_NIC_INFO, 2, 19},
40 {QLCNIC_CMD_SET_NIC_INFO, 32, 1},
41 {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
42 {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
43 {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
44 {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
45 {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
46 {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
47 {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
48 {QLCNIC_CMD_CONFIG_PORT, 4, 1},
49 {QLCNIC_CMD_TEMP_SIZE, 1, 4},
50 {QLCNIC_CMD_GET_TEMP_HDR, 5, 5},
51 {QLCNIC_CMD_GET_LINK_EVENT, 2, 1},
52 {QLCNIC_CMD_CONFIG_MAC_VLAN, 4, 3},
53 {QLCNIC_CMD_CONFIG_INTR_COAL, 6, 1},
54 {QLCNIC_CMD_CONFIGURE_RSS, 14, 1},
55 {QLCNIC_CMD_CONFIGURE_LED, 2, 1},
56 {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE, 2, 1},
57 {QLCNIC_CMD_CONFIGURE_HW_LRO, 2, 1},
58 {QLCNIC_CMD_GET_STATISTICS, 2, 80},
59 {QLCNIC_CMD_SET_PORT_CONFIG, 2, 1},
60 {QLCNIC_CMD_GET_PORT_CONFIG, 2, 2},
61 {QLCNIC_CMD_GET_LINK_STATUS, 2, 4},
62 {QLCNIC_CMD_IDC_ACK, 5, 1},
63 {QLCNIC_CMD_INIT_NIC_FUNC, 2, 1},
64 {QLCNIC_CMD_STOP_NIC_FUNC, 2, 1},
65 {QLCNIC_CMD_SET_LED_CONFIG, 5, 1},
66 {QLCNIC_CMD_GET_LED_CONFIG, 1, 5},
67 {QLCNIC_CMD_83XX_SET_DRV_VER, 4, 1},
68 {QLCNIC_CMD_ADD_RCV_RINGS, 130, 26},
69 {QLCNIC_CMD_CONFIG_VPORT, 4, 4},
70 {QLCNIC_CMD_BC_EVENT_SETUP, 2, 1},
71 {QLCNIC_CMD_DCB_QUERY_CAP, 1, 2},
72 {QLCNIC_CMD_DCB_QUERY_PARAM, 2, 50},
73 };
74
75 const u32 qlcnic_83xx_ext_reg_tbl[] = {
76 0x38CC, /* Global Reset */
77 0x38F0, /* Wildcard */
78 0x38FC, /* Informant */
79 0x3038, /* Host MBX ctrl */
80 0x303C, /* FW MBX ctrl */
81 0x355C, /* BOOT LOADER ADDRESS REG */
82 0x3560, /* BOOT LOADER SIZE REG */
83 0x3564, /* FW IMAGE ADDR REG */
84 0x1000, /* MBX intr enable */
85 0x1200, /* Default Intr mask */
86 0x1204, /* Default Interrupt ID */
87 0x3780, /* QLC_83XX_IDC_MAJ_VERSION */
88 0x3784, /* QLC_83XX_IDC_DEV_STATE */
89 0x3788, /* QLC_83XX_IDC_DRV_PRESENCE */
90 0x378C, /* QLC_83XX_IDC_DRV_ACK */
91 0x3790, /* QLC_83XX_IDC_CTRL */
92 0x3794, /* QLC_83XX_IDC_DRV_AUDIT */
93 0x3798, /* QLC_83XX_IDC_MIN_VERSION */
94 0x379C, /* QLC_83XX_RECOVER_DRV_LOCK */
95 0x37A0, /* QLC_83XX_IDC_PF_0 */
96 0x37A4, /* QLC_83XX_IDC_PF_1 */
97 0x37A8, /* QLC_83XX_IDC_PF_2 */
98 0x37AC, /* QLC_83XX_IDC_PF_3 */
99 0x37B0, /* QLC_83XX_IDC_PF_4 */
100 0x37B4, /* QLC_83XX_IDC_PF_5 */
101 0x37B8, /* QLC_83XX_IDC_PF_6 */
102 0x37BC, /* QLC_83XX_IDC_PF_7 */
103 0x37C0, /* QLC_83XX_IDC_PF_8 */
104 0x37C4, /* QLC_83XX_IDC_PF_9 */
105 0x37C8, /* QLC_83XX_IDC_PF_10 */
106 0x37CC, /* QLC_83XX_IDC_PF_11 */
107 0x37D0, /* QLC_83XX_IDC_PF_12 */
108 0x37D4, /* QLC_83XX_IDC_PF_13 */
109 0x37D8, /* QLC_83XX_IDC_PF_14 */
110 0x37DC, /* QLC_83XX_IDC_PF_15 */
111 0x37E0, /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */
112 0x37E4, /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */
113 0x37F0, /* QLC_83XX_DRV_OP_MODE */
114 0x37F4, /* QLC_83XX_VNIC_STATE */
115 0x3868, /* QLC_83XX_DRV_LOCK */
116 0x386C, /* QLC_83XX_DRV_UNLOCK */
117 0x3504, /* QLC_83XX_DRV_LOCK_ID */
118 0x34A4, /* QLC_83XX_ASIC_TEMP */
119 };
120
121 const u32 qlcnic_83xx_reg_tbl[] = {
122 0x34A8, /* PEG_HALT_STAT1 */
123 0x34AC, /* PEG_HALT_STAT2 */
124 0x34B0, /* FW_HEARTBEAT */
125 0x3500, /* FLASH LOCK_ID */
126 0x3528, /* FW_CAPABILITIES */
127 0x3538, /* Driver active, DRV_REG0 */
128 0x3540, /* Device state, DRV_REG1 */
129 0x3544, /* Driver state, DRV_REG2 */
130 0x3548, /* Driver scratch, DRV_REG3 */
131 0x354C, /* Device partiton info, DRV_REG4 */
132 0x3524, /* Driver IDC ver, DRV_REG5 */
133 0x3550, /* FW_VER_MAJOR */
134 0x3554, /* FW_VER_MINOR */
135 0x3558, /* FW_VER_SUB */
136 0x359C, /* NPAR STATE */
137 0x35FC, /* FW_IMG_VALID */
138 0x3650, /* CMD_PEG_STATE */
139 0x373C, /* RCV_PEG_STATE */
140 0x37B4, /* ASIC TEMP */
141 0x356C, /* FW API */
142 0x3570, /* DRV OP MODE */
143 0x3850, /* FLASH LOCK */
144 0x3854, /* FLASH UNLOCK */
145 };
146
147 static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = {
148 .read_crb = qlcnic_83xx_read_crb,
149 .write_crb = qlcnic_83xx_write_crb,
150 .read_reg = qlcnic_83xx_rd_reg_indirect,
151 .write_reg = qlcnic_83xx_wrt_reg_indirect,
152 .get_mac_address = qlcnic_83xx_get_mac_address,
153 .setup_intr = qlcnic_83xx_setup_intr,
154 .alloc_mbx_args = qlcnic_83xx_alloc_mbx_args,
155 .mbx_cmd = qlcnic_83xx_issue_cmd,
156 .get_func_no = qlcnic_83xx_get_func_no,
157 .api_lock = qlcnic_83xx_cam_lock,
158 .api_unlock = qlcnic_83xx_cam_unlock,
159 .add_sysfs = qlcnic_83xx_add_sysfs,
160 .remove_sysfs = qlcnic_83xx_remove_sysfs,
161 .process_lb_rcv_ring_diag = qlcnic_83xx_process_rcv_ring_diag,
162 .create_rx_ctx = qlcnic_83xx_create_rx_ctx,
163 .create_tx_ctx = qlcnic_83xx_create_tx_ctx,
164 .del_rx_ctx = qlcnic_83xx_del_rx_ctx,
165 .del_tx_ctx = qlcnic_83xx_del_tx_ctx,
166 .setup_link_event = qlcnic_83xx_setup_link_event,
167 .get_nic_info = qlcnic_83xx_get_nic_info,
168 .get_pci_info = qlcnic_83xx_get_pci_info,
169 .set_nic_info = qlcnic_83xx_set_nic_info,
170 .change_macvlan = qlcnic_83xx_sre_macaddr_change,
171 .napi_enable = qlcnic_83xx_napi_enable,
172 .napi_disable = qlcnic_83xx_napi_disable,
173 .config_intr_coal = qlcnic_83xx_config_intr_coal,
174 .config_rss = qlcnic_83xx_config_rss,
175 .config_hw_lro = qlcnic_83xx_config_hw_lro,
176 .config_promisc_mode = qlcnic_83xx_nic_set_promisc,
177 .change_l2_filter = qlcnic_83xx_change_l2_filter,
178 .get_board_info = qlcnic_83xx_get_port_info,
179 .set_mac_filter_count = qlcnic_83xx_set_mac_filter_count,
180 .free_mac_list = qlcnic_82xx_free_mac_list,
181 .io_error_detected = qlcnic_83xx_io_error_detected,
182 .io_slot_reset = qlcnic_83xx_io_slot_reset,
183 .io_resume = qlcnic_83xx_io_resume,
184
185 };
186
187 static struct qlcnic_nic_template qlcnic_83xx_ops = {
188 .config_bridged_mode = qlcnic_config_bridged_mode,
189 .config_led = qlcnic_config_led,
190 .request_reset = qlcnic_83xx_idc_request_reset,
191 .cancel_idc_work = qlcnic_83xx_idc_exit,
192 .napi_add = qlcnic_83xx_napi_add,
193 .napi_del = qlcnic_83xx_napi_del,
194 .config_ipaddr = qlcnic_83xx_config_ipaddr,
195 .clear_legacy_intr = qlcnic_83xx_clear_legacy_intr,
196 .shutdown = qlcnic_83xx_shutdown,
197 .resume = qlcnic_83xx_resume,
198 };
199
200 void qlcnic_83xx_register_map(struct qlcnic_hardware_context *ahw)
201 {
202 ahw->hw_ops = &qlcnic_83xx_hw_ops;
203 ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl;
204 ahw->ext_reg_tbl = (u32 *)qlcnic_83xx_ext_reg_tbl;
205 }
206
207 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *adapter)
208 {
209 u32 fw_major, fw_minor, fw_build;
210 struct pci_dev *pdev = adapter->pdev;
211
212 fw_major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
213 fw_minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
214 fw_build = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
215 adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build);
216
217 dev_info(&pdev->dev, "Driver v%s, firmware version %d.%d.%d\n",
218 QLCNIC_LINUX_VERSIONID, fw_major, fw_minor, fw_build);
219
220 return adapter->fw_version;
221 }
222
223 static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr)
224 {
225 void __iomem *base;
226 u32 val;
227
228 base = adapter->ahw->pci_base0 +
229 QLC_83XX_CRB_WIN_FUNC(adapter->ahw->pci_func);
230 writel(addr, base);
231 val = readl(base);
232 if (val != addr)
233 return -EIO;
234
235 return 0;
236 }
237
238 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
239 int *err)
240 {
241 struct qlcnic_hardware_context *ahw = adapter->ahw;
242
243 *err = __qlcnic_set_win_base(adapter, (u32) addr);
244 if (!*err) {
245 return QLCRDX(ahw, QLCNIC_WILDCARD);
246 } else {
247 dev_err(&adapter->pdev->dev,
248 "%s failed, addr = 0x%lx\n", __func__, addr);
249 return -EIO;
250 }
251 }
252
253 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
254 u32 data)
255 {
256 int err;
257 struct qlcnic_hardware_context *ahw = adapter->ahw;
258
259 err = __qlcnic_set_win_base(adapter, (u32) addr);
260 if (!err) {
261 QLCWRX(ahw, QLCNIC_WILDCARD, data);
262 return 0;
263 } else {
264 dev_err(&adapter->pdev->dev,
265 "%s failed, addr = 0x%x data = 0x%x\n",
266 __func__, (int)addr, data);
267 return err;
268 }
269 }
270
271 int qlcnic_83xx_setup_intr(struct qlcnic_adapter *adapter, u8 num_intr, int txq)
272 {
273 int err, i, num_msix;
274 struct qlcnic_hardware_context *ahw = adapter->ahw;
275
276 if (!num_intr)
277 num_intr = QLCNIC_DEF_NUM_STS_DESC_RINGS;
278 num_msix = rounddown_pow_of_two(min_t(int, num_online_cpus(),
279 num_intr));
280 /* account for AEN interrupt MSI-X based interrupts */
281 num_msix += 1;
282
283 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
284 num_msix += adapter->max_drv_tx_rings;
285
286 err = qlcnic_enable_msix(adapter, num_msix);
287 if (err == -ENOMEM)
288 return err;
289 if (adapter->flags & QLCNIC_MSIX_ENABLED)
290 num_msix = adapter->ahw->num_msix;
291 else {
292 if (qlcnic_sriov_vf_check(adapter))
293 return -EINVAL;
294 num_msix = 1;
295 }
296 /* setup interrupt mapping table for fw */
297 ahw->intr_tbl = vzalloc(num_msix *
298 sizeof(struct qlcnic_intrpt_config));
299 if (!ahw->intr_tbl)
300 return -ENOMEM;
301 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
302 /* MSI-X enablement failed, use legacy interrupt */
303 adapter->tgt_status_reg = ahw->pci_base0 + QLC_83XX_INTX_PTR;
304 adapter->tgt_mask_reg = ahw->pci_base0 + QLC_83XX_INTX_MASK;
305 adapter->isr_int_vec = ahw->pci_base0 + QLC_83XX_INTX_TRGR;
306 adapter->msix_entries[0].vector = adapter->pdev->irq;
307 dev_info(&adapter->pdev->dev, "using legacy interrupt\n");
308 }
309
310 for (i = 0; i < num_msix; i++) {
311 if (adapter->flags & QLCNIC_MSIX_ENABLED)
312 ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX;
313 else
314 ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX;
315 ahw->intr_tbl[i].id = i;
316 ahw->intr_tbl[i].src = 0;
317 }
318 return 0;
319 }
320
321 inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter)
322 {
323 writel(0, adapter->tgt_mask_reg);
324 }
325
326 inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter *adapter)
327 {
328 if (adapter->tgt_mask_reg)
329 writel(1, adapter->tgt_mask_reg);
330 }
331
332 /* Enable MSI-x and INT-x interrupts */
333 void qlcnic_83xx_enable_intr(struct qlcnic_adapter *adapter,
334 struct qlcnic_host_sds_ring *sds_ring)
335 {
336 writel(0, sds_ring->crb_intr_mask);
337 }
338
339 /* Disable MSI-x and INT-x interrupts */
340 void qlcnic_83xx_disable_intr(struct qlcnic_adapter *adapter,
341 struct qlcnic_host_sds_ring *sds_ring)
342 {
343 writel(1, sds_ring->crb_intr_mask);
344 }
345
346 inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
347 *adapter)
348 {
349 u32 mask;
350
351 /* Mailbox in MSI-x mode and Legacy Interrupt share the same
352 * source register. We could be here before contexts are created
353 * and sds_ring->crb_intr_mask has not been initialized, calculate
354 * BAR offset for Interrupt Source Register
355 */
356 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
357 writel(0, adapter->ahw->pci_base0 + mask);
358 }
359
360 void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter)
361 {
362 u32 mask;
363
364 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
365 writel(1, adapter->ahw->pci_base0 + mask);
366 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0);
367 }
368
369 static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter,
370 struct qlcnic_cmd_args *cmd)
371 {
372 int i;
373
374 if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
375 return;
376
377 for (i = 0; i < cmd->rsp.num; i++)
378 cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i));
379 }
380
381 irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter)
382 {
383 u32 intr_val;
384 struct qlcnic_hardware_context *ahw = adapter->ahw;
385 int retries = 0;
386
387 intr_val = readl(adapter->tgt_status_reg);
388
389 if (!QLC_83XX_VALID_INTX_BIT31(intr_val))
390 return IRQ_NONE;
391
392 if (QLC_83XX_INTX_FUNC(intr_val) != adapter->ahw->pci_func) {
393 adapter->stats.spurious_intr++;
394 return IRQ_NONE;
395 }
396 /* The barrier is required to ensure writes to the registers */
397 wmb();
398
399 /* clear the interrupt trigger control register */
400 writel(0, adapter->isr_int_vec);
401 intr_val = readl(adapter->isr_int_vec);
402 do {
403 intr_val = readl(adapter->tgt_status_reg);
404 if (QLC_83XX_INTX_FUNC(intr_val) != ahw->pci_func)
405 break;
406 retries++;
407 } while (QLC_83XX_VALID_INTX_BIT30(intr_val) &&
408 (retries < QLC_83XX_LEGACY_INTX_MAX_RETRY));
409
410 return IRQ_HANDLED;
411 }
412
413 static inline void qlcnic_83xx_notify_mbx_response(struct qlcnic_mailbox *mbx)
414 {
415 atomic_set(&mbx->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
416 complete(&mbx->completion);
417 }
418
419 static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter *adapter)
420 {
421 u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
422 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
423 unsigned long flags;
424
425 spin_lock_irqsave(&mbx->aen_lock, flags);
426 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
427 if (!(resp & QLCNIC_SET_OWNER))
428 goto out;
429
430 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
431 if (event & QLCNIC_MBX_ASYNC_EVENT) {
432 __qlcnic_83xx_process_aen(adapter);
433 } else {
434 if (atomic_read(&mbx->rsp_status) != rsp_status)
435 qlcnic_83xx_notify_mbx_response(mbx);
436 }
437 out:
438 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
439 spin_unlock_irqrestore(&mbx->aen_lock, flags);
440 }
441
442 irqreturn_t qlcnic_83xx_intr(int irq, void *data)
443 {
444 struct qlcnic_adapter *adapter = data;
445 struct qlcnic_host_sds_ring *sds_ring;
446 struct qlcnic_hardware_context *ahw = adapter->ahw;
447
448 if (qlcnic_83xx_clear_legacy_intr(adapter) == IRQ_NONE)
449 return IRQ_NONE;
450
451 qlcnic_83xx_poll_process_aen(adapter);
452
453 if (ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
454 ahw->diag_cnt++;
455 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
456 return IRQ_HANDLED;
457 }
458
459 if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
460 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
461 } else {
462 sds_ring = &adapter->recv_ctx->sds_rings[0];
463 napi_schedule(&sds_ring->napi);
464 }
465
466 return IRQ_HANDLED;
467 }
468
469 irqreturn_t qlcnic_83xx_tmp_intr(int irq, void *data)
470 {
471 struct qlcnic_host_sds_ring *sds_ring = data;
472 struct qlcnic_adapter *adapter = sds_ring->adapter;
473
474 if (adapter->flags & QLCNIC_MSIX_ENABLED)
475 goto done;
476
477 if (adapter->nic_ops->clear_legacy_intr(adapter) == IRQ_NONE)
478 return IRQ_NONE;
479
480 done:
481 adapter->ahw->diag_cnt++;
482 qlcnic_83xx_enable_intr(adapter, sds_ring);
483
484 return IRQ_HANDLED;
485 }
486
487 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *adapter)
488 {
489 u32 num_msix;
490
491 if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
492 qlcnic_83xx_set_legacy_intr_mask(adapter);
493
494 qlcnic_83xx_disable_mbx_intr(adapter);
495
496 if (adapter->flags & QLCNIC_MSIX_ENABLED)
497 num_msix = adapter->ahw->num_msix - 1;
498 else
499 num_msix = 0;
500
501 msleep(20);
502
503 if (adapter->msix_entries) {
504 synchronize_irq(adapter->msix_entries[num_msix].vector);
505 free_irq(adapter->msix_entries[num_msix].vector, adapter);
506 }
507 }
508
509 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *adapter)
510 {
511 irq_handler_t handler;
512 u32 val;
513 int err = 0;
514 unsigned long flags = 0;
515
516 if (!(adapter->flags & QLCNIC_MSI_ENABLED) &&
517 !(adapter->flags & QLCNIC_MSIX_ENABLED))
518 flags |= IRQF_SHARED;
519
520 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
521 handler = qlcnic_83xx_handle_aen;
522 val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector;
523 err = request_irq(val, handler, flags, "qlcnic-MB", adapter);
524 if (err) {
525 dev_err(&adapter->pdev->dev,
526 "failed to register MBX interrupt\n");
527 return err;
528 }
529 } else {
530 handler = qlcnic_83xx_intr;
531 val = adapter->msix_entries[0].vector;
532 err = request_irq(val, handler, flags, "qlcnic", adapter);
533 if (err) {
534 dev_err(&adapter->pdev->dev,
535 "failed to register INTx interrupt\n");
536 return err;
537 }
538 qlcnic_83xx_clear_legacy_intr_mask(adapter);
539 }
540
541 /* Enable mailbox interrupt */
542 qlcnic_83xx_enable_mbx_interrupt(adapter);
543
544 return err;
545 }
546
547 void qlcnic_83xx_get_func_no(struct qlcnic_adapter *adapter)
548 {
549 u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT);
550 adapter->ahw->pci_func = (val >> 24) & 0xff;
551 }
552
553 int qlcnic_83xx_cam_lock(struct qlcnic_adapter *adapter)
554 {
555 void __iomem *addr;
556 u32 val, limit = 0;
557
558 struct qlcnic_hardware_context *ahw = adapter->ahw;
559
560 addr = ahw->pci_base0 + QLC_83XX_SEM_LOCK_FUNC(ahw->pci_func);
561 do {
562 val = readl(addr);
563 if (val) {
564 /* write the function number to register */
565 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER,
566 ahw->pci_func);
567 return 0;
568 }
569 usleep_range(1000, 2000);
570 } while (++limit <= QLCNIC_PCIE_SEM_TIMEOUT);
571
572 return -EIO;
573 }
574
575 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter)
576 {
577 void __iomem *addr;
578 u32 val;
579 struct qlcnic_hardware_context *ahw = adapter->ahw;
580
581 addr = ahw->pci_base0 + QLC_83XX_SEM_UNLOCK_FUNC(ahw->pci_func);
582 val = readl(addr);
583 }
584
585 void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
586 loff_t offset, size_t size)
587 {
588 int ret = 0;
589 u32 data;
590
591 if (qlcnic_api_lock(adapter)) {
592 dev_err(&adapter->pdev->dev,
593 "%s: failed to acquire lock. addr offset 0x%x\n",
594 __func__, (u32)offset);
595 return;
596 }
597
598 data = QLCRD32(adapter, (u32) offset, &ret);
599 qlcnic_api_unlock(adapter);
600
601 if (ret == -EIO) {
602 dev_err(&adapter->pdev->dev,
603 "%s: failed. addr offset 0x%x\n",
604 __func__, (u32)offset);
605 return;
606 }
607 memcpy(buf, &data, size);
608 }
609
610 void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
611 loff_t offset, size_t size)
612 {
613 u32 data;
614
615 memcpy(&data, buf, size);
616 qlcnic_83xx_wrt_reg_indirect(adapter, (u32) offset, data);
617 }
618
619 int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter)
620 {
621 int status;
622
623 status = qlcnic_83xx_get_port_config(adapter);
624 if (status) {
625 dev_err(&adapter->pdev->dev,
626 "Get Port Info failed\n");
627 } else {
628 if (QLC_83XX_SFP_10G_CAPABLE(adapter->ahw->port_config))
629 adapter->ahw->port_type = QLCNIC_XGBE;
630 else
631 adapter->ahw->port_type = QLCNIC_GBE;
632
633 if (QLC_83XX_AUTONEG(adapter->ahw->port_config))
634 adapter->ahw->link_autoneg = AUTONEG_ENABLE;
635 }
636 return status;
637 }
638
639 void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *adapter)
640 {
641 struct qlcnic_hardware_context *ahw = adapter->ahw;
642 u16 act_pci_fn = ahw->act_pci_func;
643 u16 count;
644
645 ahw->max_mc_count = QLC_83XX_MAX_MC_COUNT;
646 if (act_pci_fn <= 2)
647 count = (QLC_83XX_MAX_UC_COUNT - QLC_83XX_MAX_MC_COUNT) /
648 act_pci_fn;
649 else
650 count = (QLC_83XX_LB_MAX_FILTERS - QLC_83XX_MAX_MC_COUNT) /
651 act_pci_fn;
652 ahw->max_uc_count = count;
653 }
654
655 void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *adapter)
656 {
657 u32 val;
658
659 if (adapter->flags & QLCNIC_MSIX_ENABLED)
660 val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8);
661 else
662 val = BIT_2;
663
664 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val);
665 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
666 }
667
668 void qlcnic_83xx_check_vf(struct qlcnic_adapter *adapter,
669 const struct pci_device_id *ent)
670 {
671 u32 op_mode, priv_level;
672 struct qlcnic_hardware_context *ahw = adapter->ahw;
673
674 ahw->fw_hal_version = 2;
675 qlcnic_get_func_no(adapter);
676
677 if (qlcnic_sriov_vf_check(adapter)) {
678 qlcnic_sriov_vf_set_ops(adapter);
679 return;
680 }
681
682 /* Determine function privilege level */
683 op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE);
684 if (op_mode == QLC_83XX_DEFAULT_OPMODE)
685 priv_level = QLCNIC_MGMT_FUNC;
686 else
687 priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode,
688 ahw->pci_func);
689
690 if (priv_level == QLCNIC_NON_PRIV_FUNC) {
691 ahw->op_mode = QLCNIC_NON_PRIV_FUNC;
692 dev_info(&adapter->pdev->dev,
693 "HAL Version: %d Non Privileged function\n",
694 ahw->fw_hal_version);
695 adapter->nic_ops = &qlcnic_vf_ops;
696 } else {
697 if (pci_find_ext_capability(adapter->pdev,
698 PCI_EXT_CAP_ID_SRIOV))
699 set_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state);
700 adapter->nic_ops = &qlcnic_83xx_ops;
701 }
702 }
703
704 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
705 u32 data[]);
706 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
707 u32 data[]);
708
709 void qlcnic_dump_mbx(struct qlcnic_adapter *adapter,
710 struct qlcnic_cmd_args *cmd)
711 {
712 int i;
713
714 if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
715 return;
716
717 dev_info(&adapter->pdev->dev,
718 "Host MBX regs(%d)\n", cmd->req.num);
719 for (i = 0; i < cmd->req.num; i++) {
720 if (i && !(i % 8))
721 pr_info("\n");
722 pr_info("%08x ", cmd->req.arg[i]);
723 }
724 pr_info("\n");
725 dev_info(&adapter->pdev->dev,
726 "FW MBX regs(%d)\n", cmd->rsp.num);
727 for (i = 0; i < cmd->rsp.num; i++) {
728 if (i && !(i % 8))
729 pr_info("\n");
730 pr_info("%08x ", cmd->rsp.arg[i]);
731 }
732 pr_info("\n");
733 }
734
735 static void qlcnic_83xx_poll_for_mbx_completion(struct qlcnic_adapter *adapter,
736 struct qlcnic_cmd_args *cmd)
737 {
738 struct qlcnic_hardware_context *ahw = adapter->ahw;
739 int opcode = LSW(cmd->req.arg[0]);
740 unsigned long max_loops;
741
742 max_loops = cmd->total_cmds * QLC_83XX_MBX_CMD_LOOP;
743
744 for (; max_loops; max_loops--) {
745 if (atomic_read(&cmd->rsp_status) ==
746 QLC_83XX_MBX_RESPONSE_ARRIVED)
747 return;
748
749 udelay(1);
750 }
751
752 dev_err(&adapter->pdev->dev,
753 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
754 __func__, opcode, cmd->type, ahw->pci_func, ahw->op_mode);
755 flush_workqueue(ahw->mailbox->work_q);
756 return;
757 }
758
759 int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *adapter,
760 struct qlcnic_cmd_args *cmd)
761 {
762 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
763 struct qlcnic_hardware_context *ahw = adapter->ahw;
764 int cmd_type, err, opcode;
765 unsigned long timeout;
766
767 if (!mbx)
768 return -EIO;
769
770 opcode = LSW(cmd->req.arg[0]);
771 cmd_type = cmd->type;
772 err = mbx->ops->enqueue_cmd(adapter, cmd, &timeout);
773 if (err) {
774 dev_err(&adapter->pdev->dev,
775 "%s: Mailbox not available, cmd_op=0x%x, cmd_context=0x%x, pci_func=0x%x, op_mode=0x%x\n",
776 __func__, opcode, cmd->type, ahw->pci_func,
777 ahw->op_mode);
778 return err;
779 }
780
781 switch (cmd_type) {
782 case QLC_83XX_MBX_CMD_WAIT:
783 if (!wait_for_completion_timeout(&cmd->completion, timeout)) {
784 dev_err(&adapter->pdev->dev,
785 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
786 __func__, opcode, cmd_type, ahw->pci_func,
787 ahw->op_mode);
788 flush_workqueue(mbx->work_q);
789 }
790 break;
791 case QLC_83XX_MBX_CMD_NO_WAIT:
792 return 0;
793 case QLC_83XX_MBX_CMD_BUSY_WAIT:
794 qlcnic_83xx_poll_for_mbx_completion(adapter, cmd);
795 break;
796 default:
797 dev_err(&adapter->pdev->dev,
798 "%s: Invalid mailbox command, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
799 __func__, opcode, cmd_type, ahw->pci_func,
800 ahw->op_mode);
801 qlcnic_83xx_detach_mailbox_work(adapter);
802 }
803
804 return cmd->rsp_opcode;
805 }
806
807 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
808 struct qlcnic_adapter *adapter, u32 type)
809 {
810 int i, size;
811 u32 temp;
812 const struct qlcnic_mailbox_metadata *mbx_tbl;
813
814 memset(mbx, 0, sizeof(struct qlcnic_cmd_args));
815 mbx_tbl = qlcnic_83xx_mbx_tbl;
816 size = ARRAY_SIZE(qlcnic_83xx_mbx_tbl);
817 for (i = 0; i < size; i++) {
818 if (type == mbx_tbl[i].cmd) {
819 mbx->op_type = QLC_83XX_FW_MBX_CMD;
820 mbx->req.num = mbx_tbl[i].in_args;
821 mbx->rsp.num = mbx_tbl[i].out_args;
822 mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
823 GFP_ATOMIC);
824 if (!mbx->req.arg)
825 return -ENOMEM;
826 mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
827 GFP_ATOMIC);
828 if (!mbx->rsp.arg) {
829 kfree(mbx->req.arg);
830 mbx->req.arg = NULL;
831 return -ENOMEM;
832 }
833 memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
834 memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
835 temp = adapter->ahw->fw_hal_version << 29;
836 mbx->req.arg[0] = (type | (mbx->req.num << 16) | temp);
837 mbx->cmd_op = type;
838 return 0;
839 }
840 }
841 return -EINVAL;
842 }
843
844 void qlcnic_83xx_idc_aen_work(struct work_struct *work)
845 {
846 struct qlcnic_adapter *adapter;
847 struct qlcnic_cmd_args cmd;
848 int i, err = 0;
849
850 adapter = container_of(work, struct qlcnic_adapter, idc_aen_work.work);
851 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_IDC_ACK);
852 if (err)
853 return;
854
855 for (i = 1; i < QLC_83XX_MBX_AEN_CNT; i++)
856 cmd.req.arg[i] = adapter->ahw->mbox_aen[i];
857
858 err = qlcnic_issue_cmd(adapter, &cmd);
859 if (err)
860 dev_info(&adapter->pdev->dev,
861 "%s: Mailbox IDC ACK failed.\n", __func__);
862 qlcnic_free_mbx_args(&cmd);
863 }
864
865 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
866 u32 data[])
867 {
868 dev_dbg(&adapter->pdev->dev, "Completion AEN:0x%x.\n",
869 QLCNIC_MBX_RSP(data[0]));
870 clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status);
871 return;
872 }
873
874 void __qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
875 {
876 struct qlcnic_hardware_context *ahw = adapter->ahw;
877 u32 event[QLC_83XX_MBX_AEN_CNT];
878 int i;
879
880 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
881 event[i] = readl(QLCNIC_MBX_FW(ahw, i));
882
883 switch (QLCNIC_MBX_RSP(event[0])) {
884
885 case QLCNIC_MBX_LINK_EVENT:
886 qlcnic_83xx_handle_link_aen(adapter, event);
887 break;
888 case QLCNIC_MBX_COMP_EVENT:
889 qlcnic_83xx_handle_idc_comp_aen(adapter, event);
890 break;
891 case QLCNIC_MBX_REQUEST_EVENT:
892 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
893 adapter->ahw->mbox_aen[i] = QLCNIC_MBX_RSP(event[i]);
894 queue_delayed_work(adapter->qlcnic_wq,
895 &adapter->idc_aen_work, 0);
896 break;
897 case QLCNIC_MBX_TIME_EXTEND_EVENT:
898 ahw->extend_lb_time = event[1] >> 8 & 0xf;
899 break;
900 case QLCNIC_MBX_BC_EVENT:
901 qlcnic_sriov_handle_bc_event(adapter, event[1]);
902 break;
903 case QLCNIC_MBX_SFP_INSERT_EVENT:
904 dev_info(&adapter->pdev->dev, "SFP+ Insert AEN:0x%x.\n",
905 QLCNIC_MBX_RSP(event[0]));
906 break;
907 case QLCNIC_MBX_SFP_REMOVE_EVENT:
908 dev_info(&adapter->pdev->dev, "SFP Removed AEN:0x%x.\n",
909 QLCNIC_MBX_RSP(event[0]));
910 break;
911 case QLCNIC_MBX_DCBX_CONFIG_CHANGE_EVENT:
912 qlcnic_dcb_aen_handler(adapter->dcb, (void *)&event[1]);
913 break;
914 default:
915 dev_dbg(&adapter->pdev->dev, "Unsupported AEN:0x%x.\n",
916 QLCNIC_MBX_RSP(event[0]));
917 break;
918 }
919
920 QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
921 }
922
923 static void qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
924 {
925 u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
926 struct qlcnic_hardware_context *ahw = adapter->ahw;
927 struct qlcnic_mailbox *mbx = ahw->mailbox;
928 unsigned long flags;
929
930 spin_lock_irqsave(&mbx->aen_lock, flags);
931 resp = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL);
932 if (resp & QLCNIC_SET_OWNER) {
933 event = readl(QLCNIC_MBX_FW(ahw, 0));
934 if (event & QLCNIC_MBX_ASYNC_EVENT) {
935 __qlcnic_83xx_process_aen(adapter);
936 } else {
937 if (atomic_read(&mbx->rsp_status) != rsp_status)
938 qlcnic_83xx_notify_mbx_response(mbx);
939 }
940 }
941 spin_unlock_irqrestore(&mbx->aen_lock, flags);
942 }
943
944 static void qlcnic_83xx_mbx_poll_work(struct work_struct *work)
945 {
946 struct qlcnic_adapter *adapter;
947
948 adapter = container_of(work, struct qlcnic_adapter, mbx_poll_work.work);
949
950 if (!test_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
951 return;
952
953 qlcnic_83xx_process_aen(adapter);
954 queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work,
955 (HZ / 10));
956 }
957
958 void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *adapter)
959 {
960 if (test_and_set_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
961 return;
962
963 INIT_DELAYED_WORK(&adapter->mbx_poll_work, qlcnic_83xx_mbx_poll_work);
964 queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work, 0);
965 }
966
967 void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *adapter)
968 {
969 if (!test_and_clear_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
970 return;
971 cancel_delayed_work_sync(&adapter->mbx_poll_work);
972 }
973
974 static int qlcnic_83xx_add_rings(struct qlcnic_adapter *adapter)
975 {
976 int index, i, err, sds_mbx_size;
977 u32 *buf, intrpt_id, intr_mask;
978 u16 context_id;
979 u8 num_sds;
980 struct qlcnic_cmd_args cmd;
981 struct qlcnic_host_sds_ring *sds;
982 struct qlcnic_sds_mbx sds_mbx;
983 struct qlcnic_add_rings_mbx_out *mbx_out;
984 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
985 struct qlcnic_hardware_context *ahw = adapter->ahw;
986
987 sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
988 context_id = recv_ctx->context_id;
989 num_sds = (adapter->max_sds_rings - QLCNIC_MAX_RING_SETS);
990 ahw->hw_ops->alloc_mbx_args(&cmd, adapter,
991 QLCNIC_CMD_ADD_RCV_RINGS);
992 cmd.req.arg[1] = 0 | (num_sds << 8) | (context_id << 16);
993
994 /* set up status rings, mbx 2-81 */
995 index = 2;
996 for (i = 8; i < adapter->max_sds_rings; i++) {
997 memset(&sds_mbx, 0, sds_mbx_size);
998 sds = &recv_ctx->sds_rings[i];
999 sds->consumer = 0;
1000 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1001 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1002 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1003 sds_mbx.sds_ring_size = sds->num_desc;
1004
1005 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1006 intrpt_id = ahw->intr_tbl[i].id;
1007 else
1008 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1009
1010 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1011 sds_mbx.intrpt_id = intrpt_id;
1012 else
1013 sds_mbx.intrpt_id = 0xffff;
1014 sds_mbx.intrpt_val = 0;
1015 buf = &cmd.req.arg[index];
1016 memcpy(buf, &sds_mbx, sds_mbx_size);
1017 index += sds_mbx_size / sizeof(u32);
1018 }
1019
1020 /* send the mailbox command */
1021 err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1022 if (err) {
1023 dev_err(&adapter->pdev->dev,
1024 "Failed to add rings %d\n", err);
1025 goto out;
1026 }
1027
1028 mbx_out = (struct qlcnic_add_rings_mbx_out *)&cmd.rsp.arg[1];
1029 index = 0;
1030 /* status descriptor ring */
1031 for (i = 8; i < adapter->max_sds_rings; i++) {
1032 sds = &recv_ctx->sds_rings[i];
1033 sds->crb_sts_consumer = ahw->pci_base0 +
1034 mbx_out->host_csmr[index];
1035 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1036 intr_mask = ahw->intr_tbl[i].src;
1037 else
1038 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1039
1040 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1041 index++;
1042 }
1043 out:
1044 qlcnic_free_mbx_args(&cmd);
1045 return err;
1046 }
1047
1048 void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *adapter)
1049 {
1050 int err;
1051 u32 temp = 0;
1052 struct qlcnic_cmd_args cmd;
1053 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1054
1055 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX))
1056 return;
1057
1058 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1059 cmd.req.arg[0] |= (0x3 << 29);
1060
1061 if (qlcnic_sriov_pf_check(adapter))
1062 qlcnic_pf_set_interface_id_del_rx_ctx(adapter, &temp);
1063
1064 cmd.req.arg[1] = recv_ctx->context_id | temp;
1065 err = qlcnic_issue_cmd(adapter, &cmd);
1066 if (err)
1067 dev_err(&adapter->pdev->dev,
1068 "Failed to destroy rx ctx in firmware\n");
1069
1070 recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
1071 qlcnic_free_mbx_args(&cmd);
1072 }
1073
1074 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter)
1075 {
1076 int i, err, index, sds_mbx_size, rds_mbx_size;
1077 u8 num_sds, num_rds;
1078 u32 *buf, intrpt_id, intr_mask, cap = 0;
1079 struct qlcnic_host_sds_ring *sds;
1080 struct qlcnic_host_rds_ring *rds;
1081 struct qlcnic_sds_mbx sds_mbx;
1082 struct qlcnic_rds_mbx rds_mbx;
1083 struct qlcnic_cmd_args cmd;
1084 struct qlcnic_rcv_mbx_out *mbx_out;
1085 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1086 struct qlcnic_hardware_context *ahw = adapter->ahw;
1087 num_rds = adapter->max_rds_rings;
1088
1089 if (adapter->max_sds_rings <= QLCNIC_MAX_RING_SETS)
1090 num_sds = adapter->max_sds_rings;
1091 else
1092 num_sds = QLCNIC_MAX_RING_SETS;
1093
1094 sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1095 rds_mbx_size = sizeof(struct qlcnic_rds_mbx);
1096 cap = QLCNIC_CAP0_LEGACY_CONTEXT;
1097
1098 if (adapter->flags & QLCNIC_FW_LRO_MSS_CAP)
1099 cap |= QLC_83XX_FW_CAP_LRO_MSS;
1100
1101 /* set mailbox hdr and capabilities */
1102 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1103 QLCNIC_CMD_CREATE_RX_CTX);
1104 if (err)
1105 return err;
1106
1107 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1108 cmd.req.arg[0] |= (0x3 << 29);
1109
1110 cmd.req.arg[1] = cap;
1111 cmd.req.arg[5] = 1 | (num_rds << 5) | (num_sds << 8) |
1112 (QLC_83XX_HOST_RDS_MODE_UNIQUE << 16);
1113
1114 if (qlcnic_sriov_pf_check(adapter))
1115 qlcnic_pf_set_interface_id_create_rx_ctx(adapter,
1116 &cmd.req.arg[6]);
1117 /* set up status rings, mbx 8-57/87 */
1118 index = QLC_83XX_HOST_SDS_MBX_IDX;
1119 for (i = 0; i < num_sds; i++) {
1120 memset(&sds_mbx, 0, sds_mbx_size);
1121 sds = &recv_ctx->sds_rings[i];
1122 sds->consumer = 0;
1123 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1124 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1125 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1126 sds_mbx.sds_ring_size = sds->num_desc;
1127 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1128 intrpt_id = ahw->intr_tbl[i].id;
1129 else
1130 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1131 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1132 sds_mbx.intrpt_id = intrpt_id;
1133 else
1134 sds_mbx.intrpt_id = 0xffff;
1135 sds_mbx.intrpt_val = 0;
1136 buf = &cmd.req.arg[index];
1137 memcpy(buf, &sds_mbx, sds_mbx_size);
1138 index += sds_mbx_size / sizeof(u32);
1139 }
1140 /* set up receive rings, mbx 88-111/135 */
1141 index = QLCNIC_HOST_RDS_MBX_IDX;
1142 rds = &recv_ctx->rds_rings[0];
1143 rds->producer = 0;
1144 memset(&rds_mbx, 0, rds_mbx_size);
1145 rds_mbx.phy_addr_reg_low = LSD(rds->phys_addr);
1146 rds_mbx.phy_addr_reg_high = MSD(rds->phys_addr);
1147 rds_mbx.reg_ring_sz = rds->dma_size;
1148 rds_mbx.reg_ring_len = rds->num_desc;
1149 /* Jumbo ring */
1150 rds = &recv_ctx->rds_rings[1];
1151 rds->producer = 0;
1152 rds_mbx.phy_addr_jmb_low = LSD(rds->phys_addr);
1153 rds_mbx.phy_addr_jmb_high = MSD(rds->phys_addr);
1154 rds_mbx.jmb_ring_sz = rds->dma_size;
1155 rds_mbx.jmb_ring_len = rds->num_desc;
1156 buf = &cmd.req.arg[index];
1157 memcpy(buf, &rds_mbx, rds_mbx_size);
1158
1159 /* send the mailbox command */
1160 err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1161 if (err) {
1162 dev_err(&adapter->pdev->dev,
1163 "Failed to create Rx ctx in firmware%d\n", err);
1164 goto out;
1165 }
1166 mbx_out = (struct qlcnic_rcv_mbx_out *)&cmd.rsp.arg[1];
1167 recv_ctx->context_id = mbx_out->ctx_id;
1168 recv_ctx->state = mbx_out->state;
1169 recv_ctx->virt_port = mbx_out->vport_id;
1170 dev_info(&adapter->pdev->dev, "Rx Context[%d] Created, state:0x%x\n",
1171 recv_ctx->context_id, recv_ctx->state);
1172 /* Receive descriptor ring */
1173 /* Standard ring */
1174 rds = &recv_ctx->rds_rings[0];
1175 rds->crb_rcv_producer = ahw->pci_base0 +
1176 mbx_out->host_prod[0].reg_buf;
1177 /* Jumbo ring */
1178 rds = &recv_ctx->rds_rings[1];
1179 rds->crb_rcv_producer = ahw->pci_base0 +
1180 mbx_out->host_prod[0].jmb_buf;
1181 /* status descriptor ring */
1182 for (i = 0; i < num_sds; i++) {
1183 sds = &recv_ctx->sds_rings[i];
1184 sds->crb_sts_consumer = ahw->pci_base0 +
1185 mbx_out->host_csmr[i];
1186 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1187 intr_mask = ahw->intr_tbl[i].src;
1188 else
1189 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1190 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1191 }
1192
1193 if (adapter->max_sds_rings > QLCNIC_MAX_RING_SETS)
1194 err = qlcnic_83xx_add_rings(adapter);
1195 out:
1196 qlcnic_free_mbx_args(&cmd);
1197 return err;
1198 }
1199
1200 void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *adapter,
1201 struct qlcnic_host_tx_ring *tx_ring)
1202 {
1203 struct qlcnic_cmd_args cmd;
1204 u32 temp = 0;
1205
1206 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX))
1207 return;
1208
1209 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1210 cmd.req.arg[0] |= (0x3 << 29);
1211
1212 if (qlcnic_sriov_pf_check(adapter))
1213 qlcnic_pf_set_interface_id_del_tx_ctx(adapter, &temp);
1214
1215 cmd.req.arg[1] = tx_ring->ctx_id | temp;
1216 if (qlcnic_issue_cmd(adapter, &cmd))
1217 dev_err(&adapter->pdev->dev,
1218 "Failed to destroy tx ctx in firmware\n");
1219 qlcnic_free_mbx_args(&cmd);
1220 }
1221
1222 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *adapter,
1223 struct qlcnic_host_tx_ring *tx, int ring)
1224 {
1225 int err;
1226 u16 msix_id;
1227 u32 *buf, intr_mask, temp = 0;
1228 struct qlcnic_cmd_args cmd;
1229 struct qlcnic_tx_mbx mbx;
1230 struct qlcnic_tx_mbx_out *mbx_out;
1231 struct qlcnic_hardware_context *ahw = adapter->ahw;
1232 u32 msix_vector;
1233
1234 /* Reset host resources */
1235 tx->producer = 0;
1236 tx->sw_consumer = 0;
1237 *(tx->hw_consumer) = 0;
1238
1239 memset(&mbx, 0, sizeof(struct qlcnic_tx_mbx));
1240
1241 /* setup mailbox inbox registerss */
1242 mbx.phys_addr_low = LSD(tx->phys_addr);
1243 mbx.phys_addr_high = MSD(tx->phys_addr);
1244 mbx.cnsmr_index_low = LSD(tx->hw_cons_phys_addr);
1245 mbx.cnsmr_index_high = MSD(tx->hw_cons_phys_addr);
1246 mbx.size = tx->num_desc;
1247 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
1248 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
1249 msix_vector = adapter->max_sds_rings + ring;
1250 else
1251 msix_vector = adapter->max_sds_rings - 1;
1252 msix_id = ahw->intr_tbl[msix_vector].id;
1253 } else {
1254 msix_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1255 }
1256
1257 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1258 mbx.intr_id = msix_id;
1259 else
1260 mbx.intr_id = 0xffff;
1261 mbx.src = 0;
1262
1263 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
1264 if (err)
1265 return err;
1266
1267 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1268 cmd.req.arg[0] |= (0x3 << 29);
1269
1270 if (qlcnic_sriov_pf_check(adapter))
1271 qlcnic_pf_set_interface_id_create_tx_ctx(adapter, &temp);
1272
1273 cmd.req.arg[1] = QLCNIC_CAP0_LEGACY_CONTEXT;
1274 cmd.req.arg[5] = QLCNIC_MAX_TX_QUEUES | temp;
1275 buf = &cmd.req.arg[6];
1276 memcpy(buf, &mbx, sizeof(struct qlcnic_tx_mbx));
1277 /* send the mailbox command*/
1278 err = qlcnic_issue_cmd(adapter, &cmd);
1279 if (err) {
1280 dev_err(&adapter->pdev->dev,
1281 "Failed to create Tx ctx in firmware 0x%x\n", err);
1282 goto out;
1283 }
1284 mbx_out = (struct qlcnic_tx_mbx_out *)&cmd.rsp.arg[2];
1285 tx->crb_cmd_producer = ahw->pci_base0 + mbx_out->host_prod;
1286 tx->ctx_id = mbx_out->ctx_id;
1287 if ((adapter->flags & QLCNIC_MSIX_ENABLED) &&
1288 !(adapter->flags & QLCNIC_TX_INTR_SHARED)) {
1289 intr_mask = ahw->intr_tbl[adapter->max_sds_rings + ring].src;
1290 tx->crb_intr_mask = ahw->pci_base0 + intr_mask;
1291 }
1292 dev_info(&adapter->pdev->dev, "Tx Context[0x%x] Created, state:0x%x\n",
1293 tx->ctx_id, mbx_out->state);
1294 out:
1295 qlcnic_free_mbx_args(&cmd);
1296 return err;
1297 }
1298
1299 static int qlcnic_83xx_diag_alloc_res(struct net_device *netdev, int test,
1300 int num_sds_ring)
1301 {
1302 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1303 struct qlcnic_host_sds_ring *sds_ring;
1304 struct qlcnic_host_rds_ring *rds_ring;
1305 u16 adapter_state = adapter->is_up;
1306 u8 ring;
1307 int ret;
1308
1309 netif_device_detach(netdev);
1310
1311 if (netif_running(netdev))
1312 __qlcnic_down(adapter, netdev);
1313
1314 qlcnic_detach(adapter);
1315
1316 adapter->max_sds_rings = 1;
1317 adapter->ahw->diag_test = test;
1318 adapter->ahw->linkup = 0;
1319
1320 ret = qlcnic_attach(adapter);
1321 if (ret) {
1322 netif_device_attach(netdev);
1323 return ret;
1324 }
1325
1326 ret = qlcnic_fw_create_ctx(adapter);
1327 if (ret) {
1328 qlcnic_detach(adapter);
1329 if (adapter_state == QLCNIC_ADAPTER_UP_MAGIC) {
1330 adapter->max_sds_rings = num_sds_ring;
1331 qlcnic_attach(adapter);
1332 }
1333 netif_device_attach(netdev);
1334 return ret;
1335 }
1336
1337 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1338 rds_ring = &adapter->recv_ctx->rds_rings[ring];
1339 qlcnic_post_rx_buffers(adapter, rds_ring, ring);
1340 }
1341
1342 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1343 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
1344 sds_ring = &adapter->recv_ctx->sds_rings[ring];
1345 qlcnic_83xx_enable_intr(adapter, sds_ring);
1346 }
1347 }
1348
1349 if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1350 /* disable and free mailbox interrupt */
1351 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
1352 qlcnic_83xx_enable_mbx_poll(adapter);
1353 qlcnic_83xx_free_mbx_intr(adapter);
1354 }
1355 adapter->ahw->loopback_state = 0;
1356 adapter->ahw->hw_ops->setup_link_event(adapter, 1);
1357 }
1358
1359 set_bit(__QLCNIC_DEV_UP, &adapter->state);
1360 return 0;
1361 }
1362
1363 static void qlcnic_83xx_diag_free_res(struct net_device *netdev,
1364 int max_sds_rings)
1365 {
1366 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1367 struct qlcnic_host_sds_ring *sds_ring;
1368 int ring, err;
1369
1370 clear_bit(__QLCNIC_DEV_UP, &adapter->state);
1371 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1372 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
1373 sds_ring = &adapter->recv_ctx->sds_rings[ring];
1374 qlcnic_83xx_disable_intr(adapter, sds_ring);
1375 if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
1376 qlcnic_83xx_enable_mbx_poll(adapter);
1377 }
1378 }
1379
1380 qlcnic_fw_destroy_ctx(adapter);
1381 qlcnic_detach(adapter);
1382
1383 if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1384 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
1385 err = qlcnic_83xx_setup_mbx_intr(adapter);
1386 qlcnic_83xx_disable_mbx_poll(adapter);
1387 if (err) {
1388 dev_err(&adapter->pdev->dev,
1389 "%s: failed to setup mbx interrupt\n",
1390 __func__);
1391 goto out;
1392 }
1393 }
1394 }
1395 adapter->ahw->diag_test = 0;
1396 adapter->max_sds_rings = max_sds_rings;
1397
1398 if (qlcnic_attach(adapter))
1399 goto out;
1400
1401 if (netif_running(netdev))
1402 __qlcnic_up(adapter, netdev);
1403
1404 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST &&
1405 !(adapter->flags & QLCNIC_MSIX_ENABLED))
1406 qlcnic_83xx_disable_mbx_poll(adapter);
1407 out:
1408 netif_device_attach(netdev);
1409 }
1410
1411 int qlcnic_83xx_config_led(struct qlcnic_adapter *adapter, u32 state,
1412 u32 beacon)
1413 {
1414 struct qlcnic_cmd_args cmd;
1415 u32 mbx_in;
1416 int i, status = 0;
1417
1418 if (state) {
1419 /* Get LED configuration */
1420 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1421 QLCNIC_CMD_GET_LED_CONFIG);
1422 if (status)
1423 return status;
1424
1425 status = qlcnic_issue_cmd(adapter, &cmd);
1426 if (status) {
1427 dev_err(&adapter->pdev->dev,
1428 "Get led config failed.\n");
1429 goto mbx_err;
1430 } else {
1431 for (i = 0; i < 4; i++)
1432 adapter->ahw->mbox_reg[i] = cmd.rsp.arg[i+1];
1433 }
1434 qlcnic_free_mbx_args(&cmd);
1435 /* Set LED Configuration */
1436 mbx_in = (LSW(QLC_83XX_LED_CONFIG) << 16) |
1437 LSW(QLC_83XX_LED_CONFIG);
1438 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1439 QLCNIC_CMD_SET_LED_CONFIG);
1440 if (status)
1441 return status;
1442
1443 cmd.req.arg[1] = mbx_in;
1444 cmd.req.arg[2] = mbx_in;
1445 cmd.req.arg[3] = mbx_in;
1446 if (beacon)
1447 cmd.req.arg[4] = QLC_83XX_ENABLE_BEACON;
1448 status = qlcnic_issue_cmd(adapter, &cmd);
1449 if (status) {
1450 dev_err(&adapter->pdev->dev,
1451 "Set led config failed.\n");
1452 }
1453 mbx_err:
1454 qlcnic_free_mbx_args(&cmd);
1455 return status;
1456
1457 } else {
1458 /* Restoring default LED configuration */
1459 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1460 QLCNIC_CMD_SET_LED_CONFIG);
1461 if (status)
1462 return status;
1463
1464 cmd.req.arg[1] = adapter->ahw->mbox_reg[0];
1465 cmd.req.arg[2] = adapter->ahw->mbox_reg[1];
1466 cmd.req.arg[3] = adapter->ahw->mbox_reg[2];
1467 if (beacon)
1468 cmd.req.arg[4] = adapter->ahw->mbox_reg[3];
1469 status = qlcnic_issue_cmd(adapter, &cmd);
1470 if (status)
1471 dev_err(&adapter->pdev->dev,
1472 "Restoring led config failed.\n");
1473 qlcnic_free_mbx_args(&cmd);
1474 return status;
1475 }
1476 }
1477
1478 int qlcnic_83xx_set_led(struct net_device *netdev,
1479 enum ethtool_phys_id_state state)
1480 {
1481 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1482 int err = -EIO, active = 1;
1483
1484 if (adapter->ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1485 netdev_warn(netdev,
1486 "LED test is not supported in non-privileged mode\n");
1487 return -EOPNOTSUPP;
1488 }
1489
1490 switch (state) {
1491 case ETHTOOL_ID_ACTIVE:
1492 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state))
1493 return -EBUSY;
1494
1495 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1496 break;
1497
1498 err = qlcnic_83xx_config_led(adapter, active, 0);
1499 if (err)
1500 netdev_err(netdev, "Failed to set LED blink state\n");
1501 break;
1502 case ETHTOOL_ID_INACTIVE:
1503 active = 0;
1504
1505 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1506 break;
1507
1508 err = qlcnic_83xx_config_led(adapter, active, 0);
1509 if (err)
1510 netdev_err(netdev, "Failed to reset LED blink state\n");
1511 break;
1512
1513 default:
1514 return -EINVAL;
1515 }
1516
1517 if (!active || err)
1518 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state);
1519
1520 return err;
1521 }
1522
1523 void qlcnic_83xx_register_nic_idc_func(struct qlcnic_adapter *adapter,
1524 int enable)
1525 {
1526 struct qlcnic_cmd_args cmd;
1527 int status;
1528
1529 if (qlcnic_sriov_vf_check(adapter))
1530 return;
1531
1532 if (enable) {
1533 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1534 QLCNIC_CMD_INIT_NIC_FUNC);
1535 if (status)
1536 return;
1537
1538 cmd.req.arg[1] = BIT_0 | BIT_31;
1539 } else {
1540 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1541 QLCNIC_CMD_STOP_NIC_FUNC);
1542 if (status)
1543 return;
1544
1545 cmd.req.arg[1] = BIT_0 | BIT_31;
1546 }
1547 status = qlcnic_issue_cmd(adapter, &cmd);
1548 if (status)
1549 dev_err(&adapter->pdev->dev,
1550 "Failed to %s in NIC IDC function event.\n",
1551 (enable ? "register" : "unregister"));
1552
1553 qlcnic_free_mbx_args(&cmd);
1554 }
1555
1556 int qlcnic_83xx_set_port_config(struct qlcnic_adapter *adapter)
1557 {
1558 struct qlcnic_cmd_args cmd;
1559 int err;
1560
1561 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_PORT_CONFIG);
1562 if (err)
1563 return err;
1564
1565 cmd.req.arg[1] = adapter->ahw->port_config;
1566 err = qlcnic_issue_cmd(adapter, &cmd);
1567 if (err)
1568 dev_info(&adapter->pdev->dev, "Set Port Config failed.\n");
1569 qlcnic_free_mbx_args(&cmd);
1570 return err;
1571 }
1572
1573 int qlcnic_83xx_get_port_config(struct qlcnic_adapter *adapter)
1574 {
1575 struct qlcnic_cmd_args cmd;
1576 int err;
1577
1578 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PORT_CONFIG);
1579 if (err)
1580 return err;
1581
1582 err = qlcnic_issue_cmd(adapter, &cmd);
1583 if (err)
1584 dev_info(&adapter->pdev->dev, "Get Port config failed\n");
1585 else
1586 adapter->ahw->port_config = cmd.rsp.arg[1];
1587 qlcnic_free_mbx_args(&cmd);
1588 return err;
1589 }
1590
1591 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *adapter, int enable)
1592 {
1593 int err;
1594 u32 temp;
1595 struct qlcnic_cmd_args cmd;
1596
1597 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_EVENT);
1598 if (err)
1599 return err;
1600
1601 temp = adapter->recv_ctx->context_id << 16;
1602 cmd.req.arg[1] = (enable ? 1 : 0) | BIT_8 | temp;
1603 err = qlcnic_issue_cmd(adapter, &cmd);
1604 if (err)
1605 dev_info(&adapter->pdev->dev,
1606 "Setup linkevent mailbox failed\n");
1607 qlcnic_free_mbx_args(&cmd);
1608 return err;
1609 }
1610
1611 static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter *adapter,
1612 u32 *interface_id)
1613 {
1614 if (qlcnic_sriov_pf_check(adapter)) {
1615 qlcnic_pf_set_interface_id_promisc(adapter, interface_id);
1616 } else {
1617 if (!qlcnic_sriov_vf_check(adapter))
1618 *interface_id = adapter->recv_ctx->context_id << 16;
1619 }
1620 }
1621
1622 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
1623 {
1624 struct qlcnic_cmd_args *cmd = NULL;
1625 u32 temp = 0;
1626 int err;
1627
1628 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1629 return -EIO;
1630
1631 cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
1632 if (!cmd)
1633 return -ENOMEM;
1634
1635 err = qlcnic_alloc_mbx_args(cmd, adapter,
1636 QLCNIC_CMD_CONFIGURE_MAC_RX_MODE);
1637 if (err)
1638 goto out;
1639
1640 cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
1641 qlcnic_83xx_set_interface_id_promisc(adapter, &temp);
1642 cmd->req.arg[1] = (mode ? 1 : 0) | temp;
1643 err = qlcnic_issue_cmd(adapter, cmd);
1644 if (!err)
1645 return err;
1646
1647 qlcnic_free_mbx_args(cmd);
1648
1649 out:
1650 kfree(cmd);
1651 return err;
1652 }
1653
1654 int qlcnic_83xx_loopback_test(struct net_device *netdev, u8 mode)
1655 {
1656 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1657 struct qlcnic_hardware_context *ahw = adapter->ahw;
1658 int ret = 0, loop = 0, max_sds_rings = adapter->max_sds_rings;
1659
1660 if (ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1661 netdev_warn(netdev,
1662 "Loopback test not supported in non privileged mode\n");
1663 return -ENOTSUPP;
1664 }
1665
1666 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1667 netdev_info(netdev, "Device is resetting\n");
1668 return -EBUSY;
1669 }
1670
1671 if (qlcnic_get_diag_lock(adapter)) {
1672 netdev_info(netdev, "Device is in diagnostics mode\n");
1673 return -EBUSY;
1674 }
1675
1676 netdev_info(netdev, "%s loopback test in progress\n",
1677 mode == QLCNIC_ILB_MODE ? "internal" : "external");
1678
1679 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST,
1680 max_sds_rings);
1681 if (ret)
1682 goto fail_diag_alloc;
1683
1684 ret = qlcnic_83xx_set_lb_mode(adapter, mode);
1685 if (ret)
1686 goto free_diag_res;
1687
1688 /* Poll for link up event before running traffic */
1689 do {
1690 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1691
1692 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1693 netdev_info(netdev,
1694 "Device is resetting, free LB test resources\n");
1695 ret = -EBUSY;
1696 goto free_diag_res;
1697 }
1698 if (loop++ > QLC_83XX_LB_WAIT_COUNT) {
1699 netdev_info(netdev,
1700 "Firmware didn't sent link up event to loopback request\n");
1701 ret = -ETIMEDOUT;
1702 qlcnic_83xx_clear_lb_mode(adapter, mode);
1703 goto free_diag_res;
1704 }
1705 } while ((adapter->ahw->linkup && ahw->has_link_events) != 1);
1706
1707 /* Make sure carrier is off and queue is stopped during loopback */
1708 if (netif_running(netdev)) {
1709 netif_carrier_off(netdev);
1710 netif_tx_stop_all_queues(netdev);
1711 }
1712
1713 ret = qlcnic_do_lb_test(adapter, mode);
1714
1715 qlcnic_83xx_clear_lb_mode(adapter, mode);
1716
1717 free_diag_res:
1718 qlcnic_83xx_diag_free_res(netdev, max_sds_rings);
1719
1720 fail_diag_alloc:
1721 adapter->max_sds_rings = max_sds_rings;
1722 qlcnic_release_diag_lock(adapter);
1723 return ret;
1724 }
1725
1726 static void qlcnic_extend_lb_idc_cmpltn_wait(struct qlcnic_adapter *adapter,
1727 u32 *max_wait_count)
1728 {
1729 struct qlcnic_hardware_context *ahw = adapter->ahw;
1730 int temp;
1731
1732 netdev_info(adapter->netdev, "Recieved loopback IDC time extend event for 0x%x seconds\n",
1733 ahw->extend_lb_time);
1734 temp = ahw->extend_lb_time * 1000;
1735 *max_wait_count += temp / QLC_83XX_LB_MSLEEP_COUNT;
1736 ahw->extend_lb_time = 0;
1737 }
1738
1739 int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1740 {
1741 struct qlcnic_hardware_context *ahw = adapter->ahw;
1742 struct net_device *netdev = adapter->netdev;
1743 u32 config, max_wait_count;
1744 int status = 0, loop = 0;
1745
1746 ahw->extend_lb_time = 0;
1747 max_wait_count = QLC_83XX_LB_WAIT_COUNT;
1748 status = qlcnic_83xx_get_port_config(adapter);
1749 if (status)
1750 return status;
1751
1752 config = ahw->port_config;
1753
1754 /* Check if port is already in loopback mode */
1755 if ((config & QLC_83XX_CFG_LOOPBACK_HSS) ||
1756 (config & QLC_83XX_CFG_LOOPBACK_EXT)) {
1757 netdev_err(netdev,
1758 "Port already in Loopback mode.\n");
1759 return -EINPROGRESS;
1760 }
1761
1762 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1763
1764 if (mode == QLCNIC_ILB_MODE)
1765 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_HSS;
1766 if (mode == QLCNIC_ELB_MODE)
1767 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_EXT;
1768
1769 status = qlcnic_83xx_set_port_config(adapter);
1770 if (status) {
1771 netdev_err(netdev,
1772 "Failed to Set Loopback Mode = 0x%x.\n",
1773 ahw->port_config);
1774 ahw->port_config = config;
1775 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1776 return status;
1777 }
1778
1779 /* Wait for Link and IDC Completion AEN */
1780 do {
1781 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1782
1783 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1784 netdev_info(netdev,
1785 "Device is resetting, free LB test resources\n");
1786 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1787 return -EBUSY;
1788 }
1789
1790 if (ahw->extend_lb_time)
1791 qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1792 &max_wait_count);
1793
1794 if (loop++ > max_wait_count) {
1795 netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1796 __func__);
1797 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1798 qlcnic_83xx_clear_lb_mode(adapter, mode);
1799 return -ETIMEDOUT;
1800 }
1801 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1802
1803 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1804 QLCNIC_MAC_ADD);
1805 return status;
1806 }
1807
1808 int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1809 {
1810 struct qlcnic_hardware_context *ahw = adapter->ahw;
1811 u32 config = ahw->port_config, max_wait_count;
1812 struct net_device *netdev = adapter->netdev;
1813 int status = 0, loop = 0;
1814
1815 ahw->extend_lb_time = 0;
1816 max_wait_count = QLC_83XX_LB_WAIT_COUNT;
1817 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1818 if (mode == QLCNIC_ILB_MODE)
1819 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_HSS;
1820 if (mode == QLCNIC_ELB_MODE)
1821 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_EXT;
1822
1823 status = qlcnic_83xx_set_port_config(adapter);
1824 if (status) {
1825 netdev_err(netdev,
1826 "Failed to Clear Loopback Mode = 0x%x.\n",
1827 ahw->port_config);
1828 ahw->port_config = config;
1829 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1830 return status;
1831 }
1832
1833 /* Wait for Link and IDC Completion AEN */
1834 do {
1835 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1836
1837 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1838 netdev_info(netdev,
1839 "Device is resetting, free LB test resources\n");
1840 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1841 return -EBUSY;
1842 }
1843
1844 if (ahw->extend_lb_time)
1845 qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1846 &max_wait_count);
1847
1848 if (loop++ > max_wait_count) {
1849 netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1850 __func__);
1851 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1852 return -ETIMEDOUT;
1853 }
1854 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1855
1856 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1857 QLCNIC_MAC_DEL);
1858 return status;
1859 }
1860
1861 static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter *adapter,
1862 u32 *interface_id)
1863 {
1864 if (qlcnic_sriov_pf_check(adapter)) {
1865 qlcnic_pf_set_interface_id_ipaddr(adapter, interface_id);
1866 } else {
1867 if (!qlcnic_sriov_vf_check(adapter))
1868 *interface_id = adapter->recv_ctx->context_id << 16;
1869 }
1870 }
1871
1872 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip,
1873 int mode)
1874 {
1875 int err;
1876 u32 temp = 0, temp_ip;
1877 struct qlcnic_cmd_args cmd;
1878
1879 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1880 QLCNIC_CMD_CONFIGURE_IP_ADDR);
1881 if (err)
1882 return;
1883
1884 qlcnic_83xx_set_interface_id_ipaddr(adapter, &temp);
1885
1886 if (mode == QLCNIC_IP_UP)
1887 cmd.req.arg[1] = 1 | temp;
1888 else
1889 cmd.req.arg[1] = 2 | temp;
1890
1891 /*
1892 * Adapter needs IP address in network byte order.
1893 * But hardware mailbox registers go through writel(), hence IP address
1894 * gets swapped on big endian architecture.
1895 * To negate swapping of writel() on big endian architecture
1896 * use swab32(value).
1897 */
1898
1899 temp_ip = swab32(ntohl(ip));
1900 memcpy(&cmd.req.arg[2], &temp_ip, sizeof(u32));
1901 err = qlcnic_issue_cmd(adapter, &cmd);
1902 if (err != QLCNIC_RCODE_SUCCESS)
1903 dev_err(&adapter->netdev->dev,
1904 "could not notify %s IP 0x%x request\n",
1905 (mode == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
1906
1907 qlcnic_free_mbx_args(&cmd);
1908 }
1909
1910 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *adapter, int mode)
1911 {
1912 int err;
1913 u32 temp, arg1;
1914 struct qlcnic_cmd_args cmd;
1915 int lro_bit_mask;
1916
1917 lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0);
1918
1919 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1920 return 0;
1921
1922 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_HW_LRO);
1923 if (err)
1924 return err;
1925
1926 temp = adapter->recv_ctx->context_id << 16;
1927 arg1 = lro_bit_mask | temp;
1928 cmd.req.arg[1] = arg1;
1929
1930 err = qlcnic_issue_cmd(adapter, &cmd);
1931 if (err)
1932 dev_info(&adapter->pdev->dev, "LRO config failed\n");
1933 qlcnic_free_mbx_args(&cmd);
1934
1935 return err;
1936 }
1937
1938 int qlcnic_83xx_config_rss(struct qlcnic_adapter *adapter, int enable)
1939 {
1940 int err;
1941 u32 word;
1942 struct qlcnic_cmd_args cmd;
1943 const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
1944 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
1945 0x255b0ec26d5a56daULL };
1946
1947 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_RSS);
1948 if (err)
1949 return err;
1950 /*
1951 * RSS request:
1952 * bits 3-0: Rsvd
1953 * 5-4: hash_type_ipv4
1954 * 7-6: hash_type_ipv6
1955 * 8: enable
1956 * 9: use indirection table
1957 * 16-31: indirection table mask
1958 */
1959 word = ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
1960 ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
1961 ((u32)(enable & 0x1) << 8) |
1962 ((0x7ULL) << 16);
1963 cmd.req.arg[1] = (adapter->recv_ctx->context_id);
1964 cmd.req.arg[2] = word;
1965 memcpy(&cmd.req.arg[4], key, sizeof(key));
1966
1967 err = qlcnic_issue_cmd(adapter, &cmd);
1968
1969 if (err)
1970 dev_info(&adapter->pdev->dev, "RSS config failed\n");
1971 qlcnic_free_mbx_args(&cmd);
1972
1973 return err;
1974
1975 }
1976
1977 static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter *adapter,
1978 u32 *interface_id)
1979 {
1980 if (qlcnic_sriov_pf_check(adapter)) {
1981 qlcnic_pf_set_interface_id_macaddr(adapter, interface_id);
1982 } else {
1983 if (!qlcnic_sriov_vf_check(adapter))
1984 *interface_id = adapter->recv_ctx->context_id << 16;
1985 }
1986 }
1987
1988 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
1989 u16 vlan_id, u8 op)
1990 {
1991 struct qlcnic_cmd_args *cmd = NULL;
1992 struct qlcnic_macvlan_mbx mv;
1993 u32 *buf, temp = 0;
1994 int err;
1995
1996 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1997 return -EIO;
1998
1999 cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
2000 if (!cmd)
2001 return -ENOMEM;
2002
2003 err = qlcnic_alloc_mbx_args(cmd, adapter, QLCNIC_CMD_CONFIG_MAC_VLAN);
2004 if (err)
2005 goto out;
2006
2007 cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
2008
2009 if (vlan_id)
2010 op = (op == QLCNIC_MAC_ADD || op == QLCNIC_MAC_VLAN_ADD) ?
2011 QLCNIC_MAC_VLAN_ADD : QLCNIC_MAC_VLAN_DEL;
2012
2013 cmd->req.arg[1] = op | (1 << 8);
2014 qlcnic_83xx_set_interface_id_macaddr(adapter, &temp);
2015 cmd->req.arg[1] |= temp;
2016 mv.vlan = vlan_id;
2017 mv.mac_addr0 = addr[0];
2018 mv.mac_addr1 = addr[1];
2019 mv.mac_addr2 = addr[2];
2020 mv.mac_addr3 = addr[3];
2021 mv.mac_addr4 = addr[4];
2022 mv.mac_addr5 = addr[5];
2023 buf = &cmd->req.arg[2];
2024 memcpy(buf, &mv, sizeof(struct qlcnic_macvlan_mbx));
2025 err = qlcnic_issue_cmd(adapter, cmd);
2026 if (!err)
2027 return err;
2028
2029 qlcnic_free_mbx_args(cmd);
2030 out:
2031 kfree(cmd);
2032 return err;
2033 }
2034
2035 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr,
2036 u16 vlan_id)
2037 {
2038 u8 mac[ETH_ALEN];
2039 memcpy(&mac, addr, ETH_ALEN);
2040 qlcnic_83xx_sre_macaddr_change(adapter, mac, vlan_id, QLCNIC_MAC_ADD);
2041 }
2042
2043 void qlcnic_83xx_configure_mac(struct qlcnic_adapter *adapter, u8 *mac,
2044 u8 type, struct qlcnic_cmd_args *cmd)
2045 {
2046 switch (type) {
2047 case QLCNIC_SET_STATION_MAC:
2048 case QLCNIC_SET_FAC_DEF_MAC:
2049 memcpy(&cmd->req.arg[2], mac, sizeof(u32));
2050 memcpy(&cmd->req.arg[3], &mac[4], sizeof(u16));
2051 break;
2052 }
2053 cmd->req.arg[1] = type;
2054 }
2055
2056 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac,
2057 u8 function)
2058 {
2059 int err, i;
2060 struct qlcnic_cmd_args cmd;
2061 u32 mac_low, mac_high;
2062
2063 function = 0;
2064 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
2065 if (err)
2066 return err;
2067
2068 qlcnic_83xx_configure_mac(adapter, mac, QLCNIC_GET_CURRENT_MAC, &cmd);
2069 err = qlcnic_issue_cmd(adapter, &cmd);
2070
2071 if (err == QLCNIC_RCODE_SUCCESS) {
2072 mac_low = cmd.rsp.arg[1];
2073 mac_high = cmd.rsp.arg[2];
2074
2075 for (i = 0; i < 2; i++)
2076 mac[i] = (u8) (mac_high >> ((1 - i) * 8));
2077 for (i = 2; i < 6; i++)
2078 mac[i] = (u8) (mac_low >> ((5 - i) * 8));
2079 } else {
2080 dev_err(&adapter->pdev->dev, "Failed to get mac address%d\n",
2081 err);
2082 err = -EIO;
2083 }
2084 qlcnic_free_mbx_args(&cmd);
2085 return err;
2086 }
2087
2088 void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *adapter)
2089 {
2090 int err;
2091 u16 temp;
2092 struct qlcnic_cmd_args cmd;
2093 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2094
2095 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2096 return;
2097
2098 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
2099 if (err)
2100 return;
2101
2102 if (coal->type == QLCNIC_INTR_COAL_TYPE_RX) {
2103 temp = adapter->recv_ctx->context_id;
2104 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_RX | temp << 16;
2105 temp = coal->rx_time_us;
2106 cmd.req.arg[2] = coal->rx_packets | temp << 16;
2107 } else if (coal->type == QLCNIC_INTR_COAL_TYPE_TX) {
2108 temp = adapter->tx_ring->ctx_id;
2109 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_TX | temp << 16;
2110 temp = coal->tx_time_us;
2111 cmd.req.arg[2] = coal->tx_packets | temp << 16;
2112 }
2113 cmd.req.arg[3] = coal->flag;
2114 err = qlcnic_issue_cmd(adapter, &cmd);
2115 if (err != QLCNIC_RCODE_SUCCESS)
2116 dev_info(&adapter->pdev->dev,
2117 "Failed to send interrupt coalescence parameters\n");
2118 qlcnic_free_mbx_args(&cmd);
2119 }
2120
2121 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
2122 u32 data[])
2123 {
2124 struct qlcnic_hardware_context *ahw = adapter->ahw;
2125 u8 link_status, duplex;
2126 /* link speed */
2127 link_status = LSB(data[3]) & 1;
2128 if (link_status) {
2129 ahw->link_speed = MSW(data[2]);
2130 duplex = LSB(MSW(data[3]));
2131 if (duplex)
2132 ahw->link_duplex = DUPLEX_FULL;
2133 else
2134 ahw->link_duplex = DUPLEX_HALF;
2135 } else {
2136 ahw->link_speed = SPEED_UNKNOWN;
2137 ahw->link_duplex = DUPLEX_UNKNOWN;
2138 }
2139
2140 ahw->link_autoneg = MSB(MSW(data[3]));
2141 ahw->module_type = MSB(LSW(data[3]));
2142 ahw->has_link_events = 1;
2143 qlcnic_advert_link_change(adapter, link_status);
2144 }
2145
2146 irqreturn_t qlcnic_83xx_handle_aen(int irq, void *data)
2147 {
2148 struct qlcnic_adapter *adapter = data;
2149 struct qlcnic_mailbox *mbx;
2150 u32 mask, resp, event;
2151 unsigned long flags;
2152
2153 mbx = adapter->ahw->mailbox;
2154 spin_lock_irqsave(&mbx->aen_lock, flags);
2155 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
2156 if (!(resp & QLCNIC_SET_OWNER))
2157 goto out;
2158
2159 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
2160 if (event & QLCNIC_MBX_ASYNC_EVENT)
2161 __qlcnic_83xx_process_aen(adapter);
2162 else
2163 qlcnic_83xx_notify_mbx_response(mbx);
2164
2165 out:
2166 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
2167 writel(0, adapter->ahw->pci_base0 + mask);
2168 spin_unlock_irqrestore(&mbx->aen_lock, flags);
2169 return IRQ_HANDLED;
2170 }
2171
2172 int qlcnic_enable_eswitch(struct qlcnic_adapter *adapter, u8 port, u8 enable)
2173 {
2174 int err = -EIO;
2175 struct qlcnic_cmd_args cmd;
2176
2177 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2178 dev_err(&adapter->pdev->dev,
2179 "%s: Error, invoked by non management func\n",
2180 __func__);
2181 return err;
2182 }
2183
2184 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_TOGGLE_ESWITCH);
2185 if (err)
2186 return err;
2187
2188 cmd.req.arg[1] = (port & 0xf) | BIT_4;
2189 err = qlcnic_issue_cmd(adapter, &cmd);
2190
2191 if (err != QLCNIC_RCODE_SUCCESS) {
2192 dev_err(&adapter->pdev->dev, "Failed to enable eswitch%d\n",
2193 err);
2194 err = -EIO;
2195 }
2196 qlcnic_free_mbx_args(&cmd);
2197
2198 return err;
2199
2200 }
2201
2202 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *adapter,
2203 struct qlcnic_info *nic)
2204 {
2205 int i, err = -EIO;
2206 struct qlcnic_cmd_args cmd;
2207
2208 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2209 dev_err(&adapter->pdev->dev,
2210 "%s: Error, invoked by non management func\n",
2211 __func__);
2212 return err;
2213 }
2214
2215 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
2216 if (err)
2217 return err;
2218
2219 cmd.req.arg[1] = (nic->pci_func << 16);
2220 cmd.req.arg[2] = 0x1 << 16;
2221 cmd.req.arg[3] = nic->phys_port | (nic->switch_mode << 16);
2222 cmd.req.arg[4] = nic->capabilities;
2223 cmd.req.arg[5] = (nic->max_mac_filters & 0xFF) | ((nic->max_mtu) << 16);
2224 cmd.req.arg[6] = (nic->max_tx_ques) | ((nic->max_rx_ques) << 16);
2225 cmd.req.arg[7] = (nic->min_tx_bw) | ((nic->max_tx_bw) << 16);
2226 for (i = 8; i < 32; i++)
2227 cmd.req.arg[i] = 0;
2228
2229 err = qlcnic_issue_cmd(adapter, &cmd);
2230
2231 if (err != QLCNIC_RCODE_SUCCESS) {
2232 dev_err(&adapter->pdev->dev, "Failed to set nic info%d\n",
2233 err);
2234 err = -EIO;
2235 }
2236
2237 qlcnic_free_mbx_args(&cmd);
2238
2239 return err;
2240 }
2241
2242 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *adapter,
2243 struct qlcnic_info *npar_info, u8 func_id)
2244 {
2245 int err;
2246 u32 temp;
2247 u8 op = 0;
2248 struct qlcnic_cmd_args cmd;
2249 struct qlcnic_hardware_context *ahw = adapter->ahw;
2250
2251 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
2252 if (err)
2253 return err;
2254
2255 if (func_id != ahw->pci_func) {
2256 temp = func_id << 16;
2257 cmd.req.arg[1] = op | BIT_31 | temp;
2258 } else {
2259 cmd.req.arg[1] = ahw->pci_func << 16;
2260 }
2261 err = qlcnic_issue_cmd(adapter, &cmd);
2262 if (err) {
2263 dev_info(&adapter->pdev->dev,
2264 "Failed to get nic info %d\n", err);
2265 goto out;
2266 }
2267
2268 npar_info->op_type = cmd.rsp.arg[1];
2269 npar_info->pci_func = cmd.rsp.arg[2] & 0xFFFF;
2270 npar_info->op_mode = (cmd.rsp.arg[2] & 0xFFFF0000) >> 16;
2271 npar_info->phys_port = cmd.rsp.arg[3] & 0xFFFF;
2272 npar_info->switch_mode = (cmd.rsp.arg[3] & 0xFFFF0000) >> 16;
2273 npar_info->capabilities = cmd.rsp.arg[4];
2274 npar_info->max_mac_filters = cmd.rsp.arg[5] & 0xFF;
2275 npar_info->max_mtu = (cmd.rsp.arg[5] & 0xFFFF0000) >> 16;
2276 npar_info->max_tx_ques = cmd.rsp.arg[6] & 0xFFFF;
2277 npar_info->max_rx_ques = (cmd.rsp.arg[6] & 0xFFFF0000) >> 16;
2278 npar_info->min_tx_bw = cmd.rsp.arg[7] & 0xFFFF;
2279 npar_info->max_tx_bw = (cmd.rsp.arg[7] & 0xFFFF0000) >> 16;
2280 if (cmd.rsp.arg[8] & 0x1)
2281 npar_info->max_bw_reg_offset = (cmd.rsp.arg[8] & 0x7FFE) >> 1;
2282 if (cmd.rsp.arg[8] & 0x10000) {
2283 temp = (cmd.rsp.arg[8] & 0x7FFE0000) >> 17;
2284 npar_info->max_linkspeed_reg_offset = temp;
2285 }
2286
2287 memcpy(ahw->extra_capability, &cmd.rsp.arg[16],
2288 sizeof(ahw->extra_capability));
2289
2290 out:
2291 qlcnic_free_mbx_args(&cmd);
2292 return err;
2293 }
2294
2295 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *adapter,
2296 struct qlcnic_pci_info *pci_info)
2297 {
2298 struct qlcnic_hardware_context *ahw = adapter->ahw;
2299 struct device *dev = &adapter->pdev->dev;
2300 struct qlcnic_cmd_args cmd;
2301 int i, err = 0, j = 0;
2302 u32 temp;
2303
2304 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
2305 if (err)
2306 return err;
2307
2308 err = qlcnic_issue_cmd(adapter, &cmd);
2309
2310 ahw->act_pci_func = 0;
2311 if (err == QLCNIC_RCODE_SUCCESS) {
2312 ahw->max_pci_func = cmd.rsp.arg[1] & 0xFF;
2313 for (i = 2, j = 0; j < QLCNIC_MAX_PCI_FUNC; j++, pci_info++) {
2314 pci_info->id = cmd.rsp.arg[i] & 0xFFFF;
2315 pci_info->active = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2316 i++;
2317 pci_info->type = cmd.rsp.arg[i] & 0xFFFF;
2318 if (pci_info->type == QLCNIC_TYPE_NIC)
2319 ahw->act_pci_func++;
2320 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2321 pci_info->default_port = temp;
2322 i++;
2323 pci_info->tx_min_bw = cmd.rsp.arg[i] & 0xFFFF;
2324 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2325 pci_info->tx_max_bw = temp;
2326 i = i + 2;
2327 memcpy(pci_info->mac, &cmd.rsp.arg[i], ETH_ALEN - 2);
2328 i++;
2329 memcpy(pci_info->mac + sizeof(u32), &cmd.rsp.arg[i], 2);
2330 i = i + 3;
2331 }
2332 } else {
2333 dev_err(dev, "Failed to get PCI Info, error = %d\n", err);
2334 err = -EIO;
2335 }
2336
2337 qlcnic_free_mbx_args(&cmd);
2338
2339 return err;
2340 }
2341
2342 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *adapter, bool op_type)
2343 {
2344 int i, index, err;
2345 u8 max_ints;
2346 u32 val, temp, type;
2347 struct qlcnic_cmd_args cmd;
2348
2349 max_ints = adapter->ahw->num_msix - 1;
2350 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTRPT);
2351 if (err)
2352 return err;
2353
2354 cmd.req.arg[1] = max_ints;
2355
2356 if (qlcnic_sriov_vf_check(adapter))
2357 cmd.req.arg[1] |= (adapter->ahw->pci_func << 8) | BIT_16;
2358
2359 for (i = 0, index = 2; i < max_ints; i++) {
2360 type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
2361 val = type | (adapter->ahw->intr_tbl[i].type << 4);
2362 if (adapter->ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
2363 val |= (adapter->ahw->intr_tbl[i].id << 16);
2364 cmd.req.arg[index++] = val;
2365 }
2366 err = qlcnic_issue_cmd(adapter, &cmd);
2367 if (err) {
2368 dev_err(&adapter->pdev->dev,
2369 "Failed to configure interrupts 0x%x\n", err);
2370 goto out;
2371 }
2372
2373 max_ints = cmd.rsp.arg[1];
2374 for (i = 0, index = 2; i < max_ints; i++, index += 2) {
2375 val = cmd.rsp.arg[index];
2376 if (LSB(val)) {
2377 dev_info(&adapter->pdev->dev,
2378 "Can't configure interrupt %d\n",
2379 adapter->ahw->intr_tbl[i].id);
2380 continue;
2381 }
2382 if (op_type) {
2383 adapter->ahw->intr_tbl[i].id = MSW(val);
2384 adapter->ahw->intr_tbl[i].enabled = 1;
2385 temp = cmd.rsp.arg[index + 1];
2386 adapter->ahw->intr_tbl[i].src = temp;
2387 } else {
2388 adapter->ahw->intr_tbl[i].id = i;
2389 adapter->ahw->intr_tbl[i].enabled = 0;
2390 adapter->ahw->intr_tbl[i].src = 0;
2391 }
2392 }
2393 out:
2394 qlcnic_free_mbx_args(&cmd);
2395 return err;
2396 }
2397
2398 int qlcnic_83xx_lock_flash(struct qlcnic_adapter *adapter)
2399 {
2400 int id, timeout = 0;
2401 u32 status = 0;
2402
2403 while (status == 0) {
2404 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK);
2405 if (status)
2406 break;
2407
2408 if (++timeout >= QLC_83XX_FLASH_LOCK_TIMEOUT) {
2409 id = QLC_SHARED_REG_RD32(adapter,
2410 QLCNIC_FLASH_LOCK_OWNER);
2411 dev_err(&adapter->pdev->dev,
2412 "%s: failed, lock held by %d\n", __func__, id);
2413 return -EIO;
2414 }
2415 usleep_range(1000, 2000);
2416 }
2417
2418 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, adapter->portnum);
2419 return 0;
2420 }
2421
2422 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *adapter)
2423 {
2424 QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK);
2425 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 0xFF);
2426 }
2427
2428 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter,
2429 u32 flash_addr, u8 *p_data,
2430 int count)
2431 {
2432 u32 word, range, flash_offset, addr = flash_addr, ret;
2433 ulong indirect_add, direct_window;
2434 int i, err = 0;
2435
2436 flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1);
2437 if (addr & 0x3) {
2438 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2439 return -EIO;
2440 }
2441
2442 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_DIRECT_WINDOW,
2443 (addr));
2444
2445 range = flash_offset + (count * sizeof(u32));
2446 /* Check if data is spread across multiple sectors */
2447 if (range > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2448
2449 /* Multi sector read */
2450 for (i = 0; i < count; i++) {
2451 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2452 ret = QLCRD32(adapter, indirect_add, &err);
2453 if (err == -EIO)
2454 return err;
2455
2456 word = ret;
2457 *(u32 *)p_data = word;
2458 p_data = p_data + 4;
2459 addr = addr + 4;
2460 flash_offset = flash_offset + 4;
2461
2462 if (flash_offset > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2463 direct_window = QLC_83XX_FLASH_DIRECT_WINDOW;
2464 /* This write is needed once for each sector */
2465 qlcnic_83xx_wrt_reg_indirect(adapter,
2466 direct_window,
2467 (addr));
2468 flash_offset = 0;
2469 }
2470 }
2471 } else {
2472 /* Single sector read */
2473 for (i = 0; i < count; i++) {
2474 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2475 ret = QLCRD32(adapter, indirect_add, &err);
2476 if (err == -EIO)
2477 return err;
2478
2479 word = ret;
2480 *(u32 *)p_data = word;
2481 p_data = p_data + 4;
2482 addr = addr + 4;
2483 }
2484 }
2485
2486 return 0;
2487 }
2488
2489 static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter)
2490 {
2491 u32 status;
2492 int retries = QLC_83XX_FLASH_READ_RETRY_COUNT;
2493 int err = 0;
2494
2495 do {
2496 status = QLCRD32(adapter, QLC_83XX_FLASH_STATUS, &err);
2497 if (err == -EIO)
2498 return err;
2499
2500 if ((status & QLC_83XX_FLASH_STATUS_READY) ==
2501 QLC_83XX_FLASH_STATUS_READY)
2502 break;
2503
2504 msleep(QLC_83XX_FLASH_STATUS_REG_POLL_DELAY);
2505 } while (--retries);
2506
2507 if (!retries)
2508 return -EIO;
2509
2510 return 0;
2511 }
2512
2513 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *adapter)
2514 {
2515 int ret;
2516 u32 cmd;
2517 cmd = adapter->ahw->fdt.write_statusreg_cmd;
2518 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2519 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | cmd));
2520 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2521 adapter->ahw->fdt.write_enable_bits);
2522 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2523 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2524 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2525 if (ret)
2526 return -EIO;
2527
2528 return 0;
2529 }
2530
2531 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *adapter)
2532 {
2533 int ret;
2534
2535 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2536 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG |
2537 adapter->ahw->fdt.write_statusreg_cmd));
2538 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2539 adapter->ahw->fdt.write_disable_bits);
2540 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2541 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2542 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2543 if (ret)
2544 return -EIO;
2545
2546 return 0;
2547 }
2548
2549 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter)
2550 {
2551 int ret, err = 0;
2552 u32 mfg_id;
2553
2554 if (qlcnic_83xx_lock_flash(adapter))
2555 return -EIO;
2556
2557 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2558 QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL);
2559 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2560 QLC_83XX_FLASH_READ_CTRL);
2561 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2562 if (ret) {
2563 qlcnic_83xx_unlock_flash(adapter);
2564 return -EIO;
2565 }
2566
2567 mfg_id = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
2568 if (err == -EIO) {
2569 qlcnic_83xx_unlock_flash(adapter);
2570 return err;
2571 }
2572
2573 adapter->flash_mfg_id = (mfg_id & 0xFF);
2574 qlcnic_83xx_unlock_flash(adapter);
2575
2576 return 0;
2577 }
2578
2579 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *adapter)
2580 {
2581 int count, fdt_size, ret = 0;
2582
2583 fdt_size = sizeof(struct qlcnic_fdt);
2584 count = fdt_size / sizeof(u32);
2585
2586 if (qlcnic_83xx_lock_flash(adapter))
2587 return -EIO;
2588
2589 memset(&adapter->ahw->fdt, 0, fdt_size);
2590 ret = qlcnic_83xx_lockless_flash_read32(adapter, QLCNIC_FDT_LOCATION,
2591 (u8 *)&adapter->ahw->fdt,
2592 count);
2593
2594 qlcnic_83xx_unlock_flash(adapter);
2595 return ret;
2596 }
2597
2598 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *adapter,
2599 u32 sector_start_addr)
2600 {
2601 u32 reversed_addr, addr1, addr2, cmd;
2602 int ret = -EIO;
2603
2604 if (qlcnic_83xx_lock_flash(adapter) != 0)
2605 return -EIO;
2606
2607 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2608 ret = qlcnic_83xx_enable_flash_write(adapter);
2609 if (ret) {
2610 qlcnic_83xx_unlock_flash(adapter);
2611 dev_err(&adapter->pdev->dev,
2612 "%s failed at %d\n",
2613 __func__, __LINE__);
2614 return ret;
2615 }
2616 }
2617
2618 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2619 if (ret) {
2620 qlcnic_83xx_unlock_flash(adapter);
2621 dev_err(&adapter->pdev->dev,
2622 "%s: failed at %d\n", __func__, __LINE__);
2623 return -EIO;
2624 }
2625
2626 addr1 = (sector_start_addr & 0xFF) << 16;
2627 addr2 = (sector_start_addr & 0xFF0000) >> 16;
2628 reversed_addr = addr1 | addr2;
2629
2630 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2631 reversed_addr);
2632 cmd = QLC_83XX_FLASH_FDT_ERASE_DEF_SIG | adapter->ahw->fdt.erase_cmd;
2633 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id)
2634 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, cmd);
2635 else
2636 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2637 QLC_83XX_FLASH_OEM_ERASE_SIG);
2638 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2639 QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2640
2641 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2642 if (ret) {
2643 qlcnic_83xx_unlock_flash(adapter);
2644 dev_err(&adapter->pdev->dev,
2645 "%s: failed at %d\n", __func__, __LINE__);
2646 return -EIO;
2647 }
2648
2649 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2650 ret = qlcnic_83xx_disable_flash_write(adapter);
2651 if (ret) {
2652 qlcnic_83xx_unlock_flash(adapter);
2653 dev_err(&adapter->pdev->dev,
2654 "%s: failed at %d\n", __func__, __LINE__);
2655 return ret;
2656 }
2657 }
2658
2659 qlcnic_83xx_unlock_flash(adapter);
2660
2661 return 0;
2662 }
2663
2664 int qlcnic_83xx_flash_write32(struct qlcnic_adapter *adapter, u32 addr,
2665 u32 *p_data)
2666 {
2667 int ret = -EIO;
2668 u32 addr1 = 0x00800000 | (addr >> 2);
2669
2670 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, addr1);
2671 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data);
2672 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2673 QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2674 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2675 if (ret) {
2676 dev_err(&adapter->pdev->dev,
2677 "%s: failed at %d\n", __func__, __LINE__);
2678 return -EIO;
2679 }
2680
2681 return 0;
2682 }
2683
2684 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr,
2685 u32 *p_data, int count)
2686 {
2687 u32 temp;
2688 int ret = -EIO, err = 0;
2689
2690 if ((count < QLC_83XX_FLASH_WRITE_MIN) ||
2691 (count > QLC_83XX_FLASH_WRITE_MAX)) {
2692 dev_err(&adapter->pdev->dev,
2693 "%s: Invalid word count\n", __func__);
2694 return -EIO;
2695 }
2696
2697 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2698 if (err == -EIO)
2699 return err;
2700
2701 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL,
2702 (temp | QLC_83XX_FLASH_SPI_CTRL));
2703 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2704 QLC_83XX_FLASH_ADDR_TEMP_VAL);
2705
2706 /* First DWORD write */
2707 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2708 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2709 QLC_83XX_FLASH_FIRST_MS_PATTERN);
2710 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2711 if (ret) {
2712 dev_err(&adapter->pdev->dev,
2713 "%s: failed at %d\n", __func__, __LINE__);
2714 return -EIO;
2715 }
2716
2717 count--;
2718 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2719 QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL);
2720 /* Second to N-1 DWORD writes */
2721 while (count != 1) {
2722 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2723 *p_data++);
2724 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2725 QLC_83XX_FLASH_SECOND_MS_PATTERN);
2726 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2727 if (ret) {
2728 dev_err(&adapter->pdev->dev,
2729 "%s: failed at %d\n", __func__, __LINE__);
2730 return -EIO;
2731 }
2732 count--;
2733 }
2734
2735 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2736 QLC_83XX_FLASH_ADDR_TEMP_VAL |
2737 (addr >> 2));
2738 /* Last DWORD write */
2739 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2740 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2741 QLC_83XX_FLASH_LAST_MS_PATTERN);
2742 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2743 if (ret) {
2744 dev_err(&adapter->pdev->dev,
2745 "%s: failed at %d\n", __func__, __LINE__);
2746 return -EIO;
2747 }
2748
2749 ret = QLCRD32(adapter, QLC_83XX_FLASH_SPI_STATUS, &err);
2750 if (err == -EIO)
2751 return err;
2752
2753 if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) {
2754 dev_err(&adapter->pdev->dev, "%s: failed at %d\n",
2755 __func__, __LINE__);
2756 /* Operation failed, clear error bit */
2757 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2758 if (err == -EIO)
2759 return err;
2760
2761 qlcnic_83xx_wrt_reg_indirect(adapter,
2762 QLC_83XX_FLASH_SPI_CONTROL,
2763 (temp | QLC_83XX_FLASH_SPI_CTRL));
2764 }
2765
2766 return 0;
2767 }
2768
2769 static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter *adapter)
2770 {
2771 u32 val, id;
2772
2773 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2774
2775 /* Check if recovery need to be performed by the calling function */
2776 if ((val & QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK) == 0) {
2777 val = val & ~0x3F;
2778 val = val | ((adapter->portnum << 2) |
2779 QLC_83XX_NEED_DRV_LOCK_RECOVERY);
2780 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2781 dev_info(&adapter->pdev->dev,
2782 "%s: lock recovery initiated\n", __func__);
2783 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY);
2784 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2785 id = ((val >> 2) & 0xF);
2786 if (id == adapter->portnum) {
2787 val = val & ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK;
2788 val = val | QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS;
2789 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2790 /* Force release the lock */
2791 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2792 /* Clear recovery bits */
2793 val = val & ~0x3F;
2794 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2795 dev_info(&adapter->pdev->dev,
2796 "%s: lock recovery completed\n", __func__);
2797 } else {
2798 dev_info(&adapter->pdev->dev,
2799 "%s: func %d to resume lock recovery process\n",
2800 __func__, id);
2801 }
2802 } else {
2803 dev_info(&adapter->pdev->dev,
2804 "%s: lock recovery initiated by other functions\n",
2805 __func__);
2806 }
2807 }
2808
2809 int qlcnic_83xx_lock_driver(struct qlcnic_adapter *adapter)
2810 {
2811 u32 lock_alive_counter, val, id, i = 0, status = 0, temp = 0;
2812 int max_attempt = 0;
2813
2814 while (status == 0) {
2815 status = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK);
2816 if (status)
2817 break;
2818
2819 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY);
2820 i++;
2821
2822 if (i == 1)
2823 temp = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2824
2825 if (i == QLC_83XX_DRV_LOCK_WAIT_COUNTER) {
2826 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2827 if (val == temp) {
2828 id = val & 0xFF;
2829 dev_info(&adapter->pdev->dev,
2830 "%s: lock to be recovered from %d\n",
2831 __func__, id);
2832 qlcnic_83xx_recover_driver_lock(adapter);
2833 i = 0;
2834 max_attempt++;
2835 } else {
2836 dev_err(&adapter->pdev->dev,
2837 "%s: failed to get lock\n", __func__);
2838 return -EIO;
2839 }
2840 }
2841
2842 /* Force exit from while loop after few attempts */
2843 if (max_attempt == QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT) {
2844 dev_err(&adapter->pdev->dev,
2845 "%s: failed to get lock\n", __func__);
2846 return -EIO;
2847 }
2848 }
2849
2850 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2851 lock_alive_counter = val >> 8;
2852 lock_alive_counter++;
2853 val = lock_alive_counter << 8 | adapter->portnum;
2854 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2855
2856 return 0;
2857 }
2858
2859 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *adapter)
2860 {
2861 u32 val, lock_alive_counter, id;
2862
2863 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2864 id = val & 0xFF;
2865 lock_alive_counter = val >> 8;
2866
2867 if (id != adapter->portnum)
2868 dev_err(&adapter->pdev->dev,
2869 "%s:Warning func %d is unlocking lock owned by %d\n",
2870 __func__, adapter->portnum, id);
2871
2872 val = (lock_alive_counter << 8) | 0xFF;
2873 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2874 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2875 }
2876
2877 int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr,
2878 u32 *data, u32 count)
2879 {
2880 int i, j, ret = 0;
2881 u32 temp;
2882 int err = 0;
2883
2884 /* Check alignment */
2885 if (addr & 0xF)
2886 return -EIO;
2887
2888 mutex_lock(&adapter->ahw->mem_lock);
2889 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_HI, 0);
2890
2891 for (i = 0; i < count; i++, addr += 16) {
2892 if (!((ADDR_IN_RANGE(addr, QLCNIC_ADDR_QDR_NET,
2893 QLCNIC_ADDR_QDR_NET_MAX)) ||
2894 (ADDR_IN_RANGE(addr, QLCNIC_ADDR_DDR_NET,
2895 QLCNIC_ADDR_DDR_NET_MAX)))) {
2896 mutex_unlock(&adapter->ahw->mem_lock);
2897 return -EIO;
2898 }
2899
2900 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_LO, addr);
2901 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_LO,
2902 *data++);
2903 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_HI,
2904 *data++);
2905 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_ULO,
2906 *data++);
2907 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_UHI,
2908 *data++);
2909 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2910 QLCNIC_TA_WRITE_ENABLE);
2911 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2912 QLCNIC_TA_WRITE_START);
2913
2914 for (j = 0; j < MAX_CTL_CHECK; j++) {
2915 temp = QLCRD32(adapter, QLCNIC_MS_CTRL, &err);
2916 if (err == -EIO) {
2917 mutex_unlock(&adapter->ahw->mem_lock);
2918 return err;
2919 }
2920
2921 if ((temp & TA_CTL_BUSY) == 0)
2922 break;
2923 }
2924
2925 /* Status check failure */
2926 if (j >= MAX_CTL_CHECK) {
2927 printk_ratelimited(KERN_WARNING
2928 "MS memory write failed\n");
2929 mutex_unlock(&adapter->ahw->mem_lock);
2930 return -EIO;
2931 }
2932 }
2933
2934 mutex_unlock(&adapter->ahw->mem_lock);
2935
2936 return ret;
2937 }
2938
2939 int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr,
2940 u8 *p_data, int count)
2941 {
2942 u32 word, addr = flash_addr, ret;
2943 ulong indirect_addr;
2944 int i, err = 0;
2945
2946 if (qlcnic_83xx_lock_flash(adapter) != 0)
2947 return -EIO;
2948
2949 if (addr & 0x3) {
2950 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2951 qlcnic_83xx_unlock_flash(adapter);
2952 return -EIO;
2953 }
2954
2955 for (i = 0; i < count; i++) {
2956 if (qlcnic_83xx_wrt_reg_indirect(adapter,
2957 QLC_83XX_FLASH_DIRECT_WINDOW,
2958 (addr))) {
2959 qlcnic_83xx_unlock_flash(adapter);
2960 return -EIO;
2961 }
2962
2963 indirect_addr = QLC_83XX_FLASH_DIRECT_DATA(addr);
2964 ret = QLCRD32(adapter, indirect_addr, &err);
2965 if (err == -EIO)
2966 return err;
2967
2968 word = ret;
2969 *(u32 *)p_data = word;
2970 p_data = p_data + 4;
2971 addr = addr + 4;
2972 }
2973
2974 qlcnic_83xx_unlock_flash(adapter);
2975
2976 return 0;
2977 }
2978
2979 int qlcnic_83xx_test_link(struct qlcnic_adapter *adapter)
2980 {
2981 u8 pci_func;
2982 int err;
2983 u32 config = 0, state;
2984 struct qlcnic_cmd_args cmd;
2985 struct qlcnic_hardware_context *ahw = adapter->ahw;
2986
2987 if (qlcnic_sriov_vf_check(adapter))
2988 pci_func = adapter->portnum;
2989 else
2990 pci_func = ahw->pci_func;
2991
2992 state = readl(ahw->pci_base0 + QLC_83XX_LINK_STATE(pci_func));
2993 if (!QLC_83xx_FUNC_VAL(state, pci_func)) {
2994 dev_info(&adapter->pdev->dev, "link state down\n");
2995 return config;
2996 }
2997
2998 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS);
2999 if (err)
3000 return err;
3001
3002 err = qlcnic_issue_cmd(adapter, &cmd);
3003 if (err) {
3004 dev_info(&adapter->pdev->dev,
3005 "Get Link Status Command failed: 0x%x\n", err);
3006 goto out;
3007 } else {
3008 config = cmd.rsp.arg[1];
3009 switch (QLC_83XX_CURRENT_LINK_SPEED(config)) {
3010 case QLC_83XX_10M_LINK:
3011 ahw->link_speed = SPEED_10;
3012 break;
3013 case QLC_83XX_100M_LINK:
3014 ahw->link_speed = SPEED_100;
3015 break;
3016 case QLC_83XX_1G_LINK:
3017 ahw->link_speed = SPEED_1000;
3018 break;
3019 case QLC_83XX_10G_LINK:
3020 ahw->link_speed = SPEED_10000;
3021 break;
3022 default:
3023 ahw->link_speed = 0;
3024 break;
3025 }
3026 config = cmd.rsp.arg[3];
3027 if (QLC_83XX_SFP_PRESENT(config)) {
3028 switch (ahw->module_type) {
3029 case LINKEVENT_MODULE_OPTICAL_UNKNOWN:
3030 case LINKEVENT_MODULE_OPTICAL_SRLR:
3031 case LINKEVENT_MODULE_OPTICAL_LRM:
3032 case LINKEVENT_MODULE_OPTICAL_SFP_1G:
3033 ahw->supported_type = PORT_FIBRE;
3034 break;
3035 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE:
3036 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN:
3037 case LINKEVENT_MODULE_TWINAX:
3038 ahw->supported_type = PORT_TP;
3039 break;
3040 default:
3041 ahw->supported_type = PORT_OTHER;
3042 }
3043 }
3044 if (config & 1)
3045 err = 1;
3046 }
3047 out:
3048 qlcnic_free_mbx_args(&cmd);
3049 return config;
3050 }
3051
3052 int qlcnic_83xx_get_settings(struct qlcnic_adapter *adapter,
3053 struct ethtool_cmd *ecmd)
3054 {
3055 u32 config = 0;
3056 int status = 0;
3057 struct qlcnic_hardware_context *ahw = adapter->ahw;
3058
3059 if (!test_bit(__QLCNIC_MAINTENANCE_MODE, &adapter->state)) {
3060 /* Get port configuration info */
3061 status = qlcnic_83xx_get_port_info(adapter);
3062 /* Get Link Status related info */
3063 config = qlcnic_83xx_test_link(adapter);
3064 ahw->module_type = QLC_83XX_SFP_MODULE_TYPE(config);
3065 }
3066
3067 /* hard code until there is a way to get it from flash */
3068 ahw->board_type = QLCNIC_BRDTYPE_83XX_10G;
3069
3070 if (netif_running(adapter->netdev) && ahw->has_link_events) {
3071 ethtool_cmd_speed_set(ecmd, ahw->link_speed);
3072 ecmd->duplex = ahw->link_duplex;
3073 ecmd->autoneg = ahw->link_autoneg;
3074 } else {
3075 ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN);
3076 ecmd->duplex = DUPLEX_UNKNOWN;
3077 ecmd->autoneg = AUTONEG_DISABLE;
3078 }
3079
3080 if (ahw->port_type == QLCNIC_XGBE) {
3081 ecmd->supported = SUPPORTED_10000baseT_Full;
3082 ecmd->advertising = ADVERTISED_10000baseT_Full;
3083 } else {
3084 ecmd->supported = (SUPPORTED_10baseT_Half |
3085 SUPPORTED_10baseT_Full |
3086 SUPPORTED_100baseT_Half |
3087 SUPPORTED_100baseT_Full |
3088 SUPPORTED_1000baseT_Half |
3089 SUPPORTED_1000baseT_Full);
3090 ecmd->advertising = (ADVERTISED_100baseT_Half |
3091 ADVERTISED_100baseT_Full |
3092 ADVERTISED_1000baseT_Half |
3093 ADVERTISED_1000baseT_Full);
3094 }
3095
3096 switch (ahw->supported_type) {
3097 case PORT_FIBRE:
3098 ecmd->supported |= SUPPORTED_FIBRE;
3099 ecmd->advertising |= ADVERTISED_FIBRE;
3100 ecmd->port = PORT_FIBRE;
3101 ecmd->transceiver = XCVR_EXTERNAL;
3102 break;
3103 case PORT_TP:
3104 ecmd->supported |= SUPPORTED_TP;
3105 ecmd->advertising |= ADVERTISED_TP;
3106 ecmd->port = PORT_TP;
3107 ecmd->transceiver = XCVR_INTERNAL;
3108 break;
3109 default:
3110 ecmd->supported |= SUPPORTED_FIBRE;
3111 ecmd->advertising |= ADVERTISED_FIBRE;
3112 ecmd->port = PORT_OTHER;
3113 ecmd->transceiver = XCVR_EXTERNAL;
3114 break;
3115 }
3116 ecmd->phy_address = ahw->physical_port;
3117 return status;
3118 }
3119
3120 int qlcnic_83xx_set_settings(struct qlcnic_adapter *adapter,
3121 struct ethtool_cmd *ecmd)
3122 {
3123 int status = 0;
3124 u32 config = adapter->ahw->port_config;
3125
3126 if (ecmd->autoneg)
3127 adapter->ahw->port_config |= BIT_15;
3128
3129 switch (ethtool_cmd_speed(ecmd)) {
3130 case SPEED_10:
3131 adapter->ahw->port_config |= BIT_8;
3132 break;
3133 case SPEED_100:
3134 adapter->ahw->port_config |= BIT_9;
3135 break;
3136 case SPEED_1000:
3137 adapter->ahw->port_config |= BIT_10;
3138 break;
3139 case SPEED_10000:
3140 adapter->ahw->port_config |= BIT_11;
3141 break;
3142 default:
3143 return -EINVAL;
3144 }
3145
3146 status = qlcnic_83xx_set_port_config(adapter);
3147 if (status) {
3148 dev_info(&adapter->pdev->dev,
3149 "Failed to Set Link Speed and autoneg.\n");
3150 adapter->ahw->port_config = config;
3151 }
3152 return status;
3153 }
3154
3155 static inline u64 *qlcnic_83xx_copy_stats(struct qlcnic_cmd_args *cmd,
3156 u64 *data, int index)
3157 {
3158 u32 low, hi;
3159 u64 val;
3160
3161 low = cmd->rsp.arg[index];
3162 hi = cmd->rsp.arg[index + 1];
3163 val = (((u64) low) | (((u64) hi) << 32));
3164 *data++ = val;
3165 return data;
3166 }
3167
3168 static u64 *qlcnic_83xx_fill_stats(struct qlcnic_adapter *adapter,
3169 struct qlcnic_cmd_args *cmd, u64 *data,
3170 int type, int *ret)
3171 {
3172 int err, k, total_regs;
3173
3174 *ret = 0;
3175 err = qlcnic_issue_cmd(adapter, cmd);
3176 if (err != QLCNIC_RCODE_SUCCESS) {
3177 dev_info(&adapter->pdev->dev,
3178 "Error in get statistics mailbox command\n");
3179 *ret = -EIO;
3180 return data;
3181 }
3182 total_regs = cmd->rsp.num;
3183 switch (type) {
3184 case QLC_83XX_STAT_MAC:
3185 /* fill in MAC tx counters */
3186 for (k = 2; k < 28; k += 2)
3187 data = qlcnic_83xx_copy_stats(cmd, data, k);
3188 /* skip 24 bytes of reserved area */
3189 /* fill in MAC rx counters */
3190 for (k += 6; k < 60; k += 2)
3191 data = qlcnic_83xx_copy_stats(cmd, data, k);
3192 /* skip 24 bytes of reserved area */
3193 /* fill in MAC rx frame stats */
3194 for (k += 6; k < 80; k += 2)
3195 data = qlcnic_83xx_copy_stats(cmd, data, k);
3196 /* fill in eSwitch stats */
3197 for (; k < total_regs; k += 2)
3198 data = qlcnic_83xx_copy_stats(cmd, data, k);
3199 break;
3200 case QLC_83XX_STAT_RX:
3201 for (k = 2; k < 8; k += 2)
3202 data = qlcnic_83xx_copy_stats(cmd, data, k);
3203 /* skip 8 bytes of reserved data */
3204 for (k += 2; k < 24; k += 2)
3205 data = qlcnic_83xx_copy_stats(cmd, data, k);
3206 /* skip 8 bytes containing RE1FBQ error data */
3207 for (k += 2; k < total_regs; k += 2)
3208 data = qlcnic_83xx_copy_stats(cmd, data, k);
3209 break;
3210 case QLC_83XX_STAT_TX:
3211 for (k = 2; k < 10; k += 2)
3212 data = qlcnic_83xx_copy_stats(cmd, data, k);
3213 /* skip 8 bytes of reserved data */
3214 for (k += 2; k < total_regs; k += 2)
3215 data = qlcnic_83xx_copy_stats(cmd, data, k);
3216 break;
3217 default:
3218 dev_warn(&adapter->pdev->dev, "Unknown get statistics mode\n");
3219 *ret = -EIO;
3220 }
3221 return data;
3222 }
3223
3224 void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data)
3225 {
3226 struct qlcnic_cmd_args cmd;
3227 struct net_device *netdev = adapter->netdev;
3228 int ret = 0;
3229
3230 ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_STATISTICS);
3231 if (ret)
3232 return;
3233 /* Get Tx stats */
3234 cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16);
3235 cmd.rsp.num = QLC_83XX_TX_STAT_REGS;
3236 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3237 QLC_83XX_STAT_TX, &ret);
3238 if (ret) {
3239 netdev_err(netdev, "Error getting Tx stats\n");
3240 goto out;
3241 }
3242 /* Get MAC stats */
3243 cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16);
3244 cmd.rsp.num = QLC_83XX_MAC_STAT_REGS;
3245 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3246 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3247 QLC_83XX_STAT_MAC, &ret);
3248 if (ret) {
3249 netdev_err(netdev, "Error getting MAC stats\n");
3250 goto out;
3251 }
3252 /* Get Rx stats */
3253 cmd.req.arg[1] = adapter->recv_ctx->context_id << 16;
3254 cmd.rsp.num = QLC_83XX_RX_STAT_REGS;
3255 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3256 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3257 QLC_83XX_STAT_RX, &ret);
3258 if (ret)
3259 netdev_err(netdev, "Error getting Rx stats\n");
3260 out:
3261 qlcnic_free_mbx_args(&cmd);
3262 }
3263
3264 int qlcnic_83xx_reg_test(struct qlcnic_adapter *adapter)
3265 {
3266 u32 major, minor, sub;
3267
3268 major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
3269 minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
3270 sub = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
3271
3272 if (adapter->fw_version != QLCNIC_VERSION_CODE(major, minor, sub)) {
3273 dev_info(&adapter->pdev->dev, "%s: Reg test failed\n",
3274 __func__);
3275 return 1;
3276 }
3277 return 0;
3278 }
3279
3280 inline int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *adapter)
3281 {
3282 return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl) *
3283 sizeof(*adapter->ahw->ext_reg_tbl)) +
3284 (ARRAY_SIZE(qlcnic_83xx_reg_tbl) *
3285 sizeof(*adapter->ahw->reg_tbl));
3286 }
3287
3288 int qlcnic_83xx_get_registers(struct qlcnic_adapter *adapter, u32 *regs_buff)
3289 {
3290 int i, j = 0;
3291
3292 for (i = QLCNIC_DEV_INFO_SIZE + 1;
3293 j < ARRAY_SIZE(qlcnic_83xx_reg_tbl); i++, j++)
3294 regs_buff[i] = QLC_SHARED_REG_RD32(adapter, j);
3295
3296 for (j = 0; j < ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl); j++)
3297 regs_buff[i++] = QLCRDX(adapter->ahw, j);
3298 return i;
3299 }
3300
3301 int qlcnic_83xx_interrupt_test(struct net_device *netdev)
3302 {
3303 struct qlcnic_adapter *adapter = netdev_priv(netdev);
3304 struct qlcnic_hardware_context *ahw = adapter->ahw;
3305 struct qlcnic_cmd_args cmd;
3306 u32 data;
3307 u16 intrpt_id, id;
3308 u8 val;
3309 int ret, max_sds_rings = adapter->max_sds_rings;
3310
3311 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
3312 netdev_info(netdev, "Device is resetting\n");
3313 return -EBUSY;
3314 }
3315
3316 if (qlcnic_get_diag_lock(adapter)) {
3317 netdev_info(netdev, "Device in diagnostics mode\n");
3318 return -EBUSY;
3319 }
3320
3321 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_INTERRUPT_TEST,
3322 max_sds_rings);
3323 if (ret)
3324 goto fail_diag_irq;
3325
3326 ahw->diag_cnt = 0;
3327 ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INTRPT_TEST);
3328 if (ret)
3329 goto fail_diag_irq;
3330
3331 if (adapter->flags & QLCNIC_MSIX_ENABLED)
3332 intrpt_id = ahw->intr_tbl[0].id;
3333 else
3334 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
3335
3336 cmd.req.arg[1] = 1;
3337 cmd.req.arg[2] = intrpt_id;
3338 cmd.req.arg[3] = BIT_0;
3339
3340 ret = qlcnic_issue_cmd(adapter, &cmd);
3341 data = cmd.rsp.arg[2];
3342 id = LSW(data);
3343 val = LSB(MSW(data));
3344 if (id != intrpt_id)
3345 dev_info(&adapter->pdev->dev,
3346 "Interrupt generated: 0x%x, requested:0x%x\n",
3347 id, intrpt_id);
3348 if (val)
3349 dev_err(&adapter->pdev->dev,
3350 "Interrupt test error: 0x%x\n", val);
3351 if (ret)
3352 goto done;
3353
3354 msleep(20);
3355 ret = !ahw->diag_cnt;
3356
3357 done:
3358 qlcnic_free_mbx_args(&cmd);
3359 qlcnic_83xx_diag_free_res(netdev, max_sds_rings);
3360
3361 fail_diag_irq:
3362 adapter->max_sds_rings = max_sds_rings;
3363 qlcnic_release_diag_lock(adapter);
3364 return ret;
3365 }
3366
3367 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *adapter,
3368 struct ethtool_pauseparam *pause)
3369 {
3370 struct qlcnic_hardware_context *ahw = adapter->ahw;
3371 int status = 0;
3372 u32 config;
3373
3374 status = qlcnic_83xx_get_port_config(adapter);
3375 if (status) {
3376 dev_err(&adapter->pdev->dev,
3377 "%s: Get Pause Config failed\n", __func__);
3378 return;
3379 }
3380 config = ahw->port_config;
3381 if (config & QLC_83XX_CFG_STD_PAUSE) {
3382 switch (MSW(config)) {
3383 case QLC_83XX_TX_PAUSE:
3384 pause->tx_pause = 1;
3385 break;
3386 case QLC_83XX_RX_PAUSE:
3387 pause->rx_pause = 1;
3388 break;
3389 case QLC_83XX_TX_RX_PAUSE:
3390 default:
3391 /* Backward compatibility for existing
3392 * flash definitions
3393 */
3394 pause->tx_pause = 1;
3395 pause->rx_pause = 1;
3396 }
3397 }
3398
3399 if (QLC_83XX_AUTONEG(config))
3400 pause->autoneg = 1;
3401 }
3402
3403 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *adapter,
3404 struct ethtool_pauseparam *pause)
3405 {
3406 struct qlcnic_hardware_context *ahw = adapter->ahw;
3407 int status = 0;
3408 u32 config;
3409
3410 status = qlcnic_83xx_get_port_config(adapter);
3411 if (status) {
3412 dev_err(&adapter->pdev->dev,
3413 "%s: Get Pause Config failed.\n", __func__);
3414 return status;
3415 }
3416 config = ahw->port_config;
3417
3418 if (ahw->port_type == QLCNIC_GBE) {
3419 if (pause->autoneg)
3420 ahw->port_config |= QLC_83XX_ENABLE_AUTONEG;
3421 if (!pause->autoneg)
3422 ahw->port_config &= ~QLC_83XX_ENABLE_AUTONEG;
3423 } else if ((ahw->port_type == QLCNIC_XGBE) && (pause->autoneg)) {
3424 return -EOPNOTSUPP;
3425 }
3426
3427 if (!(config & QLC_83XX_CFG_STD_PAUSE))
3428 ahw->port_config |= QLC_83XX_CFG_STD_PAUSE;
3429
3430 if (pause->rx_pause && pause->tx_pause) {
3431 ahw->port_config |= QLC_83XX_CFG_STD_TX_RX_PAUSE;
3432 } else if (pause->rx_pause && !pause->tx_pause) {
3433 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_PAUSE;
3434 ahw->port_config |= QLC_83XX_CFG_STD_RX_PAUSE;
3435 } else if (pause->tx_pause && !pause->rx_pause) {
3436 ahw->port_config &= ~QLC_83XX_CFG_STD_RX_PAUSE;
3437 ahw->port_config |= QLC_83XX_CFG_STD_TX_PAUSE;
3438 } else if (!pause->rx_pause && !pause->tx_pause) {
3439 ahw->port_config &= ~(QLC_83XX_CFG_STD_TX_RX_PAUSE |
3440 QLC_83XX_CFG_STD_PAUSE);
3441 }
3442 status = qlcnic_83xx_set_port_config(adapter);
3443 if (status) {
3444 dev_err(&adapter->pdev->dev,
3445 "%s: Set Pause Config failed.\n", __func__);
3446 ahw->port_config = config;
3447 }
3448 return status;
3449 }
3450
3451 static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter)
3452 {
3453 int ret, err = 0;
3454 u32 temp;
3455
3456 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
3457 QLC_83XX_FLASH_OEM_READ_SIG);
3458 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
3459 QLC_83XX_FLASH_READ_CTRL);
3460 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
3461 if (ret)
3462 return -EIO;
3463
3464 temp = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
3465 if (err == -EIO)
3466 return err;
3467
3468 return temp & 0xFF;
3469 }
3470
3471 int qlcnic_83xx_flash_test(struct qlcnic_adapter *adapter)
3472 {
3473 int status;
3474
3475 status = qlcnic_83xx_read_flash_status_reg(adapter);
3476 if (status == -EIO) {
3477 dev_info(&adapter->pdev->dev, "%s: EEPROM test failed.\n",
3478 __func__);
3479 return 1;
3480 }
3481 return 0;
3482 }
3483
3484 int qlcnic_83xx_shutdown(struct pci_dev *pdev)
3485 {
3486 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3487 struct net_device *netdev = adapter->netdev;
3488 int retval;
3489
3490 netif_device_detach(netdev);
3491 qlcnic_cancel_idc_work(adapter);
3492
3493 if (netif_running(netdev))
3494 qlcnic_down(adapter, netdev);
3495
3496 qlcnic_83xx_disable_mbx_intr(adapter);
3497 cancel_delayed_work_sync(&adapter->idc_aen_work);
3498
3499 retval = pci_save_state(pdev);
3500 if (retval)
3501 return retval;
3502
3503 return 0;
3504 }
3505
3506 int qlcnic_83xx_resume(struct qlcnic_adapter *adapter)
3507 {
3508 struct qlcnic_hardware_context *ahw = adapter->ahw;
3509 struct qlc_83xx_idc *idc = &ahw->idc;
3510 int err = 0;
3511
3512 err = qlcnic_83xx_idc_init(adapter);
3513 if (err)
3514 return err;
3515
3516 if (ahw->nic_mode == QLC_83XX_VIRTUAL_NIC_MODE) {
3517 if (ahw->op_mode == QLCNIC_MGMT_FUNC) {
3518 qlcnic_83xx_set_vnic_opmode(adapter);
3519 } else {
3520 err = qlcnic_83xx_check_vnic_state(adapter);
3521 if (err)
3522 return err;
3523 }
3524 }
3525
3526 err = qlcnic_83xx_idc_reattach_driver(adapter);
3527 if (err)
3528 return err;
3529
3530 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
3531 idc->delay);
3532 return err;
3533 }
3534
3535 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx)
3536 {
3537 INIT_COMPLETION(mbx->completion);
3538 set_bit(QLC_83XX_MBX_READY, &mbx->status);
3539 }
3540
3541 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx)
3542 {
3543 if (!mbx)
3544 return;
3545
3546 destroy_workqueue(mbx->work_q);
3547 kfree(mbx);
3548 }
3549
3550 static inline void
3551 qlcnic_83xx_notify_cmd_completion(struct qlcnic_adapter *adapter,
3552 struct qlcnic_cmd_args *cmd)
3553 {
3554 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
3555
3556 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
3557 qlcnic_free_mbx_args(cmd);
3558 kfree(cmd);
3559 return;
3560 }
3561 complete(&cmd->completion);
3562 }
3563
3564 static void qlcnic_83xx_flush_mbx_queue(struct qlcnic_adapter *adapter)
3565 {
3566 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3567 struct list_head *head = &mbx->cmd_q;
3568 struct qlcnic_cmd_args *cmd = NULL;
3569
3570 spin_lock(&mbx->queue_lock);
3571
3572 while (!list_empty(head)) {
3573 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3574 dev_info(&adapter->pdev->dev, "%s: Mailbox command 0x%x\n",
3575 __func__, cmd->cmd_op);
3576 list_del(&cmd->list);
3577 mbx->num_cmds--;
3578 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3579 }
3580
3581 spin_unlock(&mbx->queue_lock);
3582 }
3583
3584 static int qlcnic_83xx_check_mbx_status(struct qlcnic_adapter *adapter)
3585 {
3586 struct qlcnic_hardware_context *ahw = adapter->ahw;
3587 struct qlcnic_mailbox *mbx = ahw->mailbox;
3588 u32 host_mbx_ctrl;
3589
3590 if (!test_bit(QLC_83XX_MBX_READY, &mbx->status))
3591 return -EBUSY;
3592
3593 host_mbx_ctrl = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
3594 if (host_mbx_ctrl) {
3595 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3596 ahw->idc.collect_dump = 1;
3597 return -EIO;
3598 }
3599
3600 return 0;
3601 }
3602
3603 static inline void qlcnic_83xx_signal_mbx_cmd(struct qlcnic_adapter *adapter,
3604 u8 issue_cmd)
3605 {
3606 if (issue_cmd)
3607 QLCWRX(adapter->ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER);
3608 else
3609 QLCWRX(adapter->ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
3610 }
3611
3612 static void qlcnic_83xx_dequeue_mbx_cmd(struct qlcnic_adapter *adapter,
3613 struct qlcnic_cmd_args *cmd)
3614 {
3615 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3616
3617 spin_lock(&mbx->queue_lock);
3618
3619 list_del(&cmd->list);
3620 mbx->num_cmds--;
3621
3622 spin_unlock(&mbx->queue_lock);
3623
3624 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3625 }
3626
3627 static void qlcnic_83xx_encode_mbx_cmd(struct qlcnic_adapter *adapter,
3628 struct qlcnic_cmd_args *cmd)
3629 {
3630 u32 mbx_cmd, fw_hal_version, hdr_size, total_size, tmp;
3631 struct qlcnic_hardware_context *ahw = adapter->ahw;
3632 int i, j;
3633
3634 if (cmd->op_type != QLC_83XX_MBX_POST_BC_OP) {
3635 mbx_cmd = cmd->req.arg[0];
3636 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3637 for (i = 1; i < cmd->req.num; i++)
3638 writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i));
3639 } else {
3640 fw_hal_version = ahw->fw_hal_version;
3641 hdr_size = sizeof(struct qlcnic_bc_hdr) / sizeof(u32);
3642 total_size = cmd->pay_size + hdr_size;
3643 tmp = QLCNIC_CMD_BC_EVENT_SETUP | total_size << 16;
3644 mbx_cmd = tmp | fw_hal_version << 29;
3645 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3646
3647 /* Back channel specific operations bits */
3648 mbx_cmd = 0x1 | 1 << 4;
3649
3650 if (qlcnic_sriov_pf_check(adapter))
3651 mbx_cmd |= cmd->func_num << 5;
3652
3653 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 1));
3654
3655 for (i = 2, j = 0; j < hdr_size; i++, j++)
3656 writel(*(cmd->hdr++), QLCNIC_MBX_HOST(ahw, i));
3657 for (j = 0; j < cmd->pay_size; j++, i++)
3658 writel(*(cmd->pay++), QLCNIC_MBX_HOST(ahw, i));
3659 }
3660 }
3661
3662 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *adapter)
3663 {
3664 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3665
3666 if (!mbx)
3667 return;
3668
3669 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3670 complete(&mbx->completion);
3671 cancel_work_sync(&mbx->work);
3672 flush_workqueue(mbx->work_q);
3673 qlcnic_83xx_flush_mbx_queue(adapter);
3674 }
3675
3676 static int qlcnic_83xx_enqueue_mbx_cmd(struct qlcnic_adapter *adapter,
3677 struct qlcnic_cmd_args *cmd,
3678 unsigned long *timeout)
3679 {
3680 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3681
3682 if (test_bit(QLC_83XX_MBX_READY, &mbx->status)) {
3683 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3684 init_completion(&cmd->completion);
3685 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_UNKNOWN;
3686
3687 spin_lock(&mbx->queue_lock);
3688
3689 list_add_tail(&cmd->list, &mbx->cmd_q);
3690 mbx->num_cmds++;
3691 cmd->total_cmds = mbx->num_cmds;
3692 *timeout = cmd->total_cmds * QLC_83XX_MBX_TIMEOUT;
3693 queue_work(mbx->work_q, &mbx->work);
3694
3695 spin_unlock(&mbx->queue_lock);
3696
3697 return 0;
3698 }
3699
3700 return -EBUSY;
3701 }
3702
3703 static int qlcnic_83xx_check_mac_rcode(struct qlcnic_adapter *adapter,
3704 struct qlcnic_cmd_args *cmd)
3705 {
3706 u8 mac_cmd_rcode;
3707 u32 fw_data;
3708
3709 if (cmd->cmd_op == QLCNIC_CMD_CONFIG_MAC_VLAN) {
3710 fw_data = readl(QLCNIC_MBX_FW(adapter->ahw, 2));
3711 mac_cmd_rcode = (u8)fw_data;
3712 if (mac_cmd_rcode == QLC_83XX_NO_NIC_RESOURCE ||
3713 mac_cmd_rcode == QLC_83XX_MAC_PRESENT ||
3714 mac_cmd_rcode == QLC_83XX_MAC_ABSENT) {
3715 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3716 return QLCNIC_RCODE_SUCCESS;
3717 }
3718 }
3719
3720 return -EINVAL;
3721 }
3722
3723 static void qlcnic_83xx_decode_mbx_rsp(struct qlcnic_adapter *adapter,
3724 struct qlcnic_cmd_args *cmd)
3725 {
3726 struct qlcnic_hardware_context *ahw = adapter->ahw;
3727 struct device *dev = &adapter->pdev->dev;
3728 u8 mbx_err_code;
3729 u32 fw_data;
3730
3731 fw_data = readl(QLCNIC_MBX_FW(ahw, 0));
3732 mbx_err_code = QLCNIC_MBX_STATUS(fw_data);
3733 qlcnic_83xx_get_mbx_data(adapter, cmd);
3734
3735 switch (mbx_err_code) {
3736 case QLCNIC_MBX_RSP_OK:
3737 case QLCNIC_MBX_PORT_RSP_OK:
3738 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3739 break;
3740 default:
3741 if (!qlcnic_83xx_check_mac_rcode(adapter, cmd))
3742 break;
3743
3744 dev_err(dev, "%s: Mailbox command failed, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x, error=0x%x\n",
3745 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
3746 ahw->op_mode, mbx_err_code);
3747 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_FAILED;
3748 qlcnic_dump_mbx(adapter, cmd);
3749 }
3750
3751 return;
3752 }
3753
3754 static void qlcnic_83xx_mailbox_worker(struct work_struct *work)
3755 {
3756 struct qlcnic_mailbox *mbx = container_of(work, struct qlcnic_mailbox,
3757 work);
3758 struct qlcnic_adapter *adapter = mbx->adapter;
3759 struct qlcnic_mbx_ops *mbx_ops = mbx->ops;
3760 struct device *dev = &adapter->pdev->dev;
3761 atomic_t *rsp_status = &mbx->rsp_status;
3762 struct list_head *head = &mbx->cmd_q;
3763 struct qlcnic_hardware_context *ahw;
3764 struct qlcnic_cmd_args *cmd = NULL;
3765
3766 ahw = adapter->ahw;
3767
3768 while (true) {
3769 if (qlcnic_83xx_check_mbx_status(adapter)) {
3770 qlcnic_83xx_flush_mbx_queue(adapter);
3771 return;
3772 }
3773
3774 atomic_set(rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3775
3776 spin_lock(&mbx->queue_lock);
3777
3778 if (list_empty(head)) {
3779 spin_unlock(&mbx->queue_lock);
3780 return;
3781 }
3782 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3783
3784 spin_unlock(&mbx->queue_lock);
3785
3786 mbx_ops->encode_cmd(adapter, cmd);
3787 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_REQUEST);
3788
3789 if (wait_for_completion_timeout(&mbx->completion,
3790 QLC_83XX_MBX_TIMEOUT)) {
3791 mbx_ops->decode_resp(adapter, cmd);
3792 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_COMPLETION);
3793 } else {
3794 dev_err(dev, "%s: Mailbox command timeout, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x\n",
3795 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
3796 ahw->op_mode);
3797 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3798 qlcnic_dump_mbx(adapter, cmd);
3799 qlcnic_83xx_idc_request_reset(adapter,
3800 QLCNIC_FORCE_FW_DUMP_KEY);
3801 cmd->rsp_opcode = QLCNIC_RCODE_TIMEOUT;
3802 }
3803 mbx_ops->dequeue_cmd(adapter, cmd);
3804 }
3805 }
3806
3807 static struct qlcnic_mbx_ops qlcnic_83xx_mbx_ops = {
3808 .enqueue_cmd = qlcnic_83xx_enqueue_mbx_cmd,
3809 .dequeue_cmd = qlcnic_83xx_dequeue_mbx_cmd,
3810 .decode_resp = qlcnic_83xx_decode_mbx_rsp,
3811 .encode_cmd = qlcnic_83xx_encode_mbx_cmd,
3812 .nofity_fw = qlcnic_83xx_signal_mbx_cmd,
3813 };
3814
3815 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *adapter)
3816 {
3817 struct qlcnic_hardware_context *ahw = adapter->ahw;
3818 struct qlcnic_mailbox *mbx;
3819
3820 ahw->mailbox = kzalloc(sizeof(*mbx), GFP_KERNEL);
3821 if (!ahw->mailbox)
3822 return -ENOMEM;
3823
3824 mbx = ahw->mailbox;
3825 mbx->ops = &qlcnic_83xx_mbx_ops;
3826 mbx->adapter = adapter;
3827
3828 spin_lock_init(&mbx->queue_lock);
3829 spin_lock_init(&mbx->aen_lock);
3830 INIT_LIST_HEAD(&mbx->cmd_q);
3831 init_completion(&mbx->completion);
3832
3833 mbx->work_q = create_singlethread_workqueue("qlcnic_mailbox");
3834 if (mbx->work_q == NULL) {
3835 kfree(mbx);
3836 return -ENOMEM;
3837 }
3838
3839 INIT_WORK(&mbx->work, qlcnic_83xx_mailbox_worker);
3840 set_bit(QLC_83XX_MBX_READY, &mbx->status);
3841 return 0;
3842 }
3843
3844 pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *pdev,
3845 pci_channel_state_t state)
3846 {
3847 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3848
3849 if (state == pci_channel_io_perm_failure)
3850 return PCI_ERS_RESULT_DISCONNECT;
3851
3852 if (state == pci_channel_io_normal)
3853 return PCI_ERS_RESULT_RECOVERED;
3854
3855 set_bit(__QLCNIC_AER, &adapter->state);
3856 set_bit(__QLCNIC_RESETTING, &adapter->state);
3857
3858 qlcnic_83xx_aer_stop_poll_work(adapter);
3859
3860 pci_save_state(pdev);
3861 pci_disable_device(pdev);
3862
3863 return PCI_ERS_RESULT_NEED_RESET;
3864 }
3865
3866 pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *pdev)
3867 {
3868 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3869 int err = 0;
3870
3871 pdev->error_state = pci_channel_io_normal;
3872 err = pci_enable_device(pdev);
3873 if (err)
3874 goto disconnect;
3875
3876 pci_set_power_state(pdev, PCI_D0);
3877 pci_set_master(pdev);
3878 pci_restore_state(pdev);
3879
3880 err = qlcnic_83xx_aer_reset(adapter);
3881 if (err == 0)
3882 return PCI_ERS_RESULT_RECOVERED;
3883 disconnect:
3884 clear_bit(__QLCNIC_AER, &adapter->state);
3885 clear_bit(__QLCNIC_RESETTING, &adapter->state);
3886 return PCI_ERS_RESULT_DISCONNECT;
3887 }
3888
3889 void qlcnic_83xx_io_resume(struct pci_dev *pdev)
3890 {
3891 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3892
3893 pci_cleanup_aer_uncorrect_error_status(pdev);
3894 if (test_and_clear_bit(__QLCNIC_AER, &adapter->state))
3895 qlcnic_83xx_aer_start_poll_work(adapter);
3896 }
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