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qlcnic: Enable mailbox interface in poll mode when interrupts are not available
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic_83xx_hw.c
1 /*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
8 #include "qlcnic.h"
9 #include "qlcnic_sriov.h"
10 #include <linux/if_vlan.h>
11 #include <linux/ipv6.h>
12 #include <linux/ethtool.h>
13 #include <linux/interrupt.h>
14
15 #define QLCNIC_MAX_TX_QUEUES 1
16 #define RSS_HASHTYPE_IP_TCP 0x3
17 #define QLC_83XX_FW_MBX_CMD 0
18
19 static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = {
20 {QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1},
21 {QLCNIC_CMD_CONFIG_INTRPT, 18, 34},
22 {QLCNIC_CMD_CREATE_RX_CTX, 136, 27},
23 {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
24 {QLCNIC_CMD_CREATE_TX_CTX, 54, 18},
25 {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
26 {QLCNIC_CMD_CONFIGURE_MAC_LEARNING, 2, 1},
27 {QLCNIC_CMD_INTRPT_TEST, 22, 12},
28 {QLCNIC_CMD_SET_MTU, 3, 1},
29 {QLCNIC_CMD_READ_PHY, 4, 2},
30 {QLCNIC_CMD_WRITE_PHY, 5, 1},
31 {QLCNIC_CMD_READ_HW_REG, 4, 1},
32 {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
33 {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
34 {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
35 {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
36 {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
37 {QLCNIC_CMD_GET_PCI_INFO, 1, 66},
38 {QLCNIC_CMD_GET_NIC_INFO, 2, 19},
39 {QLCNIC_CMD_SET_NIC_INFO, 32, 1},
40 {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
41 {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
42 {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
43 {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
44 {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
45 {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
46 {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
47 {QLCNIC_CMD_CONFIG_PORT, 4, 1},
48 {QLCNIC_CMD_TEMP_SIZE, 1, 4},
49 {QLCNIC_CMD_GET_TEMP_HDR, 5, 5},
50 {QLCNIC_CMD_GET_LINK_EVENT, 2, 1},
51 {QLCNIC_CMD_CONFIG_MAC_VLAN, 4, 3},
52 {QLCNIC_CMD_CONFIG_INTR_COAL, 6, 1},
53 {QLCNIC_CMD_CONFIGURE_RSS, 14, 1},
54 {QLCNIC_CMD_CONFIGURE_LED, 2, 1},
55 {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE, 2, 1},
56 {QLCNIC_CMD_CONFIGURE_HW_LRO, 2, 1},
57 {QLCNIC_CMD_GET_STATISTICS, 2, 80},
58 {QLCNIC_CMD_SET_PORT_CONFIG, 2, 1},
59 {QLCNIC_CMD_GET_PORT_CONFIG, 2, 2},
60 {QLCNIC_CMD_GET_LINK_STATUS, 2, 4},
61 {QLCNIC_CMD_IDC_ACK, 5, 1},
62 {QLCNIC_CMD_INIT_NIC_FUNC, 2, 1},
63 {QLCNIC_CMD_STOP_NIC_FUNC, 2, 1},
64 {QLCNIC_CMD_SET_LED_CONFIG, 5, 1},
65 {QLCNIC_CMD_GET_LED_CONFIG, 1, 5},
66 {QLCNIC_CMD_83XX_SET_DRV_VER, 4, 1},
67 {QLCNIC_CMD_ADD_RCV_RINGS, 130, 26},
68 {QLCNIC_CMD_CONFIG_VPORT, 4, 4},
69 {QLCNIC_CMD_BC_EVENT_SETUP, 2, 1},
70 };
71
72 const u32 qlcnic_83xx_ext_reg_tbl[] = {
73 0x38CC, /* Global Reset */
74 0x38F0, /* Wildcard */
75 0x38FC, /* Informant */
76 0x3038, /* Host MBX ctrl */
77 0x303C, /* FW MBX ctrl */
78 0x355C, /* BOOT LOADER ADDRESS REG */
79 0x3560, /* BOOT LOADER SIZE REG */
80 0x3564, /* FW IMAGE ADDR REG */
81 0x1000, /* MBX intr enable */
82 0x1200, /* Default Intr mask */
83 0x1204, /* Default Interrupt ID */
84 0x3780, /* QLC_83XX_IDC_MAJ_VERSION */
85 0x3784, /* QLC_83XX_IDC_DEV_STATE */
86 0x3788, /* QLC_83XX_IDC_DRV_PRESENCE */
87 0x378C, /* QLC_83XX_IDC_DRV_ACK */
88 0x3790, /* QLC_83XX_IDC_CTRL */
89 0x3794, /* QLC_83XX_IDC_DRV_AUDIT */
90 0x3798, /* QLC_83XX_IDC_MIN_VERSION */
91 0x379C, /* QLC_83XX_RECOVER_DRV_LOCK */
92 0x37A0, /* QLC_83XX_IDC_PF_0 */
93 0x37A4, /* QLC_83XX_IDC_PF_1 */
94 0x37A8, /* QLC_83XX_IDC_PF_2 */
95 0x37AC, /* QLC_83XX_IDC_PF_3 */
96 0x37B0, /* QLC_83XX_IDC_PF_4 */
97 0x37B4, /* QLC_83XX_IDC_PF_5 */
98 0x37B8, /* QLC_83XX_IDC_PF_6 */
99 0x37BC, /* QLC_83XX_IDC_PF_7 */
100 0x37C0, /* QLC_83XX_IDC_PF_8 */
101 0x37C4, /* QLC_83XX_IDC_PF_9 */
102 0x37C8, /* QLC_83XX_IDC_PF_10 */
103 0x37CC, /* QLC_83XX_IDC_PF_11 */
104 0x37D0, /* QLC_83XX_IDC_PF_12 */
105 0x37D4, /* QLC_83XX_IDC_PF_13 */
106 0x37D8, /* QLC_83XX_IDC_PF_14 */
107 0x37DC, /* QLC_83XX_IDC_PF_15 */
108 0x37E0, /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */
109 0x37E4, /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */
110 0x37F0, /* QLC_83XX_DRV_OP_MODE */
111 0x37F4, /* QLC_83XX_VNIC_STATE */
112 0x3868, /* QLC_83XX_DRV_LOCK */
113 0x386C, /* QLC_83XX_DRV_UNLOCK */
114 0x3504, /* QLC_83XX_DRV_LOCK_ID */
115 0x34A4, /* QLC_83XX_ASIC_TEMP */
116 };
117
118 const u32 qlcnic_83xx_reg_tbl[] = {
119 0x34A8, /* PEG_HALT_STAT1 */
120 0x34AC, /* PEG_HALT_STAT2 */
121 0x34B0, /* FW_HEARTBEAT */
122 0x3500, /* FLASH LOCK_ID */
123 0x3528, /* FW_CAPABILITIES */
124 0x3538, /* Driver active, DRV_REG0 */
125 0x3540, /* Device state, DRV_REG1 */
126 0x3544, /* Driver state, DRV_REG2 */
127 0x3548, /* Driver scratch, DRV_REG3 */
128 0x354C, /* Device partiton info, DRV_REG4 */
129 0x3524, /* Driver IDC ver, DRV_REG5 */
130 0x3550, /* FW_VER_MAJOR */
131 0x3554, /* FW_VER_MINOR */
132 0x3558, /* FW_VER_SUB */
133 0x359C, /* NPAR STATE */
134 0x35FC, /* FW_IMG_VALID */
135 0x3650, /* CMD_PEG_STATE */
136 0x373C, /* RCV_PEG_STATE */
137 0x37B4, /* ASIC TEMP */
138 0x356C, /* FW API */
139 0x3570, /* DRV OP MODE */
140 0x3850, /* FLASH LOCK */
141 0x3854, /* FLASH UNLOCK */
142 };
143
144 static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = {
145 .read_crb = qlcnic_83xx_read_crb,
146 .write_crb = qlcnic_83xx_write_crb,
147 .read_reg = qlcnic_83xx_rd_reg_indirect,
148 .write_reg = qlcnic_83xx_wrt_reg_indirect,
149 .get_mac_address = qlcnic_83xx_get_mac_address,
150 .setup_intr = qlcnic_83xx_setup_intr,
151 .alloc_mbx_args = qlcnic_83xx_alloc_mbx_args,
152 .mbx_cmd = qlcnic_83xx_issue_cmd,
153 .get_func_no = qlcnic_83xx_get_func_no,
154 .api_lock = qlcnic_83xx_cam_lock,
155 .api_unlock = qlcnic_83xx_cam_unlock,
156 .add_sysfs = qlcnic_83xx_add_sysfs,
157 .remove_sysfs = qlcnic_83xx_remove_sysfs,
158 .process_lb_rcv_ring_diag = qlcnic_83xx_process_rcv_ring_diag,
159 .create_rx_ctx = qlcnic_83xx_create_rx_ctx,
160 .create_tx_ctx = qlcnic_83xx_create_tx_ctx,
161 .del_rx_ctx = qlcnic_83xx_del_rx_ctx,
162 .del_tx_ctx = qlcnic_83xx_del_tx_ctx,
163 .setup_link_event = qlcnic_83xx_setup_link_event,
164 .get_nic_info = qlcnic_83xx_get_nic_info,
165 .get_pci_info = qlcnic_83xx_get_pci_info,
166 .set_nic_info = qlcnic_83xx_set_nic_info,
167 .change_macvlan = qlcnic_83xx_sre_macaddr_change,
168 .napi_enable = qlcnic_83xx_napi_enable,
169 .napi_disable = qlcnic_83xx_napi_disable,
170 .config_intr_coal = qlcnic_83xx_config_intr_coal,
171 .config_rss = qlcnic_83xx_config_rss,
172 .config_hw_lro = qlcnic_83xx_config_hw_lro,
173 .config_promisc_mode = qlcnic_83xx_nic_set_promisc,
174 .change_l2_filter = qlcnic_83xx_change_l2_filter,
175 .get_board_info = qlcnic_83xx_get_port_info,
176 .set_mac_filter_count = qlcnic_83xx_set_mac_filter_count,
177 .free_mac_list = qlcnic_82xx_free_mac_list,
178 };
179
180 static struct qlcnic_nic_template qlcnic_83xx_ops = {
181 .config_bridged_mode = qlcnic_config_bridged_mode,
182 .config_led = qlcnic_config_led,
183 .request_reset = qlcnic_83xx_idc_request_reset,
184 .cancel_idc_work = qlcnic_83xx_idc_exit,
185 .napi_add = qlcnic_83xx_napi_add,
186 .napi_del = qlcnic_83xx_napi_del,
187 .config_ipaddr = qlcnic_83xx_config_ipaddr,
188 .clear_legacy_intr = qlcnic_83xx_clear_legacy_intr,
189 .shutdown = qlcnic_83xx_shutdown,
190 .resume = qlcnic_83xx_resume,
191 };
192
193 void qlcnic_83xx_register_map(struct qlcnic_hardware_context *ahw)
194 {
195 ahw->hw_ops = &qlcnic_83xx_hw_ops;
196 ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl;
197 ahw->ext_reg_tbl = (u32 *)qlcnic_83xx_ext_reg_tbl;
198 }
199
200 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *adapter)
201 {
202 u32 fw_major, fw_minor, fw_build;
203 struct pci_dev *pdev = adapter->pdev;
204
205 fw_major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
206 fw_minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
207 fw_build = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
208 adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build);
209
210 dev_info(&pdev->dev, "Driver v%s, firmware version %d.%d.%d\n",
211 QLCNIC_LINUX_VERSIONID, fw_major, fw_minor, fw_build);
212
213 return adapter->fw_version;
214 }
215
216 static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr)
217 {
218 void __iomem *base;
219 u32 val;
220
221 base = adapter->ahw->pci_base0 +
222 QLC_83XX_CRB_WIN_FUNC(adapter->ahw->pci_func);
223 writel(addr, base);
224 val = readl(base);
225 if (val != addr)
226 return -EIO;
227
228 return 0;
229 }
230
231 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr)
232 {
233 int ret;
234 struct qlcnic_hardware_context *ahw = adapter->ahw;
235
236 ret = __qlcnic_set_win_base(adapter, (u32) addr);
237 if (!ret) {
238 return QLCRDX(ahw, QLCNIC_WILDCARD);
239 } else {
240 dev_err(&adapter->pdev->dev,
241 "%s failed, addr = 0x%x\n", __func__, (int)addr);
242 return -EIO;
243 }
244 }
245
246 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
247 u32 data)
248 {
249 int err;
250 struct qlcnic_hardware_context *ahw = adapter->ahw;
251
252 err = __qlcnic_set_win_base(adapter, (u32) addr);
253 if (!err) {
254 QLCWRX(ahw, QLCNIC_WILDCARD, data);
255 return 0;
256 } else {
257 dev_err(&adapter->pdev->dev,
258 "%s failed, addr = 0x%x data = 0x%x\n",
259 __func__, (int)addr, data);
260 return err;
261 }
262 }
263
264 int qlcnic_83xx_setup_intr(struct qlcnic_adapter *adapter, u8 num_intr)
265 {
266 int err, i, num_msix;
267 struct qlcnic_hardware_context *ahw = adapter->ahw;
268
269 if (!num_intr)
270 num_intr = QLCNIC_DEF_NUM_STS_DESC_RINGS;
271 num_msix = rounddown_pow_of_two(min_t(int, num_online_cpus(),
272 num_intr));
273 /* account for AEN interrupt MSI-X based interrupts */
274 num_msix += 1;
275
276 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
277 num_msix += adapter->max_drv_tx_rings;
278
279 err = qlcnic_enable_msix(adapter, num_msix);
280 if (err == -ENOMEM)
281 return err;
282 if (adapter->flags & QLCNIC_MSIX_ENABLED)
283 num_msix = adapter->ahw->num_msix;
284 else {
285 if (qlcnic_sriov_vf_check(adapter))
286 return -EINVAL;
287 num_msix = 1;
288 }
289 /* setup interrupt mapping table for fw */
290 ahw->intr_tbl = vzalloc(num_msix *
291 sizeof(struct qlcnic_intrpt_config));
292 if (!ahw->intr_tbl)
293 return -ENOMEM;
294 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
295 /* MSI-X enablement failed, use legacy interrupt */
296 adapter->tgt_status_reg = ahw->pci_base0 + QLC_83XX_INTX_PTR;
297 adapter->tgt_mask_reg = ahw->pci_base0 + QLC_83XX_INTX_MASK;
298 adapter->isr_int_vec = ahw->pci_base0 + QLC_83XX_INTX_TRGR;
299 adapter->msix_entries[0].vector = adapter->pdev->irq;
300 dev_info(&adapter->pdev->dev, "using legacy interrupt\n");
301 }
302
303 for (i = 0; i < num_msix; i++) {
304 if (adapter->flags & QLCNIC_MSIX_ENABLED)
305 ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX;
306 else
307 ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX;
308 ahw->intr_tbl[i].id = i;
309 ahw->intr_tbl[i].src = 0;
310 }
311 return 0;
312 }
313
314 inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter)
315 {
316 writel(0, adapter->tgt_mask_reg);
317 }
318
319 inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter *adapter)
320 {
321 writel(1, adapter->tgt_mask_reg);
322 }
323
324 /* Enable MSI-x and INT-x interrupts */
325 void qlcnic_83xx_enable_intr(struct qlcnic_adapter *adapter,
326 struct qlcnic_host_sds_ring *sds_ring)
327 {
328 writel(0, sds_ring->crb_intr_mask);
329 }
330
331 /* Disable MSI-x and INT-x interrupts */
332 void qlcnic_83xx_disable_intr(struct qlcnic_adapter *adapter,
333 struct qlcnic_host_sds_ring *sds_ring)
334 {
335 writel(1, sds_ring->crb_intr_mask);
336 }
337
338 inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
339 *adapter)
340 {
341 u32 mask;
342
343 /* Mailbox in MSI-x mode and Legacy Interrupt share the same
344 * source register. We could be here before contexts are created
345 * and sds_ring->crb_intr_mask has not been initialized, calculate
346 * BAR offset for Interrupt Source Register
347 */
348 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
349 writel(0, adapter->ahw->pci_base0 + mask);
350 }
351
352 void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter)
353 {
354 u32 mask;
355
356 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
357 writel(1, adapter->ahw->pci_base0 + mask);
358 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0);
359 }
360
361 static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter,
362 struct qlcnic_cmd_args *cmd)
363 {
364 int i;
365
366 if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
367 return;
368
369 for (i = 0; i < cmd->rsp.num; i++)
370 cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i));
371 }
372
373 irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter)
374 {
375 u32 intr_val;
376 struct qlcnic_hardware_context *ahw = adapter->ahw;
377 int retries = 0;
378
379 intr_val = readl(adapter->tgt_status_reg);
380
381 if (!QLC_83XX_VALID_INTX_BIT31(intr_val))
382 return IRQ_NONE;
383
384 if (QLC_83XX_INTX_FUNC(intr_val) != adapter->ahw->pci_func) {
385 adapter->stats.spurious_intr++;
386 return IRQ_NONE;
387 }
388 /* The barrier is required to ensure writes to the registers */
389 wmb();
390
391 /* clear the interrupt trigger control register */
392 writel(0, adapter->isr_int_vec);
393 intr_val = readl(adapter->isr_int_vec);
394 do {
395 intr_val = readl(adapter->tgt_status_reg);
396 if (QLC_83XX_INTX_FUNC(intr_val) != ahw->pci_func)
397 break;
398 retries++;
399 } while (QLC_83XX_VALID_INTX_BIT30(intr_val) &&
400 (retries < QLC_83XX_LEGACY_INTX_MAX_RETRY));
401
402 return IRQ_HANDLED;
403 }
404
405 static inline void qlcnic_83xx_notify_mbx_response(struct qlcnic_mailbox *mbx)
406 {
407 atomic_set(&mbx->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
408 complete(&mbx->completion);
409 }
410
411 static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter *adapter)
412 {
413 u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
414 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
415 unsigned long flags;
416
417 spin_lock_irqsave(&mbx->aen_lock, flags);
418 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
419 if (!(resp & QLCNIC_SET_OWNER))
420 goto out;
421
422 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
423 if (event & QLCNIC_MBX_ASYNC_EVENT) {
424 __qlcnic_83xx_process_aen(adapter);
425 } else {
426 if (atomic_read(&mbx->rsp_status) != rsp_status)
427 qlcnic_83xx_notify_mbx_response(mbx);
428 }
429 out:
430 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
431 spin_unlock_irqrestore(&mbx->aen_lock, flags);
432 }
433
434 irqreturn_t qlcnic_83xx_intr(int irq, void *data)
435 {
436 struct qlcnic_adapter *adapter = data;
437 struct qlcnic_host_sds_ring *sds_ring;
438 struct qlcnic_hardware_context *ahw = adapter->ahw;
439
440 if (qlcnic_83xx_clear_legacy_intr(adapter) == IRQ_NONE)
441 return IRQ_NONE;
442
443 qlcnic_83xx_poll_process_aen(adapter);
444
445 if (ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
446 ahw->diag_cnt++;
447 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
448 return IRQ_HANDLED;
449 }
450
451 if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
452 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
453 } else {
454 sds_ring = &adapter->recv_ctx->sds_rings[0];
455 napi_schedule(&sds_ring->napi);
456 }
457
458 return IRQ_HANDLED;
459 }
460
461 irqreturn_t qlcnic_83xx_tmp_intr(int irq, void *data)
462 {
463 struct qlcnic_host_sds_ring *sds_ring = data;
464 struct qlcnic_adapter *adapter = sds_ring->adapter;
465
466 if (adapter->flags & QLCNIC_MSIX_ENABLED)
467 goto done;
468
469 if (adapter->nic_ops->clear_legacy_intr(adapter) == IRQ_NONE)
470 return IRQ_NONE;
471
472 done:
473 adapter->ahw->diag_cnt++;
474 qlcnic_83xx_enable_intr(adapter, sds_ring);
475
476 return IRQ_HANDLED;
477 }
478
479 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *adapter)
480 {
481 u32 num_msix;
482
483 if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
484 qlcnic_83xx_set_legacy_intr_mask(adapter);
485
486 qlcnic_83xx_disable_mbx_intr(adapter);
487
488 if (adapter->flags & QLCNIC_MSIX_ENABLED)
489 num_msix = adapter->ahw->num_msix - 1;
490 else
491 num_msix = 0;
492
493 msleep(20);
494 synchronize_irq(adapter->msix_entries[num_msix].vector);
495 free_irq(adapter->msix_entries[num_msix].vector, adapter);
496 }
497
498 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *adapter)
499 {
500 irq_handler_t handler;
501 u32 val;
502 int err = 0;
503 unsigned long flags = 0;
504
505 if (!(adapter->flags & QLCNIC_MSI_ENABLED) &&
506 !(adapter->flags & QLCNIC_MSIX_ENABLED))
507 flags |= IRQF_SHARED;
508
509 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
510 handler = qlcnic_83xx_handle_aen;
511 val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector;
512 err = request_irq(val, handler, flags, "qlcnic-MB", adapter);
513 if (err) {
514 dev_err(&adapter->pdev->dev,
515 "failed to register MBX interrupt\n");
516 return err;
517 }
518 } else {
519 handler = qlcnic_83xx_intr;
520 val = adapter->msix_entries[0].vector;
521 err = request_irq(val, handler, flags, "qlcnic", adapter);
522 if (err) {
523 dev_err(&adapter->pdev->dev,
524 "failed to register INTx interrupt\n");
525 return err;
526 }
527 qlcnic_83xx_clear_legacy_intr_mask(adapter);
528 }
529
530 /* Enable mailbox interrupt */
531 qlcnic_83xx_enable_mbx_interrupt(adapter);
532
533 return err;
534 }
535
536 void qlcnic_83xx_get_func_no(struct qlcnic_adapter *adapter)
537 {
538 u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT);
539 adapter->ahw->pci_func = (val >> 24) & 0xff;
540 }
541
542 int qlcnic_83xx_cam_lock(struct qlcnic_adapter *adapter)
543 {
544 void __iomem *addr;
545 u32 val, limit = 0;
546
547 struct qlcnic_hardware_context *ahw = adapter->ahw;
548
549 addr = ahw->pci_base0 + QLC_83XX_SEM_LOCK_FUNC(ahw->pci_func);
550 do {
551 val = readl(addr);
552 if (val) {
553 /* write the function number to register */
554 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER,
555 ahw->pci_func);
556 return 0;
557 }
558 usleep_range(1000, 2000);
559 } while (++limit <= QLCNIC_PCIE_SEM_TIMEOUT);
560
561 return -EIO;
562 }
563
564 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter)
565 {
566 void __iomem *addr;
567 u32 val;
568 struct qlcnic_hardware_context *ahw = adapter->ahw;
569
570 addr = ahw->pci_base0 + QLC_83XX_SEM_UNLOCK_FUNC(ahw->pci_func);
571 val = readl(addr);
572 }
573
574 void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
575 loff_t offset, size_t size)
576 {
577 int ret;
578 u32 data;
579
580 if (qlcnic_api_lock(adapter)) {
581 dev_err(&adapter->pdev->dev,
582 "%s: failed to acquire lock. addr offset 0x%x\n",
583 __func__, (u32)offset);
584 return;
585 }
586
587 ret = qlcnic_83xx_rd_reg_indirect(adapter, (u32) offset);
588 qlcnic_api_unlock(adapter);
589
590 if (ret == -EIO) {
591 dev_err(&adapter->pdev->dev,
592 "%s: failed. addr offset 0x%x\n",
593 __func__, (u32)offset);
594 return;
595 }
596 data = ret;
597 memcpy(buf, &data, size);
598 }
599
600 void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
601 loff_t offset, size_t size)
602 {
603 u32 data;
604
605 memcpy(&data, buf, size);
606 qlcnic_83xx_wrt_reg_indirect(adapter, (u32) offset, data);
607 }
608
609 int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter)
610 {
611 int status;
612
613 status = qlcnic_83xx_get_port_config(adapter);
614 if (status) {
615 dev_err(&adapter->pdev->dev,
616 "Get Port Info failed\n");
617 } else {
618 if (QLC_83XX_SFP_10G_CAPABLE(adapter->ahw->port_config))
619 adapter->ahw->port_type = QLCNIC_XGBE;
620 else
621 adapter->ahw->port_type = QLCNIC_GBE;
622
623 if (QLC_83XX_AUTONEG(adapter->ahw->port_config))
624 adapter->ahw->link_autoneg = AUTONEG_ENABLE;
625 }
626 return status;
627 }
628
629 void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *adapter)
630 {
631 struct qlcnic_hardware_context *ahw = adapter->ahw;
632 u16 act_pci_fn = ahw->act_pci_func;
633 u16 count;
634
635 ahw->max_mc_count = QLC_83XX_MAX_MC_COUNT;
636 if (act_pci_fn <= 2)
637 count = (QLC_83XX_MAX_UC_COUNT - QLC_83XX_MAX_MC_COUNT) /
638 act_pci_fn;
639 else
640 count = (QLC_83XX_LB_MAX_FILTERS - QLC_83XX_MAX_MC_COUNT) /
641 act_pci_fn;
642 ahw->max_uc_count = count;
643 }
644
645 void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *adapter)
646 {
647 u32 val;
648
649 if (adapter->flags & QLCNIC_MSIX_ENABLED)
650 val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8);
651 else
652 val = BIT_2;
653
654 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val);
655 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
656 }
657
658 void qlcnic_83xx_check_vf(struct qlcnic_adapter *adapter,
659 const struct pci_device_id *ent)
660 {
661 u32 op_mode, priv_level;
662 struct qlcnic_hardware_context *ahw = adapter->ahw;
663
664 ahw->fw_hal_version = 2;
665 qlcnic_get_func_no(adapter);
666
667 if (qlcnic_sriov_vf_check(adapter)) {
668 qlcnic_sriov_vf_set_ops(adapter);
669 return;
670 }
671
672 /* Determine function privilege level */
673 op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE);
674 if (op_mode == QLC_83XX_DEFAULT_OPMODE)
675 priv_level = QLCNIC_MGMT_FUNC;
676 else
677 priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode,
678 ahw->pci_func);
679
680 if (priv_level == QLCNIC_NON_PRIV_FUNC) {
681 ahw->op_mode = QLCNIC_NON_PRIV_FUNC;
682 dev_info(&adapter->pdev->dev,
683 "HAL Version: %d Non Privileged function\n",
684 ahw->fw_hal_version);
685 adapter->nic_ops = &qlcnic_vf_ops;
686 } else {
687 if (pci_find_ext_capability(adapter->pdev,
688 PCI_EXT_CAP_ID_SRIOV))
689 set_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state);
690 adapter->nic_ops = &qlcnic_83xx_ops;
691 }
692 }
693
694 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
695 u32 data[]);
696 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
697 u32 data[]);
698
699 static void qlcnic_dump_mbx(struct qlcnic_adapter *adapter,
700 struct qlcnic_cmd_args *cmd)
701 {
702 int i;
703
704 if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
705 return;
706
707 dev_info(&adapter->pdev->dev,
708 "Host MBX regs(%d)\n", cmd->req.num);
709 for (i = 0; i < cmd->req.num; i++) {
710 if (i && !(i % 8))
711 pr_info("\n");
712 pr_info("%08x ", cmd->req.arg[i]);
713 }
714 pr_info("\n");
715 dev_info(&adapter->pdev->dev,
716 "FW MBX regs(%d)\n", cmd->rsp.num);
717 for (i = 0; i < cmd->rsp.num; i++) {
718 if (i && !(i % 8))
719 pr_info("\n");
720 pr_info("%08x ", cmd->rsp.arg[i]);
721 }
722 pr_info("\n");
723 }
724
725 static inline void
726 qlcnic_83xx_poll_for_mbx_completion(struct qlcnic_adapter *adapter,
727 struct qlcnic_cmd_args *cmd)
728 {
729 struct qlcnic_hardware_context *ahw = adapter->ahw;
730 int opcode = LSW(cmd->req.arg[0]);
731 unsigned long max_loops;
732
733 max_loops = cmd->total_cmds * QLC_83XX_MBX_CMD_LOOP;
734
735 for (; max_loops; max_loops--) {
736 if (atomic_read(&cmd->rsp_status) ==
737 QLC_83XX_MBX_RESPONSE_ARRIVED)
738 return;
739
740 udelay(1);
741 }
742
743 dev_err(&adapter->pdev->dev,
744 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
745 __func__, opcode, cmd->type, ahw->pci_func, ahw->op_mode);
746 flush_workqueue(ahw->mailbox->work_q);
747 return;
748 }
749
750 int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *adapter,
751 struct qlcnic_cmd_args *cmd)
752 {
753 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
754 struct qlcnic_hardware_context *ahw = adapter->ahw;
755 int cmd_type, err, opcode;
756 unsigned long timeout;
757
758 opcode = LSW(cmd->req.arg[0]);
759 cmd_type = cmd->type;
760 err = mbx->ops->enqueue_cmd(adapter, cmd, &timeout);
761 if (err) {
762 dev_err(&adapter->pdev->dev,
763 "%s: Mailbox not available, cmd_op=0x%x, cmd_context=0x%x, pci_func=0x%x, op_mode=0x%x\n",
764 __func__, opcode, cmd->type, ahw->pci_func,
765 ahw->op_mode);
766 return err;
767 }
768
769 switch (cmd_type) {
770 case QLC_83XX_MBX_CMD_WAIT:
771 if (!wait_for_completion_timeout(&cmd->completion, timeout)) {
772 dev_err(&adapter->pdev->dev,
773 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
774 __func__, opcode, cmd_type, ahw->pci_func,
775 ahw->op_mode);
776 flush_workqueue(mbx->work_q);
777 }
778 break;
779 case QLC_83XX_MBX_CMD_NO_WAIT:
780 return 0;
781 case QLC_83XX_MBX_CMD_BUSY_WAIT:
782 qlcnic_83xx_poll_for_mbx_completion(adapter, cmd);
783 break;
784 default:
785 dev_err(&adapter->pdev->dev,
786 "%s: Invalid mailbox command, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
787 __func__, opcode, cmd_type, ahw->pci_func,
788 ahw->op_mode);
789 qlcnic_83xx_detach_mailbox_work(adapter);
790 }
791
792 return cmd->rsp_opcode;
793 }
794
795 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
796 struct qlcnic_adapter *adapter, u32 type)
797 {
798 int i, size;
799 u32 temp;
800 const struct qlcnic_mailbox_metadata *mbx_tbl;
801
802 memset(mbx, 0, sizeof(struct qlcnic_cmd_args));
803 mbx_tbl = qlcnic_83xx_mbx_tbl;
804 size = ARRAY_SIZE(qlcnic_83xx_mbx_tbl);
805 for (i = 0; i < size; i++) {
806 if (type == mbx_tbl[i].cmd) {
807 mbx->op_type = QLC_83XX_FW_MBX_CMD;
808 mbx->req.num = mbx_tbl[i].in_args;
809 mbx->rsp.num = mbx_tbl[i].out_args;
810 mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
811 GFP_ATOMIC);
812 if (!mbx->req.arg)
813 return -ENOMEM;
814 mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
815 GFP_ATOMIC);
816 if (!mbx->rsp.arg) {
817 kfree(mbx->req.arg);
818 mbx->req.arg = NULL;
819 return -ENOMEM;
820 }
821 memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
822 memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
823 temp = adapter->ahw->fw_hal_version << 29;
824 mbx->req.arg[0] = (type | (mbx->req.num << 16) | temp);
825 mbx->cmd_op = type;
826 return 0;
827 }
828 }
829 return -EINVAL;
830 }
831
832 void qlcnic_83xx_idc_aen_work(struct work_struct *work)
833 {
834 struct qlcnic_adapter *adapter;
835 struct qlcnic_cmd_args cmd;
836 int i, err = 0;
837
838 adapter = container_of(work, struct qlcnic_adapter, idc_aen_work.work);
839 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_IDC_ACK);
840 if (err)
841 return;
842
843 for (i = 1; i < QLC_83XX_MBX_AEN_CNT; i++)
844 cmd.req.arg[i] = adapter->ahw->mbox_aen[i];
845
846 err = qlcnic_issue_cmd(adapter, &cmd);
847 if (err)
848 dev_info(&adapter->pdev->dev,
849 "%s: Mailbox IDC ACK failed.\n", __func__);
850 qlcnic_free_mbx_args(&cmd);
851 }
852
853 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
854 u32 data[])
855 {
856 dev_dbg(&adapter->pdev->dev, "Completion AEN:0x%x.\n",
857 QLCNIC_MBX_RSP(data[0]));
858 clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status);
859 return;
860 }
861
862 void __qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
863 {
864 u32 event[QLC_83XX_MBX_AEN_CNT];
865 int i;
866 struct qlcnic_hardware_context *ahw = adapter->ahw;
867
868 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
869 event[i] = readl(QLCNIC_MBX_FW(ahw, i));
870
871 switch (QLCNIC_MBX_RSP(event[0])) {
872
873 case QLCNIC_MBX_LINK_EVENT:
874 qlcnic_83xx_handle_link_aen(adapter, event);
875 break;
876 case QLCNIC_MBX_COMP_EVENT:
877 qlcnic_83xx_handle_idc_comp_aen(adapter, event);
878 break;
879 case QLCNIC_MBX_REQUEST_EVENT:
880 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
881 adapter->ahw->mbox_aen[i] = QLCNIC_MBX_RSP(event[i]);
882 queue_delayed_work(adapter->qlcnic_wq,
883 &adapter->idc_aen_work, 0);
884 break;
885 case QLCNIC_MBX_TIME_EXTEND_EVENT:
886 break;
887 case QLCNIC_MBX_BC_EVENT:
888 qlcnic_sriov_handle_bc_event(adapter, event[1]);
889 break;
890 case QLCNIC_MBX_SFP_INSERT_EVENT:
891 dev_info(&adapter->pdev->dev, "SFP+ Insert AEN:0x%x.\n",
892 QLCNIC_MBX_RSP(event[0]));
893 break;
894 case QLCNIC_MBX_SFP_REMOVE_EVENT:
895 dev_info(&adapter->pdev->dev, "SFP Removed AEN:0x%x.\n",
896 QLCNIC_MBX_RSP(event[0]));
897 break;
898 default:
899 dev_dbg(&adapter->pdev->dev, "Unsupported AEN:0x%x.\n",
900 QLCNIC_MBX_RSP(event[0]));
901 break;
902 }
903
904 QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
905 }
906
907 static void qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
908 {
909 u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
910 struct qlcnic_hardware_context *ahw = adapter->ahw;
911 struct qlcnic_mailbox *mbx = ahw->mailbox;
912 unsigned long flags;
913
914 spin_lock_irqsave(&mbx->aen_lock, flags);
915 resp = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL);
916 if (resp & QLCNIC_SET_OWNER) {
917 event = readl(QLCNIC_MBX_FW(ahw, 0));
918 if (event & QLCNIC_MBX_ASYNC_EVENT) {
919 __qlcnic_83xx_process_aen(adapter);
920 } else {
921 if (atomic_read(&mbx->rsp_status) != rsp_status)
922 qlcnic_83xx_notify_mbx_response(mbx);
923 }
924 }
925 spin_unlock_irqrestore(&mbx->aen_lock, flags);
926 }
927
928 static void qlcnic_83xx_mbx_poll_work(struct work_struct *work)
929 {
930 struct qlcnic_adapter *adapter;
931
932 adapter = container_of(work, struct qlcnic_adapter, mbx_poll_work.work);
933
934 if (!test_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
935 return;
936
937 qlcnic_83xx_process_aen(adapter);
938 queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work,
939 (HZ / 10));
940 }
941
942 void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *adapter)
943 {
944 if (test_and_set_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
945 return;
946
947 INIT_DELAYED_WORK(&adapter->mbx_poll_work, qlcnic_83xx_mbx_poll_work);
948 queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work, 0);
949 }
950
951 void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *adapter)
952 {
953 if (!test_and_clear_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
954 return;
955 cancel_delayed_work_sync(&adapter->mbx_poll_work);
956 }
957
958 static int qlcnic_83xx_add_rings(struct qlcnic_adapter *adapter)
959 {
960 int index, i, err, sds_mbx_size;
961 u32 *buf, intrpt_id, intr_mask;
962 u16 context_id;
963 u8 num_sds;
964 struct qlcnic_cmd_args cmd;
965 struct qlcnic_host_sds_ring *sds;
966 struct qlcnic_sds_mbx sds_mbx;
967 struct qlcnic_add_rings_mbx_out *mbx_out;
968 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
969 struct qlcnic_hardware_context *ahw = adapter->ahw;
970
971 sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
972 context_id = recv_ctx->context_id;
973 num_sds = (adapter->max_sds_rings - QLCNIC_MAX_RING_SETS);
974 ahw->hw_ops->alloc_mbx_args(&cmd, adapter,
975 QLCNIC_CMD_ADD_RCV_RINGS);
976 cmd.req.arg[1] = 0 | (num_sds << 8) | (context_id << 16);
977
978 /* set up status rings, mbx 2-81 */
979 index = 2;
980 for (i = 8; i < adapter->max_sds_rings; i++) {
981 memset(&sds_mbx, 0, sds_mbx_size);
982 sds = &recv_ctx->sds_rings[i];
983 sds->consumer = 0;
984 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
985 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
986 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
987 sds_mbx.sds_ring_size = sds->num_desc;
988
989 if (adapter->flags & QLCNIC_MSIX_ENABLED)
990 intrpt_id = ahw->intr_tbl[i].id;
991 else
992 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
993
994 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
995 sds_mbx.intrpt_id = intrpt_id;
996 else
997 sds_mbx.intrpt_id = 0xffff;
998 sds_mbx.intrpt_val = 0;
999 buf = &cmd.req.arg[index];
1000 memcpy(buf, &sds_mbx, sds_mbx_size);
1001 index += sds_mbx_size / sizeof(u32);
1002 }
1003
1004 /* send the mailbox command */
1005 err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1006 if (err) {
1007 dev_err(&adapter->pdev->dev,
1008 "Failed to add rings %d\n", err);
1009 goto out;
1010 }
1011
1012 mbx_out = (struct qlcnic_add_rings_mbx_out *)&cmd.rsp.arg[1];
1013 index = 0;
1014 /* status descriptor ring */
1015 for (i = 8; i < adapter->max_sds_rings; i++) {
1016 sds = &recv_ctx->sds_rings[i];
1017 sds->crb_sts_consumer = ahw->pci_base0 +
1018 mbx_out->host_csmr[index];
1019 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1020 intr_mask = ahw->intr_tbl[i].src;
1021 else
1022 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1023
1024 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1025 index++;
1026 }
1027 out:
1028 qlcnic_free_mbx_args(&cmd);
1029 return err;
1030 }
1031
1032 void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *adapter)
1033 {
1034 int err;
1035 u32 temp = 0;
1036 struct qlcnic_cmd_args cmd;
1037 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1038
1039 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX))
1040 return;
1041
1042 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1043 cmd.req.arg[0] |= (0x3 << 29);
1044
1045 if (qlcnic_sriov_pf_check(adapter))
1046 qlcnic_pf_set_interface_id_del_rx_ctx(adapter, &temp);
1047
1048 cmd.req.arg[1] = recv_ctx->context_id | temp;
1049 err = qlcnic_issue_cmd(adapter, &cmd);
1050 if (err)
1051 dev_err(&adapter->pdev->dev,
1052 "Failed to destroy rx ctx in firmware\n");
1053
1054 recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
1055 qlcnic_free_mbx_args(&cmd);
1056 }
1057
1058 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter)
1059 {
1060 int i, err, index, sds_mbx_size, rds_mbx_size;
1061 u8 num_sds, num_rds;
1062 u32 *buf, intrpt_id, intr_mask, cap = 0;
1063 struct qlcnic_host_sds_ring *sds;
1064 struct qlcnic_host_rds_ring *rds;
1065 struct qlcnic_sds_mbx sds_mbx;
1066 struct qlcnic_rds_mbx rds_mbx;
1067 struct qlcnic_cmd_args cmd;
1068 struct qlcnic_rcv_mbx_out *mbx_out;
1069 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1070 struct qlcnic_hardware_context *ahw = adapter->ahw;
1071 num_rds = adapter->max_rds_rings;
1072
1073 if (adapter->max_sds_rings <= QLCNIC_MAX_RING_SETS)
1074 num_sds = adapter->max_sds_rings;
1075 else
1076 num_sds = QLCNIC_MAX_RING_SETS;
1077
1078 sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1079 rds_mbx_size = sizeof(struct qlcnic_rds_mbx);
1080 cap = QLCNIC_CAP0_LEGACY_CONTEXT;
1081
1082 if (adapter->flags & QLCNIC_FW_LRO_MSS_CAP)
1083 cap |= QLC_83XX_FW_CAP_LRO_MSS;
1084
1085 /* set mailbox hdr and capabilities */
1086 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1087 QLCNIC_CMD_CREATE_RX_CTX);
1088 if (err)
1089 return err;
1090
1091 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1092 cmd.req.arg[0] |= (0x3 << 29);
1093
1094 cmd.req.arg[1] = cap;
1095 cmd.req.arg[5] = 1 | (num_rds << 5) | (num_sds << 8) |
1096 (QLC_83XX_HOST_RDS_MODE_UNIQUE << 16);
1097
1098 if (qlcnic_sriov_pf_check(adapter))
1099 qlcnic_pf_set_interface_id_create_rx_ctx(adapter,
1100 &cmd.req.arg[6]);
1101 /* set up status rings, mbx 8-57/87 */
1102 index = QLC_83XX_HOST_SDS_MBX_IDX;
1103 for (i = 0; i < num_sds; i++) {
1104 memset(&sds_mbx, 0, sds_mbx_size);
1105 sds = &recv_ctx->sds_rings[i];
1106 sds->consumer = 0;
1107 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1108 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1109 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1110 sds_mbx.sds_ring_size = sds->num_desc;
1111 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1112 intrpt_id = ahw->intr_tbl[i].id;
1113 else
1114 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1115 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1116 sds_mbx.intrpt_id = intrpt_id;
1117 else
1118 sds_mbx.intrpt_id = 0xffff;
1119 sds_mbx.intrpt_val = 0;
1120 buf = &cmd.req.arg[index];
1121 memcpy(buf, &sds_mbx, sds_mbx_size);
1122 index += sds_mbx_size / sizeof(u32);
1123 }
1124 /* set up receive rings, mbx 88-111/135 */
1125 index = QLCNIC_HOST_RDS_MBX_IDX;
1126 rds = &recv_ctx->rds_rings[0];
1127 rds->producer = 0;
1128 memset(&rds_mbx, 0, rds_mbx_size);
1129 rds_mbx.phy_addr_reg_low = LSD(rds->phys_addr);
1130 rds_mbx.phy_addr_reg_high = MSD(rds->phys_addr);
1131 rds_mbx.reg_ring_sz = rds->dma_size;
1132 rds_mbx.reg_ring_len = rds->num_desc;
1133 /* Jumbo ring */
1134 rds = &recv_ctx->rds_rings[1];
1135 rds->producer = 0;
1136 rds_mbx.phy_addr_jmb_low = LSD(rds->phys_addr);
1137 rds_mbx.phy_addr_jmb_high = MSD(rds->phys_addr);
1138 rds_mbx.jmb_ring_sz = rds->dma_size;
1139 rds_mbx.jmb_ring_len = rds->num_desc;
1140 buf = &cmd.req.arg[index];
1141 memcpy(buf, &rds_mbx, rds_mbx_size);
1142
1143 /* send the mailbox command */
1144 err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1145 if (err) {
1146 dev_err(&adapter->pdev->dev,
1147 "Failed to create Rx ctx in firmware%d\n", err);
1148 goto out;
1149 }
1150 mbx_out = (struct qlcnic_rcv_mbx_out *)&cmd.rsp.arg[1];
1151 recv_ctx->context_id = mbx_out->ctx_id;
1152 recv_ctx->state = mbx_out->state;
1153 recv_ctx->virt_port = mbx_out->vport_id;
1154 dev_info(&adapter->pdev->dev, "Rx Context[%d] Created, state:0x%x\n",
1155 recv_ctx->context_id, recv_ctx->state);
1156 /* Receive descriptor ring */
1157 /* Standard ring */
1158 rds = &recv_ctx->rds_rings[0];
1159 rds->crb_rcv_producer = ahw->pci_base0 +
1160 mbx_out->host_prod[0].reg_buf;
1161 /* Jumbo ring */
1162 rds = &recv_ctx->rds_rings[1];
1163 rds->crb_rcv_producer = ahw->pci_base0 +
1164 mbx_out->host_prod[0].jmb_buf;
1165 /* status descriptor ring */
1166 for (i = 0; i < num_sds; i++) {
1167 sds = &recv_ctx->sds_rings[i];
1168 sds->crb_sts_consumer = ahw->pci_base0 +
1169 mbx_out->host_csmr[i];
1170 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1171 intr_mask = ahw->intr_tbl[i].src;
1172 else
1173 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1174 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1175 }
1176
1177 if (adapter->max_sds_rings > QLCNIC_MAX_RING_SETS)
1178 err = qlcnic_83xx_add_rings(adapter);
1179 out:
1180 qlcnic_free_mbx_args(&cmd);
1181 return err;
1182 }
1183
1184 void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *adapter,
1185 struct qlcnic_host_tx_ring *tx_ring)
1186 {
1187 struct qlcnic_cmd_args cmd;
1188 u32 temp = 0;
1189
1190 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX))
1191 return;
1192
1193 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1194 cmd.req.arg[0] |= (0x3 << 29);
1195
1196 if (qlcnic_sriov_pf_check(adapter))
1197 qlcnic_pf_set_interface_id_del_tx_ctx(adapter, &temp);
1198
1199 cmd.req.arg[1] = tx_ring->ctx_id | temp;
1200 if (qlcnic_issue_cmd(adapter, &cmd))
1201 dev_err(&adapter->pdev->dev,
1202 "Failed to destroy tx ctx in firmware\n");
1203 qlcnic_free_mbx_args(&cmd);
1204 }
1205
1206 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *adapter,
1207 struct qlcnic_host_tx_ring *tx, int ring)
1208 {
1209 int err;
1210 u16 msix_id;
1211 u32 *buf, intr_mask, temp = 0;
1212 struct qlcnic_cmd_args cmd;
1213 struct qlcnic_tx_mbx mbx;
1214 struct qlcnic_tx_mbx_out *mbx_out;
1215 struct qlcnic_hardware_context *ahw = adapter->ahw;
1216 u32 msix_vector;
1217
1218 /* Reset host resources */
1219 tx->producer = 0;
1220 tx->sw_consumer = 0;
1221 *(tx->hw_consumer) = 0;
1222
1223 memset(&mbx, 0, sizeof(struct qlcnic_tx_mbx));
1224
1225 /* setup mailbox inbox registerss */
1226 mbx.phys_addr_low = LSD(tx->phys_addr);
1227 mbx.phys_addr_high = MSD(tx->phys_addr);
1228 mbx.cnsmr_index_low = LSD(tx->hw_cons_phys_addr);
1229 mbx.cnsmr_index_high = MSD(tx->hw_cons_phys_addr);
1230 mbx.size = tx->num_desc;
1231 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
1232 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
1233 msix_vector = adapter->max_sds_rings + ring;
1234 else
1235 msix_vector = adapter->max_sds_rings - 1;
1236 msix_id = ahw->intr_tbl[msix_vector].id;
1237 } else {
1238 msix_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1239 }
1240
1241 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1242 mbx.intr_id = msix_id;
1243 else
1244 mbx.intr_id = 0xffff;
1245 mbx.src = 0;
1246
1247 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
1248 if (err)
1249 return err;
1250
1251 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1252 cmd.req.arg[0] |= (0x3 << 29);
1253
1254 if (qlcnic_sriov_pf_check(adapter))
1255 qlcnic_pf_set_interface_id_create_tx_ctx(adapter, &temp);
1256
1257 cmd.req.arg[1] = QLCNIC_CAP0_LEGACY_CONTEXT;
1258 cmd.req.arg[5] = QLCNIC_MAX_TX_QUEUES | temp;
1259 buf = &cmd.req.arg[6];
1260 memcpy(buf, &mbx, sizeof(struct qlcnic_tx_mbx));
1261 /* send the mailbox command*/
1262 err = qlcnic_issue_cmd(adapter, &cmd);
1263 if (err) {
1264 dev_err(&adapter->pdev->dev,
1265 "Failed to create Tx ctx in firmware 0x%x\n", err);
1266 goto out;
1267 }
1268 mbx_out = (struct qlcnic_tx_mbx_out *)&cmd.rsp.arg[2];
1269 tx->crb_cmd_producer = ahw->pci_base0 + mbx_out->host_prod;
1270 tx->ctx_id = mbx_out->ctx_id;
1271 if ((adapter->flags & QLCNIC_MSIX_ENABLED) &&
1272 !(adapter->flags & QLCNIC_TX_INTR_SHARED)) {
1273 intr_mask = ahw->intr_tbl[adapter->max_sds_rings + ring].src;
1274 tx->crb_intr_mask = ahw->pci_base0 + intr_mask;
1275 }
1276 dev_info(&adapter->pdev->dev, "Tx Context[0x%x] Created, state:0x%x\n",
1277 tx->ctx_id, mbx_out->state);
1278 out:
1279 qlcnic_free_mbx_args(&cmd);
1280 return err;
1281 }
1282
1283 static int qlcnic_83xx_diag_alloc_res(struct net_device *netdev, int test,
1284 int num_sds_ring)
1285 {
1286 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1287 struct qlcnic_host_sds_ring *sds_ring;
1288 struct qlcnic_host_rds_ring *rds_ring;
1289 u16 adapter_state = adapter->is_up;
1290 u8 ring;
1291 int ret;
1292
1293 netif_device_detach(netdev);
1294
1295 if (netif_running(netdev))
1296 __qlcnic_down(adapter, netdev);
1297
1298 qlcnic_detach(adapter);
1299
1300 adapter->max_sds_rings = 1;
1301 adapter->ahw->diag_test = test;
1302 adapter->ahw->linkup = 0;
1303
1304 ret = qlcnic_attach(adapter);
1305 if (ret) {
1306 netif_device_attach(netdev);
1307 return ret;
1308 }
1309
1310 ret = qlcnic_fw_create_ctx(adapter);
1311 if (ret) {
1312 qlcnic_detach(adapter);
1313 if (adapter_state == QLCNIC_ADAPTER_UP_MAGIC) {
1314 adapter->max_sds_rings = num_sds_ring;
1315 qlcnic_attach(adapter);
1316 }
1317 netif_device_attach(netdev);
1318 return ret;
1319 }
1320
1321 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1322 rds_ring = &adapter->recv_ctx->rds_rings[ring];
1323 qlcnic_post_rx_buffers(adapter, rds_ring, ring);
1324 }
1325
1326 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1327 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
1328 sds_ring = &adapter->recv_ctx->sds_rings[ring];
1329 qlcnic_83xx_enable_intr(adapter, sds_ring);
1330 }
1331 }
1332
1333 if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1334 /* disable and free mailbox interrupt */
1335 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
1336 qlcnic_83xx_enable_mbx_poll(adapter);
1337 qlcnic_83xx_free_mbx_intr(adapter);
1338 }
1339 adapter->ahw->loopback_state = 0;
1340 adapter->ahw->hw_ops->setup_link_event(adapter, 1);
1341 }
1342
1343 set_bit(__QLCNIC_DEV_UP, &adapter->state);
1344 return 0;
1345 }
1346
1347 static void qlcnic_83xx_diag_free_res(struct net_device *netdev,
1348 int max_sds_rings)
1349 {
1350 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1351 struct qlcnic_host_sds_ring *sds_ring;
1352 int ring, err;
1353
1354 clear_bit(__QLCNIC_DEV_UP, &adapter->state);
1355 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1356 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
1357 sds_ring = &adapter->recv_ctx->sds_rings[ring];
1358 qlcnic_83xx_disable_intr(adapter, sds_ring);
1359 if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
1360 qlcnic_83xx_enable_mbx_poll(adapter);
1361 }
1362 }
1363
1364 qlcnic_fw_destroy_ctx(adapter);
1365 qlcnic_detach(adapter);
1366
1367 if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1368 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
1369 err = qlcnic_83xx_setup_mbx_intr(adapter);
1370 qlcnic_83xx_disable_mbx_poll(adapter);
1371 if (err) {
1372 dev_err(&adapter->pdev->dev,
1373 "%s: failed to setup mbx interrupt\n",
1374 __func__);
1375 goto out;
1376 }
1377 }
1378 }
1379 adapter->ahw->diag_test = 0;
1380 adapter->max_sds_rings = max_sds_rings;
1381
1382 if (qlcnic_attach(adapter))
1383 goto out;
1384
1385 if (netif_running(netdev))
1386 __qlcnic_up(adapter, netdev);
1387
1388 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST &&
1389 !(adapter->flags & QLCNIC_MSIX_ENABLED))
1390 qlcnic_83xx_disable_mbx_poll(adapter);
1391 out:
1392 netif_device_attach(netdev);
1393 }
1394
1395 int qlcnic_83xx_config_led(struct qlcnic_adapter *adapter, u32 state,
1396 u32 beacon)
1397 {
1398 struct qlcnic_cmd_args cmd;
1399 u32 mbx_in;
1400 int i, status = 0;
1401
1402 if (state) {
1403 /* Get LED configuration */
1404 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1405 QLCNIC_CMD_GET_LED_CONFIG);
1406 if (status)
1407 return status;
1408
1409 status = qlcnic_issue_cmd(adapter, &cmd);
1410 if (status) {
1411 dev_err(&adapter->pdev->dev,
1412 "Get led config failed.\n");
1413 goto mbx_err;
1414 } else {
1415 for (i = 0; i < 4; i++)
1416 adapter->ahw->mbox_reg[i] = cmd.rsp.arg[i+1];
1417 }
1418 qlcnic_free_mbx_args(&cmd);
1419 /* Set LED Configuration */
1420 mbx_in = (LSW(QLC_83XX_LED_CONFIG) << 16) |
1421 LSW(QLC_83XX_LED_CONFIG);
1422 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1423 QLCNIC_CMD_SET_LED_CONFIG);
1424 if (status)
1425 return status;
1426
1427 cmd.req.arg[1] = mbx_in;
1428 cmd.req.arg[2] = mbx_in;
1429 cmd.req.arg[3] = mbx_in;
1430 if (beacon)
1431 cmd.req.arg[4] = QLC_83XX_ENABLE_BEACON;
1432 status = qlcnic_issue_cmd(adapter, &cmd);
1433 if (status) {
1434 dev_err(&adapter->pdev->dev,
1435 "Set led config failed.\n");
1436 }
1437 mbx_err:
1438 qlcnic_free_mbx_args(&cmd);
1439 return status;
1440
1441 } else {
1442 /* Restoring default LED configuration */
1443 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1444 QLCNIC_CMD_SET_LED_CONFIG);
1445 if (status)
1446 return status;
1447
1448 cmd.req.arg[1] = adapter->ahw->mbox_reg[0];
1449 cmd.req.arg[2] = adapter->ahw->mbox_reg[1];
1450 cmd.req.arg[3] = adapter->ahw->mbox_reg[2];
1451 if (beacon)
1452 cmd.req.arg[4] = adapter->ahw->mbox_reg[3];
1453 status = qlcnic_issue_cmd(adapter, &cmd);
1454 if (status)
1455 dev_err(&adapter->pdev->dev,
1456 "Restoring led config failed.\n");
1457 qlcnic_free_mbx_args(&cmd);
1458 return status;
1459 }
1460 }
1461
1462 int qlcnic_83xx_set_led(struct net_device *netdev,
1463 enum ethtool_phys_id_state state)
1464 {
1465 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1466 int err = -EIO, active = 1;
1467
1468 if (adapter->ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1469 netdev_warn(netdev,
1470 "LED test is not supported in non-privileged mode\n");
1471 return -EOPNOTSUPP;
1472 }
1473
1474 switch (state) {
1475 case ETHTOOL_ID_ACTIVE:
1476 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state))
1477 return -EBUSY;
1478
1479 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1480 break;
1481
1482 err = qlcnic_83xx_config_led(adapter, active, 0);
1483 if (err)
1484 netdev_err(netdev, "Failed to set LED blink state\n");
1485 break;
1486 case ETHTOOL_ID_INACTIVE:
1487 active = 0;
1488
1489 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1490 break;
1491
1492 err = qlcnic_83xx_config_led(adapter, active, 0);
1493 if (err)
1494 netdev_err(netdev, "Failed to reset LED blink state\n");
1495 break;
1496
1497 default:
1498 return -EINVAL;
1499 }
1500
1501 if (!active || err)
1502 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state);
1503
1504 return err;
1505 }
1506
1507 void qlcnic_83xx_register_nic_idc_func(struct qlcnic_adapter *adapter,
1508 int enable)
1509 {
1510 struct qlcnic_cmd_args cmd;
1511 int status;
1512
1513 if (qlcnic_sriov_vf_check(adapter))
1514 return;
1515
1516 if (enable) {
1517 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1518 QLCNIC_CMD_INIT_NIC_FUNC);
1519 if (status)
1520 return;
1521
1522 cmd.req.arg[1] = BIT_0 | BIT_31;
1523 } else {
1524 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1525 QLCNIC_CMD_STOP_NIC_FUNC);
1526 if (status)
1527 return;
1528
1529 cmd.req.arg[1] = BIT_0 | BIT_31;
1530 }
1531 status = qlcnic_issue_cmd(adapter, &cmd);
1532 if (status)
1533 dev_err(&adapter->pdev->dev,
1534 "Failed to %s in NIC IDC function event.\n",
1535 (enable ? "register" : "unregister"));
1536
1537 qlcnic_free_mbx_args(&cmd);
1538 }
1539
1540 int qlcnic_83xx_set_port_config(struct qlcnic_adapter *adapter)
1541 {
1542 struct qlcnic_cmd_args cmd;
1543 int err;
1544
1545 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_PORT_CONFIG);
1546 if (err)
1547 return err;
1548
1549 cmd.req.arg[1] = adapter->ahw->port_config;
1550 err = qlcnic_issue_cmd(adapter, &cmd);
1551 if (err)
1552 dev_info(&adapter->pdev->dev, "Set Port Config failed.\n");
1553 qlcnic_free_mbx_args(&cmd);
1554 return err;
1555 }
1556
1557 int qlcnic_83xx_get_port_config(struct qlcnic_adapter *adapter)
1558 {
1559 struct qlcnic_cmd_args cmd;
1560 int err;
1561
1562 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PORT_CONFIG);
1563 if (err)
1564 return err;
1565
1566 err = qlcnic_issue_cmd(adapter, &cmd);
1567 if (err)
1568 dev_info(&adapter->pdev->dev, "Get Port config failed\n");
1569 else
1570 adapter->ahw->port_config = cmd.rsp.arg[1];
1571 qlcnic_free_mbx_args(&cmd);
1572 return err;
1573 }
1574
1575 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *adapter, int enable)
1576 {
1577 int err;
1578 u32 temp;
1579 struct qlcnic_cmd_args cmd;
1580
1581 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_EVENT);
1582 if (err)
1583 return err;
1584
1585 temp = adapter->recv_ctx->context_id << 16;
1586 cmd.req.arg[1] = (enable ? 1 : 0) | BIT_8 | temp;
1587 err = qlcnic_issue_cmd(adapter, &cmd);
1588 if (err)
1589 dev_info(&adapter->pdev->dev,
1590 "Setup linkevent mailbox failed\n");
1591 qlcnic_free_mbx_args(&cmd);
1592 return err;
1593 }
1594
1595 static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter *adapter,
1596 u32 *interface_id)
1597 {
1598 if (qlcnic_sriov_pf_check(adapter)) {
1599 qlcnic_pf_set_interface_id_promisc(adapter, interface_id);
1600 } else {
1601 if (!qlcnic_sriov_vf_check(adapter))
1602 *interface_id = adapter->recv_ctx->context_id << 16;
1603 }
1604 }
1605
1606 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
1607 {
1608 struct qlcnic_cmd_args *cmd = NULL;
1609 u32 temp = 0;
1610 int err;
1611
1612 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1613 return -EIO;
1614
1615 cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
1616 if (!cmd)
1617 return -ENOMEM;
1618
1619 err = qlcnic_alloc_mbx_args(cmd, adapter,
1620 QLCNIC_CMD_CONFIGURE_MAC_RX_MODE);
1621 if (err)
1622 goto out;
1623
1624 cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
1625 qlcnic_83xx_set_interface_id_promisc(adapter, &temp);
1626 cmd->req.arg[1] = (mode ? 1 : 0) | temp;
1627 err = qlcnic_issue_cmd(adapter, cmd);
1628 if (!err)
1629 return err;
1630
1631 qlcnic_free_mbx_args(cmd);
1632
1633 out:
1634 kfree(cmd);
1635 return err;
1636 }
1637
1638 int qlcnic_83xx_loopback_test(struct net_device *netdev, u8 mode)
1639 {
1640 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1641 struct qlcnic_hardware_context *ahw = adapter->ahw;
1642 int ret = 0, loop = 0, max_sds_rings = adapter->max_sds_rings;
1643
1644 if (ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1645 netdev_warn(netdev,
1646 "Loopback test not supported in non privileged mode\n");
1647 return -ENOTSUPP;
1648 }
1649
1650 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1651 netdev_info(netdev, "Device is resetting\n");
1652 return -EBUSY;
1653 }
1654
1655 if (qlcnic_get_diag_lock(adapter)) {
1656 netdev_info(netdev, "Device is in diagnostics mode\n");
1657 return -EBUSY;
1658 }
1659
1660 netdev_info(netdev, "%s loopback test in progress\n",
1661 mode == QLCNIC_ILB_MODE ? "internal" : "external");
1662
1663 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST,
1664 max_sds_rings);
1665 if (ret)
1666 goto fail_diag_alloc;
1667
1668 ret = qlcnic_83xx_set_lb_mode(adapter, mode);
1669 if (ret)
1670 goto free_diag_res;
1671
1672 /* Poll for link up event before running traffic */
1673 do {
1674 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1675
1676 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1677 netdev_info(netdev,
1678 "Device is resetting, free LB test resources\n");
1679 ret = -EBUSY;
1680 goto free_diag_res;
1681 }
1682 if (loop++ > QLC_83XX_LB_WAIT_COUNT) {
1683 netdev_info(netdev,
1684 "Firmware didn't sent link up event to loopback request\n");
1685 ret = -ETIMEDOUT;
1686 qlcnic_83xx_clear_lb_mode(adapter, mode);
1687 goto free_diag_res;
1688 }
1689 } while ((adapter->ahw->linkup && ahw->has_link_events) != 1);
1690
1691 /* Make sure carrier is off and queue is stopped during loopback */
1692 if (netif_running(netdev)) {
1693 netif_carrier_off(netdev);
1694 netif_stop_queue(netdev);
1695 }
1696
1697 ret = qlcnic_do_lb_test(adapter, mode);
1698
1699 qlcnic_83xx_clear_lb_mode(adapter, mode);
1700
1701 free_diag_res:
1702 qlcnic_83xx_diag_free_res(netdev, max_sds_rings);
1703
1704 fail_diag_alloc:
1705 adapter->max_sds_rings = max_sds_rings;
1706 qlcnic_release_diag_lock(adapter);
1707 return ret;
1708 }
1709
1710 int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1711 {
1712 struct qlcnic_hardware_context *ahw = adapter->ahw;
1713 struct net_device *netdev = adapter->netdev;
1714 int status = 0, loop = 0;
1715 u32 config;
1716
1717 status = qlcnic_83xx_get_port_config(adapter);
1718 if (status)
1719 return status;
1720
1721 config = ahw->port_config;
1722
1723 /* Check if port is already in loopback mode */
1724 if ((config & QLC_83XX_CFG_LOOPBACK_HSS) ||
1725 (config & QLC_83XX_CFG_LOOPBACK_EXT)) {
1726 netdev_err(netdev,
1727 "Port already in Loopback mode.\n");
1728 return -EINPROGRESS;
1729 }
1730
1731 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1732
1733 if (mode == QLCNIC_ILB_MODE)
1734 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_HSS;
1735 if (mode == QLCNIC_ELB_MODE)
1736 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_EXT;
1737
1738 status = qlcnic_83xx_set_port_config(adapter);
1739 if (status) {
1740 netdev_err(netdev,
1741 "Failed to Set Loopback Mode = 0x%x.\n",
1742 ahw->port_config);
1743 ahw->port_config = config;
1744 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1745 return status;
1746 }
1747
1748 /* Wait for Link and IDC Completion AEN */
1749 do {
1750 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1751
1752 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1753 netdev_info(netdev,
1754 "Device is resetting, free LB test resources\n");
1755 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1756 return -EBUSY;
1757 }
1758 if (loop++ > QLC_83XX_LB_WAIT_COUNT) {
1759 netdev_err(netdev,
1760 "Did not receive IDC completion AEN\n");
1761 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1762 qlcnic_83xx_clear_lb_mode(adapter, mode);
1763 return -ETIMEDOUT;
1764 }
1765 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1766
1767 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1768 QLCNIC_MAC_ADD);
1769 return status;
1770 }
1771
1772 int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1773 {
1774 struct qlcnic_hardware_context *ahw = adapter->ahw;
1775 struct net_device *netdev = adapter->netdev;
1776 int status = 0, loop = 0;
1777 u32 config = ahw->port_config;
1778
1779 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1780 if (mode == QLCNIC_ILB_MODE)
1781 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_HSS;
1782 if (mode == QLCNIC_ELB_MODE)
1783 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_EXT;
1784
1785 status = qlcnic_83xx_set_port_config(adapter);
1786 if (status) {
1787 netdev_err(netdev,
1788 "Failed to Clear Loopback Mode = 0x%x.\n",
1789 ahw->port_config);
1790 ahw->port_config = config;
1791 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1792 return status;
1793 }
1794
1795 /* Wait for Link and IDC Completion AEN */
1796 do {
1797 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1798
1799 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1800 netdev_info(netdev,
1801 "Device is resetting, free LB test resources\n");
1802 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1803 return -EBUSY;
1804 }
1805
1806 if (loop++ > QLC_83XX_LB_WAIT_COUNT) {
1807 netdev_err(netdev,
1808 "Did not receive IDC completion AEN\n");
1809 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1810 return -ETIMEDOUT;
1811 }
1812 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1813
1814 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1815 QLCNIC_MAC_DEL);
1816 return status;
1817 }
1818
1819 static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter *adapter,
1820 u32 *interface_id)
1821 {
1822 if (qlcnic_sriov_pf_check(adapter)) {
1823 qlcnic_pf_set_interface_id_ipaddr(adapter, interface_id);
1824 } else {
1825 if (!qlcnic_sriov_vf_check(adapter))
1826 *interface_id = adapter->recv_ctx->context_id << 16;
1827 }
1828 }
1829
1830 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip,
1831 int mode)
1832 {
1833 int err;
1834 u32 temp = 0, temp_ip;
1835 struct qlcnic_cmd_args cmd;
1836
1837 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1838 QLCNIC_CMD_CONFIGURE_IP_ADDR);
1839 if (err)
1840 return;
1841
1842 qlcnic_83xx_set_interface_id_ipaddr(adapter, &temp);
1843
1844 if (mode == QLCNIC_IP_UP)
1845 cmd.req.arg[1] = 1 | temp;
1846 else
1847 cmd.req.arg[1] = 2 | temp;
1848
1849 /*
1850 * Adapter needs IP address in network byte order.
1851 * But hardware mailbox registers go through writel(), hence IP address
1852 * gets swapped on big endian architecture.
1853 * To negate swapping of writel() on big endian architecture
1854 * use swab32(value).
1855 */
1856
1857 temp_ip = swab32(ntohl(ip));
1858 memcpy(&cmd.req.arg[2], &temp_ip, sizeof(u32));
1859 err = qlcnic_issue_cmd(adapter, &cmd);
1860 if (err != QLCNIC_RCODE_SUCCESS)
1861 dev_err(&adapter->netdev->dev,
1862 "could not notify %s IP 0x%x request\n",
1863 (mode == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
1864
1865 qlcnic_free_mbx_args(&cmd);
1866 }
1867
1868 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *adapter, int mode)
1869 {
1870 int err;
1871 u32 temp, arg1;
1872 struct qlcnic_cmd_args cmd;
1873 int lro_bit_mask;
1874
1875 lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0);
1876
1877 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1878 return 0;
1879
1880 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_HW_LRO);
1881 if (err)
1882 return err;
1883
1884 temp = adapter->recv_ctx->context_id << 16;
1885 arg1 = lro_bit_mask | temp;
1886 cmd.req.arg[1] = arg1;
1887
1888 err = qlcnic_issue_cmd(adapter, &cmd);
1889 if (err)
1890 dev_info(&adapter->pdev->dev, "LRO config failed\n");
1891 qlcnic_free_mbx_args(&cmd);
1892
1893 return err;
1894 }
1895
1896 int qlcnic_83xx_config_rss(struct qlcnic_adapter *adapter, int enable)
1897 {
1898 int err;
1899 u32 word;
1900 struct qlcnic_cmd_args cmd;
1901 const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
1902 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
1903 0x255b0ec26d5a56daULL };
1904
1905 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_RSS);
1906 if (err)
1907 return err;
1908 /*
1909 * RSS request:
1910 * bits 3-0: Rsvd
1911 * 5-4: hash_type_ipv4
1912 * 7-6: hash_type_ipv6
1913 * 8: enable
1914 * 9: use indirection table
1915 * 16-31: indirection table mask
1916 */
1917 word = ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
1918 ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
1919 ((u32)(enable & 0x1) << 8) |
1920 ((0x7ULL) << 16);
1921 cmd.req.arg[1] = (adapter->recv_ctx->context_id);
1922 cmd.req.arg[2] = word;
1923 memcpy(&cmd.req.arg[4], key, sizeof(key));
1924
1925 err = qlcnic_issue_cmd(adapter, &cmd);
1926
1927 if (err)
1928 dev_info(&adapter->pdev->dev, "RSS config failed\n");
1929 qlcnic_free_mbx_args(&cmd);
1930
1931 return err;
1932
1933 }
1934
1935 static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter *adapter,
1936 u32 *interface_id)
1937 {
1938 if (qlcnic_sriov_pf_check(adapter)) {
1939 qlcnic_pf_set_interface_id_macaddr(adapter, interface_id);
1940 } else {
1941 if (!qlcnic_sriov_vf_check(adapter))
1942 *interface_id = adapter->recv_ctx->context_id << 16;
1943 }
1944 }
1945
1946 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
1947 u16 vlan_id, u8 op)
1948 {
1949 struct qlcnic_cmd_args *cmd = NULL;
1950 struct qlcnic_macvlan_mbx mv;
1951 u32 *buf, temp = 0;
1952 int err;
1953
1954 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1955 return -EIO;
1956
1957 cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
1958 if (!cmd)
1959 return -ENOMEM;
1960
1961 err = qlcnic_alloc_mbx_args(cmd, adapter, QLCNIC_CMD_CONFIG_MAC_VLAN);
1962 if (err)
1963 goto out;
1964
1965 cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
1966
1967 if (vlan_id)
1968 op = (op == QLCNIC_MAC_ADD || op == QLCNIC_MAC_VLAN_ADD) ?
1969 QLCNIC_MAC_VLAN_ADD : QLCNIC_MAC_VLAN_DEL;
1970
1971 cmd->req.arg[1] = op | (1 << 8);
1972 qlcnic_83xx_set_interface_id_macaddr(adapter, &temp);
1973 cmd->req.arg[1] |= temp;
1974 mv.vlan = vlan_id;
1975 mv.mac_addr0 = addr[0];
1976 mv.mac_addr1 = addr[1];
1977 mv.mac_addr2 = addr[2];
1978 mv.mac_addr3 = addr[3];
1979 mv.mac_addr4 = addr[4];
1980 mv.mac_addr5 = addr[5];
1981 buf = &cmd->req.arg[2];
1982 memcpy(buf, &mv, sizeof(struct qlcnic_macvlan_mbx));
1983 err = qlcnic_issue_cmd(adapter, cmd);
1984 if (!err)
1985 return err;
1986
1987 qlcnic_free_mbx_args(cmd);
1988 out:
1989 kfree(cmd);
1990 return err;
1991 }
1992
1993 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr,
1994 u16 vlan_id)
1995 {
1996 u8 mac[ETH_ALEN];
1997 memcpy(&mac, addr, ETH_ALEN);
1998 qlcnic_83xx_sre_macaddr_change(adapter, mac, vlan_id, QLCNIC_MAC_ADD);
1999 }
2000
2001 void qlcnic_83xx_configure_mac(struct qlcnic_adapter *adapter, u8 *mac,
2002 u8 type, struct qlcnic_cmd_args *cmd)
2003 {
2004 switch (type) {
2005 case QLCNIC_SET_STATION_MAC:
2006 case QLCNIC_SET_FAC_DEF_MAC:
2007 memcpy(&cmd->req.arg[2], mac, sizeof(u32));
2008 memcpy(&cmd->req.arg[3], &mac[4], sizeof(u16));
2009 break;
2010 }
2011 cmd->req.arg[1] = type;
2012 }
2013
2014 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac)
2015 {
2016 int err, i;
2017 struct qlcnic_cmd_args cmd;
2018 u32 mac_low, mac_high;
2019
2020 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
2021 if (err)
2022 return err;
2023
2024 qlcnic_83xx_configure_mac(adapter, mac, QLCNIC_GET_CURRENT_MAC, &cmd);
2025 err = qlcnic_issue_cmd(adapter, &cmd);
2026
2027 if (err == QLCNIC_RCODE_SUCCESS) {
2028 mac_low = cmd.rsp.arg[1];
2029 mac_high = cmd.rsp.arg[2];
2030
2031 for (i = 0; i < 2; i++)
2032 mac[i] = (u8) (mac_high >> ((1 - i) * 8));
2033 for (i = 2; i < 6; i++)
2034 mac[i] = (u8) (mac_low >> ((5 - i) * 8));
2035 } else {
2036 dev_err(&adapter->pdev->dev, "Failed to get mac address%d\n",
2037 err);
2038 err = -EIO;
2039 }
2040 qlcnic_free_mbx_args(&cmd);
2041 return err;
2042 }
2043
2044 void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *adapter)
2045 {
2046 int err;
2047 u16 temp;
2048 struct qlcnic_cmd_args cmd;
2049 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2050
2051 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2052 return;
2053
2054 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
2055 if (err)
2056 return;
2057
2058 if (coal->type == QLCNIC_INTR_COAL_TYPE_RX) {
2059 temp = adapter->recv_ctx->context_id;
2060 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_RX | temp << 16;
2061 temp = coal->rx_time_us;
2062 cmd.req.arg[2] = coal->rx_packets | temp << 16;
2063 } else if (coal->type == QLCNIC_INTR_COAL_TYPE_TX) {
2064 temp = adapter->tx_ring->ctx_id;
2065 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_TX | temp << 16;
2066 temp = coal->tx_time_us;
2067 cmd.req.arg[2] = coal->tx_packets | temp << 16;
2068 }
2069 cmd.req.arg[3] = coal->flag;
2070 err = qlcnic_issue_cmd(adapter, &cmd);
2071 if (err != QLCNIC_RCODE_SUCCESS)
2072 dev_info(&adapter->pdev->dev,
2073 "Failed to send interrupt coalescence parameters\n");
2074 qlcnic_free_mbx_args(&cmd);
2075 }
2076
2077 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
2078 u32 data[])
2079 {
2080 u8 link_status, duplex;
2081 /* link speed */
2082 link_status = LSB(data[3]) & 1;
2083 adapter->ahw->link_speed = MSW(data[2]);
2084 adapter->ahw->link_autoneg = MSB(MSW(data[3]));
2085 adapter->ahw->module_type = MSB(LSW(data[3]));
2086 duplex = LSB(MSW(data[3]));
2087 if (duplex)
2088 adapter->ahw->link_duplex = DUPLEX_FULL;
2089 else
2090 adapter->ahw->link_duplex = DUPLEX_HALF;
2091 adapter->ahw->has_link_events = 1;
2092 qlcnic_advert_link_change(adapter, link_status);
2093 }
2094
2095 irqreturn_t qlcnic_83xx_handle_aen(int irq, void *data)
2096 {
2097 struct qlcnic_adapter *adapter = data;
2098 struct qlcnic_mailbox *mbx;
2099 u32 mask, resp, event;
2100 unsigned long flags;
2101
2102 mbx = adapter->ahw->mailbox;
2103 spin_lock_irqsave(&mbx->aen_lock, flags);
2104 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
2105 if (!(resp & QLCNIC_SET_OWNER))
2106 goto out;
2107
2108 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
2109 if (event & QLCNIC_MBX_ASYNC_EVENT)
2110 __qlcnic_83xx_process_aen(adapter);
2111 else
2112 qlcnic_83xx_notify_mbx_response(mbx);
2113
2114 out:
2115 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
2116 writel(0, adapter->ahw->pci_base0 + mask);
2117 spin_unlock_irqrestore(&mbx->aen_lock, flags);
2118 return IRQ_HANDLED;
2119 }
2120
2121 int qlcnic_enable_eswitch(struct qlcnic_adapter *adapter, u8 port, u8 enable)
2122 {
2123 int err = -EIO;
2124 struct qlcnic_cmd_args cmd;
2125
2126 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2127 dev_err(&adapter->pdev->dev,
2128 "%s: Error, invoked by non management func\n",
2129 __func__);
2130 return err;
2131 }
2132
2133 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_TOGGLE_ESWITCH);
2134 if (err)
2135 return err;
2136
2137 cmd.req.arg[1] = (port & 0xf) | BIT_4;
2138 err = qlcnic_issue_cmd(adapter, &cmd);
2139
2140 if (err != QLCNIC_RCODE_SUCCESS) {
2141 dev_err(&adapter->pdev->dev, "Failed to enable eswitch%d\n",
2142 err);
2143 err = -EIO;
2144 }
2145 qlcnic_free_mbx_args(&cmd);
2146
2147 return err;
2148
2149 }
2150
2151 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *adapter,
2152 struct qlcnic_info *nic)
2153 {
2154 int i, err = -EIO;
2155 struct qlcnic_cmd_args cmd;
2156
2157 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2158 dev_err(&adapter->pdev->dev,
2159 "%s: Error, invoked by non management func\n",
2160 __func__);
2161 return err;
2162 }
2163
2164 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
2165 if (err)
2166 return err;
2167
2168 cmd.req.arg[1] = (nic->pci_func << 16);
2169 cmd.req.arg[2] = 0x1 << 16;
2170 cmd.req.arg[3] = nic->phys_port | (nic->switch_mode << 16);
2171 cmd.req.arg[4] = nic->capabilities;
2172 cmd.req.arg[5] = (nic->max_mac_filters & 0xFF) | ((nic->max_mtu) << 16);
2173 cmd.req.arg[6] = (nic->max_tx_ques) | ((nic->max_rx_ques) << 16);
2174 cmd.req.arg[7] = (nic->min_tx_bw) | ((nic->max_tx_bw) << 16);
2175 for (i = 8; i < 32; i++)
2176 cmd.req.arg[i] = 0;
2177
2178 err = qlcnic_issue_cmd(adapter, &cmd);
2179
2180 if (err != QLCNIC_RCODE_SUCCESS) {
2181 dev_err(&adapter->pdev->dev, "Failed to set nic info%d\n",
2182 err);
2183 err = -EIO;
2184 }
2185
2186 qlcnic_free_mbx_args(&cmd);
2187
2188 return err;
2189 }
2190
2191 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *adapter,
2192 struct qlcnic_info *npar_info, u8 func_id)
2193 {
2194 int err;
2195 u32 temp;
2196 u8 op = 0;
2197 struct qlcnic_cmd_args cmd;
2198 struct qlcnic_hardware_context *ahw = adapter->ahw;
2199
2200 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
2201 if (err)
2202 return err;
2203
2204 if (func_id != ahw->pci_func) {
2205 temp = func_id << 16;
2206 cmd.req.arg[1] = op | BIT_31 | temp;
2207 } else {
2208 cmd.req.arg[1] = ahw->pci_func << 16;
2209 }
2210 err = qlcnic_issue_cmd(adapter, &cmd);
2211 if (err) {
2212 dev_info(&adapter->pdev->dev,
2213 "Failed to get nic info %d\n", err);
2214 goto out;
2215 }
2216
2217 npar_info->op_type = cmd.rsp.arg[1];
2218 npar_info->pci_func = cmd.rsp.arg[2] & 0xFFFF;
2219 npar_info->op_mode = (cmd.rsp.arg[2] & 0xFFFF0000) >> 16;
2220 npar_info->phys_port = cmd.rsp.arg[3] & 0xFFFF;
2221 npar_info->switch_mode = (cmd.rsp.arg[3] & 0xFFFF0000) >> 16;
2222 npar_info->capabilities = cmd.rsp.arg[4];
2223 npar_info->max_mac_filters = cmd.rsp.arg[5] & 0xFF;
2224 npar_info->max_mtu = (cmd.rsp.arg[5] & 0xFFFF0000) >> 16;
2225 npar_info->max_tx_ques = cmd.rsp.arg[6] & 0xFFFF;
2226 npar_info->max_rx_ques = (cmd.rsp.arg[6] & 0xFFFF0000) >> 16;
2227 npar_info->min_tx_bw = cmd.rsp.arg[7] & 0xFFFF;
2228 npar_info->max_tx_bw = (cmd.rsp.arg[7] & 0xFFFF0000) >> 16;
2229 if (cmd.rsp.arg[8] & 0x1)
2230 npar_info->max_bw_reg_offset = (cmd.rsp.arg[8] & 0x7FFE) >> 1;
2231 if (cmd.rsp.arg[8] & 0x10000) {
2232 temp = (cmd.rsp.arg[8] & 0x7FFE0000) >> 17;
2233 npar_info->max_linkspeed_reg_offset = temp;
2234 }
2235 if (npar_info->capabilities & QLCNIC_FW_CAPABILITY_MORE_CAPS)
2236 memcpy(ahw->extra_capability, &cmd.rsp.arg[16],
2237 sizeof(ahw->extra_capability));
2238
2239 out:
2240 qlcnic_free_mbx_args(&cmd);
2241 return err;
2242 }
2243
2244 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *adapter,
2245 struct qlcnic_pci_info *pci_info)
2246 {
2247 struct qlcnic_hardware_context *ahw = adapter->ahw;
2248 struct device *dev = &adapter->pdev->dev;
2249 struct qlcnic_cmd_args cmd;
2250 int i, err = 0, j = 0;
2251 u32 temp;
2252
2253 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
2254 if (err)
2255 return err;
2256
2257 err = qlcnic_issue_cmd(adapter, &cmd);
2258
2259 ahw->act_pci_func = 0;
2260 if (err == QLCNIC_RCODE_SUCCESS) {
2261 ahw->max_pci_func = cmd.rsp.arg[1] & 0xFF;
2262 for (i = 2, j = 0; j < QLCNIC_MAX_PCI_FUNC; j++, pci_info++) {
2263 pci_info->id = cmd.rsp.arg[i] & 0xFFFF;
2264 pci_info->active = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2265 i++;
2266 pci_info->type = cmd.rsp.arg[i] & 0xFFFF;
2267 if (pci_info->type == QLCNIC_TYPE_NIC)
2268 ahw->act_pci_func++;
2269 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2270 pci_info->default_port = temp;
2271 i++;
2272 pci_info->tx_min_bw = cmd.rsp.arg[i] & 0xFFFF;
2273 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2274 pci_info->tx_max_bw = temp;
2275 i = i + 2;
2276 memcpy(pci_info->mac, &cmd.rsp.arg[i], ETH_ALEN - 2);
2277 i++;
2278 memcpy(pci_info->mac + sizeof(u32), &cmd.rsp.arg[i], 2);
2279 i = i + 3;
2280 if (ahw->op_mode == QLCNIC_MGMT_FUNC)
2281 dev_info(dev, "id = %d active = %d type = %d\n"
2282 "\tport = %d min bw = %d max bw = %d\n"
2283 "\tmac_addr = %pM\n", pci_info->id,
2284 pci_info->active, pci_info->type,
2285 pci_info->default_port,
2286 pci_info->tx_min_bw,
2287 pci_info->tx_max_bw, pci_info->mac);
2288 }
2289 if (ahw->op_mode == QLCNIC_MGMT_FUNC)
2290 dev_info(dev, "Max vNIC functions = %d, active vNIC functions = %d\n",
2291 ahw->max_pci_func, ahw->act_pci_func);
2292
2293 } else {
2294 dev_err(dev, "Failed to get PCI Info, error = %d\n", err);
2295 err = -EIO;
2296 }
2297
2298 qlcnic_free_mbx_args(&cmd);
2299
2300 return err;
2301 }
2302
2303 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *adapter, bool op_type)
2304 {
2305 int i, index, err;
2306 u8 max_ints;
2307 u32 val, temp, type;
2308 struct qlcnic_cmd_args cmd;
2309
2310 max_ints = adapter->ahw->num_msix - 1;
2311 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTRPT);
2312 if (err)
2313 return err;
2314
2315 cmd.req.arg[1] = max_ints;
2316
2317 if (qlcnic_sriov_vf_check(adapter))
2318 cmd.req.arg[1] |= (adapter->ahw->pci_func << 8) | BIT_16;
2319
2320 for (i = 0, index = 2; i < max_ints; i++) {
2321 type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
2322 val = type | (adapter->ahw->intr_tbl[i].type << 4);
2323 if (adapter->ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
2324 val |= (adapter->ahw->intr_tbl[i].id << 16);
2325 cmd.req.arg[index++] = val;
2326 }
2327 err = qlcnic_issue_cmd(adapter, &cmd);
2328 if (err) {
2329 dev_err(&adapter->pdev->dev,
2330 "Failed to configure interrupts 0x%x\n", err);
2331 goto out;
2332 }
2333
2334 max_ints = cmd.rsp.arg[1];
2335 for (i = 0, index = 2; i < max_ints; i++, index += 2) {
2336 val = cmd.rsp.arg[index];
2337 if (LSB(val)) {
2338 dev_info(&adapter->pdev->dev,
2339 "Can't configure interrupt %d\n",
2340 adapter->ahw->intr_tbl[i].id);
2341 continue;
2342 }
2343 if (op_type) {
2344 adapter->ahw->intr_tbl[i].id = MSW(val);
2345 adapter->ahw->intr_tbl[i].enabled = 1;
2346 temp = cmd.rsp.arg[index + 1];
2347 adapter->ahw->intr_tbl[i].src = temp;
2348 } else {
2349 adapter->ahw->intr_tbl[i].id = i;
2350 adapter->ahw->intr_tbl[i].enabled = 0;
2351 adapter->ahw->intr_tbl[i].src = 0;
2352 }
2353 }
2354 out:
2355 qlcnic_free_mbx_args(&cmd);
2356 return err;
2357 }
2358
2359 int qlcnic_83xx_lock_flash(struct qlcnic_adapter *adapter)
2360 {
2361 int id, timeout = 0;
2362 u32 status = 0;
2363
2364 while (status == 0) {
2365 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK);
2366 if (status)
2367 break;
2368
2369 if (++timeout >= QLC_83XX_FLASH_LOCK_TIMEOUT) {
2370 id = QLC_SHARED_REG_RD32(adapter,
2371 QLCNIC_FLASH_LOCK_OWNER);
2372 dev_err(&adapter->pdev->dev,
2373 "%s: failed, lock held by %d\n", __func__, id);
2374 return -EIO;
2375 }
2376 usleep_range(1000, 2000);
2377 }
2378
2379 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, adapter->portnum);
2380 return 0;
2381 }
2382
2383 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *adapter)
2384 {
2385 QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK);
2386 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 0xFF);
2387 }
2388
2389 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter,
2390 u32 flash_addr, u8 *p_data,
2391 int count)
2392 {
2393 int i, ret;
2394 u32 word, range, flash_offset, addr = flash_addr;
2395 ulong indirect_add, direct_window;
2396
2397 flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1);
2398 if (addr & 0x3) {
2399 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2400 return -EIO;
2401 }
2402
2403 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_DIRECT_WINDOW,
2404 (addr));
2405
2406 range = flash_offset + (count * sizeof(u32));
2407 /* Check if data is spread across multiple sectors */
2408 if (range > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2409
2410 /* Multi sector read */
2411 for (i = 0; i < count; i++) {
2412 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2413 ret = qlcnic_83xx_rd_reg_indirect(adapter,
2414 indirect_add);
2415 if (ret == -EIO)
2416 return -EIO;
2417
2418 word = ret;
2419 *(u32 *)p_data = word;
2420 p_data = p_data + 4;
2421 addr = addr + 4;
2422 flash_offset = flash_offset + 4;
2423
2424 if (flash_offset > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2425 direct_window = QLC_83XX_FLASH_DIRECT_WINDOW;
2426 /* This write is needed once for each sector */
2427 qlcnic_83xx_wrt_reg_indirect(adapter,
2428 direct_window,
2429 (addr));
2430 flash_offset = 0;
2431 }
2432 }
2433 } else {
2434 /* Single sector read */
2435 for (i = 0; i < count; i++) {
2436 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2437 ret = qlcnic_83xx_rd_reg_indirect(adapter,
2438 indirect_add);
2439 if (ret == -EIO)
2440 return -EIO;
2441
2442 word = ret;
2443 *(u32 *)p_data = word;
2444 p_data = p_data + 4;
2445 addr = addr + 4;
2446 }
2447 }
2448
2449 return 0;
2450 }
2451
2452 static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter)
2453 {
2454 u32 status;
2455 int retries = QLC_83XX_FLASH_READ_RETRY_COUNT;
2456
2457 do {
2458 status = qlcnic_83xx_rd_reg_indirect(adapter,
2459 QLC_83XX_FLASH_STATUS);
2460 if ((status & QLC_83XX_FLASH_STATUS_READY) ==
2461 QLC_83XX_FLASH_STATUS_READY)
2462 break;
2463
2464 msleep(QLC_83XX_FLASH_STATUS_REG_POLL_DELAY);
2465 } while (--retries);
2466
2467 if (!retries)
2468 return -EIO;
2469
2470 return 0;
2471 }
2472
2473 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *adapter)
2474 {
2475 int ret;
2476 u32 cmd;
2477 cmd = adapter->ahw->fdt.write_statusreg_cmd;
2478 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2479 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | cmd));
2480 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2481 adapter->ahw->fdt.write_enable_bits);
2482 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2483 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2484 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2485 if (ret)
2486 return -EIO;
2487
2488 return 0;
2489 }
2490
2491 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *adapter)
2492 {
2493 int ret;
2494
2495 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2496 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG |
2497 adapter->ahw->fdt.write_statusreg_cmd));
2498 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2499 adapter->ahw->fdt.write_disable_bits);
2500 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2501 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2502 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2503 if (ret)
2504 return -EIO;
2505
2506 return 0;
2507 }
2508
2509 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter)
2510 {
2511 int ret, mfg_id;
2512
2513 if (qlcnic_83xx_lock_flash(adapter))
2514 return -EIO;
2515
2516 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2517 QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL);
2518 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2519 QLC_83XX_FLASH_READ_CTRL);
2520 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2521 if (ret) {
2522 qlcnic_83xx_unlock_flash(adapter);
2523 return -EIO;
2524 }
2525
2526 mfg_id = qlcnic_83xx_rd_reg_indirect(adapter, QLC_83XX_FLASH_RDDATA);
2527 if (mfg_id == -EIO)
2528 return -EIO;
2529
2530 adapter->flash_mfg_id = (mfg_id & 0xFF);
2531 qlcnic_83xx_unlock_flash(adapter);
2532
2533 return 0;
2534 }
2535
2536 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *adapter)
2537 {
2538 int count, fdt_size, ret = 0;
2539
2540 fdt_size = sizeof(struct qlcnic_fdt);
2541 count = fdt_size / sizeof(u32);
2542
2543 if (qlcnic_83xx_lock_flash(adapter))
2544 return -EIO;
2545
2546 memset(&adapter->ahw->fdt, 0, fdt_size);
2547 ret = qlcnic_83xx_lockless_flash_read32(adapter, QLCNIC_FDT_LOCATION,
2548 (u8 *)&adapter->ahw->fdt,
2549 count);
2550
2551 qlcnic_83xx_unlock_flash(adapter);
2552 return ret;
2553 }
2554
2555 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *adapter,
2556 u32 sector_start_addr)
2557 {
2558 u32 reversed_addr, addr1, addr2, cmd;
2559 int ret = -EIO;
2560
2561 if (qlcnic_83xx_lock_flash(adapter) != 0)
2562 return -EIO;
2563
2564 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2565 ret = qlcnic_83xx_enable_flash_write(adapter);
2566 if (ret) {
2567 qlcnic_83xx_unlock_flash(adapter);
2568 dev_err(&adapter->pdev->dev,
2569 "%s failed at %d\n",
2570 __func__, __LINE__);
2571 return ret;
2572 }
2573 }
2574
2575 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2576 if (ret) {
2577 qlcnic_83xx_unlock_flash(adapter);
2578 dev_err(&adapter->pdev->dev,
2579 "%s: failed at %d\n", __func__, __LINE__);
2580 return -EIO;
2581 }
2582
2583 addr1 = (sector_start_addr & 0xFF) << 16;
2584 addr2 = (sector_start_addr & 0xFF0000) >> 16;
2585 reversed_addr = addr1 | addr2;
2586
2587 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2588 reversed_addr);
2589 cmd = QLC_83XX_FLASH_FDT_ERASE_DEF_SIG | adapter->ahw->fdt.erase_cmd;
2590 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id)
2591 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, cmd);
2592 else
2593 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2594 QLC_83XX_FLASH_OEM_ERASE_SIG);
2595 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2596 QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2597
2598 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2599 if (ret) {
2600 qlcnic_83xx_unlock_flash(adapter);
2601 dev_err(&adapter->pdev->dev,
2602 "%s: failed at %d\n", __func__, __LINE__);
2603 return -EIO;
2604 }
2605
2606 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2607 ret = qlcnic_83xx_disable_flash_write(adapter);
2608 if (ret) {
2609 qlcnic_83xx_unlock_flash(adapter);
2610 dev_err(&adapter->pdev->dev,
2611 "%s: failed at %d\n", __func__, __LINE__);
2612 return ret;
2613 }
2614 }
2615
2616 qlcnic_83xx_unlock_flash(adapter);
2617
2618 return 0;
2619 }
2620
2621 int qlcnic_83xx_flash_write32(struct qlcnic_adapter *adapter, u32 addr,
2622 u32 *p_data)
2623 {
2624 int ret = -EIO;
2625 u32 addr1 = 0x00800000 | (addr >> 2);
2626
2627 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, addr1);
2628 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data);
2629 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2630 QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2631 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2632 if (ret) {
2633 dev_err(&adapter->pdev->dev,
2634 "%s: failed at %d\n", __func__, __LINE__);
2635 return -EIO;
2636 }
2637
2638 return 0;
2639 }
2640
2641 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr,
2642 u32 *p_data, int count)
2643 {
2644 u32 temp;
2645 int ret = -EIO;
2646
2647 if ((count < QLC_83XX_FLASH_WRITE_MIN) ||
2648 (count > QLC_83XX_FLASH_WRITE_MAX)) {
2649 dev_err(&adapter->pdev->dev,
2650 "%s: Invalid word count\n", __func__);
2651 return -EIO;
2652 }
2653
2654 temp = qlcnic_83xx_rd_reg_indirect(adapter,
2655 QLC_83XX_FLASH_SPI_CONTROL);
2656 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL,
2657 (temp | QLC_83XX_FLASH_SPI_CTRL));
2658 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2659 QLC_83XX_FLASH_ADDR_TEMP_VAL);
2660
2661 /* First DWORD write */
2662 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2663 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2664 QLC_83XX_FLASH_FIRST_MS_PATTERN);
2665 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2666 if (ret) {
2667 dev_err(&adapter->pdev->dev,
2668 "%s: failed at %d\n", __func__, __LINE__);
2669 return -EIO;
2670 }
2671
2672 count--;
2673 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2674 QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL);
2675 /* Second to N-1 DWORD writes */
2676 while (count != 1) {
2677 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2678 *p_data++);
2679 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2680 QLC_83XX_FLASH_SECOND_MS_PATTERN);
2681 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2682 if (ret) {
2683 dev_err(&adapter->pdev->dev,
2684 "%s: failed at %d\n", __func__, __LINE__);
2685 return -EIO;
2686 }
2687 count--;
2688 }
2689
2690 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2691 QLC_83XX_FLASH_ADDR_TEMP_VAL |
2692 (addr >> 2));
2693 /* Last DWORD write */
2694 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2695 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2696 QLC_83XX_FLASH_LAST_MS_PATTERN);
2697 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2698 if (ret) {
2699 dev_err(&adapter->pdev->dev,
2700 "%s: failed at %d\n", __func__, __LINE__);
2701 return -EIO;
2702 }
2703
2704 ret = qlcnic_83xx_rd_reg_indirect(adapter, QLC_83XX_FLASH_SPI_STATUS);
2705 if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) {
2706 dev_err(&adapter->pdev->dev, "%s: failed at %d\n",
2707 __func__, __LINE__);
2708 /* Operation failed, clear error bit */
2709 temp = qlcnic_83xx_rd_reg_indirect(adapter,
2710 QLC_83XX_FLASH_SPI_CONTROL);
2711 qlcnic_83xx_wrt_reg_indirect(adapter,
2712 QLC_83XX_FLASH_SPI_CONTROL,
2713 (temp | QLC_83XX_FLASH_SPI_CTRL));
2714 }
2715
2716 return 0;
2717 }
2718
2719 static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter *adapter)
2720 {
2721 u32 val, id;
2722
2723 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2724
2725 /* Check if recovery need to be performed by the calling function */
2726 if ((val & QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK) == 0) {
2727 val = val & ~0x3F;
2728 val = val | ((adapter->portnum << 2) |
2729 QLC_83XX_NEED_DRV_LOCK_RECOVERY);
2730 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2731 dev_info(&adapter->pdev->dev,
2732 "%s: lock recovery initiated\n", __func__);
2733 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY);
2734 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2735 id = ((val >> 2) & 0xF);
2736 if (id == adapter->portnum) {
2737 val = val & ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK;
2738 val = val | QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS;
2739 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2740 /* Force release the lock */
2741 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2742 /* Clear recovery bits */
2743 val = val & ~0x3F;
2744 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2745 dev_info(&adapter->pdev->dev,
2746 "%s: lock recovery completed\n", __func__);
2747 } else {
2748 dev_info(&adapter->pdev->dev,
2749 "%s: func %d to resume lock recovery process\n",
2750 __func__, id);
2751 }
2752 } else {
2753 dev_info(&adapter->pdev->dev,
2754 "%s: lock recovery initiated by other functions\n",
2755 __func__);
2756 }
2757 }
2758
2759 int qlcnic_83xx_lock_driver(struct qlcnic_adapter *adapter)
2760 {
2761 u32 lock_alive_counter, val, id, i = 0, status = 0, temp = 0;
2762 int max_attempt = 0;
2763
2764 while (status == 0) {
2765 status = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK);
2766 if (status)
2767 break;
2768
2769 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY);
2770 i++;
2771
2772 if (i == 1)
2773 temp = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2774
2775 if (i == QLC_83XX_DRV_LOCK_WAIT_COUNTER) {
2776 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2777 if (val == temp) {
2778 id = val & 0xFF;
2779 dev_info(&adapter->pdev->dev,
2780 "%s: lock to be recovered from %d\n",
2781 __func__, id);
2782 qlcnic_83xx_recover_driver_lock(adapter);
2783 i = 0;
2784 max_attempt++;
2785 } else {
2786 dev_err(&adapter->pdev->dev,
2787 "%s: failed to get lock\n", __func__);
2788 return -EIO;
2789 }
2790 }
2791
2792 /* Force exit from while loop after few attempts */
2793 if (max_attempt == QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT) {
2794 dev_err(&adapter->pdev->dev,
2795 "%s: failed to get lock\n", __func__);
2796 return -EIO;
2797 }
2798 }
2799
2800 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2801 lock_alive_counter = val >> 8;
2802 lock_alive_counter++;
2803 val = lock_alive_counter << 8 | adapter->portnum;
2804 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2805
2806 return 0;
2807 }
2808
2809 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *adapter)
2810 {
2811 u32 val, lock_alive_counter, id;
2812
2813 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2814 id = val & 0xFF;
2815 lock_alive_counter = val >> 8;
2816
2817 if (id != adapter->portnum)
2818 dev_err(&adapter->pdev->dev,
2819 "%s:Warning func %d is unlocking lock owned by %d\n",
2820 __func__, adapter->portnum, id);
2821
2822 val = (lock_alive_counter << 8) | 0xFF;
2823 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2824 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2825 }
2826
2827 int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr,
2828 u32 *data, u32 count)
2829 {
2830 int i, j, ret = 0;
2831 u32 temp;
2832
2833 /* Check alignment */
2834 if (addr & 0xF)
2835 return -EIO;
2836
2837 mutex_lock(&adapter->ahw->mem_lock);
2838 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_HI, 0);
2839
2840 for (i = 0; i < count; i++, addr += 16) {
2841 if (!((ADDR_IN_RANGE(addr, QLCNIC_ADDR_QDR_NET,
2842 QLCNIC_ADDR_QDR_NET_MAX)) ||
2843 (ADDR_IN_RANGE(addr, QLCNIC_ADDR_DDR_NET,
2844 QLCNIC_ADDR_DDR_NET_MAX)))) {
2845 mutex_unlock(&adapter->ahw->mem_lock);
2846 return -EIO;
2847 }
2848
2849 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_LO, addr);
2850 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_LO,
2851 *data++);
2852 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_HI,
2853 *data++);
2854 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_ULO,
2855 *data++);
2856 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_UHI,
2857 *data++);
2858 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2859 QLCNIC_TA_WRITE_ENABLE);
2860 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2861 QLCNIC_TA_WRITE_START);
2862
2863 for (j = 0; j < MAX_CTL_CHECK; j++) {
2864 temp = qlcnic_83xx_rd_reg_indirect(adapter,
2865 QLCNIC_MS_CTRL);
2866 if ((temp & TA_CTL_BUSY) == 0)
2867 break;
2868 }
2869
2870 /* Status check failure */
2871 if (j >= MAX_CTL_CHECK) {
2872 printk_ratelimited(KERN_WARNING
2873 "MS memory write failed\n");
2874 mutex_unlock(&adapter->ahw->mem_lock);
2875 return -EIO;
2876 }
2877 }
2878
2879 mutex_unlock(&adapter->ahw->mem_lock);
2880
2881 return ret;
2882 }
2883
2884 int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr,
2885 u8 *p_data, int count)
2886 {
2887 int i, ret;
2888 u32 word, addr = flash_addr;
2889 ulong indirect_addr;
2890
2891 if (qlcnic_83xx_lock_flash(adapter) != 0)
2892 return -EIO;
2893
2894 if (addr & 0x3) {
2895 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2896 qlcnic_83xx_unlock_flash(adapter);
2897 return -EIO;
2898 }
2899
2900 for (i = 0; i < count; i++) {
2901 if (qlcnic_83xx_wrt_reg_indirect(adapter,
2902 QLC_83XX_FLASH_DIRECT_WINDOW,
2903 (addr))) {
2904 qlcnic_83xx_unlock_flash(adapter);
2905 return -EIO;
2906 }
2907
2908 indirect_addr = QLC_83XX_FLASH_DIRECT_DATA(addr);
2909 ret = qlcnic_83xx_rd_reg_indirect(adapter,
2910 indirect_addr);
2911 if (ret == -EIO)
2912 return -EIO;
2913 word = ret;
2914 *(u32 *)p_data = word;
2915 p_data = p_data + 4;
2916 addr = addr + 4;
2917 }
2918
2919 qlcnic_83xx_unlock_flash(adapter);
2920
2921 return 0;
2922 }
2923
2924 int qlcnic_83xx_test_link(struct qlcnic_adapter *adapter)
2925 {
2926 u8 pci_func;
2927 int err;
2928 u32 config = 0, state;
2929 struct qlcnic_cmd_args cmd;
2930 struct qlcnic_hardware_context *ahw = adapter->ahw;
2931
2932 if (qlcnic_sriov_vf_check(adapter))
2933 pci_func = adapter->portnum;
2934 else
2935 pci_func = ahw->pci_func;
2936
2937 state = readl(ahw->pci_base0 + QLC_83XX_LINK_STATE(pci_func));
2938 if (!QLC_83xx_FUNC_VAL(state, pci_func)) {
2939 dev_info(&adapter->pdev->dev, "link state down\n");
2940 return config;
2941 }
2942
2943 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS);
2944 if (err)
2945 return err;
2946
2947 err = qlcnic_issue_cmd(adapter, &cmd);
2948 if (err) {
2949 dev_info(&adapter->pdev->dev,
2950 "Get Link Status Command failed: 0x%x\n", err);
2951 goto out;
2952 } else {
2953 config = cmd.rsp.arg[1];
2954 switch (QLC_83XX_CURRENT_LINK_SPEED(config)) {
2955 case QLC_83XX_10M_LINK:
2956 ahw->link_speed = SPEED_10;
2957 break;
2958 case QLC_83XX_100M_LINK:
2959 ahw->link_speed = SPEED_100;
2960 break;
2961 case QLC_83XX_1G_LINK:
2962 ahw->link_speed = SPEED_1000;
2963 break;
2964 case QLC_83XX_10G_LINK:
2965 ahw->link_speed = SPEED_10000;
2966 break;
2967 default:
2968 ahw->link_speed = 0;
2969 break;
2970 }
2971 config = cmd.rsp.arg[3];
2972 if (QLC_83XX_SFP_PRESENT(config)) {
2973 switch (ahw->module_type) {
2974 case LINKEVENT_MODULE_OPTICAL_UNKNOWN:
2975 case LINKEVENT_MODULE_OPTICAL_SRLR:
2976 case LINKEVENT_MODULE_OPTICAL_LRM:
2977 case LINKEVENT_MODULE_OPTICAL_SFP_1G:
2978 ahw->supported_type = PORT_FIBRE;
2979 break;
2980 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE:
2981 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN:
2982 case LINKEVENT_MODULE_TWINAX:
2983 ahw->supported_type = PORT_TP;
2984 break;
2985 default:
2986 ahw->supported_type = PORT_OTHER;
2987 }
2988 }
2989 if (config & 1)
2990 err = 1;
2991 }
2992 out:
2993 qlcnic_free_mbx_args(&cmd);
2994 return config;
2995 }
2996
2997 int qlcnic_83xx_get_settings(struct qlcnic_adapter *adapter,
2998 struct ethtool_cmd *ecmd)
2999 {
3000 u32 config = 0;
3001 int status = 0;
3002 struct qlcnic_hardware_context *ahw = adapter->ahw;
3003
3004 /* Get port configuration info */
3005 status = qlcnic_83xx_get_port_info(adapter);
3006 /* Get Link Status related info */
3007 config = qlcnic_83xx_test_link(adapter);
3008 ahw->module_type = QLC_83XX_SFP_MODULE_TYPE(config);
3009 /* hard code until there is a way to get it from flash */
3010 ahw->board_type = QLCNIC_BRDTYPE_83XX_10G;
3011
3012 if (netif_running(adapter->netdev) && ahw->has_link_events) {
3013 ethtool_cmd_speed_set(ecmd, ahw->link_speed);
3014 ecmd->duplex = ahw->link_duplex;
3015 ecmd->autoneg = ahw->link_autoneg;
3016 } else {
3017 ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN);
3018 ecmd->duplex = DUPLEX_UNKNOWN;
3019 ecmd->autoneg = AUTONEG_DISABLE;
3020 }
3021
3022 if (ahw->port_type == QLCNIC_XGBE) {
3023 ecmd->supported = SUPPORTED_1000baseT_Full;
3024 ecmd->advertising = ADVERTISED_1000baseT_Full;
3025 } else {
3026 ecmd->supported = (SUPPORTED_10baseT_Half |
3027 SUPPORTED_10baseT_Full |
3028 SUPPORTED_100baseT_Half |
3029 SUPPORTED_100baseT_Full |
3030 SUPPORTED_1000baseT_Half |
3031 SUPPORTED_1000baseT_Full);
3032 ecmd->advertising = (ADVERTISED_100baseT_Half |
3033 ADVERTISED_100baseT_Full |
3034 ADVERTISED_1000baseT_Half |
3035 ADVERTISED_1000baseT_Full);
3036 }
3037
3038 switch (ahw->supported_type) {
3039 case PORT_FIBRE:
3040 ecmd->supported |= SUPPORTED_FIBRE;
3041 ecmd->advertising |= ADVERTISED_FIBRE;
3042 ecmd->port = PORT_FIBRE;
3043 ecmd->transceiver = XCVR_EXTERNAL;
3044 break;
3045 case PORT_TP:
3046 ecmd->supported |= SUPPORTED_TP;
3047 ecmd->advertising |= ADVERTISED_TP;
3048 ecmd->port = PORT_TP;
3049 ecmd->transceiver = XCVR_INTERNAL;
3050 break;
3051 default:
3052 ecmd->supported |= SUPPORTED_FIBRE;
3053 ecmd->advertising |= ADVERTISED_FIBRE;
3054 ecmd->port = PORT_OTHER;
3055 ecmd->transceiver = XCVR_EXTERNAL;
3056 break;
3057 }
3058 ecmd->phy_address = ahw->physical_port;
3059 return status;
3060 }
3061
3062 int qlcnic_83xx_set_settings(struct qlcnic_adapter *adapter,
3063 struct ethtool_cmd *ecmd)
3064 {
3065 int status = 0;
3066 u32 config = adapter->ahw->port_config;
3067
3068 if (ecmd->autoneg)
3069 adapter->ahw->port_config |= BIT_15;
3070
3071 switch (ethtool_cmd_speed(ecmd)) {
3072 case SPEED_10:
3073 adapter->ahw->port_config |= BIT_8;
3074 break;
3075 case SPEED_100:
3076 adapter->ahw->port_config |= BIT_9;
3077 break;
3078 case SPEED_1000:
3079 adapter->ahw->port_config |= BIT_10;
3080 break;
3081 case SPEED_10000:
3082 adapter->ahw->port_config |= BIT_11;
3083 break;
3084 default:
3085 return -EINVAL;
3086 }
3087
3088 status = qlcnic_83xx_set_port_config(adapter);
3089 if (status) {
3090 dev_info(&adapter->pdev->dev,
3091 "Faild to Set Link Speed and autoneg.\n");
3092 adapter->ahw->port_config = config;
3093 }
3094 return status;
3095 }
3096
3097 static inline u64 *qlcnic_83xx_copy_stats(struct qlcnic_cmd_args *cmd,
3098 u64 *data, int index)
3099 {
3100 u32 low, hi;
3101 u64 val;
3102
3103 low = cmd->rsp.arg[index];
3104 hi = cmd->rsp.arg[index + 1];
3105 val = (((u64) low) | (((u64) hi) << 32));
3106 *data++ = val;
3107 return data;
3108 }
3109
3110 static u64 *qlcnic_83xx_fill_stats(struct qlcnic_adapter *adapter,
3111 struct qlcnic_cmd_args *cmd, u64 *data,
3112 int type, int *ret)
3113 {
3114 int err, k, total_regs;
3115
3116 *ret = 0;
3117 err = qlcnic_issue_cmd(adapter, cmd);
3118 if (err != QLCNIC_RCODE_SUCCESS) {
3119 dev_info(&adapter->pdev->dev,
3120 "Error in get statistics mailbox command\n");
3121 *ret = -EIO;
3122 return data;
3123 }
3124 total_regs = cmd->rsp.num;
3125 switch (type) {
3126 case QLC_83XX_STAT_MAC:
3127 /* fill in MAC tx counters */
3128 for (k = 2; k < 28; k += 2)
3129 data = qlcnic_83xx_copy_stats(cmd, data, k);
3130 /* skip 24 bytes of reserved area */
3131 /* fill in MAC rx counters */
3132 for (k += 6; k < 60; k += 2)
3133 data = qlcnic_83xx_copy_stats(cmd, data, k);
3134 /* skip 24 bytes of reserved area */
3135 /* fill in MAC rx frame stats */
3136 for (k += 6; k < 80; k += 2)
3137 data = qlcnic_83xx_copy_stats(cmd, data, k);
3138 /* fill in eSwitch stats */
3139 for (; k < total_regs; k += 2)
3140 data = qlcnic_83xx_copy_stats(cmd, data, k);
3141 break;
3142 case QLC_83XX_STAT_RX:
3143 for (k = 2; k < 8; k += 2)
3144 data = qlcnic_83xx_copy_stats(cmd, data, k);
3145 /* skip 8 bytes of reserved data */
3146 for (k += 2; k < 24; k += 2)
3147 data = qlcnic_83xx_copy_stats(cmd, data, k);
3148 /* skip 8 bytes containing RE1FBQ error data */
3149 for (k += 2; k < total_regs; k += 2)
3150 data = qlcnic_83xx_copy_stats(cmd, data, k);
3151 break;
3152 case QLC_83XX_STAT_TX:
3153 for (k = 2; k < 10; k += 2)
3154 data = qlcnic_83xx_copy_stats(cmd, data, k);
3155 /* skip 8 bytes of reserved data */
3156 for (k += 2; k < total_regs; k += 2)
3157 data = qlcnic_83xx_copy_stats(cmd, data, k);
3158 break;
3159 default:
3160 dev_warn(&adapter->pdev->dev, "Unknown get statistics mode\n");
3161 *ret = -EIO;
3162 }
3163 return data;
3164 }
3165
3166 void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data)
3167 {
3168 struct qlcnic_cmd_args cmd;
3169 struct net_device *netdev = adapter->netdev;
3170 int ret = 0;
3171
3172 ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_STATISTICS);
3173 if (ret)
3174 return;
3175 /* Get Tx stats */
3176 cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16);
3177 cmd.rsp.num = QLC_83XX_TX_STAT_REGS;
3178 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3179 QLC_83XX_STAT_TX, &ret);
3180 if (ret) {
3181 netdev_err(netdev, "Error getting Tx stats\n");
3182 goto out;
3183 }
3184 /* Get MAC stats */
3185 cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16);
3186 cmd.rsp.num = QLC_83XX_MAC_STAT_REGS;
3187 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3188 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3189 QLC_83XX_STAT_MAC, &ret);
3190 if (ret) {
3191 netdev_err(netdev, "Error getting MAC stats\n");
3192 goto out;
3193 }
3194 /* Get Rx stats */
3195 cmd.req.arg[1] = adapter->recv_ctx->context_id << 16;
3196 cmd.rsp.num = QLC_83XX_RX_STAT_REGS;
3197 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3198 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3199 QLC_83XX_STAT_RX, &ret);
3200 if (ret)
3201 netdev_err(netdev, "Error getting Rx stats\n");
3202 out:
3203 qlcnic_free_mbx_args(&cmd);
3204 }
3205
3206 int qlcnic_83xx_reg_test(struct qlcnic_adapter *adapter)
3207 {
3208 u32 major, minor, sub;
3209
3210 major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
3211 minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
3212 sub = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
3213
3214 if (adapter->fw_version != QLCNIC_VERSION_CODE(major, minor, sub)) {
3215 dev_info(&adapter->pdev->dev, "%s: Reg test failed\n",
3216 __func__);
3217 return 1;
3218 }
3219 return 0;
3220 }
3221
3222 int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *adapter)
3223 {
3224 return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl) *
3225 sizeof(adapter->ahw->ext_reg_tbl)) +
3226 (ARRAY_SIZE(qlcnic_83xx_reg_tbl) +
3227 sizeof(adapter->ahw->reg_tbl));
3228 }
3229
3230 int qlcnic_83xx_get_registers(struct qlcnic_adapter *adapter, u32 *regs_buff)
3231 {
3232 int i, j = 0;
3233
3234 for (i = QLCNIC_DEV_INFO_SIZE + 1;
3235 j < ARRAY_SIZE(qlcnic_83xx_reg_tbl); i++, j++)
3236 regs_buff[i] = QLC_SHARED_REG_RD32(adapter, j);
3237
3238 for (j = 0; j < ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl); j++)
3239 regs_buff[i++] = QLCRDX(adapter->ahw, j);
3240 return i;
3241 }
3242
3243 int qlcnic_83xx_interrupt_test(struct net_device *netdev)
3244 {
3245 struct qlcnic_adapter *adapter = netdev_priv(netdev);
3246 struct qlcnic_hardware_context *ahw = adapter->ahw;
3247 struct qlcnic_cmd_args cmd;
3248 u32 data;
3249 u16 intrpt_id, id;
3250 u8 val;
3251 int ret, max_sds_rings = adapter->max_sds_rings;
3252
3253 if (qlcnic_get_diag_lock(adapter)) {
3254 netdev_info(netdev, "Device in diagnostics mode\n");
3255 return -EBUSY;
3256 }
3257
3258 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_INTERRUPT_TEST,
3259 max_sds_rings);
3260 if (ret)
3261 goto fail_diag_irq;
3262
3263 ahw->diag_cnt = 0;
3264 ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INTRPT_TEST);
3265 if (ret)
3266 goto fail_diag_irq;
3267
3268 if (adapter->flags & QLCNIC_MSIX_ENABLED)
3269 intrpt_id = ahw->intr_tbl[0].id;
3270 else
3271 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
3272
3273 cmd.req.arg[1] = 1;
3274 cmd.req.arg[2] = intrpt_id;
3275 cmd.req.arg[3] = BIT_0;
3276
3277 ret = qlcnic_issue_cmd(adapter, &cmd);
3278 data = cmd.rsp.arg[2];
3279 id = LSW(data);
3280 val = LSB(MSW(data));
3281 if (id != intrpt_id)
3282 dev_info(&adapter->pdev->dev,
3283 "Interrupt generated: 0x%x, requested:0x%x\n",
3284 id, intrpt_id);
3285 if (val)
3286 dev_err(&adapter->pdev->dev,
3287 "Interrupt test error: 0x%x\n", val);
3288 if (ret)
3289 goto done;
3290
3291 msleep(20);
3292 ret = !ahw->diag_cnt;
3293
3294 done:
3295 qlcnic_free_mbx_args(&cmd);
3296 qlcnic_83xx_diag_free_res(netdev, max_sds_rings);
3297
3298 fail_diag_irq:
3299 adapter->max_sds_rings = max_sds_rings;
3300 qlcnic_release_diag_lock(adapter);
3301 return ret;
3302 }
3303
3304 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *adapter,
3305 struct ethtool_pauseparam *pause)
3306 {
3307 struct qlcnic_hardware_context *ahw = adapter->ahw;
3308 int status = 0;
3309 u32 config;
3310
3311 status = qlcnic_83xx_get_port_config(adapter);
3312 if (status) {
3313 dev_err(&adapter->pdev->dev,
3314 "%s: Get Pause Config failed\n", __func__);
3315 return;
3316 }
3317 config = ahw->port_config;
3318 if (config & QLC_83XX_CFG_STD_PAUSE) {
3319 if (config & QLC_83XX_CFG_STD_TX_PAUSE)
3320 pause->tx_pause = 1;
3321 if (config & QLC_83XX_CFG_STD_RX_PAUSE)
3322 pause->rx_pause = 1;
3323 }
3324
3325 if (QLC_83XX_AUTONEG(config))
3326 pause->autoneg = 1;
3327 }
3328
3329 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *adapter,
3330 struct ethtool_pauseparam *pause)
3331 {
3332 struct qlcnic_hardware_context *ahw = adapter->ahw;
3333 int status = 0;
3334 u32 config;
3335
3336 status = qlcnic_83xx_get_port_config(adapter);
3337 if (status) {
3338 dev_err(&adapter->pdev->dev,
3339 "%s: Get Pause Config failed.\n", __func__);
3340 return status;
3341 }
3342 config = ahw->port_config;
3343
3344 if (ahw->port_type == QLCNIC_GBE) {
3345 if (pause->autoneg)
3346 ahw->port_config |= QLC_83XX_ENABLE_AUTONEG;
3347 if (!pause->autoneg)
3348 ahw->port_config &= ~QLC_83XX_ENABLE_AUTONEG;
3349 } else if ((ahw->port_type == QLCNIC_XGBE) && (pause->autoneg)) {
3350 return -EOPNOTSUPP;
3351 }
3352
3353 if (!(config & QLC_83XX_CFG_STD_PAUSE))
3354 ahw->port_config |= QLC_83XX_CFG_STD_PAUSE;
3355
3356 if (pause->rx_pause && pause->tx_pause) {
3357 ahw->port_config |= QLC_83XX_CFG_STD_TX_RX_PAUSE;
3358 } else if (pause->rx_pause && !pause->tx_pause) {
3359 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_PAUSE;
3360 ahw->port_config |= QLC_83XX_CFG_STD_RX_PAUSE;
3361 } else if (pause->tx_pause && !pause->rx_pause) {
3362 ahw->port_config &= ~QLC_83XX_CFG_STD_RX_PAUSE;
3363 ahw->port_config |= QLC_83XX_CFG_STD_TX_PAUSE;
3364 } else if (!pause->rx_pause && !pause->tx_pause) {
3365 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_RX_PAUSE;
3366 }
3367 status = qlcnic_83xx_set_port_config(adapter);
3368 if (status) {
3369 dev_err(&adapter->pdev->dev,
3370 "%s: Set Pause Config failed.\n", __func__);
3371 ahw->port_config = config;
3372 }
3373 return status;
3374 }
3375
3376 static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter)
3377 {
3378 int ret;
3379
3380 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
3381 QLC_83XX_FLASH_OEM_READ_SIG);
3382 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
3383 QLC_83XX_FLASH_READ_CTRL);
3384 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
3385 if (ret)
3386 return -EIO;
3387
3388 ret = qlcnic_83xx_rd_reg_indirect(adapter, QLC_83XX_FLASH_RDDATA);
3389 return ret & 0xFF;
3390 }
3391
3392 int qlcnic_83xx_flash_test(struct qlcnic_adapter *adapter)
3393 {
3394 int status;
3395
3396 status = qlcnic_83xx_read_flash_status_reg(adapter);
3397 if (status == -EIO) {
3398 dev_info(&adapter->pdev->dev, "%s: EEPROM test failed.\n",
3399 __func__);
3400 return 1;
3401 }
3402 return 0;
3403 }
3404
3405 int qlcnic_83xx_shutdown(struct pci_dev *pdev)
3406 {
3407 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3408 struct net_device *netdev = adapter->netdev;
3409 int retval;
3410
3411 netif_device_detach(netdev);
3412 qlcnic_cancel_idc_work(adapter);
3413
3414 if (netif_running(netdev))
3415 qlcnic_down(adapter, netdev);
3416
3417 qlcnic_83xx_disable_mbx_intr(adapter);
3418 cancel_delayed_work_sync(&adapter->idc_aen_work);
3419
3420 retval = pci_save_state(pdev);
3421 if (retval)
3422 return retval;
3423
3424 return 0;
3425 }
3426
3427 int qlcnic_83xx_resume(struct qlcnic_adapter *adapter)
3428 {
3429 struct qlcnic_hardware_context *ahw = adapter->ahw;
3430 struct qlc_83xx_idc *idc = &ahw->idc;
3431 int err = 0;
3432
3433 err = qlcnic_83xx_idc_init(adapter);
3434 if (err)
3435 return err;
3436
3437 if (ahw->nic_mode == QLC_83XX_VIRTUAL_NIC_MODE) {
3438 if (ahw->op_mode == QLCNIC_MGMT_FUNC) {
3439 qlcnic_83xx_set_vnic_opmode(adapter);
3440 } else {
3441 err = qlcnic_83xx_check_vnic_state(adapter);
3442 if (err)
3443 return err;
3444 }
3445 }
3446
3447 err = qlcnic_83xx_idc_reattach_driver(adapter);
3448 if (err)
3449 return err;
3450
3451 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
3452 idc->delay);
3453 return err;
3454 }
3455
3456 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx)
3457 {
3458 INIT_COMPLETION(mbx->completion);
3459 set_bit(QLC_83XX_MBX_READY, &mbx->status);
3460 }
3461
3462 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx)
3463 {
3464 destroy_workqueue(mbx->work_q);
3465 kfree(mbx);
3466 }
3467
3468 static inline void
3469 qlcnic_83xx_notify_cmd_completion(struct qlcnic_adapter *adapter,
3470 struct qlcnic_cmd_args *cmd)
3471 {
3472 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
3473
3474 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
3475 qlcnic_free_mbx_args(cmd);
3476 kfree(cmd);
3477 return;
3478 }
3479 complete(&cmd->completion);
3480 }
3481
3482 static inline void qlcnic_83xx_flush_mbx_queue(struct qlcnic_adapter *adapter)
3483 {
3484 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3485 struct list_head *head = &mbx->cmd_q;
3486 struct qlcnic_cmd_args *cmd = NULL;
3487
3488 spin_lock(&mbx->queue_lock);
3489
3490 while (!list_empty(head)) {
3491 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3492 list_del(&cmd->list);
3493 mbx->num_cmds--;
3494 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3495 }
3496
3497 spin_unlock(&mbx->queue_lock);
3498 }
3499
3500 static inline int qlcnic_83xx_check_mbx_status(struct qlcnic_adapter *adapter)
3501 {
3502 struct qlcnic_hardware_context *ahw = adapter->ahw;
3503 struct qlcnic_mailbox *mbx = ahw->mailbox;
3504 u32 host_mbx_ctrl;
3505
3506 if (!test_bit(QLC_83XX_MBX_READY, &mbx->status))
3507 return -EBUSY;
3508
3509 host_mbx_ctrl = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
3510 if (host_mbx_ctrl) {
3511 ahw->idc.collect_dump = 1;
3512 return -EIO;
3513 }
3514
3515 return 0;
3516 }
3517
3518 static inline void qlcnic_83xx_signal_mbx_cmd(struct qlcnic_adapter *adapter,
3519 u8 issue_cmd)
3520 {
3521 if (issue_cmd)
3522 QLCWRX(adapter->ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER);
3523 else
3524 QLCWRX(adapter->ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
3525 }
3526
3527 static inline void qlcnic_83xx_dequeue_mbx_cmd(struct qlcnic_adapter *adapter,
3528 struct qlcnic_cmd_args *cmd)
3529 {
3530 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3531
3532 spin_lock(&mbx->queue_lock);
3533
3534 list_del(&cmd->list);
3535 mbx->num_cmds--;
3536
3537 spin_unlock(&mbx->queue_lock);
3538
3539 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3540 }
3541
3542 static void qlcnic_83xx_encode_mbx_cmd(struct qlcnic_adapter *adapter,
3543 struct qlcnic_cmd_args *cmd)
3544 {
3545 u32 mbx_cmd, fw_hal_version, hdr_size, total_size, tmp;
3546 struct qlcnic_hardware_context *ahw = adapter->ahw;
3547 int i, j;
3548
3549 if (cmd->op_type != QLC_83XX_MBX_POST_BC_OP) {
3550 mbx_cmd = cmd->req.arg[0];
3551 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3552 for (i = 1; i < cmd->req.num; i++)
3553 writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i));
3554 } else {
3555 fw_hal_version = ahw->fw_hal_version;
3556 hdr_size = sizeof(struct qlcnic_bc_hdr) / sizeof(u32);
3557 total_size = cmd->pay_size + hdr_size;
3558 tmp = QLCNIC_CMD_BC_EVENT_SETUP | total_size << 16;
3559 mbx_cmd = tmp | fw_hal_version << 29;
3560 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3561
3562 /* Back channel specific operations bits */
3563 mbx_cmd = 0x1 | 1 << 4;
3564
3565 if (qlcnic_sriov_pf_check(adapter))
3566 mbx_cmd |= cmd->func_num << 5;
3567
3568 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 1));
3569
3570 for (i = 2, j = 0; j < hdr_size; i++, j++)
3571 writel(*(cmd->hdr++), QLCNIC_MBX_HOST(ahw, i));
3572 for (j = 0; j < cmd->pay_size; j++, i++)
3573 writel(*(cmd->pay++), QLCNIC_MBX_HOST(ahw, i));
3574 }
3575 }
3576
3577 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *adapter)
3578 {
3579 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3580
3581 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3582 complete(&mbx->completion);
3583 cancel_work_sync(&mbx->work);
3584 flush_workqueue(mbx->work_q);
3585 qlcnic_83xx_flush_mbx_queue(adapter);
3586 }
3587
3588 static inline int qlcnic_83xx_enqueue_mbx_cmd(struct qlcnic_adapter *adapter,
3589 struct qlcnic_cmd_args *cmd,
3590 unsigned long *timeout)
3591 {
3592 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3593
3594 if (test_bit(QLC_83XX_MBX_READY, &mbx->status)) {
3595 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3596 init_completion(&cmd->completion);
3597 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_UNKNOWN;
3598
3599 spin_lock(&mbx->queue_lock);
3600
3601 list_add_tail(&cmd->list, &mbx->cmd_q);
3602 mbx->num_cmds++;
3603 cmd->total_cmds = mbx->num_cmds;
3604 *timeout = cmd->total_cmds * QLC_83XX_MBX_TIMEOUT;
3605 queue_work(mbx->work_q, &mbx->work);
3606
3607 spin_unlock(&mbx->queue_lock);
3608
3609 return 0;
3610 }
3611
3612 return -EBUSY;
3613 }
3614
3615 static inline int qlcnic_83xx_check_mac_rcode(struct qlcnic_adapter *adapter,
3616 struct qlcnic_cmd_args *cmd)
3617 {
3618 u8 mac_cmd_rcode;
3619 u32 fw_data;
3620
3621 if (cmd->cmd_op == QLCNIC_CMD_CONFIG_MAC_VLAN) {
3622 fw_data = readl(QLCNIC_MBX_FW(adapter->ahw, 2));
3623 mac_cmd_rcode = (u8)fw_data;
3624 if (mac_cmd_rcode == QLC_83XX_NO_NIC_RESOURCE ||
3625 mac_cmd_rcode == QLC_83XX_MAC_PRESENT ||
3626 mac_cmd_rcode == QLC_83XX_MAC_ABSENT) {
3627 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3628 return QLCNIC_RCODE_SUCCESS;
3629 }
3630 }
3631
3632 return -EINVAL;
3633 }
3634
3635 static void qlcnic_83xx_decode_mbx_rsp(struct qlcnic_adapter *adapter,
3636 struct qlcnic_cmd_args *cmd)
3637 {
3638 struct qlcnic_hardware_context *ahw = adapter->ahw;
3639 struct device *dev = &adapter->pdev->dev;
3640 u8 mbx_err_code;
3641 u32 fw_data;
3642
3643 fw_data = readl(QLCNIC_MBX_FW(ahw, 0));
3644 mbx_err_code = QLCNIC_MBX_STATUS(fw_data);
3645 qlcnic_83xx_get_mbx_data(adapter, cmd);
3646
3647 switch (mbx_err_code) {
3648 case QLCNIC_MBX_RSP_OK:
3649 case QLCNIC_MBX_PORT_RSP_OK:
3650 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3651 break;
3652 default:
3653 if (!qlcnic_83xx_check_mac_rcode(adapter, cmd))
3654 break;
3655
3656 dev_err(dev, "%s: Mailbox command failed, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x, error=0x%x\n",
3657 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
3658 ahw->op_mode, mbx_err_code);
3659 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_FAILED;
3660 qlcnic_dump_mbx(adapter, cmd);
3661 }
3662
3663 return;
3664 }
3665
3666 static void qlcnic_83xx_mailbox_worker(struct work_struct *work)
3667 {
3668 struct qlcnic_mailbox *mbx = container_of(work, struct qlcnic_mailbox,
3669 work);
3670 struct qlcnic_adapter *adapter = mbx->adapter;
3671 struct qlcnic_mbx_ops *mbx_ops = mbx->ops;
3672 struct device *dev = &adapter->pdev->dev;
3673 atomic_t *rsp_status = &mbx->rsp_status;
3674 struct list_head *head = &mbx->cmd_q;
3675 struct qlcnic_hardware_context *ahw;
3676 struct qlcnic_cmd_args *cmd = NULL;
3677
3678 ahw = adapter->ahw;
3679
3680 while (true) {
3681 if (qlcnic_83xx_check_mbx_status(adapter))
3682 return;
3683
3684 atomic_set(rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3685
3686 spin_lock(&mbx->queue_lock);
3687
3688 if (list_empty(head)) {
3689 spin_unlock(&mbx->queue_lock);
3690 return;
3691 }
3692 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3693
3694 spin_unlock(&mbx->queue_lock);
3695
3696 mbx_ops->encode_cmd(adapter, cmd);
3697 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_REQUEST);
3698
3699 if (wait_for_completion_timeout(&mbx->completion,
3700 QLC_83XX_MBX_TIMEOUT)) {
3701 mbx_ops->decode_resp(adapter, cmd);
3702 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_COMPLETION);
3703 } else {
3704 dev_err(dev, "%s: Mailbox command timeout, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x\n",
3705 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
3706 ahw->op_mode);
3707 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3708 qlcnic_83xx_idc_request_reset(adapter,
3709 QLCNIC_FORCE_FW_DUMP_KEY);
3710 cmd->rsp_opcode = QLCNIC_RCODE_TIMEOUT;
3711 }
3712 mbx_ops->dequeue_cmd(adapter, cmd);
3713 }
3714 }
3715
3716 static struct qlcnic_mbx_ops qlcnic_83xx_mbx_ops = {
3717 .enqueue_cmd = qlcnic_83xx_enqueue_mbx_cmd,
3718 .dequeue_cmd = qlcnic_83xx_dequeue_mbx_cmd,
3719 .decode_resp = qlcnic_83xx_decode_mbx_rsp,
3720 .encode_cmd = qlcnic_83xx_encode_mbx_cmd,
3721 .nofity_fw = qlcnic_83xx_signal_mbx_cmd,
3722 };
3723
3724 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *adapter)
3725 {
3726 struct qlcnic_hardware_context *ahw = adapter->ahw;
3727 struct qlcnic_mailbox *mbx;
3728
3729 ahw->mailbox = kzalloc(sizeof(*mbx), GFP_KERNEL);
3730 if (!ahw->mailbox)
3731 return -ENOMEM;
3732
3733 mbx = ahw->mailbox;
3734 mbx->ops = &qlcnic_83xx_mbx_ops;
3735 mbx->adapter = adapter;
3736
3737 spin_lock_init(&mbx->queue_lock);
3738 spin_lock_init(&mbx->aen_lock);
3739 INIT_LIST_HEAD(&mbx->cmd_q);
3740 init_completion(&mbx->completion);
3741
3742 mbx->work_q = create_singlethread_workqueue("qlcnic_mailbox");
3743 if (mbx->work_q == NULL) {
3744 kfree(mbx);
3745 return -ENOMEM;
3746 }
3747
3748 INIT_WORK(&mbx->work, qlcnic_83xx_mailbox_worker);
3749 set_bit(QLC_83XX_MBX_READY, &mbx->status);
3750 return 0;
3751 }
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