2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
5 * See LICENSE.qlcnic for copyright and licensing details.
9 #include "qlcnic_sriov.h"
10 #include <linux/if_vlan.h>
11 #include <linux/ipv6.h>
12 #include <linux/ethtool.h>
13 #include <linux/interrupt.h>
14 #include <linux/aer.h>
16 #define QLCNIC_MAX_TX_QUEUES 1
17 #define RSS_HASHTYPE_IP_TCP 0x3
18 #define QLC_83XX_FW_MBX_CMD 0
20 static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl
[] = {
21 {QLCNIC_CMD_CONFIGURE_IP_ADDR
, 6, 1},
22 {QLCNIC_CMD_CONFIG_INTRPT
, 18, 34},
23 {QLCNIC_CMD_CREATE_RX_CTX
, 136, 27},
24 {QLCNIC_CMD_DESTROY_RX_CTX
, 2, 1},
25 {QLCNIC_CMD_CREATE_TX_CTX
, 54, 18},
26 {QLCNIC_CMD_DESTROY_TX_CTX
, 2, 1},
27 {QLCNIC_CMD_CONFIGURE_MAC_LEARNING
, 2, 1},
28 {QLCNIC_CMD_INTRPT_TEST
, 22, 12},
29 {QLCNIC_CMD_SET_MTU
, 3, 1},
30 {QLCNIC_CMD_READ_PHY
, 4, 2},
31 {QLCNIC_CMD_WRITE_PHY
, 5, 1},
32 {QLCNIC_CMD_READ_HW_REG
, 4, 1},
33 {QLCNIC_CMD_GET_FLOW_CTL
, 4, 2},
34 {QLCNIC_CMD_SET_FLOW_CTL
, 4, 1},
35 {QLCNIC_CMD_READ_MAX_MTU
, 4, 2},
36 {QLCNIC_CMD_READ_MAX_LRO
, 4, 2},
37 {QLCNIC_CMD_MAC_ADDRESS
, 4, 3},
38 {QLCNIC_CMD_GET_PCI_INFO
, 1, 66},
39 {QLCNIC_CMD_GET_NIC_INFO
, 2, 19},
40 {QLCNIC_CMD_SET_NIC_INFO
, 32, 1},
41 {QLCNIC_CMD_GET_ESWITCH_CAPABILITY
, 4, 3},
42 {QLCNIC_CMD_TOGGLE_ESWITCH
, 4, 1},
43 {QLCNIC_CMD_GET_ESWITCH_STATUS
, 4, 3},
44 {QLCNIC_CMD_SET_PORTMIRRORING
, 4, 1},
45 {QLCNIC_CMD_CONFIGURE_ESWITCH
, 4, 1},
46 {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG
, 4, 3},
47 {QLCNIC_CMD_GET_ESWITCH_STATS
, 5, 1},
48 {QLCNIC_CMD_CONFIG_PORT
, 4, 1},
49 {QLCNIC_CMD_TEMP_SIZE
, 1, 4},
50 {QLCNIC_CMD_GET_TEMP_HDR
, 5, 5},
51 {QLCNIC_CMD_GET_LINK_EVENT
, 2, 1},
52 {QLCNIC_CMD_CONFIG_MAC_VLAN
, 4, 3},
53 {QLCNIC_CMD_CONFIG_INTR_COAL
, 6, 1},
54 {QLCNIC_CMD_CONFIGURE_RSS
, 14, 1},
55 {QLCNIC_CMD_CONFIGURE_LED
, 2, 1},
56 {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE
, 2, 1},
57 {QLCNIC_CMD_CONFIGURE_HW_LRO
, 2, 1},
58 {QLCNIC_CMD_GET_STATISTICS
, 2, 80},
59 {QLCNIC_CMD_SET_PORT_CONFIG
, 2, 1},
60 {QLCNIC_CMD_GET_PORT_CONFIG
, 2, 2},
61 {QLCNIC_CMD_GET_LINK_STATUS
, 2, 4},
62 {QLCNIC_CMD_IDC_ACK
, 5, 1},
63 {QLCNIC_CMD_INIT_NIC_FUNC
, 2, 1},
64 {QLCNIC_CMD_STOP_NIC_FUNC
, 2, 1},
65 {QLCNIC_CMD_SET_LED_CONFIG
, 5, 1},
66 {QLCNIC_CMD_GET_LED_CONFIG
, 1, 5},
67 {QLCNIC_CMD_83XX_SET_DRV_VER
, 4, 1},
68 {QLCNIC_CMD_ADD_RCV_RINGS
, 130, 26},
69 {QLCNIC_CMD_CONFIG_VPORT
, 4, 4},
70 {QLCNIC_CMD_BC_EVENT_SETUP
, 2, 1},
71 {QLCNIC_CMD_DCB_QUERY_CAP
, 1, 2},
72 {QLCNIC_CMD_DCB_QUERY_PARAM
, 2, 50},
75 const u32 qlcnic_83xx_ext_reg_tbl
[] = {
76 0x38CC, /* Global Reset */
77 0x38F0, /* Wildcard */
78 0x38FC, /* Informant */
79 0x3038, /* Host MBX ctrl */
80 0x303C, /* FW MBX ctrl */
81 0x355C, /* BOOT LOADER ADDRESS REG */
82 0x3560, /* BOOT LOADER SIZE REG */
83 0x3564, /* FW IMAGE ADDR REG */
84 0x1000, /* MBX intr enable */
85 0x1200, /* Default Intr mask */
86 0x1204, /* Default Interrupt ID */
87 0x3780, /* QLC_83XX_IDC_MAJ_VERSION */
88 0x3784, /* QLC_83XX_IDC_DEV_STATE */
89 0x3788, /* QLC_83XX_IDC_DRV_PRESENCE */
90 0x378C, /* QLC_83XX_IDC_DRV_ACK */
91 0x3790, /* QLC_83XX_IDC_CTRL */
92 0x3794, /* QLC_83XX_IDC_DRV_AUDIT */
93 0x3798, /* QLC_83XX_IDC_MIN_VERSION */
94 0x379C, /* QLC_83XX_RECOVER_DRV_LOCK */
95 0x37A0, /* QLC_83XX_IDC_PF_0 */
96 0x37A4, /* QLC_83XX_IDC_PF_1 */
97 0x37A8, /* QLC_83XX_IDC_PF_2 */
98 0x37AC, /* QLC_83XX_IDC_PF_3 */
99 0x37B0, /* QLC_83XX_IDC_PF_4 */
100 0x37B4, /* QLC_83XX_IDC_PF_5 */
101 0x37B8, /* QLC_83XX_IDC_PF_6 */
102 0x37BC, /* QLC_83XX_IDC_PF_7 */
103 0x37C0, /* QLC_83XX_IDC_PF_8 */
104 0x37C4, /* QLC_83XX_IDC_PF_9 */
105 0x37C8, /* QLC_83XX_IDC_PF_10 */
106 0x37CC, /* QLC_83XX_IDC_PF_11 */
107 0x37D0, /* QLC_83XX_IDC_PF_12 */
108 0x37D4, /* QLC_83XX_IDC_PF_13 */
109 0x37D8, /* QLC_83XX_IDC_PF_14 */
110 0x37DC, /* QLC_83XX_IDC_PF_15 */
111 0x37E0, /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */
112 0x37E4, /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */
113 0x37F0, /* QLC_83XX_DRV_OP_MODE */
114 0x37F4, /* QLC_83XX_VNIC_STATE */
115 0x3868, /* QLC_83XX_DRV_LOCK */
116 0x386C, /* QLC_83XX_DRV_UNLOCK */
117 0x3504, /* QLC_83XX_DRV_LOCK_ID */
118 0x34A4, /* QLC_83XX_ASIC_TEMP */
121 const u32 qlcnic_83xx_reg_tbl
[] = {
122 0x34A8, /* PEG_HALT_STAT1 */
123 0x34AC, /* PEG_HALT_STAT2 */
124 0x34B0, /* FW_HEARTBEAT */
125 0x3500, /* FLASH LOCK_ID */
126 0x3528, /* FW_CAPABILITIES */
127 0x3538, /* Driver active, DRV_REG0 */
128 0x3540, /* Device state, DRV_REG1 */
129 0x3544, /* Driver state, DRV_REG2 */
130 0x3548, /* Driver scratch, DRV_REG3 */
131 0x354C, /* Device partiton info, DRV_REG4 */
132 0x3524, /* Driver IDC ver, DRV_REG5 */
133 0x3550, /* FW_VER_MAJOR */
134 0x3554, /* FW_VER_MINOR */
135 0x3558, /* FW_VER_SUB */
136 0x359C, /* NPAR STATE */
137 0x35FC, /* FW_IMG_VALID */
138 0x3650, /* CMD_PEG_STATE */
139 0x373C, /* RCV_PEG_STATE */
140 0x37B4, /* ASIC TEMP */
142 0x3570, /* DRV OP MODE */
143 0x3850, /* FLASH LOCK */
144 0x3854, /* FLASH UNLOCK */
147 static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops
= {
148 .read_crb
= qlcnic_83xx_read_crb
,
149 .write_crb
= qlcnic_83xx_write_crb
,
150 .read_reg
= qlcnic_83xx_rd_reg_indirect
,
151 .write_reg
= qlcnic_83xx_wrt_reg_indirect
,
152 .get_mac_address
= qlcnic_83xx_get_mac_address
,
153 .setup_intr
= qlcnic_83xx_setup_intr
,
154 .alloc_mbx_args
= qlcnic_83xx_alloc_mbx_args
,
155 .mbx_cmd
= qlcnic_83xx_issue_cmd
,
156 .get_func_no
= qlcnic_83xx_get_func_no
,
157 .api_lock
= qlcnic_83xx_cam_lock
,
158 .api_unlock
= qlcnic_83xx_cam_unlock
,
159 .add_sysfs
= qlcnic_83xx_add_sysfs
,
160 .remove_sysfs
= qlcnic_83xx_remove_sysfs
,
161 .process_lb_rcv_ring_diag
= qlcnic_83xx_process_rcv_ring_diag
,
162 .create_rx_ctx
= qlcnic_83xx_create_rx_ctx
,
163 .create_tx_ctx
= qlcnic_83xx_create_tx_ctx
,
164 .del_rx_ctx
= qlcnic_83xx_del_rx_ctx
,
165 .del_tx_ctx
= qlcnic_83xx_del_tx_ctx
,
166 .setup_link_event
= qlcnic_83xx_setup_link_event
,
167 .get_nic_info
= qlcnic_83xx_get_nic_info
,
168 .get_pci_info
= qlcnic_83xx_get_pci_info
,
169 .set_nic_info
= qlcnic_83xx_set_nic_info
,
170 .change_macvlan
= qlcnic_83xx_sre_macaddr_change
,
171 .napi_enable
= qlcnic_83xx_napi_enable
,
172 .napi_disable
= qlcnic_83xx_napi_disable
,
173 .config_intr_coal
= qlcnic_83xx_config_intr_coal
,
174 .config_rss
= qlcnic_83xx_config_rss
,
175 .config_hw_lro
= qlcnic_83xx_config_hw_lro
,
176 .config_promisc_mode
= qlcnic_83xx_nic_set_promisc
,
177 .change_l2_filter
= qlcnic_83xx_change_l2_filter
,
178 .get_board_info
= qlcnic_83xx_get_port_info
,
179 .set_mac_filter_count
= qlcnic_83xx_set_mac_filter_count
,
180 .free_mac_list
= qlcnic_82xx_free_mac_list
,
181 .io_error_detected
= qlcnic_83xx_io_error_detected
,
182 .io_slot_reset
= qlcnic_83xx_io_slot_reset
,
183 .io_resume
= qlcnic_83xx_io_resume
,
187 static struct qlcnic_nic_template qlcnic_83xx_ops
= {
188 .config_bridged_mode
= qlcnic_config_bridged_mode
,
189 .config_led
= qlcnic_config_led
,
190 .request_reset
= qlcnic_83xx_idc_request_reset
,
191 .cancel_idc_work
= qlcnic_83xx_idc_exit
,
192 .napi_add
= qlcnic_83xx_napi_add
,
193 .napi_del
= qlcnic_83xx_napi_del
,
194 .config_ipaddr
= qlcnic_83xx_config_ipaddr
,
195 .clear_legacy_intr
= qlcnic_83xx_clear_legacy_intr
,
196 .shutdown
= qlcnic_83xx_shutdown
,
197 .resume
= qlcnic_83xx_resume
,
200 void qlcnic_83xx_register_map(struct qlcnic_hardware_context
*ahw
)
202 ahw
->hw_ops
= &qlcnic_83xx_hw_ops
;
203 ahw
->reg_tbl
= (u32
*)qlcnic_83xx_reg_tbl
;
204 ahw
->ext_reg_tbl
= (u32
*)qlcnic_83xx_ext_reg_tbl
;
207 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter
*adapter
)
209 u32 fw_major
, fw_minor
, fw_build
;
210 struct pci_dev
*pdev
= adapter
->pdev
;
212 fw_major
= QLC_SHARED_REG_RD32(adapter
, QLCNIC_FW_VERSION_MAJOR
);
213 fw_minor
= QLC_SHARED_REG_RD32(adapter
, QLCNIC_FW_VERSION_MINOR
);
214 fw_build
= QLC_SHARED_REG_RD32(adapter
, QLCNIC_FW_VERSION_SUB
);
215 adapter
->fw_version
= QLCNIC_VERSION_CODE(fw_major
, fw_minor
, fw_build
);
217 dev_info(&pdev
->dev
, "Driver v%s, firmware version %d.%d.%d\n",
218 QLCNIC_LINUX_VERSIONID
, fw_major
, fw_minor
, fw_build
);
220 return adapter
->fw_version
;
223 static int __qlcnic_set_win_base(struct qlcnic_adapter
*adapter
, u32 addr
)
228 base
= adapter
->ahw
->pci_base0
+
229 QLC_83XX_CRB_WIN_FUNC(adapter
->ahw
->pci_func
);
238 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter
*adapter
, ulong addr
,
241 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
243 *err
= __qlcnic_set_win_base(adapter
, (u32
) addr
);
245 return QLCRDX(ahw
, QLCNIC_WILDCARD
);
247 dev_err(&adapter
->pdev
->dev
,
248 "%s failed, addr = 0x%lx\n", __func__
, addr
);
253 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter
*adapter
, ulong addr
,
257 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
259 err
= __qlcnic_set_win_base(adapter
, (u32
) addr
);
261 QLCWRX(ahw
, QLCNIC_WILDCARD
, data
);
264 dev_err(&adapter
->pdev
->dev
,
265 "%s failed, addr = 0x%x data = 0x%x\n",
266 __func__
, (int)addr
, data
);
271 int qlcnic_83xx_setup_intr(struct qlcnic_adapter
*adapter
, u8 num_intr
, int txq
)
273 int err
, i
, num_msix
;
274 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
277 num_intr
= QLCNIC_DEF_NUM_STS_DESC_RINGS
;
278 num_msix
= rounddown_pow_of_two(min_t(int, num_online_cpus(),
280 /* account for AEN interrupt MSI-X based interrupts */
283 if (!(adapter
->flags
& QLCNIC_TX_INTR_SHARED
))
284 num_msix
+= adapter
->max_drv_tx_rings
;
286 err
= qlcnic_enable_msix(adapter
, num_msix
);
289 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
290 num_msix
= adapter
->ahw
->num_msix
;
292 if (qlcnic_sriov_vf_check(adapter
))
296 /* setup interrupt mapping table for fw */
297 ahw
->intr_tbl
= vzalloc(num_msix
*
298 sizeof(struct qlcnic_intrpt_config
));
301 if (!(adapter
->flags
& QLCNIC_MSIX_ENABLED
)) {
302 /* MSI-X enablement failed, use legacy interrupt */
303 adapter
->tgt_status_reg
= ahw
->pci_base0
+ QLC_83XX_INTX_PTR
;
304 adapter
->tgt_mask_reg
= ahw
->pci_base0
+ QLC_83XX_INTX_MASK
;
305 adapter
->isr_int_vec
= ahw
->pci_base0
+ QLC_83XX_INTX_TRGR
;
306 adapter
->msix_entries
[0].vector
= adapter
->pdev
->irq
;
307 dev_info(&adapter
->pdev
->dev
, "using legacy interrupt\n");
310 for (i
= 0; i
< num_msix
; i
++) {
311 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
312 ahw
->intr_tbl
[i
].type
= QLCNIC_INTRPT_MSIX
;
314 ahw
->intr_tbl
[i
].type
= QLCNIC_INTRPT_INTX
;
315 ahw
->intr_tbl
[i
].id
= i
;
316 ahw
->intr_tbl
[i
].src
= 0;
321 inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter
*adapter
)
323 writel(0, adapter
->tgt_mask_reg
);
326 inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter
*adapter
)
328 writel(1, adapter
->tgt_mask_reg
);
331 /* Enable MSI-x and INT-x interrupts */
332 void qlcnic_83xx_enable_intr(struct qlcnic_adapter
*adapter
,
333 struct qlcnic_host_sds_ring
*sds_ring
)
335 writel(0, sds_ring
->crb_intr_mask
);
338 /* Disable MSI-x and INT-x interrupts */
339 void qlcnic_83xx_disable_intr(struct qlcnic_adapter
*adapter
,
340 struct qlcnic_host_sds_ring
*sds_ring
)
342 writel(1, sds_ring
->crb_intr_mask
);
345 inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
350 /* Mailbox in MSI-x mode and Legacy Interrupt share the same
351 * source register. We could be here before contexts are created
352 * and sds_ring->crb_intr_mask has not been initialized, calculate
353 * BAR offset for Interrupt Source Register
355 mask
= QLCRDX(adapter
->ahw
, QLCNIC_DEF_INT_MASK
);
356 writel(0, adapter
->ahw
->pci_base0
+ mask
);
359 void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter
*adapter
)
363 mask
= QLCRDX(adapter
->ahw
, QLCNIC_DEF_INT_MASK
);
364 writel(1, adapter
->ahw
->pci_base0
+ mask
);
365 QLCWRX(adapter
->ahw
, QLCNIC_MBX_INTR_ENBL
, 0);
368 static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter
*adapter
,
369 struct qlcnic_cmd_args
*cmd
)
373 if (cmd
->op_type
== QLC_83XX_MBX_POST_BC_OP
)
376 for (i
= 0; i
< cmd
->rsp
.num
; i
++)
377 cmd
->rsp
.arg
[i
] = readl(QLCNIC_MBX_FW(adapter
->ahw
, i
));
380 irqreturn_t
qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter
*adapter
)
383 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
386 intr_val
= readl(adapter
->tgt_status_reg
);
388 if (!QLC_83XX_VALID_INTX_BIT31(intr_val
))
391 if (QLC_83XX_INTX_FUNC(intr_val
) != adapter
->ahw
->pci_func
) {
392 adapter
->stats
.spurious_intr
++;
395 /* The barrier is required to ensure writes to the registers */
398 /* clear the interrupt trigger control register */
399 writel(0, adapter
->isr_int_vec
);
400 intr_val
= readl(adapter
->isr_int_vec
);
402 intr_val
= readl(adapter
->tgt_status_reg
);
403 if (QLC_83XX_INTX_FUNC(intr_val
) != ahw
->pci_func
)
406 } while (QLC_83XX_VALID_INTX_BIT30(intr_val
) &&
407 (retries
< QLC_83XX_LEGACY_INTX_MAX_RETRY
));
412 static inline void qlcnic_83xx_notify_mbx_response(struct qlcnic_mailbox
*mbx
)
414 atomic_set(&mbx
->rsp_status
, QLC_83XX_MBX_RESPONSE_ARRIVED
);
415 complete(&mbx
->completion
);
418 static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter
*adapter
)
420 u32 resp
, event
, rsp_status
= QLC_83XX_MBX_RESPONSE_ARRIVED
;
421 struct qlcnic_mailbox
*mbx
= adapter
->ahw
->mailbox
;
424 spin_lock_irqsave(&mbx
->aen_lock
, flags
);
425 resp
= QLCRDX(adapter
->ahw
, QLCNIC_FW_MBX_CTRL
);
426 if (!(resp
& QLCNIC_SET_OWNER
))
429 event
= readl(QLCNIC_MBX_FW(adapter
->ahw
, 0));
430 if (event
& QLCNIC_MBX_ASYNC_EVENT
) {
431 __qlcnic_83xx_process_aen(adapter
);
433 if (atomic_read(&mbx
->rsp_status
) != rsp_status
)
434 qlcnic_83xx_notify_mbx_response(mbx
);
437 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter
);
438 spin_unlock_irqrestore(&mbx
->aen_lock
, flags
);
441 irqreturn_t
qlcnic_83xx_intr(int irq
, void *data
)
443 struct qlcnic_adapter
*adapter
= data
;
444 struct qlcnic_host_sds_ring
*sds_ring
;
445 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
447 if (qlcnic_83xx_clear_legacy_intr(adapter
) == IRQ_NONE
)
450 qlcnic_83xx_poll_process_aen(adapter
);
452 if (ahw
->diag_test
== QLCNIC_INTERRUPT_TEST
) {
454 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter
);
458 if (!test_bit(__QLCNIC_DEV_UP
, &adapter
->state
)) {
459 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter
);
461 sds_ring
= &adapter
->recv_ctx
->sds_rings
[0];
462 napi_schedule(&sds_ring
->napi
);
468 irqreturn_t
qlcnic_83xx_tmp_intr(int irq
, void *data
)
470 struct qlcnic_host_sds_ring
*sds_ring
= data
;
471 struct qlcnic_adapter
*adapter
= sds_ring
->adapter
;
473 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
476 if (adapter
->nic_ops
->clear_legacy_intr(adapter
) == IRQ_NONE
)
480 adapter
->ahw
->diag_cnt
++;
481 qlcnic_83xx_enable_intr(adapter
, sds_ring
);
486 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter
*adapter
)
490 if (!(adapter
->flags
& QLCNIC_MSIX_ENABLED
))
491 qlcnic_83xx_set_legacy_intr_mask(adapter
);
493 qlcnic_83xx_disable_mbx_intr(adapter
);
495 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
496 num_msix
= adapter
->ahw
->num_msix
- 1;
501 synchronize_irq(adapter
->msix_entries
[num_msix
].vector
);
502 free_irq(adapter
->msix_entries
[num_msix
].vector
, adapter
);
505 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter
*adapter
)
507 irq_handler_t handler
;
510 unsigned long flags
= 0;
512 if (!(adapter
->flags
& QLCNIC_MSI_ENABLED
) &&
513 !(adapter
->flags
& QLCNIC_MSIX_ENABLED
))
514 flags
|= IRQF_SHARED
;
516 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
) {
517 handler
= qlcnic_83xx_handle_aen
;
518 val
= adapter
->msix_entries
[adapter
->ahw
->num_msix
- 1].vector
;
519 err
= request_irq(val
, handler
, flags
, "qlcnic-MB", adapter
);
521 dev_err(&adapter
->pdev
->dev
,
522 "failed to register MBX interrupt\n");
526 handler
= qlcnic_83xx_intr
;
527 val
= adapter
->msix_entries
[0].vector
;
528 err
= request_irq(val
, handler
, flags
, "qlcnic", adapter
);
530 dev_err(&adapter
->pdev
->dev
,
531 "failed to register INTx interrupt\n");
534 qlcnic_83xx_clear_legacy_intr_mask(adapter
);
537 /* Enable mailbox interrupt */
538 qlcnic_83xx_enable_mbx_interrupt(adapter
);
543 void qlcnic_83xx_get_func_no(struct qlcnic_adapter
*adapter
)
545 u32 val
= QLCRDX(adapter
->ahw
, QLCNIC_INFORMANT
);
546 adapter
->ahw
->pci_func
= (val
>> 24) & 0xff;
549 int qlcnic_83xx_cam_lock(struct qlcnic_adapter
*adapter
)
554 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
556 addr
= ahw
->pci_base0
+ QLC_83XX_SEM_LOCK_FUNC(ahw
->pci_func
);
560 /* write the function number to register */
561 QLC_SHARED_REG_WR32(adapter
, QLCNIC_FLASH_LOCK_OWNER
,
565 usleep_range(1000, 2000);
566 } while (++limit
<= QLCNIC_PCIE_SEM_TIMEOUT
);
571 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter
*adapter
)
575 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
577 addr
= ahw
->pci_base0
+ QLC_83XX_SEM_UNLOCK_FUNC(ahw
->pci_func
);
581 void qlcnic_83xx_read_crb(struct qlcnic_adapter
*adapter
, char *buf
,
582 loff_t offset
, size_t size
)
587 if (qlcnic_api_lock(adapter
)) {
588 dev_err(&adapter
->pdev
->dev
,
589 "%s: failed to acquire lock. addr offset 0x%x\n",
590 __func__
, (u32
)offset
);
594 data
= QLCRD32(adapter
, (u32
) offset
, &ret
);
595 qlcnic_api_unlock(adapter
);
598 dev_err(&adapter
->pdev
->dev
,
599 "%s: failed. addr offset 0x%x\n",
600 __func__
, (u32
)offset
);
603 memcpy(buf
, &data
, size
);
606 void qlcnic_83xx_write_crb(struct qlcnic_adapter
*adapter
, char *buf
,
607 loff_t offset
, size_t size
)
611 memcpy(&data
, buf
, size
);
612 qlcnic_83xx_wrt_reg_indirect(adapter
, (u32
) offset
, data
);
615 int qlcnic_83xx_get_port_info(struct qlcnic_adapter
*adapter
)
619 status
= qlcnic_83xx_get_port_config(adapter
);
621 dev_err(&adapter
->pdev
->dev
,
622 "Get Port Info failed\n");
624 if (QLC_83XX_SFP_10G_CAPABLE(adapter
->ahw
->port_config
))
625 adapter
->ahw
->port_type
= QLCNIC_XGBE
;
627 adapter
->ahw
->port_type
= QLCNIC_GBE
;
629 if (QLC_83XX_AUTONEG(adapter
->ahw
->port_config
))
630 adapter
->ahw
->link_autoneg
= AUTONEG_ENABLE
;
635 void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter
*adapter
)
637 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
638 u16 act_pci_fn
= ahw
->act_pci_func
;
641 ahw
->max_mc_count
= QLC_83XX_MAX_MC_COUNT
;
643 count
= (QLC_83XX_MAX_UC_COUNT
- QLC_83XX_MAX_MC_COUNT
) /
646 count
= (QLC_83XX_LB_MAX_FILTERS
- QLC_83XX_MAX_MC_COUNT
) /
648 ahw
->max_uc_count
= count
;
651 void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter
*adapter
)
655 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
656 val
= BIT_2
| ((adapter
->ahw
->num_msix
- 1) << 8);
660 QLCWRX(adapter
->ahw
, QLCNIC_MBX_INTR_ENBL
, val
);
661 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter
);
664 void qlcnic_83xx_check_vf(struct qlcnic_adapter
*adapter
,
665 const struct pci_device_id
*ent
)
667 u32 op_mode
, priv_level
;
668 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
670 ahw
->fw_hal_version
= 2;
671 qlcnic_get_func_no(adapter
);
673 if (qlcnic_sriov_vf_check(adapter
)) {
674 qlcnic_sriov_vf_set_ops(adapter
);
678 /* Determine function privilege level */
679 op_mode
= QLCRDX(adapter
->ahw
, QLC_83XX_DRV_OP_MODE
);
680 if (op_mode
== QLC_83XX_DEFAULT_OPMODE
)
681 priv_level
= QLCNIC_MGMT_FUNC
;
683 priv_level
= QLC_83XX_GET_FUNC_PRIVILEGE(op_mode
,
686 if (priv_level
== QLCNIC_NON_PRIV_FUNC
) {
687 ahw
->op_mode
= QLCNIC_NON_PRIV_FUNC
;
688 dev_info(&adapter
->pdev
->dev
,
689 "HAL Version: %d Non Privileged function\n",
690 ahw
->fw_hal_version
);
691 adapter
->nic_ops
= &qlcnic_vf_ops
;
693 if (pci_find_ext_capability(adapter
->pdev
,
694 PCI_EXT_CAP_ID_SRIOV
))
695 set_bit(__QLCNIC_SRIOV_CAPABLE
, &adapter
->state
);
696 adapter
->nic_ops
= &qlcnic_83xx_ops
;
700 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter
*adapter
,
702 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter
*adapter
,
705 void qlcnic_dump_mbx(struct qlcnic_adapter
*adapter
,
706 struct qlcnic_cmd_args
*cmd
)
710 if (cmd
->op_type
== QLC_83XX_MBX_POST_BC_OP
)
713 dev_info(&adapter
->pdev
->dev
,
714 "Host MBX regs(%d)\n", cmd
->req
.num
);
715 for (i
= 0; i
< cmd
->req
.num
; i
++) {
718 pr_info("%08x ", cmd
->req
.arg
[i
]);
721 dev_info(&adapter
->pdev
->dev
,
722 "FW MBX regs(%d)\n", cmd
->rsp
.num
);
723 for (i
= 0; i
< cmd
->rsp
.num
; i
++) {
726 pr_info("%08x ", cmd
->rsp
.arg
[i
]);
731 static void qlcnic_83xx_poll_for_mbx_completion(struct qlcnic_adapter
*adapter
,
732 struct qlcnic_cmd_args
*cmd
)
734 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
735 int opcode
= LSW(cmd
->req
.arg
[0]);
736 unsigned long max_loops
;
738 max_loops
= cmd
->total_cmds
* QLC_83XX_MBX_CMD_LOOP
;
740 for (; max_loops
; max_loops
--) {
741 if (atomic_read(&cmd
->rsp_status
) ==
742 QLC_83XX_MBX_RESPONSE_ARRIVED
)
748 dev_err(&adapter
->pdev
->dev
,
749 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
750 __func__
, opcode
, cmd
->type
, ahw
->pci_func
, ahw
->op_mode
);
751 flush_workqueue(ahw
->mailbox
->work_q
);
755 int qlcnic_83xx_issue_cmd(struct qlcnic_adapter
*adapter
,
756 struct qlcnic_cmd_args
*cmd
)
758 struct qlcnic_mailbox
*mbx
= adapter
->ahw
->mailbox
;
759 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
760 int cmd_type
, err
, opcode
;
761 unsigned long timeout
;
763 opcode
= LSW(cmd
->req
.arg
[0]);
764 cmd_type
= cmd
->type
;
765 err
= mbx
->ops
->enqueue_cmd(adapter
, cmd
, &timeout
);
767 dev_err(&adapter
->pdev
->dev
,
768 "%s: Mailbox not available, cmd_op=0x%x, cmd_context=0x%x, pci_func=0x%x, op_mode=0x%x\n",
769 __func__
, opcode
, cmd
->type
, ahw
->pci_func
,
775 case QLC_83XX_MBX_CMD_WAIT
:
776 if (!wait_for_completion_timeout(&cmd
->completion
, timeout
)) {
777 dev_err(&adapter
->pdev
->dev
,
778 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
779 __func__
, opcode
, cmd_type
, ahw
->pci_func
,
781 flush_workqueue(mbx
->work_q
);
784 case QLC_83XX_MBX_CMD_NO_WAIT
:
786 case QLC_83XX_MBX_CMD_BUSY_WAIT
:
787 qlcnic_83xx_poll_for_mbx_completion(adapter
, cmd
);
790 dev_err(&adapter
->pdev
->dev
,
791 "%s: Invalid mailbox command, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
792 __func__
, opcode
, cmd_type
, ahw
->pci_func
,
794 qlcnic_83xx_detach_mailbox_work(adapter
);
797 return cmd
->rsp_opcode
;
800 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args
*mbx
,
801 struct qlcnic_adapter
*adapter
, u32 type
)
805 const struct qlcnic_mailbox_metadata
*mbx_tbl
;
807 memset(mbx
, 0, sizeof(struct qlcnic_cmd_args
));
808 mbx_tbl
= qlcnic_83xx_mbx_tbl
;
809 size
= ARRAY_SIZE(qlcnic_83xx_mbx_tbl
);
810 for (i
= 0; i
< size
; i
++) {
811 if (type
== mbx_tbl
[i
].cmd
) {
812 mbx
->op_type
= QLC_83XX_FW_MBX_CMD
;
813 mbx
->req
.num
= mbx_tbl
[i
].in_args
;
814 mbx
->rsp
.num
= mbx_tbl
[i
].out_args
;
815 mbx
->req
.arg
= kcalloc(mbx
->req
.num
, sizeof(u32
),
819 mbx
->rsp
.arg
= kcalloc(mbx
->rsp
.num
, sizeof(u32
),
826 memset(mbx
->req
.arg
, 0, sizeof(u32
) * mbx
->req
.num
);
827 memset(mbx
->rsp
.arg
, 0, sizeof(u32
) * mbx
->rsp
.num
);
828 temp
= adapter
->ahw
->fw_hal_version
<< 29;
829 mbx
->req
.arg
[0] = (type
| (mbx
->req
.num
<< 16) | temp
);
837 void qlcnic_83xx_idc_aen_work(struct work_struct
*work
)
839 struct qlcnic_adapter
*adapter
;
840 struct qlcnic_cmd_args cmd
;
843 adapter
= container_of(work
, struct qlcnic_adapter
, idc_aen_work
.work
);
844 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_IDC_ACK
);
848 for (i
= 1; i
< QLC_83XX_MBX_AEN_CNT
; i
++)
849 cmd
.req
.arg
[i
] = adapter
->ahw
->mbox_aen
[i
];
851 err
= qlcnic_issue_cmd(adapter
, &cmd
);
853 dev_info(&adapter
->pdev
->dev
,
854 "%s: Mailbox IDC ACK failed.\n", __func__
);
855 qlcnic_free_mbx_args(&cmd
);
858 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter
*adapter
,
861 dev_dbg(&adapter
->pdev
->dev
, "Completion AEN:0x%x.\n",
862 QLCNIC_MBX_RSP(data
[0]));
863 clear_bit(QLC_83XX_IDC_COMP_AEN
, &adapter
->ahw
->idc
.status
);
867 void __qlcnic_83xx_process_aen(struct qlcnic_adapter
*adapter
)
869 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
870 u32 event
[QLC_83XX_MBX_AEN_CNT
];
873 for (i
= 0; i
< QLC_83XX_MBX_AEN_CNT
; i
++)
874 event
[i
] = readl(QLCNIC_MBX_FW(ahw
, i
));
876 switch (QLCNIC_MBX_RSP(event
[0])) {
878 case QLCNIC_MBX_LINK_EVENT
:
879 qlcnic_83xx_handle_link_aen(adapter
, event
);
881 case QLCNIC_MBX_COMP_EVENT
:
882 qlcnic_83xx_handle_idc_comp_aen(adapter
, event
);
884 case QLCNIC_MBX_REQUEST_EVENT
:
885 for (i
= 0; i
< QLC_83XX_MBX_AEN_CNT
; i
++)
886 adapter
->ahw
->mbox_aen
[i
] = QLCNIC_MBX_RSP(event
[i
]);
887 queue_delayed_work(adapter
->qlcnic_wq
,
888 &adapter
->idc_aen_work
, 0);
890 case QLCNIC_MBX_TIME_EXTEND_EVENT
:
891 ahw
->extend_lb_time
= event
[1] >> 8 & 0xf;
893 case QLCNIC_MBX_BC_EVENT
:
894 qlcnic_sriov_handle_bc_event(adapter
, event
[1]);
896 case QLCNIC_MBX_SFP_INSERT_EVENT
:
897 dev_info(&adapter
->pdev
->dev
, "SFP+ Insert AEN:0x%x.\n",
898 QLCNIC_MBX_RSP(event
[0]));
900 case QLCNIC_MBX_SFP_REMOVE_EVENT
:
901 dev_info(&adapter
->pdev
->dev
, "SFP Removed AEN:0x%x.\n",
902 QLCNIC_MBX_RSP(event
[0]));
904 case QLCNIC_MBX_DCBX_CONFIG_CHANGE_EVENT
:
905 qlcnic_dcb_handle_aen(adapter
, (void *)&event
[1]);
908 dev_dbg(&adapter
->pdev
->dev
, "Unsupported AEN:0x%x.\n",
909 QLCNIC_MBX_RSP(event
[0]));
913 QLCWRX(ahw
, QLCNIC_FW_MBX_CTRL
, QLCNIC_CLR_OWNER
);
916 static void qlcnic_83xx_process_aen(struct qlcnic_adapter
*adapter
)
918 u32 resp
, event
, rsp_status
= QLC_83XX_MBX_RESPONSE_ARRIVED
;
919 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
920 struct qlcnic_mailbox
*mbx
= ahw
->mailbox
;
923 spin_lock_irqsave(&mbx
->aen_lock
, flags
);
924 resp
= QLCRDX(ahw
, QLCNIC_FW_MBX_CTRL
);
925 if (resp
& QLCNIC_SET_OWNER
) {
926 event
= readl(QLCNIC_MBX_FW(ahw
, 0));
927 if (event
& QLCNIC_MBX_ASYNC_EVENT
) {
928 __qlcnic_83xx_process_aen(adapter
);
930 if (atomic_read(&mbx
->rsp_status
) != rsp_status
)
931 qlcnic_83xx_notify_mbx_response(mbx
);
934 spin_unlock_irqrestore(&mbx
->aen_lock
, flags
);
937 static void qlcnic_83xx_mbx_poll_work(struct work_struct
*work
)
939 struct qlcnic_adapter
*adapter
;
941 adapter
= container_of(work
, struct qlcnic_adapter
, mbx_poll_work
.work
);
943 if (!test_bit(__QLCNIC_MBX_POLL_ENABLE
, &adapter
->state
))
946 qlcnic_83xx_process_aen(adapter
);
947 queue_delayed_work(adapter
->qlcnic_wq
, &adapter
->mbx_poll_work
,
951 void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter
*adapter
)
953 if (test_and_set_bit(__QLCNIC_MBX_POLL_ENABLE
, &adapter
->state
))
956 INIT_DELAYED_WORK(&adapter
->mbx_poll_work
, qlcnic_83xx_mbx_poll_work
);
957 queue_delayed_work(adapter
->qlcnic_wq
, &adapter
->mbx_poll_work
, 0);
960 void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter
*adapter
)
962 if (!test_and_clear_bit(__QLCNIC_MBX_POLL_ENABLE
, &adapter
->state
))
964 cancel_delayed_work_sync(&adapter
->mbx_poll_work
);
967 static int qlcnic_83xx_add_rings(struct qlcnic_adapter
*adapter
)
969 int index
, i
, err
, sds_mbx_size
;
970 u32
*buf
, intrpt_id
, intr_mask
;
973 struct qlcnic_cmd_args cmd
;
974 struct qlcnic_host_sds_ring
*sds
;
975 struct qlcnic_sds_mbx sds_mbx
;
976 struct qlcnic_add_rings_mbx_out
*mbx_out
;
977 struct qlcnic_recv_context
*recv_ctx
= adapter
->recv_ctx
;
978 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
980 sds_mbx_size
= sizeof(struct qlcnic_sds_mbx
);
981 context_id
= recv_ctx
->context_id
;
982 num_sds
= (adapter
->max_sds_rings
- QLCNIC_MAX_RING_SETS
);
983 ahw
->hw_ops
->alloc_mbx_args(&cmd
, adapter
,
984 QLCNIC_CMD_ADD_RCV_RINGS
);
985 cmd
.req
.arg
[1] = 0 | (num_sds
<< 8) | (context_id
<< 16);
987 /* set up status rings, mbx 2-81 */
989 for (i
= 8; i
< adapter
->max_sds_rings
; i
++) {
990 memset(&sds_mbx
, 0, sds_mbx_size
);
991 sds
= &recv_ctx
->sds_rings
[i
];
993 memset(sds
->desc_head
, 0, STATUS_DESC_RINGSIZE(sds
));
994 sds_mbx
.phy_addr_low
= LSD(sds
->phys_addr
);
995 sds_mbx
.phy_addr_high
= MSD(sds
->phys_addr
);
996 sds_mbx
.sds_ring_size
= sds
->num_desc
;
998 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
999 intrpt_id
= ahw
->intr_tbl
[i
].id
;
1001 intrpt_id
= QLCRDX(ahw
, QLCNIC_DEF_INT_ID
);
1003 if (adapter
->ahw
->diag_test
!= QLCNIC_LOOPBACK_TEST
)
1004 sds_mbx
.intrpt_id
= intrpt_id
;
1006 sds_mbx
.intrpt_id
= 0xffff;
1007 sds_mbx
.intrpt_val
= 0;
1008 buf
= &cmd
.req
.arg
[index
];
1009 memcpy(buf
, &sds_mbx
, sds_mbx_size
);
1010 index
+= sds_mbx_size
/ sizeof(u32
);
1013 /* send the mailbox command */
1014 err
= ahw
->hw_ops
->mbx_cmd(adapter
, &cmd
);
1016 dev_err(&adapter
->pdev
->dev
,
1017 "Failed to add rings %d\n", err
);
1021 mbx_out
= (struct qlcnic_add_rings_mbx_out
*)&cmd
.rsp
.arg
[1];
1023 /* status descriptor ring */
1024 for (i
= 8; i
< adapter
->max_sds_rings
; i
++) {
1025 sds
= &recv_ctx
->sds_rings
[i
];
1026 sds
->crb_sts_consumer
= ahw
->pci_base0
+
1027 mbx_out
->host_csmr
[index
];
1028 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
1029 intr_mask
= ahw
->intr_tbl
[i
].src
;
1031 intr_mask
= QLCRDX(ahw
, QLCNIC_DEF_INT_MASK
);
1033 sds
->crb_intr_mask
= ahw
->pci_base0
+ intr_mask
;
1037 qlcnic_free_mbx_args(&cmd
);
1041 void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter
*adapter
)
1045 struct qlcnic_cmd_args cmd
;
1046 struct qlcnic_recv_context
*recv_ctx
= adapter
->recv_ctx
;
1048 if (qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_DESTROY_RX_CTX
))
1051 if (qlcnic_sriov_pf_check(adapter
) || qlcnic_sriov_vf_check(adapter
))
1052 cmd
.req
.arg
[0] |= (0x3 << 29);
1054 if (qlcnic_sriov_pf_check(adapter
))
1055 qlcnic_pf_set_interface_id_del_rx_ctx(adapter
, &temp
);
1057 cmd
.req
.arg
[1] = recv_ctx
->context_id
| temp
;
1058 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1060 dev_err(&adapter
->pdev
->dev
,
1061 "Failed to destroy rx ctx in firmware\n");
1063 recv_ctx
->state
= QLCNIC_HOST_CTX_STATE_FREED
;
1064 qlcnic_free_mbx_args(&cmd
);
1067 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter
*adapter
)
1069 int i
, err
, index
, sds_mbx_size
, rds_mbx_size
;
1070 u8 num_sds
, num_rds
;
1071 u32
*buf
, intrpt_id
, intr_mask
, cap
= 0;
1072 struct qlcnic_host_sds_ring
*sds
;
1073 struct qlcnic_host_rds_ring
*rds
;
1074 struct qlcnic_sds_mbx sds_mbx
;
1075 struct qlcnic_rds_mbx rds_mbx
;
1076 struct qlcnic_cmd_args cmd
;
1077 struct qlcnic_rcv_mbx_out
*mbx_out
;
1078 struct qlcnic_recv_context
*recv_ctx
= adapter
->recv_ctx
;
1079 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
1080 num_rds
= adapter
->max_rds_rings
;
1082 if (adapter
->max_sds_rings
<= QLCNIC_MAX_RING_SETS
)
1083 num_sds
= adapter
->max_sds_rings
;
1085 num_sds
= QLCNIC_MAX_RING_SETS
;
1087 sds_mbx_size
= sizeof(struct qlcnic_sds_mbx
);
1088 rds_mbx_size
= sizeof(struct qlcnic_rds_mbx
);
1089 cap
= QLCNIC_CAP0_LEGACY_CONTEXT
;
1091 if (adapter
->flags
& QLCNIC_FW_LRO_MSS_CAP
)
1092 cap
|= QLC_83XX_FW_CAP_LRO_MSS
;
1094 /* set mailbox hdr and capabilities */
1095 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
1096 QLCNIC_CMD_CREATE_RX_CTX
);
1100 if (qlcnic_sriov_pf_check(adapter
) || qlcnic_sriov_vf_check(adapter
))
1101 cmd
.req
.arg
[0] |= (0x3 << 29);
1103 cmd
.req
.arg
[1] = cap
;
1104 cmd
.req
.arg
[5] = 1 | (num_rds
<< 5) | (num_sds
<< 8) |
1105 (QLC_83XX_HOST_RDS_MODE_UNIQUE
<< 16);
1107 if (qlcnic_sriov_pf_check(adapter
))
1108 qlcnic_pf_set_interface_id_create_rx_ctx(adapter
,
1110 /* set up status rings, mbx 8-57/87 */
1111 index
= QLC_83XX_HOST_SDS_MBX_IDX
;
1112 for (i
= 0; i
< num_sds
; i
++) {
1113 memset(&sds_mbx
, 0, sds_mbx_size
);
1114 sds
= &recv_ctx
->sds_rings
[i
];
1116 memset(sds
->desc_head
, 0, STATUS_DESC_RINGSIZE(sds
));
1117 sds_mbx
.phy_addr_low
= LSD(sds
->phys_addr
);
1118 sds_mbx
.phy_addr_high
= MSD(sds
->phys_addr
);
1119 sds_mbx
.sds_ring_size
= sds
->num_desc
;
1120 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
1121 intrpt_id
= ahw
->intr_tbl
[i
].id
;
1123 intrpt_id
= QLCRDX(ahw
, QLCNIC_DEF_INT_ID
);
1124 if (adapter
->ahw
->diag_test
!= QLCNIC_LOOPBACK_TEST
)
1125 sds_mbx
.intrpt_id
= intrpt_id
;
1127 sds_mbx
.intrpt_id
= 0xffff;
1128 sds_mbx
.intrpt_val
= 0;
1129 buf
= &cmd
.req
.arg
[index
];
1130 memcpy(buf
, &sds_mbx
, sds_mbx_size
);
1131 index
+= sds_mbx_size
/ sizeof(u32
);
1133 /* set up receive rings, mbx 88-111/135 */
1134 index
= QLCNIC_HOST_RDS_MBX_IDX
;
1135 rds
= &recv_ctx
->rds_rings
[0];
1137 memset(&rds_mbx
, 0, rds_mbx_size
);
1138 rds_mbx
.phy_addr_reg_low
= LSD(rds
->phys_addr
);
1139 rds_mbx
.phy_addr_reg_high
= MSD(rds
->phys_addr
);
1140 rds_mbx
.reg_ring_sz
= rds
->dma_size
;
1141 rds_mbx
.reg_ring_len
= rds
->num_desc
;
1143 rds
= &recv_ctx
->rds_rings
[1];
1145 rds_mbx
.phy_addr_jmb_low
= LSD(rds
->phys_addr
);
1146 rds_mbx
.phy_addr_jmb_high
= MSD(rds
->phys_addr
);
1147 rds_mbx
.jmb_ring_sz
= rds
->dma_size
;
1148 rds_mbx
.jmb_ring_len
= rds
->num_desc
;
1149 buf
= &cmd
.req
.arg
[index
];
1150 memcpy(buf
, &rds_mbx
, rds_mbx_size
);
1152 /* send the mailbox command */
1153 err
= ahw
->hw_ops
->mbx_cmd(adapter
, &cmd
);
1155 dev_err(&adapter
->pdev
->dev
,
1156 "Failed to create Rx ctx in firmware%d\n", err
);
1159 mbx_out
= (struct qlcnic_rcv_mbx_out
*)&cmd
.rsp
.arg
[1];
1160 recv_ctx
->context_id
= mbx_out
->ctx_id
;
1161 recv_ctx
->state
= mbx_out
->state
;
1162 recv_ctx
->virt_port
= mbx_out
->vport_id
;
1163 dev_info(&adapter
->pdev
->dev
, "Rx Context[%d] Created, state:0x%x\n",
1164 recv_ctx
->context_id
, recv_ctx
->state
);
1165 /* Receive descriptor ring */
1167 rds
= &recv_ctx
->rds_rings
[0];
1168 rds
->crb_rcv_producer
= ahw
->pci_base0
+
1169 mbx_out
->host_prod
[0].reg_buf
;
1171 rds
= &recv_ctx
->rds_rings
[1];
1172 rds
->crb_rcv_producer
= ahw
->pci_base0
+
1173 mbx_out
->host_prod
[0].jmb_buf
;
1174 /* status descriptor ring */
1175 for (i
= 0; i
< num_sds
; i
++) {
1176 sds
= &recv_ctx
->sds_rings
[i
];
1177 sds
->crb_sts_consumer
= ahw
->pci_base0
+
1178 mbx_out
->host_csmr
[i
];
1179 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
1180 intr_mask
= ahw
->intr_tbl
[i
].src
;
1182 intr_mask
= QLCRDX(ahw
, QLCNIC_DEF_INT_MASK
);
1183 sds
->crb_intr_mask
= ahw
->pci_base0
+ intr_mask
;
1186 if (adapter
->max_sds_rings
> QLCNIC_MAX_RING_SETS
)
1187 err
= qlcnic_83xx_add_rings(adapter
);
1189 qlcnic_free_mbx_args(&cmd
);
1193 void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter
*adapter
,
1194 struct qlcnic_host_tx_ring
*tx_ring
)
1196 struct qlcnic_cmd_args cmd
;
1199 if (qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_DESTROY_TX_CTX
))
1202 if (qlcnic_sriov_pf_check(adapter
) || qlcnic_sriov_vf_check(adapter
))
1203 cmd
.req
.arg
[0] |= (0x3 << 29);
1205 if (qlcnic_sriov_pf_check(adapter
))
1206 qlcnic_pf_set_interface_id_del_tx_ctx(adapter
, &temp
);
1208 cmd
.req
.arg
[1] = tx_ring
->ctx_id
| temp
;
1209 if (qlcnic_issue_cmd(adapter
, &cmd
))
1210 dev_err(&adapter
->pdev
->dev
,
1211 "Failed to destroy tx ctx in firmware\n");
1212 qlcnic_free_mbx_args(&cmd
);
1215 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter
*adapter
,
1216 struct qlcnic_host_tx_ring
*tx
, int ring
)
1220 u32
*buf
, intr_mask
, temp
= 0;
1221 struct qlcnic_cmd_args cmd
;
1222 struct qlcnic_tx_mbx mbx
;
1223 struct qlcnic_tx_mbx_out
*mbx_out
;
1224 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
1227 /* Reset host resources */
1229 tx
->sw_consumer
= 0;
1230 *(tx
->hw_consumer
) = 0;
1232 memset(&mbx
, 0, sizeof(struct qlcnic_tx_mbx
));
1234 /* setup mailbox inbox registerss */
1235 mbx
.phys_addr_low
= LSD(tx
->phys_addr
);
1236 mbx
.phys_addr_high
= MSD(tx
->phys_addr
);
1237 mbx
.cnsmr_index_low
= LSD(tx
->hw_cons_phys_addr
);
1238 mbx
.cnsmr_index_high
= MSD(tx
->hw_cons_phys_addr
);
1239 mbx
.size
= tx
->num_desc
;
1240 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
) {
1241 if (!(adapter
->flags
& QLCNIC_TX_INTR_SHARED
))
1242 msix_vector
= adapter
->max_sds_rings
+ ring
;
1244 msix_vector
= adapter
->max_sds_rings
- 1;
1245 msix_id
= ahw
->intr_tbl
[msix_vector
].id
;
1247 msix_id
= QLCRDX(ahw
, QLCNIC_DEF_INT_ID
);
1250 if (adapter
->ahw
->diag_test
!= QLCNIC_LOOPBACK_TEST
)
1251 mbx
.intr_id
= msix_id
;
1253 mbx
.intr_id
= 0xffff;
1256 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_CREATE_TX_CTX
);
1260 if (qlcnic_sriov_pf_check(adapter
) || qlcnic_sriov_vf_check(adapter
))
1261 cmd
.req
.arg
[0] |= (0x3 << 29);
1263 if (qlcnic_sriov_pf_check(adapter
))
1264 qlcnic_pf_set_interface_id_create_tx_ctx(adapter
, &temp
);
1266 cmd
.req
.arg
[1] = QLCNIC_CAP0_LEGACY_CONTEXT
;
1267 cmd
.req
.arg
[5] = QLCNIC_MAX_TX_QUEUES
| temp
;
1268 buf
= &cmd
.req
.arg
[6];
1269 memcpy(buf
, &mbx
, sizeof(struct qlcnic_tx_mbx
));
1270 /* send the mailbox command*/
1271 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1273 dev_err(&adapter
->pdev
->dev
,
1274 "Failed to create Tx ctx in firmware 0x%x\n", err
);
1277 mbx_out
= (struct qlcnic_tx_mbx_out
*)&cmd
.rsp
.arg
[2];
1278 tx
->crb_cmd_producer
= ahw
->pci_base0
+ mbx_out
->host_prod
;
1279 tx
->ctx_id
= mbx_out
->ctx_id
;
1280 if ((adapter
->flags
& QLCNIC_MSIX_ENABLED
) &&
1281 !(adapter
->flags
& QLCNIC_TX_INTR_SHARED
)) {
1282 intr_mask
= ahw
->intr_tbl
[adapter
->max_sds_rings
+ ring
].src
;
1283 tx
->crb_intr_mask
= ahw
->pci_base0
+ intr_mask
;
1285 dev_info(&adapter
->pdev
->dev
, "Tx Context[0x%x] Created, state:0x%x\n",
1286 tx
->ctx_id
, mbx_out
->state
);
1288 qlcnic_free_mbx_args(&cmd
);
1292 static int qlcnic_83xx_diag_alloc_res(struct net_device
*netdev
, int test
,
1295 struct qlcnic_adapter
*adapter
= netdev_priv(netdev
);
1296 struct qlcnic_host_sds_ring
*sds_ring
;
1297 struct qlcnic_host_rds_ring
*rds_ring
;
1298 u16 adapter_state
= adapter
->is_up
;
1302 netif_device_detach(netdev
);
1304 if (netif_running(netdev
))
1305 __qlcnic_down(adapter
, netdev
);
1307 qlcnic_detach(adapter
);
1309 adapter
->max_sds_rings
= 1;
1310 adapter
->ahw
->diag_test
= test
;
1311 adapter
->ahw
->linkup
= 0;
1313 ret
= qlcnic_attach(adapter
);
1315 netif_device_attach(netdev
);
1319 ret
= qlcnic_fw_create_ctx(adapter
);
1321 qlcnic_detach(adapter
);
1322 if (adapter_state
== QLCNIC_ADAPTER_UP_MAGIC
) {
1323 adapter
->max_sds_rings
= num_sds_ring
;
1324 qlcnic_attach(adapter
);
1326 netif_device_attach(netdev
);
1330 for (ring
= 0; ring
< adapter
->max_rds_rings
; ring
++) {
1331 rds_ring
= &adapter
->recv_ctx
->rds_rings
[ring
];
1332 qlcnic_post_rx_buffers(adapter
, rds_ring
, ring
);
1335 if (adapter
->ahw
->diag_test
== QLCNIC_INTERRUPT_TEST
) {
1336 for (ring
= 0; ring
< adapter
->max_sds_rings
; ring
++) {
1337 sds_ring
= &adapter
->recv_ctx
->sds_rings
[ring
];
1338 qlcnic_83xx_enable_intr(adapter
, sds_ring
);
1342 if (adapter
->ahw
->diag_test
== QLCNIC_LOOPBACK_TEST
) {
1343 /* disable and free mailbox interrupt */
1344 if (!(adapter
->flags
& QLCNIC_MSIX_ENABLED
)) {
1345 qlcnic_83xx_enable_mbx_poll(adapter
);
1346 qlcnic_83xx_free_mbx_intr(adapter
);
1348 adapter
->ahw
->loopback_state
= 0;
1349 adapter
->ahw
->hw_ops
->setup_link_event(adapter
, 1);
1352 set_bit(__QLCNIC_DEV_UP
, &adapter
->state
);
1356 static void qlcnic_83xx_diag_free_res(struct net_device
*netdev
,
1359 struct qlcnic_adapter
*adapter
= netdev_priv(netdev
);
1360 struct qlcnic_host_sds_ring
*sds_ring
;
1363 clear_bit(__QLCNIC_DEV_UP
, &adapter
->state
);
1364 if (adapter
->ahw
->diag_test
== QLCNIC_INTERRUPT_TEST
) {
1365 for (ring
= 0; ring
< adapter
->max_sds_rings
; ring
++) {
1366 sds_ring
= &adapter
->recv_ctx
->sds_rings
[ring
];
1367 qlcnic_83xx_disable_intr(adapter
, sds_ring
);
1368 if (!(adapter
->flags
& QLCNIC_MSIX_ENABLED
))
1369 qlcnic_83xx_enable_mbx_poll(adapter
);
1373 qlcnic_fw_destroy_ctx(adapter
);
1374 qlcnic_detach(adapter
);
1376 if (adapter
->ahw
->diag_test
== QLCNIC_LOOPBACK_TEST
) {
1377 if (!(adapter
->flags
& QLCNIC_MSIX_ENABLED
)) {
1378 err
= qlcnic_83xx_setup_mbx_intr(adapter
);
1379 qlcnic_83xx_disable_mbx_poll(adapter
);
1381 dev_err(&adapter
->pdev
->dev
,
1382 "%s: failed to setup mbx interrupt\n",
1388 adapter
->ahw
->diag_test
= 0;
1389 adapter
->max_sds_rings
= max_sds_rings
;
1391 if (qlcnic_attach(adapter
))
1394 if (netif_running(netdev
))
1395 __qlcnic_up(adapter
, netdev
);
1397 if (adapter
->ahw
->diag_test
== QLCNIC_INTERRUPT_TEST
&&
1398 !(adapter
->flags
& QLCNIC_MSIX_ENABLED
))
1399 qlcnic_83xx_disable_mbx_poll(adapter
);
1401 netif_device_attach(netdev
);
1404 int qlcnic_83xx_config_led(struct qlcnic_adapter
*adapter
, u32 state
,
1407 struct qlcnic_cmd_args cmd
;
1412 /* Get LED configuration */
1413 status
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
1414 QLCNIC_CMD_GET_LED_CONFIG
);
1418 status
= qlcnic_issue_cmd(adapter
, &cmd
);
1420 dev_err(&adapter
->pdev
->dev
,
1421 "Get led config failed.\n");
1424 for (i
= 0; i
< 4; i
++)
1425 adapter
->ahw
->mbox_reg
[i
] = cmd
.rsp
.arg
[i
+1];
1427 qlcnic_free_mbx_args(&cmd
);
1428 /* Set LED Configuration */
1429 mbx_in
= (LSW(QLC_83XX_LED_CONFIG
) << 16) |
1430 LSW(QLC_83XX_LED_CONFIG
);
1431 status
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
1432 QLCNIC_CMD_SET_LED_CONFIG
);
1436 cmd
.req
.arg
[1] = mbx_in
;
1437 cmd
.req
.arg
[2] = mbx_in
;
1438 cmd
.req
.arg
[3] = mbx_in
;
1440 cmd
.req
.arg
[4] = QLC_83XX_ENABLE_BEACON
;
1441 status
= qlcnic_issue_cmd(adapter
, &cmd
);
1443 dev_err(&adapter
->pdev
->dev
,
1444 "Set led config failed.\n");
1447 qlcnic_free_mbx_args(&cmd
);
1451 /* Restoring default LED configuration */
1452 status
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
1453 QLCNIC_CMD_SET_LED_CONFIG
);
1457 cmd
.req
.arg
[1] = adapter
->ahw
->mbox_reg
[0];
1458 cmd
.req
.arg
[2] = adapter
->ahw
->mbox_reg
[1];
1459 cmd
.req
.arg
[3] = adapter
->ahw
->mbox_reg
[2];
1461 cmd
.req
.arg
[4] = adapter
->ahw
->mbox_reg
[3];
1462 status
= qlcnic_issue_cmd(adapter
, &cmd
);
1464 dev_err(&adapter
->pdev
->dev
,
1465 "Restoring led config failed.\n");
1466 qlcnic_free_mbx_args(&cmd
);
1471 int qlcnic_83xx_set_led(struct net_device
*netdev
,
1472 enum ethtool_phys_id_state state
)
1474 struct qlcnic_adapter
*adapter
= netdev_priv(netdev
);
1475 int err
= -EIO
, active
= 1;
1477 if (adapter
->ahw
->op_mode
== QLCNIC_NON_PRIV_FUNC
) {
1479 "LED test is not supported in non-privileged mode\n");
1484 case ETHTOOL_ID_ACTIVE
:
1485 if (test_and_set_bit(__QLCNIC_LED_ENABLE
, &adapter
->state
))
1488 if (test_bit(__QLCNIC_RESETTING
, &adapter
->state
))
1491 err
= qlcnic_83xx_config_led(adapter
, active
, 0);
1493 netdev_err(netdev
, "Failed to set LED blink state\n");
1495 case ETHTOOL_ID_INACTIVE
:
1498 if (test_bit(__QLCNIC_RESETTING
, &adapter
->state
))
1501 err
= qlcnic_83xx_config_led(adapter
, active
, 0);
1503 netdev_err(netdev
, "Failed to reset LED blink state\n");
1511 clear_bit(__QLCNIC_LED_ENABLE
, &adapter
->state
);
1516 void qlcnic_83xx_register_nic_idc_func(struct qlcnic_adapter
*adapter
,
1519 struct qlcnic_cmd_args cmd
;
1522 if (qlcnic_sriov_vf_check(adapter
))
1526 status
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
1527 QLCNIC_CMD_INIT_NIC_FUNC
);
1531 cmd
.req
.arg
[1] = BIT_0
| BIT_31
;
1533 status
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
1534 QLCNIC_CMD_STOP_NIC_FUNC
);
1538 cmd
.req
.arg
[1] = BIT_0
| BIT_31
;
1540 status
= qlcnic_issue_cmd(adapter
, &cmd
);
1542 dev_err(&adapter
->pdev
->dev
,
1543 "Failed to %s in NIC IDC function event.\n",
1544 (enable
? "register" : "unregister"));
1546 qlcnic_free_mbx_args(&cmd
);
1549 int qlcnic_83xx_set_port_config(struct qlcnic_adapter
*adapter
)
1551 struct qlcnic_cmd_args cmd
;
1554 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_SET_PORT_CONFIG
);
1558 cmd
.req
.arg
[1] = adapter
->ahw
->port_config
;
1559 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1561 dev_info(&adapter
->pdev
->dev
, "Set Port Config failed.\n");
1562 qlcnic_free_mbx_args(&cmd
);
1566 int qlcnic_83xx_get_port_config(struct qlcnic_adapter
*adapter
)
1568 struct qlcnic_cmd_args cmd
;
1571 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_GET_PORT_CONFIG
);
1575 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1577 dev_info(&adapter
->pdev
->dev
, "Get Port config failed\n");
1579 adapter
->ahw
->port_config
= cmd
.rsp
.arg
[1];
1580 qlcnic_free_mbx_args(&cmd
);
1584 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter
*adapter
, int enable
)
1588 struct qlcnic_cmd_args cmd
;
1590 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_GET_LINK_EVENT
);
1594 temp
= adapter
->recv_ctx
->context_id
<< 16;
1595 cmd
.req
.arg
[1] = (enable
? 1 : 0) | BIT_8
| temp
;
1596 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1598 dev_info(&adapter
->pdev
->dev
,
1599 "Setup linkevent mailbox failed\n");
1600 qlcnic_free_mbx_args(&cmd
);
1604 static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter
*adapter
,
1607 if (qlcnic_sriov_pf_check(adapter
)) {
1608 qlcnic_pf_set_interface_id_promisc(adapter
, interface_id
);
1610 if (!qlcnic_sriov_vf_check(adapter
))
1611 *interface_id
= adapter
->recv_ctx
->context_id
<< 16;
1615 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter
*adapter
, u32 mode
)
1617 struct qlcnic_cmd_args
*cmd
= NULL
;
1621 if (adapter
->recv_ctx
->state
== QLCNIC_HOST_CTX_STATE_FREED
)
1624 cmd
= kzalloc(sizeof(*cmd
), GFP_ATOMIC
);
1628 err
= qlcnic_alloc_mbx_args(cmd
, adapter
,
1629 QLCNIC_CMD_CONFIGURE_MAC_RX_MODE
);
1633 cmd
->type
= QLC_83XX_MBX_CMD_NO_WAIT
;
1634 qlcnic_83xx_set_interface_id_promisc(adapter
, &temp
);
1635 cmd
->req
.arg
[1] = (mode
? 1 : 0) | temp
;
1636 err
= qlcnic_issue_cmd(adapter
, cmd
);
1640 qlcnic_free_mbx_args(cmd
);
1647 int qlcnic_83xx_loopback_test(struct net_device
*netdev
, u8 mode
)
1649 struct qlcnic_adapter
*adapter
= netdev_priv(netdev
);
1650 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
1651 int ret
= 0, loop
= 0, max_sds_rings
= adapter
->max_sds_rings
;
1653 if (ahw
->op_mode
== QLCNIC_NON_PRIV_FUNC
) {
1655 "Loopback test not supported in non privileged mode\n");
1659 if (test_bit(__QLCNIC_RESETTING
, &adapter
->state
)) {
1660 netdev_info(netdev
, "Device is resetting\n");
1664 if (qlcnic_get_diag_lock(adapter
)) {
1665 netdev_info(netdev
, "Device is in diagnostics mode\n");
1669 netdev_info(netdev
, "%s loopback test in progress\n",
1670 mode
== QLCNIC_ILB_MODE
? "internal" : "external");
1672 ret
= qlcnic_83xx_diag_alloc_res(netdev
, QLCNIC_LOOPBACK_TEST
,
1675 goto fail_diag_alloc
;
1677 ret
= qlcnic_83xx_set_lb_mode(adapter
, mode
);
1681 /* Poll for link up event before running traffic */
1683 msleep(QLC_83XX_LB_MSLEEP_COUNT
);
1685 if (test_bit(__QLCNIC_RESETTING
, &adapter
->state
)) {
1687 "Device is resetting, free LB test resources\n");
1691 if (loop
++ > QLC_83XX_LB_WAIT_COUNT
) {
1693 "Firmware didn't sent link up event to loopback request\n");
1695 qlcnic_83xx_clear_lb_mode(adapter
, mode
);
1698 } while ((adapter
->ahw
->linkup
&& ahw
->has_link_events
) != 1);
1700 /* Make sure carrier is off and queue is stopped during loopback */
1701 if (netif_running(netdev
)) {
1702 netif_carrier_off(netdev
);
1703 netif_tx_stop_all_queues(netdev
);
1706 ret
= qlcnic_do_lb_test(adapter
, mode
);
1708 qlcnic_83xx_clear_lb_mode(adapter
, mode
);
1711 qlcnic_83xx_diag_free_res(netdev
, max_sds_rings
);
1714 adapter
->max_sds_rings
= max_sds_rings
;
1715 qlcnic_release_diag_lock(adapter
);
1719 static void qlcnic_extend_lb_idc_cmpltn_wait(struct qlcnic_adapter
*adapter
,
1720 u32
*max_wait_count
)
1722 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
1725 netdev_info(adapter
->netdev
, "Recieved loopback IDC time extend event for 0x%x seconds\n",
1726 ahw
->extend_lb_time
);
1727 temp
= ahw
->extend_lb_time
* 1000;
1728 *max_wait_count
+= temp
/ QLC_83XX_LB_MSLEEP_COUNT
;
1729 ahw
->extend_lb_time
= 0;
1732 int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter
*adapter
, u8 mode
)
1734 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
1735 struct net_device
*netdev
= adapter
->netdev
;
1736 u32 config
, max_wait_count
;
1737 int status
= 0, loop
= 0;
1739 ahw
->extend_lb_time
= 0;
1740 max_wait_count
= QLC_83XX_LB_WAIT_COUNT
;
1741 status
= qlcnic_83xx_get_port_config(adapter
);
1745 config
= ahw
->port_config
;
1747 /* Check if port is already in loopback mode */
1748 if ((config
& QLC_83XX_CFG_LOOPBACK_HSS
) ||
1749 (config
& QLC_83XX_CFG_LOOPBACK_EXT
)) {
1751 "Port already in Loopback mode.\n");
1752 return -EINPROGRESS
;
1755 set_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
);
1757 if (mode
== QLCNIC_ILB_MODE
)
1758 ahw
->port_config
|= QLC_83XX_CFG_LOOPBACK_HSS
;
1759 if (mode
== QLCNIC_ELB_MODE
)
1760 ahw
->port_config
|= QLC_83XX_CFG_LOOPBACK_EXT
;
1762 status
= qlcnic_83xx_set_port_config(adapter
);
1765 "Failed to Set Loopback Mode = 0x%x.\n",
1767 ahw
->port_config
= config
;
1768 clear_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
);
1772 /* Wait for Link and IDC Completion AEN */
1774 msleep(QLC_83XX_LB_MSLEEP_COUNT
);
1776 if (test_bit(__QLCNIC_RESETTING
, &adapter
->state
)) {
1778 "Device is resetting, free LB test resources\n");
1779 clear_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
);
1783 if (ahw
->extend_lb_time
)
1784 qlcnic_extend_lb_idc_cmpltn_wait(adapter
,
1787 if (loop
++ > max_wait_count
) {
1788 netdev_err(netdev
, "%s: Did not receive loopback IDC completion AEN\n",
1790 clear_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
);
1791 qlcnic_83xx_clear_lb_mode(adapter
, mode
);
1794 } while (test_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
));
1796 qlcnic_sre_macaddr_change(adapter
, adapter
->mac_addr
, 0,
1801 int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter
*adapter
, u8 mode
)
1803 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
1804 u32 config
= ahw
->port_config
, max_wait_count
;
1805 struct net_device
*netdev
= adapter
->netdev
;
1806 int status
= 0, loop
= 0;
1808 ahw
->extend_lb_time
= 0;
1809 max_wait_count
= QLC_83XX_LB_WAIT_COUNT
;
1810 set_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
);
1811 if (mode
== QLCNIC_ILB_MODE
)
1812 ahw
->port_config
&= ~QLC_83XX_CFG_LOOPBACK_HSS
;
1813 if (mode
== QLCNIC_ELB_MODE
)
1814 ahw
->port_config
&= ~QLC_83XX_CFG_LOOPBACK_EXT
;
1816 status
= qlcnic_83xx_set_port_config(adapter
);
1819 "Failed to Clear Loopback Mode = 0x%x.\n",
1821 ahw
->port_config
= config
;
1822 clear_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
);
1826 /* Wait for Link and IDC Completion AEN */
1828 msleep(QLC_83XX_LB_MSLEEP_COUNT
);
1830 if (test_bit(__QLCNIC_RESETTING
, &adapter
->state
)) {
1832 "Device is resetting, free LB test resources\n");
1833 clear_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
);
1837 if (ahw
->extend_lb_time
)
1838 qlcnic_extend_lb_idc_cmpltn_wait(adapter
,
1841 if (loop
++ > max_wait_count
) {
1842 netdev_err(netdev
, "%s: Did not receive loopback IDC completion AEN\n",
1844 clear_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
);
1847 } while (test_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
));
1849 qlcnic_sre_macaddr_change(adapter
, adapter
->mac_addr
, 0,
1854 static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter
*adapter
,
1857 if (qlcnic_sriov_pf_check(adapter
)) {
1858 qlcnic_pf_set_interface_id_ipaddr(adapter
, interface_id
);
1860 if (!qlcnic_sriov_vf_check(adapter
))
1861 *interface_id
= adapter
->recv_ctx
->context_id
<< 16;
1865 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter
*adapter
, __be32 ip
,
1869 u32 temp
= 0, temp_ip
;
1870 struct qlcnic_cmd_args cmd
;
1872 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
1873 QLCNIC_CMD_CONFIGURE_IP_ADDR
);
1877 qlcnic_83xx_set_interface_id_ipaddr(adapter
, &temp
);
1879 if (mode
== QLCNIC_IP_UP
)
1880 cmd
.req
.arg
[1] = 1 | temp
;
1882 cmd
.req
.arg
[1] = 2 | temp
;
1885 * Adapter needs IP address in network byte order.
1886 * But hardware mailbox registers go through writel(), hence IP address
1887 * gets swapped on big endian architecture.
1888 * To negate swapping of writel() on big endian architecture
1889 * use swab32(value).
1892 temp_ip
= swab32(ntohl(ip
));
1893 memcpy(&cmd
.req
.arg
[2], &temp_ip
, sizeof(u32
));
1894 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1895 if (err
!= QLCNIC_RCODE_SUCCESS
)
1896 dev_err(&adapter
->netdev
->dev
,
1897 "could not notify %s IP 0x%x request\n",
1898 (mode
== QLCNIC_IP_UP
) ? "Add" : "Remove", ip
);
1900 qlcnic_free_mbx_args(&cmd
);
1903 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter
*adapter
, int mode
)
1907 struct qlcnic_cmd_args cmd
;
1910 lro_bit_mask
= (mode
? (BIT_0
| BIT_1
| BIT_2
| BIT_3
) : 0);
1912 if (adapter
->recv_ctx
->state
== QLCNIC_HOST_CTX_STATE_FREED
)
1915 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_CONFIGURE_HW_LRO
);
1919 temp
= adapter
->recv_ctx
->context_id
<< 16;
1920 arg1
= lro_bit_mask
| temp
;
1921 cmd
.req
.arg
[1] = arg1
;
1923 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1925 dev_info(&adapter
->pdev
->dev
, "LRO config failed\n");
1926 qlcnic_free_mbx_args(&cmd
);
1931 int qlcnic_83xx_config_rss(struct qlcnic_adapter
*adapter
, int enable
)
1935 struct qlcnic_cmd_args cmd
;
1936 const u64 key
[] = { 0xbeac01fa6a42b73bULL
, 0x8030f20c77cb2da3ULL
,
1937 0xae7b30b4d0ca2bcbULL
, 0x43a38fb04167253dULL
,
1938 0x255b0ec26d5a56daULL
};
1940 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_CONFIGURE_RSS
);
1946 * 5-4: hash_type_ipv4
1947 * 7-6: hash_type_ipv6
1949 * 9: use indirection table
1950 * 16-31: indirection table mask
1952 word
= ((u32
)(RSS_HASHTYPE_IP_TCP
& 0x3) << 4) |
1953 ((u32
)(RSS_HASHTYPE_IP_TCP
& 0x3) << 6) |
1954 ((u32
)(enable
& 0x1) << 8) |
1956 cmd
.req
.arg
[1] = (adapter
->recv_ctx
->context_id
);
1957 cmd
.req
.arg
[2] = word
;
1958 memcpy(&cmd
.req
.arg
[4], key
, sizeof(key
));
1960 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1963 dev_info(&adapter
->pdev
->dev
, "RSS config failed\n");
1964 qlcnic_free_mbx_args(&cmd
);
1970 static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter
*adapter
,
1973 if (qlcnic_sriov_pf_check(adapter
)) {
1974 qlcnic_pf_set_interface_id_macaddr(adapter
, interface_id
);
1976 if (!qlcnic_sriov_vf_check(adapter
))
1977 *interface_id
= adapter
->recv_ctx
->context_id
<< 16;
1981 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter
*adapter
, u8
*addr
,
1984 struct qlcnic_cmd_args
*cmd
= NULL
;
1985 struct qlcnic_macvlan_mbx mv
;
1989 if (adapter
->recv_ctx
->state
== QLCNIC_HOST_CTX_STATE_FREED
)
1992 cmd
= kzalloc(sizeof(*cmd
), GFP_ATOMIC
);
1996 err
= qlcnic_alloc_mbx_args(cmd
, adapter
, QLCNIC_CMD_CONFIG_MAC_VLAN
);
2000 cmd
->type
= QLC_83XX_MBX_CMD_NO_WAIT
;
2003 op
= (op
== QLCNIC_MAC_ADD
|| op
== QLCNIC_MAC_VLAN_ADD
) ?
2004 QLCNIC_MAC_VLAN_ADD
: QLCNIC_MAC_VLAN_DEL
;
2006 cmd
->req
.arg
[1] = op
| (1 << 8);
2007 qlcnic_83xx_set_interface_id_macaddr(adapter
, &temp
);
2008 cmd
->req
.arg
[1] |= temp
;
2010 mv
.mac_addr0
= addr
[0];
2011 mv
.mac_addr1
= addr
[1];
2012 mv
.mac_addr2
= addr
[2];
2013 mv
.mac_addr3
= addr
[3];
2014 mv
.mac_addr4
= addr
[4];
2015 mv
.mac_addr5
= addr
[5];
2016 buf
= &cmd
->req
.arg
[2];
2017 memcpy(buf
, &mv
, sizeof(struct qlcnic_macvlan_mbx
));
2018 err
= qlcnic_issue_cmd(adapter
, cmd
);
2022 qlcnic_free_mbx_args(cmd
);
2028 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter
*adapter
, u64
*addr
,
2032 memcpy(&mac
, addr
, ETH_ALEN
);
2033 qlcnic_83xx_sre_macaddr_change(adapter
, mac
, vlan_id
, QLCNIC_MAC_ADD
);
2036 void qlcnic_83xx_configure_mac(struct qlcnic_adapter
*adapter
, u8
*mac
,
2037 u8 type
, struct qlcnic_cmd_args
*cmd
)
2040 case QLCNIC_SET_STATION_MAC
:
2041 case QLCNIC_SET_FAC_DEF_MAC
:
2042 memcpy(&cmd
->req
.arg
[2], mac
, sizeof(u32
));
2043 memcpy(&cmd
->req
.arg
[3], &mac
[4], sizeof(u16
));
2046 cmd
->req
.arg
[1] = type
;
2049 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter
*adapter
, u8
*mac
,
2053 struct qlcnic_cmd_args cmd
;
2054 u32 mac_low
, mac_high
;
2057 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_MAC_ADDRESS
);
2061 qlcnic_83xx_configure_mac(adapter
, mac
, QLCNIC_GET_CURRENT_MAC
, &cmd
);
2062 err
= qlcnic_issue_cmd(adapter
, &cmd
);
2064 if (err
== QLCNIC_RCODE_SUCCESS
) {
2065 mac_low
= cmd
.rsp
.arg
[1];
2066 mac_high
= cmd
.rsp
.arg
[2];
2068 for (i
= 0; i
< 2; i
++)
2069 mac
[i
] = (u8
) (mac_high
>> ((1 - i
) * 8));
2070 for (i
= 2; i
< 6; i
++)
2071 mac
[i
] = (u8
) (mac_low
>> ((5 - i
) * 8));
2073 dev_err(&adapter
->pdev
->dev
, "Failed to get mac address%d\n",
2077 qlcnic_free_mbx_args(&cmd
);
2081 void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter
*adapter
)
2085 struct qlcnic_cmd_args cmd
;
2086 struct qlcnic_nic_intr_coalesce
*coal
= &adapter
->ahw
->coal
;
2088 if (adapter
->recv_ctx
->state
== QLCNIC_HOST_CTX_STATE_FREED
)
2091 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_CONFIG_INTR_COAL
);
2095 if (coal
->type
== QLCNIC_INTR_COAL_TYPE_RX
) {
2096 temp
= adapter
->recv_ctx
->context_id
;
2097 cmd
.req
.arg
[1] = QLCNIC_INTR_COAL_TYPE_RX
| temp
<< 16;
2098 temp
= coal
->rx_time_us
;
2099 cmd
.req
.arg
[2] = coal
->rx_packets
| temp
<< 16;
2100 } else if (coal
->type
== QLCNIC_INTR_COAL_TYPE_TX
) {
2101 temp
= adapter
->tx_ring
->ctx_id
;
2102 cmd
.req
.arg
[1] = QLCNIC_INTR_COAL_TYPE_TX
| temp
<< 16;
2103 temp
= coal
->tx_time_us
;
2104 cmd
.req
.arg
[2] = coal
->tx_packets
| temp
<< 16;
2106 cmd
.req
.arg
[3] = coal
->flag
;
2107 err
= qlcnic_issue_cmd(adapter
, &cmd
);
2108 if (err
!= QLCNIC_RCODE_SUCCESS
)
2109 dev_info(&adapter
->pdev
->dev
,
2110 "Failed to send interrupt coalescence parameters\n");
2111 qlcnic_free_mbx_args(&cmd
);
2114 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter
*adapter
,
2117 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
2118 u8 link_status
, duplex
;
2120 link_status
= LSB(data
[3]) & 1;
2122 ahw
->link_speed
= MSW(data
[2]);
2123 duplex
= LSB(MSW(data
[3]));
2125 ahw
->link_duplex
= DUPLEX_FULL
;
2127 ahw
->link_duplex
= DUPLEX_HALF
;
2129 ahw
->link_speed
= SPEED_UNKNOWN
;
2130 ahw
->link_duplex
= DUPLEX_UNKNOWN
;
2133 ahw
->link_autoneg
= MSB(MSW(data
[3]));
2134 ahw
->module_type
= MSB(LSW(data
[3]));
2135 ahw
->has_link_events
= 1;
2136 qlcnic_advert_link_change(adapter
, link_status
);
2139 irqreturn_t
qlcnic_83xx_handle_aen(int irq
, void *data
)
2141 struct qlcnic_adapter
*adapter
= data
;
2142 struct qlcnic_mailbox
*mbx
;
2143 u32 mask
, resp
, event
;
2144 unsigned long flags
;
2146 mbx
= adapter
->ahw
->mailbox
;
2147 spin_lock_irqsave(&mbx
->aen_lock
, flags
);
2148 resp
= QLCRDX(adapter
->ahw
, QLCNIC_FW_MBX_CTRL
);
2149 if (!(resp
& QLCNIC_SET_OWNER
))
2152 event
= readl(QLCNIC_MBX_FW(adapter
->ahw
, 0));
2153 if (event
& QLCNIC_MBX_ASYNC_EVENT
)
2154 __qlcnic_83xx_process_aen(adapter
);
2156 qlcnic_83xx_notify_mbx_response(mbx
);
2159 mask
= QLCRDX(adapter
->ahw
, QLCNIC_DEF_INT_MASK
);
2160 writel(0, adapter
->ahw
->pci_base0
+ mask
);
2161 spin_unlock_irqrestore(&mbx
->aen_lock
, flags
);
2165 int qlcnic_enable_eswitch(struct qlcnic_adapter
*adapter
, u8 port
, u8 enable
)
2168 struct qlcnic_cmd_args cmd
;
2170 if (adapter
->ahw
->op_mode
!= QLCNIC_MGMT_FUNC
) {
2171 dev_err(&adapter
->pdev
->dev
,
2172 "%s: Error, invoked by non management func\n",
2177 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_TOGGLE_ESWITCH
);
2181 cmd
.req
.arg
[1] = (port
& 0xf) | BIT_4
;
2182 err
= qlcnic_issue_cmd(adapter
, &cmd
);
2184 if (err
!= QLCNIC_RCODE_SUCCESS
) {
2185 dev_err(&adapter
->pdev
->dev
, "Failed to enable eswitch%d\n",
2189 qlcnic_free_mbx_args(&cmd
);
2195 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter
*adapter
,
2196 struct qlcnic_info
*nic
)
2199 struct qlcnic_cmd_args cmd
;
2201 if (adapter
->ahw
->op_mode
!= QLCNIC_MGMT_FUNC
) {
2202 dev_err(&adapter
->pdev
->dev
,
2203 "%s: Error, invoked by non management func\n",
2208 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_SET_NIC_INFO
);
2212 cmd
.req
.arg
[1] = (nic
->pci_func
<< 16);
2213 cmd
.req
.arg
[2] = 0x1 << 16;
2214 cmd
.req
.arg
[3] = nic
->phys_port
| (nic
->switch_mode
<< 16);
2215 cmd
.req
.arg
[4] = nic
->capabilities
;
2216 cmd
.req
.arg
[5] = (nic
->max_mac_filters
& 0xFF) | ((nic
->max_mtu
) << 16);
2217 cmd
.req
.arg
[6] = (nic
->max_tx_ques
) | ((nic
->max_rx_ques
) << 16);
2218 cmd
.req
.arg
[7] = (nic
->min_tx_bw
) | ((nic
->max_tx_bw
) << 16);
2219 for (i
= 8; i
< 32; i
++)
2222 err
= qlcnic_issue_cmd(adapter
, &cmd
);
2224 if (err
!= QLCNIC_RCODE_SUCCESS
) {
2225 dev_err(&adapter
->pdev
->dev
, "Failed to set nic info%d\n",
2230 qlcnic_free_mbx_args(&cmd
);
2235 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter
*adapter
,
2236 struct qlcnic_info
*npar_info
, u8 func_id
)
2241 struct qlcnic_cmd_args cmd
;
2242 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
2244 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_GET_NIC_INFO
);
2248 if (func_id
!= ahw
->pci_func
) {
2249 temp
= func_id
<< 16;
2250 cmd
.req
.arg
[1] = op
| BIT_31
| temp
;
2252 cmd
.req
.arg
[1] = ahw
->pci_func
<< 16;
2254 err
= qlcnic_issue_cmd(adapter
, &cmd
);
2256 dev_info(&adapter
->pdev
->dev
,
2257 "Failed to get nic info %d\n", err
);
2261 npar_info
->op_type
= cmd
.rsp
.arg
[1];
2262 npar_info
->pci_func
= cmd
.rsp
.arg
[2] & 0xFFFF;
2263 npar_info
->op_mode
= (cmd
.rsp
.arg
[2] & 0xFFFF0000) >> 16;
2264 npar_info
->phys_port
= cmd
.rsp
.arg
[3] & 0xFFFF;
2265 npar_info
->switch_mode
= (cmd
.rsp
.arg
[3] & 0xFFFF0000) >> 16;
2266 npar_info
->capabilities
= cmd
.rsp
.arg
[4];
2267 npar_info
->max_mac_filters
= cmd
.rsp
.arg
[5] & 0xFF;
2268 npar_info
->max_mtu
= (cmd
.rsp
.arg
[5] & 0xFFFF0000) >> 16;
2269 npar_info
->max_tx_ques
= cmd
.rsp
.arg
[6] & 0xFFFF;
2270 npar_info
->max_rx_ques
= (cmd
.rsp
.arg
[6] & 0xFFFF0000) >> 16;
2271 npar_info
->min_tx_bw
= cmd
.rsp
.arg
[7] & 0xFFFF;
2272 npar_info
->max_tx_bw
= (cmd
.rsp
.arg
[7] & 0xFFFF0000) >> 16;
2273 if (cmd
.rsp
.arg
[8] & 0x1)
2274 npar_info
->max_bw_reg_offset
= (cmd
.rsp
.arg
[8] & 0x7FFE) >> 1;
2275 if (cmd
.rsp
.arg
[8] & 0x10000) {
2276 temp
= (cmd
.rsp
.arg
[8] & 0x7FFE0000) >> 17;
2277 npar_info
->max_linkspeed_reg_offset
= temp
;
2279 if (npar_info
->capabilities
& QLCNIC_FW_CAPABILITY_MORE_CAPS
)
2280 memcpy(ahw
->extra_capability
, &cmd
.rsp
.arg
[16],
2281 sizeof(ahw
->extra_capability
));
2284 qlcnic_free_mbx_args(&cmd
);
2288 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter
*adapter
,
2289 struct qlcnic_pci_info
*pci_info
)
2291 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
2292 struct device
*dev
= &adapter
->pdev
->dev
;
2293 struct qlcnic_cmd_args cmd
;
2294 int i
, err
= 0, j
= 0;
2297 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_GET_PCI_INFO
);
2301 err
= qlcnic_issue_cmd(adapter
, &cmd
);
2303 ahw
->act_pci_func
= 0;
2304 if (err
== QLCNIC_RCODE_SUCCESS
) {
2305 ahw
->max_pci_func
= cmd
.rsp
.arg
[1] & 0xFF;
2306 for (i
= 2, j
= 0; j
< QLCNIC_MAX_PCI_FUNC
; j
++, pci_info
++) {
2307 pci_info
->id
= cmd
.rsp
.arg
[i
] & 0xFFFF;
2308 pci_info
->active
= (cmd
.rsp
.arg
[i
] & 0xFFFF0000) >> 16;
2310 pci_info
->type
= cmd
.rsp
.arg
[i
] & 0xFFFF;
2311 if (pci_info
->type
== QLCNIC_TYPE_NIC
)
2312 ahw
->act_pci_func
++;
2313 temp
= (cmd
.rsp
.arg
[i
] & 0xFFFF0000) >> 16;
2314 pci_info
->default_port
= temp
;
2316 pci_info
->tx_min_bw
= cmd
.rsp
.arg
[i
] & 0xFFFF;
2317 temp
= (cmd
.rsp
.arg
[i
] & 0xFFFF0000) >> 16;
2318 pci_info
->tx_max_bw
= temp
;
2320 memcpy(pci_info
->mac
, &cmd
.rsp
.arg
[i
], ETH_ALEN
- 2);
2322 memcpy(pci_info
->mac
+ sizeof(u32
), &cmd
.rsp
.arg
[i
], 2);
2324 if (ahw
->op_mode
== QLCNIC_MGMT_FUNC
)
2325 dev_info(dev
, "id = %d active = %d type = %d\n"
2326 "\tport = %d min bw = %d max bw = %d\n"
2327 "\tmac_addr = %pM\n", pci_info
->id
,
2328 pci_info
->active
, pci_info
->type
,
2329 pci_info
->default_port
,
2330 pci_info
->tx_min_bw
,
2331 pci_info
->tx_max_bw
, pci_info
->mac
);
2333 if (ahw
->op_mode
== QLCNIC_MGMT_FUNC
)
2334 dev_info(dev
, "Max functions = %d, active functions = %d\n",
2335 ahw
->max_pci_func
, ahw
->act_pci_func
);
2338 dev_err(dev
, "Failed to get PCI Info, error = %d\n", err
);
2342 qlcnic_free_mbx_args(&cmd
);
2347 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter
*adapter
, bool op_type
)
2351 u32 val
, temp
, type
;
2352 struct qlcnic_cmd_args cmd
;
2354 max_ints
= adapter
->ahw
->num_msix
- 1;
2355 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_CONFIG_INTRPT
);
2359 cmd
.req
.arg
[1] = max_ints
;
2361 if (qlcnic_sriov_vf_check(adapter
))
2362 cmd
.req
.arg
[1] |= (adapter
->ahw
->pci_func
<< 8) | BIT_16
;
2364 for (i
= 0, index
= 2; i
< max_ints
; i
++) {
2365 type
= op_type
? QLCNIC_INTRPT_ADD
: QLCNIC_INTRPT_DEL
;
2366 val
= type
| (adapter
->ahw
->intr_tbl
[i
].type
<< 4);
2367 if (adapter
->ahw
->intr_tbl
[i
].type
== QLCNIC_INTRPT_MSIX
)
2368 val
|= (adapter
->ahw
->intr_tbl
[i
].id
<< 16);
2369 cmd
.req
.arg
[index
++] = val
;
2371 err
= qlcnic_issue_cmd(adapter
, &cmd
);
2373 dev_err(&adapter
->pdev
->dev
,
2374 "Failed to configure interrupts 0x%x\n", err
);
2378 max_ints
= cmd
.rsp
.arg
[1];
2379 for (i
= 0, index
= 2; i
< max_ints
; i
++, index
+= 2) {
2380 val
= cmd
.rsp
.arg
[index
];
2382 dev_info(&adapter
->pdev
->dev
,
2383 "Can't configure interrupt %d\n",
2384 adapter
->ahw
->intr_tbl
[i
].id
);
2388 adapter
->ahw
->intr_tbl
[i
].id
= MSW(val
);
2389 adapter
->ahw
->intr_tbl
[i
].enabled
= 1;
2390 temp
= cmd
.rsp
.arg
[index
+ 1];
2391 adapter
->ahw
->intr_tbl
[i
].src
= temp
;
2393 adapter
->ahw
->intr_tbl
[i
].id
= i
;
2394 adapter
->ahw
->intr_tbl
[i
].enabled
= 0;
2395 adapter
->ahw
->intr_tbl
[i
].src
= 0;
2399 qlcnic_free_mbx_args(&cmd
);
2403 int qlcnic_83xx_lock_flash(struct qlcnic_adapter
*adapter
)
2405 int id
, timeout
= 0;
2408 while (status
== 0) {
2409 status
= QLC_SHARED_REG_RD32(adapter
, QLCNIC_FLASH_LOCK
);
2413 if (++timeout
>= QLC_83XX_FLASH_LOCK_TIMEOUT
) {
2414 id
= QLC_SHARED_REG_RD32(adapter
,
2415 QLCNIC_FLASH_LOCK_OWNER
);
2416 dev_err(&adapter
->pdev
->dev
,
2417 "%s: failed, lock held by %d\n", __func__
, id
);
2420 usleep_range(1000, 2000);
2423 QLC_SHARED_REG_WR32(adapter
, QLCNIC_FLASH_LOCK_OWNER
, adapter
->portnum
);
2427 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter
*adapter
)
2429 QLC_SHARED_REG_RD32(adapter
, QLCNIC_FLASH_UNLOCK
);
2430 QLC_SHARED_REG_WR32(adapter
, QLCNIC_FLASH_LOCK_OWNER
, 0xFF);
2433 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter
*adapter
,
2434 u32 flash_addr
, u8
*p_data
,
2437 u32 word
, range
, flash_offset
, addr
= flash_addr
, ret
;
2438 ulong indirect_add
, direct_window
;
2441 flash_offset
= addr
& (QLCNIC_FLASH_SECTOR_SIZE
- 1);
2443 dev_err(&adapter
->pdev
->dev
, "Illegal addr = 0x%x\n", addr
);
2447 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_DIRECT_WINDOW
,
2450 range
= flash_offset
+ (count
* sizeof(u32
));
2451 /* Check if data is spread across multiple sectors */
2452 if (range
> (QLCNIC_FLASH_SECTOR_SIZE
- 1)) {
2454 /* Multi sector read */
2455 for (i
= 0; i
< count
; i
++) {
2456 indirect_add
= QLC_83XX_FLASH_DIRECT_DATA(addr
);
2457 ret
= QLCRD32(adapter
, indirect_add
, &err
);
2462 *(u32
*)p_data
= word
;
2463 p_data
= p_data
+ 4;
2465 flash_offset
= flash_offset
+ 4;
2467 if (flash_offset
> (QLCNIC_FLASH_SECTOR_SIZE
- 1)) {
2468 direct_window
= QLC_83XX_FLASH_DIRECT_WINDOW
;
2469 /* This write is needed once for each sector */
2470 qlcnic_83xx_wrt_reg_indirect(adapter
,
2477 /* Single sector read */
2478 for (i
= 0; i
< count
; i
++) {
2479 indirect_add
= QLC_83XX_FLASH_DIRECT_DATA(addr
);
2480 ret
= QLCRD32(adapter
, indirect_add
, &err
);
2485 *(u32
*)p_data
= word
;
2486 p_data
= p_data
+ 4;
2494 static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter
*adapter
)
2497 int retries
= QLC_83XX_FLASH_READ_RETRY_COUNT
;
2501 status
= QLCRD32(adapter
, QLC_83XX_FLASH_STATUS
, &err
);
2505 if ((status
& QLC_83XX_FLASH_STATUS_READY
) ==
2506 QLC_83XX_FLASH_STATUS_READY
)
2509 msleep(QLC_83XX_FLASH_STATUS_REG_POLL_DELAY
);
2510 } while (--retries
);
2518 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter
*adapter
)
2522 cmd
= adapter
->ahw
->fdt
.write_statusreg_cmd
;
2523 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
,
2524 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG
| cmd
));
2525 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_WRDATA
,
2526 adapter
->ahw
->fdt
.write_enable_bits
);
2527 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
2528 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL
);
2529 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2536 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter
*adapter
)
2540 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
,
2541 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG
|
2542 adapter
->ahw
->fdt
.write_statusreg_cmd
));
2543 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_WRDATA
,
2544 adapter
->ahw
->fdt
.write_disable_bits
);
2545 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
2546 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL
);
2547 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2554 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter
*adapter
)
2559 if (qlcnic_83xx_lock_flash(adapter
))
2562 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
,
2563 QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL
);
2564 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
2565 QLC_83XX_FLASH_READ_CTRL
);
2566 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2568 qlcnic_83xx_unlock_flash(adapter
);
2572 mfg_id
= QLCRD32(adapter
, QLC_83XX_FLASH_RDDATA
, &err
);
2574 qlcnic_83xx_unlock_flash(adapter
);
2578 adapter
->flash_mfg_id
= (mfg_id
& 0xFF);
2579 qlcnic_83xx_unlock_flash(adapter
);
2584 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter
*adapter
)
2586 int count
, fdt_size
, ret
= 0;
2588 fdt_size
= sizeof(struct qlcnic_fdt
);
2589 count
= fdt_size
/ sizeof(u32
);
2591 if (qlcnic_83xx_lock_flash(adapter
))
2594 memset(&adapter
->ahw
->fdt
, 0, fdt_size
);
2595 ret
= qlcnic_83xx_lockless_flash_read32(adapter
, QLCNIC_FDT_LOCATION
,
2596 (u8
*)&adapter
->ahw
->fdt
,
2599 qlcnic_83xx_unlock_flash(adapter
);
2603 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter
*adapter
,
2604 u32 sector_start_addr
)
2606 u32 reversed_addr
, addr1
, addr2
, cmd
;
2609 if (qlcnic_83xx_lock_flash(adapter
) != 0)
2612 if (adapter
->ahw
->fdt
.mfg_id
== adapter
->flash_mfg_id
) {
2613 ret
= qlcnic_83xx_enable_flash_write(adapter
);
2615 qlcnic_83xx_unlock_flash(adapter
);
2616 dev_err(&adapter
->pdev
->dev
,
2617 "%s failed at %d\n",
2618 __func__
, __LINE__
);
2623 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2625 qlcnic_83xx_unlock_flash(adapter
);
2626 dev_err(&adapter
->pdev
->dev
,
2627 "%s: failed at %d\n", __func__
, __LINE__
);
2631 addr1
= (sector_start_addr
& 0xFF) << 16;
2632 addr2
= (sector_start_addr
& 0xFF0000) >> 16;
2633 reversed_addr
= addr1
| addr2
;
2635 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_WRDATA
,
2637 cmd
= QLC_83XX_FLASH_FDT_ERASE_DEF_SIG
| adapter
->ahw
->fdt
.erase_cmd
;
2638 if (adapter
->ahw
->fdt
.mfg_id
== adapter
->flash_mfg_id
)
2639 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
, cmd
);
2641 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
,
2642 QLC_83XX_FLASH_OEM_ERASE_SIG
);
2643 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
2644 QLC_83XX_FLASH_LAST_ERASE_MS_VAL
);
2646 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2648 qlcnic_83xx_unlock_flash(adapter
);
2649 dev_err(&adapter
->pdev
->dev
,
2650 "%s: failed at %d\n", __func__
, __LINE__
);
2654 if (adapter
->ahw
->fdt
.mfg_id
== adapter
->flash_mfg_id
) {
2655 ret
= qlcnic_83xx_disable_flash_write(adapter
);
2657 qlcnic_83xx_unlock_flash(adapter
);
2658 dev_err(&adapter
->pdev
->dev
,
2659 "%s: failed at %d\n", __func__
, __LINE__
);
2664 qlcnic_83xx_unlock_flash(adapter
);
2669 int qlcnic_83xx_flash_write32(struct qlcnic_adapter
*adapter
, u32 addr
,
2673 u32 addr1
= 0x00800000 | (addr
>> 2);
2675 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
, addr1
);
2676 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_WRDATA
, *p_data
);
2677 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
2678 QLC_83XX_FLASH_LAST_ERASE_MS_VAL
);
2679 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2681 dev_err(&adapter
->pdev
->dev
,
2682 "%s: failed at %d\n", __func__
, __LINE__
);
2689 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter
*adapter
, u32 addr
,
2690 u32
*p_data
, int count
)
2693 int ret
= -EIO
, err
= 0;
2695 if ((count
< QLC_83XX_FLASH_WRITE_MIN
) ||
2696 (count
> QLC_83XX_FLASH_WRITE_MAX
)) {
2697 dev_err(&adapter
->pdev
->dev
,
2698 "%s: Invalid word count\n", __func__
);
2702 temp
= QLCRD32(adapter
, QLC_83XX_FLASH_SPI_CONTROL
, &err
);
2706 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_SPI_CONTROL
,
2707 (temp
| QLC_83XX_FLASH_SPI_CTRL
));
2708 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
,
2709 QLC_83XX_FLASH_ADDR_TEMP_VAL
);
2711 /* First DWORD write */
2712 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_WRDATA
, *p_data
++);
2713 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
2714 QLC_83XX_FLASH_FIRST_MS_PATTERN
);
2715 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2717 dev_err(&adapter
->pdev
->dev
,
2718 "%s: failed at %d\n", __func__
, __LINE__
);
2723 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
,
2724 QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL
);
2725 /* Second to N-1 DWORD writes */
2726 while (count
!= 1) {
2727 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_WRDATA
,
2729 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
2730 QLC_83XX_FLASH_SECOND_MS_PATTERN
);
2731 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2733 dev_err(&adapter
->pdev
->dev
,
2734 "%s: failed at %d\n", __func__
, __LINE__
);
2740 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
,
2741 QLC_83XX_FLASH_ADDR_TEMP_VAL
|
2743 /* Last DWORD write */
2744 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_WRDATA
, *p_data
++);
2745 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
2746 QLC_83XX_FLASH_LAST_MS_PATTERN
);
2747 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2749 dev_err(&adapter
->pdev
->dev
,
2750 "%s: failed at %d\n", __func__
, __LINE__
);
2754 ret
= QLCRD32(adapter
, QLC_83XX_FLASH_SPI_STATUS
, &err
);
2758 if ((ret
& QLC_83XX_FLASH_SPI_CTRL
) == QLC_83XX_FLASH_SPI_CTRL
) {
2759 dev_err(&adapter
->pdev
->dev
, "%s: failed at %d\n",
2760 __func__
, __LINE__
);
2761 /* Operation failed, clear error bit */
2762 temp
= QLCRD32(adapter
, QLC_83XX_FLASH_SPI_CONTROL
, &err
);
2766 qlcnic_83xx_wrt_reg_indirect(adapter
,
2767 QLC_83XX_FLASH_SPI_CONTROL
,
2768 (temp
| QLC_83XX_FLASH_SPI_CTRL
));
2774 static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter
*adapter
)
2778 val
= QLCRDX(adapter
->ahw
, QLC_83XX_RECOVER_DRV_LOCK
);
2780 /* Check if recovery need to be performed by the calling function */
2781 if ((val
& QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK
) == 0) {
2783 val
= val
| ((adapter
->portnum
<< 2) |
2784 QLC_83XX_NEED_DRV_LOCK_RECOVERY
);
2785 QLCWRX(adapter
->ahw
, QLC_83XX_RECOVER_DRV_LOCK
, val
);
2786 dev_info(&adapter
->pdev
->dev
,
2787 "%s: lock recovery initiated\n", __func__
);
2788 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY
);
2789 val
= QLCRDX(adapter
->ahw
, QLC_83XX_RECOVER_DRV_LOCK
);
2790 id
= ((val
>> 2) & 0xF);
2791 if (id
== adapter
->portnum
) {
2792 val
= val
& ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK
;
2793 val
= val
| QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS
;
2794 QLCWRX(adapter
->ahw
, QLC_83XX_RECOVER_DRV_LOCK
, val
);
2795 /* Force release the lock */
2796 QLCRDX(adapter
->ahw
, QLC_83XX_DRV_UNLOCK
);
2797 /* Clear recovery bits */
2799 QLCWRX(adapter
->ahw
, QLC_83XX_RECOVER_DRV_LOCK
, val
);
2800 dev_info(&adapter
->pdev
->dev
,
2801 "%s: lock recovery completed\n", __func__
);
2803 dev_info(&adapter
->pdev
->dev
,
2804 "%s: func %d to resume lock recovery process\n",
2808 dev_info(&adapter
->pdev
->dev
,
2809 "%s: lock recovery initiated by other functions\n",
2814 int qlcnic_83xx_lock_driver(struct qlcnic_adapter
*adapter
)
2816 u32 lock_alive_counter
, val
, id
, i
= 0, status
= 0, temp
= 0;
2817 int max_attempt
= 0;
2819 while (status
== 0) {
2820 status
= QLCRDX(adapter
->ahw
, QLC_83XX_DRV_LOCK
);
2824 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY
);
2828 temp
= QLCRDX(adapter
->ahw
, QLC_83XX_DRV_LOCK_ID
);
2830 if (i
== QLC_83XX_DRV_LOCK_WAIT_COUNTER
) {
2831 val
= QLCRDX(adapter
->ahw
, QLC_83XX_DRV_LOCK_ID
);
2834 dev_info(&adapter
->pdev
->dev
,
2835 "%s: lock to be recovered from %d\n",
2837 qlcnic_83xx_recover_driver_lock(adapter
);
2841 dev_err(&adapter
->pdev
->dev
,
2842 "%s: failed to get lock\n", __func__
);
2847 /* Force exit from while loop after few attempts */
2848 if (max_attempt
== QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT
) {
2849 dev_err(&adapter
->pdev
->dev
,
2850 "%s: failed to get lock\n", __func__
);
2855 val
= QLCRDX(adapter
->ahw
, QLC_83XX_DRV_LOCK_ID
);
2856 lock_alive_counter
= val
>> 8;
2857 lock_alive_counter
++;
2858 val
= lock_alive_counter
<< 8 | adapter
->portnum
;
2859 QLCWRX(adapter
->ahw
, QLC_83XX_DRV_LOCK_ID
, val
);
2864 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter
*adapter
)
2866 u32 val
, lock_alive_counter
, id
;
2868 val
= QLCRDX(adapter
->ahw
, QLC_83XX_DRV_LOCK_ID
);
2870 lock_alive_counter
= val
>> 8;
2872 if (id
!= adapter
->portnum
)
2873 dev_err(&adapter
->pdev
->dev
,
2874 "%s:Warning func %d is unlocking lock owned by %d\n",
2875 __func__
, adapter
->portnum
, id
);
2877 val
= (lock_alive_counter
<< 8) | 0xFF;
2878 QLCWRX(adapter
->ahw
, QLC_83XX_DRV_LOCK_ID
, val
);
2879 QLCRDX(adapter
->ahw
, QLC_83XX_DRV_UNLOCK
);
2882 int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter
*adapter
, u64 addr
,
2883 u32
*data
, u32 count
)
2889 /* Check alignment */
2893 mutex_lock(&adapter
->ahw
->mem_lock
);
2894 qlcnic_83xx_wrt_reg_indirect(adapter
, QLCNIC_MS_ADDR_HI
, 0);
2896 for (i
= 0; i
< count
; i
++, addr
+= 16) {
2897 if (!((ADDR_IN_RANGE(addr
, QLCNIC_ADDR_QDR_NET
,
2898 QLCNIC_ADDR_QDR_NET_MAX
)) ||
2899 (ADDR_IN_RANGE(addr
, QLCNIC_ADDR_DDR_NET
,
2900 QLCNIC_ADDR_DDR_NET_MAX
)))) {
2901 mutex_unlock(&adapter
->ahw
->mem_lock
);
2905 qlcnic_83xx_wrt_reg_indirect(adapter
, QLCNIC_MS_ADDR_LO
, addr
);
2906 qlcnic_83xx_wrt_reg_indirect(adapter
, QLCNIC_MS_WRTDATA_LO
,
2908 qlcnic_83xx_wrt_reg_indirect(adapter
, QLCNIC_MS_WRTDATA_HI
,
2910 qlcnic_83xx_wrt_reg_indirect(adapter
, QLCNIC_MS_WRTDATA_ULO
,
2912 qlcnic_83xx_wrt_reg_indirect(adapter
, QLCNIC_MS_WRTDATA_UHI
,
2914 qlcnic_83xx_wrt_reg_indirect(adapter
, QLCNIC_MS_CTRL
,
2915 QLCNIC_TA_WRITE_ENABLE
);
2916 qlcnic_83xx_wrt_reg_indirect(adapter
, QLCNIC_MS_CTRL
,
2917 QLCNIC_TA_WRITE_START
);
2919 for (j
= 0; j
< MAX_CTL_CHECK
; j
++) {
2920 temp
= QLCRD32(adapter
, QLCNIC_MS_CTRL
, &err
);
2922 mutex_unlock(&adapter
->ahw
->mem_lock
);
2926 if ((temp
& TA_CTL_BUSY
) == 0)
2930 /* Status check failure */
2931 if (j
>= MAX_CTL_CHECK
) {
2932 printk_ratelimited(KERN_WARNING
2933 "MS memory write failed\n");
2934 mutex_unlock(&adapter
->ahw
->mem_lock
);
2939 mutex_unlock(&adapter
->ahw
->mem_lock
);
2944 int qlcnic_83xx_flash_read32(struct qlcnic_adapter
*adapter
, u32 flash_addr
,
2945 u8
*p_data
, int count
)
2947 u32 word
, addr
= flash_addr
, ret
;
2948 ulong indirect_addr
;
2951 if (qlcnic_83xx_lock_flash(adapter
) != 0)
2955 dev_err(&adapter
->pdev
->dev
, "Illegal addr = 0x%x\n", addr
);
2956 qlcnic_83xx_unlock_flash(adapter
);
2960 for (i
= 0; i
< count
; i
++) {
2961 if (qlcnic_83xx_wrt_reg_indirect(adapter
,
2962 QLC_83XX_FLASH_DIRECT_WINDOW
,
2964 qlcnic_83xx_unlock_flash(adapter
);
2968 indirect_addr
= QLC_83XX_FLASH_DIRECT_DATA(addr
);
2969 ret
= QLCRD32(adapter
, indirect_addr
, &err
);
2974 *(u32
*)p_data
= word
;
2975 p_data
= p_data
+ 4;
2979 qlcnic_83xx_unlock_flash(adapter
);
2984 int qlcnic_83xx_test_link(struct qlcnic_adapter
*adapter
)
2988 u32 config
= 0, state
;
2989 struct qlcnic_cmd_args cmd
;
2990 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
2992 if (qlcnic_sriov_vf_check(adapter
))
2993 pci_func
= adapter
->portnum
;
2995 pci_func
= ahw
->pci_func
;
2997 state
= readl(ahw
->pci_base0
+ QLC_83XX_LINK_STATE(pci_func
));
2998 if (!QLC_83xx_FUNC_VAL(state
, pci_func
)) {
2999 dev_info(&adapter
->pdev
->dev
, "link state down\n");
3003 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_GET_LINK_STATUS
);
3007 err
= qlcnic_issue_cmd(adapter
, &cmd
);
3009 dev_info(&adapter
->pdev
->dev
,
3010 "Get Link Status Command failed: 0x%x\n", err
);
3013 config
= cmd
.rsp
.arg
[1];
3014 switch (QLC_83XX_CURRENT_LINK_SPEED(config
)) {
3015 case QLC_83XX_10M_LINK
:
3016 ahw
->link_speed
= SPEED_10
;
3018 case QLC_83XX_100M_LINK
:
3019 ahw
->link_speed
= SPEED_100
;
3021 case QLC_83XX_1G_LINK
:
3022 ahw
->link_speed
= SPEED_1000
;
3024 case QLC_83XX_10G_LINK
:
3025 ahw
->link_speed
= SPEED_10000
;
3028 ahw
->link_speed
= 0;
3031 config
= cmd
.rsp
.arg
[3];
3032 if (QLC_83XX_SFP_PRESENT(config
)) {
3033 switch (ahw
->module_type
) {
3034 case LINKEVENT_MODULE_OPTICAL_UNKNOWN
:
3035 case LINKEVENT_MODULE_OPTICAL_SRLR
:
3036 case LINKEVENT_MODULE_OPTICAL_LRM
:
3037 case LINKEVENT_MODULE_OPTICAL_SFP_1G
:
3038 ahw
->supported_type
= PORT_FIBRE
;
3040 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE
:
3041 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN
:
3042 case LINKEVENT_MODULE_TWINAX
:
3043 ahw
->supported_type
= PORT_TP
;
3046 ahw
->supported_type
= PORT_OTHER
;
3053 qlcnic_free_mbx_args(&cmd
);
3057 int qlcnic_83xx_get_settings(struct qlcnic_adapter
*adapter
,
3058 struct ethtool_cmd
*ecmd
)
3062 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3064 /* Get port configuration info */
3065 status
= qlcnic_83xx_get_port_info(adapter
);
3066 /* Get Link Status related info */
3067 config
= qlcnic_83xx_test_link(adapter
);
3068 ahw
->module_type
= QLC_83XX_SFP_MODULE_TYPE(config
);
3069 /* hard code until there is a way to get it from flash */
3070 ahw
->board_type
= QLCNIC_BRDTYPE_83XX_10G
;
3072 if (netif_running(adapter
->netdev
) && ahw
->has_link_events
) {
3073 ethtool_cmd_speed_set(ecmd
, ahw
->link_speed
);
3074 ecmd
->duplex
= ahw
->link_duplex
;
3075 ecmd
->autoneg
= ahw
->link_autoneg
;
3077 ethtool_cmd_speed_set(ecmd
, SPEED_UNKNOWN
);
3078 ecmd
->duplex
= DUPLEX_UNKNOWN
;
3079 ecmd
->autoneg
= AUTONEG_DISABLE
;
3082 if (ahw
->port_type
== QLCNIC_XGBE
) {
3083 ecmd
->supported
= SUPPORTED_10000baseT_Full
;
3084 ecmd
->advertising
= ADVERTISED_10000baseT_Full
;
3086 ecmd
->supported
= (SUPPORTED_10baseT_Half
|
3087 SUPPORTED_10baseT_Full
|
3088 SUPPORTED_100baseT_Half
|
3089 SUPPORTED_100baseT_Full
|
3090 SUPPORTED_1000baseT_Half
|
3091 SUPPORTED_1000baseT_Full
);
3092 ecmd
->advertising
= (ADVERTISED_100baseT_Half
|
3093 ADVERTISED_100baseT_Full
|
3094 ADVERTISED_1000baseT_Half
|
3095 ADVERTISED_1000baseT_Full
);
3098 switch (ahw
->supported_type
) {
3100 ecmd
->supported
|= SUPPORTED_FIBRE
;
3101 ecmd
->advertising
|= ADVERTISED_FIBRE
;
3102 ecmd
->port
= PORT_FIBRE
;
3103 ecmd
->transceiver
= XCVR_EXTERNAL
;
3106 ecmd
->supported
|= SUPPORTED_TP
;
3107 ecmd
->advertising
|= ADVERTISED_TP
;
3108 ecmd
->port
= PORT_TP
;
3109 ecmd
->transceiver
= XCVR_INTERNAL
;
3112 ecmd
->supported
|= SUPPORTED_FIBRE
;
3113 ecmd
->advertising
|= ADVERTISED_FIBRE
;
3114 ecmd
->port
= PORT_OTHER
;
3115 ecmd
->transceiver
= XCVR_EXTERNAL
;
3118 ecmd
->phy_address
= ahw
->physical_port
;
3122 int qlcnic_83xx_set_settings(struct qlcnic_adapter
*adapter
,
3123 struct ethtool_cmd
*ecmd
)
3126 u32 config
= adapter
->ahw
->port_config
;
3129 adapter
->ahw
->port_config
|= BIT_15
;
3131 switch (ethtool_cmd_speed(ecmd
)) {
3133 adapter
->ahw
->port_config
|= BIT_8
;
3136 adapter
->ahw
->port_config
|= BIT_9
;
3139 adapter
->ahw
->port_config
|= BIT_10
;
3142 adapter
->ahw
->port_config
|= BIT_11
;
3148 status
= qlcnic_83xx_set_port_config(adapter
);
3150 dev_info(&adapter
->pdev
->dev
,
3151 "Failed to Set Link Speed and autoneg.\n");
3152 adapter
->ahw
->port_config
= config
;
3157 static inline u64
*qlcnic_83xx_copy_stats(struct qlcnic_cmd_args
*cmd
,
3158 u64
*data
, int index
)
3163 low
= cmd
->rsp
.arg
[index
];
3164 hi
= cmd
->rsp
.arg
[index
+ 1];
3165 val
= (((u64
) low
) | (((u64
) hi
) << 32));
3170 static u64
*qlcnic_83xx_fill_stats(struct qlcnic_adapter
*adapter
,
3171 struct qlcnic_cmd_args
*cmd
, u64
*data
,
3174 int err
, k
, total_regs
;
3177 err
= qlcnic_issue_cmd(adapter
, cmd
);
3178 if (err
!= QLCNIC_RCODE_SUCCESS
) {
3179 dev_info(&adapter
->pdev
->dev
,
3180 "Error in get statistics mailbox command\n");
3184 total_regs
= cmd
->rsp
.num
;
3186 case QLC_83XX_STAT_MAC
:
3187 /* fill in MAC tx counters */
3188 for (k
= 2; k
< 28; k
+= 2)
3189 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3190 /* skip 24 bytes of reserved area */
3191 /* fill in MAC rx counters */
3192 for (k
+= 6; k
< 60; k
+= 2)
3193 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3194 /* skip 24 bytes of reserved area */
3195 /* fill in MAC rx frame stats */
3196 for (k
+= 6; k
< 80; k
+= 2)
3197 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3198 /* fill in eSwitch stats */
3199 for (; k
< total_regs
; k
+= 2)
3200 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3202 case QLC_83XX_STAT_RX
:
3203 for (k
= 2; k
< 8; k
+= 2)
3204 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3205 /* skip 8 bytes of reserved data */
3206 for (k
+= 2; k
< 24; k
+= 2)
3207 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3208 /* skip 8 bytes containing RE1FBQ error data */
3209 for (k
+= 2; k
< total_regs
; k
+= 2)
3210 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3212 case QLC_83XX_STAT_TX
:
3213 for (k
= 2; k
< 10; k
+= 2)
3214 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3215 /* skip 8 bytes of reserved data */
3216 for (k
+= 2; k
< total_regs
; k
+= 2)
3217 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3220 dev_warn(&adapter
->pdev
->dev
, "Unknown get statistics mode\n");
3226 void qlcnic_83xx_get_stats(struct qlcnic_adapter
*adapter
, u64
*data
)
3228 struct qlcnic_cmd_args cmd
;
3229 struct net_device
*netdev
= adapter
->netdev
;
3232 ret
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_GET_STATISTICS
);
3236 cmd
.req
.arg
[1] = BIT_1
| (adapter
->tx_ring
->ctx_id
<< 16);
3237 cmd
.rsp
.num
= QLC_83XX_TX_STAT_REGS
;
3238 data
= qlcnic_83xx_fill_stats(adapter
, &cmd
, data
,
3239 QLC_83XX_STAT_TX
, &ret
);
3241 netdev_err(netdev
, "Error getting Tx stats\n");
3245 cmd
.req
.arg
[1] = BIT_2
| (adapter
->portnum
<< 16);
3246 cmd
.rsp
.num
= QLC_83XX_MAC_STAT_REGS
;
3247 memset(cmd
.rsp
.arg
, 0, sizeof(u32
) * cmd
.rsp
.num
);
3248 data
= qlcnic_83xx_fill_stats(adapter
, &cmd
, data
,
3249 QLC_83XX_STAT_MAC
, &ret
);
3251 netdev_err(netdev
, "Error getting MAC stats\n");
3255 cmd
.req
.arg
[1] = adapter
->recv_ctx
->context_id
<< 16;
3256 cmd
.rsp
.num
= QLC_83XX_RX_STAT_REGS
;
3257 memset(cmd
.rsp
.arg
, 0, sizeof(u32
) * cmd
.rsp
.num
);
3258 data
= qlcnic_83xx_fill_stats(adapter
, &cmd
, data
,
3259 QLC_83XX_STAT_RX
, &ret
);
3261 netdev_err(netdev
, "Error getting Rx stats\n");
3263 qlcnic_free_mbx_args(&cmd
);
3266 int qlcnic_83xx_reg_test(struct qlcnic_adapter
*adapter
)
3268 u32 major
, minor
, sub
;
3270 major
= QLC_SHARED_REG_RD32(adapter
, QLCNIC_FW_VERSION_MAJOR
);
3271 minor
= QLC_SHARED_REG_RD32(adapter
, QLCNIC_FW_VERSION_MINOR
);
3272 sub
= QLC_SHARED_REG_RD32(adapter
, QLCNIC_FW_VERSION_SUB
);
3274 if (adapter
->fw_version
!= QLCNIC_VERSION_CODE(major
, minor
, sub
)) {
3275 dev_info(&adapter
->pdev
->dev
, "%s: Reg test failed\n",
3282 int qlcnic_83xx_get_regs_len(struct qlcnic_adapter
*adapter
)
3284 return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl
) *
3285 sizeof(adapter
->ahw
->ext_reg_tbl
)) +
3286 (ARRAY_SIZE(qlcnic_83xx_reg_tbl
) +
3287 sizeof(adapter
->ahw
->reg_tbl
));
3290 int qlcnic_83xx_get_registers(struct qlcnic_adapter
*adapter
, u32
*regs_buff
)
3294 for (i
= QLCNIC_DEV_INFO_SIZE
+ 1;
3295 j
< ARRAY_SIZE(qlcnic_83xx_reg_tbl
); i
++, j
++)
3296 regs_buff
[i
] = QLC_SHARED_REG_RD32(adapter
, j
);
3298 for (j
= 0; j
< ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl
); j
++)
3299 regs_buff
[i
++] = QLCRDX(adapter
->ahw
, j
);
3303 int qlcnic_83xx_interrupt_test(struct net_device
*netdev
)
3305 struct qlcnic_adapter
*adapter
= netdev_priv(netdev
);
3306 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3307 struct qlcnic_cmd_args cmd
;
3311 int ret
, max_sds_rings
= adapter
->max_sds_rings
;
3313 if (test_bit(__QLCNIC_RESETTING
, &adapter
->state
)) {
3314 netdev_info(netdev
, "Device is resetting\n");
3318 if (qlcnic_get_diag_lock(adapter
)) {
3319 netdev_info(netdev
, "Device in diagnostics mode\n");
3323 ret
= qlcnic_83xx_diag_alloc_res(netdev
, QLCNIC_INTERRUPT_TEST
,
3329 ret
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_INTRPT_TEST
);
3333 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
3334 intrpt_id
= ahw
->intr_tbl
[0].id
;
3336 intrpt_id
= QLCRDX(ahw
, QLCNIC_DEF_INT_ID
);
3339 cmd
.req
.arg
[2] = intrpt_id
;
3340 cmd
.req
.arg
[3] = BIT_0
;
3342 ret
= qlcnic_issue_cmd(adapter
, &cmd
);
3343 data
= cmd
.rsp
.arg
[2];
3345 val
= LSB(MSW(data
));
3346 if (id
!= intrpt_id
)
3347 dev_info(&adapter
->pdev
->dev
,
3348 "Interrupt generated: 0x%x, requested:0x%x\n",
3351 dev_err(&adapter
->pdev
->dev
,
3352 "Interrupt test error: 0x%x\n", val
);
3357 ret
= !ahw
->diag_cnt
;
3360 qlcnic_free_mbx_args(&cmd
);
3361 qlcnic_83xx_diag_free_res(netdev
, max_sds_rings
);
3364 adapter
->max_sds_rings
= max_sds_rings
;
3365 qlcnic_release_diag_lock(adapter
);
3369 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter
*adapter
,
3370 struct ethtool_pauseparam
*pause
)
3372 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3376 status
= qlcnic_83xx_get_port_config(adapter
);
3378 dev_err(&adapter
->pdev
->dev
,
3379 "%s: Get Pause Config failed\n", __func__
);
3382 config
= ahw
->port_config
;
3383 if (config
& QLC_83XX_CFG_STD_PAUSE
) {
3384 if (config
& QLC_83XX_CFG_STD_TX_PAUSE
)
3385 pause
->tx_pause
= 1;
3386 if (config
& QLC_83XX_CFG_STD_RX_PAUSE
)
3387 pause
->rx_pause
= 1;
3390 if (QLC_83XX_AUTONEG(config
))
3394 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter
*adapter
,
3395 struct ethtool_pauseparam
*pause
)
3397 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3401 status
= qlcnic_83xx_get_port_config(adapter
);
3403 dev_err(&adapter
->pdev
->dev
,
3404 "%s: Get Pause Config failed.\n", __func__
);
3407 config
= ahw
->port_config
;
3409 if (ahw
->port_type
== QLCNIC_GBE
) {
3411 ahw
->port_config
|= QLC_83XX_ENABLE_AUTONEG
;
3412 if (!pause
->autoneg
)
3413 ahw
->port_config
&= ~QLC_83XX_ENABLE_AUTONEG
;
3414 } else if ((ahw
->port_type
== QLCNIC_XGBE
) && (pause
->autoneg
)) {
3418 if (!(config
& QLC_83XX_CFG_STD_PAUSE
))
3419 ahw
->port_config
|= QLC_83XX_CFG_STD_PAUSE
;
3421 if (pause
->rx_pause
&& pause
->tx_pause
) {
3422 ahw
->port_config
|= QLC_83XX_CFG_STD_TX_RX_PAUSE
;
3423 } else if (pause
->rx_pause
&& !pause
->tx_pause
) {
3424 ahw
->port_config
&= ~QLC_83XX_CFG_STD_TX_PAUSE
;
3425 ahw
->port_config
|= QLC_83XX_CFG_STD_RX_PAUSE
;
3426 } else if (pause
->tx_pause
&& !pause
->rx_pause
) {
3427 ahw
->port_config
&= ~QLC_83XX_CFG_STD_RX_PAUSE
;
3428 ahw
->port_config
|= QLC_83XX_CFG_STD_TX_PAUSE
;
3429 } else if (!pause
->rx_pause
&& !pause
->tx_pause
) {
3430 ahw
->port_config
&= ~QLC_83XX_CFG_STD_TX_RX_PAUSE
;
3432 status
= qlcnic_83xx_set_port_config(adapter
);
3434 dev_err(&adapter
->pdev
->dev
,
3435 "%s: Set Pause Config failed.\n", __func__
);
3436 ahw
->port_config
= config
;
3441 static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter
*adapter
)
3446 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
,
3447 QLC_83XX_FLASH_OEM_READ_SIG
);
3448 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
3449 QLC_83XX_FLASH_READ_CTRL
);
3450 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
3454 temp
= QLCRD32(adapter
, QLC_83XX_FLASH_RDDATA
, &err
);
3461 int qlcnic_83xx_flash_test(struct qlcnic_adapter
*adapter
)
3465 status
= qlcnic_83xx_read_flash_status_reg(adapter
);
3466 if (status
== -EIO
) {
3467 dev_info(&adapter
->pdev
->dev
, "%s: EEPROM test failed.\n",
3474 int qlcnic_83xx_shutdown(struct pci_dev
*pdev
)
3476 struct qlcnic_adapter
*adapter
= pci_get_drvdata(pdev
);
3477 struct net_device
*netdev
= adapter
->netdev
;
3480 netif_device_detach(netdev
);
3481 qlcnic_cancel_idc_work(adapter
);
3483 if (netif_running(netdev
))
3484 qlcnic_down(adapter
, netdev
);
3486 qlcnic_83xx_disable_mbx_intr(adapter
);
3487 cancel_delayed_work_sync(&adapter
->idc_aen_work
);
3489 retval
= pci_save_state(pdev
);
3496 int qlcnic_83xx_resume(struct qlcnic_adapter
*adapter
)
3498 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3499 struct qlc_83xx_idc
*idc
= &ahw
->idc
;
3502 err
= qlcnic_83xx_idc_init(adapter
);
3506 if (ahw
->nic_mode
== QLC_83XX_VIRTUAL_NIC_MODE
) {
3507 if (ahw
->op_mode
== QLCNIC_MGMT_FUNC
) {
3508 qlcnic_83xx_set_vnic_opmode(adapter
);
3510 err
= qlcnic_83xx_check_vnic_state(adapter
);
3516 err
= qlcnic_83xx_idc_reattach_driver(adapter
);
3520 qlcnic_schedule_work(adapter
, qlcnic_83xx_idc_poll_dev_state
,
3525 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox
*mbx
)
3527 INIT_COMPLETION(mbx
->completion
);
3528 set_bit(QLC_83XX_MBX_READY
, &mbx
->status
);
3531 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox
*mbx
)
3533 destroy_workqueue(mbx
->work_q
);
3538 qlcnic_83xx_notify_cmd_completion(struct qlcnic_adapter
*adapter
,
3539 struct qlcnic_cmd_args
*cmd
)
3541 atomic_set(&cmd
->rsp_status
, QLC_83XX_MBX_RESPONSE_ARRIVED
);
3543 if (cmd
->type
== QLC_83XX_MBX_CMD_NO_WAIT
) {
3544 qlcnic_free_mbx_args(cmd
);
3548 complete(&cmd
->completion
);
3551 static void qlcnic_83xx_flush_mbx_queue(struct qlcnic_adapter
*adapter
)
3553 struct qlcnic_mailbox
*mbx
= adapter
->ahw
->mailbox
;
3554 struct list_head
*head
= &mbx
->cmd_q
;
3555 struct qlcnic_cmd_args
*cmd
= NULL
;
3557 spin_lock(&mbx
->queue_lock
);
3559 while (!list_empty(head
)) {
3560 cmd
= list_entry(head
->next
, struct qlcnic_cmd_args
, list
);
3561 dev_info(&adapter
->pdev
->dev
, "%s: Mailbox command 0x%x\n",
3562 __func__
, cmd
->cmd_op
);
3563 list_del(&cmd
->list
);
3565 qlcnic_83xx_notify_cmd_completion(adapter
, cmd
);
3568 spin_unlock(&mbx
->queue_lock
);
3571 static int qlcnic_83xx_check_mbx_status(struct qlcnic_adapter
*adapter
)
3573 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3574 struct qlcnic_mailbox
*mbx
= ahw
->mailbox
;
3577 if (!test_bit(QLC_83XX_MBX_READY
, &mbx
->status
))
3580 host_mbx_ctrl
= QLCRDX(ahw
, QLCNIC_HOST_MBX_CTRL
);
3581 if (host_mbx_ctrl
) {
3582 clear_bit(QLC_83XX_MBX_READY
, &mbx
->status
);
3583 ahw
->idc
.collect_dump
= 1;
3590 static inline void qlcnic_83xx_signal_mbx_cmd(struct qlcnic_adapter
*adapter
,
3594 QLCWRX(adapter
->ahw
, QLCNIC_HOST_MBX_CTRL
, QLCNIC_SET_OWNER
);
3596 QLCWRX(adapter
->ahw
, QLCNIC_FW_MBX_CTRL
, QLCNIC_CLR_OWNER
);
3599 static void qlcnic_83xx_dequeue_mbx_cmd(struct qlcnic_adapter
*adapter
,
3600 struct qlcnic_cmd_args
*cmd
)
3602 struct qlcnic_mailbox
*mbx
= adapter
->ahw
->mailbox
;
3604 spin_lock(&mbx
->queue_lock
);
3606 list_del(&cmd
->list
);
3609 spin_unlock(&mbx
->queue_lock
);
3611 qlcnic_83xx_notify_cmd_completion(adapter
, cmd
);
3614 static void qlcnic_83xx_encode_mbx_cmd(struct qlcnic_adapter
*adapter
,
3615 struct qlcnic_cmd_args
*cmd
)
3617 u32 mbx_cmd
, fw_hal_version
, hdr_size
, total_size
, tmp
;
3618 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3621 if (cmd
->op_type
!= QLC_83XX_MBX_POST_BC_OP
) {
3622 mbx_cmd
= cmd
->req
.arg
[0];
3623 writel(mbx_cmd
, QLCNIC_MBX_HOST(ahw
, 0));
3624 for (i
= 1; i
< cmd
->req
.num
; i
++)
3625 writel(cmd
->req
.arg
[i
], QLCNIC_MBX_HOST(ahw
, i
));
3627 fw_hal_version
= ahw
->fw_hal_version
;
3628 hdr_size
= sizeof(struct qlcnic_bc_hdr
) / sizeof(u32
);
3629 total_size
= cmd
->pay_size
+ hdr_size
;
3630 tmp
= QLCNIC_CMD_BC_EVENT_SETUP
| total_size
<< 16;
3631 mbx_cmd
= tmp
| fw_hal_version
<< 29;
3632 writel(mbx_cmd
, QLCNIC_MBX_HOST(ahw
, 0));
3634 /* Back channel specific operations bits */
3635 mbx_cmd
= 0x1 | 1 << 4;
3637 if (qlcnic_sriov_pf_check(adapter
))
3638 mbx_cmd
|= cmd
->func_num
<< 5;
3640 writel(mbx_cmd
, QLCNIC_MBX_HOST(ahw
, 1));
3642 for (i
= 2, j
= 0; j
< hdr_size
; i
++, j
++)
3643 writel(*(cmd
->hdr
++), QLCNIC_MBX_HOST(ahw
, i
));
3644 for (j
= 0; j
< cmd
->pay_size
; j
++, i
++)
3645 writel(*(cmd
->pay
++), QLCNIC_MBX_HOST(ahw
, i
));
3649 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter
*adapter
)
3651 struct qlcnic_mailbox
*mbx
= adapter
->ahw
->mailbox
;
3653 clear_bit(QLC_83XX_MBX_READY
, &mbx
->status
);
3654 complete(&mbx
->completion
);
3655 cancel_work_sync(&mbx
->work
);
3656 flush_workqueue(mbx
->work_q
);
3657 qlcnic_83xx_flush_mbx_queue(adapter
);
3660 static int qlcnic_83xx_enqueue_mbx_cmd(struct qlcnic_adapter
*adapter
,
3661 struct qlcnic_cmd_args
*cmd
,
3662 unsigned long *timeout
)
3664 struct qlcnic_mailbox
*mbx
= adapter
->ahw
->mailbox
;
3666 if (test_bit(QLC_83XX_MBX_READY
, &mbx
->status
)) {
3667 atomic_set(&cmd
->rsp_status
, QLC_83XX_MBX_RESPONSE_WAIT
);
3668 init_completion(&cmd
->completion
);
3669 cmd
->rsp_opcode
= QLC_83XX_MBX_RESPONSE_UNKNOWN
;
3671 spin_lock(&mbx
->queue_lock
);
3673 list_add_tail(&cmd
->list
, &mbx
->cmd_q
);
3675 cmd
->total_cmds
= mbx
->num_cmds
;
3676 *timeout
= cmd
->total_cmds
* QLC_83XX_MBX_TIMEOUT
;
3677 queue_work(mbx
->work_q
, &mbx
->work
);
3679 spin_unlock(&mbx
->queue_lock
);
3687 static int qlcnic_83xx_check_mac_rcode(struct qlcnic_adapter
*adapter
,
3688 struct qlcnic_cmd_args
*cmd
)
3693 if (cmd
->cmd_op
== QLCNIC_CMD_CONFIG_MAC_VLAN
) {
3694 fw_data
= readl(QLCNIC_MBX_FW(adapter
->ahw
, 2));
3695 mac_cmd_rcode
= (u8
)fw_data
;
3696 if (mac_cmd_rcode
== QLC_83XX_NO_NIC_RESOURCE
||
3697 mac_cmd_rcode
== QLC_83XX_MAC_PRESENT
||
3698 mac_cmd_rcode
== QLC_83XX_MAC_ABSENT
) {
3699 cmd
->rsp_opcode
= QLCNIC_RCODE_SUCCESS
;
3700 return QLCNIC_RCODE_SUCCESS
;
3707 static void qlcnic_83xx_decode_mbx_rsp(struct qlcnic_adapter
*adapter
,
3708 struct qlcnic_cmd_args
*cmd
)
3710 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3711 struct device
*dev
= &adapter
->pdev
->dev
;
3715 fw_data
= readl(QLCNIC_MBX_FW(ahw
, 0));
3716 mbx_err_code
= QLCNIC_MBX_STATUS(fw_data
);
3717 qlcnic_83xx_get_mbx_data(adapter
, cmd
);
3719 switch (mbx_err_code
) {
3720 case QLCNIC_MBX_RSP_OK
:
3721 case QLCNIC_MBX_PORT_RSP_OK
:
3722 cmd
->rsp_opcode
= QLCNIC_RCODE_SUCCESS
;
3725 if (!qlcnic_83xx_check_mac_rcode(adapter
, cmd
))
3728 dev_err(dev
, "%s: Mailbox command failed, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x, error=0x%x\n",
3729 __func__
, cmd
->cmd_op
, cmd
->type
, ahw
->pci_func
,
3730 ahw
->op_mode
, mbx_err_code
);
3731 cmd
->rsp_opcode
= QLC_83XX_MBX_RESPONSE_FAILED
;
3732 qlcnic_dump_mbx(adapter
, cmd
);
3738 static void qlcnic_83xx_mailbox_worker(struct work_struct
*work
)
3740 struct qlcnic_mailbox
*mbx
= container_of(work
, struct qlcnic_mailbox
,
3742 struct qlcnic_adapter
*adapter
= mbx
->adapter
;
3743 struct qlcnic_mbx_ops
*mbx_ops
= mbx
->ops
;
3744 struct device
*dev
= &adapter
->pdev
->dev
;
3745 atomic_t
*rsp_status
= &mbx
->rsp_status
;
3746 struct list_head
*head
= &mbx
->cmd_q
;
3747 struct qlcnic_hardware_context
*ahw
;
3748 struct qlcnic_cmd_args
*cmd
= NULL
;
3753 if (qlcnic_83xx_check_mbx_status(adapter
)) {
3754 qlcnic_83xx_flush_mbx_queue(adapter
);
3758 atomic_set(rsp_status
, QLC_83XX_MBX_RESPONSE_WAIT
);
3760 spin_lock(&mbx
->queue_lock
);
3762 if (list_empty(head
)) {
3763 spin_unlock(&mbx
->queue_lock
);
3766 cmd
= list_entry(head
->next
, struct qlcnic_cmd_args
, list
);
3768 spin_unlock(&mbx
->queue_lock
);
3770 mbx_ops
->encode_cmd(adapter
, cmd
);
3771 mbx_ops
->nofity_fw(adapter
, QLC_83XX_MBX_REQUEST
);
3773 if (wait_for_completion_timeout(&mbx
->completion
,
3774 QLC_83XX_MBX_TIMEOUT
)) {
3775 mbx_ops
->decode_resp(adapter
, cmd
);
3776 mbx_ops
->nofity_fw(adapter
, QLC_83XX_MBX_COMPLETION
);
3778 dev_err(dev
, "%s: Mailbox command timeout, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x\n",
3779 __func__
, cmd
->cmd_op
, cmd
->type
, ahw
->pci_func
,
3781 clear_bit(QLC_83XX_MBX_READY
, &mbx
->status
);
3782 qlcnic_dump_mbx(adapter
, cmd
);
3783 qlcnic_83xx_idc_request_reset(adapter
,
3784 QLCNIC_FORCE_FW_DUMP_KEY
);
3785 cmd
->rsp_opcode
= QLCNIC_RCODE_TIMEOUT
;
3787 mbx_ops
->dequeue_cmd(adapter
, cmd
);
3791 static struct qlcnic_mbx_ops qlcnic_83xx_mbx_ops
= {
3792 .enqueue_cmd
= qlcnic_83xx_enqueue_mbx_cmd
,
3793 .dequeue_cmd
= qlcnic_83xx_dequeue_mbx_cmd
,
3794 .decode_resp
= qlcnic_83xx_decode_mbx_rsp
,
3795 .encode_cmd
= qlcnic_83xx_encode_mbx_cmd
,
3796 .nofity_fw
= qlcnic_83xx_signal_mbx_cmd
,
3799 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter
*adapter
)
3801 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3802 struct qlcnic_mailbox
*mbx
;
3804 ahw
->mailbox
= kzalloc(sizeof(*mbx
), GFP_KERNEL
);
3809 mbx
->ops
= &qlcnic_83xx_mbx_ops
;
3810 mbx
->adapter
= adapter
;
3812 spin_lock_init(&mbx
->queue_lock
);
3813 spin_lock_init(&mbx
->aen_lock
);
3814 INIT_LIST_HEAD(&mbx
->cmd_q
);
3815 init_completion(&mbx
->completion
);
3817 mbx
->work_q
= create_singlethread_workqueue("qlcnic_mailbox");
3818 if (mbx
->work_q
== NULL
) {
3823 INIT_WORK(&mbx
->work
, qlcnic_83xx_mailbox_worker
);
3824 set_bit(QLC_83XX_MBX_READY
, &mbx
->status
);
3828 pci_ers_result_t
qlcnic_83xx_io_error_detected(struct pci_dev
*pdev
,
3829 pci_channel_state_t state
)
3831 struct qlcnic_adapter
*adapter
= pci_get_drvdata(pdev
);
3833 if (state
== pci_channel_io_perm_failure
)
3834 return PCI_ERS_RESULT_DISCONNECT
;
3836 if (state
== pci_channel_io_normal
)
3837 return PCI_ERS_RESULT_RECOVERED
;
3839 set_bit(__QLCNIC_AER
, &adapter
->state
);
3840 set_bit(__QLCNIC_RESETTING
, &adapter
->state
);
3842 qlcnic_83xx_aer_stop_poll_work(adapter
);
3844 pci_save_state(pdev
);
3845 pci_disable_device(pdev
);
3847 return PCI_ERS_RESULT_NEED_RESET
;
3850 pci_ers_result_t
qlcnic_83xx_io_slot_reset(struct pci_dev
*pdev
)
3852 struct qlcnic_adapter
*adapter
= pci_get_drvdata(pdev
);
3855 pdev
->error_state
= pci_channel_io_normal
;
3856 err
= pci_enable_device(pdev
);
3860 pci_set_power_state(pdev
, PCI_D0
);
3861 pci_set_master(pdev
);
3862 pci_restore_state(pdev
);
3864 err
= qlcnic_83xx_aer_reset(adapter
);
3866 return PCI_ERS_RESULT_RECOVERED
;
3868 clear_bit(__QLCNIC_AER
, &adapter
->state
);
3869 clear_bit(__QLCNIC_RESETTING
, &adapter
->state
);
3870 return PCI_ERS_RESULT_DISCONNECT
;
3873 void qlcnic_83xx_io_resume(struct pci_dev
*pdev
)
3875 struct qlcnic_adapter
*adapter
= pci_get_drvdata(pdev
);
3877 pci_cleanup_aer_uncorrect_error_status(pdev
);
3878 if (test_and_clear_bit(__QLCNIC_AER
, &adapter
->state
))
3879 qlcnic_83xx_aer_start_poll_work(adapter
);