2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
5 * See LICENSE.qlcnic for copyright and licensing details.
8 #include "qlcnic_sriov.h"
10 #include "qlcnic_hw.h"
12 /* Reset template definitions */
13 #define QLC_83XX_RESTART_TEMPLATE_SIZE 0x2000
14 #define QLC_83XX_RESET_TEMPLATE_ADDR 0x4F0000
15 #define QLC_83XX_RESET_SEQ_VERSION 0x0101
17 #define QLC_83XX_OPCODE_NOP 0x0000
18 #define QLC_83XX_OPCODE_WRITE_LIST 0x0001
19 #define QLC_83XX_OPCODE_READ_WRITE_LIST 0x0002
20 #define QLC_83XX_OPCODE_POLL_LIST 0x0004
21 #define QLC_83XX_OPCODE_POLL_WRITE_LIST 0x0008
22 #define QLC_83XX_OPCODE_READ_MODIFY_WRITE 0x0010
23 #define QLC_83XX_OPCODE_SEQ_PAUSE 0x0020
24 #define QLC_83XX_OPCODE_SEQ_END 0x0040
25 #define QLC_83XX_OPCODE_TMPL_END 0x0080
26 #define QLC_83XX_OPCODE_POLL_READ_LIST 0x0100
28 /* EPORT control registers */
29 #define QLC_83XX_RESET_CONTROL 0x28084E50
30 #define QLC_83XX_RESET_REG 0x28084E60
31 #define QLC_83XX_RESET_PORT0 0x28084E70
32 #define QLC_83XX_RESET_PORT1 0x28084E80
33 #define QLC_83XX_RESET_PORT2 0x28084E90
34 #define QLC_83XX_RESET_PORT3 0x28084EA0
35 #define QLC_83XX_RESET_SRESHIM 0x28084EB0
36 #define QLC_83XX_RESET_EPGSHIM 0x28084EC0
37 #define QLC_83XX_RESET_ETHERPCS 0x28084ED0
39 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter
*adapter
);
40 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter
*p_dev
);
41 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter
*adapter
);
44 struct qlc_83xx_reset_hdr
{
45 #if defined(__LITTLE_ENDIAN)
54 #elif defined(__BIG_ENDIAN)
66 /* Command entry header. */
67 struct qlc_83xx_entry_hdr
{
68 #if defined(__LITTLE_ENDIAN)
73 #elif defined(__BIG_ENDIAN)
81 /* Generic poll command */
82 struct qlc_83xx_poll
{
87 /* Read modify write command */
92 #if defined(__LITTLE_ENDIAN)
97 #elif defined(__BIG_ENDIAN)
105 /* Generic command with 2 DWORD */
106 struct qlc_83xx_entry
{
111 /* Generic command with 4 DWORD */
112 struct qlc_83xx_quad_entry
{
118 static const char *const qlc_83xx_idc_states
[] = {
130 qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter
*adapter
)
134 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_DRV_PRESENCE
);
141 static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter
*adapter
)
144 cur
= adapter
->ahw
->idc
.curr_state
;
145 prev
= adapter
->ahw
->idc
.prev_state
;
147 dev_info(&adapter
->pdev
->dev
,
148 "current state = %s, prev state = %s\n",
149 adapter
->ahw
->idc
.name
[cur
],
150 adapter
->ahw
->idc
.name
[prev
]);
153 static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter
*adapter
,
160 if (qlcnic_83xx_lock_driver(adapter
))
164 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_DRV_AUDIT
);
165 val
|= (adapter
->portnum
& 0xf);
168 seconds
= jiffies
/ HZ
- adapter
->ahw
->idc
.sec_counter
;
170 seconds
= jiffies
/ HZ
;
173 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_DRV_AUDIT
, val
);
174 adapter
->ahw
->idc
.sec_counter
= jiffies
/ HZ
;
177 qlcnic_83xx_unlock_driver(adapter
);
182 static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter
*adapter
)
186 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_MIN_VERSION
);
187 val
= val
& ~(0x3 << (adapter
->portnum
* 2));
188 val
= val
| (QLC_83XX_IDC_MINOR_VERSION
<< (adapter
->portnum
* 2));
189 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_MIN_VERSION
, val
);
192 static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter
*adapter
,
198 if (qlcnic_83xx_lock_driver(adapter
))
202 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_MAJ_VERSION
);
204 val
= val
| QLC_83XX_IDC_MAJOR_VERSION
;
205 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_MAJ_VERSION
, val
);
208 qlcnic_83xx_unlock_driver(adapter
);
214 qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter
*adapter
,
215 int status
, int lock
)
220 if (qlcnic_83xx_lock_driver(adapter
))
224 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_DRV_PRESENCE
);
227 val
= val
| (1 << adapter
->portnum
);
229 val
= val
& ~(1 << adapter
->portnum
);
231 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_DRV_PRESENCE
, val
);
232 qlcnic_83xx_idc_update_minor_version(adapter
);
235 qlcnic_83xx_unlock_driver(adapter
);
240 static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter
*adapter
)
245 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_MAJ_VERSION
);
246 version
= val
& 0xFF;
248 if (version
!= QLC_83XX_IDC_MAJOR_VERSION
) {
249 dev_info(&adapter
->pdev
->dev
,
250 "%s:mismatch. version 0x%x, expected version 0x%x\n",
251 __func__
, version
, QLC_83XX_IDC_MAJOR_VERSION
);
258 static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter
*adapter
,
264 if (qlcnic_83xx_lock_driver(adapter
))
268 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_DRV_ACK
, 0);
269 /* Clear gracefull reset bit */
270 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_CTRL
);
271 val
&= ~QLC_83XX_IDC_GRACEFULL_RESET
;
272 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_CTRL
, val
);
275 qlcnic_83xx_unlock_driver(adapter
);
280 static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter
*adapter
,
286 if (qlcnic_83xx_lock_driver(adapter
))
290 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_DRV_ACK
);
292 val
= val
| (1 << adapter
->portnum
);
294 val
= val
& ~(1 << adapter
->portnum
);
295 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_DRV_ACK
, val
);
298 qlcnic_83xx_unlock_driver(adapter
);
303 static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter
*adapter
,
308 seconds
= jiffies
/ HZ
- adapter
->ahw
->idc
.sec_counter
;
309 if (seconds
<= time_limit
)
316 * qlcnic_83xx_idc_check_reset_ack_reg
318 * @adapter: adapter structure
320 * Check ACK wait limit and clear the functions which failed to ACK
322 * Return 0 if all functions have acknowledged the reset request.
324 static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter
*adapter
)
327 u32 ack
, presence
, val
;
329 timeout
= QLC_83XX_IDC_RESET_TIMEOUT_SECS
;
330 ack
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_DRV_ACK
);
331 presence
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_DRV_PRESENCE
);
332 dev_info(&adapter
->pdev
->dev
,
333 "%s: ack = 0x%x, presence = 0x%x\n", __func__
, ack
, presence
);
334 if (!((ack
& presence
) == presence
)) {
335 if (qlcnic_83xx_idc_check_timeout(adapter
, timeout
)) {
336 /* Clear functions which failed to ACK */
337 dev_info(&adapter
->pdev
->dev
,
338 "%s: ACK wait exceeds time limit\n", __func__
);
339 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_DRV_PRESENCE
);
340 val
= val
& ~(ack
^ presence
);
341 if (qlcnic_83xx_lock_driver(adapter
))
343 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_DRV_PRESENCE
, val
);
344 dev_info(&adapter
->pdev
->dev
,
345 "%s: updated drv presence reg = 0x%x\n",
347 qlcnic_83xx_unlock_driver(adapter
);
354 dev_info(&adapter
->pdev
->dev
,
355 "%s: Reset ACK received from all functions\n",
362 * qlcnic_83xx_idc_tx_soft_reset
364 * @adapter: adapter structure
366 * Handle context deletion and recreation request from transmit routine
368 * Returns -EBUSY or Success (0)
371 static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter
*adapter
)
373 struct net_device
*netdev
= adapter
->netdev
;
375 if (test_and_set_bit(__QLCNIC_RESETTING
, &adapter
->state
))
378 netif_device_detach(netdev
);
379 qlcnic_down(adapter
, netdev
);
380 qlcnic_up(adapter
, netdev
);
381 netif_device_attach(netdev
);
382 clear_bit(__QLCNIC_RESETTING
, &adapter
->state
);
383 dev_err(&adapter
->pdev
->dev
, "%s:\n", __func__
);
389 * qlcnic_83xx_idc_detach_driver
391 * @adapter: adapter structure
392 * Detach net interface, stop TX and cleanup resources before the HW reset.
396 static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter
*adapter
)
399 struct net_device
*netdev
= adapter
->netdev
;
401 netif_device_detach(netdev
);
402 qlcnic_83xx_detach_mailbox_work(adapter
);
404 /* Disable mailbox interrupt */
405 qlcnic_83xx_disable_mbx_intr(adapter
);
406 qlcnic_down(adapter
, netdev
);
407 for (i
= 0; i
< adapter
->ahw
->num_msix
; i
++) {
408 adapter
->ahw
->intr_tbl
[i
].id
= i
;
409 adapter
->ahw
->intr_tbl
[i
].enabled
= 0;
410 adapter
->ahw
->intr_tbl
[i
].src
= 0;
413 if (qlcnic_sriov_pf_check(adapter
))
414 qlcnic_sriov_pf_reset(adapter
);
418 * qlcnic_83xx_idc_attach_driver
420 * @adapter: adapter structure
422 * Re-attach and re-enable net interface
426 static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter
*adapter
)
428 struct net_device
*netdev
= adapter
->netdev
;
430 if (netif_running(netdev
)) {
431 if (qlcnic_up(adapter
, netdev
))
433 qlcnic_restore_indev_addr(netdev
, NETDEV_UP
);
436 netif_device_attach(netdev
);
439 static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter
*adapter
,
443 if (qlcnic_83xx_lock_driver(adapter
))
447 qlcnic_83xx_idc_clear_registers(adapter
, 0);
448 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_DEV_STATE
, QLC_83XX_IDC_DEV_FAILED
);
450 qlcnic_83xx_unlock_driver(adapter
);
452 qlcnic_83xx_idc_log_state_history(adapter
);
453 dev_info(&adapter
->pdev
->dev
, "Device will enter failed state\n");
458 static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter
*adapter
,
462 if (qlcnic_83xx_lock_driver(adapter
))
466 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_DEV_STATE
, QLC_83XX_IDC_DEV_INIT
);
469 qlcnic_83xx_unlock_driver(adapter
);
474 static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter
*adapter
,
478 if (qlcnic_83xx_lock_driver(adapter
))
482 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_DEV_STATE
,
483 QLC_83XX_IDC_DEV_NEED_QUISCENT
);
486 qlcnic_83xx_unlock_driver(adapter
);
492 qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter
*adapter
, int lock
)
495 if (qlcnic_83xx_lock_driver(adapter
))
499 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_DEV_STATE
,
500 QLC_83XX_IDC_DEV_NEED_RESET
);
503 qlcnic_83xx_unlock_driver(adapter
);
508 static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter
*adapter
,
512 if (qlcnic_83xx_lock_driver(adapter
))
516 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_DEV_STATE
, QLC_83XX_IDC_DEV_READY
);
518 qlcnic_83xx_unlock_driver(adapter
);
524 * qlcnic_83xx_idc_find_reset_owner_id
526 * @adapter: adapter structure
528 * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE.
529 * Within the same class, function with lowest PCI ID assumes ownership
531 * Returns: reset owner id or failure indication (-EIO)
534 static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter
*adapter
)
536 u32 reg
, reg1
, reg2
, i
, j
, owner
, class;
538 reg1
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_DEV_PARTITION_INFO_1
);
539 reg2
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_DEV_PARTITION_INFO_2
);
540 owner
= QLCNIC_TYPE_NIC
;
546 class = (((reg
& (0xF << j
* 4)) >> j
* 4) & 0x3);
549 if (i
== (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO
- 1)) {
556 if (i
== (QLC_83XX_IDC_MAX_CNA_FUNCTIONS
- 1)) {
557 if (owner
== QLCNIC_TYPE_NIC
)
558 owner
= QLCNIC_TYPE_ISCSI
;
559 else if (owner
== QLCNIC_TYPE_ISCSI
)
560 owner
= QLCNIC_TYPE_FCOE
;
561 else if (owner
== QLCNIC_TYPE_FCOE
)
567 } while (i
++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS
);
572 static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter
*adapter
, int lock
)
576 ret
= qlcnic_83xx_restart_hw(adapter
);
579 qlcnic_83xx_idc_enter_failed_state(adapter
, lock
);
581 qlcnic_83xx_idc_clear_registers(adapter
, lock
);
582 ret
= qlcnic_83xx_idc_enter_ready_state(adapter
, lock
);
588 static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter
*adapter
)
592 status
= QLC_SHARED_REG_RD32(adapter
, QLCNIC_PEG_HALT_STATUS1
);
594 if (status
& QLCNIC_RCODE_FATAL_ERROR
) {
595 dev_err(&adapter
->pdev
->dev
,
596 "peg halt status1=0x%x\n", status
);
597 if (QLCNIC_FWERROR_CODE(status
) == QLCNIC_FWERROR_FAN_FAILURE
) {
598 dev_err(&adapter
->pdev
->dev
,
599 "On board active cooling fan failed. "
600 "Device has been halted.\n");
601 dev_err(&adapter
->pdev
->dev
,
602 "Replace the adapter.\n");
610 int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter
*adapter
)
614 qlcnic_83xx_reinit_mbx_work(adapter
->ahw
->mailbox
);
615 qlcnic_83xx_enable_mbx_interrupt(adapter
);
617 /* register for NIC IDC AEN Events */
618 qlcnic_83xx_register_nic_idc_func(adapter
, 1);
620 err
= qlcnic_sriov_pf_reinit(adapter
);
624 qlcnic_83xx_enable_mbx_interrupt(adapter
);
626 if (qlcnic_83xx_configure_opmode(adapter
)) {
627 qlcnic_83xx_idc_enter_failed_state(adapter
, 1);
631 if (adapter
->nic_ops
->init_driver(adapter
)) {
632 qlcnic_83xx_idc_enter_failed_state(adapter
, 1);
636 if (adapter
->portnum
== 0)
637 qlcnic_set_drv_version(adapter
);
639 qlcnic_dcb_get_info(adapter
->dcb
);
640 qlcnic_83xx_idc_attach_driver(adapter
);
645 static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter
*adapter
)
647 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
649 qlcnic_83xx_idc_update_drv_presence_reg(adapter
, 1, 1);
650 qlcnic_83xx_idc_update_audit_reg(adapter
, 0, 1);
651 set_bit(QLC_83XX_MODULE_LOADED
, &adapter
->ahw
->idc
.status
);
653 ahw
->idc
.quiesce_req
= 0;
654 ahw
->idc
.delay
= QLC_83XX_IDC_FW_POLL_DELAY
;
655 ahw
->idc
.err_code
= 0;
656 ahw
->idc
.collect_dump
= 0;
657 ahw
->reset_context
= 0;
658 adapter
->tx_timeo_cnt
= 0;
659 ahw
->idc
.delay_reset
= 0;
661 clear_bit(__QLCNIC_RESETTING
, &adapter
->state
);
665 * qlcnic_83xx_idc_ready_state_entry
667 * @adapter: adapter structure
669 * Perform ready state initialization, this routine will get invoked only
670 * once from READY state.
672 * Returns: Error code or Success(0)
675 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter
*adapter
)
677 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
679 if (ahw
->idc
.prev_state
!= QLC_83XX_IDC_DEV_READY
) {
680 qlcnic_83xx_idc_update_idc_params(adapter
);
681 /* Re-attach the device if required */
682 if ((ahw
->idc
.prev_state
== QLC_83XX_IDC_DEV_NEED_RESET
) ||
683 (ahw
->idc
.prev_state
== QLC_83XX_IDC_DEV_INIT
)) {
684 if (qlcnic_83xx_idc_reattach_driver(adapter
))
693 * qlcnic_83xx_idc_vnic_pf_entry
695 * @adapter: adapter structure
697 * Ensure vNIC mode privileged function starts only after vNIC mode is
698 * enabled by management function.
699 * If vNIC mode is ready, start initialization.
704 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter
*adapter
)
707 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
709 /* Privileged function waits till mgmt function enables VNIC mode */
710 state
= QLCRDX(adapter
->ahw
, QLC_83XX_VNIC_STATE
);
711 if (state
!= QLCNIC_DEV_NPAR_OPER
) {
712 if (!ahw
->idc
.vnic_wait_limit
--) {
713 qlcnic_83xx_idc_enter_failed_state(adapter
, 1);
716 dev_info(&adapter
->pdev
->dev
, "vNIC mode disabled\n");
720 /* Perform one time initialization from ready state */
721 if (ahw
->idc
.vnic_state
!= QLCNIC_DEV_NPAR_OPER
) {
722 qlcnic_83xx_idc_update_idc_params(adapter
);
724 /* If the previous state is UNKNOWN, device will be
725 already attached properly by Init routine*/
726 if (ahw
->idc
.prev_state
!= QLC_83XX_IDC_DEV_UNKNOWN
) {
727 if (qlcnic_83xx_idc_reattach_driver(adapter
))
730 adapter
->ahw
->idc
.vnic_state
= QLCNIC_DEV_NPAR_OPER
;
731 dev_info(&adapter
->pdev
->dev
, "vNIC mode enabled\n");
738 static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter
*adapter
)
740 adapter
->ahw
->idc
.err_code
= -EIO
;
741 dev_err(&adapter
->pdev
->dev
,
742 "%s: Device in unknown state\n", __func__
);
747 * qlcnic_83xx_idc_cold_state
749 * @adapter: adapter structure
751 * If HW is up and running device will enter READY state.
752 * If firmware image from host needs to be loaded, device is
753 * forced to start with the file firmware image.
755 * Returns: Error code or Success(0)
758 static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter
*adapter
)
760 qlcnic_83xx_idc_update_drv_presence_reg(adapter
, 1, 0);
761 qlcnic_83xx_idc_update_audit_reg(adapter
, 1, 0);
763 if (qlcnic_load_fw_file
) {
764 qlcnic_83xx_idc_restart_hw(adapter
, 0);
766 if (qlcnic_83xx_check_hw_status(adapter
)) {
767 qlcnic_83xx_idc_enter_failed_state(adapter
, 0);
770 qlcnic_83xx_idc_enter_ready_state(adapter
, 0);
777 * qlcnic_83xx_idc_init_state
779 * @adapter: adapter structure
781 * Reset owner will restart the device from this state.
782 * Device will enter failed state if it remains
783 * in this state for more than DEV_INIT time limit.
785 * Returns: Error code or Success(0)
788 static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter
*adapter
)
790 int timeout
, ret
= 0;
793 timeout
= QLC_83XX_IDC_INIT_TIMEOUT_SECS
;
794 if (adapter
->ahw
->idc
.prev_state
== QLC_83XX_IDC_DEV_NEED_RESET
) {
795 owner
= qlcnic_83xx_idc_find_reset_owner_id(adapter
);
796 if (adapter
->ahw
->pci_func
== owner
)
797 ret
= qlcnic_83xx_idc_restart_hw(adapter
, 1);
799 ret
= qlcnic_83xx_idc_check_timeout(adapter
, timeout
);
806 * qlcnic_83xx_idc_ready_state
808 * @adapter: adapter structure
810 * Perform IDC protocol specicifed actions after monitoring device state and
813 * Returns: Error code or Success(0)
816 static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter
*adapter
)
818 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
819 struct qlcnic_mailbox
*mbx
= ahw
->mailbox
;
824 /* Perform NIC configuration based ready state entry actions */
825 if (ahw
->idc
.state_entry(adapter
))
828 if (qlcnic_check_temp(adapter
)) {
829 if (ahw
->temp
== QLCNIC_TEMP_PANIC
) {
830 qlcnic_83xx_idc_check_fan_failure(adapter
);
831 dev_err(&adapter
->pdev
->dev
,
832 "Error: device temperature %d above limits\n",
834 clear_bit(QLC_83XX_MBX_READY
, &mbx
->status
);
835 set_bit(__QLCNIC_RESETTING
, &adapter
->state
);
836 qlcnic_83xx_idc_detach_driver(adapter
);
837 qlcnic_83xx_idc_enter_failed_state(adapter
, 1);
842 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_CTRL
);
843 ret
= qlcnic_83xx_check_heartbeat(adapter
);
845 adapter
->flags
|= QLCNIC_FW_HANG
;
846 if (!(val
& QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY
)) {
847 clear_bit(QLC_83XX_MBX_READY
, &mbx
->status
);
848 set_bit(__QLCNIC_RESETTING
, &adapter
->state
);
849 qlcnic_83xx_idc_enter_need_reset_state(adapter
, 1);
851 owner
= qlcnic_83xx_idc_find_reset_owner_id(adapter
);
852 if (ahw
->pci_func
== owner
)
853 qlcnic_dump_fw(adapter
);
858 if ((val
& QLC_83XX_IDC_GRACEFULL_RESET
) || ahw
->idc
.collect_dump
) {
859 clear_bit(QLC_83XX_MBX_READY
, &mbx
->status
);
861 /* Move to need reset state and prepare for reset */
862 qlcnic_83xx_idc_enter_need_reset_state(adapter
, 1);
866 /* Check for soft reset request */
867 if (ahw
->reset_context
&&
868 !(val
& QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY
)) {
869 adapter
->ahw
->reset_context
= 0;
870 qlcnic_83xx_idc_tx_soft_reset(adapter
);
874 /* Move to need quiesce state if requested */
875 if (adapter
->ahw
->idc
.quiesce_req
) {
876 qlcnic_83xx_idc_enter_need_quiesce(adapter
, 1);
877 qlcnic_83xx_idc_update_audit_reg(adapter
, 0, 1);
885 * qlcnic_83xx_idc_need_reset_state
887 * @adapter: adapter structure
889 * Device will remain in this state until:
890 * Reset request ACK's are recieved from all the functions
891 * Wait time exceeds max time limit
893 * Returns: Error code or Success(0)
896 static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter
*adapter
)
898 struct qlcnic_mailbox
*mbx
= adapter
->ahw
->mailbox
;
901 if (adapter
->ahw
->idc
.prev_state
!= QLC_83XX_IDC_DEV_NEED_RESET
) {
902 qlcnic_83xx_idc_update_audit_reg(adapter
, 0, 1);
903 set_bit(__QLCNIC_RESETTING
, &adapter
->state
);
904 clear_bit(QLC_83XX_MBX_READY
, &mbx
->status
);
905 if (adapter
->ahw
->nic_mode
== QLCNIC_VNIC_MODE
)
906 qlcnic_83xx_disable_vnic_mode(adapter
, 1);
908 if (qlcnic_check_diag_status(adapter
)) {
909 dev_info(&adapter
->pdev
->dev
,
910 "%s: Wait for diag completion\n", __func__
);
911 adapter
->ahw
->idc
.delay_reset
= 1;
914 qlcnic_83xx_idc_update_drv_ack_reg(adapter
, 1, 1);
915 qlcnic_83xx_idc_detach_driver(adapter
);
919 if (qlcnic_check_diag_status(adapter
)) {
920 dev_info(&adapter
->pdev
->dev
,
921 "%s: Wait for diag completion\n", __func__
);
924 if (adapter
->ahw
->idc
.delay_reset
) {
925 qlcnic_83xx_idc_update_drv_ack_reg(adapter
, 1, 1);
926 qlcnic_83xx_idc_detach_driver(adapter
);
927 adapter
->ahw
->idc
.delay_reset
= 0;
930 /* Check for ACK from other functions */
931 ret
= qlcnic_83xx_idc_check_reset_ack_reg(adapter
);
933 dev_info(&adapter
->pdev
->dev
,
934 "%s: Waiting for reset ACK\n", __func__
);
939 /* Transit to INIT state and restart the HW */
940 qlcnic_83xx_idc_enter_init_state(adapter
, 1);
945 static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter
*adapter
)
947 dev_err(&adapter
->pdev
->dev
, "%s: TBD\n", __func__
);
951 static int qlcnic_83xx_idc_failed_state(struct qlcnic_adapter
*adapter
)
953 dev_err(&adapter
->pdev
->dev
, "%s: please restart!!\n", __func__
);
954 clear_bit(__QLCNIC_RESETTING
, &adapter
->state
);
955 adapter
->ahw
->idc
.err_code
= -EIO
;
960 static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter
*adapter
)
962 dev_info(&adapter
->pdev
->dev
, "%s: TBD\n", __func__
);
966 static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter
*adapter
,
971 cur
= adapter
->ahw
->idc
.curr_state
;
972 prev
= adapter
->ahw
->idc
.prev_state
;
975 if ((next
< QLC_83XX_IDC_DEV_COLD
) ||
976 (next
> QLC_83XX_IDC_DEV_QUISCENT
)) {
977 dev_err(&adapter
->pdev
->dev
,
978 "%s: curr %d, prev %d, next state %d is invalid\n",
979 __func__
, cur
, prev
, state
);
983 if ((cur
== QLC_83XX_IDC_DEV_UNKNOWN
) &&
984 (prev
== QLC_83XX_IDC_DEV_UNKNOWN
)) {
985 if ((next
!= QLC_83XX_IDC_DEV_COLD
) &&
986 (next
!= QLC_83XX_IDC_DEV_READY
)) {
987 dev_err(&adapter
->pdev
->dev
,
988 "%s: failed, cur %d prev %d next %d\n",
989 __func__
, cur
, prev
, next
);
994 if (next
== QLC_83XX_IDC_DEV_INIT
) {
995 if ((prev
!= QLC_83XX_IDC_DEV_INIT
) &&
996 (prev
!= QLC_83XX_IDC_DEV_COLD
) &&
997 (prev
!= QLC_83XX_IDC_DEV_NEED_RESET
)) {
998 dev_err(&adapter
->pdev
->dev
,
999 "%s: failed, cur %d prev %d next %d\n",
1000 __func__
, cur
, prev
, next
);
1008 static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter
*adapter
)
1010 if (adapter
->fhash
.fnum
)
1011 qlcnic_prune_lb_filters(adapter
);
1015 * qlcnic_83xx_idc_poll_dev_state
1017 * @work: kernel work queue structure used to schedule the function
1019 * Poll device state periodically and perform state specific
1020 * actions defined by Inter Driver Communication (IDC) protocol.
1025 void qlcnic_83xx_idc_poll_dev_state(struct work_struct
*work
)
1027 struct qlcnic_adapter
*adapter
;
1030 adapter
= container_of(work
, struct qlcnic_adapter
, fw_work
.work
);
1031 state
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_DEV_STATE
);
1033 if (qlcnic_83xx_idc_check_state_validity(adapter
, state
)) {
1034 qlcnic_83xx_idc_log_state_history(adapter
);
1035 adapter
->ahw
->idc
.curr_state
= QLC_83XX_IDC_DEV_UNKNOWN
;
1037 adapter
->ahw
->idc
.curr_state
= state
;
1040 switch (adapter
->ahw
->idc
.curr_state
) {
1041 case QLC_83XX_IDC_DEV_READY
:
1042 qlcnic_83xx_idc_ready_state(adapter
);
1044 case QLC_83XX_IDC_DEV_NEED_RESET
:
1045 qlcnic_83xx_idc_need_reset_state(adapter
);
1047 case QLC_83XX_IDC_DEV_NEED_QUISCENT
:
1048 qlcnic_83xx_idc_need_quiesce_state(adapter
);
1050 case QLC_83XX_IDC_DEV_FAILED
:
1051 qlcnic_83xx_idc_failed_state(adapter
);
1053 case QLC_83XX_IDC_DEV_INIT
:
1054 qlcnic_83xx_idc_init_state(adapter
);
1056 case QLC_83XX_IDC_DEV_QUISCENT
:
1057 qlcnic_83xx_idc_quiesce_state(adapter
);
1060 qlcnic_83xx_idc_unknown_state(adapter
);
1063 adapter
->ahw
->idc
.prev_state
= adapter
->ahw
->idc
.curr_state
;
1064 qlcnic_83xx_periodic_tasks(adapter
);
1066 /* Do not reschedule if firmaware is in hanged state and auto
1067 * recovery is disabled
1069 if ((adapter
->flags
& QLCNIC_FW_HANG
) && !qlcnic_auto_fw_reset
)
1072 /* Re-schedule the function */
1073 if (test_bit(QLC_83XX_MODULE_LOADED
, &adapter
->ahw
->idc
.status
))
1074 qlcnic_schedule_work(adapter
, qlcnic_83xx_idc_poll_dev_state
,
1075 adapter
->ahw
->idc
.delay
);
1078 static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter
*adapter
)
1080 u32 idc_params
, val
;
1082 if (qlcnic_83xx_lockless_flash_read32(adapter
,
1083 QLC_83XX_IDC_FLASH_PARAM_ADDR
,
1084 (u8
*)&idc_params
, 1)) {
1085 dev_info(&adapter
->pdev
->dev
,
1086 "%s:failed to get IDC params from flash\n", __func__
);
1087 adapter
->dev_init_timeo
= QLC_83XX_IDC_INIT_TIMEOUT_SECS
;
1088 adapter
->reset_ack_timeo
= QLC_83XX_IDC_RESET_TIMEOUT_SECS
;
1090 adapter
->dev_init_timeo
= idc_params
& 0xFFFF;
1091 adapter
->reset_ack_timeo
= ((idc_params
>> 16) & 0xFFFF);
1094 adapter
->ahw
->idc
.curr_state
= QLC_83XX_IDC_DEV_UNKNOWN
;
1095 adapter
->ahw
->idc
.prev_state
= QLC_83XX_IDC_DEV_UNKNOWN
;
1096 adapter
->ahw
->idc
.delay
= QLC_83XX_IDC_FW_POLL_DELAY
;
1097 adapter
->ahw
->idc
.err_code
= 0;
1098 adapter
->ahw
->idc
.collect_dump
= 0;
1099 adapter
->ahw
->idc
.name
= (char **)qlc_83xx_idc_states
;
1101 clear_bit(__QLCNIC_RESETTING
, &adapter
->state
);
1102 set_bit(QLC_83XX_MODULE_LOADED
, &adapter
->ahw
->idc
.status
);
1104 /* Check if reset recovery is disabled */
1105 if (!qlcnic_auto_fw_reset
) {
1106 /* Propagate do not reset request to other functions */
1107 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_CTRL
);
1108 val
= val
| QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY
;
1109 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_CTRL
, val
);
1114 qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter
*adapter
)
1118 if (qlcnic_83xx_lock_driver(adapter
))
1121 /* Clear driver lock register */
1122 QLCWRX(adapter
->ahw
, QLC_83XX_RECOVER_DRV_LOCK
, 0);
1123 if (qlcnic_83xx_idc_update_major_version(adapter
, 0)) {
1124 qlcnic_83xx_unlock_driver(adapter
);
1128 state
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_DEV_STATE
);
1129 if (qlcnic_83xx_idc_check_state_validity(adapter
, state
)) {
1130 qlcnic_83xx_unlock_driver(adapter
);
1134 if (state
!= QLC_83XX_IDC_DEV_COLD
&& qlcnic_load_fw_file
) {
1135 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_DEV_STATE
,
1136 QLC_83XX_IDC_DEV_COLD
);
1137 state
= QLC_83XX_IDC_DEV_COLD
;
1140 adapter
->ahw
->idc
.curr_state
= state
;
1141 /* First to load function should cold boot the device */
1142 if (state
== QLC_83XX_IDC_DEV_COLD
)
1143 qlcnic_83xx_idc_cold_state_handler(adapter
);
1145 /* Check if reset recovery is enabled */
1146 if (qlcnic_auto_fw_reset
) {
1147 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_CTRL
);
1148 val
= val
& ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY
;
1149 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_CTRL
, val
);
1152 qlcnic_83xx_unlock_driver(adapter
);
1157 int qlcnic_83xx_idc_init(struct qlcnic_adapter
*adapter
)
1161 qlcnic_83xx_setup_idc_parameters(adapter
);
1163 if (qlcnic_83xx_get_reset_instruction_template(adapter
))
1166 if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter
)) {
1167 if (qlcnic_83xx_idc_first_to_load_function_handler(adapter
))
1170 if (qlcnic_83xx_idc_check_major_version(adapter
))
1174 qlcnic_83xx_idc_update_audit_reg(adapter
, 0, 1);
1179 void qlcnic_83xx_idc_exit(struct qlcnic_adapter
*adapter
)
1184 while (test_and_set_bit(__QLCNIC_RESETTING
, &adapter
->state
))
1185 usleep_range(10000, 11000);
1187 id
= QLCRDX(adapter
->ahw
, QLC_83XX_DRV_LOCK_ID
);
1190 if (id
== adapter
->portnum
) {
1191 dev_err(&adapter
->pdev
->dev
,
1192 "%s: wait for lock recovery.. %d\n", __func__
, id
);
1194 id
= QLCRDX(adapter
->ahw
, QLC_83XX_DRV_LOCK_ID
);
1198 /* Clear driver presence bit */
1199 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_DRV_PRESENCE
);
1200 val
= val
& ~(1 << adapter
->portnum
);
1201 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_DRV_PRESENCE
, val
);
1202 clear_bit(QLC_83XX_MODULE_LOADED
, &adapter
->ahw
->idc
.status
);
1203 clear_bit(__QLCNIC_RESETTING
, &adapter
->state
);
1205 cancel_delayed_work_sync(&adapter
->fw_work
);
1208 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter
*adapter
, u32 key
)
1212 if (qlcnic_sriov_vf_check(adapter
))
1215 if (qlcnic_83xx_lock_driver(adapter
)) {
1216 dev_err(&adapter
->pdev
->dev
,
1217 "%s:failed, please retry\n", __func__
);
1221 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_CTRL
);
1222 if ((val
& QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY
) ||
1223 !qlcnic_auto_fw_reset
) {
1224 dev_err(&adapter
->pdev
->dev
,
1225 "%s:failed, device in non reset mode\n", __func__
);
1226 qlcnic_83xx_unlock_driver(adapter
);
1230 if (key
== QLCNIC_FORCE_FW_RESET
) {
1231 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_CTRL
);
1232 val
= val
| QLC_83XX_IDC_GRACEFULL_RESET
;
1233 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_CTRL
, val
);
1234 } else if (key
== QLCNIC_FORCE_FW_DUMP_KEY
) {
1235 adapter
->ahw
->idc
.collect_dump
= 1;
1238 qlcnic_83xx_unlock_driver(adapter
);
1242 static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter
*adapter
)
1249 src
= QLC_83XX_BOOTLOADER_FLASH_ADDR
;
1250 dest
= QLCRDX(adapter
->ahw
, QLCNIC_BOOTLOADER_ADDR
);
1251 size
= QLCRDX(adapter
->ahw
, QLCNIC_BOOTLOADER_SIZE
);
1253 /* alignment check */
1255 size
= (size
+ 16) & ~0xF;
1257 p_cache
= kzalloc(size
, GFP_KERNEL
);
1258 if (p_cache
== NULL
)
1261 ret
= qlcnic_83xx_lockless_flash_read32(adapter
, src
, p_cache
,
1262 size
/ sizeof(u32
));
1267 /* 16 byte write to MS memory */
1268 ret
= qlcnic_83xx_ms_mem_write128(adapter
, dest
, (u32
*)p_cache
,
1279 static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter
*adapter
)
1281 struct qlc_83xx_fw_info
*fw_info
= adapter
->ahw
->fw_info
;
1282 const struct firmware
*fw
= fw_info
->fw
;
1289 dest
= QLCRDX(adapter
->ahw
, QLCNIC_FW_IMAGE_ADDR
);
1290 size
= (fw
->size
& ~0xF);
1291 p_cache
= (u32
*)fw
->data
;
1294 ret
= qlcnic_83xx_ms_mem_write128(adapter
, addr
,
1295 (u32
*)p_cache
, size
/ 16);
1297 dev_err(&adapter
->pdev
->dev
, "MS memory write failed\n");
1298 release_firmware(fw
);
1303 /* alignment check */
1304 if (fw
->size
& 0xF) {
1306 for (i
= 0; i
< (fw
->size
& 0xF); i
++)
1307 data
[i
] = fw
->data
[size
+ i
];
1310 ret
= qlcnic_83xx_ms_mem_write128(adapter
, addr
,
1313 dev_err(&adapter
->pdev
->dev
,
1314 "MS memory write failed\n");
1315 release_firmware(fw
);
1320 release_firmware(fw
);
1326 static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter
*adapter
)
1329 u32 val
= 0, val1
= 0, reg
= 0;
1332 val
= QLCRD32(adapter
, QLC_83XX_SRE_SHIM_REG
, &err
);
1335 dev_info(&adapter
->pdev
->dev
, "SRE-Shim Ctrl:0x%x\n", val
);
1337 for (j
= 0; j
< 2; j
++) {
1339 dev_info(&adapter
->pdev
->dev
,
1340 "Port 0 RxB Pause Threshold Regs[TC7..TC0]:");
1341 reg
= QLC_83XX_PORT0_THRESHOLD
;
1342 } else if (j
== 1) {
1343 dev_info(&adapter
->pdev
->dev
,
1344 "Port 1 RxB Pause Threshold Regs[TC7..TC0]:");
1345 reg
= QLC_83XX_PORT1_THRESHOLD
;
1347 for (i
= 0; i
< 8; i
++) {
1348 val
= QLCRD32(adapter
, reg
+ (i
* 0x4), &err
);
1351 dev_info(&adapter
->pdev
->dev
, "0x%x ", val
);
1353 dev_info(&adapter
->pdev
->dev
, "\n");
1356 for (j
= 0; j
< 2; j
++) {
1358 dev_info(&adapter
->pdev
->dev
,
1359 "Port 0 RxB TC Max Cell Registers[4..1]:");
1360 reg
= QLC_83XX_PORT0_TC_MC_REG
;
1361 } else if (j
== 1) {
1362 dev_info(&adapter
->pdev
->dev
,
1363 "Port 1 RxB TC Max Cell Registers[4..1]:");
1364 reg
= QLC_83XX_PORT1_TC_MC_REG
;
1366 for (i
= 0; i
< 4; i
++) {
1367 val
= QLCRD32(adapter
, reg
+ (i
* 0x4), &err
);
1370 dev_info(&adapter
->pdev
->dev
, "0x%x ", val
);
1372 dev_info(&adapter
->pdev
->dev
, "\n");
1375 for (j
= 0; j
< 2; j
++) {
1377 dev_info(&adapter
->pdev
->dev
,
1378 "Port 0 RxB Rx TC Stats[TC7..TC0]:");
1379 reg
= QLC_83XX_PORT0_TC_STATS
;
1380 } else if (j
== 1) {
1381 dev_info(&adapter
->pdev
->dev
,
1382 "Port 1 RxB Rx TC Stats[TC7..TC0]:");
1383 reg
= QLC_83XX_PORT1_TC_STATS
;
1385 for (i
= 7; i
>= 0; i
--) {
1386 val
= QLCRD32(adapter
, reg
, &err
);
1389 val
&= ~(0x7 << 29); /* Reset bits 29 to 31 */
1390 QLCWR32(adapter
, reg
, (val
| (i
<< 29)));
1391 val
= QLCRD32(adapter
, reg
, &err
);
1394 dev_info(&adapter
->pdev
->dev
, "0x%x ", val
);
1396 dev_info(&adapter
->pdev
->dev
, "\n");
1399 val
= QLCRD32(adapter
, QLC_83XX_PORT2_IFB_THRESHOLD
, &err
);
1402 val1
= QLCRD32(adapter
, QLC_83XX_PORT3_IFB_THRESHOLD
, &err
);
1405 dev_info(&adapter
->pdev
->dev
,
1406 "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n",
1411 static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter
*adapter
)
1415 if (qlcnic_83xx_lock_driver(adapter
)) {
1416 dev_err(&adapter
->pdev
->dev
,
1417 "%s:failed to acquire driver lock\n", __func__
);
1421 qlcnic_83xx_dump_pause_control_regs(adapter
);
1422 QLCWR32(adapter
, QLC_83XX_SRE_SHIM_REG
, 0x0);
1424 for (j
= 0; j
< 2; j
++) {
1426 reg
= QLC_83XX_PORT0_THRESHOLD
;
1428 reg
= QLC_83XX_PORT1_THRESHOLD
;
1430 for (i
= 0; i
< 8; i
++)
1431 QLCWR32(adapter
, reg
+ (i
* 0x4), 0x0);
1434 for (j
= 0; j
< 2; j
++) {
1436 reg
= QLC_83XX_PORT0_TC_MC_REG
;
1438 reg
= QLC_83XX_PORT1_TC_MC_REG
;
1440 for (i
= 0; i
< 4; i
++)
1441 QLCWR32(adapter
, reg
+ (i
* 0x4), 0x03FF03FF);
1444 QLCWR32(adapter
, QLC_83XX_PORT2_IFB_THRESHOLD
, 0);
1445 QLCWR32(adapter
, QLC_83XX_PORT3_IFB_THRESHOLD
, 0);
1446 dev_info(&adapter
->pdev
->dev
,
1447 "Disabled pause frames successfully on all ports\n");
1448 qlcnic_83xx_unlock_driver(adapter
);
1451 static void qlcnic_83xx_take_eport_out_of_reset(struct qlcnic_adapter
*adapter
)
1453 QLCWR32(adapter
, QLC_83XX_RESET_REG
, 0);
1454 QLCWR32(adapter
, QLC_83XX_RESET_PORT0
, 0);
1455 QLCWR32(adapter
, QLC_83XX_RESET_PORT1
, 0);
1456 QLCWR32(adapter
, QLC_83XX_RESET_PORT2
, 0);
1457 QLCWR32(adapter
, QLC_83XX_RESET_PORT3
, 0);
1458 QLCWR32(adapter
, QLC_83XX_RESET_SRESHIM
, 0);
1459 QLCWR32(adapter
, QLC_83XX_RESET_EPGSHIM
, 0);
1460 QLCWR32(adapter
, QLC_83XX_RESET_ETHERPCS
, 0);
1461 QLCWR32(adapter
, QLC_83XX_RESET_CONTROL
, 1);
1464 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter
*p_dev
)
1466 u32 heartbeat
, peg_status
;
1467 int retries
, ret
= -EIO
, err
= 0;
1469 retries
= QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT
;
1470 p_dev
->heartbeat
= QLC_SHARED_REG_RD32(p_dev
,
1471 QLCNIC_PEG_ALIVE_COUNTER
);
1474 msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS
);
1475 heartbeat
= QLC_SHARED_REG_RD32(p_dev
,
1476 QLCNIC_PEG_ALIVE_COUNTER
);
1477 if (heartbeat
!= p_dev
->heartbeat
) {
1478 ret
= QLCNIC_RCODE_SUCCESS
;
1481 } while (--retries
);
1484 dev_err(&p_dev
->pdev
->dev
, "firmware hang detected\n");
1485 qlcnic_83xx_take_eport_out_of_reset(p_dev
);
1486 qlcnic_83xx_disable_pause_frames(p_dev
);
1487 peg_status
= QLC_SHARED_REG_RD32(p_dev
,
1488 QLCNIC_PEG_HALT_STATUS1
);
1489 dev_info(&p_dev
->pdev
->dev
, "Dumping HW/FW registers\n"
1490 "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n"
1491 "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n"
1492 "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n"
1493 "PEG_NET_4_PC: 0x%x\n", peg_status
,
1494 QLC_SHARED_REG_RD32(p_dev
, QLCNIC_PEG_HALT_STATUS2
),
1495 QLCRD32(p_dev
, QLC_83XX_CRB_PEG_NET_0
, &err
),
1496 QLCRD32(p_dev
, QLC_83XX_CRB_PEG_NET_1
, &err
),
1497 QLCRD32(p_dev
, QLC_83XX_CRB_PEG_NET_2
, &err
),
1498 QLCRD32(p_dev
, QLC_83XX_CRB_PEG_NET_3
, &err
),
1499 QLCRD32(p_dev
, QLC_83XX_CRB_PEG_NET_4
, &err
));
1501 if (QLCNIC_FWERROR_CODE(peg_status
) == 0x67)
1502 dev_err(&p_dev
->pdev
->dev
,
1503 "Device is being reset err code 0x00006700.\n");
1509 static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter
*p_dev
)
1511 int retries
= QLCNIC_CMDPEG_CHECK_RETRY_COUNT
;
1515 val
= QLC_SHARED_REG_RD32(p_dev
, QLCNIC_CMDPEG_STATE
);
1516 if (val
== QLC_83XX_CMDPEG_COMPLETE
)
1518 msleep(QLCNIC_CMDPEG_CHECK_DELAY
);
1519 } while (--retries
);
1521 dev_err(&p_dev
->pdev
->dev
, "%s: failed, state = 0x%x\n", __func__
, val
);
1525 int qlcnic_83xx_check_hw_status(struct qlcnic_adapter
*p_dev
)
1529 err
= qlcnic_83xx_check_cmd_peg_status(p_dev
);
1533 err
= qlcnic_83xx_check_heartbeat(p_dev
);
1540 static int qlcnic_83xx_poll_reg(struct qlcnic_adapter
*p_dev
, u32 addr
,
1541 int duration
, u32 mask
, u32 status
)
1543 int timeout_error
, err
= 0;
1547 value
= QLCRD32(p_dev
, addr
, &err
);
1550 retries
= duration
/ 10;
1553 if ((value
& mask
) != status
) {
1555 msleep(duration
/ 10);
1556 value
= QLCRD32(p_dev
, addr
, &err
);
1563 } while (retries
--);
1565 if (timeout_error
) {
1566 p_dev
->ahw
->reset
.seq_error
++;
1567 dev_err(&p_dev
->pdev
->dev
,
1568 "%s: Timeout Err, entry_num = %d\n",
1569 __func__
, p_dev
->ahw
->reset
.seq_index
);
1570 dev_err(&p_dev
->pdev
->dev
,
1571 "0x%08x 0x%08x 0x%08x\n",
1572 value
, mask
, status
);
1575 return timeout_error
;
1578 static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter
*p_dev
)
1581 u16
*buff
= (u16
*)p_dev
->ahw
->reset
.buff
;
1582 int count
= p_dev
->ahw
->reset
.hdr
->size
/ sizeof(u16
);
1588 sum
= (sum
& 0xFFFF) + (sum
>> 16);
1593 dev_err(&p_dev
->pdev
->dev
, "%s: failed\n", __func__
);
1598 int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter
*p_dev
)
1600 struct qlcnic_hardware_context
*ahw
= p_dev
->ahw
;
1601 u32 addr
, count
, prev_ver
, curr_ver
;
1604 if (ahw
->reset
.buff
!= NULL
) {
1605 prev_ver
= p_dev
->fw_version
;
1606 curr_ver
= qlcnic_83xx_get_fw_version(p_dev
);
1607 if (curr_ver
> prev_ver
)
1608 kfree(ahw
->reset
.buff
);
1613 ahw
->reset
.seq_error
= 0;
1614 ahw
->reset
.buff
= kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE
, GFP_KERNEL
);
1615 if (p_dev
->ahw
->reset
.buff
== NULL
)
1618 p_buff
= p_dev
->ahw
->reset
.buff
;
1619 addr
= QLC_83XX_RESET_TEMPLATE_ADDR
;
1620 count
= sizeof(struct qlc_83xx_reset_hdr
) / sizeof(u32
);
1622 /* Copy template header from flash */
1623 if (qlcnic_83xx_flash_read32(p_dev
, addr
, p_buff
, count
)) {
1624 dev_err(&p_dev
->pdev
->dev
, "%s: flash read failed\n", __func__
);
1627 ahw
->reset
.hdr
= (struct qlc_83xx_reset_hdr
*)ahw
->reset
.buff
;
1628 addr
= QLC_83XX_RESET_TEMPLATE_ADDR
+ ahw
->reset
.hdr
->hdr_size
;
1629 p_buff
= ahw
->reset
.buff
+ ahw
->reset
.hdr
->hdr_size
;
1630 count
= (ahw
->reset
.hdr
->size
- ahw
->reset
.hdr
->hdr_size
) / sizeof(u32
);
1632 /* Copy rest of the template */
1633 if (qlcnic_83xx_flash_read32(p_dev
, addr
, p_buff
, count
)) {
1634 dev_err(&p_dev
->pdev
->dev
, "%s: flash read failed\n", __func__
);
1638 if (qlcnic_83xx_reset_template_checksum(p_dev
))
1640 /* Get Stop, Start and Init command offsets */
1641 ahw
->reset
.init_offset
= ahw
->reset
.buff
+ ahw
->reset
.hdr
->init_offset
;
1642 ahw
->reset
.start_offset
= ahw
->reset
.buff
+
1643 ahw
->reset
.hdr
->start_offset
;
1644 ahw
->reset
.stop_offset
= ahw
->reset
.buff
+ ahw
->reset
.hdr
->hdr_size
;
1648 /* Read Write HW register command */
1649 static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter
*p_dev
,
1650 u32 raddr
, u32 waddr
)
1655 value
= QLCRD32(p_dev
, raddr
, &err
);
1658 qlcnic_83xx_wrt_reg_indirect(p_dev
, waddr
, value
);
1661 /* Read Modify Write HW register command */
1662 static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter
*p_dev
,
1663 u32 raddr
, u32 waddr
,
1664 struct qlc_83xx_rmw
*p_rmw_hdr
)
1669 if (p_rmw_hdr
->index_a
) {
1670 value
= p_dev
->ahw
->reset
.array
[p_rmw_hdr
->index_a
];
1672 value
= QLCRD32(p_dev
, raddr
, &err
);
1677 value
&= p_rmw_hdr
->mask
;
1678 value
<<= p_rmw_hdr
->shl
;
1679 value
>>= p_rmw_hdr
->shr
;
1680 value
|= p_rmw_hdr
->or_value
;
1681 value
^= p_rmw_hdr
->xor_value
;
1682 qlcnic_83xx_wrt_reg_indirect(p_dev
, waddr
, value
);
1685 /* Write HW register command */
1686 static void qlcnic_83xx_write_list(struct qlcnic_adapter
*p_dev
,
1687 struct qlc_83xx_entry_hdr
*p_hdr
)
1690 struct qlc_83xx_entry
*entry
;
1692 entry
= (struct qlc_83xx_entry
*)((char *)p_hdr
+
1693 sizeof(struct qlc_83xx_entry_hdr
));
1695 for (i
= 0; i
< p_hdr
->count
; i
++, entry
++) {
1696 qlcnic_83xx_wrt_reg_indirect(p_dev
, entry
->arg1
,
1699 udelay((u32
)(p_hdr
->delay
));
1703 /* Read and Write instruction */
1704 static void qlcnic_83xx_read_write_list(struct qlcnic_adapter
*p_dev
,
1705 struct qlc_83xx_entry_hdr
*p_hdr
)
1708 struct qlc_83xx_entry
*entry
;
1710 entry
= (struct qlc_83xx_entry
*)((char *)p_hdr
+
1711 sizeof(struct qlc_83xx_entry_hdr
));
1713 for (i
= 0; i
< p_hdr
->count
; i
++, entry
++) {
1714 qlcnic_83xx_read_write_crb_reg(p_dev
, entry
->arg1
,
1717 udelay((u32
)(p_hdr
->delay
));
1721 /* Poll HW register command */
1722 static void qlcnic_83xx_poll_list(struct qlcnic_adapter
*p_dev
,
1723 struct qlc_83xx_entry_hdr
*p_hdr
)
1726 struct qlc_83xx_entry
*entry
;
1727 struct qlc_83xx_poll
*poll
;
1729 unsigned long arg1
, arg2
;
1731 poll
= (struct qlc_83xx_poll
*)((char *)p_hdr
+
1732 sizeof(struct qlc_83xx_entry_hdr
));
1734 entry
= (struct qlc_83xx_entry
*)((char *)poll
+
1735 sizeof(struct qlc_83xx_poll
));
1736 delay
= (long)p_hdr
->delay
;
1739 for (i
= 0; i
< p_hdr
->count
; i
++, entry
++)
1740 qlcnic_83xx_poll_reg(p_dev
, entry
->arg1
,
1744 for (i
= 0; i
< p_hdr
->count
; i
++, entry
++) {
1748 if (qlcnic_83xx_poll_reg(p_dev
,
1752 QLCRD32(p_dev
, arg1
, &err
);
1755 QLCRD32(p_dev
, arg2
, &err
);
1764 /* Poll and write HW register command */
1765 static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter
*p_dev
,
1766 struct qlc_83xx_entry_hdr
*p_hdr
)
1770 struct qlc_83xx_quad_entry
*entry
;
1771 struct qlc_83xx_poll
*poll
;
1773 poll
= (struct qlc_83xx_poll
*)((char *)p_hdr
+
1774 sizeof(struct qlc_83xx_entry_hdr
));
1775 entry
= (struct qlc_83xx_quad_entry
*)((char *)poll
+
1776 sizeof(struct qlc_83xx_poll
));
1777 delay
= (long)p_hdr
->delay
;
1779 for (i
= 0; i
< p_hdr
->count
; i
++, entry
++) {
1780 qlcnic_83xx_wrt_reg_indirect(p_dev
, entry
->dr_addr
,
1782 qlcnic_83xx_wrt_reg_indirect(p_dev
, entry
->ar_addr
,
1785 qlcnic_83xx_poll_reg(p_dev
, entry
->ar_addr
, delay
,
1786 poll
->mask
, poll
->status
);
1790 /* Read Modify Write register command */
1791 static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter
*p_dev
,
1792 struct qlc_83xx_entry_hdr
*p_hdr
)
1795 struct qlc_83xx_entry
*entry
;
1796 struct qlc_83xx_rmw
*rmw_hdr
;
1798 rmw_hdr
= (struct qlc_83xx_rmw
*)((char *)p_hdr
+
1799 sizeof(struct qlc_83xx_entry_hdr
));
1801 entry
= (struct qlc_83xx_entry
*)((char *)rmw_hdr
+
1802 sizeof(struct qlc_83xx_rmw
));
1804 for (i
= 0; i
< p_hdr
->count
; i
++, entry
++) {
1805 qlcnic_83xx_rmw_crb_reg(p_dev
, entry
->arg1
,
1806 entry
->arg2
, rmw_hdr
);
1808 udelay((u32
)(p_hdr
->delay
));
1812 static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr
*p_hdr
)
1815 mdelay((u32
)((long)p_hdr
->delay
));
1818 /* Read and poll register command */
1819 static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter
*p_dev
,
1820 struct qlc_83xx_entry_hdr
*p_hdr
)
1823 int index
, i
, j
, err
;
1824 struct qlc_83xx_quad_entry
*entry
;
1825 struct qlc_83xx_poll
*poll
;
1828 poll
= (struct qlc_83xx_poll
*)((char *)p_hdr
+
1829 sizeof(struct qlc_83xx_entry_hdr
));
1831 entry
= (struct qlc_83xx_quad_entry
*)((char *)poll
+
1832 sizeof(struct qlc_83xx_poll
));
1833 delay
= (long)p_hdr
->delay
;
1835 for (i
= 0; i
< p_hdr
->count
; i
++, entry
++) {
1836 qlcnic_83xx_wrt_reg_indirect(p_dev
, entry
->ar_addr
,
1839 if (!qlcnic_83xx_poll_reg(p_dev
, entry
->ar_addr
, delay
,
1840 poll
->mask
, poll
->status
)){
1841 index
= p_dev
->ahw
->reset
.array_index
;
1842 addr
= entry
->dr_addr
;
1843 j
= QLCRD32(p_dev
, addr
, &err
);
1847 p_dev
->ahw
->reset
.array
[index
++] = j
;
1849 if (index
== QLC_83XX_MAX_RESET_SEQ_ENTRIES
)
1850 p_dev
->ahw
->reset
.array_index
= 1;
1856 static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter
*p_dev
)
1858 p_dev
->ahw
->reset
.seq_end
= 1;
1861 static void qlcnic_83xx_template_end(struct qlcnic_adapter
*p_dev
)
1863 p_dev
->ahw
->reset
.template_end
= 1;
1864 if (p_dev
->ahw
->reset
.seq_error
== 0)
1865 dev_err(&p_dev
->pdev
->dev
,
1866 "HW restart process completed successfully.\n");
1868 dev_err(&p_dev
->pdev
->dev
,
1869 "HW restart completed with timeout errors.\n");
1873 * qlcnic_83xx_exec_template_cmd
1875 * @p_dev: adapter structure
1876 * @p_buff: Poiter to instruction template
1878 * Template provides instructions to stop, restart and initalize firmware.
1879 * These instructions are abstracted as a series of read, write and
1880 * poll operations on hardware registers. Register information and operation
1881 * specifics are not exposed to the driver. Driver reads the template from
1882 * flash and executes the instructions located at pre-defined offsets.
1886 static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter
*p_dev
,
1890 struct qlc_83xx_entry_hdr
*p_hdr
;
1891 char *entry
= p_buff
;
1893 p_dev
->ahw
->reset
.seq_end
= 0;
1894 p_dev
->ahw
->reset
.template_end
= 0;
1895 entries
= p_dev
->ahw
->reset
.hdr
->entries
;
1896 index
= p_dev
->ahw
->reset
.seq_index
;
1898 for (; (!p_dev
->ahw
->reset
.seq_end
) && (index
< entries
); index
++) {
1899 p_hdr
= (struct qlc_83xx_entry_hdr
*)entry
;
1901 switch (p_hdr
->cmd
) {
1902 case QLC_83XX_OPCODE_NOP
:
1904 case QLC_83XX_OPCODE_WRITE_LIST
:
1905 qlcnic_83xx_write_list(p_dev
, p_hdr
);
1907 case QLC_83XX_OPCODE_READ_WRITE_LIST
:
1908 qlcnic_83xx_read_write_list(p_dev
, p_hdr
);
1910 case QLC_83XX_OPCODE_POLL_LIST
:
1911 qlcnic_83xx_poll_list(p_dev
, p_hdr
);
1913 case QLC_83XX_OPCODE_POLL_WRITE_LIST
:
1914 qlcnic_83xx_poll_write_list(p_dev
, p_hdr
);
1916 case QLC_83XX_OPCODE_READ_MODIFY_WRITE
:
1917 qlcnic_83xx_read_modify_write(p_dev
, p_hdr
);
1919 case QLC_83XX_OPCODE_SEQ_PAUSE
:
1920 qlcnic_83xx_pause(p_hdr
);
1922 case QLC_83XX_OPCODE_SEQ_END
:
1923 qlcnic_83xx_seq_end(p_dev
);
1925 case QLC_83XX_OPCODE_TMPL_END
:
1926 qlcnic_83xx_template_end(p_dev
);
1928 case QLC_83XX_OPCODE_POLL_READ_LIST
:
1929 qlcnic_83xx_poll_read_list(p_dev
, p_hdr
);
1932 dev_err(&p_dev
->pdev
->dev
,
1933 "%s: Unknown opcode 0x%04x in template %d\n",
1934 __func__
, p_hdr
->cmd
, index
);
1937 entry
+= p_hdr
->size
;
1939 p_dev
->ahw
->reset
.seq_index
= index
;
1942 static void qlcnic_83xx_stop_hw(struct qlcnic_adapter
*p_dev
)
1944 p_dev
->ahw
->reset
.seq_index
= 0;
1946 qlcnic_83xx_exec_template_cmd(p_dev
, p_dev
->ahw
->reset
.stop_offset
);
1947 if (p_dev
->ahw
->reset
.seq_end
!= 1)
1948 dev_err(&p_dev
->pdev
->dev
, "%s: failed\n", __func__
);
1951 static void qlcnic_83xx_start_hw(struct qlcnic_adapter
*p_dev
)
1953 qlcnic_83xx_exec_template_cmd(p_dev
, p_dev
->ahw
->reset
.start_offset
);
1954 if (p_dev
->ahw
->reset
.template_end
!= 1)
1955 dev_err(&p_dev
->pdev
->dev
, "%s: failed\n", __func__
);
1958 static void qlcnic_83xx_init_hw(struct qlcnic_adapter
*p_dev
)
1960 qlcnic_83xx_exec_template_cmd(p_dev
, p_dev
->ahw
->reset
.init_offset
);
1961 if (p_dev
->ahw
->reset
.seq_end
!= 1)
1962 dev_err(&p_dev
->pdev
->dev
, "%s: failed\n", __func__
);
1965 static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter
*adapter
)
1967 struct qlc_83xx_fw_info
*fw_info
= adapter
->ahw
->fw_info
;
1970 if (request_firmware(&fw_info
->fw
, fw_info
->fw_file_name
,
1971 &(adapter
->pdev
->dev
))) {
1972 dev_err(&adapter
->pdev
->dev
,
1973 "No file FW image, loading flash FW image.\n");
1974 QLC_SHARED_REG_WR32(adapter
, QLCNIC_FW_IMG_VALID
,
1975 QLC_83XX_BOOT_FROM_FLASH
);
1977 if (qlcnic_83xx_copy_fw_file(adapter
))
1979 QLC_SHARED_REG_WR32(adapter
, QLCNIC_FW_IMG_VALID
,
1980 QLC_83XX_BOOT_FROM_FILE
);
1986 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter
*adapter
)
1991 qlcnic_83xx_stop_hw(adapter
);
1993 /* Collect FW register dump if required */
1994 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_CTRL
);
1995 if (!(val
& QLC_83XX_IDC_GRACEFULL_RESET
))
1996 qlcnic_dump_fw(adapter
);
1997 qlcnic_83xx_init_hw(adapter
);
1999 if (qlcnic_83xx_copy_bootloader(adapter
))
2001 /* Boot either flash image or firmware image from host file system */
2002 if (qlcnic_load_fw_file
) {
2003 if (qlcnic_83xx_load_fw_image_from_host(adapter
))
2006 QLC_SHARED_REG_WR32(adapter
, QLCNIC_FW_IMG_VALID
,
2007 QLC_83XX_BOOT_FROM_FLASH
);
2010 qlcnic_83xx_start_hw(adapter
);
2011 if (qlcnic_83xx_check_hw_status(adapter
))
2017 int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter
*adapter
)
2020 struct qlcnic_info nic_info
;
2021 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
2023 memset(&nic_info
, 0, sizeof(struct qlcnic_info
));
2024 err
= qlcnic_get_nic_info(adapter
, &nic_info
, ahw
->pci_func
);
2028 ahw
->physical_port
= (u8
) nic_info
.phys_port
;
2029 ahw
->switch_mode
= nic_info
.switch_mode
;
2030 ahw
->max_tx_ques
= nic_info
.max_tx_ques
;
2031 ahw
->max_rx_ques
= nic_info
.max_rx_ques
;
2032 ahw
->capabilities
= nic_info
.capabilities
;
2033 ahw
->max_mac_filters
= nic_info
.max_mac_filters
;
2034 ahw
->max_mtu
= nic_info
.max_mtu
;
2036 adapter
->max_tx_rings
= ahw
->max_tx_ques
;
2037 adapter
->max_sds_rings
= ahw
->max_rx_ques
;
2038 /* eSwitch capability indicates vNIC mode.
2039 * vNIC and SRIOV are mutually exclusive operational modes.
2040 * If SR-IOV capability is detected, SR-IOV physical function
2041 * will get initialized in default mode.
2042 * SR-IOV virtual function initialization follows a
2043 * different code path and opmode.
2044 * SRIOV mode has precedence over vNIC mode.
2046 if (test_bit(__QLCNIC_SRIOV_CAPABLE
, &adapter
->state
))
2047 return QLC_83XX_DEFAULT_OPMODE
;
2049 if (ahw
->capabilities
& QLC_83XX_ESWITCH_CAPABILITY
)
2050 return QLCNIC_VNIC_MODE
;
2052 return QLC_83XX_DEFAULT_OPMODE
;
2055 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter
*adapter
)
2057 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
2060 ret
= qlcnic_83xx_get_nic_configuration(adapter
);
2064 if (ret
== QLCNIC_VNIC_MODE
) {
2065 ahw
->nic_mode
= QLCNIC_VNIC_MODE
;
2067 if (qlcnic_83xx_config_vnic_opmode(adapter
))
2070 adapter
->max_sds_rings
= QLCNIC_MAX_VNIC_SDS_RINGS
;
2071 adapter
->max_tx_rings
= QLCNIC_MAX_VNIC_TX_RINGS
;
2072 } else if (ret
== QLC_83XX_DEFAULT_OPMODE
) {
2073 ahw
->nic_mode
= QLCNIC_DEFAULT_MODE
;
2074 adapter
->nic_ops
->init_driver
= qlcnic_83xx_init_default_driver
;
2075 ahw
->idc
.state_entry
= qlcnic_83xx_idc_ready_state_entry
;
2076 adapter
->max_sds_rings
= ahw
->max_rx_ques
;
2077 adapter
->max_tx_rings
= ahw
->max_tx_ques
;
2085 static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter
*adapter
)
2087 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
2089 if (ahw
->port_type
== QLCNIC_XGBE
) {
2090 adapter
->num_rxd
= DEFAULT_RCV_DESCRIPTORS_10G
;
2091 adapter
->max_rxd
= MAX_RCV_DESCRIPTORS_10G
;
2092 adapter
->num_jumbo_rxd
= MAX_JUMBO_RCV_DESCRIPTORS_10G
;
2093 adapter
->max_jumbo_rxd
= MAX_JUMBO_RCV_DESCRIPTORS_10G
;
2095 } else if (ahw
->port_type
== QLCNIC_GBE
) {
2096 adapter
->num_rxd
= DEFAULT_RCV_DESCRIPTORS_1G
;
2097 adapter
->num_jumbo_rxd
= MAX_JUMBO_RCV_DESCRIPTORS_1G
;
2098 adapter
->max_jumbo_rxd
= MAX_JUMBO_RCV_DESCRIPTORS_1G
;
2099 adapter
->max_rxd
= MAX_RCV_DESCRIPTORS_1G
;
2101 adapter
->num_txd
= MAX_CMD_DESCRIPTORS
;
2102 adapter
->max_rds_rings
= MAX_RDS_RINGS
;
2105 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter
*adapter
)
2109 qlcnic_83xx_get_minidump_template(adapter
);
2110 if (qlcnic_83xx_get_port_info(adapter
))
2113 qlcnic_83xx_config_buff_descriptors(adapter
);
2114 adapter
->ahw
->msix_supported
= !!qlcnic_use_msi_x
;
2115 adapter
->flags
|= QLCNIC_ADAPTER_INITIALIZED
;
2117 dev_info(&adapter
->pdev
->dev
, "HAL Version: %d\n",
2118 adapter
->ahw
->fw_hal_version
);
2123 #define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1))
2124 static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter
*adapter
)
2126 struct qlcnic_cmd_args cmd
;
2127 u32 presence_mask
, audit_mask
;
2130 presence_mask
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_DRV_PRESENCE
);
2131 audit_mask
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_DRV_AUDIT
);
2133 if (IS_QLC_83XX_USED(adapter
, presence_mask
, audit_mask
)) {
2134 status
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
2135 QLCNIC_CMD_STOP_NIC_FUNC
);
2139 cmd
.req
.arg
[1] = BIT_31
;
2140 status
= qlcnic_issue_cmd(adapter
, &cmd
);
2142 dev_err(&adapter
->pdev
->dev
,
2143 "Failed to clean up the function resources\n");
2144 qlcnic_free_mbx_args(&cmd
);
2148 static int qlcnic_83xx_get_fw_info(struct qlcnic_adapter
*adapter
)
2150 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
2151 struct pci_dev
*pdev
= adapter
->pdev
;
2152 struct qlc_83xx_fw_info
*fw_info
;
2155 ahw
->fw_info
= kzalloc(sizeof(*fw_info
), GFP_KERNEL
);
2156 if (!ahw
->fw_info
) {
2159 fw_info
= ahw
->fw_info
;
2160 switch (pdev
->device
) {
2161 case PCI_DEVICE_ID_QLOGIC_QLE834X
:
2162 strncpy(fw_info
->fw_file_name
, QLC_83XX_FW_FILE_NAME
,
2163 QLC_FW_FILE_NAME_LEN
);
2165 case PCI_DEVICE_ID_QLOGIC_QLE844X
:
2166 strncpy(fw_info
->fw_file_name
, QLC_84XX_FW_FILE_NAME
,
2167 QLC_FW_FILE_NAME_LEN
);
2170 dev_err(&pdev
->dev
, "%s: Invalid device id\n",
2180 static void qlcnic_83xx_init_rings(struct qlcnic_adapter
*adapter
)
2182 u8 rx_cnt
= QLCNIC_DEF_SDS_RINGS
;
2183 u8 tx_cnt
= QLCNIC_DEF_TX_RINGS
;
2185 adapter
->max_tx_rings
= QLCNIC_MAX_TX_RINGS
;
2186 adapter
->max_sds_rings
= QLCNIC_MAX_SDS_RINGS
;
2188 if (!adapter
->ahw
->msix_supported
) {
2189 rx_cnt
= QLCNIC_SINGLE_RING
;
2190 tx_cnt
= QLCNIC_SINGLE_RING
;
2193 /* compute and set drv sds rings */
2194 qlcnic_set_tx_ring_count(adapter
, tx_cnt
);
2195 qlcnic_set_sds_ring_count(adapter
, rx_cnt
);
2198 int qlcnic_83xx_init(struct qlcnic_adapter
*adapter
, int pci_using_dac
)
2200 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
2201 struct qlcnic_dcb
*dcb
;
2204 ahw
->msix_supported
= !!qlcnic_use_msi_x
;
2206 qlcnic_83xx_init_rings(adapter
);
2208 err
= qlcnic_83xx_init_mailbox_work(adapter
);
2212 if (qlcnic_sriov_vf_check(adapter
)) {
2213 err
= qlcnic_sriov_vf_init(adapter
, pci_using_dac
);
2220 if (qlcnic_83xx_read_flash_descriptor_table(adapter
) ||
2221 qlcnic_83xx_read_flash_mfg_id(adapter
)) {
2222 dev_err(&adapter
->pdev
->dev
, "Failed reading flash mfg id\n");
2223 err
= -ENOTRECOVERABLE
;
2227 err
= qlcnic_83xx_check_hw_status(adapter
);
2231 err
= qlcnic_83xx_get_fw_info(adapter
);
2235 err
= qlcnic_83xx_idc_init(adapter
);
2239 err
= qlcnic_setup_intr(adapter
);
2241 dev_err(&adapter
->pdev
->dev
, "Failed to setup interrupt\n");
2245 err
= qlcnic_83xx_setup_mbx_intr(adapter
);
2247 goto disable_mbx_intr
;
2249 qlcnic_83xx_clear_function_resources(adapter
);
2251 INIT_DELAYED_WORK(&adapter
->idc_aen_work
, qlcnic_83xx_idc_aen_work
);
2253 /* register for NIC IDC AEN Events */
2254 qlcnic_83xx_register_nic_idc_func(adapter
, 1);
2256 /* Configure default, SR-IOV or Virtual NIC mode of operation */
2257 err
= qlcnic_83xx_configure_opmode(adapter
);
2259 goto disable_mbx_intr
;
2262 /* Perform operating mode specific initialization */
2263 err
= adapter
->nic_ops
->init_driver(adapter
);
2265 goto disable_mbx_intr
;
2269 if (dcb
&& qlcnic_dcb_attach(dcb
))
2270 qlcnic_clear_dcb_ops(dcb
);
2272 /* Periodically monitor device status */
2273 qlcnic_83xx_idc_poll_dev_state(&adapter
->fw_work
.work
);
2277 qlcnic_83xx_free_mbx_intr(adapter
);
2280 qlcnic_teardown_intr(adapter
);
2283 qlcnic_83xx_detach_mailbox_work(adapter
);
2284 qlcnic_83xx_free_mailbox(ahw
->mailbox
);
2285 ahw
->mailbox
= NULL
;
2290 void qlcnic_83xx_aer_stop_poll_work(struct qlcnic_adapter
*adapter
)
2292 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
2293 struct qlc_83xx_idc
*idc
= &ahw
->idc
;
2295 clear_bit(QLC_83XX_MBX_READY
, &idc
->status
);
2296 cancel_delayed_work_sync(&adapter
->fw_work
);
2298 if (ahw
->nic_mode
== QLCNIC_VNIC_MODE
)
2299 qlcnic_83xx_disable_vnic_mode(adapter
, 1);
2301 qlcnic_83xx_idc_detach_driver(adapter
);
2302 qlcnic_83xx_register_nic_idc_func(adapter
, 0);
2304 cancel_delayed_work_sync(&adapter
->idc_aen_work
);
2307 int qlcnic_83xx_aer_reset(struct qlcnic_adapter
*adapter
)
2309 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
2310 struct qlc_83xx_idc
*idc
= &ahw
->idc
;
2314 /* Mark the previous IDC state as NEED_RESET so
2315 * that state_entry() will perform the reattachment
2316 * and bringup the device
2318 idc
->prev_state
= QLC_83XX_IDC_DEV_NEED_RESET
;
2319 owner
= qlcnic_83xx_idc_find_reset_owner_id(adapter
);
2320 if (ahw
->pci_func
== owner
) {
2321 ret
= qlcnic_83xx_restart_hw(adapter
);
2324 qlcnic_83xx_idc_clear_registers(adapter
, 0);
2327 ret
= idc
->state_entry(adapter
);
2331 void qlcnic_83xx_aer_start_poll_work(struct qlcnic_adapter
*adapter
)
2333 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
2334 struct qlc_83xx_idc
*idc
= &ahw
->idc
;
2337 idc
->prev_state
= QLC_83XX_IDC_DEV_READY
;
2338 owner
= qlcnic_83xx_idc_find_reset_owner_id(adapter
);
2339 if (ahw
->pci_func
== owner
)
2340 qlcnic_83xx_idc_enter_ready_state(adapter
, 0);
2342 qlcnic_schedule_work(adapter
, qlcnic_83xx_idc_poll_dev_state
, 0);