2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
5 * See LICENSE.qlcnic for copyright and licensing details.
8 #include <linux/types.h>
10 #include "qlcnic_sriov.h"
12 #include "qlcnic_83xx_hw.h"
14 #define QLC_BC_COMMAND 0
15 #define QLC_BC_RESPONSE 1
17 #define QLC_MBOX_RESP_TIMEOUT (10 * HZ)
18 #define QLC_MBOX_CH_FREE_TIMEOUT (10 * HZ)
21 #define QLC_BC_CFREE 1
23 #define QLC_BC_HDR_SZ 16
24 #define QLC_BC_PAYLOAD_SZ (1024 - QLC_BC_HDR_SZ)
26 #define QLC_DEFAULT_RCV_DESCRIPTORS_SRIOV_VF 2048
27 #define QLC_DEFAULT_JUMBO_RCV_DESCRIPTORS_SRIOV_VF 512
29 #define QLC_83XX_VF_RESET_FAIL_THRESH 8
30 #define QLC_BC_CMD_MAX_RETRY_CNT 5
32 static void qlcnic_sriov_handle_async_issue_cmd(struct work_struct
*work
);
33 static void qlcnic_sriov_vf_free_mac_list(struct qlcnic_adapter
*);
34 static int qlcnic_sriov_alloc_bc_mbx_args(struct qlcnic_cmd_args
*, u32
);
35 static void qlcnic_sriov_vf_poll_dev_state(struct work_struct
*);
36 static void qlcnic_sriov_vf_cancel_fw_work(struct qlcnic_adapter
*);
37 static void qlcnic_sriov_cleanup_transaction(struct qlcnic_bc_trans
*);
38 static int qlcnic_sriov_issue_cmd(struct qlcnic_adapter
*,
39 struct qlcnic_cmd_args
*);
40 static int qlcnic_sriov_channel_cfg_cmd(struct qlcnic_adapter
*, u8
);
41 static void qlcnic_sriov_process_bc_cmd(struct work_struct
*);
42 static int qlcnic_sriov_vf_shutdown(struct pci_dev
*);
43 static int qlcnic_sriov_vf_resume(struct qlcnic_adapter
*);
44 static int qlcnic_sriov_async_issue_cmd(struct qlcnic_adapter
*,
45 struct qlcnic_cmd_args
*);
47 static struct qlcnic_hardware_ops qlcnic_sriov_vf_hw_ops
= {
48 .read_crb
= qlcnic_83xx_read_crb
,
49 .write_crb
= qlcnic_83xx_write_crb
,
50 .read_reg
= qlcnic_83xx_rd_reg_indirect
,
51 .write_reg
= qlcnic_83xx_wrt_reg_indirect
,
52 .get_mac_address
= qlcnic_83xx_get_mac_address
,
53 .setup_intr
= qlcnic_83xx_setup_intr
,
54 .alloc_mbx_args
= qlcnic_83xx_alloc_mbx_args
,
55 .mbx_cmd
= qlcnic_sriov_issue_cmd
,
56 .get_func_no
= qlcnic_83xx_get_func_no
,
57 .api_lock
= qlcnic_83xx_cam_lock
,
58 .api_unlock
= qlcnic_83xx_cam_unlock
,
59 .process_lb_rcv_ring_diag
= qlcnic_83xx_process_rcv_ring_diag
,
60 .create_rx_ctx
= qlcnic_83xx_create_rx_ctx
,
61 .create_tx_ctx
= qlcnic_83xx_create_tx_ctx
,
62 .del_rx_ctx
= qlcnic_83xx_del_rx_ctx
,
63 .del_tx_ctx
= qlcnic_83xx_del_tx_ctx
,
64 .setup_link_event
= qlcnic_83xx_setup_link_event
,
65 .get_nic_info
= qlcnic_83xx_get_nic_info
,
66 .get_pci_info
= qlcnic_83xx_get_pci_info
,
67 .set_nic_info
= qlcnic_83xx_set_nic_info
,
68 .change_macvlan
= qlcnic_83xx_sre_macaddr_change
,
69 .napi_enable
= qlcnic_83xx_napi_enable
,
70 .napi_disable
= qlcnic_83xx_napi_disable
,
71 .config_intr_coal
= qlcnic_83xx_config_intr_coal
,
72 .config_rss
= qlcnic_83xx_config_rss
,
73 .config_hw_lro
= qlcnic_83xx_config_hw_lro
,
74 .config_promisc_mode
= qlcnic_83xx_nic_set_promisc
,
75 .change_l2_filter
= qlcnic_83xx_change_l2_filter
,
76 .get_board_info
= qlcnic_83xx_get_port_info
,
77 .free_mac_list
= qlcnic_sriov_vf_free_mac_list
,
78 .enable_sds_intr
= qlcnic_83xx_enable_sds_intr
,
79 .disable_sds_intr
= qlcnic_83xx_disable_sds_intr
,
82 static struct qlcnic_nic_template qlcnic_sriov_vf_ops
= {
83 .config_bridged_mode
= qlcnic_config_bridged_mode
,
84 .config_led
= qlcnic_config_led
,
85 .cancel_idc_work
= qlcnic_sriov_vf_cancel_fw_work
,
86 .napi_add
= qlcnic_83xx_napi_add
,
87 .napi_del
= qlcnic_83xx_napi_del
,
88 .shutdown
= qlcnic_sriov_vf_shutdown
,
89 .resume
= qlcnic_sriov_vf_resume
,
90 .config_ipaddr
= qlcnic_83xx_config_ipaddr
,
91 .clear_legacy_intr
= qlcnic_83xx_clear_legacy_intr
,
94 static const struct qlcnic_mailbox_metadata qlcnic_sriov_bc_mbx_tbl
[] = {
95 {QLCNIC_BC_CMD_CHANNEL_INIT
, 2, 2},
96 {QLCNIC_BC_CMD_CHANNEL_TERM
, 2, 2},
97 {QLCNIC_BC_CMD_GET_ACL
, 3, 14},
98 {QLCNIC_BC_CMD_CFG_GUEST_VLAN
, 2, 2},
101 static inline bool qlcnic_sriov_bc_msg_check(u32 val
)
103 return (val
& (1 << QLC_BC_MSG
)) ? true : false;
106 static inline bool qlcnic_sriov_channel_free_check(u32 val
)
108 return (val
& (1 << QLC_BC_CFREE
)) ? true : false;
111 static inline bool qlcnic_sriov_flr_check(u32 val
)
113 return (val
& (1 << QLC_BC_FLR
)) ? true : false;
116 static inline u8
qlcnic_sriov_target_func_id(u32 val
)
118 return (val
>> 4) & 0xff;
121 static int qlcnic_sriov_virtid_fn(struct qlcnic_adapter
*adapter
, int vf_id
)
123 struct pci_dev
*dev
= adapter
->pdev
;
127 if (qlcnic_sriov_vf_check(adapter
))
130 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_SRIOV
);
133 pci_read_config_word(dev
, pos
+ PCI_SRIOV_VF_OFFSET
, &offset
);
134 pci_read_config_word(dev
, pos
+ PCI_SRIOV_VF_STRIDE
, &stride
);
136 return (dev
->devfn
+ offset
+ stride
* vf_id
) & 0xff;
139 int qlcnic_sriov_init(struct qlcnic_adapter
*adapter
, int num_vfs
)
141 struct qlcnic_sriov
*sriov
;
142 struct qlcnic_back_channel
*bc
;
143 struct workqueue_struct
*wq
;
144 struct qlcnic_vport
*vp
;
145 struct qlcnic_vf_info
*vf
;
148 if (!qlcnic_sriov_enable_check(adapter
))
151 sriov
= kzalloc(sizeof(struct qlcnic_sriov
), GFP_KERNEL
);
155 adapter
->ahw
->sriov
= sriov
;
156 sriov
->num_vfs
= num_vfs
;
158 sriov
->vf_info
= kzalloc(sizeof(struct qlcnic_vf_info
) *
159 num_vfs
, GFP_KERNEL
);
160 if (!sriov
->vf_info
) {
162 goto qlcnic_free_sriov
;
165 wq
= create_singlethread_workqueue("bc-trans");
168 dev_err(&adapter
->pdev
->dev
,
169 "Cannot create bc-trans workqueue\n");
170 goto qlcnic_free_vf_info
;
173 bc
->bc_trans_wq
= wq
;
175 wq
= create_singlethread_workqueue("async");
178 dev_err(&adapter
->pdev
->dev
, "Cannot create async workqueue\n");
179 goto qlcnic_destroy_trans_wq
;
182 bc
->bc_async_wq
= wq
;
183 INIT_LIST_HEAD(&bc
->async_cmd_list
);
184 INIT_WORK(&bc
->vf_async_work
, qlcnic_sriov_handle_async_issue_cmd
);
185 spin_lock_init(&bc
->queue_lock
);
186 bc
->adapter
= adapter
;
188 for (i
= 0; i
< num_vfs
; i
++) {
189 vf
= &sriov
->vf_info
[i
];
190 vf
->adapter
= adapter
;
191 vf
->pci_func
= qlcnic_sriov_virtid_fn(adapter
, i
);
192 mutex_init(&vf
->send_cmd_lock
);
193 spin_lock_init(&vf
->vlan_list_lock
);
194 INIT_LIST_HEAD(&vf
->rcv_act
.wait_list
);
195 INIT_LIST_HEAD(&vf
->rcv_pend
.wait_list
);
196 spin_lock_init(&vf
->rcv_act
.lock
);
197 spin_lock_init(&vf
->rcv_pend
.lock
);
198 init_completion(&vf
->ch_free_cmpl
);
200 INIT_WORK(&vf
->trans_work
, qlcnic_sriov_process_bc_cmd
);
202 if (qlcnic_sriov_pf_check(adapter
)) {
203 vp
= kzalloc(sizeof(struct qlcnic_vport
), GFP_KERNEL
);
206 goto qlcnic_destroy_async_wq
;
208 sriov
->vf_info
[i
].vp
= vp
;
209 vp
->vlan_mode
= QLC_GUEST_VLAN_MODE
;
210 vp
->max_tx_bw
= MAX_BW
;
211 vp
->min_tx_bw
= MIN_BW
;
212 vp
->spoofchk
= false;
213 random_ether_addr(vp
->mac
);
214 dev_info(&adapter
->pdev
->dev
,
215 "MAC Address %pM is configured for VF %d\n",
222 qlcnic_destroy_async_wq
:
223 destroy_workqueue(bc
->bc_async_wq
);
225 qlcnic_destroy_trans_wq
:
226 destroy_workqueue(bc
->bc_trans_wq
);
229 kfree(sriov
->vf_info
);
232 kfree(adapter
->ahw
->sriov
);
236 void qlcnic_sriov_cleanup_list(struct qlcnic_trans_list
*t_list
)
238 struct qlcnic_bc_trans
*trans
;
239 struct qlcnic_cmd_args cmd
;
242 spin_lock_irqsave(&t_list
->lock
, flags
);
244 while (!list_empty(&t_list
->wait_list
)) {
245 trans
= list_first_entry(&t_list
->wait_list
,
246 struct qlcnic_bc_trans
, list
);
247 list_del(&trans
->list
);
249 cmd
.req
.arg
= (u32
*)trans
->req_pay
;
250 cmd
.rsp
.arg
= (u32
*)trans
->rsp_pay
;
251 qlcnic_free_mbx_args(&cmd
);
252 qlcnic_sriov_cleanup_transaction(trans
);
255 spin_unlock_irqrestore(&t_list
->lock
, flags
);
258 void __qlcnic_sriov_cleanup(struct qlcnic_adapter
*adapter
)
260 struct qlcnic_sriov
*sriov
= adapter
->ahw
->sriov
;
261 struct qlcnic_back_channel
*bc
= &sriov
->bc
;
262 struct qlcnic_vf_info
*vf
;
265 if (!qlcnic_sriov_enable_check(adapter
))
268 qlcnic_sriov_cleanup_async_list(bc
);
269 destroy_workqueue(bc
->bc_async_wq
);
271 for (i
= 0; i
< sriov
->num_vfs
; i
++) {
272 vf
= &sriov
->vf_info
[i
];
273 qlcnic_sriov_cleanup_list(&vf
->rcv_pend
);
274 cancel_work_sync(&vf
->trans_work
);
275 qlcnic_sriov_cleanup_list(&vf
->rcv_act
);
278 destroy_workqueue(bc
->bc_trans_wq
);
280 for (i
= 0; i
< sriov
->num_vfs
; i
++)
281 kfree(sriov
->vf_info
[i
].vp
);
283 kfree(sriov
->vf_info
);
284 kfree(adapter
->ahw
->sriov
);
287 static void qlcnic_sriov_vf_cleanup(struct qlcnic_adapter
*adapter
)
289 qlcnic_sriov_channel_cfg_cmd(adapter
, QLCNIC_BC_CMD_CHANNEL_TERM
);
290 qlcnic_sriov_cfg_bc_intr(adapter
, 0);
291 __qlcnic_sriov_cleanup(adapter
);
294 void qlcnic_sriov_cleanup(struct qlcnic_adapter
*adapter
)
296 if (!test_bit(__QLCNIC_SRIOV_ENABLE
, &adapter
->state
))
299 qlcnic_sriov_free_vlans(adapter
);
301 if (qlcnic_sriov_pf_check(adapter
))
302 qlcnic_sriov_pf_cleanup(adapter
);
304 if (qlcnic_sriov_vf_check(adapter
))
305 qlcnic_sriov_vf_cleanup(adapter
);
308 static int qlcnic_sriov_post_bc_msg(struct qlcnic_adapter
*adapter
, u32
*hdr
,
309 u32
*pay
, u8 pci_func
, u8 size
)
311 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
312 struct qlcnic_mailbox
*mbx
= ahw
->mailbox
;
313 struct qlcnic_cmd_args cmd
;
314 unsigned long timeout
;
317 memset(&cmd
, 0, sizeof(struct qlcnic_cmd_args
));
321 cmd
.func_num
= pci_func
;
322 cmd
.op_type
= QLC_83XX_MBX_POST_BC_OP
;
323 cmd
.cmd_op
= ((struct qlcnic_bc_hdr
*)hdr
)->cmd_op
;
325 err
= mbx
->ops
->enqueue_cmd(adapter
, &cmd
, &timeout
);
327 dev_err(&adapter
->pdev
->dev
,
328 "%s: Mailbox not available, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
329 __func__
, cmd
.cmd_op
, cmd
.type
, ahw
->pci_func
,
334 if (!wait_for_completion_timeout(&cmd
.completion
, timeout
)) {
335 dev_err(&adapter
->pdev
->dev
,
336 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
337 __func__
, cmd
.cmd_op
, cmd
.type
, ahw
->pci_func
,
339 flush_workqueue(mbx
->work_q
);
342 return cmd
.rsp_opcode
;
345 static void qlcnic_sriov_vf_cfg_buff_desc(struct qlcnic_adapter
*adapter
)
347 adapter
->num_rxd
= QLC_DEFAULT_RCV_DESCRIPTORS_SRIOV_VF
;
348 adapter
->max_rxd
= MAX_RCV_DESCRIPTORS_10G
;
349 adapter
->num_jumbo_rxd
= QLC_DEFAULT_JUMBO_RCV_DESCRIPTORS_SRIOV_VF
;
350 adapter
->max_jumbo_rxd
= MAX_JUMBO_RCV_DESCRIPTORS_10G
;
351 adapter
->num_txd
= MAX_CMD_DESCRIPTORS
;
352 adapter
->max_rds_rings
= MAX_RDS_RINGS
;
355 int qlcnic_sriov_get_vf_vport_info(struct qlcnic_adapter
*adapter
,
356 struct qlcnic_info
*npar_info
, u16 vport_id
)
358 struct device
*dev
= &adapter
->pdev
->dev
;
359 struct qlcnic_cmd_args cmd
;
363 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_GET_NIC_INFO
);
367 cmd
.req
.arg
[1] = vport_id
<< 16 | 0x1;
368 err
= qlcnic_issue_cmd(adapter
, &cmd
);
370 dev_err(&adapter
->pdev
->dev
,
371 "Failed to get vport info, err=%d\n", err
);
372 qlcnic_free_mbx_args(&cmd
);
376 status
= cmd
.rsp
.arg
[2] & 0xffff;
378 npar_info
->min_tx_bw
= MSW(cmd
.rsp
.arg
[2]);
380 npar_info
->max_tx_bw
= LSW(cmd
.rsp
.arg
[3]);
382 npar_info
->max_tx_ques
= MSW(cmd
.rsp
.arg
[3]);
384 npar_info
->max_tx_mac_filters
= LSW(cmd
.rsp
.arg
[4]);
386 npar_info
->max_rx_mcast_mac_filters
= MSW(cmd
.rsp
.arg
[4]);
388 npar_info
->max_rx_ucast_mac_filters
= LSW(cmd
.rsp
.arg
[5]);
390 npar_info
->max_rx_ip_addr
= MSW(cmd
.rsp
.arg
[5]);
392 npar_info
->max_rx_lro_flow
= LSW(cmd
.rsp
.arg
[6]);
394 npar_info
->max_rx_status_rings
= MSW(cmd
.rsp
.arg
[6]);
396 npar_info
->max_rx_buf_rings
= LSW(cmd
.rsp
.arg
[7]);
398 npar_info
->max_rx_ques
= MSW(cmd
.rsp
.arg
[7]);
399 npar_info
->max_tx_vlan_keys
= LSW(cmd
.rsp
.arg
[8]);
400 npar_info
->max_local_ipv6_addrs
= MSW(cmd
.rsp
.arg
[8]);
401 npar_info
->max_remote_ipv6_addrs
= LSW(cmd
.rsp
.arg
[9]);
403 dev_info(dev
, "\n\tmin_tx_bw: %d, max_tx_bw: %d max_tx_ques: %d,\n"
404 "\tmax_tx_mac_filters: %d max_rx_mcast_mac_filters: %d,\n"
405 "\tmax_rx_ucast_mac_filters: 0x%x, max_rx_ip_addr: %d,\n"
406 "\tmax_rx_lro_flow: %d max_rx_status_rings: %d,\n"
407 "\tmax_rx_buf_rings: %d, max_rx_ques: %d, max_tx_vlan_keys %d\n"
408 "\tlocal_ipv6_addr: %d, remote_ipv6_addr: %d\n",
409 npar_info
->min_tx_bw
, npar_info
->max_tx_bw
,
410 npar_info
->max_tx_ques
, npar_info
->max_tx_mac_filters
,
411 npar_info
->max_rx_mcast_mac_filters
,
412 npar_info
->max_rx_ucast_mac_filters
, npar_info
->max_rx_ip_addr
,
413 npar_info
->max_rx_lro_flow
, npar_info
->max_rx_status_rings
,
414 npar_info
->max_rx_buf_rings
, npar_info
->max_rx_ques
,
415 npar_info
->max_tx_vlan_keys
, npar_info
->max_local_ipv6_addrs
,
416 npar_info
->max_remote_ipv6_addrs
);
418 qlcnic_free_mbx_args(&cmd
);
422 static int qlcnic_sriov_set_pvid_mode(struct qlcnic_adapter
*adapter
,
423 struct qlcnic_cmd_args
*cmd
)
425 adapter
->rx_pvid
= MSW(cmd
->rsp
.arg
[1]) & 0xffff;
426 adapter
->flags
&= ~QLCNIC_TAGGING_ENABLED
;
430 static int qlcnic_sriov_set_guest_vlan_mode(struct qlcnic_adapter
*adapter
,
431 struct qlcnic_cmd_args
*cmd
)
433 struct qlcnic_sriov
*sriov
= adapter
->ahw
->sriov
;
437 if (sriov
->allowed_vlans
)
440 sriov
->any_vlan
= cmd
->rsp
.arg
[2] & 0xf;
441 sriov
->num_allowed_vlans
= cmd
->rsp
.arg
[2] >> 16;
442 dev_info(&adapter
->pdev
->dev
, "Number of allowed Guest VLANs = %d\n",
443 sriov
->num_allowed_vlans
);
445 qlcnic_sriov_alloc_vlans(adapter
);
447 if (!sriov
->any_vlan
)
450 num_vlans
= sriov
->num_allowed_vlans
;
451 sriov
->allowed_vlans
= kzalloc(sizeof(u16
) * num_vlans
, GFP_KERNEL
);
452 if (!sriov
->allowed_vlans
)
455 vlans
= (u16
*)&cmd
->rsp
.arg
[3];
456 for (i
= 0; i
< num_vlans
; i
++)
457 sriov
->allowed_vlans
[i
] = vlans
[i
];
462 static int qlcnic_sriov_get_vf_acl(struct qlcnic_adapter
*adapter
)
464 struct qlcnic_sriov
*sriov
= adapter
->ahw
->sriov
;
465 struct qlcnic_cmd_args cmd
;
468 memset(&cmd
, 0, sizeof(cmd
));
469 ret
= qlcnic_sriov_alloc_bc_mbx_args(&cmd
, QLCNIC_BC_CMD_GET_ACL
);
473 ret
= qlcnic_issue_cmd(adapter
, &cmd
);
475 dev_err(&adapter
->pdev
->dev
, "Failed to get ACL, err=%d\n",
478 sriov
->vlan_mode
= cmd
.rsp
.arg
[1] & 0x3;
479 switch (sriov
->vlan_mode
) {
480 case QLC_GUEST_VLAN_MODE
:
481 ret
= qlcnic_sriov_set_guest_vlan_mode(adapter
, &cmd
);
484 ret
= qlcnic_sriov_set_pvid_mode(adapter
, &cmd
);
489 qlcnic_free_mbx_args(&cmd
);
493 static int qlcnic_sriov_vf_init_driver(struct qlcnic_adapter
*adapter
)
495 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
496 struct qlcnic_info nic_info
;
499 err
= qlcnic_sriov_get_vf_vport_info(adapter
, &nic_info
, 0);
503 ahw
->max_mc_count
= nic_info
.max_rx_mcast_mac_filters
;
505 err
= qlcnic_get_nic_info(adapter
, &nic_info
, ahw
->pci_func
);
509 if (qlcnic_83xx_get_port_info(adapter
))
512 qlcnic_sriov_vf_cfg_buff_desc(adapter
);
513 adapter
->flags
|= QLCNIC_ADAPTER_INITIALIZED
;
514 dev_info(&adapter
->pdev
->dev
, "HAL Version: %d\n",
515 adapter
->ahw
->fw_hal_version
);
517 ahw
->physical_port
= (u8
) nic_info
.phys_port
;
518 ahw
->switch_mode
= nic_info
.switch_mode
;
519 ahw
->max_mtu
= nic_info
.max_mtu
;
520 ahw
->op_mode
= nic_info
.op_mode
;
521 ahw
->capabilities
= nic_info
.capabilities
;
525 static int qlcnic_sriov_setup_vf(struct qlcnic_adapter
*adapter
,
530 adapter
->flags
|= QLCNIC_VLAN_FILTERING
;
531 adapter
->ahw
->total_nic_func
= 1;
532 INIT_LIST_HEAD(&adapter
->vf_mc_list
);
533 if (!qlcnic_use_msi_x
&& !!qlcnic_use_msi
)
534 dev_warn(&adapter
->pdev
->dev
,
535 "Device does not support MSI interrupts\n");
537 /* compute and set default and max tx/sds rings */
538 qlcnic_set_tx_ring_count(adapter
, QLCNIC_SINGLE_RING
);
539 qlcnic_set_sds_ring_count(adapter
, QLCNIC_SINGLE_RING
);
541 err
= qlcnic_setup_intr(adapter
);
543 dev_err(&adapter
->pdev
->dev
, "Failed to setup interrupt\n");
544 goto err_out_disable_msi
;
547 err
= qlcnic_83xx_setup_mbx_intr(adapter
);
549 goto err_out_disable_msi
;
551 err
= qlcnic_sriov_init(adapter
, 1);
553 goto err_out_disable_mbx_intr
;
555 err
= qlcnic_sriov_cfg_bc_intr(adapter
, 1);
557 goto err_out_cleanup_sriov
;
559 err
= qlcnic_sriov_channel_cfg_cmd(adapter
, QLCNIC_BC_CMD_CHANNEL_INIT
);
561 goto err_out_disable_bc_intr
;
563 err
= qlcnic_sriov_vf_init_driver(adapter
);
565 goto err_out_send_channel_term
;
567 err
= qlcnic_sriov_get_vf_acl(adapter
);
569 goto err_out_send_channel_term
;
571 err
= qlcnic_setup_netdev(adapter
, adapter
->netdev
, pci_using_dac
);
573 goto err_out_send_channel_term
;
575 pci_set_drvdata(adapter
->pdev
, adapter
);
576 dev_info(&adapter
->pdev
->dev
, "%s: XGbE port initialized\n",
577 adapter
->netdev
->name
);
579 qlcnic_schedule_work(adapter
, qlcnic_sriov_vf_poll_dev_state
,
580 adapter
->ahw
->idc
.delay
);
583 err_out_send_channel_term
:
584 qlcnic_sriov_channel_cfg_cmd(adapter
, QLCNIC_BC_CMD_CHANNEL_TERM
);
586 err_out_disable_bc_intr
:
587 qlcnic_sriov_cfg_bc_intr(adapter
, 0);
589 err_out_cleanup_sriov
:
590 __qlcnic_sriov_cleanup(adapter
);
592 err_out_disable_mbx_intr
:
593 qlcnic_83xx_free_mbx_intr(adapter
);
596 qlcnic_teardown_intr(adapter
);
600 static int qlcnic_sriov_check_dev_ready(struct qlcnic_adapter
*adapter
)
606 if (++adapter
->fw_fail_cnt
> QLC_BC_CMD_MAX_RETRY_CNT
)
608 state
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_DEV_STATE
);
609 } while (state
!= QLC_83XX_IDC_DEV_READY
);
614 int qlcnic_sriov_vf_init(struct qlcnic_adapter
*adapter
, int pci_using_dac
)
616 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
619 set_bit(QLC_83XX_MODULE_LOADED
, &ahw
->idc
.status
);
620 ahw
->idc
.delay
= QLC_83XX_IDC_FW_POLL_DELAY
;
621 ahw
->reset_context
= 0;
622 adapter
->fw_fail_cnt
= 0;
623 ahw
->msix_supported
= 1;
624 adapter
->need_fw_reset
= 0;
625 adapter
->flags
|= QLCNIC_TX_INTR_SHARED
;
627 err
= qlcnic_sriov_check_dev_ready(adapter
);
631 err
= qlcnic_sriov_setup_vf(adapter
, pci_using_dac
);
635 if (qlcnic_read_mac_addr(adapter
))
636 dev_warn(&adapter
->pdev
->dev
, "failed to read mac addr\n");
638 INIT_DELAYED_WORK(&adapter
->idc_aen_work
, qlcnic_83xx_idc_aen_work
);
640 clear_bit(__QLCNIC_RESETTING
, &adapter
->state
);
644 void qlcnic_sriov_vf_set_ops(struct qlcnic_adapter
*adapter
)
646 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
648 ahw
->op_mode
= QLCNIC_SRIOV_VF_FUNC
;
649 dev_info(&adapter
->pdev
->dev
,
650 "HAL Version: %d Non Privileged SRIOV function\n",
651 ahw
->fw_hal_version
);
652 adapter
->nic_ops
= &qlcnic_sriov_vf_ops
;
653 set_bit(__QLCNIC_SRIOV_ENABLE
, &adapter
->state
);
657 void qlcnic_sriov_vf_register_map(struct qlcnic_hardware_context
*ahw
)
659 ahw
->hw_ops
= &qlcnic_sriov_vf_hw_ops
;
660 ahw
->reg_tbl
= (u32
*)qlcnic_83xx_reg_tbl
;
661 ahw
->ext_reg_tbl
= (u32
*)qlcnic_83xx_ext_reg_tbl
;
664 static u32
qlcnic_sriov_get_bc_paysize(u32 real_pay_size
, u8 curr_frag
)
668 pay_size
= real_pay_size
/ ((curr_frag
+ 1) * QLC_BC_PAYLOAD_SZ
);
671 pay_size
= QLC_BC_PAYLOAD_SZ
;
673 pay_size
= real_pay_size
% QLC_BC_PAYLOAD_SZ
;
678 int qlcnic_sriov_func_to_index(struct qlcnic_adapter
*adapter
, u8 pci_func
)
680 struct qlcnic_vf_info
*vf_info
= adapter
->ahw
->sriov
->vf_info
;
683 if (qlcnic_sriov_vf_check(adapter
))
686 for (i
= 0; i
< adapter
->ahw
->sriov
->num_vfs
; i
++) {
687 if (vf_info
[i
].pci_func
== pci_func
)
694 static inline int qlcnic_sriov_alloc_bc_trans(struct qlcnic_bc_trans
**trans
)
696 *trans
= kzalloc(sizeof(struct qlcnic_bc_trans
), GFP_ATOMIC
);
700 init_completion(&(*trans
)->resp_cmpl
);
704 static inline int qlcnic_sriov_alloc_bc_msg(struct qlcnic_bc_hdr
**hdr
,
707 *hdr
= kzalloc(sizeof(struct qlcnic_bc_hdr
) * size
, GFP_ATOMIC
);
714 static int qlcnic_sriov_alloc_bc_mbx_args(struct qlcnic_cmd_args
*mbx
, u32 type
)
716 const struct qlcnic_mailbox_metadata
*mbx_tbl
;
719 mbx_tbl
= qlcnic_sriov_bc_mbx_tbl
;
720 size
= ARRAY_SIZE(qlcnic_sriov_bc_mbx_tbl
);
722 for (i
= 0; i
< size
; i
++) {
723 if (type
== mbx_tbl
[i
].cmd
) {
724 mbx
->op_type
= QLC_BC_CMD
;
725 mbx
->req
.num
= mbx_tbl
[i
].in_args
;
726 mbx
->rsp
.num
= mbx_tbl
[i
].out_args
;
727 mbx
->req
.arg
= kcalloc(mbx
->req
.num
, sizeof(u32
),
731 mbx
->rsp
.arg
= kcalloc(mbx
->rsp
.num
, sizeof(u32
),
738 mbx
->req
.arg
[0] = (type
| (mbx
->req
.num
<< 16) |
740 mbx
->rsp
.arg
[0] = (type
& 0xffff) | mbx
->rsp
.num
<< 16;
747 static int qlcnic_sriov_prepare_bc_hdr(struct qlcnic_bc_trans
*trans
,
748 struct qlcnic_cmd_args
*cmd
,
749 u16 seq
, u8 msg_type
)
751 struct qlcnic_bc_hdr
*hdr
;
753 u32 num_regs
, bc_pay_sz
;
755 u8 cmd_op
, num_frags
, t_num_frags
;
757 bc_pay_sz
= QLC_BC_PAYLOAD_SZ
;
758 if (msg_type
== QLC_BC_COMMAND
) {
759 trans
->req_pay
= (struct qlcnic_bc_payload
*)cmd
->req
.arg
;
760 trans
->rsp_pay
= (struct qlcnic_bc_payload
*)cmd
->rsp
.arg
;
761 num_regs
= cmd
->req
.num
;
762 trans
->req_pay_size
= (num_regs
* 4);
763 num_regs
= cmd
->rsp
.num
;
764 trans
->rsp_pay_size
= (num_regs
* 4);
765 cmd_op
= cmd
->req
.arg
[0] & 0xff;
766 remainder
= (trans
->req_pay_size
) % (bc_pay_sz
);
767 num_frags
= (trans
->req_pay_size
) / (bc_pay_sz
);
770 t_num_frags
= num_frags
;
771 if (qlcnic_sriov_alloc_bc_msg(&trans
->req_hdr
, num_frags
))
773 remainder
= (trans
->rsp_pay_size
) % (bc_pay_sz
);
774 num_frags
= (trans
->rsp_pay_size
) / (bc_pay_sz
);
777 if (qlcnic_sriov_alloc_bc_msg(&trans
->rsp_hdr
, num_frags
))
779 num_frags
= t_num_frags
;
780 hdr
= trans
->req_hdr
;
782 cmd
->req
.arg
= (u32
*)trans
->req_pay
;
783 cmd
->rsp
.arg
= (u32
*)trans
->rsp_pay
;
784 cmd_op
= cmd
->req
.arg
[0] & 0xff;
785 cmd
->cmd_op
= cmd_op
;
786 remainder
= (trans
->rsp_pay_size
) % (bc_pay_sz
);
787 num_frags
= (trans
->rsp_pay_size
) / (bc_pay_sz
);
790 cmd
->req
.num
= trans
->req_pay_size
/ 4;
791 cmd
->rsp
.num
= trans
->rsp_pay_size
/ 4;
792 hdr
= trans
->rsp_hdr
;
793 cmd
->op_type
= trans
->req_hdr
->op_type
;
796 trans
->trans_id
= seq
;
797 trans
->cmd_id
= cmd_op
;
798 for (i
= 0; i
< num_frags
; i
++) {
800 hdr
[i
].msg_type
= msg_type
;
801 hdr
[i
].op_type
= cmd
->op_type
;
803 hdr
[i
].num_frags
= num_frags
;
804 hdr
[i
].frag_num
= i
+ 1;
805 hdr
[i
].cmd_op
= cmd_op
;
811 static void qlcnic_sriov_cleanup_transaction(struct qlcnic_bc_trans
*trans
)
815 kfree(trans
->req_hdr
);
816 kfree(trans
->rsp_hdr
);
820 static int qlcnic_sriov_clear_trans(struct qlcnic_vf_info
*vf
,
821 struct qlcnic_bc_trans
*trans
, u8 type
)
823 struct qlcnic_trans_list
*t_list
;
827 if (type
== QLC_BC_RESPONSE
) {
828 t_list
= &vf
->rcv_act
;
829 spin_lock_irqsave(&t_list
->lock
, flags
);
831 list_del(&trans
->list
);
832 if (t_list
->count
> 0)
834 spin_unlock_irqrestore(&t_list
->lock
, flags
);
836 if (type
== QLC_BC_COMMAND
) {
837 while (test_and_set_bit(QLC_BC_VF_SEND
, &vf
->state
))
840 clear_bit(QLC_BC_VF_SEND
, &vf
->state
);
845 static void qlcnic_sriov_schedule_bc_cmd(struct qlcnic_sriov
*sriov
,
846 struct qlcnic_vf_info
*vf
,
849 if (test_bit(QLC_BC_VF_FLR
, &vf
->state
) ||
850 vf
->adapter
->need_fw_reset
)
853 queue_work(sriov
->bc
.bc_trans_wq
, &vf
->trans_work
);
856 static inline void qlcnic_sriov_wait_for_resp(struct qlcnic_bc_trans
*trans
)
858 struct completion
*cmpl
= &trans
->resp_cmpl
;
860 if (wait_for_completion_timeout(cmpl
, QLC_MBOX_RESP_TIMEOUT
))
861 trans
->trans_state
= QLC_END
;
863 trans
->trans_state
= QLC_ABORT
;
868 static void qlcnic_sriov_handle_multi_frags(struct qlcnic_bc_trans
*trans
,
871 if (type
== QLC_BC_RESPONSE
) {
872 trans
->curr_rsp_frag
++;
873 if (trans
->curr_rsp_frag
< trans
->rsp_hdr
->num_frags
)
874 trans
->trans_state
= QLC_INIT
;
876 trans
->trans_state
= QLC_END
;
878 trans
->curr_req_frag
++;
879 if (trans
->curr_req_frag
< trans
->req_hdr
->num_frags
)
880 trans
->trans_state
= QLC_INIT
;
882 trans
->trans_state
= QLC_WAIT_FOR_RESP
;
886 static void qlcnic_sriov_wait_for_channel_free(struct qlcnic_bc_trans
*trans
,
889 struct qlcnic_vf_info
*vf
= trans
->vf
;
890 struct completion
*cmpl
= &vf
->ch_free_cmpl
;
892 if (!wait_for_completion_timeout(cmpl
, QLC_MBOX_CH_FREE_TIMEOUT
)) {
893 trans
->trans_state
= QLC_ABORT
;
897 clear_bit(QLC_BC_VF_CHANNEL
, &vf
->state
);
898 qlcnic_sriov_handle_multi_frags(trans
, type
);
901 static void qlcnic_sriov_pull_bc_msg(struct qlcnic_adapter
*adapter
,
902 u32
*hdr
, u32
*pay
, u32 size
)
904 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
906 u8 i
, max
= 2, hdr_size
, j
;
908 hdr_size
= (sizeof(struct qlcnic_bc_hdr
) / sizeof(u32
));
909 max
= (size
/ sizeof(u32
)) + hdr_size
;
911 fw_mbx
= readl(QLCNIC_MBX_FW(ahw
, 0));
912 for (i
= 2, j
= 0; j
< hdr_size
; i
++, j
++)
913 *(hdr
++) = readl(QLCNIC_MBX_FW(ahw
, i
));
914 for (; j
< max
; i
++, j
++)
915 *(pay
++) = readl(QLCNIC_MBX_FW(ahw
, i
));
918 static int __qlcnic_sriov_issue_bc_post(struct qlcnic_vf_info
*vf
)
924 if (!test_and_set_bit(QLC_BC_VF_CHANNEL
, &vf
->state
)) {
934 static int qlcnic_sriov_issue_bc_post(struct qlcnic_bc_trans
*trans
, u8 type
)
936 struct qlcnic_vf_info
*vf
= trans
->vf
;
937 u32 pay_size
, hdr_size
;
940 u8 pci_func
= trans
->func_id
;
942 if (__qlcnic_sriov_issue_bc_post(vf
))
945 if (type
== QLC_BC_COMMAND
) {
946 hdr
= (u32
*)(trans
->req_hdr
+ trans
->curr_req_frag
);
947 pay
= (u32
*)(trans
->req_pay
+ trans
->curr_req_frag
);
948 hdr_size
= (sizeof(struct qlcnic_bc_hdr
) / sizeof(u32
));
949 pay_size
= qlcnic_sriov_get_bc_paysize(trans
->req_pay_size
,
950 trans
->curr_req_frag
);
951 pay_size
= (pay_size
/ sizeof(u32
));
953 hdr
= (u32
*)(trans
->rsp_hdr
+ trans
->curr_rsp_frag
);
954 pay
= (u32
*)(trans
->rsp_pay
+ trans
->curr_rsp_frag
);
955 hdr_size
= (sizeof(struct qlcnic_bc_hdr
) / sizeof(u32
));
956 pay_size
= qlcnic_sriov_get_bc_paysize(trans
->rsp_pay_size
,
957 trans
->curr_rsp_frag
);
958 pay_size
= (pay_size
/ sizeof(u32
));
961 ret
= qlcnic_sriov_post_bc_msg(vf
->adapter
, hdr
, pay
,
966 static int __qlcnic_sriov_send_bc_msg(struct qlcnic_bc_trans
*trans
,
967 struct qlcnic_vf_info
*vf
, u8 type
)
973 if (test_bit(QLC_BC_VF_FLR
, &vf
->state
) ||
974 vf
->adapter
->need_fw_reset
)
975 trans
->trans_state
= QLC_ABORT
;
977 switch (trans
->trans_state
) {
979 trans
->trans_state
= QLC_WAIT_FOR_CHANNEL_FREE
;
980 if (qlcnic_sriov_issue_bc_post(trans
, type
))
981 trans
->trans_state
= QLC_ABORT
;
983 case QLC_WAIT_FOR_CHANNEL_FREE
:
984 qlcnic_sriov_wait_for_channel_free(trans
, type
);
986 case QLC_WAIT_FOR_RESP
:
987 qlcnic_sriov_wait_for_resp(trans
);
996 clear_bit(QLC_BC_VF_CHANNEL
, &vf
->state
);
1006 static int qlcnic_sriov_send_bc_cmd(struct qlcnic_adapter
*adapter
,
1007 struct qlcnic_bc_trans
*trans
, int pci_func
)
1009 struct qlcnic_vf_info
*vf
;
1010 int err
, index
= qlcnic_sriov_func_to_index(adapter
, pci_func
);
1015 vf
= &adapter
->ahw
->sriov
->vf_info
[index
];
1017 trans
->func_id
= pci_func
;
1019 if (!test_bit(QLC_BC_VF_STATE
, &vf
->state
)) {
1020 if (qlcnic_sriov_pf_check(adapter
))
1022 if (qlcnic_sriov_vf_check(adapter
) &&
1023 trans
->cmd_id
!= QLCNIC_BC_CMD_CHANNEL_INIT
)
1027 mutex_lock(&vf
->send_cmd_lock
);
1028 vf
->send_cmd
= trans
;
1029 err
= __qlcnic_sriov_send_bc_msg(trans
, vf
, QLC_BC_COMMAND
);
1030 qlcnic_sriov_clear_trans(vf
, trans
, QLC_BC_COMMAND
);
1031 mutex_unlock(&vf
->send_cmd_lock
);
1035 static void __qlcnic_sriov_process_bc_cmd(struct qlcnic_adapter
*adapter
,
1036 struct qlcnic_bc_trans
*trans
,
1037 struct qlcnic_cmd_args
*cmd
)
1039 #ifdef CONFIG_QLCNIC_SRIOV
1040 if (qlcnic_sriov_pf_check(adapter
)) {
1041 qlcnic_sriov_pf_process_bc_cmd(adapter
, trans
, cmd
);
1045 cmd
->rsp
.arg
[0] |= (0x9 << 25);
1049 static void qlcnic_sriov_process_bc_cmd(struct work_struct
*work
)
1051 struct qlcnic_vf_info
*vf
= container_of(work
, struct qlcnic_vf_info
,
1053 struct qlcnic_bc_trans
*trans
= NULL
;
1054 struct qlcnic_adapter
*adapter
= vf
->adapter
;
1055 struct qlcnic_cmd_args cmd
;
1058 if (adapter
->need_fw_reset
)
1061 if (test_bit(QLC_BC_VF_FLR
, &vf
->state
))
1064 memset(&cmd
, 0, sizeof(struct qlcnic_cmd_args
));
1065 trans
= list_first_entry(&vf
->rcv_act
.wait_list
,
1066 struct qlcnic_bc_trans
, list
);
1067 adapter
= vf
->adapter
;
1069 if (qlcnic_sriov_prepare_bc_hdr(trans
, &cmd
, trans
->req_hdr
->seq_id
,
1073 __qlcnic_sriov_process_bc_cmd(adapter
, trans
, &cmd
);
1074 trans
->trans_state
= QLC_INIT
;
1075 __qlcnic_sriov_send_bc_msg(trans
, vf
, QLC_BC_RESPONSE
);
1078 qlcnic_free_mbx_args(&cmd
);
1079 req
= qlcnic_sriov_clear_trans(vf
, trans
, QLC_BC_RESPONSE
);
1080 qlcnic_sriov_cleanup_transaction(trans
);
1082 qlcnic_sriov_schedule_bc_cmd(adapter
->ahw
->sriov
, vf
,
1083 qlcnic_sriov_process_bc_cmd
);
1086 static void qlcnic_sriov_handle_bc_resp(struct qlcnic_bc_hdr
*hdr
,
1087 struct qlcnic_vf_info
*vf
)
1089 struct qlcnic_bc_trans
*trans
;
1092 if (test_and_set_bit(QLC_BC_VF_SEND
, &vf
->state
))
1095 trans
= vf
->send_cmd
;
1100 if (trans
->trans_id
!= hdr
->seq_id
)
1103 pay_size
= qlcnic_sriov_get_bc_paysize(trans
->rsp_pay_size
,
1104 trans
->curr_rsp_frag
);
1105 qlcnic_sriov_pull_bc_msg(vf
->adapter
,
1106 (u32
*)(trans
->rsp_hdr
+ trans
->curr_rsp_frag
),
1107 (u32
*)(trans
->rsp_pay
+ trans
->curr_rsp_frag
),
1109 if (++trans
->curr_rsp_frag
< trans
->rsp_hdr
->num_frags
)
1112 complete(&trans
->resp_cmpl
);
1115 clear_bit(QLC_BC_VF_SEND
, &vf
->state
);
1118 int __qlcnic_sriov_add_act_list(struct qlcnic_sriov
*sriov
,
1119 struct qlcnic_vf_info
*vf
,
1120 struct qlcnic_bc_trans
*trans
)
1122 struct qlcnic_trans_list
*t_list
= &vf
->rcv_act
;
1125 list_add_tail(&trans
->list
, &t_list
->wait_list
);
1126 if (t_list
->count
== 1)
1127 qlcnic_sriov_schedule_bc_cmd(sriov
, vf
,
1128 qlcnic_sriov_process_bc_cmd
);
1132 static int qlcnic_sriov_add_act_list(struct qlcnic_sriov
*sriov
,
1133 struct qlcnic_vf_info
*vf
,
1134 struct qlcnic_bc_trans
*trans
)
1136 struct qlcnic_trans_list
*t_list
= &vf
->rcv_act
;
1138 spin_lock(&t_list
->lock
);
1140 __qlcnic_sriov_add_act_list(sriov
, vf
, trans
);
1142 spin_unlock(&t_list
->lock
);
1146 static void qlcnic_sriov_handle_pending_trans(struct qlcnic_sriov
*sriov
,
1147 struct qlcnic_vf_info
*vf
,
1148 struct qlcnic_bc_hdr
*hdr
)
1150 struct qlcnic_bc_trans
*trans
= NULL
;
1151 struct list_head
*node
;
1152 u32 pay_size
, curr_frag
;
1153 u8 found
= 0, active
= 0;
1155 spin_lock(&vf
->rcv_pend
.lock
);
1156 if (vf
->rcv_pend
.count
> 0) {
1157 list_for_each(node
, &vf
->rcv_pend
.wait_list
) {
1158 trans
= list_entry(node
, struct qlcnic_bc_trans
, list
);
1159 if (trans
->trans_id
== hdr
->seq_id
) {
1167 curr_frag
= trans
->curr_req_frag
;
1168 pay_size
= qlcnic_sriov_get_bc_paysize(trans
->req_pay_size
,
1170 qlcnic_sriov_pull_bc_msg(vf
->adapter
,
1171 (u32
*)(trans
->req_hdr
+ curr_frag
),
1172 (u32
*)(trans
->req_pay
+ curr_frag
),
1174 trans
->curr_req_frag
++;
1175 if (trans
->curr_req_frag
>= hdr
->num_frags
) {
1176 vf
->rcv_pend
.count
--;
1177 list_del(&trans
->list
);
1181 spin_unlock(&vf
->rcv_pend
.lock
);
1184 if (qlcnic_sriov_add_act_list(sriov
, vf
, trans
))
1185 qlcnic_sriov_cleanup_transaction(trans
);
1190 static void qlcnic_sriov_handle_bc_cmd(struct qlcnic_sriov
*sriov
,
1191 struct qlcnic_bc_hdr
*hdr
,
1192 struct qlcnic_vf_info
*vf
)
1194 struct qlcnic_bc_trans
*trans
;
1195 struct qlcnic_adapter
*adapter
= vf
->adapter
;
1196 struct qlcnic_cmd_args cmd
;
1201 if (adapter
->need_fw_reset
)
1204 if (!test_bit(QLC_BC_VF_STATE
, &vf
->state
) &&
1205 hdr
->op_type
!= QLC_BC_CMD
&&
1206 hdr
->cmd_op
!= QLCNIC_BC_CMD_CHANNEL_INIT
)
1209 if (hdr
->frag_num
> 1) {
1210 qlcnic_sriov_handle_pending_trans(sriov
, vf
, hdr
);
1214 memset(&cmd
, 0, sizeof(struct qlcnic_cmd_args
));
1215 cmd_op
= hdr
->cmd_op
;
1216 if (qlcnic_sriov_alloc_bc_trans(&trans
))
1219 if (hdr
->op_type
== QLC_BC_CMD
)
1220 err
= qlcnic_sriov_alloc_bc_mbx_args(&cmd
, cmd_op
);
1222 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, cmd_op
);
1225 qlcnic_sriov_cleanup_transaction(trans
);
1229 cmd
.op_type
= hdr
->op_type
;
1230 if (qlcnic_sriov_prepare_bc_hdr(trans
, &cmd
, hdr
->seq_id
,
1232 qlcnic_free_mbx_args(&cmd
);
1233 qlcnic_sriov_cleanup_transaction(trans
);
1237 pay_size
= qlcnic_sriov_get_bc_paysize(trans
->req_pay_size
,
1238 trans
->curr_req_frag
);
1239 qlcnic_sriov_pull_bc_msg(vf
->adapter
,
1240 (u32
*)(trans
->req_hdr
+ trans
->curr_req_frag
),
1241 (u32
*)(trans
->req_pay
+ trans
->curr_req_frag
),
1243 trans
->func_id
= vf
->pci_func
;
1245 trans
->trans_id
= hdr
->seq_id
;
1246 trans
->curr_req_frag
++;
1248 if (qlcnic_sriov_soft_flr_check(adapter
, trans
, vf
))
1251 if (trans
->curr_req_frag
== trans
->req_hdr
->num_frags
) {
1252 if (qlcnic_sriov_add_act_list(sriov
, vf
, trans
)) {
1253 qlcnic_free_mbx_args(&cmd
);
1254 qlcnic_sriov_cleanup_transaction(trans
);
1257 spin_lock(&vf
->rcv_pend
.lock
);
1258 list_add_tail(&trans
->list
, &vf
->rcv_pend
.wait_list
);
1259 vf
->rcv_pend
.count
++;
1260 spin_unlock(&vf
->rcv_pend
.lock
);
1264 static void qlcnic_sriov_handle_msg_event(struct qlcnic_sriov
*sriov
,
1265 struct qlcnic_vf_info
*vf
)
1267 struct qlcnic_bc_hdr hdr
;
1268 u32
*ptr
= (u32
*)&hdr
;
1271 for (i
= 2; i
< 6; i
++)
1272 ptr
[i
- 2] = readl(QLCNIC_MBX_FW(vf
->adapter
->ahw
, i
));
1273 msg_type
= hdr
.msg_type
;
1276 case QLC_BC_COMMAND
:
1277 qlcnic_sriov_handle_bc_cmd(sriov
, &hdr
, vf
);
1279 case QLC_BC_RESPONSE
:
1280 qlcnic_sriov_handle_bc_resp(&hdr
, vf
);
1285 static void qlcnic_sriov_handle_flr_event(struct qlcnic_sriov
*sriov
,
1286 struct qlcnic_vf_info
*vf
)
1288 struct qlcnic_adapter
*adapter
= vf
->adapter
;
1290 if (qlcnic_sriov_pf_check(adapter
))
1291 qlcnic_sriov_pf_handle_flr(sriov
, vf
);
1293 dev_err(&adapter
->pdev
->dev
,
1294 "Invalid event to VF. VF should not get FLR event\n");
1297 void qlcnic_sriov_handle_bc_event(struct qlcnic_adapter
*adapter
, u32 event
)
1299 struct qlcnic_vf_info
*vf
;
1300 struct qlcnic_sriov
*sriov
;
1304 sriov
= adapter
->ahw
->sriov
;
1305 pci_func
= qlcnic_sriov_target_func_id(event
);
1306 index
= qlcnic_sriov_func_to_index(adapter
, pci_func
);
1311 vf
= &sriov
->vf_info
[index
];
1312 vf
->pci_func
= pci_func
;
1314 if (qlcnic_sriov_channel_free_check(event
))
1315 complete(&vf
->ch_free_cmpl
);
1317 if (qlcnic_sriov_flr_check(event
)) {
1318 qlcnic_sriov_handle_flr_event(sriov
, vf
);
1322 if (qlcnic_sriov_bc_msg_check(event
))
1323 qlcnic_sriov_handle_msg_event(sriov
, vf
);
1326 int qlcnic_sriov_cfg_bc_intr(struct qlcnic_adapter
*adapter
, u8 enable
)
1328 struct qlcnic_cmd_args cmd
;
1331 if (!test_bit(__QLCNIC_SRIOV_ENABLE
, &adapter
->state
))
1334 if (qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_BC_EVENT_SETUP
))
1338 cmd
.req
.arg
[1] = (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7);
1340 err
= qlcnic_83xx_issue_cmd(adapter
, &cmd
);
1342 if (err
!= QLCNIC_RCODE_SUCCESS
) {
1343 dev_err(&adapter
->pdev
->dev
,
1344 "Failed to %s bc events, err=%d\n",
1345 (enable
? "enable" : "disable"), err
);
1348 qlcnic_free_mbx_args(&cmd
);
1352 static int qlcnic_sriov_retry_bc_cmd(struct qlcnic_adapter
*adapter
,
1353 struct qlcnic_bc_trans
*trans
)
1355 u8 max
= QLC_BC_CMD_MAX_RETRY_CNT
;
1358 state
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_DEV_STATE
);
1359 if (state
== QLC_83XX_IDC_DEV_READY
) {
1361 clear_bit(QLC_BC_VF_CHANNEL
, &trans
->vf
->state
);
1362 trans
->trans_state
= QLC_INIT
;
1363 if (++adapter
->fw_fail_cnt
> max
)
1372 static int __qlcnic_sriov_issue_cmd(struct qlcnic_adapter
*adapter
,
1373 struct qlcnic_cmd_args
*cmd
)
1375 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
1376 struct qlcnic_mailbox
*mbx
= ahw
->mailbox
;
1377 struct device
*dev
= &adapter
->pdev
->dev
;
1378 struct qlcnic_bc_trans
*trans
;
1380 u32 rsp_data
, opcode
, mbx_err_code
, rsp
;
1381 u16 seq
= ++adapter
->ahw
->sriov
->bc
.trans_counter
;
1382 u8 func
= ahw
->pci_func
;
1384 rsp
= qlcnic_sriov_alloc_bc_trans(&trans
);
1388 rsp
= qlcnic_sriov_prepare_bc_hdr(trans
, cmd
, seq
, QLC_BC_COMMAND
);
1390 goto cleanup_transaction
;
1393 if (!test_bit(QLC_83XX_MBX_READY
, &mbx
->status
)) {
1395 QLCDB(adapter
, DRV
, "MBX not Ready!(cmd 0x%x) for VF 0x%x\n",
1396 QLCNIC_MBX_RSP(cmd
->req
.arg
[0]), func
);
1400 err
= qlcnic_sriov_send_bc_cmd(adapter
, trans
, func
);
1402 dev_err(dev
, "MBX command 0x%x timed out for VF %d\n",
1403 (cmd
->req
.arg
[0] & 0xffff), func
);
1404 rsp
= QLCNIC_RCODE_TIMEOUT
;
1406 /* After adapter reset PF driver may take some time to
1407 * respond to VF's request. Retry request till maximum retries.
1409 if ((trans
->req_hdr
->cmd_op
== QLCNIC_BC_CMD_CHANNEL_INIT
) &&
1410 !qlcnic_sriov_retry_bc_cmd(adapter
, trans
))
1416 rsp_data
= cmd
->rsp
.arg
[0];
1417 mbx_err_code
= QLCNIC_MBX_STATUS(rsp_data
);
1418 opcode
= QLCNIC_MBX_RSP(cmd
->req
.arg
[0]);
1420 if ((mbx_err_code
== QLCNIC_MBX_RSP_OK
) ||
1421 (mbx_err_code
== QLCNIC_MBX_PORT_RSP_OK
)) {
1422 rsp
= QLCNIC_RCODE_SUCCESS
;
1424 if (cmd
->type
== QLC_83XX_MBX_CMD_NO_WAIT
) {
1425 rsp
= QLCNIC_RCODE_SUCCESS
;
1432 "MBX command 0x%x failed with err:0x%x for VF %d\n",
1433 opcode
, mbx_err_code
, func
);
1438 if (rsp
== QLCNIC_RCODE_TIMEOUT
) {
1439 ahw
->reset_context
= 1;
1440 adapter
->need_fw_reset
= 1;
1441 clear_bit(QLC_83XX_MBX_READY
, &mbx
->status
);
1444 cleanup_transaction
:
1445 qlcnic_sriov_cleanup_transaction(trans
);
1448 if (cmd
->type
== QLC_83XX_MBX_CMD_NO_WAIT
) {
1449 qlcnic_free_mbx_args(cmd
);
1457 static int qlcnic_sriov_issue_cmd(struct qlcnic_adapter
*adapter
,
1458 struct qlcnic_cmd_args
*cmd
)
1460 if (cmd
->type
== QLC_83XX_MBX_CMD_NO_WAIT
)
1461 return qlcnic_sriov_async_issue_cmd(adapter
, cmd
);
1463 return __qlcnic_sriov_issue_cmd(adapter
, cmd
);
1466 static int qlcnic_sriov_channel_cfg_cmd(struct qlcnic_adapter
*adapter
, u8 cmd_op
)
1468 struct qlcnic_cmd_args cmd
;
1469 struct qlcnic_vf_info
*vf
= &adapter
->ahw
->sriov
->vf_info
[0];
1472 memset(&cmd
, 0, sizeof(cmd
));
1473 if (qlcnic_sriov_alloc_bc_mbx_args(&cmd
, cmd_op
))
1476 ret
= qlcnic_issue_cmd(adapter
, &cmd
);
1478 dev_err(&adapter
->pdev
->dev
,
1479 "Failed bc channel %s %d\n", cmd_op
? "term" : "init",
1484 cmd_op
= (cmd
.rsp
.arg
[0] & 0xff);
1485 if (cmd
.rsp
.arg
[0] >> 25 == 2)
1487 if (cmd_op
== QLCNIC_BC_CMD_CHANNEL_INIT
)
1488 set_bit(QLC_BC_VF_STATE
, &vf
->state
);
1490 clear_bit(QLC_BC_VF_STATE
, &vf
->state
);
1493 qlcnic_free_mbx_args(&cmd
);
1497 static void qlcnic_vf_add_mc_list(struct net_device
*netdev
, const u8
*mac
,
1498 enum qlcnic_mac_type mac_type
)
1500 struct qlcnic_adapter
*adapter
= netdev_priv(netdev
);
1501 struct qlcnic_sriov
*sriov
= adapter
->ahw
->sriov
;
1502 struct qlcnic_vf_info
*vf
;
1506 vf
= &adapter
->ahw
->sriov
->vf_info
[0];
1508 if (!qlcnic_sriov_check_any_vlan(vf
)) {
1509 qlcnic_nic_add_mac(adapter
, mac
, 0, mac_type
);
1511 spin_lock(&vf
->vlan_list_lock
);
1512 for (i
= 0; i
< sriov
->num_allowed_vlans
; i
++) {
1513 vlan_id
= vf
->sriov_vlans
[i
];
1515 qlcnic_nic_add_mac(adapter
, mac
, vlan_id
,
1518 spin_unlock(&vf
->vlan_list_lock
);
1519 if (qlcnic_84xx_check(adapter
))
1520 qlcnic_nic_add_mac(adapter
, mac
, 0, mac_type
);
1524 void qlcnic_sriov_cleanup_async_list(struct qlcnic_back_channel
*bc
)
1526 struct list_head
*head
= &bc
->async_cmd_list
;
1527 struct qlcnic_async_cmd
*entry
;
1529 flush_workqueue(bc
->bc_async_wq
);
1530 cancel_work_sync(&bc
->vf_async_work
);
1532 spin_lock(&bc
->queue_lock
);
1533 while (!list_empty(head
)) {
1534 entry
= list_entry(head
->next
, struct qlcnic_async_cmd
,
1536 list_del(&entry
->list
);
1540 spin_unlock(&bc
->queue_lock
);
1543 void qlcnic_sriov_vf_set_multi(struct net_device
*netdev
)
1545 struct qlcnic_adapter
*adapter
= netdev_priv(netdev
);
1546 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
1547 static const u8 bcast_addr
[ETH_ALEN
] = {
1548 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
1550 struct netdev_hw_addr
*ha
;
1551 u32 mode
= VPORT_MISS_MODE_DROP
;
1553 if (!test_bit(__QLCNIC_FW_ATTACHED
, &adapter
->state
))
1556 if (netdev
->flags
& IFF_PROMISC
) {
1557 if (!(adapter
->flags
& QLCNIC_PROMISC_DISABLED
))
1558 mode
= VPORT_MISS_MODE_ACCEPT_ALL
;
1559 } else if ((netdev
->flags
& IFF_ALLMULTI
) ||
1560 (netdev_mc_count(netdev
) > ahw
->max_mc_count
)) {
1561 mode
= VPORT_MISS_MODE_ACCEPT_MULTI
;
1563 qlcnic_vf_add_mc_list(netdev
, bcast_addr
, QLCNIC_BROADCAST_MAC
);
1564 if (!netdev_mc_empty(netdev
)) {
1565 qlcnic_flush_mcast_mac(adapter
);
1566 netdev_for_each_mc_addr(ha
, netdev
)
1567 qlcnic_vf_add_mc_list(netdev
, ha
->addr
,
1568 QLCNIC_MULTICAST_MAC
);
1572 /* configure unicast MAC address, if there is not sufficient space
1573 * to store all the unicast addresses then enable promiscuous mode
1575 if (netdev_uc_count(netdev
) > ahw
->max_uc_count
) {
1576 mode
= VPORT_MISS_MODE_ACCEPT_ALL
;
1577 } else if (!netdev_uc_empty(netdev
)) {
1578 netdev_for_each_uc_addr(ha
, netdev
)
1579 qlcnic_vf_add_mc_list(netdev
, ha
->addr
,
1580 QLCNIC_UNICAST_MAC
);
1583 if (adapter
->pdev
->is_virtfn
) {
1584 if (mode
== VPORT_MISS_MODE_ACCEPT_ALL
&&
1585 !adapter
->fdb_mac_learn
) {
1586 qlcnic_alloc_lb_filters_mem(adapter
);
1587 adapter
->drv_mac_learn
= 1;
1588 adapter
->rx_mac_learn
= true;
1590 adapter
->drv_mac_learn
= 0;
1591 adapter
->rx_mac_learn
= false;
1595 qlcnic_nic_set_promisc(adapter
, mode
);
1598 static void qlcnic_sriov_handle_async_issue_cmd(struct work_struct
*work
)
1600 struct qlcnic_async_cmd
*entry
, *tmp
;
1601 struct qlcnic_back_channel
*bc
;
1602 struct qlcnic_cmd_args
*cmd
;
1603 struct list_head
*head
;
1604 LIST_HEAD(del_list
);
1606 bc
= container_of(work
, struct qlcnic_back_channel
, vf_async_work
);
1607 head
= &bc
->async_cmd_list
;
1609 spin_lock(&bc
->queue_lock
);
1610 list_splice_init(head
, &del_list
);
1611 spin_unlock(&bc
->queue_lock
);
1613 list_for_each_entry_safe(entry
, tmp
, &del_list
, list
) {
1614 list_del(&entry
->list
);
1616 __qlcnic_sriov_issue_cmd(bc
->adapter
, cmd
);
1620 if (!list_empty(head
))
1621 queue_work(bc
->bc_async_wq
, &bc
->vf_async_work
);
1626 static struct qlcnic_async_cmd
*
1627 qlcnic_sriov_alloc_async_cmd(struct qlcnic_back_channel
*bc
,
1628 struct qlcnic_cmd_args
*cmd
)
1630 struct qlcnic_async_cmd
*entry
= NULL
;
1632 entry
= kzalloc(sizeof(*entry
), GFP_ATOMIC
);
1638 spin_lock(&bc
->queue_lock
);
1639 list_add_tail(&entry
->list
, &bc
->async_cmd_list
);
1640 spin_unlock(&bc
->queue_lock
);
1645 static void qlcnic_sriov_schedule_async_cmd(struct qlcnic_back_channel
*bc
,
1646 struct qlcnic_cmd_args
*cmd
)
1648 struct qlcnic_async_cmd
*entry
= NULL
;
1650 entry
= qlcnic_sriov_alloc_async_cmd(bc
, cmd
);
1652 qlcnic_free_mbx_args(cmd
);
1657 queue_work(bc
->bc_async_wq
, &bc
->vf_async_work
);
1660 static int qlcnic_sriov_async_issue_cmd(struct qlcnic_adapter
*adapter
,
1661 struct qlcnic_cmd_args
*cmd
)
1664 struct qlcnic_back_channel
*bc
= &adapter
->ahw
->sriov
->bc
;
1666 if (adapter
->need_fw_reset
)
1669 qlcnic_sriov_schedule_async_cmd(bc
, cmd
);
1674 static int qlcnic_sriov_vf_reinit_driver(struct qlcnic_adapter
*adapter
)
1678 adapter
->need_fw_reset
= 0;
1679 qlcnic_83xx_reinit_mbx_work(adapter
->ahw
->mailbox
);
1680 qlcnic_83xx_enable_mbx_interrupt(adapter
);
1682 err
= qlcnic_sriov_cfg_bc_intr(adapter
, 1);
1686 err
= qlcnic_sriov_channel_cfg_cmd(adapter
, QLCNIC_BC_CMD_CHANNEL_INIT
);
1688 goto err_out_cleanup_bc_intr
;
1690 err
= qlcnic_sriov_vf_init_driver(adapter
);
1692 goto err_out_term_channel
;
1696 err_out_term_channel
:
1697 qlcnic_sriov_channel_cfg_cmd(adapter
, QLCNIC_BC_CMD_CHANNEL_TERM
);
1699 err_out_cleanup_bc_intr
:
1700 qlcnic_sriov_cfg_bc_intr(adapter
, 0);
1704 static void qlcnic_sriov_vf_attach(struct qlcnic_adapter
*adapter
)
1706 struct net_device
*netdev
= adapter
->netdev
;
1708 if (netif_running(netdev
)) {
1709 if (!qlcnic_up(adapter
, netdev
))
1710 qlcnic_restore_indev_addr(netdev
, NETDEV_UP
);
1713 netif_device_attach(netdev
);
1716 static void qlcnic_sriov_vf_detach(struct qlcnic_adapter
*adapter
)
1718 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
1719 struct qlcnic_intrpt_config
*intr_tbl
= ahw
->intr_tbl
;
1720 struct net_device
*netdev
= adapter
->netdev
;
1721 u8 i
, max_ints
= ahw
->num_msix
- 1;
1723 netif_device_detach(netdev
);
1724 qlcnic_83xx_detach_mailbox_work(adapter
);
1725 qlcnic_83xx_disable_mbx_intr(adapter
);
1727 if (netif_running(netdev
))
1728 qlcnic_down(adapter
, netdev
);
1730 for (i
= 0; i
< max_ints
; i
++) {
1732 intr_tbl
[i
].enabled
= 0;
1733 intr_tbl
[i
].src
= 0;
1735 ahw
->reset_context
= 0;
1738 static int qlcnic_sriov_vf_handle_dev_ready(struct qlcnic_adapter
*adapter
)
1740 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
1741 struct device
*dev
= &adapter
->pdev
->dev
;
1742 struct qlc_83xx_idc
*idc
= &ahw
->idc
;
1743 u8 func
= ahw
->pci_func
;
1746 if ((idc
->prev_state
== QLC_83XX_IDC_DEV_NEED_RESET
) ||
1747 (idc
->prev_state
== QLC_83XX_IDC_DEV_INIT
)) {
1748 if (!qlcnic_sriov_vf_reinit_driver(adapter
)) {
1749 qlcnic_sriov_vf_attach(adapter
);
1750 adapter
->fw_fail_cnt
= 0;
1752 "%s: Reinitialization of VF 0x%x done after FW reset\n",
1756 "%s: Reinitialization of VF 0x%x failed after FW reset\n",
1758 state
= QLCRDX(ahw
, QLC_83XX_IDC_DEV_STATE
);
1759 dev_info(dev
, "Current state 0x%x after FW reset\n",
1767 static int qlcnic_sriov_vf_handle_context_reset(struct qlcnic_adapter
*adapter
)
1769 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
1770 struct qlcnic_mailbox
*mbx
= ahw
->mailbox
;
1771 struct device
*dev
= &adapter
->pdev
->dev
;
1772 struct qlc_83xx_idc
*idc
= &ahw
->idc
;
1773 u8 func
= ahw
->pci_func
;
1776 adapter
->reset_ctx_cnt
++;
1778 /* Skip the context reset and check if FW is hung */
1779 if (adapter
->reset_ctx_cnt
< 3) {
1780 adapter
->need_fw_reset
= 1;
1781 clear_bit(QLC_83XX_MBX_READY
, &mbx
->status
);
1783 "Resetting context, wait here to check if FW is in failed state\n");
1787 /* Check if number of resets exceed the threshold.
1788 * If it exceeds the threshold just fail the VF.
1790 if (adapter
->reset_ctx_cnt
> QLC_83XX_VF_RESET_FAIL_THRESH
) {
1791 clear_bit(QLC_83XX_MODULE_LOADED
, &idc
->status
);
1792 adapter
->tx_timeo_cnt
= 0;
1793 adapter
->fw_fail_cnt
= 0;
1794 adapter
->reset_ctx_cnt
= 0;
1795 qlcnic_sriov_vf_detach(adapter
);
1797 "Device context resets have exceeded the threshold, device interface will be shutdown\n");
1801 dev_info(dev
, "Resetting context of VF 0x%x\n", func
);
1802 dev_info(dev
, "%s: Context reset count %d for VF 0x%x\n",
1803 __func__
, adapter
->reset_ctx_cnt
, func
);
1804 set_bit(__QLCNIC_RESETTING
, &adapter
->state
);
1805 adapter
->need_fw_reset
= 1;
1806 clear_bit(QLC_83XX_MBX_READY
, &mbx
->status
);
1807 qlcnic_sriov_vf_detach(adapter
);
1808 adapter
->need_fw_reset
= 0;
1810 if (!qlcnic_sriov_vf_reinit_driver(adapter
)) {
1811 qlcnic_sriov_vf_attach(adapter
);
1812 adapter
->tx_timeo_cnt
= 0;
1813 adapter
->reset_ctx_cnt
= 0;
1814 adapter
->fw_fail_cnt
= 0;
1815 dev_info(dev
, "Done resetting context for VF 0x%x\n", func
);
1817 dev_err(dev
, "%s: Reinitialization of VF 0x%x failed\n",
1819 state
= QLCRDX(ahw
, QLC_83XX_IDC_DEV_STATE
);
1820 dev_info(dev
, "%s: Current state 0x%x\n", __func__
, state
);
1826 static int qlcnic_sriov_vf_idc_ready_state(struct qlcnic_adapter
*adapter
)
1828 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
1831 if (ahw
->idc
.prev_state
!= QLC_83XX_IDC_DEV_READY
)
1832 ret
= qlcnic_sriov_vf_handle_dev_ready(adapter
);
1833 else if (ahw
->reset_context
)
1834 ret
= qlcnic_sriov_vf_handle_context_reset(adapter
);
1836 clear_bit(__QLCNIC_RESETTING
, &adapter
->state
);
1840 static int qlcnic_sriov_vf_idc_failed_state(struct qlcnic_adapter
*adapter
)
1842 struct qlc_83xx_idc
*idc
= &adapter
->ahw
->idc
;
1844 dev_err(&adapter
->pdev
->dev
, "Device is in failed state\n");
1845 if (idc
->prev_state
== QLC_83XX_IDC_DEV_READY
)
1846 qlcnic_sriov_vf_detach(adapter
);
1848 clear_bit(QLC_83XX_MODULE_LOADED
, &idc
->status
);
1849 clear_bit(__QLCNIC_RESETTING
, &adapter
->state
);
1854 qlcnic_sriov_vf_idc_need_quiescent_state(struct qlcnic_adapter
*adapter
)
1856 struct qlcnic_mailbox
*mbx
= adapter
->ahw
->mailbox
;
1857 struct qlc_83xx_idc
*idc
= &adapter
->ahw
->idc
;
1859 dev_info(&adapter
->pdev
->dev
, "Device is in quiescent state\n");
1860 if (idc
->prev_state
== QLC_83XX_IDC_DEV_READY
) {
1861 set_bit(__QLCNIC_RESETTING
, &adapter
->state
);
1862 adapter
->tx_timeo_cnt
= 0;
1863 adapter
->reset_ctx_cnt
= 0;
1864 clear_bit(QLC_83XX_MBX_READY
, &mbx
->status
);
1865 qlcnic_sriov_vf_detach(adapter
);
1871 static int qlcnic_sriov_vf_idc_init_reset_state(struct qlcnic_adapter
*adapter
)
1873 struct qlcnic_mailbox
*mbx
= adapter
->ahw
->mailbox
;
1874 struct qlc_83xx_idc
*idc
= &adapter
->ahw
->idc
;
1875 u8 func
= adapter
->ahw
->pci_func
;
1877 if (idc
->prev_state
== QLC_83XX_IDC_DEV_READY
) {
1878 dev_err(&adapter
->pdev
->dev
,
1879 "Firmware hang detected by VF 0x%x\n", func
);
1880 set_bit(__QLCNIC_RESETTING
, &adapter
->state
);
1881 adapter
->tx_timeo_cnt
= 0;
1882 adapter
->reset_ctx_cnt
= 0;
1883 clear_bit(QLC_83XX_MBX_READY
, &mbx
->status
);
1884 qlcnic_sriov_vf_detach(adapter
);
1889 static int qlcnic_sriov_vf_idc_unknown_state(struct qlcnic_adapter
*adapter
)
1891 dev_err(&adapter
->pdev
->dev
, "%s: Device in unknown state\n", __func__
);
1895 static void qlcnic_sriov_vf_periodic_tasks(struct qlcnic_adapter
*adapter
)
1897 if (adapter
->fhash
.fnum
)
1898 qlcnic_prune_lb_filters(adapter
);
1901 static void qlcnic_sriov_vf_poll_dev_state(struct work_struct
*work
)
1903 struct qlcnic_adapter
*adapter
;
1904 struct qlc_83xx_idc
*idc
;
1907 adapter
= container_of(work
, struct qlcnic_adapter
, fw_work
.work
);
1908 idc
= &adapter
->ahw
->idc
;
1909 idc
->curr_state
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_DEV_STATE
);
1911 switch (idc
->curr_state
) {
1912 case QLC_83XX_IDC_DEV_READY
:
1913 ret
= qlcnic_sriov_vf_idc_ready_state(adapter
);
1915 case QLC_83XX_IDC_DEV_NEED_RESET
:
1916 case QLC_83XX_IDC_DEV_INIT
:
1917 ret
= qlcnic_sriov_vf_idc_init_reset_state(adapter
);
1919 case QLC_83XX_IDC_DEV_NEED_QUISCENT
:
1920 ret
= qlcnic_sriov_vf_idc_need_quiescent_state(adapter
);
1922 case QLC_83XX_IDC_DEV_FAILED
:
1923 ret
= qlcnic_sriov_vf_idc_failed_state(adapter
);
1925 case QLC_83XX_IDC_DEV_QUISCENT
:
1928 ret
= qlcnic_sriov_vf_idc_unknown_state(adapter
);
1931 idc
->prev_state
= idc
->curr_state
;
1932 qlcnic_sriov_vf_periodic_tasks(adapter
);
1934 if (!ret
&& test_bit(QLC_83XX_MODULE_LOADED
, &idc
->status
))
1935 qlcnic_schedule_work(adapter
, qlcnic_sriov_vf_poll_dev_state
,
1939 static void qlcnic_sriov_vf_cancel_fw_work(struct qlcnic_adapter
*adapter
)
1941 while (test_and_set_bit(__QLCNIC_RESETTING
, &adapter
->state
))
1944 clear_bit(QLC_83XX_MODULE_LOADED
, &adapter
->ahw
->idc
.status
);
1945 clear_bit(__QLCNIC_RESETTING
, &adapter
->state
);
1946 cancel_delayed_work_sync(&adapter
->fw_work
);
1949 static int qlcnic_sriov_check_vlan_id(struct qlcnic_sriov
*sriov
,
1950 struct qlcnic_vf_info
*vf
, u16 vlan_id
)
1952 int i
, err
= -EINVAL
;
1954 if (!vf
->sriov_vlans
)
1957 spin_lock_bh(&vf
->vlan_list_lock
);
1959 for (i
= 0; i
< sriov
->num_allowed_vlans
; i
++) {
1960 if (vf
->sriov_vlans
[i
] == vlan_id
) {
1966 spin_unlock_bh(&vf
->vlan_list_lock
);
1970 static int qlcnic_sriov_validate_num_vlans(struct qlcnic_sriov
*sriov
,
1971 struct qlcnic_vf_info
*vf
)
1975 spin_lock_bh(&vf
->vlan_list_lock
);
1977 if (vf
->num_vlan
>= sriov
->num_allowed_vlans
)
1980 spin_unlock_bh(&vf
->vlan_list_lock
);
1984 static int qlcnic_sriov_validate_vlan_cfg(struct qlcnic_adapter
*adapter
,
1987 struct qlcnic_sriov
*sriov
= adapter
->ahw
->sriov
;
1988 struct qlcnic_vf_info
*vf
;
1993 vf
= &adapter
->ahw
->sriov
->vf_info
[0];
1994 vlan_exist
= qlcnic_sriov_check_any_vlan(vf
);
1995 if (sriov
->vlan_mode
!= QLC_GUEST_VLAN_MODE
)
1999 if (qlcnic_83xx_vf_check(adapter
) && vlan_exist
)
2002 if (qlcnic_sriov_validate_num_vlans(sriov
, vf
))
2005 if (sriov
->any_vlan
) {
2006 for (i
= 0; i
< sriov
->num_allowed_vlans
; i
++) {
2007 if (sriov
->allowed_vlans
[i
] == vid
)
2015 if (!vlan_exist
|| qlcnic_sriov_check_vlan_id(sriov
, vf
, vid
))
2022 static void qlcnic_sriov_vlan_operation(struct qlcnic_vf_info
*vf
, u16 vlan_id
,
2023 enum qlcnic_vlan_operations opcode
)
2025 struct qlcnic_adapter
*adapter
= vf
->adapter
;
2026 struct qlcnic_sriov
*sriov
;
2028 sriov
= adapter
->ahw
->sriov
;
2030 if (!vf
->sriov_vlans
)
2033 spin_lock_bh(&vf
->vlan_list_lock
);
2037 qlcnic_sriov_add_vlan_id(sriov
, vf
, vlan_id
);
2039 case QLC_VLAN_DELETE
:
2040 qlcnic_sriov_del_vlan_id(sriov
, vf
, vlan_id
);
2043 netdev_err(adapter
->netdev
, "Invalid VLAN operation\n");
2046 spin_unlock_bh(&vf
->vlan_list_lock
);
2050 int qlcnic_sriov_cfg_vf_guest_vlan(struct qlcnic_adapter
*adapter
,
2053 struct qlcnic_sriov
*sriov
= adapter
->ahw
->sriov
;
2054 struct net_device
*netdev
= adapter
->netdev
;
2055 struct qlcnic_vf_info
*vf
;
2056 struct qlcnic_cmd_args cmd
;
2059 memset(&cmd
, 0, sizeof(cmd
));
2063 vf
= &adapter
->ahw
->sriov
->vf_info
[0];
2064 ret
= qlcnic_sriov_validate_vlan_cfg(adapter
, vid
, enable
);
2068 ret
= qlcnic_sriov_alloc_bc_mbx_args(&cmd
,
2069 QLCNIC_BC_CMD_CFG_GUEST_VLAN
);
2073 cmd
.req
.arg
[1] = (enable
& 1) | vid
<< 16;
2075 qlcnic_sriov_cleanup_async_list(&sriov
->bc
);
2076 ret
= qlcnic_issue_cmd(adapter
, &cmd
);
2078 dev_err(&adapter
->pdev
->dev
,
2079 "Failed to configure guest VLAN, err=%d\n", ret
);
2081 netif_addr_lock_bh(netdev
);
2082 qlcnic_free_mac_list(adapter
);
2083 netif_addr_unlock_bh(netdev
);
2086 qlcnic_sriov_vlan_operation(vf
, vid
, QLC_VLAN_ADD
);
2088 qlcnic_sriov_vlan_operation(vf
, vid
, QLC_VLAN_DELETE
);
2090 netif_addr_lock_bh(netdev
);
2091 qlcnic_set_multi(netdev
);
2092 netif_addr_unlock_bh(netdev
);
2095 qlcnic_free_mbx_args(&cmd
);
2099 static void qlcnic_sriov_vf_free_mac_list(struct qlcnic_adapter
*adapter
)
2101 struct list_head
*head
= &adapter
->mac_list
;
2102 struct qlcnic_mac_vlan_list
*cur
;
2104 while (!list_empty(head
)) {
2105 cur
= list_entry(head
->next
, struct qlcnic_mac_vlan_list
, list
);
2106 qlcnic_sre_macaddr_change(adapter
, cur
->mac_addr
, cur
->vlan_id
,
2108 list_del(&cur
->list
);
2114 static int qlcnic_sriov_vf_shutdown(struct pci_dev
*pdev
)
2116 struct qlcnic_adapter
*adapter
= pci_get_drvdata(pdev
);
2117 struct net_device
*netdev
= adapter
->netdev
;
2120 netif_device_detach(netdev
);
2121 qlcnic_cancel_idc_work(adapter
);
2123 if (netif_running(netdev
))
2124 qlcnic_down(adapter
, netdev
);
2126 qlcnic_sriov_channel_cfg_cmd(adapter
, QLCNIC_BC_CMD_CHANNEL_TERM
);
2127 qlcnic_sriov_cfg_bc_intr(adapter
, 0);
2128 qlcnic_83xx_disable_mbx_intr(adapter
);
2129 cancel_delayed_work_sync(&adapter
->idc_aen_work
);
2131 retval
= pci_save_state(pdev
);
2138 static int qlcnic_sriov_vf_resume(struct qlcnic_adapter
*adapter
)
2140 struct qlc_83xx_idc
*idc
= &adapter
->ahw
->idc
;
2141 struct net_device
*netdev
= adapter
->netdev
;
2144 set_bit(QLC_83XX_MODULE_LOADED
, &idc
->status
);
2145 qlcnic_83xx_enable_mbx_interrupt(adapter
);
2146 err
= qlcnic_sriov_cfg_bc_intr(adapter
, 1);
2150 err
= qlcnic_sriov_channel_cfg_cmd(adapter
, QLCNIC_BC_CMD_CHANNEL_INIT
);
2152 if (netif_running(netdev
)) {
2153 err
= qlcnic_up(adapter
, netdev
);
2155 qlcnic_restore_indev_addr(netdev
, NETDEV_UP
);
2159 netif_device_attach(netdev
);
2160 qlcnic_schedule_work(adapter
, qlcnic_sriov_vf_poll_dev_state
,
2165 void qlcnic_sriov_alloc_vlans(struct qlcnic_adapter
*adapter
)
2167 struct qlcnic_sriov
*sriov
= adapter
->ahw
->sriov
;
2168 struct qlcnic_vf_info
*vf
;
2171 for (i
= 0; i
< sriov
->num_vfs
; i
++) {
2172 vf
= &sriov
->vf_info
[i
];
2173 vf
->sriov_vlans
= kcalloc(sriov
->num_allowed_vlans
,
2174 sizeof(*vf
->sriov_vlans
), GFP_KERNEL
);
2178 void qlcnic_sriov_free_vlans(struct qlcnic_adapter
*adapter
)
2180 struct qlcnic_sriov
*sriov
= adapter
->ahw
->sriov
;
2181 struct qlcnic_vf_info
*vf
;
2184 for (i
= 0; i
< sriov
->num_vfs
; i
++) {
2185 vf
= &sriov
->vf_info
[i
];
2186 kfree(vf
->sriov_vlans
);
2187 vf
->sriov_vlans
= NULL
;
2191 void qlcnic_sriov_add_vlan_id(struct qlcnic_sriov
*sriov
,
2192 struct qlcnic_vf_info
*vf
, u16 vlan_id
)
2196 for (i
= 0; i
< sriov
->num_allowed_vlans
; i
++) {
2197 if (!vf
->sriov_vlans
[i
]) {
2198 vf
->sriov_vlans
[i
] = vlan_id
;
2205 void qlcnic_sriov_del_vlan_id(struct qlcnic_sriov
*sriov
,
2206 struct qlcnic_vf_info
*vf
, u16 vlan_id
)
2210 for (i
= 0; i
< sriov
->num_allowed_vlans
; i
++) {
2211 if (vf
->sriov_vlans
[i
] == vlan_id
) {
2212 vf
->sriov_vlans
[i
] = 0;
2219 bool qlcnic_sriov_check_any_vlan(struct qlcnic_vf_info
*vf
)
2223 spin_lock_bh(&vf
->vlan_list_lock
);
2228 spin_unlock_bh(&vf
->vlan_list_lock
);