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[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic_sriov_common.c
1 /*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
8 #include "qlcnic_sriov.h"
9 #include "qlcnic.h"
10 #include "qlcnic_83xx_hw.h"
11 #include <linux/types.h>
12
13 #define QLC_BC_COMMAND 0
14 #define QLC_BC_RESPONSE 1
15
16 #define QLC_MBOX_RESP_TIMEOUT (10 * HZ)
17 #define QLC_MBOX_CH_FREE_TIMEOUT (10 * HZ)
18
19 #define QLC_BC_MSG 0
20 #define QLC_BC_CFREE 1
21 #define QLC_BC_FLR 2
22 #define QLC_BC_HDR_SZ 16
23 #define QLC_BC_PAYLOAD_SZ (1024 - QLC_BC_HDR_SZ)
24
25 #define QLC_DEFAULT_RCV_DESCRIPTORS_SRIOV_VF 2048
26 #define QLC_DEFAULT_JUMBO_RCV_DESCRIPTORS_SRIOV_VF 512
27
28 #define QLC_83XX_VF_RESET_FAIL_THRESH 8
29 #define QLC_BC_CMD_MAX_RETRY_CNT 5
30
31 static void qlcnic_sriov_vf_free_mac_list(struct qlcnic_adapter *);
32 static int qlcnic_sriov_alloc_bc_mbx_args(struct qlcnic_cmd_args *, u32);
33 static void qlcnic_sriov_vf_poll_dev_state(struct work_struct *);
34 static void qlcnic_sriov_vf_cancel_fw_work(struct qlcnic_adapter *);
35 static void qlcnic_sriov_cleanup_transaction(struct qlcnic_bc_trans *);
36 static int qlcnic_sriov_issue_cmd(struct qlcnic_adapter *,
37 struct qlcnic_cmd_args *);
38 static int qlcnic_sriov_channel_cfg_cmd(struct qlcnic_adapter *, u8);
39 static void qlcnic_sriov_process_bc_cmd(struct work_struct *);
40 static int qlcnic_sriov_vf_shutdown(struct pci_dev *);
41 static int qlcnic_sriov_vf_resume(struct qlcnic_adapter *);
42 static int qlcnic_sriov_async_issue_cmd(struct qlcnic_adapter *,
43 struct qlcnic_cmd_args *);
44
45 static struct qlcnic_hardware_ops qlcnic_sriov_vf_hw_ops = {
46 .read_crb = qlcnic_83xx_read_crb,
47 .write_crb = qlcnic_83xx_write_crb,
48 .read_reg = qlcnic_83xx_rd_reg_indirect,
49 .write_reg = qlcnic_83xx_wrt_reg_indirect,
50 .get_mac_address = qlcnic_83xx_get_mac_address,
51 .setup_intr = qlcnic_83xx_setup_intr,
52 .alloc_mbx_args = qlcnic_83xx_alloc_mbx_args,
53 .mbx_cmd = qlcnic_sriov_issue_cmd,
54 .get_func_no = qlcnic_83xx_get_func_no,
55 .api_lock = qlcnic_83xx_cam_lock,
56 .api_unlock = qlcnic_83xx_cam_unlock,
57 .process_lb_rcv_ring_diag = qlcnic_83xx_process_rcv_ring_diag,
58 .create_rx_ctx = qlcnic_83xx_create_rx_ctx,
59 .create_tx_ctx = qlcnic_83xx_create_tx_ctx,
60 .del_rx_ctx = qlcnic_83xx_del_rx_ctx,
61 .del_tx_ctx = qlcnic_83xx_del_tx_ctx,
62 .setup_link_event = qlcnic_83xx_setup_link_event,
63 .get_nic_info = qlcnic_83xx_get_nic_info,
64 .get_pci_info = qlcnic_83xx_get_pci_info,
65 .set_nic_info = qlcnic_83xx_set_nic_info,
66 .change_macvlan = qlcnic_83xx_sre_macaddr_change,
67 .napi_enable = qlcnic_83xx_napi_enable,
68 .napi_disable = qlcnic_83xx_napi_disable,
69 .config_intr_coal = qlcnic_83xx_config_intr_coal,
70 .config_rss = qlcnic_83xx_config_rss,
71 .config_hw_lro = qlcnic_83xx_config_hw_lro,
72 .config_promisc_mode = qlcnic_83xx_nic_set_promisc,
73 .change_l2_filter = qlcnic_83xx_change_l2_filter,
74 .get_board_info = qlcnic_83xx_get_port_info,
75 .free_mac_list = qlcnic_sriov_vf_free_mac_list,
76 .enable_sds_intr = qlcnic_83xx_enable_sds_intr,
77 .disable_sds_intr = qlcnic_83xx_disable_sds_intr,
78 };
79
80 static struct qlcnic_nic_template qlcnic_sriov_vf_ops = {
81 .config_bridged_mode = qlcnic_config_bridged_mode,
82 .config_led = qlcnic_config_led,
83 .cancel_idc_work = qlcnic_sriov_vf_cancel_fw_work,
84 .napi_add = qlcnic_83xx_napi_add,
85 .napi_del = qlcnic_83xx_napi_del,
86 .shutdown = qlcnic_sriov_vf_shutdown,
87 .resume = qlcnic_sriov_vf_resume,
88 .config_ipaddr = qlcnic_83xx_config_ipaddr,
89 .clear_legacy_intr = qlcnic_83xx_clear_legacy_intr,
90 };
91
92 static const struct qlcnic_mailbox_metadata qlcnic_sriov_bc_mbx_tbl[] = {
93 {QLCNIC_BC_CMD_CHANNEL_INIT, 2, 2},
94 {QLCNIC_BC_CMD_CHANNEL_TERM, 2, 2},
95 {QLCNIC_BC_CMD_GET_ACL, 3, 14},
96 {QLCNIC_BC_CMD_CFG_GUEST_VLAN, 2, 2},
97 };
98
99 static inline bool qlcnic_sriov_bc_msg_check(u32 val)
100 {
101 return (val & (1 << QLC_BC_MSG)) ? true : false;
102 }
103
104 static inline bool qlcnic_sriov_channel_free_check(u32 val)
105 {
106 return (val & (1 << QLC_BC_CFREE)) ? true : false;
107 }
108
109 static inline bool qlcnic_sriov_flr_check(u32 val)
110 {
111 return (val & (1 << QLC_BC_FLR)) ? true : false;
112 }
113
114 static inline u8 qlcnic_sriov_target_func_id(u32 val)
115 {
116 return (val >> 4) & 0xff;
117 }
118
119 static int qlcnic_sriov_virtid_fn(struct qlcnic_adapter *adapter, int vf_id)
120 {
121 struct pci_dev *dev = adapter->pdev;
122 int pos;
123 u16 stride, offset;
124
125 if (qlcnic_sriov_vf_check(adapter))
126 return 0;
127
128 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
129 pci_read_config_word(dev, pos + PCI_SRIOV_VF_OFFSET, &offset);
130 pci_read_config_word(dev, pos + PCI_SRIOV_VF_STRIDE, &stride);
131
132 return (dev->devfn + offset + stride * vf_id) & 0xff;
133 }
134
135 int qlcnic_sriov_init(struct qlcnic_adapter *adapter, int num_vfs)
136 {
137 struct qlcnic_sriov *sriov;
138 struct qlcnic_back_channel *bc;
139 struct workqueue_struct *wq;
140 struct qlcnic_vport *vp;
141 struct qlcnic_vf_info *vf;
142 int err, i;
143
144 if (!qlcnic_sriov_enable_check(adapter))
145 return -EIO;
146
147 sriov = kzalloc(sizeof(struct qlcnic_sriov), GFP_KERNEL);
148 if (!sriov)
149 return -ENOMEM;
150
151 adapter->ahw->sriov = sriov;
152 sriov->num_vfs = num_vfs;
153 bc = &sriov->bc;
154 sriov->vf_info = kzalloc(sizeof(struct qlcnic_vf_info) *
155 num_vfs, GFP_KERNEL);
156 if (!sriov->vf_info) {
157 err = -ENOMEM;
158 goto qlcnic_free_sriov;
159 }
160
161 wq = create_singlethread_workqueue("bc-trans");
162 if (wq == NULL) {
163 err = -ENOMEM;
164 dev_err(&adapter->pdev->dev,
165 "Cannot create bc-trans workqueue\n");
166 goto qlcnic_free_vf_info;
167 }
168
169 bc->bc_trans_wq = wq;
170
171 wq = create_singlethread_workqueue("async");
172 if (wq == NULL) {
173 err = -ENOMEM;
174 dev_err(&adapter->pdev->dev, "Cannot create async workqueue\n");
175 goto qlcnic_destroy_trans_wq;
176 }
177
178 bc->bc_async_wq = wq;
179 INIT_LIST_HEAD(&bc->async_list);
180
181 for (i = 0; i < num_vfs; i++) {
182 vf = &sriov->vf_info[i];
183 vf->adapter = adapter;
184 vf->pci_func = qlcnic_sriov_virtid_fn(adapter, i);
185 mutex_init(&vf->send_cmd_lock);
186 spin_lock_init(&vf->vlan_list_lock);
187 INIT_LIST_HEAD(&vf->rcv_act.wait_list);
188 INIT_LIST_HEAD(&vf->rcv_pend.wait_list);
189 spin_lock_init(&vf->rcv_act.lock);
190 spin_lock_init(&vf->rcv_pend.lock);
191 init_completion(&vf->ch_free_cmpl);
192
193 INIT_WORK(&vf->trans_work, qlcnic_sriov_process_bc_cmd);
194
195 if (qlcnic_sriov_pf_check(adapter)) {
196 vp = kzalloc(sizeof(struct qlcnic_vport), GFP_KERNEL);
197 if (!vp) {
198 err = -ENOMEM;
199 goto qlcnic_destroy_async_wq;
200 }
201 sriov->vf_info[i].vp = vp;
202 vp->vlan_mode = QLC_GUEST_VLAN_MODE;
203 vp->max_tx_bw = MAX_BW;
204 vp->spoofchk = false;
205 random_ether_addr(vp->mac);
206 dev_info(&adapter->pdev->dev,
207 "MAC Address %pM is configured for VF %d\n",
208 vp->mac, i);
209 }
210 }
211
212 return 0;
213
214 qlcnic_destroy_async_wq:
215 destroy_workqueue(bc->bc_async_wq);
216
217 qlcnic_destroy_trans_wq:
218 destroy_workqueue(bc->bc_trans_wq);
219
220 qlcnic_free_vf_info:
221 kfree(sriov->vf_info);
222
223 qlcnic_free_sriov:
224 kfree(adapter->ahw->sriov);
225 return err;
226 }
227
228 void qlcnic_sriov_cleanup_list(struct qlcnic_trans_list *t_list)
229 {
230 struct qlcnic_bc_trans *trans;
231 struct qlcnic_cmd_args cmd;
232 unsigned long flags;
233
234 spin_lock_irqsave(&t_list->lock, flags);
235
236 while (!list_empty(&t_list->wait_list)) {
237 trans = list_first_entry(&t_list->wait_list,
238 struct qlcnic_bc_trans, list);
239 list_del(&trans->list);
240 t_list->count--;
241 cmd.req.arg = (u32 *)trans->req_pay;
242 cmd.rsp.arg = (u32 *)trans->rsp_pay;
243 qlcnic_free_mbx_args(&cmd);
244 qlcnic_sriov_cleanup_transaction(trans);
245 }
246
247 spin_unlock_irqrestore(&t_list->lock, flags);
248 }
249
250 void __qlcnic_sriov_cleanup(struct qlcnic_adapter *adapter)
251 {
252 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
253 struct qlcnic_back_channel *bc = &sriov->bc;
254 struct qlcnic_vf_info *vf;
255 int i;
256
257 if (!qlcnic_sriov_enable_check(adapter))
258 return;
259
260 qlcnic_sriov_cleanup_async_list(bc);
261 destroy_workqueue(bc->bc_async_wq);
262
263 for (i = 0; i < sriov->num_vfs; i++) {
264 vf = &sriov->vf_info[i];
265 qlcnic_sriov_cleanup_list(&vf->rcv_pend);
266 cancel_work_sync(&vf->trans_work);
267 qlcnic_sriov_cleanup_list(&vf->rcv_act);
268 }
269
270 destroy_workqueue(bc->bc_trans_wq);
271
272 for (i = 0; i < sriov->num_vfs; i++)
273 kfree(sriov->vf_info[i].vp);
274
275 kfree(sriov->vf_info);
276 kfree(adapter->ahw->sriov);
277 }
278
279 static void qlcnic_sriov_vf_cleanup(struct qlcnic_adapter *adapter)
280 {
281 qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM);
282 qlcnic_sriov_cfg_bc_intr(adapter, 0);
283 __qlcnic_sriov_cleanup(adapter);
284 }
285
286 void qlcnic_sriov_cleanup(struct qlcnic_adapter *adapter)
287 {
288 if (!test_bit(__QLCNIC_SRIOV_ENABLE, &adapter->state))
289 return;
290
291 qlcnic_sriov_free_vlans(adapter);
292
293 if (qlcnic_sriov_pf_check(adapter))
294 qlcnic_sriov_pf_cleanup(adapter);
295
296 if (qlcnic_sriov_vf_check(adapter))
297 qlcnic_sriov_vf_cleanup(adapter);
298 }
299
300 static int qlcnic_sriov_post_bc_msg(struct qlcnic_adapter *adapter, u32 *hdr,
301 u32 *pay, u8 pci_func, u8 size)
302 {
303 struct qlcnic_hardware_context *ahw = adapter->ahw;
304 struct qlcnic_mailbox *mbx = ahw->mailbox;
305 struct qlcnic_cmd_args cmd;
306 unsigned long timeout;
307 int err;
308
309 memset(&cmd, 0, sizeof(struct qlcnic_cmd_args));
310 cmd.hdr = hdr;
311 cmd.pay = pay;
312 cmd.pay_size = size;
313 cmd.func_num = pci_func;
314 cmd.op_type = QLC_83XX_MBX_POST_BC_OP;
315 cmd.cmd_op = ((struct qlcnic_bc_hdr *)hdr)->cmd_op;
316
317 err = mbx->ops->enqueue_cmd(adapter, &cmd, &timeout);
318 if (err) {
319 dev_err(&adapter->pdev->dev,
320 "%s: Mailbox not available, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
321 __func__, cmd.cmd_op, cmd.type, ahw->pci_func,
322 ahw->op_mode);
323 return err;
324 }
325
326 if (!wait_for_completion_timeout(&cmd.completion, timeout)) {
327 dev_err(&adapter->pdev->dev,
328 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
329 __func__, cmd.cmd_op, cmd.type, ahw->pci_func,
330 ahw->op_mode);
331 flush_workqueue(mbx->work_q);
332 }
333
334 return cmd.rsp_opcode;
335 }
336
337 static void qlcnic_sriov_vf_cfg_buff_desc(struct qlcnic_adapter *adapter)
338 {
339 adapter->num_rxd = QLC_DEFAULT_RCV_DESCRIPTORS_SRIOV_VF;
340 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G;
341 adapter->num_jumbo_rxd = QLC_DEFAULT_JUMBO_RCV_DESCRIPTORS_SRIOV_VF;
342 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
343 adapter->num_txd = MAX_CMD_DESCRIPTORS;
344 adapter->max_rds_rings = MAX_RDS_RINGS;
345 }
346
347 int qlcnic_sriov_get_vf_vport_info(struct qlcnic_adapter *adapter,
348 struct qlcnic_info *npar_info, u16 vport_id)
349 {
350 struct device *dev = &adapter->pdev->dev;
351 struct qlcnic_cmd_args cmd;
352 int err;
353 u32 status;
354
355 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
356 if (err)
357 return err;
358
359 cmd.req.arg[1] = vport_id << 16 | 0x1;
360 err = qlcnic_issue_cmd(adapter, &cmd);
361 if (err) {
362 dev_err(&adapter->pdev->dev,
363 "Failed to get vport info, err=%d\n", err);
364 qlcnic_free_mbx_args(&cmd);
365 return err;
366 }
367
368 status = cmd.rsp.arg[2] & 0xffff;
369 if (status & BIT_0)
370 npar_info->min_tx_bw = MSW(cmd.rsp.arg[2]);
371 if (status & BIT_1)
372 npar_info->max_tx_bw = LSW(cmd.rsp.arg[3]);
373 if (status & BIT_2)
374 npar_info->max_tx_ques = MSW(cmd.rsp.arg[3]);
375 if (status & BIT_3)
376 npar_info->max_tx_mac_filters = LSW(cmd.rsp.arg[4]);
377 if (status & BIT_4)
378 npar_info->max_rx_mcast_mac_filters = MSW(cmd.rsp.arg[4]);
379 if (status & BIT_5)
380 npar_info->max_rx_ucast_mac_filters = LSW(cmd.rsp.arg[5]);
381 if (status & BIT_6)
382 npar_info->max_rx_ip_addr = MSW(cmd.rsp.arg[5]);
383 if (status & BIT_7)
384 npar_info->max_rx_lro_flow = LSW(cmd.rsp.arg[6]);
385 if (status & BIT_8)
386 npar_info->max_rx_status_rings = MSW(cmd.rsp.arg[6]);
387 if (status & BIT_9)
388 npar_info->max_rx_buf_rings = LSW(cmd.rsp.arg[7]);
389
390 npar_info->max_rx_ques = MSW(cmd.rsp.arg[7]);
391 npar_info->max_tx_vlan_keys = LSW(cmd.rsp.arg[8]);
392 npar_info->max_local_ipv6_addrs = MSW(cmd.rsp.arg[8]);
393 npar_info->max_remote_ipv6_addrs = LSW(cmd.rsp.arg[9]);
394
395 dev_info(dev, "\n\tmin_tx_bw: %d, max_tx_bw: %d max_tx_ques: %d,\n"
396 "\tmax_tx_mac_filters: %d max_rx_mcast_mac_filters: %d,\n"
397 "\tmax_rx_ucast_mac_filters: 0x%x, max_rx_ip_addr: %d,\n"
398 "\tmax_rx_lro_flow: %d max_rx_status_rings: %d,\n"
399 "\tmax_rx_buf_rings: %d, max_rx_ques: %d, max_tx_vlan_keys %d\n"
400 "\tlocal_ipv6_addr: %d, remote_ipv6_addr: %d\n",
401 npar_info->min_tx_bw, npar_info->max_tx_bw,
402 npar_info->max_tx_ques, npar_info->max_tx_mac_filters,
403 npar_info->max_rx_mcast_mac_filters,
404 npar_info->max_rx_ucast_mac_filters, npar_info->max_rx_ip_addr,
405 npar_info->max_rx_lro_flow, npar_info->max_rx_status_rings,
406 npar_info->max_rx_buf_rings, npar_info->max_rx_ques,
407 npar_info->max_tx_vlan_keys, npar_info->max_local_ipv6_addrs,
408 npar_info->max_remote_ipv6_addrs);
409
410 qlcnic_free_mbx_args(&cmd);
411 return err;
412 }
413
414 static int qlcnic_sriov_set_pvid_mode(struct qlcnic_adapter *adapter,
415 struct qlcnic_cmd_args *cmd)
416 {
417 adapter->rx_pvid = MSW(cmd->rsp.arg[1]) & 0xffff;
418 adapter->flags &= ~QLCNIC_TAGGING_ENABLED;
419 return 0;
420 }
421
422 static int qlcnic_sriov_set_guest_vlan_mode(struct qlcnic_adapter *adapter,
423 struct qlcnic_cmd_args *cmd)
424 {
425 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
426 int i, num_vlans;
427 u16 *vlans;
428
429 if (sriov->allowed_vlans)
430 return 0;
431
432 sriov->any_vlan = cmd->rsp.arg[2] & 0xf;
433 sriov->num_allowed_vlans = cmd->rsp.arg[2] >> 16;
434 dev_info(&adapter->pdev->dev, "Number of allowed Guest VLANs = %d\n",
435 sriov->num_allowed_vlans);
436
437 qlcnic_sriov_alloc_vlans(adapter);
438
439 if (!sriov->any_vlan)
440 return 0;
441
442 num_vlans = sriov->num_allowed_vlans;
443 sriov->allowed_vlans = kzalloc(sizeof(u16) * num_vlans, GFP_KERNEL);
444 if (!sriov->allowed_vlans)
445 return -ENOMEM;
446
447 vlans = (u16 *)&cmd->rsp.arg[3];
448 for (i = 0; i < num_vlans; i++)
449 sriov->allowed_vlans[i] = vlans[i];
450
451 return 0;
452 }
453
454 static int qlcnic_sriov_get_vf_acl(struct qlcnic_adapter *adapter)
455 {
456 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
457 struct qlcnic_cmd_args cmd;
458 int ret = 0;
459
460 ret = qlcnic_sriov_alloc_bc_mbx_args(&cmd, QLCNIC_BC_CMD_GET_ACL);
461 if (ret)
462 return ret;
463
464 ret = qlcnic_issue_cmd(adapter, &cmd);
465 if (ret) {
466 dev_err(&adapter->pdev->dev, "Failed to get ACL, err=%d\n",
467 ret);
468 } else {
469 sriov->vlan_mode = cmd.rsp.arg[1] & 0x3;
470 switch (sriov->vlan_mode) {
471 case QLC_GUEST_VLAN_MODE:
472 ret = qlcnic_sriov_set_guest_vlan_mode(adapter, &cmd);
473 break;
474 case QLC_PVID_MODE:
475 ret = qlcnic_sriov_set_pvid_mode(adapter, &cmd);
476 break;
477 }
478 }
479
480 qlcnic_free_mbx_args(&cmd);
481 return ret;
482 }
483
484 static int qlcnic_sriov_vf_init_driver(struct qlcnic_adapter *adapter)
485 {
486 struct qlcnic_hardware_context *ahw = adapter->ahw;
487 struct qlcnic_info nic_info;
488 int err;
489
490 err = qlcnic_sriov_get_vf_vport_info(adapter, &nic_info, 0);
491 if (err)
492 return err;
493
494 ahw->max_mc_count = nic_info.max_rx_mcast_mac_filters;
495
496 err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func);
497 if (err)
498 return -EIO;
499
500 if (qlcnic_83xx_get_port_info(adapter))
501 return -EIO;
502
503 qlcnic_sriov_vf_cfg_buff_desc(adapter);
504 adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
505 dev_info(&adapter->pdev->dev, "HAL Version: %d\n",
506 adapter->ahw->fw_hal_version);
507
508 ahw->physical_port = (u8) nic_info.phys_port;
509 ahw->switch_mode = nic_info.switch_mode;
510 ahw->max_mtu = nic_info.max_mtu;
511 ahw->op_mode = nic_info.op_mode;
512 ahw->capabilities = nic_info.capabilities;
513 return 0;
514 }
515
516 static int qlcnic_sriov_setup_vf(struct qlcnic_adapter *adapter,
517 int pci_using_dac)
518 {
519 int err;
520
521 adapter->flags |= QLCNIC_VLAN_FILTERING;
522 adapter->ahw->total_nic_func = 1;
523 INIT_LIST_HEAD(&adapter->vf_mc_list);
524 if (!qlcnic_use_msi_x && !!qlcnic_use_msi)
525 dev_warn(&adapter->pdev->dev,
526 "Device does not support MSI interrupts\n");
527
528 /* compute and set default and max tx/sds rings */
529 qlcnic_set_tx_ring_count(adapter, QLCNIC_SINGLE_RING);
530 qlcnic_set_sds_ring_count(adapter, QLCNIC_SINGLE_RING);
531
532 err = qlcnic_setup_intr(adapter);
533 if (err) {
534 dev_err(&adapter->pdev->dev, "Failed to setup interrupt\n");
535 goto err_out_disable_msi;
536 }
537
538 err = qlcnic_83xx_setup_mbx_intr(adapter);
539 if (err)
540 goto err_out_disable_msi;
541
542 err = qlcnic_sriov_init(adapter, 1);
543 if (err)
544 goto err_out_disable_mbx_intr;
545
546 err = qlcnic_sriov_cfg_bc_intr(adapter, 1);
547 if (err)
548 goto err_out_cleanup_sriov;
549
550 err = qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_INIT);
551 if (err)
552 goto err_out_disable_bc_intr;
553
554 err = qlcnic_sriov_vf_init_driver(adapter);
555 if (err)
556 goto err_out_send_channel_term;
557
558 err = qlcnic_sriov_get_vf_acl(adapter);
559 if (err)
560 goto err_out_send_channel_term;
561
562 err = qlcnic_setup_netdev(adapter, adapter->netdev, pci_using_dac);
563 if (err)
564 goto err_out_send_channel_term;
565
566 pci_set_drvdata(adapter->pdev, adapter);
567 dev_info(&adapter->pdev->dev, "%s: XGbE port initialized\n",
568 adapter->netdev->name);
569
570 qlcnic_schedule_work(adapter, qlcnic_sriov_vf_poll_dev_state,
571 adapter->ahw->idc.delay);
572 return 0;
573
574 err_out_send_channel_term:
575 qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM);
576
577 err_out_disable_bc_intr:
578 qlcnic_sriov_cfg_bc_intr(adapter, 0);
579
580 err_out_cleanup_sriov:
581 __qlcnic_sriov_cleanup(adapter);
582
583 err_out_disable_mbx_intr:
584 qlcnic_83xx_free_mbx_intr(adapter);
585
586 err_out_disable_msi:
587 qlcnic_teardown_intr(adapter);
588 return err;
589 }
590
591 static int qlcnic_sriov_check_dev_ready(struct qlcnic_adapter *adapter)
592 {
593 u32 state;
594
595 do {
596 msleep(20);
597 if (++adapter->fw_fail_cnt > QLC_BC_CMD_MAX_RETRY_CNT)
598 return -EIO;
599 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
600 } while (state != QLC_83XX_IDC_DEV_READY);
601
602 return 0;
603 }
604
605 int qlcnic_sriov_vf_init(struct qlcnic_adapter *adapter, int pci_using_dac)
606 {
607 struct qlcnic_hardware_context *ahw = adapter->ahw;
608 int err;
609
610 set_bit(QLC_83XX_MODULE_LOADED, &ahw->idc.status);
611 ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
612 ahw->reset_context = 0;
613 adapter->fw_fail_cnt = 0;
614 ahw->msix_supported = 1;
615 adapter->need_fw_reset = 0;
616 adapter->flags |= QLCNIC_TX_INTR_SHARED;
617
618 err = qlcnic_sriov_check_dev_ready(adapter);
619 if (err)
620 return err;
621
622 err = qlcnic_sriov_setup_vf(adapter, pci_using_dac);
623 if (err)
624 return err;
625
626 if (qlcnic_read_mac_addr(adapter))
627 dev_warn(&adapter->pdev->dev, "failed to read mac addr\n");
628
629 INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work);
630
631 clear_bit(__QLCNIC_RESETTING, &adapter->state);
632 return 0;
633 }
634
635 void qlcnic_sriov_vf_set_ops(struct qlcnic_adapter *adapter)
636 {
637 struct qlcnic_hardware_context *ahw = adapter->ahw;
638
639 ahw->op_mode = QLCNIC_SRIOV_VF_FUNC;
640 dev_info(&adapter->pdev->dev,
641 "HAL Version: %d Non Privileged SRIOV function\n",
642 ahw->fw_hal_version);
643 adapter->nic_ops = &qlcnic_sriov_vf_ops;
644 set_bit(__QLCNIC_SRIOV_ENABLE, &adapter->state);
645 return;
646 }
647
648 void qlcnic_sriov_vf_register_map(struct qlcnic_hardware_context *ahw)
649 {
650 ahw->hw_ops = &qlcnic_sriov_vf_hw_ops;
651 ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl;
652 ahw->ext_reg_tbl = (u32 *)qlcnic_83xx_ext_reg_tbl;
653 }
654
655 static u32 qlcnic_sriov_get_bc_paysize(u32 real_pay_size, u8 curr_frag)
656 {
657 u32 pay_size;
658
659 pay_size = real_pay_size / ((curr_frag + 1) * QLC_BC_PAYLOAD_SZ);
660
661 if (pay_size)
662 pay_size = QLC_BC_PAYLOAD_SZ;
663 else
664 pay_size = real_pay_size % QLC_BC_PAYLOAD_SZ;
665
666 return pay_size;
667 }
668
669 int qlcnic_sriov_func_to_index(struct qlcnic_adapter *adapter, u8 pci_func)
670 {
671 struct qlcnic_vf_info *vf_info = adapter->ahw->sriov->vf_info;
672 u8 i;
673
674 if (qlcnic_sriov_vf_check(adapter))
675 return 0;
676
677 for (i = 0; i < adapter->ahw->sriov->num_vfs; i++) {
678 if (vf_info[i].pci_func == pci_func)
679 return i;
680 }
681
682 return -EINVAL;
683 }
684
685 static inline int qlcnic_sriov_alloc_bc_trans(struct qlcnic_bc_trans **trans)
686 {
687 *trans = kzalloc(sizeof(struct qlcnic_bc_trans), GFP_ATOMIC);
688 if (!*trans)
689 return -ENOMEM;
690
691 init_completion(&(*trans)->resp_cmpl);
692 return 0;
693 }
694
695 static inline int qlcnic_sriov_alloc_bc_msg(struct qlcnic_bc_hdr **hdr,
696 u32 size)
697 {
698 *hdr = kzalloc(sizeof(struct qlcnic_bc_hdr) * size, GFP_ATOMIC);
699 if (!*hdr)
700 return -ENOMEM;
701
702 return 0;
703 }
704
705 static int qlcnic_sriov_alloc_bc_mbx_args(struct qlcnic_cmd_args *mbx, u32 type)
706 {
707 const struct qlcnic_mailbox_metadata *mbx_tbl;
708 int i, size;
709
710 mbx_tbl = qlcnic_sriov_bc_mbx_tbl;
711 size = ARRAY_SIZE(qlcnic_sriov_bc_mbx_tbl);
712
713 for (i = 0; i < size; i++) {
714 if (type == mbx_tbl[i].cmd) {
715 mbx->op_type = QLC_BC_CMD;
716 mbx->req.num = mbx_tbl[i].in_args;
717 mbx->rsp.num = mbx_tbl[i].out_args;
718 mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
719 GFP_ATOMIC);
720 if (!mbx->req.arg)
721 return -ENOMEM;
722 mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
723 GFP_ATOMIC);
724 if (!mbx->rsp.arg) {
725 kfree(mbx->req.arg);
726 mbx->req.arg = NULL;
727 return -ENOMEM;
728 }
729 memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
730 memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
731 mbx->req.arg[0] = (type | (mbx->req.num << 16) |
732 (3 << 29));
733 mbx->rsp.arg[0] = (type & 0xffff) | mbx->rsp.num << 16;
734 return 0;
735 }
736 }
737 return -EINVAL;
738 }
739
740 static int qlcnic_sriov_prepare_bc_hdr(struct qlcnic_bc_trans *trans,
741 struct qlcnic_cmd_args *cmd,
742 u16 seq, u8 msg_type)
743 {
744 struct qlcnic_bc_hdr *hdr;
745 int i;
746 u32 num_regs, bc_pay_sz;
747 u16 remainder;
748 u8 cmd_op, num_frags, t_num_frags;
749
750 bc_pay_sz = QLC_BC_PAYLOAD_SZ;
751 if (msg_type == QLC_BC_COMMAND) {
752 trans->req_pay = (struct qlcnic_bc_payload *)cmd->req.arg;
753 trans->rsp_pay = (struct qlcnic_bc_payload *)cmd->rsp.arg;
754 num_regs = cmd->req.num;
755 trans->req_pay_size = (num_regs * 4);
756 num_regs = cmd->rsp.num;
757 trans->rsp_pay_size = (num_regs * 4);
758 cmd_op = cmd->req.arg[0] & 0xff;
759 remainder = (trans->req_pay_size) % (bc_pay_sz);
760 num_frags = (trans->req_pay_size) / (bc_pay_sz);
761 if (remainder)
762 num_frags++;
763 t_num_frags = num_frags;
764 if (qlcnic_sriov_alloc_bc_msg(&trans->req_hdr, num_frags))
765 return -ENOMEM;
766 remainder = (trans->rsp_pay_size) % (bc_pay_sz);
767 num_frags = (trans->rsp_pay_size) / (bc_pay_sz);
768 if (remainder)
769 num_frags++;
770 if (qlcnic_sriov_alloc_bc_msg(&trans->rsp_hdr, num_frags))
771 return -ENOMEM;
772 num_frags = t_num_frags;
773 hdr = trans->req_hdr;
774 } else {
775 cmd->req.arg = (u32 *)trans->req_pay;
776 cmd->rsp.arg = (u32 *)trans->rsp_pay;
777 cmd_op = cmd->req.arg[0] & 0xff;
778 cmd->cmd_op = cmd_op;
779 remainder = (trans->rsp_pay_size) % (bc_pay_sz);
780 num_frags = (trans->rsp_pay_size) / (bc_pay_sz);
781 if (remainder)
782 num_frags++;
783 cmd->req.num = trans->req_pay_size / 4;
784 cmd->rsp.num = trans->rsp_pay_size / 4;
785 hdr = trans->rsp_hdr;
786 cmd->op_type = trans->req_hdr->op_type;
787 }
788
789 trans->trans_id = seq;
790 trans->cmd_id = cmd_op;
791 for (i = 0; i < num_frags; i++) {
792 hdr[i].version = 2;
793 hdr[i].msg_type = msg_type;
794 hdr[i].op_type = cmd->op_type;
795 hdr[i].num_cmds = 1;
796 hdr[i].num_frags = num_frags;
797 hdr[i].frag_num = i + 1;
798 hdr[i].cmd_op = cmd_op;
799 hdr[i].seq_id = seq;
800 }
801 return 0;
802 }
803
804 static void qlcnic_sriov_cleanup_transaction(struct qlcnic_bc_trans *trans)
805 {
806 if (!trans)
807 return;
808 kfree(trans->req_hdr);
809 kfree(trans->rsp_hdr);
810 kfree(trans);
811 }
812
813 static int qlcnic_sriov_clear_trans(struct qlcnic_vf_info *vf,
814 struct qlcnic_bc_trans *trans, u8 type)
815 {
816 struct qlcnic_trans_list *t_list;
817 unsigned long flags;
818 int ret = 0;
819
820 if (type == QLC_BC_RESPONSE) {
821 t_list = &vf->rcv_act;
822 spin_lock_irqsave(&t_list->lock, flags);
823 t_list->count--;
824 list_del(&trans->list);
825 if (t_list->count > 0)
826 ret = 1;
827 spin_unlock_irqrestore(&t_list->lock, flags);
828 }
829 if (type == QLC_BC_COMMAND) {
830 while (test_and_set_bit(QLC_BC_VF_SEND, &vf->state))
831 msleep(100);
832 vf->send_cmd = NULL;
833 clear_bit(QLC_BC_VF_SEND, &vf->state);
834 }
835 return ret;
836 }
837
838 static void qlcnic_sriov_schedule_bc_cmd(struct qlcnic_sriov *sriov,
839 struct qlcnic_vf_info *vf,
840 work_func_t func)
841 {
842 if (test_bit(QLC_BC_VF_FLR, &vf->state) ||
843 vf->adapter->need_fw_reset)
844 return;
845
846 queue_work(sriov->bc.bc_trans_wq, &vf->trans_work);
847 }
848
849 static inline void qlcnic_sriov_wait_for_resp(struct qlcnic_bc_trans *trans)
850 {
851 struct completion *cmpl = &trans->resp_cmpl;
852
853 if (wait_for_completion_timeout(cmpl, QLC_MBOX_RESP_TIMEOUT))
854 trans->trans_state = QLC_END;
855 else
856 trans->trans_state = QLC_ABORT;
857
858 return;
859 }
860
861 static void qlcnic_sriov_handle_multi_frags(struct qlcnic_bc_trans *trans,
862 u8 type)
863 {
864 if (type == QLC_BC_RESPONSE) {
865 trans->curr_rsp_frag++;
866 if (trans->curr_rsp_frag < trans->rsp_hdr->num_frags)
867 trans->trans_state = QLC_INIT;
868 else
869 trans->trans_state = QLC_END;
870 } else {
871 trans->curr_req_frag++;
872 if (trans->curr_req_frag < trans->req_hdr->num_frags)
873 trans->trans_state = QLC_INIT;
874 else
875 trans->trans_state = QLC_WAIT_FOR_RESP;
876 }
877 }
878
879 static void qlcnic_sriov_wait_for_channel_free(struct qlcnic_bc_trans *trans,
880 u8 type)
881 {
882 struct qlcnic_vf_info *vf = trans->vf;
883 struct completion *cmpl = &vf->ch_free_cmpl;
884
885 if (!wait_for_completion_timeout(cmpl, QLC_MBOX_CH_FREE_TIMEOUT)) {
886 trans->trans_state = QLC_ABORT;
887 return;
888 }
889
890 clear_bit(QLC_BC_VF_CHANNEL, &vf->state);
891 qlcnic_sriov_handle_multi_frags(trans, type);
892 }
893
894 static void qlcnic_sriov_pull_bc_msg(struct qlcnic_adapter *adapter,
895 u32 *hdr, u32 *pay, u32 size)
896 {
897 struct qlcnic_hardware_context *ahw = adapter->ahw;
898 u32 fw_mbx;
899 u8 i, max = 2, hdr_size, j;
900
901 hdr_size = (sizeof(struct qlcnic_bc_hdr) / sizeof(u32));
902 max = (size / sizeof(u32)) + hdr_size;
903
904 fw_mbx = readl(QLCNIC_MBX_FW(ahw, 0));
905 for (i = 2, j = 0; j < hdr_size; i++, j++)
906 *(hdr++) = readl(QLCNIC_MBX_FW(ahw, i));
907 for (; j < max; i++, j++)
908 *(pay++) = readl(QLCNIC_MBX_FW(ahw, i));
909 }
910
911 static int __qlcnic_sriov_issue_bc_post(struct qlcnic_vf_info *vf)
912 {
913 int ret = -EBUSY;
914 u32 timeout = 10000;
915
916 do {
917 if (!test_and_set_bit(QLC_BC_VF_CHANNEL, &vf->state)) {
918 ret = 0;
919 break;
920 }
921 mdelay(1);
922 } while (--timeout);
923
924 return ret;
925 }
926
927 static int qlcnic_sriov_issue_bc_post(struct qlcnic_bc_trans *trans, u8 type)
928 {
929 struct qlcnic_vf_info *vf = trans->vf;
930 u32 pay_size, hdr_size;
931 u32 *hdr, *pay;
932 int ret;
933 u8 pci_func = trans->func_id;
934
935 if (__qlcnic_sriov_issue_bc_post(vf))
936 return -EBUSY;
937
938 if (type == QLC_BC_COMMAND) {
939 hdr = (u32 *)(trans->req_hdr + trans->curr_req_frag);
940 pay = (u32 *)(trans->req_pay + trans->curr_req_frag);
941 hdr_size = (sizeof(struct qlcnic_bc_hdr) / sizeof(u32));
942 pay_size = qlcnic_sriov_get_bc_paysize(trans->req_pay_size,
943 trans->curr_req_frag);
944 pay_size = (pay_size / sizeof(u32));
945 } else {
946 hdr = (u32 *)(trans->rsp_hdr + trans->curr_rsp_frag);
947 pay = (u32 *)(trans->rsp_pay + trans->curr_rsp_frag);
948 hdr_size = (sizeof(struct qlcnic_bc_hdr) / sizeof(u32));
949 pay_size = qlcnic_sriov_get_bc_paysize(trans->rsp_pay_size,
950 trans->curr_rsp_frag);
951 pay_size = (pay_size / sizeof(u32));
952 }
953
954 ret = qlcnic_sriov_post_bc_msg(vf->adapter, hdr, pay,
955 pci_func, pay_size);
956 return ret;
957 }
958
959 static int __qlcnic_sriov_send_bc_msg(struct qlcnic_bc_trans *trans,
960 struct qlcnic_vf_info *vf, u8 type)
961 {
962 bool flag = true;
963 int err = -EIO;
964
965 while (flag) {
966 if (test_bit(QLC_BC_VF_FLR, &vf->state) ||
967 vf->adapter->need_fw_reset)
968 trans->trans_state = QLC_ABORT;
969
970 switch (trans->trans_state) {
971 case QLC_INIT:
972 trans->trans_state = QLC_WAIT_FOR_CHANNEL_FREE;
973 if (qlcnic_sriov_issue_bc_post(trans, type))
974 trans->trans_state = QLC_ABORT;
975 break;
976 case QLC_WAIT_FOR_CHANNEL_FREE:
977 qlcnic_sriov_wait_for_channel_free(trans, type);
978 break;
979 case QLC_WAIT_FOR_RESP:
980 qlcnic_sriov_wait_for_resp(trans);
981 break;
982 case QLC_END:
983 err = 0;
984 flag = false;
985 break;
986 case QLC_ABORT:
987 err = -EIO;
988 flag = false;
989 clear_bit(QLC_BC_VF_CHANNEL, &vf->state);
990 break;
991 default:
992 err = -EIO;
993 flag = false;
994 }
995 }
996 return err;
997 }
998
999 static int qlcnic_sriov_send_bc_cmd(struct qlcnic_adapter *adapter,
1000 struct qlcnic_bc_trans *trans, int pci_func)
1001 {
1002 struct qlcnic_vf_info *vf;
1003 int err, index = qlcnic_sriov_func_to_index(adapter, pci_func);
1004
1005 if (index < 0)
1006 return -EIO;
1007
1008 vf = &adapter->ahw->sriov->vf_info[index];
1009 trans->vf = vf;
1010 trans->func_id = pci_func;
1011
1012 if (!test_bit(QLC_BC_VF_STATE, &vf->state)) {
1013 if (qlcnic_sriov_pf_check(adapter))
1014 return -EIO;
1015 if (qlcnic_sriov_vf_check(adapter) &&
1016 trans->cmd_id != QLCNIC_BC_CMD_CHANNEL_INIT)
1017 return -EIO;
1018 }
1019
1020 mutex_lock(&vf->send_cmd_lock);
1021 vf->send_cmd = trans;
1022 err = __qlcnic_sriov_send_bc_msg(trans, vf, QLC_BC_COMMAND);
1023 qlcnic_sriov_clear_trans(vf, trans, QLC_BC_COMMAND);
1024 mutex_unlock(&vf->send_cmd_lock);
1025 return err;
1026 }
1027
1028 static void __qlcnic_sriov_process_bc_cmd(struct qlcnic_adapter *adapter,
1029 struct qlcnic_bc_trans *trans,
1030 struct qlcnic_cmd_args *cmd)
1031 {
1032 #ifdef CONFIG_QLCNIC_SRIOV
1033 if (qlcnic_sriov_pf_check(adapter)) {
1034 qlcnic_sriov_pf_process_bc_cmd(adapter, trans, cmd);
1035 return;
1036 }
1037 #endif
1038 cmd->rsp.arg[0] |= (0x9 << 25);
1039 return;
1040 }
1041
1042 static void qlcnic_sriov_process_bc_cmd(struct work_struct *work)
1043 {
1044 struct qlcnic_vf_info *vf = container_of(work, struct qlcnic_vf_info,
1045 trans_work);
1046 struct qlcnic_bc_trans *trans = NULL;
1047 struct qlcnic_adapter *adapter = vf->adapter;
1048 struct qlcnic_cmd_args cmd;
1049 u8 req;
1050
1051 if (adapter->need_fw_reset)
1052 return;
1053
1054 if (test_bit(QLC_BC_VF_FLR, &vf->state))
1055 return;
1056
1057 memset(&cmd, 0, sizeof(struct qlcnic_cmd_args));
1058 trans = list_first_entry(&vf->rcv_act.wait_list,
1059 struct qlcnic_bc_trans, list);
1060 adapter = vf->adapter;
1061
1062 if (qlcnic_sriov_prepare_bc_hdr(trans, &cmd, trans->req_hdr->seq_id,
1063 QLC_BC_RESPONSE))
1064 goto cleanup_trans;
1065
1066 __qlcnic_sriov_process_bc_cmd(adapter, trans, &cmd);
1067 trans->trans_state = QLC_INIT;
1068 __qlcnic_sriov_send_bc_msg(trans, vf, QLC_BC_RESPONSE);
1069
1070 cleanup_trans:
1071 qlcnic_free_mbx_args(&cmd);
1072 req = qlcnic_sriov_clear_trans(vf, trans, QLC_BC_RESPONSE);
1073 qlcnic_sriov_cleanup_transaction(trans);
1074 if (req)
1075 qlcnic_sriov_schedule_bc_cmd(adapter->ahw->sriov, vf,
1076 qlcnic_sriov_process_bc_cmd);
1077 }
1078
1079 static void qlcnic_sriov_handle_bc_resp(struct qlcnic_bc_hdr *hdr,
1080 struct qlcnic_vf_info *vf)
1081 {
1082 struct qlcnic_bc_trans *trans;
1083 u32 pay_size;
1084
1085 if (test_and_set_bit(QLC_BC_VF_SEND, &vf->state))
1086 return;
1087
1088 trans = vf->send_cmd;
1089
1090 if (trans == NULL)
1091 goto clear_send;
1092
1093 if (trans->trans_id != hdr->seq_id)
1094 goto clear_send;
1095
1096 pay_size = qlcnic_sriov_get_bc_paysize(trans->rsp_pay_size,
1097 trans->curr_rsp_frag);
1098 qlcnic_sriov_pull_bc_msg(vf->adapter,
1099 (u32 *)(trans->rsp_hdr + trans->curr_rsp_frag),
1100 (u32 *)(trans->rsp_pay + trans->curr_rsp_frag),
1101 pay_size);
1102 if (++trans->curr_rsp_frag < trans->rsp_hdr->num_frags)
1103 goto clear_send;
1104
1105 complete(&trans->resp_cmpl);
1106
1107 clear_send:
1108 clear_bit(QLC_BC_VF_SEND, &vf->state);
1109 }
1110
1111 int __qlcnic_sriov_add_act_list(struct qlcnic_sriov *sriov,
1112 struct qlcnic_vf_info *vf,
1113 struct qlcnic_bc_trans *trans)
1114 {
1115 struct qlcnic_trans_list *t_list = &vf->rcv_act;
1116
1117 t_list->count++;
1118 list_add_tail(&trans->list, &t_list->wait_list);
1119 if (t_list->count == 1)
1120 qlcnic_sriov_schedule_bc_cmd(sriov, vf,
1121 qlcnic_sriov_process_bc_cmd);
1122 return 0;
1123 }
1124
1125 static int qlcnic_sriov_add_act_list(struct qlcnic_sriov *sriov,
1126 struct qlcnic_vf_info *vf,
1127 struct qlcnic_bc_trans *trans)
1128 {
1129 struct qlcnic_trans_list *t_list = &vf->rcv_act;
1130
1131 spin_lock(&t_list->lock);
1132
1133 __qlcnic_sriov_add_act_list(sriov, vf, trans);
1134
1135 spin_unlock(&t_list->lock);
1136 return 0;
1137 }
1138
1139 static void qlcnic_sriov_handle_pending_trans(struct qlcnic_sriov *sriov,
1140 struct qlcnic_vf_info *vf,
1141 struct qlcnic_bc_hdr *hdr)
1142 {
1143 struct qlcnic_bc_trans *trans = NULL;
1144 struct list_head *node;
1145 u32 pay_size, curr_frag;
1146 u8 found = 0, active = 0;
1147
1148 spin_lock(&vf->rcv_pend.lock);
1149 if (vf->rcv_pend.count > 0) {
1150 list_for_each(node, &vf->rcv_pend.wait_list) {
1151 trans = list_entry(node, struct qlcnic_bc_trans, list);
1152 if (trans->trans_id == hdr->seq_id) {
1153 found = 1;
1154 break;
1155 }
1156 }
1157 }
1158
1159 if (found) {
1160 curr_frag = trans->curr_req_frag;
1161 pay_size = qlcnic_sriov_get_bc_paysize(trans->req_pay_size,
1162 curr_frag);
1163 qlcnic_sriov_pull_bc_msg(vf->adapter,
1164 (u32 *)(trans->req_hdr + curr_frag),
1165 (u32 *)(trans->req_pay + curr_frag),
1166 pay_size);
1167 trans->curr_req_frag++;
1168 if (trans->curr_req_frag >= hdr->num_frags) {
1169 vf->rcv_pend.count--;
1170 list_del(&trans->list);
1171 active = 1;
1172 }
1173 }
1174 spin_unlock(&vf->rcv_pend.lock);
1175
1176 if (active)
1177 if (qlcnic_sriov_add_act_list(sriov, vf, trans))
1178 qlcnic_sriov_cleanup_transaction(trans);
1179
1180 return;
1181 }
1182
1183 static void qlcnic_sriov_handle_bc_cmd(struct qlcnic_sriov *sriov,
1184 struct qlcnic_bc_hdr *hdr,
1185 struct qlcnic_vf_info *vf)
1186 {
1187 struct qlcnic_bc_trans *trans;
1188 struct qlcnic_adapter *adapter = vf->adapter;
1189 struct qlcnic_cmd_args cmd;
1190 u32 pay_size;
1191 int err;
1192 u8 cmd_op;
1193
1194 if (adapter->need_fw_reset)
1195 return;
1196
1197 if (!test_bit(QLC_BC_VF_STATE, &vf->state) &&
1198 hdr->op_type != QLC_BC_CMD &&
1199 hdr->cmd_op != QLCNIC_BC_CMD_CHANNEL_INIT)
1200 return;
1201
1202 if (hdr->frag_num > 1) {
1203 qlcnic_sriov_handle_pending_trans(sriov, vf, hdr);
1204 return;
1205 }
1206
1207 memset(&cmd, 0, sizeof(struct qlcnic_cmd_args));
1208 cmd_op = hdr->cmd_op;
1209 if (qlcnic_sriov_alloc_bc_trans(&trans))
1210 return;
1211
1212 if (hdr->op_type == QLC_BC_CMD)
1213 err = qlcnic_sriov_alloc_bc_mbx_args(&cmd, cmd_op);
1214 else
1215 err = qlcnic_alloc_mbx_args(&cmd, adapter, cmd_op);
1216
1217 if (err) {
1218 qlcnic_sriov_cleanup_transaction(trans);
1219 return;
1220 }
1221
1222 cmd.op_type = hdr->op_type;
1223 if (qlcnic_sriov_prepare_bc_hdr(trans, &cmd, hdr->seq_id,
1224 QLC_BC_COMMAND)) {
1225 qlcnic_free_mbx_args(&cmd);
1226 qlcnic_sriov_cleanup_transaction(trans);
1227 return;
1228 }
1229
1230 pay_size = qlcnic_sriov_get_bc_paysize(trans->req_pay_size,
1231 trans->curr_req_frag);
1232 qlcnic_sriov_pull_bc_msg(vf->adapter,
1233 (u32 *)(trans->req_hdr + trans->curr_req_frag),
1234 (u32 *)(trans->req_pay + trans->curr_req_frag),
1235 pay_size);
1236 trans->func_id = vf->pci_func;
1237 trans->vf = vf;
1238 trans->trans_id = hdr->seq_id;
1239 trans->curr_req_frag++;
1240
1241 if (qlcnic_sriov_soft_flr_check(adapter, trans, vf))
1242 return;
1243
1244 if (trans->curr_req_frag == trans->req_hdr->num_frags) {
1245 if (qlcnic_sriov_add_act_list(sriov, vf, trans)) {
1246 qlcnic_free_mbx_args(&cmd);
1247 qlcnic_sriov_cleanup_transaction(trans);
1248 }
1249 } else {
1250 spin_lock(&vf->rcv_pend.lock);
1251 list_add_tail(&trans->list, &vf->rcv_pend.wait_list);
1252 vf->rcv_pend.count++;
1253 spin_unlock(&vf->rcv_pend.lock);
1254 }
1255 }
1256
1257 static void qlcnic_sriov_handle_msg_event(struct qlcnic_sriov *sriov,
1258 struct qlcnic_vf_info *vf)
1259 {
1260 struct qlcnic_bc_hdr hdr;
1261 u32 *ptr = (u32 *)&hdr;
1262 u8 msg_type, i;
1263
1264 for (i = 2; i < 6; i++)
1265 ptr[i - 2] = readl(QLCNIC_MBX_FW(vf->adapter->ahw, i));
1266 msg_type = hdr.msg_type;
1267
1268 switch (msg_type) {
1269 case QLC_BC_COMMAND:
1270 qlcnic_sriov_handle_bc_cmd(sriov, &hdr, vf);
1271 break;
1272 case QLC_BC_RESPONSE:
1273 qlcnic_sriov_handle_bc_resp(&hdr, vf);
1274 break;
1275 }
1276 }
1277
1278 static void qlcnic_sriov_handle_flr_event(struct qlcnic_sriov *sriov,
1279 struct qlcnic_vf_info *vf)
1280 {
1281 struct qlcnic_adapter *adapter = vf->adapter;
1282
1283 if (qlcnic_sriov_pf_check(adapter))
1284 qlcnic_sriov_pf_handle_flr(sriov, vf);
1285 else
1286 dev_err(&adapter->pdev->dev,
1287 "Invalid event to VF. VF should not get FLR event\n");
1288 }
1289
1290 void qlcnic_sriov_handle_bc_event(struct qlcnic_adapter *adapter, u32 event)
1291 {
1292 struct qlcnic_vf_info *vf;
1293 struct qlcnic_sriov *sriov;
1294 int index;
1295 u8 pci_func;
1296
1297 sriov = adapter->ahw->sriov;
1298 pci_func = qlcnic_sriov_target_func_id(event);
1299 index = qlcnic_sriov_func_to_index(adapter, pci_func);
1300
1301 if (index < 0)
1302 return;
1303
1304 vf = &sriov->vf_info[index];
1305 vf->pci_func = pci_func;
1306
1307 if (qlcnic_sriov_channel_free_check(event))
1308 complete(&vf->ch_free_cmpl);
1309
1310 if (qlcnic_sriov_flr_check(event)) {
1311 qlcnic_sriov_handle_flr_event(sriov, vf);
1312 return;
1313 }
1314
1315 if (qlcnic_sriov_bc_msg_check(event))
1316 qlcnic_sriov_handle_msg_event(sriov, vf);
1317 }
1318
1319 int qlcnic_sriov_cfg_bc_intr(struct qlcnic_adapter *adapter, u8 enable)
1320 {
1321 struct qlcnic_cmd_args cmd;
1322 int err;
1323
1324 if (!test_bit(__QLCNIC_SRIOV_ENABLE, &adapter->state))
1325 return 0;
1326
1327 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_BC_EVENT_SETUP))
1328 return -ENOMEM;
1329
1330 if (enable)
1331 cmd.req.arg[1] = (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7);
1332
1333 err = qlcnic_83xx_issue_cmd(adapter, &cmd);
1334
1335 if (err != QLCNIC_RCODE_SUCCESS) {
1336 dev_err(&adapter->pdev->dev,
1337 "Failed to %s bc events, err=%d\n",
1338 (enable ? "enable" : "disable"), err);
1339 }
1340
1341 qlcnic_free_mbx_args(&cmd);
1342 return err;
1343 }
1344
1345 static int qlcnic_sriov_retry_bc_cmd(struct qlcnic_adapter *adapter,
1346 struct qlcnic_bc_trans *trans)
1347 {
1348 u8 max = QLC_BC_CMD_MAX_RETRY_CNT;
1349 u32 state;
1350
1351 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1352 if (state == QLC_83XX_IDC_DEV_READY) {
1353 msleep(20);
1354 clear_bit(QLC_BC_VF_CHANNEL, &trans->vf->state);
1355 trans->trans_state = QLC_INIT;
1356 if (++adapter->fw_fail_cnt > max)
1357 return -EIO;
1358 else
1359 return 0;
1360 }
1361
1362 return -EIO;
1363 }
1364
1365 static int __qlcnic_sriov_issue_cmd(struct qlcnic_adapter *adapter,
1366 struct qlcnic_cmd_args *cmd)
1367 {
1368 struct qlcnic_hardware_context *ahw = adapter->ahw;
1369 struct qlcnic_mailbox *mbx = ahw->mailbox;
1370 struct device *dev = &adapter->pdev->dev;
1371 struct qlcnic_bc_trans *trans;
1372 int err;
1373 u32 rsp_data, opcode, mbx_err_code, rsp;
1374 u16 seq = ++adapter->ahw->sriov->bc.trans_counter;
1375 u8 func = ahw->pci_func;
1376
1377 rsp = qlcnic_sriov_alloc_bc_trans(&trans);
1378 if (rsp)
1379 goto free_cmd;
1380
1381 rsp = qlcnic_sriov_prepare_bc_hdr(trans, cmd, seq, QLC_BC_COMMAND);
1382 if (rsp)
1383 goto cleanup_transaction;
1384
1385 retry:
1386 if (!test_bit(QLC_83XX_MBX_READY, &mbx->status)) {
1387 rsp = -EIO;
1388 QLCDB(adapter, DRV, "MBX not Ready!(cmd 0x%x) for VF 0x%x\n",
1389 QLCNIC_MBX_RSP(cmd->req.arg[0]), func);
1390 goto err_out;
1391 }
1392
1393 err = qlcnic_sriov_send_bc_cmd(adapter, trans, func);
1394 if (err) {
1395 dev_err(dev, "MBX command 0x%x timed out for VF %d\n",
1396 (cmd->req.arg[0] & 0xffff), func);
1397 rsp = QLCNIC_RCODE_TIMEOUT;
1398
1399 /* After adapter reset PF driver may take some time to
1400 * respond to VF's request. Retry request till maximum retries.
1401 */
1402 if ((trans->req_hdr->cmd_op == QLCNIC_BC_CMD_CHANNEL_INIT) &&
1403 !qlcnic_sriov_retry_bc_cmd(adapter, trans))
1404 goto retry;
1405
1406 goto err_out;
1407 }
1408
1409 rsp_data = cmd->rsp.arg[0];
1410 mbx_err_code = QLCNIC_MBX_STATUS(rsp_data);
1411 opcode = QLCNIC_MBX_RSP(cmd->req.arg[0]);
1412
1413 if ((mbx_err_code == QLCNIC_MBX_RSP_OK) ||
1414 (mbx_err_code == QLCNIC_MBX_PORT_RSP_OK)) {
1415 rsp = QLCNIC_RCODE_SUCCESS;
1416 } else {
1417 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
1418 rsp = QLCNIC_RCODE_SUCCESS;
1419 } else {
1420 rsp = mbx_err_code;
1421 if (!rsp)
1422 rsp = 1;
1423
1424 dev_err(dev,
1425 "MBX command 0x%x failed with err:0x%x for VF %d\n",
1426 opcode, mbx_err_code, func);
1427 }
1428 }
1429
1430 err_out:
1431 if (rsp == QLCNIC_RCODE_TIMEOUT) {
1432 ahw->reset_context = 1;
1433 adapter->need_fw_reset = 1;
1434 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
1435 }
1436
1437 cleanup_transaction:
1438 qlcnic_sriov_cleanup_transaction(trans);
1439
1440 free_cmd:
1441 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
1442 qlcnic_free_mbx_args(cmd);
1443 kfree(cmd);
1444 }
1445
1446 return rsp;
1447 }
1448
1449
1450 static int qlcnic_sriov_issue_cmd(struct qlcnic_adapter *adapter,
1451 struct qlcnic_cmd_args *cmd)
1452 {
1453 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT)
1454 return qlcnic_sriov_async_issue_cmd(adapter, cmd);
1455 else
1456 return __qlcnic_sriov_issue_cmd(adapter, cmd);
1457 }
1458
1459 static int qlcnic_sriov_channel_cfg_cmd(struct qlcnic_adapter *adapter, u8 cmd_op)
1460 {
1461 struct qlcnic_cmd_args cmd;
1462 struct qlcnic_vf_info *vf = &adapter->ahw->sriov->vf_info[0];
1463 int ret;
1464
1465 if (qlcnic_sriov_alloc_bc_mbx_args(&cmd, cmd_op))
1466 return -ENOMEM;
1467
1468 ret = qlcnic_issue_cmd(adapter, &cmd);
1469 if (ret) {
1470 dev_err(&adapter->pdev->dev,
1471 "Failed bc channel %s %d\n", cmd_op ? "term" : "init",
1472 ret);
1473 goto out;
1474 }
1475
1476 cmd_op = (cmd.rsp.arg[0] & 0xff);
1477 if (cmd.rsp.arg[0] >> 25 == 2)
1478 return 2;
1479 if (cmd_op == QLCNIC_BC_CMD_CHANNEL_INIT)
1480 set_bit(QLC_BC_VF_STATE, &vf->state);
1481 else
1482 clear_bit(QLC_BC_VF_STATE, &vf->state);
1483
1484 out:
1485 qlcnic_free_mbx_args(&cmd);
1486 return ret;
1487 }
1488
1489 static void qlcnic_vf_add_mc_list(struct net_device *netdev, const u8 *mac)
1490 {
1491 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1492 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
1493 struct qlcnic_vf_info *vf;
1494 u16 vlan_id;
1495 int i;
1496
1497 vf = &adapter->ahw->sriov->vf_info[0];
1498
1499 if (!qlcnic_sriov_check_any_vlan(vf)) {
1500 qlcnic_nic_add_mac(adapter, mac, 0);
1501 } else {
1502 spin_lock(&vf->vlan_list_lock);
1503 for (i = 0; i < sriov->num_allowed_vlans; i++) {
1504 vlan_id = vf->sriov_vlans[i];
1505 if (vlan_id)
1506 qlcnic_nic_add_mac(adapter, mac, vlan_id);
1507 }
1508 spin_unlock(&vf->vlan_list_lock);
1509 if (qlcnic_84xx_check(adapter))
1510 qlcnic_nic_add_mac(adapter, mac, 0);
1511 }
1512 }
1513
1514 void qlcnic_sriov_cleanup_async_list(struct qlcnic_back_channel *bc)
1515 {
1516 struct list_head *head = &bc->async_list;
1517 struct qlcnic_async_work_list *entry;
1518
1519 flush_workqueue(bc->bc_async_wq);
1520 while (!list_empty(head)) {
1521 entry = list_entry(head->next, struct qlcnic_async_work_list,
1522 list);
1523 cancel_work_sync(&entry->work);
1524 list_del(&entry->list);
1525 kfree(entry);
1526 }
1527 }
1528
1529 void qlcnic_sriov_vf_set_multi(struct net_device *netdev)
1530 {
1531 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1532 struct qlcnic_hardware_context *ahw = adapter->ahw;
1533 static const u8 bcast_addr[ETH_ALEN] = {
1534 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
1535 };
1536 struct netdev_hw_addr *ha;
1537 u32 mode = VPORT_MISS_MODE_DROP;
1538
1539 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
1540 return;
1541
1542 if (netdev->flags & IFF_PROMISC) {
1543 if (!(adapter->flags & QLCNIC_PROMISC_DISABLED))
1544 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1545 } else if ((netdev->flags & IFF_ALLMULTI) ||
1546 (netdev_mc_count(netdev) > ahw->max_mc_count)) {
1547 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
1548 } else {
1549 qlcnic_vf_add_mc_list(netdev, bcast_addr);
1550 if (!netdev_mc_empty(netdev)) {
1551 netdev_for_each_mc_addr(ha, netdev)
1552 qlcnic_vf_add_mc_list(netdev, ha->addr);
1553 }
1554 }
1555
1556 /* configure unicast MAC address, if there is not sufficient space
1557 * to store all the unicast addresses then enable promiscuous mode
1558 */
1559 if (netdev_uc_count(netdev) > ahw->max_uc_count) {
1560 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1561 } else if (!netdev_uc_empty(netdev)) {
1562 netdev_for_each_uc_addr(ha, netdev)
1563 qlcnic_vf_add_mc_list(netdev, ha->addr);
1564 }
1565
1566 if (adapter->pdev->is_virtfn) {
1567 if (mode == VPORT_MISS_MODE_ACCEPT_ALL &&
1568 !adapter->fdb_mac_learn) {
1569 qlcnic_alloc_lb_filters_mem(adapter);
1570 adapter->drv_mac_learn = 1;
1571 adapter->rx_mac_learn = true;
1572 } else {
1573 adapter->drv_mac_learn = 0;
1574 adapter->rx_mac_learn = false;
1575 }
1576 }
1577
1578 qlcnic_nic_set_promisc(adapter, mode);
1579 }
1580
1581 static void qlcnic_sriov_handle_async_issue_cmd(struct work_struct *work)
1582 {
1583 struct qlcnic_async_work_list *entry;
1584 struct qlcnic_adapter *adapter;
1585 struct qlcnic_cmd_args *cmd;
1586
1587 entry = container_of(work, struct qlcnic_async_work_list, work);
1588 adapter = entry->ptr;
1589 cmd = entry->cmd;
1590 __qlcnic_sriov_issue_cmd(adapter, cmd);
1591 return;
1592 }
1593
1594 static struct qlcnic_async_work_list *
1595 qlcnic_sriov_get_free_node_async_work(struct qlcnic_back_channel *bc)
1596 {
1597 struct list_head *node;
1598 struct qlcnic_async_work_list *entry = NULL;
1599 u8 empty = 0;
1600
1601 list_for_each(node, &bc->async_list) {
1602 entry = list_entry(node, struct qlcnic_async_work_list, list);
1603 if (!work_pending(&entry->work)) {
1604 empty = 1;
1605 break;
1606 }
1607 }
1608
1609 if (!empty) {
1610 entry = kzalloc(sizeof(struct qlcnic_async_work_list),
1611 GFP_ATOMIC);
1612 if (entry == NULL)
1613 return NULL;
1614 list_add_tail(&entry->list, &bc->async_list);
1615 }
1616
1617 return entry;
1618 }
1619
1620 static void qlcnic_sriov_schedule_async_cmd(struct qlcnic_back_channel *bc,
1621 work_func_t func, void *data,
1622 struct qlcnic_cmd_args *cmd)
1623 {
1624 struct qlcnic_async_work_list *entry = NULL;
1625
1626 entry = qlcnic_sriov_get_free_node_async_work(bc);
1627 if (!entry)
1628 return;
1629
1630 entry->ptr = data;
1631 entry->cmd = cmd;
1632 INIT_WORK(&entry->work, func);
1633 queue_work(bc->bc_async_wq, &entry->work);
1634 }
1635
1636 static int qlcnic_sriov_async_issue_cmd(struct qlcnic_adapter *adapter,
1637 struct qlcnic_cmd_args *cmd)
1638 {
1639
1640 struct qlcnic_back_channel *bc = &adapter->ahw->sriov->bc;
1641
1642 if (adapter->need_fw_reset)
1643 return -EIO;
1644
1645 qlcnic_sriov_schedule_async_cmd(bc, qlcnic_sriov_handle_async_issue_cmd,
1646 adapter, cmd);
1647 return 0;
1648 }
1649
1650 static int qlcnic_sriov_vf_reinit_driver(struct qlcnic_adapter *adapter)
1651 {
1652 int err;
1653
1654 adapter->need_fw_reset = 0;
1655 qlcnic_83xx_reinit_mbx_work(adapter->ahw->mailbox);
1656 qlcnic_83xx_enable_mbx_interrupt(adapter);
1657
1658 err = qlcnic_sriov_cfg_bc_intr(adapter, 1);
1659 if (err)
1660 return err;
1661
1662 err = qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_INIT);
1663 if (err)
1664 goto err_out_cleanup_bc_intr;
1665
1666 err = qlcnic_sriov_vf_init_driver(adapter);
1667 if (err)
1668 goto err_out_term_channel;
1669
1670 return 0;
1671
1672 err_out_term_channel:
1673 qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM);
1674
1675 err_out_cleanup_bc_intr:
1676 qlcnic_sriov_cfg_bc_intr(adapter, 0);
1677 return err;
1678 }
1679
1680 static void qlcnic_sriov_vf_attach(struct qlcnic_adapter *adapter)
1681 {
1682 struct net_device *netdev = adapter->netdev;
1683
1684 if (netif_running(netdev)) {
1685 if (!qlcnic_up(adapter, netdev))
1686 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
1687 }
1688
1689 netif_device_attach(netdev);
1690 }
1691
1692 static void qlcnic_sriov_vf_detach(struct qlcnic_adapter *adapter)
1693 {
1694 struct qlcnic_hardware_context *ahw = adapter->ahw;
1695 struct qlcnic_intrpt_config *intr_tbl = ahw->intr_tbl;
1696 struct net_device *netdev = adapter->netdev;
1697 u8 i, max_ints = ahw->num_msix - 1;
1698
1699 netif_device_detach(netdev);
1700 qlcnic_83xx_detach_mailbox_work(adapter);
1701 qlcnic_83xx_disable_mbx_intr(adapter);
1702
1703 if (netif_running(netdev))
1704 qlcnic_down(adapter, netdev);
1705
1706 for (i = 0; i < max_ints; i++) {
1707 intr_tbl[i].id = i;
1708 intr_tbl[i].enabled = 0;
1709 intr_tbl[i].src = 0;
1710 }
1711 ahw->reset_context = 0;
1712 }
1713
1714 static int qlcnic_sriov_vf_handle_dev_ready(struct qlcnic_adapter *adapter)
1715 {
1716 struct qlcnic_hardware_context *ahw = adapter->ahw;
1717 struct device *dev = &adapter->pdev->dev;
1718 struct qlc_83xx_idc *idc = &ahw->idc;
1719 u8 func = ahw->pci_func;
1720 u32 state;
1721
1722 if ((idc->prev_state == QLC_83XX_IDC_DEV_NEED_RESET) ||
1723 (idc->prev_state == QLC_83XX_IDC_DEV_INIT)) {
1724 if (!qlcnic_sriov_vf_reinit_driver(adapter)) {
1725 qlcnic_sriov_vf_attach(adapter);
1726 adapter->fw_fail_cnt = 0;
1727 dev_info(dev,
1728 "%s: Reinitialization of VF 0x%x done after FW reset\n",
1729 __func__, func);
1730 } else {
1731 dev_err(dev,
1732 "%s: Reinitialization of VF 0x%x failed after FW reset\n",
1733 __func__, func);
1734 state = QLCRDX(ahw, QLC_83XX_IDC_DEV_STATE);
1735 dev_info(dev, "Current state 0x%x after FW reset\n",
1736 state);
1737 }
1738 }
1739
1740 return 0;
1741 }
1742
1743 static int qlcnic_sriov_vf_handle_context_reset(struct qlcnic_adapter *adapter)
1744 {
1745 struct qlcnic_hardware_context *ahw = adapter->ahw;
1746 struct qlcnic_mailbox *mbx = ahw->mailbox;
1747 struct device *dev = &adapter->pdev->dev;
1748 struct qlc_83xx_idc *idc = &ahw->idc;
1749 u8 func = ahw->pci_func;
1750 u32 state;
1751
1752 adapter->reset_ctx_cnt++;
1753
1754 /* Skip the context reset and check if FW is hung */
1755 if (adapter->reset_ctx_cnt < 3) {
1756 adapter->need_fw_reset = 1;
1757 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
1758 dev_info(dev,
1759 "Resetting context, wait here to check if FW is in failed state\n");
1760 return 0;
1761 }
1762
1763 /* Check if number of resets exceed the threshold.
1764 * If it exceeds the threshold just fail the VF.
1765 */
1766 if (adapter->reset_ctx_cnt > QLC_83XX_VF_RESET_FAIL_THRESH) {
1767 clear_bit(QLC_83XX_MODULE_LOADED, &idc->status);
1768 adapter->tx_timeo_cnt = 0;
1769 adapter->fw_fail_cnt = 0;
1770 adapter->reset_ctx_cnt = 0;
1771 qlcnic_sriov_vf_detach(adapter);
1772 dev_err(dev,
1773 "Device context resets have exceeded the threshold, device interface will be shutdown\n");
1774 return -EIO;
1775 }
1776
1777 dev_info(dev, "Resetting context of VF 0x%x\n", func);
1778 dev_info(dev, "%s: Context reset count %d for VF 0x%x\n",
1779 __func__, adapter->reset_ctx_cnt, func);
1780 set_bit(__QLCNIC_RESETTING, &adapter->state);
1781 adapter->need_fw_reset = 1;
1782 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
1783 qlcnic_sriov_vf_detach(adapter);
1784 adapter->need_fw_reset = 0;
1785
1786 if (!qlcnic_sriov_vf_reinit_driver(adapter)) {
1787 qlcnic_sriov_vf_attach(adapter);
1788 adapter->tx_timeo_cnt = 0;
1789 adapter->reset_ctx_cnt = 0;
1790 adapter->fw_fail_cnt = 0;
1791 dev_info(dev, "Done resetting context for VF 0x%x\n", func);
1792 } else {
1793 dev_err(dev, "%s: Reinitialization of VF 0x%x failed\n",
1794 __func__, func);
1795 state = QLCRDX(ahw, QLC_83XX_IDC_DEV_STATE);
1796 dev_info(dev, "%s: Current state 0x%x\n", __func__, state);
1797 }
1798
1799 return 0;
1800 }
1801
1802 static int qlcnic_sriov_vf_idc_ready_state(struct qlcnic_adapter *adapter)
1803 {
1804 struct qlcnic_hardware_context *ahw = adapter->ahw;
1805 int ret = 0;
1806
1807 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY)
1808 ret = qlcnic_sriov_vf_handle_dev_ready(adapter);
1809 else if (ahw->reset_context)
1810 ret = qlcnic_sriov_vf_handle_context_reset(adapter);
1811
1812 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1813 return ret;
1814 }
1815
1816 static int qlcnic_sriov_vf_idc_failed_state(struct qlcnic_adapter *adapter)
1817 {
1818 struct qlc_83xx_idc *idc = &adapter->ahw->idc;
1819
1820 dev_err(&adapter->pdev->dev, "Device is in failed state\n");
1821 if (idc->prev_state == QLC_83XX_IDC_DEV_READY)
1822 qlcnic_sriov_vf_detach(adapter);
1823
1824 clear_bit(QLC_83XX_MODULE_LOADED, &idc->status);
1825 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1826 return -EIO;
1827 }
1828
1829 static int
1830 qlcnic_sriov_vf_idc_need_quiescent_state(struct qlcnic_adapter *adapter)
1831 {
1832 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
1833 struct qlc_83xx_idc *idc = &adapter->ahw->idc;
1834
1835 dev_info(&adapter->pdev->dev, "Device is in quiescent state\n");
1836 if (idc->prev_state == QLC_83XX_IDC_DEV_READY) {
1837 set_bit(__QLCNIC_RESETTING, &adapter->state);
1838 adapter->tx_timeo_cnt = 0;
1839 adapter->reset_ctx_cnt = 0;
1840 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
1841 qlcnic_sriov_vf_detach(adapter);
1842 }
1843
1844 return 0;
1845 }
1846
1847 static int qlcnic_sriov_vf_idc_init_reset_state(struct qlcnic_adapter *adapter)
1848 {
1849 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
1850 struct qlc_83xx_idc *idc = &adapter->ahw->idc;
1851 u8 func = adapter->ahw->pci_func;
1852
1853 if (idc->prev_state == QLC_83XX_IDC_DEV_READY) {
1854 dev_err(&adapter->pdev->dev,
1855 "Firmware hang detected by VF 0x%x\n", func);
1856 set_bit(__QLCNIC_RESETTING, &adapter->state);
1857 adapter->tx_timeo_cnt = 0;
1858 adapter->reset_ctx_cnt = 0;
1859 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
1860 qlcnic_sriov_vf_detach(adapter);
1861 }
1862 return 0;
1863 }
1864
1865 static int qlcnic_sriov_vf_idc_unknown_state(struct qlcnic_adapter *adapter)
1866 {
1867 dev_err(&adapter->pdev->dev, "%s: Device in unknown state\n", __func__);
1868 return 0;
1869 }
1870
1871 static void qlcnic_sriov_vf_periodic_tasks(struct qlcnic_adapter *adapter)
1872 {
1873 if (adapter->fhash.fnum)
1874 qlcnic_prune_lb_filters(adapter);
1875 }
1876
1877 static void qlcnic_sriov_vf_poll_dev_state(struct work_struct *work)
1878 {
1879 struct qlcnic_adapter *adapter;
1880 struct qlc_83xx_idc *idc;
1881 int ret = 0;
1882
1883 adapter = container_of(work, struct qlcnic_adapter, fw_work.work);
1884 idc = &adapter->ahw->idc;
1885 idc->curr_state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1886
1887 switch (idc->curr_state) {
1888 case QLC_83XX_IDC_DEV_READY:
1889 ret = qlcnic_sriov_vf_idc_ready_state(adapter);
1890 break;
1891 case QLC_83XX_IDC_DEV_NEED_RESET:
1892 case QLC_83XX_IDC_DEV_INIT:
1893 ret = qlcnic_sriov_vf_idc_init_reset_state(adapter);
1894 break;
1895 case QLC_83XX_IDC_DEV_NEED_QUISCENT:
1896 ret = qlcnic_sriov_vf_idc_need_quiescent_state(adapter);
1897 break;
1898 case QLC_83XX_IDC_DEV_FAILED:
1899 ret = qlcnic_sriov_vf_idc_failed_state(adapter);
1900 break;
1901 case QLC_83XX_IDC_DEV_QUISCENT:
1902 break;
1903 default:
1904 ret = qlcnic_sriov_vf_idc_unknown_state(adapter);
1905 }
1906
1907 idc->prev_state = idc->curr_state;
1908 qlcnic_sriov_vf_periodic_tasks(adapter);
1909
1910 if (!ret && test_bit(QLC_83XX_MODULE_LOADED, &idc->status))
1911 qlcnic_schedule_work(adapter, qlcnic_sriov_vf_poll_dev_state,
1912 idc->delay);
1913 }
1914
1915 static void qlcnic_sriov_vf_cancel_fw_work(struct qlcnic_adapter *adapter)
1916 {
1917 while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1918 msleep(20);
1919
1920 clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1921 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1922 cancel_delayed_work_sync(&adapter->fw_work);
1923 }
1924
1925 static int qlcnic_sriov_check_vlan_id(struct qlcnic_sriov *sriov,
1926 struct qlcnic_vf_info *vf, u16 vlan_id)
1927 {
1928 int i, err = -EINVAL;
1929
1930 if (!vf->sriov_vlans)
1931 return err;
1932
1933 spin_lock_bh(&vf->vlan_list_lock);
1934
1935 for (i = 0; i < sriov->num_allowed_vlans; i++) {
1936 if (vf->sriov_vlans[i] == vlan_id) {
1937 err = 0;
1938 break;
1939 }
1940 }
1941
1942 spin_unlock_bh(&vf->vlan_list_lock);
1943 return err;
1944 }
1945
1946 static int qlcnic_sriov_validate_num_vlans(struct qlcnic_sriov *sriov,
1947 struct qlcnic_vf_info *vf)
1948 {
1949 int err = 0;
1950
1951 spin_lock_bh(&vf->vlan_list_lock);
1952
1953 if (vf->num_vlan >= sriov->num_allowed_vlans)
1954 err = -EINVAL;
1955
1956 spin_unlock_bh(&vf->vlan_list_lock);
1957 return err;
1958 }
1959
1960 static int qlcnic_sriov_validate_vlan_cfg(struct qlcnic_adapter *adapter,
1961 u16 vid, u8 enable)
1962 {
1963 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
1964 struct qlcnic_vf_info *vf;
1965 bool vlan_exist;
1966 u8 allowed = 0;
1967 int i;
1968
1969 vf = &adapter->ahw->sriov->vf_info[0];
1970 vlan_exist = qlcnic_sriov_check_any_vlan(vf);
1971 if (sriov->vlan_mode != QLC_GUEST_VLAN_MODE)
1972 return -EINVAL;
1973
1974 if (enable) {
1975 if (qlcnic_83xx_vf_check(adapter) && vlan_exist)
1976 return -EINVAL;
1977
1978 if (qlcnic_sriov_validate_num_vlans(sriov, vf))
1979 return -EINVAL;
1980
1981 if (sriov->any_vlan) {
1982 for (i = 0; i < sriov->num_allowed_vlans; i++) {
1983 if (sriov->allowed_vlans[i] == vid)
1984 allowed = 1;
1985 }
1986
1987 if (!allowed)
1988 return -EINVAL;
1989 }
1990 } else {
1991 if (!vlan_exist || qlcnic_sriov_check_vlan_id(sriov, vf, vid))
1992 return -EINVAL;
1993 }
1994
1995 return 0;
1996 }
1997
1998 static void qlcnic_sriov_vlan_operation(struct qlcnic_vf_info *vf, u16 vlan_id,
1999 enum qlcnic_vlan_operations opcode)
2000 {
2001 struct qlcnic_adapter *adapter = vf->adapter;
2002 struct qlcnic_sriov *sriov;
2003
2004 sriov = adapter->ahw->sriov;
2005
2006 if (!vf->sriov_vlans)
2007 return;
2008
2009 spin_lock_bh(&vf->vlan_list_lock);
2010
2011 switch (opcode) {
2012 case QLC_VLAN_ADD:
2013 qlcnic_sriov_add_vlan_id(sriov, vf, vlan_id);
2014 break;
2015 case QLC_VLAN_DELETE:
2016 qlcnic_sriov_del_vlan_id(sriov, vf, vlan_id);
2017 break;
2018 default:
2019 netdev_err(adapter->netdev, "Invalid VLAN operation\n");
2020 }
2021
2022 spin_unlock_bh(&vf->vlan_list_lock);
2023 return;
2024 }
2025
2026 int qlcnic_sriov_cfg_vf_guest_vlan(struct qlcnic_adapter *adapter,
2027 u16 vid, u8 enable)
2028 {
2029 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
2030 struct net_device *netdev = adapter->netdev;
2031 struct qlcnic_vf_info *vf;
2032 struct qlcnic_cmd_args cmd;
2033 int ret;
2034
2035 if (vid == 0)
2036 return 0;
2037
2038 vf = &adapter->ahw->sriov->vf_info[0];
2039 ret = qlcnic_sriov_validate_vlan_cfg(adapter, vid, enable);
2040 if (ret)
2041 return ret;
2042
2043 ret = qlcnic_sriov_alloc_bc_mbx_args(&cmd,
2044 QLCNIC_BC_CMD_CFG_GUEST_VLAN);
2045 if (ret)
2046 return ret;
2047
2048 cmd.req.arg[1] = (enable & 1) | vid << 16;
2049
2050 qlcnic_sriov_cleanup_async_list(&sriov->bc);
2051 ret = qlcnic_issue_cmd(adapter, &cmd);
2052 if (ret) {
2053 dev_err(&adapter->pdev->dev,
2054 "Failed to configure guest VLAN, err=%d\n", ret);
2055 } else {
2056 netif_addr_lock_bh(netdev);
2057 qlcnic_free_mac_list(adapter);
2058 netif_addr_unlock_bh(netdev);
2059
2060 if (enable)
2061 qlcnic_sriov_vlan_operation(vf, vid, QLC_VLAN_ADD);
2062 else
2063 qlcnic_sriov_vlan_operation(vf, vid, QLC_VLAN_DELETE);
2064
2065 netif_addr_lock_bh(netdev);
2066 qlcnic_set_multi(netdev);
2067 netif_addr_unlock_bh(netdev);
2068 }
2069
2070 qlcnic_free_mbx_args(&cmd);
2071 return ret;
2072 }
2073
2074 static void qlcnic_sriov_vf_free_mac_list(struct qlcnic_adapter *adapter)
2075 {
2076 struct list_head *head = &adapter->mac_list;
2077 struct qlcnic_mac_vlan_list *cur;
2078
2079 while (!list_empty(head)) {
2080 cur = list_entry(head->next, struct qlcnic_mac_vlan_list, list);
2081 qlcnic_sre_macaddr_change(adapter, cur->mac_addr, cur->vlan_id,
2082 QLCNIC_MAC_DEL);
2083 list_del(&cur->list);
2084 kfree(cur);
2085 }
2086 }
2087
2088
2089 static int qlcnic_sriov_vf_shutdown(struct pci_dev *pdev)
2090 {
2091 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
2092 struct net_device *netdev = adapter->netdev;
2093 int retval;
2094
2095 netif_device_detach(netdev);
2096 qlcnic_cancel_idc_work(adapter);
2097
2098 if (netif_running(netdev))
2099 qlcnic_down(adapter, netdev);
2100
2101 qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM);
2102 qlcnic_sriov_cfg_bc_intr(adapter, 0);
2103 qlcnic_83xx_disable_mbx_intr(adapter);
2104 cancel_delayed_work_sync(&adapter->idc_aen_work);
2105
2106 retval = pci_save_state(pdev);
2107 if (retval)
2108 return retval;
2109
2110 return 0;
2111 }
2112
2113 static int qlcnic_sriov_vf_resume(struct qlcnic_adapter *adapter)
2114 {
2115 struct qlc_83xx_idc *idc = &adapter->ahw->idc;
2116 struct net_device *netdev = adapter->netdev;
2117 int err;
2118
2119 set_bit(QLC_83XX_MODULE_LOADED, &idc->status);
2120 qlcnic_83xx_enable_mbx_interrupt(adapter);
2121 err = qlcnic_sriov_cfg_bc_intr(adapter, 1);
2122 if (err)
2123 return err;
2124
2125 err = qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_INIT);
2126 if (!err) {
2127 if (netif_running(netdev)) {
2128 err = qlcnic_up(adapter, netdev);
2129 if (!err)
2130 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
2131 }
2132 }
2133
2134 netif_device_attach(netdev);
2135 qlcnic_schedule_work(adapter, qlcnic_sriov_vf_poll_dev_state,
2136 idc->delay);
2137 return err;
2138 }
2139
2140 void qlcnic_sriov_alloc_vlans(struct qlcnic_adapter *adapter)
2141 {
2142 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
2143 struct qlcnic_vf_info *vf;
2144 int i;
2145
2146 for (i = 0; i < sriov->num_vfs; i++) {
2147 vf = &sriov->vf_info[i];
2148 vf->sriov_vlans = kcalloc(sriov->num_allowed_vlans,
2149 sizeof(*vf->sriov_vlans), GFP_KERNEL);
2150 }
2151 }
2152
2153 void qlcnic_sriov_free_vlans(struct qlcnic_adapter *adapter)
2154 {
2155 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
2156 struct qlcnic_vf_info *vf;
2157 int i;
2158
2159 for (i = 0; i < sriov->num_vfs; i++) {
2160 vf = &sriov->vf_info[i];
2161 kfree(vf->sriov_vlans);
2162 vf->sriov_vlans = NULL;
2163 }
2164 }
2165
2166 void qlcnic_sriov_add_vlan_id(struct qlcnic_sriov *sriov,
2167 struct qlcnic_vf_info *vf, u16 vlan_id)
2168 {
2169 int i;
2170
2171 for (i = 0; i < sriov->num_allowed_vlans; i++) {
2172 if (!vf->sriov_vlans[i]) {
2173 vf->sriov_vlans[i] = vlan_id;
2174 vf->num_vlan++;
2175 return;
2176 }
2177 }
2178 }
2179
2180 void qlcnic_sriov_del_vlan_id(struct qlcnic_sriov *sriov,
2181 struct qlcnic_vf_info *vf, u16 vlan_id)
2182 {
2183 int i;
2184
2185 for (i = 0; i < sriov->num_allowed_vlans; i++) {
2186 if (vf->sriov_vlans[i] == vlan_id) {
2187 vf->sriov_vlans[i] = 0;
2188 vf->num_vlan--;
2189 return;
2190 }
2191 }
2192 }
2193
2194 bool qlcnic_sriov_check_any_vlan(struct qlcnic_vf_info *vf)
2195 {
2196 bool err = false;
2197
2198 spin_lock_bh(&vf->vlan_list_lock);
2199
2200 if (vf->num_vlan)
2201 err = true;
2202
2203 spin_unlock_bh(&vf->vlan_list_lock);
2204 return err;
2205 }
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