drivers/net/ethernet/qualcomm/emac/emac-sgmii.c

   1 /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 /* Qualcomm Technologies, Inc. EMAC SGMII Controller driver.
  14  */
  15
  16 #include <linux/iopoll.h>
  17 #include <linux/acpi.h>
  18 #include <linux/of_device.h>
  19 #include "emac.h"
  20 #include "emac-mac.h"
  21 #include "emac-sgmii.h"
  22
  23 /* EMAC_SGMII register offsets */
  24 #define EMAC_SGMII_PHY_AUTONEG_CFG2             0x0048
  25 #define EMAC_SGMII_PHY_SPEED_CFG1               0x0074
  26 #define EMAC_SGMII_PHY_IRQ_CMD                  0x00ac
  27 #define EMAC_SGMII_PHY_INTERRUPT_CLEAR          0x00b0
  28 #define EMAC_SGMII_PHY_INTERRUPT_STATUS         0x00b8
  29
  30 #define FORCE_AN_TX_CFG                         BIT(5)
  31 #define FORCE_AN_RX_CFG                         BIT(4)
  32 #define AN_ENABLE                               BIT(0)
  33
  34 #define DUPLEX_MODE                             BIT(4)
  35 #define SPDMODE_1000                            BIT(1)
  36 #define SPDMODE_100                             BIT(0)
  37 #define SPDMODE_10                              0
  38
  39 #define IRQ_GLOBAL_CLEAR                        BIT(0)
  40
  41 #define DECODE_CODE_ERR                         BIT(7)
  42 #define DECODE_DISP_ERR                         BIT(6)
  43
  44 #define SGMII_PHY_IRQ_CLR_WAIT_TIME             10
  45
  46 #define SGMII_PHY_INTERRUPT_ERR         (DECODE_CODE_ERR | DECODE_DISP_ERR)
  47
  48 #define SERDES_START_WAIT_TIMES                 100
  49
  50 static int emac_sgmii_link_init(struct emac_adapter *adpt)
  51 {
  52         struct phy_device *phydev = adpt->phydev;
  53         struct emac_phy *phy = &adpt->phy;
  54         u32 val;
  55
  56         val = readl(phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2);
  57
  58         if (phydev->autoneg == AUTONEG_ENABLE) {
  59                 val &= ~(FORCE_AN_RX_CFG | FORCE_AN_TX_CFG);
  60                 val |= AN_ENABLE;
  61                 writel(val, phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2);
  62         } else {
  63                 u32 speed_cfg;
  64
  65                 switch (phydev->speed) {
  66                 case SPEED_10:
  67                         speed_cfg = SPDMODE_10;
  68                         break;
  69                 case SPEED_100:
  70                         speed_cfg = SPDMODE_100;
  71                         break;
  72                 case SPEED_1000:
  73                         speed_cfg = SPDMODE_1000;
  74                         break;
  75                 default:
  76                         return -EINVAL;
  77                 }
  78
  79                 if (phydev->duplex == DUPLEX_FULL)
  80                         speed_cfg |= DUPLEX_MODE;
  81
  82                 val &= ~AN_ENABLE;
  83                 writel(speed_cfg, phy->base + EMAC_SGMII_PHY_SPEED_CFG1);
  84                 writel(val, phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2);
  85         }
  86
  87         return 0;
  88 }
  89
  90 static int emac_sgmii_irq_clear(struct emac_adapter *adpt, u32 irq_bits)
  91 {
  92         struct emac_phy *phy = &adpt->phy;
  93         u32 status;
  94
  95         writel_relaxed(irq_bits, phy->base + EMAC_SGMII_PHY_INTERRUPT_CLEAR);
  96         writel_relaxed(IRQ_GLOBAL_CLEAR, phy->base + EMAC_SGMII_PHY_IRQ_CMD);
  97         /* Ensure interrupt clear command is written to HW */
  98         wmb();
  99
 100         /* After set the IRQ_GLOBAL_CLEAR bit, the status clearing must
 101          * be confirmed before clearing the bits in other registers.
 102          * It takes a few cycles for hw to clear the interrupt status.
 103          */
 104         if (readl_poll_timeout_atomic(phy->base +
 105                                       EMAC_SGMII_PHY_INTERRUPT_STATUS,
 106                                       status, !(status & irq_bits), 1,
 107                                       SGMII_PHY_IRQ_CLR_WAIT_TIME)) {
 108                 netdev_err(adpt->netdev,
 109                            "error: failed clear SGMII irq: status:0x%x bits:0x%x\n",
 110                            status, irq_bits);
 111                 return -EIO;
 112         }
 113
 114         /* Finalize clearing procedure */
 115         writel_relaxed(0, phy->base + EMAC_SGMII_PHY_IRQ_CMD);
 116         writel_relaxed(0, phy->base + EMAC_SGMII_PHY_INTERRUPT_CLEAR);
 117
 118         /* Ensure that clearing procedure finalization is written to HW */
 119         wmb();
 120
 121         return 0;
 122 }
 123
 124 static void emac_sgmii_reset_prepare(struct emac_adapter *adpt)
 125 {
 126         struct emac_phy *phy = &adpt->phy;
 127         u32 val;
 128
 129         /* Reset PHY */
 130         val = readl(phy->base + EMAC_EMAC_WRAPPER_CSR2);
 131         writel(((val & ~PHY_RESET) | PHY_RESET), phy->base +
 132                EMAC_EMAC_WRAPPER_CSR2);
 133         /* Ensure phy-reset command is written to HW before the release cmd */
 134         msleep(50);
 135         val = readl(phy->base + EMAC_EMAC_WRAPPER_CSR2);
 136         writel((val & ~PHY_RESET), phy->base + EMAC_EMAC_WRAPPER_CSR2);
 137         /* Ensure phy-reset release command is written to HW before initializing
 138          * SGMII
 139          */
 140         msleep(50);
 141 }
 142
 143 void emac_sgmii_reset(struct emac_adapter *adpt)
 144 {
 145         int ret;
 146
 147         emac_sgmii_reset_prepare(adpt);
 148
 149         ret = emac_sgmii_link_init(adpt);
 150         if (ret) {
 151                 netdev_err(adpt->netdev, "unsupported link speed\n");
 152                 return;
 153         }
 154
 155         ret = adpt->phy.initialize(adpt);
 156         if (ret)
 157                 netdev_err(adpt->netdev,
 158                            "could not reinitialize internal PHY (error=%i)\n",
 159                            ret);
 160 }
 161
 162 static int emac_sgmii_acpi_match(struct device *dev, void *data)
 163 {
 164         static const struct acpi_device_id match_table[] = {
 165                 {
 166                         .id = "QCOM8071",
 167                         .driver_data = (kernel_ulong_t)emac_sgmii_init_qdf2432,
 168                 },
 169                 {}
 170         };
 171         const struct acpi_device_id *id = acpi_match_device(match_table, dev);
 172         emac_sgmii_initialize *initialize = data;
 173
 174         if (id)
 175                 *initialize = (emac_sgmii_initialize)id->driver_data;
 176
 177         return !!id;
 178 }
 179
 180 static const struct of_device_id emac_sgmii_dt_match[] = {
 181         {
 182                 .compatible = "qcom,fsm9900-emac-sgmii",
 183                 .data = emac_sgmii_init_fsm9900,
 184         },
 185         {
 186                 .compatible = "qcom,qdf2432-emac-sgmii",
 187                 .data = emac_sgmii_init_qdf2432,
 188         },
 189         {}
 190 };
 191
 192 int emac_sgmii_config(struct platform_device *pdev, struct emac_adapter *adpt)
 193 {
 194         struct platform_device *sgmii_pdev = NULL;
 195         struct emac_phy *phy = &adpt->phy;
 196         struct resource *res;
 197         int ret;
 198
 199         if (has_acpi_companion(&pdev->dev)) {
 200                 struct device *dev;
 201
 202                 dev = device_find_child(&pdev->dev, &phy->initialize,
 203                                         emac_sgmii_acpi_match);
 204
 205                 if (!dev) {
 206                         dev_err(&pdev->dev, "cannot find internal phy node\n");
 207                         return -ENODEV;
 208                 }
 209
 210                 sgmii_pdev = to_platform_device(dev);
 211         } else {
 212                 const struct of_device_id *match;
 213                 struct device_node *np;
 214
 215                 np = of_parse_phandle(pdev->dev.of_node, "internal-phy", 0);
 216                 if (!np) {
 217                         dev_err(&pdev->dev, "missing internal-phy property\n");
 218                         return -ENODEV;
 219                 }
 220
 221                 sgmii_pdev = of_find_device_by_node(np);
 222                 if (!sgmii_pdev) {
 223                         dev_err(&pdev->dev, "invalid internal-phy property\n");
 224                         return -ENODEV;
 225                 }
 226
 227                 match = of_match_device(emac_sgmii_dt_match, &sgmii_pdev->dev);
 228                 if (!match) {
 229                         dev_err(&pdev->dev, "unrecognized internal phy node\n");
 230                         ret = -ENODEV;
 231                         goto error_put_device;
 232                 }
 233
 234                 phy->initialize = (emac_sgmii_initialize)match->data;
 235         }
 236
 237         /* Base address is the first address */
 238         res = platform_get_resource(sgmii_pdev, IORESOURCE_MEM, 0);
 239         if (!res) {
 240                 ret = -EINVAL;
 241                 goto error_put_device;
 242         }
 243
 244         phy->base = ioremap(res->start, resource_size(res));
 245         if (!phy->base) {
 246                 ret = -ENOMEM;
 247                 goto error_put_device;
 248         }
 249
 250         /* v2 SGMII has a per-lane digital digital, so parse it if it exists */
 251         res = platform_get_resource(sgmii_pdev, IORESOURCE_MEM, 1);
 252         if (res) {
 253                 phy->digital = ioremap(res->start, resource_size(res));
 254                 if (!phy->digital) {
 255                         ret = -ENOMEM;
 256                         goto error_unmap_base;
 257                 }
 258         }
 259
 260         ret = phy->initialize(adpt);
 261         if (ret)
 262                 goto error;
 263
 264         emac_sgmii_irq_clear(adpt, SGMII_PHY_INTERRUPT_ERR);
 265
 266         /* We've remapped the addresses, so we don't need the device any
 267          * more.  of_find_device_by_node() says we should release it.
 268          */
 269         put_device(&sgmii_pdev->dev);
 270
 271         return 0;
 272
 273 error:
 274         if (phy->digital)
 275                 iounmap(phy->digital);
 276 error_unmap_base:
 277         iounmap(phy->base);
 278 error_put_device:
 279         put_device(&sgmii_pdev->dev);
 280
 281         return ret;
 282 }