1 /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
13 /* Qualcomm Technologies, Inc. EMAC SGMII Controller driver.
16 #include <linux/interrupt.h>
17 #include <linux/iopoll.h>
18 #include <linux/acpi.h>
19 #include <linux/of_device.h>
22 #include "emac-sgmii.h"
24 /* EMAC_SGMII register offsets */
25 #define EMAC_SGMII_PHY_AUTONEG_CFG2 0x0048
26 #define EMAC_SGMII_PHY_SPEED_CFG1 0x0074
27 #define EMAC_SGMII_PHY_IRQ_CMD 0x00ac
28 #define EMAC_SGMII_PHY_INTERRUPT_CLEAR 0x00b0
29 #define EMAC_SGMII_PHY_INTERRUPT_MASK 0x00b4
30 #define EMAC_SGMII_PHY_INTERRUPT_STATUS 0x00b8
31 #define EMAC_SGMII_PHY_RX_CHK_STATUS 0x00d4
33 #define FORCE_AN_TX_CFG BIT(5)
34 #define FORCE_AN_RX_CFG BIT(4)
35 #define AN_ENABLE BIT(0)
37 #define DUPLEX_MODE BIT(4)
38 #define SPDMODE_1000 BIT(1)
39 #define SPDMODE_100 BIT(0)
42 #define CDR_ALIGN_DET BIT(6)
44 #define IRQ_GLOBAL_CLEAR BIT(0)
46 #define DECODE_CODE_ERR BIT(7)
47 #define DECODE_DISP_ERR BIT(6)
49 #define SGMII_PHY_IRQ_CLR_WAIT_TIME 10
51 #define SGMII_PHY_INTERRUPT_ERR (DECODE_CODE_ERR | DECODE_DISP_ERR)
52 #define SGMII_ISR_MASK (SGMII_PHY_INTERRUPT_ERR)
54 #define SERDES_START_WAIT_TIMES 100
56 /* Initialize the SGMII link between the internal and external PHYs. */
57 static void emac_sgmii_link_init(struct emac_adapter
*adpt
)
59 struct emac_sgmii
*phy
= &adpt
->phy
;
62 /* Always use autonegotiation. It works no matter how the external
65 val
= readl(phy
->base
+ EMAC_SGMII_PHY_AUTONEG_CFG2
);
66 val
&= ~(FORCE_AN_RX_CFG
| FORCE_AN_TX_CFG
);
68 writel(val
, phy
->base
+ EMAC_SGMII_PHY_AUTONEG_CFG2
);
71 static int emac_sgmii_irq_clear(struct emac_adapter
*adpt
, u32 irq_bits
)
73 struct emac_sgmii
*phy
= &adpt
->phy
;
76 writel_relaxed(irq_bits
, phy
->base
+ EMAC_SGMII_PHY_INTERRUPT_CLEAR
);
77 writel_relaxed(IRQ_GLOBAL_CLEAR
, phy
->base
+ EMAC_SGMII_PHY_IRQ_CMD
);
78 /* Ensure interrupt clear command is written to HW */
81 /* After set the IRQ_GLOBAL_CLEAR bit, the status clearing must
82 * be confirmed before clearing the bits in other registers.
83 * It takes a few cycles for hw to clear the interrupt status.
85 if (readl_poll_timeout_atomic(phy
->base
+
86 EMAC_SGMII_PHY_INTERRUPT_STATUS
,
87 status
, !(status
& irq_bits
), 1,
88 SGMII_PHY_IRQ_CLR_WAIT_TIME
)) {
89 netdev_err(adpt
->netdev
,
90 "error: failed clear SGMII irq: status:0x%x bits:0x%x\n",
95 /* Finalize clearing procedure */
96 writel_relaxed(0, phy
->base
+ EMAC_SGMII_PHY_IRQ_CMD
);
97 writel_relaxed(0, phy
->base
+ EMAC_SGMII_PHY_INTERRUPT_CLEAR
);
99 /* Ensure that clearing procedure finalization is written to HW */
105 /* The number of decode errors that triggers a reset */
106 #define DECODE_ERROR_LIMIT 2
108 static irqreturn_t
emac_sgmii_interrupt(int irq
, void *data
)
110 struct emac_adapter
*adpt
= data
;
111 struct emac_sgmii
*phy
= &adpt
->phy
;
114 status
= readl(phy
->base
+ EMAC_SGMII_PHY_INTERRUPT_STATUS
);
115 status
&= SGMII_ISR_MASK
;
119 /* If we get a decoding error and CDR is not locked, then try
120 * resetting the internal PHY. The internal PHY uses an embedded
121 * clock with Clock and Data Recovery (CDR) to recover the
124 if (status
& SGMII_PHY_INTERRUPT_ERR
) {
127 /* The SGMII is capable of recovering from some decode
128 * errors automatically. However, if we get multiple
129 * decode errors in a row, then assume that something
130 * is wrong and reset the interface.
132 count
= atomic_inc_return(&phy
->decode_error_count
);
133 if (count
== DECODE_ERROR_LIMIT
) {
134 schedule_work(&adpt
->work_thread
);
135 atomic_set(&phy
->decode_error_count
, 0);
138 /* We only care about consecutive decode errors. */
139 atomic_set(&phy
->decode_error_count
, 0);
142 if (emac_sgmii_irq_clear(adpt
, status
)) {
143 netdev_warn(adpt
->netdev
, "failed to clear SGMII interrupt\n");
144 schedule_work(&adpt
->work_thread
);
150 static void emac_sgmii_reset_prepare(struct emac_adapter
*adpt
)
152 struct emac_sgmii
*phy
= &adpt
->phy
;
156 val
= readl(phy
->base
+ EMAC_EMAC_WRAPPER_CSR2
);
157 writel(((val
& ~PHY_RESET
) | PHY_RESET
), phy
->base
+
158 EMAC_EMAC_WRAPPER_CSR2
);
159 /* Ensure phy-reset command is written to HW before the release cmd */
161 val
= readl(phy
->base
+ EMAC_EMAC_WRAPPER_CSR2
);
162 writel((val
& ~PHY_RESET
), phy
->base
+ EMAC_EMAC_WRAPPER_CSR2
);
163 /* Ensure phy-reset release command is written to HW before initializing
169 void emac_sgmii_reset(struct emac_adapter
*adpt
)
173 emac_sgmii_reset_prepare(adpt
);
174 emac_sgmii_link_init(adpt
);
176 ret
= adpt
->phy
.initialize(adpt
);
178 netdev_err(adpt
->netdev
,
179 "could not reinitialize internal PHY (error=%i)\n",
183 static int emac_sgmii_open(struct emac_adapter
*adpt
)
185 struct emac_sgmii
*sgmii
= &adpt
->phy
;
189 /* Make sure interrupts are cleared and disabled first */
190 ret
= emac_sgmii_irq_clear(adpt
, 0xff);
193 writel(0, sgmii
->base
+ EMAC_SGMII_PHY_INTERRUPT_MASK
);
195 ret
= request_irq(sgmii
->irq
, emac_sgmii_interrupt
, 0,
198 netdev_err(adpt
->netdev
,
199 "could not register handler for internal PHY\n");
207 static int emac_sgmii_close(struct emac_adapter
*adpt
)
209 struct emac_sgmii
*sgmii
= &adpt
->phy
;
211 /* Make sure interrupts are disabled */
212 writel(0, sgmii
->base
+ EMAC_SGMII_PHY_INTERRUPT_MASK
);
213 free_irq(sgmii
->irq
, adpt
);
218 /* The error interrupts are only valid after the link is up */
219 static int emac_sgmii_link_up(struct emac_adapter
*adpt
)
221 struct emac_sgmii
*sgmii
= &adpt
->phy
;
224 /* Clear and enable interrupts */
225 ret
= emac_sgmii_irq_clear(adpt
, 0xff);
229 writel(SGMII_ISR_MASK
, sgmii
->base
+ EMAC_SGMII_PHY_INTERRUPT_MASK
);
234 static int emac_sgmii_link_down(struct emac_adapter
*adpt
)
236 struct emac_sgmii
*sgmii
= &adpt
->phy
;
238 /* Disable interrupts */
239 writel(0, sgmii
->base
+ EMAC_SGMII_PHY_INTERRUPT_MASK
);
240 synchronize_irq(sgmii
->irq
);
245 static int emac_sgmii_acpi_match(struct device
*dev
, void *data
)
248 static const struct acpi_device_id match_table
[] = {
254 const struct acpi_device_id
*id
= acpi_match_device(match_table
, dev
);
255 emac_sgmii_function
*initialize
= data
;
258 acpi_handle handle
= ACPI_HANDLE(dev
);
259 unsigned long long hrv
;
262 status
= acpi_evaluate_integer(handle
, "_HRV", NULL
, &hrv
);
264 if (status
== AE_NOT_FOUND
)
265 /* Older versions of the QDF2432 ACPI tables do
266 * not have an _HRV property.
270 /* Something is wrong with the tables */
276 *initialize
= emac_sgmii_init_qdf2432
;
279 *initialize
= emac_sgmii_init_qdf2400
;
288 static const struct of_device_id emac_sgmii_dt_match
[] = {
290 .compatible
= "qcom,fsm9900-emac-sgmii",
291 .data
= emac_sgmii_init_fsm9900
,
294 .compatible
= "qcom,qdf2432-emac-sgmii",
295 .data
= emac_sgmii_init_qdf2432
,
300 /* Dummy function for systems without an internal PHY. This avoids having
301 * to check for NULL pointers before calling the functions.
303 static int emac_sgmii_dummy(struct emac_adapter
*adpt
)
308 int emac_sgmii_config(struct platform_device
*pdev
, struct emac_adapter
*adpt
)
310 struct platform_device
*sgmii_pdev
= NULL
;
311 struct emac_sgmii
*phy
= &adpt
->phy
;
312 struct resource
*res
;
315 if (has_acpi_companion(&pdev
->dev
)) {
318 dev
= device_find_child(&pdev
->dev
, &phy
->initialize
,
319 emac_sgmii_acpi_match
);
322 dev_warn(&pdev
->dev
, "cannot find internal phy node\n");
323 /* There is typically no internal PHY on emulation
324 * systems, so if we can't find the node, assume
325 * we are on an emulation system and stub-out
326 * support for the internal PHY. These systems only
329 phy
->open
= emac_sgmii_dummy
;
330 phy
->close
= emac_sgmii_dummy
;
331 phy
->link_up
= emac_sgmii_dummy
;
332 phy
->link_down
= emac_sgmii_dummy
;
337 sgmii_pdev
= to_platform_device(dev
);
339 const struct of_device_id
*match
;
340 struct device_node
*np
;
342 np
= of_parse_phandle(pdev
->dev
.of_node
, "internal-phy", 0);
344 dev_err(&pdev
->dev
, "missing internal-phy property\n");
348 sgmii_pdev
= of_find_device_by_node(np
);
350 dev_err(&pdev
->dev
, "invalid internal-phy property\n");
354 match
= of_match_device(emac_sgmii_dt_match
, &sgmii_pdev
->dev
);
356 dev_err(&pdev
->dev
, "unrecognized internal phy node\n");
358 goto error_put_device
;
361 phy
->initialize
= (emac_sgmii_function
)match
->data
;
364 phy
->open
= emac_sgmii_open
;
365 phy
->close
= emac_sgmii_close
;
366 phy
->link_up
= emac_sgmii_link_up
;
367 phy
->link_down
= emac_sgmii_link_down
;
369 /* Base address is the first address */
370 res
= platform_get_resource(sgmii_pdev
, IORESOURCE_MEM
, 0);
373 goto error_put_device
;
376 phy
->base
= ioremap(res
->start
, resource_size(res
));
379 goto error_put_device
;
382 /* v2 SGMII has a per-lane digital digital, so parse it if it exists */
383 res
= platform_get_resource(sgmii_pdev
, IORESOURCE_MEM
, 1);
385 phy
->digital
= ioremap(res
->start
, resource_size(res
));
388 goto error_unmap_base
;
392 ret
= phy
->initialize(adpt
);
396 emac_sgmii_link_init(adpt
);
398 ret
= platform_get_irq(sgmii_pdev
, 0);
402 /* We've remapped the addresses, so we don't need the device any
403 * more. of_find_device_by_node() says we should release it.
405 put_device(&sgmii_pdev
->dev
);
411 iounmap(phy
->digital
);
415 put_device(&sgmii_pdev
->dev
);