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1 /*
2
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
7
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
11
12 -----<snip>-----
13
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41 Contributors:
42
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
45
46 Tigran Aivazian - bug fixes, skbuff free cleanup
47
48 Martin Mares - suggestions for PCI cleanup
49
50 David S. Miller - PCI DMA and softnet updates
51
52 Ernst Gill - fixes ported from BSD driver
53
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
56
57 Gerard Sharp - bug fix, testing and feedback
58
59 David Ford - Rx ring wrap fix
60
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
63
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
66
67 Santiago Garcia Mantinan - testing and feedback
68
69 Jens David - 2.2.x kernel backports
70
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
73
74 Jean-Jacques Michel - bug fix
75
76 Tobias Ringström - Rx interrupt status checking suggestion
77
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
80
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
82
83 Robert Kuebel - Save kernel thread from dying on any signal.
84
85 Submitting bug reports:
86
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
89
90 */
91
92 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
93
94 #define DRV_NAME "8139too"
95 #define DRV_VERSION "0.9.28"
96
97
98 #include <linux/module.h>
99 #include <linux/kernel.h>
100 #include <linux/compiler.h>
101 #include <linux/pci.h>
102 #include <linux/init.h>
103 #include <linux/interrupt.h>
104 #include <linux/netdevice.h>
105 #include <linux/etherdevice.h>
106 #include <linux/rtnetlink.h>
107 #include <linux/delay.h>
108 #include <linux/ethtool.h>
109 #include <linux/mii.h>
110 #include <linux/completion.h>
111 #include <linux/crc32.h>
112 #include <linux/io.h>
113 #include <linux/uaccess.h>
114 #include <linux/gfp.h>
115 #include <asm/irq.h>
116
117 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
118
119 /* Default Message level */
120 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
121 NETIF_MSG_PROBE | \
122 NETIF_MSG_LINK)
123
124
125 /* define to 1, 2 or 3 to enable copious debugging info */
126 #define RTL8139_DEBUG 0
127
128 /* define to 1 to disable lightweight runtime debugging checks */
129 #undef RTL8139_NDEBUG
130
131
132 #ifdef RTL8139_NDEBUG
133 # define assert(expr) do {} while (0)
134 #else
135 # define assert(expr) \
136 if (unlikely(!(expr))) { \
137 pr_err("Assertion failed! %s,%s,%s,line=%d\n", \
138 #expr, __FILE__, __func__, __LINE__); \
139 }
140 #endif
141
142
143 /* A few user-configurable values. */
144 /* media options */
145 #define MAX_UNITS 8
146 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
147 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
148
149 /* Whether to use MMIO or PIO. Default to MMIO. */
150 #ifdef CONFIG_8139TOO_PIO
151 static bool use_io = true;
152 #else
153 static bool use_io = false;
154 #endif
155
156 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
157 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
158 static int multicast_filter_limit = 32;
159
160 /* bitmapped message enable number */
161 static int debug = -1;
162
163 /*
164 * Receive ring size
165 * Warning: 64K ring has hardware issues and may lock up.
166 */
167 #if defined(CONFIG_SH_DREAMCAST)
168 #define RX_BUF_IDX 0 /* 8K ring */
169 #else
170 #define RX_BUF_IDX 2 /* 32K ring */
171 #endif
172 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
173 #define RX_BUF_PAD 16
174 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
175
176 #if RX_BUF_LEN == 65536
177 #define RX_BUF_TOT_LEN RX_BUF_LEN
178 #else
179 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
180 #endif
181
182 /* Number of Tx descriptor registers. */
183 #define NUM_TX_DESC 4
184
185 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
186 #define MAX_ETH_FRAME_SIZE 1536
187
188 /* max supported payload size */
189 #define MAX_ETH_DATA_SIZE (MAX_ETH_FRAME_SIZE - ETH_HLEN - ETH_FCS_LEN)
190
191 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
192 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
193 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
194
195 /* PCI Tuning Parameters
196 Threshold is bytes transferred to chip before transmission starts. */
197 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
198
199 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
200 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
201 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
202 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
203 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
204
205 /* Operational parameters that usually are not changed. */
206 /* Time in jiffies before concluding the transmitter is hung. */
207 #define TX_TIMEOUT (6*HZ)
208
209
210 enum {
211 HAS_MII_XCVR = 0x010000,
212 HAS_CHIP_XCVR = 0x020000,
213 HAS_LNK_CHNG = 0x040000,
214 };
215
216 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
217 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
218 #define RTL_MIN_IO_SIZE 0x80
219 #define RTL8139B_IO_SIZE 256
220
221 #define RTL8129_CAPS HAS_MII_XCVR
222 #define RTL8139_CAPS (HAS_CHIP_XCVR|HAS_LNK_CHNG)
223
224 typedef enum {
225 RTL8139 = 0,
226 RTL8129,
227 } board_t;
228
229
230 /* indexed by board_t, above */
231 static const struct {
232 const char *name;
233 u32 hw_flags;
234 } board_info[] = {
235 { "RealTek RTL8139", RTL8139_CAPS },
236 { "RealTek RTL8129", RTL8129_CAPS },
237 };
238
239
240 static const struct pci_device_id rtl8139_pci_tbl[] = {
241 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
242 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
243 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
256 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
257 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
258 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
259 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
260
261 #ifdef CONFIG_SH_SECUREEDGE5410
262 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
263 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
264 #endif
265 #ifdef CONFIG_8139TOO_8129
266 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
267 #endif
268
269 /* some crazy cards report invalid vendor ids like
270 * 0x0001 here. The other ids are valid and constant,
271 * so we simply don't match on the main vendor id.
272 */
273 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
274 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
275 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
276
277 {0,}
278 };
279 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
280
281 static struct {
282 const char str[ETH_GSTRING_LEN];
283 } ethtool_stats_keys[] = {
284 { "early_rx" },
285 { "tx_buf_mapped" },
286 { "tx_timeouts" },
287 { "rx_lost_in_ring" },
288 };
289
290 /* The rest of these values should never change. */
291
292 /* Symbolic offsets to registers. */
293 enum RTL8139_registers {
294 MAC0 = 0, /* Ethernet hardware address. */
295 MAR0 = 8, /* Multicast filter. */
296 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
297 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
298 RxBuf = 0x30,
299 ChipCmd = 0x37,
300 RxBufPtr = 0x38,
301 RxBufAddr = 0x3A,
302 IntrMask = 0x3C,
303 IntrStatus = 0x3E,
304 TxConfig = 0x40,
305 RxConfig = 0x44,
306 Timer = 0x48, /* A general-purpose counter. */
307 RxMissed = 0x4C, /* 24 bits valid, write clears. */
308 Cfg9346 = 0x50,
309 Config0 = 0x51,
310 Config1 = 0x52,
311 TimerInt = 0x54,
312 MediaStatus = 0x58,
313 Config3 = 0x59,
314 Config4 = 0x5A, /* absent on RTL-8139A */
315 HltClk = 0x5B,
316 MultiIntr = 0x5C,
317 TxSummary = 0x60,
318 BasicModeCtrl = 0x62,
319 BasicModeStatus = 0x64,
320 NWayAdvert = 0x66,
321 NWayLPAR = 0x68,
322 NWayExpansion = 0x6A,
323 /* Undocumented registers, but required for proper operation. */
324 FIFOTMS = 0x70, /* FIFO Control and test. */
325 CSCR = 0x74, /* Chip Status and Configuration Register. */
326 PARA78 = 0x78,
327 FlashReg = 0xD4, /* Communication with Flash ROM, four bytes. */
328 PARA7c = 0x7c, /* Magic transceiver parameter register. */
329 Config5 = 0xD8, /* absent on RTL-8139A */
330 };
331
332 enum ClearBitMasks {
333 MultiIntrClear = 0xF000,
334 ChipCmdClear = 0xE2,
335 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
336 };
337
338 enum ChipCmdBits {
339 CmdReset = 0x10,
340 CmdRxEnb = 0x08,
341 CmdTxEnb = 0x04,
342 RxBufEmpty = 0x01,
343 };
344
345 /* Interrupt register bits, using my own meaningful names. */
346 enum IntrStatusBits {
347 PCIErr = 0x8000,
348 PCSTimeout = 0x4000,
349 RxFIFOOver = 0x40,
350 RxUnderrun = 0x20,
351 RxOverflow = 0x10,
352 TxErr = 0x08,
353 TxOK = 0x04,
354 RxErr = 0x02,
355 RxOK = 0x01,
356
357 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
358 };
359
360 enum TxStatusBits {
361 TxHostOwns = 0x2000,
362 TxUnderrun = 0x4000,
363 TxStatOK = 0x8000,
364 TxOutOfWindow = 0x20000000,
365 TxAborted = 0x40000000,
366 TxCarrierLost = 0x80000000,
367 };
368 enum RxStatusBits {
369 RxMulticast = 0x8000,
370 RxPhysical = 0x4000,
371 RxBroadcast = 0x2000,
372 RxBadSymbol = 0x0020,
373 RxRunt = 0x0010,
374 RxTooLong = 0x0008,
375 RxCRCErr = 0x0004,
376 RxBadAlign = 0x0002,
377 RxStatusOK = 0x0001,
378 };
379
380 /* Bits in RxConfig. */
381 enum rx_mode_bits {
382 AcceptErr = 0x20,
383 AcceptRunt = 0x10,
384 AcceptBroadcast = 0x08,
385 AcceptMulticast = 0x04,
386 AcceptMyPhys = 0x02,
387 AcceptAllPhys = 0x01,
388 };
389
390 /* Bits in TxConfig. */
391 enum tx_config_bits {
392 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
393 TxIFGShift = 24,
394 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
395 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
396 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
397 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
398
399 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
400 TxCRC = (1 << 16), /* DISABLE Tx pkt CRC append */
401 TxClearAbt = (1 << 0), /* Clear abort (WO) */
402 TxDMAShift = 8, /* DMA burst value (0-7) is shifted X many bits */
403 TxRetryShift = 4, /* TXRR value (0-15) is shifted X many bits */
404
405 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
406 };
407
408 /* Bits in Config1 */
409 enum Config1Bits {
410 Cfg1_PM_Enable = 0x01,
411 Cfg1_VPD_Enable = 0x02,
412 Cfg1_PIO = 0x04,
413 Cfg1_MMIO = 0x08,
414 LWAKE = 0x10, /* not on 8139, 8139A */
415 Cfg1_Driver_Load = 0x20,
416 Cfg1_LED0 = 0x40,
417 Cfg1_LED1 = 0x80,
418 SLEEP = (1 << 1), /* only on 8139, 8139A */
419 PWRDN = (1 << 0), /* only on 8139, 8139A */
420 };
421
422 /* Bits in Config3 */
423 enum Config3Bits {
424 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
425 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
426 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
427 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
428 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
429 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
430 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
431 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
432 };
433
434 /* Bits in Config4 */
435 enum Config4Bits {
436 LWPTN = (1 << 2), /* not on 8139, 8139A */
437 };
438
439 /* Bits in Config5 */
440 enum Config5Bits {
441 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
442 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
443 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
444 Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */
445 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
446 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
447 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
448 };
449
450 enum RxConfigBits {
451 /* rx fifo threshold */
452 RxCfgFIFOShift = 13,
453 RxCfgFIFONone = (7 << RxCfgFIFOShift),
454
455 /* Max DMA burst */
456 RxCfgDMAShift = 8,
457 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
458
459 /* rx ring buffer length */
460 RxCfgRcv8K = 0,
461 RxCfgRcv16K = (1 << 11),
462 RxCfgRcv32K = (1 << 12),
463 RxCfgRcv64K = (1 << 11) | (1 << 12),
464
465 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
466 RxNoWrap = (1 << 7),
467 };
468
469 /* Twister tuning parameters from RealTek.
470 Completely undocumented, but required to tune bad links on some boards. */
471 enum CSCRBits {
472 CSCR_LinkOKBit = 0x0400,
473 CSCR_LinkChangeBit = 0x0800,
474 CSCR_LinkStatusBits = 0x0f000,
475 CSCR_LinkDownOffCmd = 0x003c0,
476 CSCR_LinkDownCmd = 0x0f3c0,
477 };
478
479 enum Cfg9346Bits {
480 Cfg9346_Lock = 0x00,
481 Cfg9346_Unlock = 0xC0,
482 };
483
484 typedef enum {
485 CH_8139 = 0,
486 CH_8139_K,
487 CH_8139A,
488 CH_8139A_G,
489 CH_8139B,
490 CH_8130,
491 CH_8139C,
492 CH_8100,
493 CH_8100B_8139D,
494 CH_8101,
495 } chip_t;
496
497 enum chip_flags {
498 HasHltClk = (1 << 0),
499 HasLWake = (1 << 1),
500 };
501
502 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
503 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
504 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
505
506 /* directly indexed by chip_t, above */
507 static const struct {
508 const char *name;
509 u32 version; /* from RTL8139C/RTL8139D docs */
510 u32 flags;
511 } rtl_chip_info[] = {
512 { "RTL-8139",
513 HW_REVID(1, 0, 0, 0, 0, 0, 0),
514 HasHltClk,
515 },
516
517 { "RTL-8139 rev K",
518 HW_REVID(1, 1, 0, 0, 0, 0, 0),
519 HasHltClk,
520 },
521
522 { "RTL-8139A",
523 HW_REVID(1, 1, 1, 0, 0, 0, 0),
524 HasHltClk, /* XXX undocumented? */
525 },
526
527 { "RTL-8139A rev G",
528 HW_REVID(1, 1, 1, 0, 0, 1, 0),
529 HasHltClk, /* XXX undocumented? */
530 },
531
532 { "RTL-8139B",
533 HW_REVID(1, 1, 1, 1, 0, 0, 0),
534 HasLWake,
535 },
536
537 { "RTL-8130",
538 HW_REVID(1, 1, 1, 1, 1, 0, 0),
539 HasLWake,
540 },
541
542 { "RTL-8139C",
543 HW_REVID(1, 1, 1, 0, 1, 0, 0),
544 HasLWake,
545 },
546
547 { "RTL-8100",
548 HW_REVID(1, 1, 1, 1, 0, 1, 0),
549 HasLWake,
550 },
551
552 { "RTL-8100B/8139D",
553 HW_REVID(1, 1, 1, 0, 1, 0, 1),
554 HasHltClk /* XXX undocumented? */
555 | HasLWake,
556 },
557
558 { "RTL-8101",
559 HW_REVID(1, 1, 1, 0, 1, 1, 1),
560 HasLWake,
561 },
562 };
563
564 struct rtl_extra_stats {
565 unsigned long early_rx;
566 unsigned long tx_buf_mapped;
567 unsigned long tx_timeouts;
568 unsigned long rx_lost_in_ring;
569 };
570
571 struct rtl8139_stats {
572 u64 packets;
573 u64 bytes;
574 struct u64_stats_sync syncp;
575 };
576
577 struct rtl8139_private {
578 void __iomem *mmio_addr;
579 int drv_flags;
580 struct pci_dev *pci_dev;
581 u32 msg_enable;
582 struct napi_struct napi;
583 struct net_device *dev;
584
585 unsigned char *rx_ring;
586 unsigned int cur_rx; /* RX buf index of next pkt */
587 struct rtl8139_stats rx_stats;
588 dma_addr_t rx_ring_dma;
589
590 unsigned int tx_flag;
591 unsigned long cur_tx;
592 unsigned long dirty_tx;
593 struct rtl8139_stats tx_stats;
594 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
595 unsigned char *tx_bufs; /* Tx bounce buffer region. */
596 dma_addr_t tx_bufs_dma;
597
598 signed char phys[4]; /* MII device addresses. */
599
600 /* Twister tune state. */
601 char twistie, twist_row, twist_col;
602
603 unsigned int watchdog_fired : 1;
604 unsigned int default_port : 4; /* Last dev->if_port value. */
605 unsigned int have_thread : 1;
606
607 spinlock_t lock;
608 spinlock_t rx_lock;
609
610 chip_t chipset;
611 u32 rx_config;
612 struct rtl_extra_stats xstats;
613
614 struct delayed_work thread;
615
616 struct mii_if_info mii;
617 unsigned int regs_len;
618 unsigned long fifo_copy_timeout;
619 };
620
621 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
622 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
623 MODULE_LICENSE("GPL");
624 MODULE_VERSION(DRV_VERSION);
625
626 module_param(use_io, bool, 0);
627 MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO");
628 module_param(multicast_filter_limit, int, 0);
629 module_param_array(media, int, NULL, 0);
630 module_param_array(full_duplex, int, NULL, 0);
631 module_param(debug, int, 0);
632 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
633 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
634 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
635 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
636
637 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
638 static int rtl8139_open (struct net_device *dev);
639 static int mdio_read (struct net_device *dev, int phy_id, int location);
640 static void mdio_write (struct net_device *dev, int phy_id, int location,
641 int val);
642 static void rtl8139_start_thread(struct rtl8139_private *tp);
643 static void rtl8139_tx_timeout (struct net_device *dev);
644 static void rtl8139_init_ring (struct net_device *dev);
645 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb,
646 struct net_device *dev);
647 #ifdef CONFIG_NET_POLL_CONTROLLER
648 static void rtl8139_poll_controller(struct net_device *dev);
649 #endif
650 static int rtl8139_set_mac_address(struct net_device *dev, void *p);
651 static int rtl8139_poll(struct napi_struct *napi, int budget);
652 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);
653 static int rtl8139_close (struct net_device *dev);
654 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
655 static struct rtnl_link_stats64 *rtl8139_get_stats64(struct net_device *dev,
656 struct rtnl_link_stats64
657 *stats);
658 static void rtl8139_set_rx_mode (struct net_device *dev);
659 static void __set_rx_mode (struct net_device *dev);
660 static void rtl8139_hw_start (struct net_device *dev);
661 static void rtl8139_thread (struct work_struct *work);
662 static void rtl8139_tx_timeout_task(struct work_struct *work);
663 static const struct ethtool_ops rtl8139_ethtool_ops;
664
665 /* write MMIO register, with flush */
666 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
667 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
668 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
669 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
670
671 /* write MMIO register */
672 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg))
673 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg))
674 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg))
675
676 /* read MMIO register */
677 #define RTL_R8(reg) ioread8 (ioaddr + (reg))
678 #define RTL_R16(reg) ioread16 (ioaddr + (reg))
679 #define RTL_R32(reg) ioread32 (ioaddr + (reg))
680
681
682 static const u16 rtl8139_intr_mask =
683 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
684 TxErr | TxOK | RxErr | RxOK;
685
686 static const u16 rtl8139_norx_intr_mask =
687 PCIErr | PCSTimeout | RxUnderrun |
688 TxErr | TxOK | RxErr ;
689
690 #if RX_BUF_IDX == 0
691 static const unsigned int rtl8139_rx_config =
692 RxCfgRcv8K | RxNoWrap |
693 (RX_FIFO_THRESH << RxCfgFIFOShift) |
694 (RX_DMA_BURST << RxCfgDMAShift);
695 #elif RX_BUF_IDX == 1
696 static const unsigned int rtl8139_rx_config =
697 RxCfgRcv16K | RxNoWrap |
698 (RX_FIFO_THRESH << RxCfgFIFOShift) |
699 (RX_DMA_BURST << RxCfgDMAShift);
700 #elif RX_BUF_IDX == 2
701 static const unsigned int rtl8139_rx_config =
702 RxCfgRcv32K | RxNoWrap |
703 (RX_FIFO_THRESH << RxCfgFIFOShift) |
704 (RX_DMA_BURST << RxCfgDMAShift);
705 #elif RX_BUF_IDX == 3
706 static const unsigned int rtl8139_rx_config =
707 RxCfgRcv64K |
708 (RX_FIFO_THRESH << RxCfgFIFOShift) |
709 (RX_DMA_BURST << RxCfgDMAShift);
710 #else
711 #error "Invalid configuration for 8139_RXBUF_IDX"
712 #endif
713
714 static const unsigned int rtl8139_tx_config =
715 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
716
717 static void __rtl8139_cleanup_dev (struct net_device *dev)
718 {
719 struct rtl8139_private *tp = netdev_priv(dev);
720 struct pci_dev *pdev;
721
722 assert (dev != NULL);
723 assert (tp->pci_dev != NULL);
724 pdev = tp->pci_dev;
725
726 if (tp->mmio_addr)
727 pci_iounmap (pdev, tp->mmio_addr);
728
729 /* it's ok to call this even if we have no regions to free */
730 pci_release_regions (pdev);
731
732 free_netdev(dev);
733 }
734
735
736 static void rtl8139_chip_reset (void __iomem *ioaddr)
737 {
738 int i;
739
740 /* Soft reset the chip. */
741 RTL_W8 (ChipCmd, CmdReset);
742
743 /* Check that the chip has finished the reset. */
744 for (i = 1000; i > 0; i--) {
745 barrier();
746 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
747 break;
748 udelay (10);
749 }
750 }
751
752
753 static struct net_device *rtl8139_init_board(struct pci_dev *pdev)
754 {
755 struct device *d = &pdev->dev;
756 void __iomem *ioaddr;
757 struct net_device *dev;
758 struct rtl8139_private *tp;
759 u8 tmp8;
760 int rc, disable_dev_on_err = 0;
761 unsigned int i, bar;
762 unsigned long io_len;
763 u32 version;
764 static const struct {
765 unsigned long mask;
766 char *type;
767 } res[] = {
768 { IORESOURCE_IO, "PIO" },
769 { IORESOURCE_MEM, "MMIO" }
770 };
771
772 assert (pdev != NULL);
773
774 /* dev and priv zeroed in alloc_etherdev */
775 dev = alloc_etherdev (sizeof (*tp));
776 if (dev == NULL)
777 return ERR_PTR(-ENOMEM);
778
779 SET_NETDEV_DEV(dev, &pdev->dev);
780
781 tp = netdev_priv(dev);
782 tp->pci_dev = pdev;
783
784 /* enable device (incl. PCI PM wakeup and hotplug setup) */
785 rc = pci_enable_device (pdev);
786 if (rc)
787 goto err_out;
788
789 rc = pci_request_regions (pdev, DRV_NAME);
790 if (rc)
791 goto err_out;
792 disable_dev_on_err = 1;
793
794 pci_set_master (pdev);
795
796 u64_stats_init(&tp->rx_stats.syncp);
797 u64_stats_init(&tp->tx_stats.syncp);
798
799 retry:
800 /* PIO bar register comes first. */
801 bar = !use_io;
802
803 io_len = pci_resource_len(pdev, bar);
804
805 dev_dbg(d, "%s region size = 0x%02lX\n", res[bar].type, io_len);
806
807 if (!(pci_resource_flags(pdev, bar) & res[bar].mask)) {
808 dev_err(d, "region #%d not a %s resource, aborting\n", bar,
809 res[bar].type);
810 rc = -ENODEV;
811 goto err_out;
812 }
813 if (io_len < RTL_MIN_IO_SIZE) {
814 dev_err(d, "Invalid PCI %s region size(s), aborting\n",
815 res[bar].type);
816 rc = -ENODEV;
817 goto err_out;
818 }
819
820 ioaddr = pci_iomap(pdev, bar, 0);
821 if (!ioaddr) {
822 dev_err(d, "cannot map %s\n", res[bar].type);
823 if (!use_io) {
824 use_io = true;
825 goto retry;
826 }
827 rc = -ENODEV;
828 goto err_out;
829 }
830 tp->regs_len = io_len;
831 tp->mmio_addr = ioaddr;
832
833 /* Bring old chips out of low-power mode. */
834 RTL_W8 (HltClk, 'R');
835
836 /* check for missing/broken hardware */
837 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
838 dev_err(&pdev->dev, "Chip not responding, ignoring board\n");
839 rc = -EIO;
840 goto err_out;
841 }
842
843 /* identify chip attached to board */
844 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
845 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
846 if (version == rtl_chip_info[i].version) {
847 tp->chipset = i;
848 goto match;
849 }
850
851 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
852 i = 0;
853 dev_dbg(&pdev->dev, "unknown chip version, assuming RTL-8139\n");
854 dev_dbg(&pdev->dev, "TxConfig = 0x%x\n", RTL_R32 (TxConfig));
855 tp->chipset = 0;
856
857 match:
858 pr_debug("chipset id (%d) == index %d, '%s'\n",
859 version, i, rtl_chip_info[i].name);
860
861 if (tp->chipset >= CH_8139B) {
862 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
863 pr_debug("PCI PM wakeup\n");
864 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
865 (tmp8 & LWAKE))
866 new_tmp8 &= ~LWAKE;
867 new_tmp8 |= Cfg1_PM_Enable;
868 if (new_tmp8 != tmp8) {
869 RTL_W8 (Cfg9346, Cfg9346_Unlock);
870 RTL_W8 (Config1, tmp8);
871 RTL_W8 (Cfg9346, Cfg9346_Lock);
872 }
873 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
874 tmp8 = RTL_R8 (Config4);
875 if (tmp8 & LWPTN) {
876 RTL_W8 (Cfg9346, Cfg9346_Unlock);
877 RTL_W8 (Config4, tmp8 & ~LWPTN);
878 RTL_W8 (Cfg9346, Cfg9346_Lock);
879 }
880 }
881 } else {
882 pr_debug("Old chip wakeup\n");
883 tmp8 = RTL_R8 (Config1);
884 tmp8 &= ~(SLEEP | PWRDN);
885 RTL_W8 (Config1, tmp8);
886 }
887
888 rtl8139_chip_reset (ioaddr);
889
890 return dev;
891
892 err_out:
893 __rtl8139_cleanup_dev (dev);
894 if (disable_dev_on_err)
895 pci_disable_device (pdev);
896 return ERR_PTR(rc);
897 }
898
899 static int rtl8139_set_features(struct net_device *dev, netdev_features_t features)
900 {
901 struct rtl8139_private *tp = netdev_priv(dev);
902 unsigned long flags;
903 netdev_features_t changed = features ^ dev->features;
904 void __iomem *ioaddr = tp->mmio_addr;
905
906 if (!(changed & (NETIF_F_RXALL)))
907 return 0;
908
909 spin_lock_irqsave(&tp->lock, flags);
910
911 if (changed & NETIF_F_RXALL) {
912 int rx_mode = tp->rx_config;
913 if (features & NETIF_F_RXALL)
914 rx_mode |= (AcceptErr | AcceptRunt);
915 else
916 rx_mode &= ~(AcceptErr | AcceptRunt);
917 tp->rx_config = rtl8139_rx_config | rx_mode;
918 RTL_W32_F(RxConfig, tp->rx_config);
919 }
920
921 spin_unlock_irqrestore(&tp->lock, flags);
922
923 return 0;
924 }
925
926 static int rtl8139_change_mtu(struct net_device *dev, int new_mtu)
927 {
928 if (new_mtu < 68 || new_mtu > MAX_ETH_DATA_SIZE)
929 return -EINVAL;
930 dev->mtu = new_mtu;
931 return 0;
932 }
933
934 static const struct net_device_ops rtl8139_netdev_ops = {
935 .ndo_open = rtl8139_open,
936 .ndo_stop = rtl8139_close,
937 .ndo_get_stats64 = rtl8139_get_stats64,
938 .ndo_change_mtu = rtl8139_change_mtu,
939 .ndo_validate_addr = eth_validate_addr,
940 .ndo_set_mac_address = rtl8139_set_mac_address,
941 .ndo_start_xmit = rtl8139_start_xmit,
942 .ndo_set_rx_mode = rtl8139_set_rx_mode,
943 .ndo_do_ioctl = netdev_ioctl,
944 .ndo_tx_timeout = rtl8139_tx_timeout,
945 #ifdef CONFIG_NET_POLL_CONTROLLER
946 .ndo_poll_controller = rtl8139_poll_controller,
947 #endif
948 .ndo_set_features = rtl8139_set_features,
949 };
950
951 static int rtl8139_init_one(struct pci_dev *pdev,
952 const struct pci_device_id *ent)
953 {
954 struct net_device *dev = NULL;
955 struct rtl8139_private *tp;
956 int i, addr_len, option;
957 void __iomem *ioaddr;
958 static int board_idx = -1;
959
960 assert (pdev != NULL);
961 assert (ent != NULL);
962
963 board_idx++;
964
965 /* when we're built into the kernel, the driver version message
966 * is only printed if at least one 8139 board has been found
967 */
968 #ifndef MODULE
969 {
970 static int printed_version;
971 if (!printed_version++)
972 pr_info(RTL8139_DRIVER_NAME "\n");
973 }
974 #endif
975
976 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
977 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {
978 dev_info(&pdev->dev,
979 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n",
980 pdev->vendor, pdev->device, pdev->revision);
981 return -ENODEV;
982 }
983
984 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
985 pdev->device == PCI_DEVICE_ID_REALTEK_8139 &&
986 pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS &&
987 pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) {
988 pr_info("OQO Model 2 detected. Forcing PIO\n");
989 use_io = 1;
990 }
991
992 dev = rtl8139_init_board (pdev);
993 if (IS_ERR(dev))
994 return PTR_ERR(dev);
995
996 assert (dev != NULL);
997 tp = netdev_priv(dev);
998 tp->dev = dev;
999
1000 ioaddr = tp->mmio_addr;
1001 assert (ioaddr != NULL);
1002
1003 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
1004 for (i = 0; i < 3; i++)
1005 ((__le16 *) (dev->dev_addr))[i] =
1006 cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len));
1007
1008 /* The Rtl8139-specific entries in the device structure. */
1009 dev->netdev_ops = &rtl8139_netdev_ops;
1010 dev->ethtool_ops = &rtl8139_ethtool_ops;
1011 dev->watchdog_timeo = TX_TIMEOUT;
1012 netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);
1013
1014 /* note: the hardware is not capable of sg/csum/highdma, however
1015 * through the use of skb_copy_and_csum_dev we enable these
1016 * features
1017 */
1018 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
1019 dev->vlan_features = dev->features;
1020
1021 dev->hw_features |= NETIF_F_RXALL;
1022 dev->hw_features |= NETIF_F_RXFCS;
1023
1024 /* tp zeroed and aligned in alloc_etherdev */
1025 tp = netdev_priv(dev);
1026
1027 /* note: tp->chipset set in rtl8139_init_board */
1028 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1029 tp->mmio_addr = ioaddr;
1030 tp->msg_enable =
1031 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1032 spin_lock_init (&tp->lock);
1033 spin_lock_init (&tp->rx_lock);
1034 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1035 tp->mii.dev = dev;
1036 tp->mii.mdio_read = mdio_read;
1037 tp->mii.mdio_write = mdio_write;
1038 tp->mii.phy_id_mask = 0x3f;
1039 tp->mii.reg_num_mask = 0x1f;
1040
1041 /* dev is fully set up and ready to use now */
1042 pr_debug("about to register device named %s (%p)...\n",
1043 dev->name, dev);
1044 i = register_netdev (dev);
1045 if (i) goto err_out;
1046
1047 pci_set_drvdata (pdev, dev);
1048
1049 netdev_info(dev, "%s at 0x%p, %pM, IRQ %d\n",
1050 board_info[ent->driver_data].name,
1051 ioaddr, dev->dev_addr, pdev->irq);
1052
1053 netdev_dbg(dev, "Identified 8139 chip type '%s'\n",
1054 rtl_chip_info[tp->chipset].name);
1055
1056 /* Find the connected MII xcvrs.
1057 Doing this in open() would allow detecting external xcvrs later, but
1058 takes too much time. */
1059 #ifdef CONFIG_8139TOO_8129
1060 if (tp->drv_flags & HAS_MII_XCVR) {
1061 int phy, phy_idx = 0;
1062 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1063 int mii_status = mdio_read(dev, phy, 1);
1064 if (mii_status != 0xffff && mii_status != 0x0000) {
1065 u16 advertising = mdio_read(dev, phy, 4);
1066 tp->phys[phy_idx++] = phy;
1067 netdev_info(dev, "MII transceiver %d status 0x%04x advertising %04x\n",
1068 phy, mii_status, advertising);
1069 }
1070 }
1071 if (phy_idx == 0) {
1072 netdev_info(dev, "No MII transceivers found! Assuming SYM transceiver\n");
1073 tp->phys[0] = 32;
1074 }
1075 } else
1076 #endif
1077 tp->phys[0] = 32;
1078 tp->mii.phy_id = tp->phys[0];
1079
1080 /* The lower four bits are the media type. */
1081 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1082 if (option > 0) {
1083 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1084 tp->default_port = option & 0xFF;
1085 if (tp->default_port)
1086 tp->mii.force_media = 1;
1087 }
1088 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1089 tp->mii.full_duplex = full_duplex[board_idx];
1090 if (tp->mii.full_duplex) {
1091 netdev_info(dev, "Media type forced to Full Duplex\n");
1092 /* Changing the MII-advertised media because might prevent
1093 re-connection. */
1094 tp->mii.force_media = 1;
1095 }
1096 if (tp->default_port) {
1097 netdev_info(dev, " Forcing %dMbps %s-duplex operation\n",
1098 (option & 0x20 ? 100 : 10),
1099 (option & 0x10 ? "full" : "half"));
1100 mdio_write(dev, tp->phys[0], 0,
1101 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1102 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1103 }
1104
1105 /* Put the chip into low-power mode. */
1106 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1107 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1108
1109 return 0;
1110
1111 err_out:
1112 __rtl8139_cleanup_dev (dev);
1113 pci_disable_device (pdev);
1114 return i;
1115 }
1116
1117
1118 static void rtl8139_remove_one(struct pci_dev *pdev)
1119 {
1120 struct net_device *dev = pci_get_drvdata (pdev);
1121 struct rtl8139_private *tp = netdev_priv(dev);
1122
1123 assert (dev != NULL);
1124
1125 cancel_delayed_work_sync(&tp->thread);
1126
1127 unregister_netdev (dev);
1128
1129 __rtl8139_cleanup_dev (dev);
1130 pci_disable_device (pdev);
1131 }
1132
1133
1134 /* Serial EEPROM section. */
1135
1136 /* EEPROM_Ctrl bits. */
1137 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1138 #define EE_CS 0x08 /* EEPROM chip select. */
1139 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1140 #define EE_WRITE_0 0x00
1141 #define EE_WRITE_1 0x02
1142 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1143 #define EE_ENB (0x80 | EE_CS)
1144
1145 /* Delay between EEPROM clock transitions.
1146 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1147 */
1148
1149 #define eeprom_delay() (void)RTL_R8(Cfg9346)
1150
1151 /* The EEPROM commands include the alway-set leading bit. */
1152 #define EE_WRITE_CMD (5)
1153 #define EE_READ_CMD (6)
1154 #define EE_ERASE_CMD (7)
1155
1156 static int read_eeprom(void __iomem *ioaddr, int location, int addr_len)
1157 {
1158 int i;
1159 unsigned retval = 0;
1160 int read_cmd = location | (EE_READ_CMD << addr_len);
1161
1162 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
1163 RTL_W8 (Cfg9346, EE_ENB);
1164 eeprom_delay ();
1165
1166 /* Shift the read command bits out. */
1167 for (i = 4 + addr_len; i >= 0; i--) {
1168 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1169 RTL_W8 (Cfg9346, EE_ENB | dataval);
1170 eeprom_delay ();
1171 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
1172 eeprom_delay ();
1173 }
1174 RTL_W8 (Cfg9346, EE_ENB);
1175 eeprom_delay ();
1176
1177 for (i = 16; i > 0; i--) {
1178 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
1179 eeprom_delay ();
1180 retval =
1181 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
1182 0);
1183 RTL_W8 (Cfg9346, EE_ENB);
1184 eeprom_delay ();
1185 }
1186
1187 /* Terminate the EEPROM access. */
1188 RTL_W8(Cfg9346, 0);
1189 eeprom_delay ();
1190
1191 return retval;
1192 }
1193
1194 /* MII serial management: mostly bogus for now. */
1195 /* Read and write the MII management registers using software-generated
1196 serial MDIO protocol.
1197 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1198 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1199 "overclocking" issues. */
1200 #define MDIO_DIR 0x80
1201 #define MDIO_DATA_OUT 0x04
1202 #define MDIO_DATA_IN 0x02
1203 #define MDIO_CLK 0x01
1204 #define MDIO_WRITE0 (MDIO_DIR)
1205 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1206
1207 #define mdio_delay() RTL_R8(Config4)
1208
1209
1210 static const char mii_2_8139_map[8] = {
1211 BasicModeCtrl,
1212 BasicModeStatus,
1213 0,
1214 0,
1215 NWayAdvert,
1216 NWayLPAR,
1217 NWayExpansion,
1218 0
1219 };
1220
1221
1222 #ifdef CONFIG_8139TOO_8129
1223 /* Syncronize the MII management interface by shifting 32 one bits out. */
1224 static void mdio_sync (void __iomem *ioaddr)
1225 {
1226 int i;
1227
1228 for (i = 32; i >= 0; i--) {
1229 RTL_W8 (Config4, MDIO_WRITE1);
1230 mdio_delay ();
1231 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
1232 mdio_delay ();
1233 }
1234 }
1235 #endif
1236
1237 static int mdio_read (struct net_device *dev, int phy_id, int location)
1238 {
1239 struct rtl8139_private *tp = netdev_priv(dev);
1240 int retval = 0;
1241 #ifdef CONFIG_8139TOO_8129
1242 void __iomem *ioaddr = tp->mmio_addr;
1243 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1244 int i;
1245 #endif
1246
1247 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1248 void __iomem *ioaddr = tp->mmio_addr;
1249 return location < 8 && mii_2_8139_map[location] ?
1250 RTL_R16 (mii_2_8139_map[location]) : 0;
1251 }
1252
1253 #ifdef CONFIG_8139TOO_8129
1254 mdio_sync (ioaddr);
1255 /* Shift the read command bits out. */
1256 for (i = 15; i >= 0; i--) {
1257 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1258
1259 RTL_W8 (Config4, MDIO_DIR | dataval);
1260 mdio_delay ();
1261 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
1262 mdio_delay ();
1263 }
1264
1265 /* Read the two transition, 16 data, and wire-idle bits. */
1266 for (i = 19; i > 0; i--) {
1267 RTL_W8 (Config4, 0);
1268 mdio_delay ();
1269 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
1270 RTL_W8 (Config4, MDIO_CLK);
1271 mdio_delay ();
1272 }
1273 #endif
1274
1275 return (retval >> 1) & 0xffff;
1276 }
1277
1278
1279 static void mdio_write (struct net_device *dev, int phy_id, int location,
1280 int value)
1281 {
1282 struct rtl8139_private *tp = netdev_priv(dev);
1283 #ifdef CONFIG_8139TOO_8129
1284 void __iomem *ioaddr = tp->mmio_addr;
1285 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1286 int i;
1287 #endif
1288
1289 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1290 void __iomem *ioaddr = tp->mmio_addr;
1291 if (location == 0) {
1292 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1293 RTL_W16 (BasicModeCtrl, value);
1294 RTL_W8 (Cfg9346, Cfg9346_Lock);
1295 } else if (location < 8 && mii_2_8139_map[location])
1296 RTL_W16 (mii_2_8139_map[location], value);
1297 return;
1298 }
1299
1300 #ifdef CONFIG_8139TOO_8129
1301 mdio_sync (ioaddr);
1302
1303 /* Shift the command bits out. */
1304 for (i = 31; i >= 0; i--) {
1305 int dataval =
1306 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1307 RTL_W8 (Config4, dataval);
1308 mdio_delay ();
1309 RTL_W8 (Config4, dataval | MDIO_CLK);
1310 mdio_delay ();
1311 }
1312 /* Clear out extra bits. */
1313 for (i = 2; i > 0; i--) {
1314 RTL_W8 (Config4, 0);
1315 mdio_delay ();
1316 RTL_W8 (Config4, MDIO_CLK);
1317 mdio_delay ();
1318 }
1319 #endif
1320 }
1321
1322
1323 static int rtl8139_open (struct net_device *dev)
1324 {
1325 struct rtl8139_private *tp = netdev_priv(dev);
1326 void __iomem *ioaddr = tp->mmio_addr;
1327 const int irq = tp->pci_dev->irq;
1328 int retval;
1329
1330 retval = request_irq(irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev);
1331 if (retval)
1332 return retval;
1333
1334 tp->tx_bufs = dma_alloc_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1335 &tp->tx_bufs_dma, GFP_KERNEL);
1336 tp->rx_ring = dma_alloc_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1337 &tp->rx_ring_dma, GFP_KERNEL);
1338 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1339 free_irq(irq, dev);
1340
1341 if (tp->tx_bufs)
1342 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1343 tp->tx_bufs, tp->tx_bufs_dma);
1344 if (tp->rx_ring)
1345 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1346 tp->rx_ring, tp->rx_ring_dma);
1347
1348 return -ENOMEM;
1349
1350 }
1351
1352 napi_enable(&tp->napi);
1353
1354 tp->mii.full_duplex = tp->mii.force_media;
1355 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1356
1357 rtl8139_init_ring (dev);
1358 rtl8139_hw_start (dev);
1359 netif_start_queue (dev);
1360
1361 netif_dbg(tp, ifup, dev,
1362 "%s() ioaddr %#llx IRQ %d GP Pins %02x %s-duplex\n",
1363 __func__,
1364 (unsigned long long)pci_resource_start (tp->pci_dev, 1),
1365 irq, RTL_R8 (MediaStatus),
1366 tp->mii.full_duplex ? "full" : "half");
1367
1368 rtl8139_start_thread(tp);
1369
1370 return 0;
1371 }
1372
1373
1374 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1375 {
1376 struct rtl8139_private *tp = netdev_priv(dev);
1377
1378 if (tp->phys[0] >= 0) {
1379 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1380 }
1381 }
1382
1383 /* Start the hardware at open or resume. */
1384 static void rtl8139_hw_start (struct net_device *dev)
1385 {
1386 struct rtl8139_private *tp = netdev_priv(dev);
1387 void __iomem *ioaddr = tp->mmio_addr;
1388 u32 i;
1389 u8 tmp;
1390
1391 /* Bring old chips out of low-power mode. */
1392 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1393 RTL_W8 (HltClk, 'R');
1394
1395 rtl8139_chip_reset (ioaddr);
1396
1397 /* unlock Config[01234] and BMCR register writes */
1398 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1399 /* Restore our idea of the MAC address. */
1400 RTL_W32_F (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1401 RTL_W32_F (MAC0 + 4, le16_to_cpu (*(__le16 *) (dev->dev_addr + 4)));
1402
1403 tp->cur_rx = 0;
1404
1405 /* init Rx ring buffer DMA address */
1406 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1407
1408 /* Must enable Tx/Rx before setting transfer thresholds! */
1409 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1410
1411 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1412 RTL_W32 (RxConfig, tp->rx_config);
1413 RTL_W32 (TxConfig, rtl8139_tx_config);
1414
1415 rtl_check_media (dev, 1);
1416
1417 if (tp->chipset >= CH_8139B) {
1418 /* Disable magic packet scanning, which is enabled
1419 * when PM is enabled in Config1. It can be reenabled
1420 * via ETHTOOL_SWOL if desired. */
1421 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1422 }
1423
1424 netdev_dbg(dev, "init buffer addresses\n");
1425
1426 /* Lock Config[01234] and BMCR register writes */
1427 RTL_W8 (Cfg9346, Cfg9346_Lock);
1428
1429 /* init Tx buffer DMA addresses */
1430 for (i = 0; i < NUM_TX_DESC; i++)
1431 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1432
1433 RTL_W32 (RxMissed, 0);
1434
1435 rtl8139_set_rx_mode (dev);
1436
1437 /* no early-rx interrupts */
1438 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1439
1440 /* make sure RxTx has started */
1441 tmp = RTL_R8 (ChipCmd);
1442 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1443 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1444
1445 /* Enable all known interrupts by setting the interrupt mask. */
1446 RTL_W16 (IntrMask, rtl8139_intr_mask);
1447 }
1448
1449
1450 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1451 static void rtl8139_init_ring (struct net_device *dev)
1452 {
1453 struct rtl8139_private *tp = netdev_priv(dev);
1454 int i;
1455
1456 tp->cur_rx = 0;
1457 tp->cur_tx = 0;
1458 tp->dirty_tx = 0;
1459
1460 for (i = 0; i < NUM_TX_DESC; i++)
1461 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1462 }
1463
1464
1465 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1466 static int next_tick = 3 * HZ;
1467
1468 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1469 static inline void rtl8139_tune_twister (struct net_device *dev,
1470 struct rtl8139_private *tp) {}
1471 #else
1472 enum TwisterParamVals {
1473 PARA78_default = 0x78fa8388,
1474 PARA7c_default = 0xcb38de43, /* param[0][3] */
1475 PARA7c_xxx = 0xcb38de43,
1476 };
1477
1478 static const unsigned long param[4][4] = {
1479 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1480 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1481 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1482 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1483 };
1484
1485 static void rtl8139_tune_twister (struct net_device *dev,
1486 struct rtl8139_private *tp)
1487 {
1488 int linkcase;
1489 void __iomem *ioaddr = tp->mmio_addr;
1490
1491 /* This is a complicated state machine to configure the "twister" for
1492 impedance/echos based on the cable length.
1493 All of this is magic and undocumented.
1494 */
1495 switch (tp->twistie) {
1496 case 1:
1497 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1498 /* We have link beat, let us tune the twister. */
1499 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1500 tp->twistie = 2; /* Change to state 2. */
1501 next_tick = HZ / 10;
1502 } else {
1503 /* Just put in some reasonable defaults for when beat returns. */
1504 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1505 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1506 RTL_W32 (PARA78, PARA78_default);
1507 RTL_W32 (PARA7c, PARA7c_default);
1508 tp->twistie = 0; /* Bail from future actions. */
1509 }
1510 break;
1511 case 2:
1512 /* Read how long it took to hear the echo. */
1513 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1514 if (linkcase == 0x7000)
1515 tp->twist_row = 3;
1516 else if (linkcase == 0x3000)
1517 tp->twist_row = 2;
1518 else if (linkcase == 0x1000)
1519 tp->twist_row = 1;
1520 else
1521 tp->twist_row = 0;
1522 tp->twist_col = 0;
1523 tp->twistie = 3; /* Change to state 2. */
1524 next_tick = HZ / 10;
1525 break;
1526 case 3:
1527 /* Put out four tuning parameters, one per 100msec. */
1528 if (tp->twist_col == 0)
1529 RTL_W16 (FIFOTMS, 0);
1530 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1531 [(int) tp->twist_col]);
1532 next_tick = HZ / 10;
1533 if (++tp->twist_col >= 4) {
1534 /* For short cables we are done.
1535 For long cables (row == 3) check for mistune. */
1536 tp->twistie =
1537 (tp->twist_row == 3) ? 4 : 0;
1538 }
1539 break;
1540 case 4:
1541 /* Special case for long cables: check for mistune. */
1542 if ((RTL_R16 (CSCR) &
1543 CSCR_LinkStatusBits) == 0x7000) {
1544 tp->twistie = 0;
1545 break;
1546 } else {
1547 RTL_W32 (PARA7c, 0xfb38de03);
1548 tp->twistie = 5;
1549 next_tick = HZ / 10;
1550 }
1551 break;
1552 case 5:
1553 /* Retune for shorter cable (column 2). */
1554 RTL_W32 (FIFOTMS, 0x20);
1555 RTL_W32 (PARA78, PARA78_default);
1556 RTL_W32 (PARA7c, PARA7c_default);
1557 RTL_W32 (FIFOTMS, 0x00);
1558 tp->twist_row = 2;
1559 tp->twist_col = 0;
1560 tp->twistie = 3;
1561 next_tick = HZ / 10;
1562 break;
1563
1564 default:
1565 /* do nothing */
1566 break;
1567 }
1568 }
1569 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1570
1571 static inline void rtl8139_thread_iter (struct net_device *dev,
1572 struct rtl8139_private *tp,
1573 void __iomem *ioaddr)
1574 {
1575 int mii_lpa;
1576
1577 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1578
1579 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1580 int duplex = ((mii_lpa & LPA_100FULL) ||
1581 (mii_lpa & 0x01C0) == 0x0040);
1582 if (tp->mii.full_duplex != duplex) {
1583 tp->mii.full_duplex = duplex;
1584
1585 if (mii_lpa) {
1586 netdev_info(dev, "Setting %s-duplex based on MII #%d link partner ability of %04x\n",
1587 tp->mii.full_duplex ? "full" : "half",
1588 tp->phys[0], mii_lpa);
1589 } else {
1590 netdev_info(dev, "media is unconnected, link down, or incompatible connection\n");
1591 }
1592 #if 0
1593 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1594 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1595 RTL_W8 (Cfg9346, Cfg9346_Lock);
1596 #endif
1597 }
1598 }
1599
1600 next_tick = HZ * 60;
1601
1602 rtl8139_tune_twister (dev, tp);
1603
1604 netdev_dbg(dev, "Media selection tick, Link partner %04x\n",
1605 RTL_R16(NWayLPAR));
1606 netdev_dbg(dev, "Other registers are IntMask %04x IntStatus %04x\n",
1607 RTL_R16(IntrMask), RTL_R16(IntrStatus));
1608 netdev_dbg(dev, "Chip config %02x %02x\n",
1609 RTL_R8(Config0), RTL_R8(Config1));
1610 }
1611
1612 static void rtl8139_thread (struct work_struct *work)
1613 {
1614 struct rtl8139_private *tp =
1615 container_of(work, struct rtl8139_private, thread.work);
1616 struct net_device *dev = tp->mii.dev;
1617 unsigned long thr_delay = next_tick;
1618
1619 rtnl_lock();
1620
1621 if (!netif_running(dev))
1622 goto out_unlock;
1623
1624 if (tp->watchdog_fired) {
1625 tp->watchdog_fired = 0;
1626 rtl8139_tx_timeout_task(work);
1627 } else
1628 rtl8139_thread_iter(dev, tp, tp->mmio_addr);
1629
1630 if (tp->have_thread)
1631 schedule_delayed_work(&tp->thread, thr_delay);
1632 out_unlock:
1633 rtnl_unlock ();
1634 }
1635
1636 static void rtl8139_start_thread(struct rtl8139_private *tp)
1637 {
1638 tp->twistie = 0;
1639 if (tp->chipset == CH_8139_K)
1640 tp->twistie = 1;
1641 else if (tp->drv_flags & HAS_LNK_CHNG)
1642 return;
1643
1644 tp->have_thread = 1;
1645 tp->watchdog_fired = 0;
1646
1647 schedule_delayed_work(&tp->thread, next_tick);
1648 }
1649
1650 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1651 {
1652 tp->cur_tx = 0;
1653 tp->dirty_tx = 0;
1654
1655 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1656 }
1657
1658 static void rtl8139_tx_timeout_task (struct work_struct *work)
1659 {
1660 struct rtl8139_private *tp =
1661 container_of(work, struct rtl8139_private, thread.work);
1662 struct net_device *dev = tp->mii.dev;
1663 void __iomem *ioaddr = tp->mmio_addr;
1664 int i;
1665 u8 tmp8;
1666
1667 netdev_dbg(dev, "Transmit timeout, status %02x %04x %04x media %02x\n",
1668 RTL_R8(ChipCmd), RTL_R16(IntrStatus),
1669 RTL_R16(IntrMask), RTL_R8(MediaStatus));
1670 /* Emit info to figure out what went wrong. */
1671 netdev_dbg(dev, "Tx queue start entry %ld dirty entry %ld\n",
1672 tp->cur_tx, tp->dirty_tx);
1673 for (i = 0; i < NUM_TX_DESC; i++)
1674 netdev_dbg(dev, "Tx descriptor %d is %08x%s\n",
1675 i, RTL_R32(TxStatus0 + (i * 4)),
1676 i == tp->dirty_tx % NUM_TX_DESC ?
1677 " (queue head)" : "");
1678
1679 tp->xstats.tx_timeouts++;
1680
1681 /* disable Tx ASAP, if not already */
1682 tmp8 = RTL_R8 (ChipCmd);
1683 if (tmp8 & CmdTxEnb)
1684 RTL_W8 (ChipCmd, CmdRxEnb);
1685
1686 spin_lock_bh(&tp->rx_lock);
1687 /* Disable interrupts by clearing the interrupt mask. */
1688 RTL_W16 (IntrMask, 0x0000);
1689
1690 /* Stop a shared interrupt from scavenging while we are. */
1691 spin_lock_irq(&tp->lock);
1692 rtl8139_tx_clear (tp);
1693 spin_unlock_irq(&tp->lock);
1694
1695 /* ...and finally, reset everything */
1696 if (netif_running(dev)) {
1697 rtl8139_hw_start (dev);
1698 netif_wake_queue (dev);
1699 }
1700 spin_unlock_bh(&tp->rx_lock);
1701 }
1702
1703 static void rtl8139_tx_timeout (struct net_device *dev)
1704 {
1705 struct rtl8139_private *tp = netdev_priv(dev);
1706
1707 tp->watchdog_fired = 1;
1708 if (!tp->have_thread) {
1709 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1710 schedule_delayed_work(&tp->thread, next_tick);
1711 }
1712 }
1713
1714 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb,
1715 struct net_device *dev)
1716 {
1717 struct rtl8139_private *tp = netdev_priv(dev);
1718 void __iomem *ioaddr = tp->mmio_addr;
1719 unsigned int entry;
1720 unsigned int len = skb->len;
1721 unsigned long flags;
1722
1723 /* Calculate the next Tx descriptor entry. */
1724 entry = tp->cur_tx % NUM_TX_DESC;
1725
1726 /* Note: the chip doesn't have auto-pad! */
1727 if (likely(len < TX_BUF_SIZE)) {
1728 if (len < ETH_ZLEN)
1729 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1730 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1731 dev_kfree_skb_any(skb);
1732 } else {
1733 dev_kfree_skb_any(skb);
1734 dev->stats.tx_dropped++;
1735 return NETDEV_TX_OK;
1736 }
1737
1738 spin_lock_irqsave(&tp->lock, flags);
1739 /*
1740 * Writing to TxStatus triggers a DMA transfer of the data
1741 * copied to tp->tx_buf[entry] above. Use a memory barrier
1742 * to make sure that the device sees the updated data.
1743 */
1744 wmb();
1745 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1746 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1747
1748 tp->cur_tx++;
1749
1750 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1751 netif_stop_queue (dev);
1752 spin_unlock_irqrestore(&tp->lock, flags);
1753
1754 netif_dbg(tp, tx_queued, dev, "Queued Tx packet size %u to slot %d\n",
1755 len, entry);
1756
1757 return NETDEV_TX_OK;
1758 }
1759
1760
1761 static void rtl8139_tx_interrupt (struct net_device *dev,
1762 struct rtl8139_private *tp,
1763 void __iomem *ioaddr)
1764 {
1765 unsigned long dirty_tx, tx_left;
1766
1767 assert (dev != NULL);
1768 assert (ioaddr != NULL);
1769
1770 dirty_tx = tp->dirty_tx;
1771 tx_left = tp->cur_tx - dirty_tx;
1772 while (tx_left > 0) {
1773 int entry = dirty_tx % NUM_TX_DESC;
1774 int txstatus;
1775
1776 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1777
1778 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1779 break; /* It still hasn't been Txed */
1780
1781 /* Note: TxCarrierLost is always asserted at 100mbps. */
1782 if (txstatus & (TxOutOfWindow | TxAborted)) {
1783 /* There was an major error, log it. */
1784 netif_dbg(tp, tx_err, dev, "Transmit error, Tx status %08x\n",
1785 txstatus);
1786 dev->stats.tx_errors++;
1787 if (txstatus & TxAborted) {
1788 dev->stats.tx_aborted_errors++;
1789 RTL_W32 (TxConfig, TxClearAbt);
1790 RTL_W16 (IntrStatus, TxErr);
1791 wmb();
1792 }
1793 if (txstatus & TxCarrierLost)
1794 dev->stats.tx_carrier_errors++;
1795 if (txstatus & TxOutOfWindow)
1796 dev->stats.tx_window_errors++;
1797 } else {
1798 if (txstatus & TxUnderrun) {
1799 /* Add 64 to the Tx FIFO threshold. */
1800 if (tp->tx_flag < 0x00300000)
1801 tp->tx_flag += 0x00020000;
1802 dev->stats.tx_fifo_errors++;
1803 }
1804 dev->stats.collisions += (txstatus >> 24) & 15;
1805 u64_stats_update_begin(&tp->tx_stats.syncp);
1806 tp->tx_stats.packets++;
1807 tp->tx_stats.bytes += txstatus & 0x7ff;
1808 u64_stats_update_end(&tp->tx_stats.syncp);
1809 }
1810
1811 dirty_tx++;
1812 tx_left--;
1813 }
1814
1815 #ifndef RTL8139_NDEBUG
1816 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1817 netdev_err(dev, "Out-of-sync dirty pointer, %ld vs. %ld\n",
1818 dirty_tx, tp->cur_tx);
1819 dirty_tx += NUM_TX_DESC;
1820 }
1821 #endif /* RTL8139_NDEBUG */
1822
1823 /* only wake the queue if we did work, and the queue is stopped */
1824 if (tp->dirty_tx != dirty_tx) {
1825 tp->dirty_tx = dirty_tx;
1826 mb();
1827 netif_wake_queue (dev);
1828 }
1829 }
1830
1831
1832 /* TODO: clean this up! Rx reset need not be this intensive */
1833 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1834 struct rtl8139_private *tp, void __iomem *ioaddr)
1835 {
1836 u8 tmp8;
1837 #ifdef CONFIG_8139_OLD_RX_RESET
1838 int tmp_work;
1839 #endif
1840
1841 netif_dbg(tp, rx_err, dev, "Ethernet frame had errors, status %08x\n",
1842 rx_status);
1843 dev->stats.rx_errors++;
1844 if (!(rx_status & RxStatusOK)) {
1845 if (rx_status & RxTooLong) {
1846 netdev_dbg(dev, "Oversized Ethernet frame, status %04x!\n",
1847 rx_status);
1848 /* A.C.: The chip hangs here. */
1849 }
1850 if (rx_status & (RxBadSymbol | RxBadAlign))
1851 dev->stats.rx_frame_errors++;
1852 if (rx_status & (RxRunt | RxTooLong))
1853 dev->stats.rx_length_errors++;
1854 if (rx_status & RxCRCErr)
1855 dev->stats.rx_crc_errors++;
1856 } else {
1857 tp->xstats.rx_lost_in_ring++;
1858 }
1859
1860 #ifndef CONFIG_8139_OLD_RX_RESET
1861 tmp8 = RTL_R8 (ChipCmd);
1862 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1863 RTL_W8 (ChipCmd, tmp8);
1864 RTL_W32 (RxConfig, tp->rx_config);
1865 tp->cur_rx = 0;
1866 #else
1867 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1868
1869 /* disable receive */
1870 RTL_W8_F (ChipCmd, CmdTxEnb);
1871 tmp_work = 200;
1872 while (--tmp_work > 0) {
1873 udelay(1);
1874 tmp8 = RTL_R8 (ChipCmd);
1875 if (!(tmp8 & CmdRxEnb))
1876 break;
1877 }
1878 if (tmp_work <= 0)
1879 netdev_warn(dev, "rx stop wait too long\n");
1880 /* restart receive */
1881 tmp_work = 200;
1882 while (--tmp_work > 0) {
1883 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1884 udelay(1);
1885 tmp8 = RTL_R8 (ChipCmd);
1886 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1887 break;
1888 }
1889 if (tmp_work <= 0)
1890 netdev_warn(dev, "tx/rx enable wait too long\n");
1891
1892 /* and reinitialize all rx related registers */
1893 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1894 /* Must enable Tx/Rx before setting transfer thresholds! */
1895 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1896
1897 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1898 RTL_W32 (RxConfig, tp->rx_config);
1899 tp->cur_rx = 0;
1900
1901 netdev_dbg(dev, "init buffer addresses\n");
1902
1903 /* Lock Config[01234] and BMCR register writes */
1904 RTL_W8 (Cfg9346, Cfg9346_Lock);
1905
1906 /* init Rx ring buffer DMA address */
1907 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1908
1909 /* A.C.: Reset the multicast list. */
1910 __set_rx_mode (dev);
1911 #endif
1912 }
1913
1914 #if RX_BUF_IDX == 3
1915 static inline void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1916 u32 offset, unsigned int size)
1917 {
1918 u32 left = RX_BUF_LEN - offset;
1919
1920 if (size > left) {
1921 skb_copy_to_linear_data(skb, ring + offset, left);
1922 skb_copy_to_linear_data_offset(skb, left, ring, size - left);
1923 } else
1924 skb_copy_to_linear_data(skb, ring + offset, size);
1925 }
1926 #endif
1927
1928 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1929 {
1930 void __iomem *ioaddr = tp->mmio_addr;
1931 u16 status;
1932
1933 status = RTL_R16 (IntrStatus) & RxAckBits;
1934
1935 /* Clear out errors and receive interrupts */
1936 if (likely(status != 0)) {
1937 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1938 tp->dev->stats.rx_errors++;
1939 if (status & RxFIFOOver)
1940 tp->dev->stats.rx_fifo_errors++;
1941 }
1942 RTL_W16_F (IntrStatus, RxAckBits);
1943 }
1944 }
1945
1946 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1947 int budget)
1948 {
1949 void __iomem *ioaddr = tp->mmio_addr;
1950 int received = 0;
1951 unsigned char *rx_ring = tp->rx_ring;
1952 unsigned int cur_rx = tp->cur_rx;
1953 unsigned int rx_size = 0;
1954
1955 netdev_dbg(dev, "In %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n",
1956 __func__, (u16)cur_rx,
1957 RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd));
1958
1959 while (netif_running(dev) && received < budget &&
1960 (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1961 u32 ring_offset = cur_rx % RX_BUF_LEN;
1962 u32 rx_status;
1963 unsigned int pkt_size;
1964 struct sk_buff *skb;
1965
1966 rmb();
1967
1968 /* read size+status of next frame from DMA ring buffer */
1969 rx_status = le32_to_cpu (*(__le32 *) (rx_ring + ring_offset));
1970 rx_size = rx_status >> 16;
1971 if (likely(!(dev->features & NETIF_F_RXFCS)))
1972 pkt_size = rx_size - 4;
1973 else
1974 pkt_size = rx_size;
1975
1976 netif_dbg(tp, rx_status, dev, "%s() status %04x, size %04x, cur %04x\n",
1977 __func__, rx_status, rx_size, cur_rx);
1978 #if RTL8139_DEBUG > 2
1979 print_hex_dump(KERN_DEBUG, "Frame contents: ",
1980 DUMP_PREFIX_OFFSET, 16, 1,
1981 &rx_ring[ring_offset], 70, true);
1982 #endif
1983
1984 /* Packet copy from FIFO still in progress.
1985 * Theoretically, this should never happen
1986 * since EarlyRx is disabled.
1987 */
1988 if (unlikely(rx_size == 0xfff0)) {
1989 if (!tp->fifo_copy_timeout)
1990 tp->fifo_copy_timeout = jiffies + 2;
1991 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
1992 netdev_dbg(dev, "hung FIFO. Reset\n");
1993 rx_size = 0;
1994 goto no_early_rx;
1995 }
1996 netif_dbg(tp, intr, dev, "fifo copy in progress\n");
1997 tp->xstats.early_rx++;
1998 break;
1999 }
2000
2001 no_early_rx:
2002 tp->fifo_copy_timeout = 0;
2003
2004 /* If Rx err or invalid rx_size/rx_status received
2005 * (which happens if we get lost in the ring),
2006 * Rx process gets reset, so we abort any further
2007 * Rx processing.
2008 */
2009 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
2010 (rx_size < 8) ||
2011 (!(rx_status & RxStatusOK)))) {
2012 if ((dev->features & NETIF_F_RXALL) &&
2013 (rx_size <= (MAX_ETH_FRAME_SIZE + 4)) &&
2014 (rx_size >= 8) &&
2015 (!(rx_status & RxStatusOK))) {
2016 /* Length is at least mostly OK, but pkt has
2017 * error. I'm hoping we can handle some of these
2018 * errors without resetting the chip. --Ben
2019 */
2020 dev->stats.rx_errors++;
2021 if (rx_status & RxCRCErr) {
2022 dev->stats.rx_crc_errors++;
2023 goto keep_pkt;
2024 }
2025 if (rx_status & RxRunt) {
2026 dev->stats.rx_length_errors++;
2027 goto keep_pkt;
2028 }
2029 }
2030 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
2031 received = -1;
2032 goto out;
2033 }
2034
2035 keep_pkt:
2036 /* Malloc up new buffer, compatible with net-2e. */
2037 /* Omit the four octet CRC from the length. */
2038
2039 skb = netdev_alloc_skb_ip_align(dev, pkt_size);
2040 if (likely(skb)) {
2041 #if RX_BUF_IDX == 3
2042 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
2043 #else
2044 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size);
2045 #endif
2046 skb_put (skb, pkt_size);
2047
2048 skb->protocol = eth_type_trans (skb, dev);
2049
2050 u64_stats_update_begin(&tp->rx_stats.syncp);
2051 tp->rx_stats.packets++;
2052 tp->rx_stats.bytes += pkt_size;
2053 u64_stats_update_end(&tp->rx_stats.syncp);
2054
2055 netif_receive_skb (skb);
2056 } else {
2057 dev->stats.rx_dropped++;
2058 }
2059 received++;
2060
2061 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2062 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2063
2064 rtl8139_isr_ack(tp);
2065 }
2066
2067 if (unlikely(!received || rx_size == 0xfff0))
2068 rtl8139_isr_ack(tp);
2069
2070 netdev_dbg(dev, "Done %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n",
2071 __func__, cur_rx,
2072 RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd));
2073
2074 tp->cur_rx = cur_rx;
2075
2076 /*
2077 * The receive buffer should be mostly empty.
2078 * Tell NAPI to reenable the Rx irq.
2079 */
2080 if (tp->fifo_copy_timeout)
2081 received = budget;
2082
2083 out:
2084 return received;
2085 }
2086
2087
2088 static void rtl8139_weird_interrupt (struct net_device *dev,
2089 struct rtl8139_private *tp,
2090 void __iomem *ioaddr,
2091 int status, int link_changed)
2092 {
2093 netdev_dbg(dev, "Abnormal interrupt, status %08x\n", status);
2094
2095 assert (dev != NULL);
2096 assert (tp != NULL);
2097 assert (ioaddr != NULL);
2098
2099 /* Update the error count. */
2100 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2101 RTL_W32 (RxMissed, 0);
2102
2103 if ((status & RxUnderrun) && link_changed &&
2104 (tp->drv_flags & HAS_LNK_CHNG)) {
2105 rtl_check_media(dev, 0);
2106 status &= ~RxUnderrun;
2107 }
2108
2109 if (status & (RxUnderrun | RxErr))
2110 dev->stats.rx_errors++;
2111
2112 if (status & PCSTimeout)
2113 dev->stats.rx_length_errors++;
2114 if (status & RxUnderrun)
2115 dev->stats.rx_fifo_errors++;
2116 if (status & PCIErr) {
2117 u16 pci_cmd_status;
2118 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2119 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2120
2121 netdev_err(dev, "PCI Bus error %04x\n", pci_cmd_status);
2122 }
2123 }
2124
2125 static int rtl8139_poll(struct napi_struct *napi, int budget)
2126 {
2127 struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi);
2128 struct net_device *dev = tp->dev;
2129 void __iomem *ioaddr = tp->mmio_addr;
2130 int work_done;
2131
2132 spin_lock(&tp->rx_lock);
2133 work_done = 0;
2134 if (likely(RTL_R16(IntrStatus) & RxAckBits))
2135 work_done += rtl8139_rx(dev, tp, budget);
2136
2137 if (work_done < budget) {
2138 unsigned long flags;
2139 /*
2140 * Order is important since data can get interrupted
2141 * again when we think we are done.
2142 */
2143 spin_lock_irqsave(&tp->lock, flags);
2144 __napi_complete(napi);
2145 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2146 spin_unlock_irqrestore(&tp->lock, flags);
2147 }
2148 spin_unlock(&tp->rx_lock);
2149
2150 return work_done;
2151 }
2152
2153 /* The interrupt handler does all of the Rx thread work and cleans up
2154 after the Tx thread. */
2155 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance)
2156 {
2157 struct net_device *dev = (struct net_device *) dev_instance;
2158 struct rtl8139_private *tp = netdev_priv(dev);
2159 void __iomem *ioaddr = tp->mmio_addr;
2160 u16 status, ackstat;
2161 int link_changed = 0; /* avoid bogus "uninit" warning */
2162 int handled = 0;
2163
2164 spin_lock (&tp->lock);
2165 status = RTL_R16 (IntrStatus);
2166
2167 /* shared irq? */
2168 if (unlikely((status & rtl8139_intr_mask) == 0))
2169 goto out;
2170
2171 handled = 1;
2172
2173 /* h/w no longer present (hotplug?) or major error, bail */
2174 if (unlikely(status == 0xFFFF))
2175 goto out;
2176
2177 /* close possible race's with dev_close */
2178 if (unlikely(!netif_running(dev))) {
2179 RTL_W16 (IntrMask, 0);
2180 goto out;
2181 }
2182
2183 /* Acknowledge all of the current interrupt sources ASAP, but
2184 an first get an additional status bit from CSCR. */
2185 if (unlikely(status & RxUnderrun))
2186 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2187
2188 ackstat = status & ~(RxAckBits | TxErr);
2189 if (ackstat)
2190 RTL_W16 (IntrStatus, ackstat);
2191
2192 /* Receive packets are processed by poll routine.
2193 If not running start it now. */
2194 if (status & RxAckBits){
2195 if (napi_schedule_prep(&tp->napi)) {
2196 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2197 __napi_schedule(&tp->napi);
2198 }
2199 }
2200
2201 /* Check uncommon events with one test. */
2202 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2203 rtl8139_weird_interrupt (dev, tp, ioaddr,
2204 status, link_changed);
2205
2206 if (status & (TxOK | TxErr)) {
2207 rtl8139_tx_interrupt (dev, tp, ioaddr);
2208 if (status & TxErr)
2209 RTL_W16 (IntrStatus, TxErr);
2210 }
2211 out:
2212 spin_unlock (&tp->lock);
2213
2214 netdev_dbg(dev, "exiting interrupt, intr_status=%#4.4x\n",
2215 RTL_R16(IntrStatus));
2216 return IRQ_RETVAL(handled);
2217 }
2218
2219 #ifdef CONFIG_NET_POLL_CONTROLLER
2220 /*
2221 * Polling receive - used by netconsole and other diagnostic tools
2222 * to allow network i/o with interrupts disabled.
2223 */
2224 static void rtl8139_poll_controller(struct net_device *dev)
2225 {
2226 struct rtl8139_private *tp = netdev_priv(dev);
2227 const int irq = tp->pci_dev->irq;
2228
2229 disable_irq(irq);
2230 rtl8139_interrupt(irq, dev);
2231 enable_irq(irq);
2232 }
2233 #endif
2234
2235 static int rtl8139_set_mac_address(struct net_device *dev, void *p)
2236 {
2237 struct rtl8139_private *tp = netdev_priv(dev);
2238 void __iomem *ioaddr = tp->mmio_addr;
2239 struct sockaddr *addr = p;
2240
2241 if (!is_valid_ether_addr(addr->sa_data))
2242 return -EADDRNOTAVAIL;
2243
2244 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2245
2246 spin_lock_irq(&tp->lock);
2247
2248 RTL_W8_F(Cfg9346, Cfg9346_Unlock);
2249 RTL_W32_F(MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
2250 RTL_W32_F(MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
2251 RTL_W8_F(Cfg9346, Cfg9346_Lock);
2252
2253 spin_unlock_irq(&tp->lock);
2254
2255 return 0;
2256 }
2257
2258 static int rtl8139_close (struct net_device *dev)
2259 {
2260 struct rtl8139_private *tp = netdev_priv(dev);
2261 void __iomem *ioaddr = tp->mmio_addr;
2262 unsigned long flags;
2263
2264 netif_stop_queue(dev);
2265 napi_disable(&tp->napi);
2266
2267 netif_dbg(tp, ifdown, dev, "Shutting down ethercard, status was 0x%04x\n",
2268 RTL_R16(IntrStatus));
2269
2270 spin_lock_irqsave (&tp->lock, flags);
2271
2272 /* Stop the chip's Tx and Rx DMA processes. */
2273 RTL_W8 (ChipCmd, 0);
2274
2275 /* Disable interrupts by clearing the interrupt mask. */
2276 RTL_W16 (IntrMask, 0);
2277
2278 /* Update the error counts. */
2279 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2280 RTL_W32 (RxMissed, 0);
2281
2282 spin_unlock_irqrestore (&tp->lock, flags);
2283
2284 free_irq(tp->pci_dev->irq, dev);
2285
2286 rtl8139_tx_clear (tp);
2287
2288 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
2289 tp->rx_ring, tp->rx_ring_dma);
2290 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
2291 tp->tx_bufs, tp->tx_bufs_dma);
2292 tp->rx_ring = NULL;
2293 tp->tx_bufs = NULL;
2294
2295 /* Green! Put the chip in low-power mode. */
2296 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2297
2298 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2299 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2300
2301 return 0;
2302 }
2303
2304
2305 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2306 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2307 other threads or interrupts aren't messing with the 8139. */
2308 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2309 {
2310 struct rtl8139_private *tp = netdev_priv(dev);
2311 void __iomem *ioaddr = tp->mmio_addr;
2312
2313 spin_lock_irq(&tp->lock);
2314 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
2315 u8 cfg3 = RTL_R8 (Config3);
2316 u8 cfg5 = RTL_R8 (Config5);
2317
2318 wol->supported = WAKE_PHY | WAKE_MAGIC
2319 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2320
2321 wol->wolopts = 0;
2322 if (cfg3 & Cfg3_LinkUp)
2323 wol->wolopts |= WAKE_PHY;
2324 if (cfg3 & Cfg3_Magic)
2325 wol->wolopts |= WAKE_MAGIC;
2326 /* (KON)FIXME: See how netdev_set_wol() handles the
2327 following constants. */
2328 if (cfg5 & Cfg5_UWF)
2329 wol->wolopts |= WAKE_UCAST;
2330 if (cfg5 & Cfg5_MWF)
2331 wol->wolopts |= WAKE_MCAST;
2332 if (cfg5 & Cfg5_BWF)
2333 wol->wolopts |= WAKE_BCAST;
2334 }
2335 spin_unlock_irq(&tp->lock);
2336 }
2337
2338
2339 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2340 that wol points to kernel memory and other threads or interrupts
2341 aren't messing with the 8139. */
2342 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2343 {
2344 struct rtl8139_private *tp = netdev_priv(dev);
2345 void __iomem *ioaddr = tp->mmio_addr;
2346 u32 support;
2347 u8 cfg3, cfg5;
2348
2349 support = ((rtl_chip_info[tp->chipset].flags & HasLWake)
2350 ? (WAKE_PHY | WAKE_MAGIC
2351 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2352 : 0);
2353 if (wol->wolopts & ~support)
2354 return -EINVAL;
2355
2356 spin_lock_irq(&tp->lock);
2357 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2358 if (wol->wolopts & WAKE_PHY)
2359 cfg3 |= Cfg3_LinkUp;
2360 if (wol->wolopts & WAKE_MAGIC)
2361 cfg3 |= Cfg3_Magic;
2362 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2363 RTL_W8 (Config3, cfg3);
2364 RTL_W8 (Cfg9346, Cfg9346_Lock);
2365
2366 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2367 /* (KON)FIXME: These are untested. We may have to set the
2368 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2369 documentation. */
2370 if (wol->wolopts & WAKE_UCAST)
2371 cfg5 |= Cfg5_UWF;
2372 if (wol->wolopts & WAKE_MCAST)
2373 cfg5 |= Cfg5_MWF;
2374 if (wol->wolopts & WAKE_BCAST)
2375 cfg5 |= Cfg5_BWF;
2376 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2377 spin_unlock_irq(&tp->lock);
2378
2379 return 0;
2380 }
2381
2382 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2383 {
2384 struct rtl8139_private *tp = netdev_priv(dev);
2385 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2386 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2387 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
2388 info->regdump_len = tp->regs_len;
2389 }
2390
2391 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2392 {
2393 struct rtl8139_private *tp = netdev_priv(dev);
2394 spin_lock_irq(&tp->lock);
2395 mii_ethtool_gset(&tp->mii, cmd);
2396 spin_unlock_irq(&tp->lock);
2397 return 0;
2398 }
2399
2400 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2401 {
2402 struct rtl8139_private *tp = netdev_priv(dev);
2403 int rc;
2404 spin_lock_irq(&tp->lock);
2405 rc = mii_ethtool_sset(&tp->mii, cmd);
2406 spin_unlock_irq(&tp->lock);
2407 return rc;
2408 }
2409
2410 static int rtl8139_nway_reset(struct net_device *dev)
2411 {
2412 struct rtl8139_private *tp = netdev_priv(dev);
2413 return mii_nway_restart(&tp->mii);
2414 }
2415
2416 static u32 rtl8139_get_link(struct net_device *dev)
2417 {
2418 struct rtl8139_private *tp = netdev_priv(dev);
2419 return mii_link_ok(&tp->mii);
2420 }
2421
2422 static u32 rtl8139_get_msglevel(struct net_device *dev)
2423 {
2424 struct rtl8139_private *tp = netdev_priv(dev);
2425 return tp->msg_enable;
2426 }
2427
2428 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2429 {
2430 struct rtl8139_private *tp = netdev_priv(dev);
2431 tp->msg_enable = datum;
2432 }
2433
2434 static int rtl8139_get_regs_len(struct net_device *dev)
2435 {
2436 struct rtl8139_private *tp;
2437 /* TODO: we are too slack to do reg dumping for pio, for now */
2438 if (use_io)
2439 return 0;
2440 tp = netdev_priv(dev);
2441 return tp->regs_len;
2442 }
2443
2444 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2445 {
2446 struct rtl8139_private *tp;
2447
2448 /* TODO: we are too slack to do reg dumping for pio, for now */
2449 if (use_io)
2450 return;
2451 tp = netdev_priv(dev);
2452
2453 regs->version = RTL_REGS_VER;
2454
2455 spin_lock_irq(&tp->lock);
2456 memcpy_fromio(regbuf, tp->mmio_addr, regs->len);
2457 spin_unlock_irq(&tp->lock);
2458 }
2459
2460 static int rtl8139_get_sset_count(struct net_device *dev, int sset)
2461 {
2462 switch (sset) {
2463 case ETH_SS_STATS:
2464 return RTL_NUM_STATS;
2465 default:
2466 return -EOPNOTSUPP;
2467 }
2468 }
2469
2470 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2471 {
2472 struct rtl8139_private *tp = netdev_priv(dev);
2473
2474 data[0] = tp->xstats.early_rx;
2475 data[1] = tp->xstats.tx_buf_mapped;
2476 data[2] = tp->xstats.tx_timeouts;
2477 data[3] = tp->xstats.rx_lost_in_ring;
2478 }
2479
2480 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2481 {
2482 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2483 }
2484
2485 static const struct ethtool_ops rtl8139_ethtool_ops = {
2486 .get_drvinfo = rtl8139_get_drvinfo,
2487 .get_settings = rtl8139_get_settings,
2488 .set_settings = rtl8139_set_settings,
2489 .get_regs_len = rtl8139_get_regs_len,
2490 .get_regs = rtl8139_get_regs,
2491 .nway_reset = rtl8139_nway_reset,
2492 .get_link = rtl8139_get_link,
2493 .get_msglevel = rtl8139_get_msglevel,
2494 .set_msglevel = rtl8139_set_msglevel,
2495 .get_wol = rtl8139_get_wol,
2496 .set_wol = rtl8139_set_wol,
2497 .get_strings = rtl8139_get_strings,
2498 .get_sset_count = rtl8139_get_sset_count,
2499 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2500 };
2501
2502 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2503 {
2504 struct rtl8139_private *tp = netdev_priv(dev);
2505 int rc;
2506
2507 if (!netif_running(dev))
2508 return -EINVAL;
2509
2510 spin_lock_irq(&tp->lock);
2511 rc = generic_mii_ioctl(&tp->mii, if_mii(rq), cmd, NULL);
2512 spin_unlock_irq(&tp->lock);
2513
2514 return rc;
2515 }
2516
2517
2518 static struct rtnl_link_stats64 *
2519 rtl8139_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
2520 {
2521 struct rtl8139_private *tp = netdev_priv(dev);
2522 void __iomem *ioaddr = tp->mmio_addr;
2523 unsigned long flags;
2524 unsigned int start;
2525
2526 if (netif_running(dev)) {
2527 spin_lock_irqsave (&tp->lock, flags);
2528 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2529 RTL_W32 (RxMissed, 0);
2530 spin_unlock_irqrestore (&tp->lock, flags);
2531 }
2532
2533 netdev_stats_to_stats64(stats, &dev->stats);
2534
2535 do {
2536 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
2537 stats->rx_packets = tp->rx_stats.packets;
2538 stats->rx_bytes = tp->rx_stats.bytes;
2539 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
2540
2541 do {
2542 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
2543 stats->tx_packets = tp->tx_stats.packets;
2544 stats->tx_bytes = tp->tx_stats.bytes;
2545 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
2546
2547 return stats;
2548 }
2549
2550 /* Set or clear the multicast filter for this adaptor.
2551 This routine is not state sensitive and need not be SMP locked. */
2552
2553 static void __set_rx_mode (struct net_device *dev)
2554 {
2555 struct rtl8139_private *tp = netdev_priv(dev);
2556 void __iomem *ioaddr = tp->mmio_addr;
2557 u32 mc_filter[2]; /* Multicast hash filter */
2558 int rx_mode;
2559 u32 tmp;
2560
2561 netdev_dbg(dev, "rtl8139_set_rx_mode(%04x) done -- Rx config %08x\n",
2562 dev->flags, RTL_R32(RxConfig));
2563
2564 /* Note: do not reorder, GCC is clever about common statements. */
2565 if (dev->flags & IFF_PROMISC) {
2566 rx_mode =
2567 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2568 AcceptAllPhys;
2569 mc_filter[1] = mc_filter[0] = 0xffffffff;
2570 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
2571 (dev->flags & IFF_ALLMULTI)) {
2572 /* Too many to filter perfectly -- accept all multicasts. */
2573 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2574 mc_filter[1] = mc_filter[0] = 0xffffffff;
2575 } else {
2576 struct netdev_hw_addr *ha;
2577 rx_mode = AcceptBroadcast | AcceptMyPhys;
2578 mc_filter[1] = mc_filter[0] = 0;
2579 netdev_for_each_mc_addr(ha, dev) {
2580 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2581
2582 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2583 rx_mode |= AcceptMulticast;
2584 }
2585 }
2586
2587 if (dev->features & NETIF_F_RXALL)
2588 rx_mode |= (AcceptErr | AcceptRunt);
2589
2590 /* We can safely update without stopping the chip. */
2591 tmp = rtl8139_rx_config | rx_mode;
2592 if (tp->rx_config != tmp) {
2593 RTL_W32_F (RxConfig, tmp);
2594 tp->rx_config = tmp;
2595 }
2596 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2597 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2598 }
2599
2600 static void rtl8139_set_rx_mode (struct net_device *dev)
2601 {
2602 unsigned long flags;
2603 struct rtl8139_private *tp = netdev_priv(dev);
2604
2605 spin_lock_irqsave (&tp->lock, flags);
2606 __set_rx_mode(dev);
2607 spin_unlock_irqrestore (&tp->lock, flags);
2608 }
2609
2610 #ifdef CONFIG_PM
2611
2612 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
2613 {
2614 struct net_device *dev = pci_get_drvdata (pdev);
2615 struct rtl8139_private *tp = netdev_priv(dev);
2616 void __iomem *ioaddr = tp->mmio_addr;
2617 unsigned long flags;
2618
2619 pci_save_state (pdev);
2620
2621 if (!netif_running (dev))
2622 return 0;
2623
2624 netif_device_detach (dev);
2625
2626 spin_lock_irqsave (&tp->lock, flags);
2627
2628 /* Disable interrupts, stop Tx and Rx. */
2629 RTL_W16 (IntrMask, 0);
2630 RTL_W8 (ChipCmd, 0);
2631
2632 /* Update the error counts. */
2633 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2634 RTL_W32 (RxMissed, 0);
2635
2636 spin_unlock_irqrestore (&tp->lock, flags);
2637
2638 pci_set_power_state (pdev, PCI_D3hot);
2639
2640 return 0;
2641 }
2642
2643
2644 static int rtl8139_resume (struct pci_dev *pdev)
2645 {
2646 struct net_device *dev = pci_get_drvdata (pdev);
2647
2648 pci_restore_state (pdev);
2649 if (!netif_running (dev))
2650 return 0;
2651 pci_set_power_state (pdev, PCI_D0);
2652 rtl8139_init_ring (dev);
2653 rtl8139_hw_start (dev);
2654 netif_device_attach (dev);
2655 return 0;
2656 }
2657
2658 #endif /* CONFIG_PM */
2659
2660
2661 static struct pci_driver rtl8139_pci_driver = {
2662 .name = DRV_NAME,
2663 .id_table = rtl8139_pci_tbl,
2664 .probe = rtl8139_init_one,
2665 .remove = rtl8139_remove_one,
2666 #ifdef CONFIG_PM
2667 .suspend = rtl8139_suspend,
2668 .resume = rtl8139_resume,
2669 #endif /* CONFIG_PM */
2670 };
2671
2672
2673 static int __init rtl8139_init_module (void)
2674 {
2675 /* when we're a module, we always print a version message,
2676 * even if no 8139 board is found.
2677 */
2678 #ifdef MODULE
2679 pr_info(RTL8139_DRIVER_NAME "\n");
2680 #endif
2681
2682 return pci_register_driver(&rtl8139_pci_driver);
2683 }
2684
2685
2686 static void __exit rtl8139_cleanup_module (void)
2687 {
2688 pci_unregister_driver (&rtl8139_pci_driver);
2689 }
2690
2691
2692 module_init(rtl8139_init_module);
2693 module_exit(rtl8139_cleanup_module);
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