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[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / realtek / r8169.c
1 /*
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28 #include <linux/pci-aspm.h>
29 #include <linux/prefetch.h>
30 #include <linux/ipv6.h>
31 #include <net/ip6_checksum.h>
32
33 #include <asm/io.h>
34 #include <asm/irq.h>
35
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
39
40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
45 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
47 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
48 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
49 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
50 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
51 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
52 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
53 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
54 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
55 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
56 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
57 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
58 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
59
60 #ifdef RTL8169_DEBUG
61 #define assert(expr) \
62 if (!(expr)) { \
63 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
64 #expr,__FILE__,__func__,__LINE__); \
65 }
66 #define dprintk(fmt, args...) \
67 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
68 #else
69 #define assert(expr) do {} while (0)
70 #define dprintk(fmt, args...) do {} while (0)
71 #endif /* RTL8169_DEBUG */
72
73 #define R8169_MSG_DEFAULT \
74 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
75
76 #define TX_SLOTS_AVAIL(tp) \
77 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
78
79 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
80 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
81 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
82
83 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
84 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
85 static const int multicast_filter_limit = 32;
86
87 #define MAX_READ_REQUEST_SHIFT 12
88 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
89 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
90
91 #define R8169_REGS_SIZE 256
92 #define R8169_NAPI_WEIGHT 64
93 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
94 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
95 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
96 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
97
98 #define RTL8169_TX_TIMEOUT (6*HZ)
99 #define RTL8169_PHY_TIMEOUT (10*HZ)
100
101 /* write/read MMIO register */
102 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
103 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
104 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
105 #define RTL_R8(reg) readb (ioaddr + (reg))
106 #define RTL_R16(reg) readw (ioaddr + (reg))
107 #define RTL_R32(reg) readl (ioaddr + (reg))
108
109 enum mac_version {
110 RTL_GIGA_MAC_VER_01 = 0,
111 RTL_GIGA_MAC_VER_02,
112 RTL_GIGA_MAC_VER_03,
113 RTL_GIGA_MAC_VER_04,
114 RTL_GIGA_MAC_VER_05,
115 RTL_GIGA_MAC_VER_06,
116 RTL_GIGA_MAC_VER_07,
117 RTL_GIGA_MAC_VER_08,
118 RTL_GIGA_MAC_VER_09,
119 RTL_GIGA_MAC_VER_10,
120 RTL_GIGA_MAC_VER_11,
121 RTL_GIGA_MAC_VER_12,
122 RTL_GIGA_MAC_VER_13,
123 RTL_GIGA_MAC_VER_14,
124 RTL_GIGA_MAC_VER_15,
125 RTL_GIGA_MAC_VER_16,
126 RTL_GIGA_MAC_VER_17,
127 RTL_GIGA_MAC_VER_18,
128 RTL_GIGA_MAC_VER_19,
129 RTL_GIGA_MAC_VER_20,
130 RTL_GIGA_MAC_VER_21,
131 RTL_GIGA_MAC_VER_22,
132 RTL_GIGA_MAC_VER_23,
133 RTL_GIGA_MAC_VER_24,
134 RTL_GIGA_MAC_VER_25,
135 RTL_GIGA_MAC_VER_26,
136 RTL_GIGA_MAC_VER_27,
137 RTL_GIGA_MAC_VER_28,
138 RTL_GIGA_MAC_VER_29,
139 RTL_GIGA_MAC_VER_30,
140 RTL_GIGA_MAC_VER_31,
141 RTL_GIGA_MAC_VER_32,
142 RTL_GIGA_MAC_VER_33,
143 RTL_GIGA_MAC_VER_34,
144 RTL_GIGA_MAC_VER_35,
145 RTL_GIGA_MAC_VER_36,
146 RTL_GIGA_MAC_VER_37,
147 RTL_GIGA_MAC_VER_38,
148 RTL_GIGA_MAC_VER_39,
149 RTL_GIGA_MAC_VER_40,
150 RTL_GIGA_MAC_VER_41,
151 RTL_GIGA_MAC_VER_42,
152 RTL_GIGA_MAC_VER_43,
153 RTL_GIGA_MAC_VER_44,
154 RTL_GIGA_MAC_VER_45,
155 RTL_GIGA_MAC_VER_46,
156 RTL_GIGA_MAC_VER_47,
157 RTL_GIGA_MAC_VER_48,
158 RTL_GIGA_MAC_VER_49,
159 RTL_GIGA_MAC_VER_50,
160 RTL_GIGA_MAC_VER_51,
161 RTL_GIGA_MAC_NONE = 0xff,
162 };
163
164 enum rtl_tx_desc_version {
165 RTL_TD_0 = 0,
166 RTL_TD_1 = 1,
167 };
168
169 #define JUMBO_1K ETH_DATA_LEN
170 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
171 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
172 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
173 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
174
175 #define _R(NAME,TD,FW,SZ,B) { \
176 .name = NAME, \
177 .txd_version = TD, \
178 .fw_name = FW, \
179 .jumbo_max = SZ, \
180 .jumbo_tx_csum = B \
181 }
182
183 static const struct {
184 const char *name;
185 enum rtl_tx_desc_version txd_version;
186 const char *fw_name;
187 u16 jumbo_max;
188 bool jumbo_tx_csum;
189 } rtl_chip_infos[] = {
190 /* PCI devices. */
191 [RTL_GIGA_MAC_VER_01] =
192 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
193 [RTL_GIGA_MAC_VER_02] =
194 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
195 [RTL_GIGA_MAC_VER_03] =
196 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
197 [RTL_GIGA_MAC_VER_04] =
198 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
199 [RTL_GIGA_MAC_VER_05] =
200 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
201 [RTL_GIGA_MAC_VER_06] =
202 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
203 /* PCI-E devices. */
204 [RTL_GIGA_MAC_VER_07] =
205 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
206 [RTL_GIGA_MAC_VER_08] =
207 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
208 [RTL_GIGA_MAC_VER_09] =
209 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
210 [RTL_GIGA_MAC_VER_10] =
211 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
212 [RTL_GIGA_MAC_VER_11] =
213 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
214 [RTL_GIGA_MAC_VER_12] =
215 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
216 [RTL_GIGA_MAC_VER_13] =
217 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
218 [RTL_GIGA_MAC_VER_14] =
219 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
220 [RTL_GIGA_MAC_VER_15] =
221 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
222 [RTL_GIGA_MAC_VER_16] =
223 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
224 [RTL_GIGA_MAC_VER_17] =
225 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
226 [RTL_GIGA_MAC_VER_18] =
227 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
228 [RTL_GIGA_MAC_VER_19] =
229 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
230 [RTL_GIGA_MAC_VER_20] =
231 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
232 [RTL_GIGA_MAC_VER_21] =
233 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
234 [RTL_GIGA_MAC_VER_22] =
235 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
236 [RTL_GIGA_MAC_VER_23] =
237 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
238 [RTL_GIGA_MAC_VER_24] =
239 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
240 [RTL_GIGA_MAC_VER_25] =
241 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
242 JUMBO_9K, false),
243 [RTL_GIGA_MAC_VER_26] =
244 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
245 JUMBO_9K, false),
246 [RTL_GIGA_MAC_VER_27] =
247 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
248 [RTL_GIGA_MAC_VER_28] =
249 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
250 [RTL_GIGA_MAC_VER_29] =
251 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
252 JUMBO_1K, true),
253 [RTL_GIGA_MAC_VER_30] =
254 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
255 JUMBO_1K, true),
256 [RTL_GIGA_MAC_VER_31] =
257 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
258 [RTL_GIGA_MAC_VER_32] =
259 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
260 JUMBO_9K, false),
261 [RTL_GIGA_MAC_VER_33] =
262 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
263 JUMBO_9K, false),
264 [RTL_GIGA_MAC_VER_34] =
265 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
266 JUMBO_9K, false),
267 [RTL_GIGA_MAC_VER_35] =
268 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
269 JUMBO_9K, false),
270 [RTL_GIGA_MAC_VER_36] =
271 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
272 JUMBO_9K, false),
273 [RTL_GIGA_MAC_VER_37] =
274 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
275 JUMBO_1K, true),
276 [RTL_GIGA_MAC_VER_38] =
277 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
278 JUMBO_9K, false),
279 [RTL_GIGA_MAC_VER_39] =
280 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
281 JUMBO_1K, true),
282 [RTL_GIGA_MAC_VER_40] =
283 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
284 JUMBO_9K, false),
285 [RTL_GIGA_MAC_VER_41] =
286 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
287 [RTL_GIGA_MAC_VER_42] =
288 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
289 JUMBO_9K, false),
290 [RTL_GIGA_MAC_VER_43] =
291 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
292 JUMBO_1K, true),
293 [RTL_GIGA_MAC_VER_44] =
294 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2,
295 JUMBO_9K, false),
296 [RTL_GIGA_MAC_VER_45] =
297 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1,
298 JUMBO_9K, false),
299 [RTL_GIGA_MAC_VER_46] =
300 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2,
301 JUMBO_9K, false),
302 [RTL_GIGA_MAC_VER_47] =
303 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1,
304 JUMBO_1K, false),
305 [RTL_GIGA_MAC_VER_48] =
306 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2,
307 JUMBO_1K, false),
308 [RTL_GIGA_MAC_VER_49] =
309 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
310 JUMBO_9K, false),
311 [RTL_GIGA_MAC_VER_50] =
312 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
313 JUMBO_9K, false),
314 [RTL_GIGA_MAC_VER_51] =
315 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
316 JUMBO_9K, false),
317 };
318 #undef _R
319
320 enum cfg_version {
321 RTL_CFG_0 = 0x00,
322 RTL_CFG_1,
323 RTL_CFG_2
324 };
325
326 static const struct pci_device_id rtl8169_pci_tbl[] = {
327 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
328 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
329 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
330 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
331 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
332 { PCI_VENDOR_ID_DLINK, 0x4300,
333 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
334 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
335 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
336 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
337 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
338 { PCI_VENDOR_ID_LINKSYS, 0x1032,
339 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
340 { 0x0001, 0x8168,
341 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
342 {0,},
343 };
344
345 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
346
347 static int rx_buf_sz = 16383;
348 static int use_dac;
349 static struct {
350 u32 msg_enable;
351 } debug = { -1 };
352
353 enum rtl_registers {
354 MAC0 = 0, /* Ethernet hardware address. */
355 MAC4 = 4,
356 MAR0 = 8, /* Multicast filter. */
357 CounterAddrLow = 0x10,
358 CounterAddrHigh = 0x14,
359 TxDescStartAddrLow = 0x20,
360 TxDescStartAddrHigh = 0x24,
361 TxHDescStartAddrLow = 0x28,
362 TxHDescStartAddrHigh = 0x2c,
363 FLASH = 0x30,
364 ERSR = 0x36,
365 ChipCmd = 0x37,
366 TxPoll = 0x38,
367 IntrMask = 0x3c,
368 IntrStatus = 0x3e,
369
370 TxConfig = 0x40,
371 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
372 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
373
374 RxConfig = 0x44,
375 #define RX128_INT_EN (1 << 15) /* 8111c and later */
376 #define RX_MULTI_EN (1 << 14) /* 8111c only */
377 #define RXCFG_FIFO_SHIFT 13
378 /* No threshold before first PCI xfer */
379 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
380 #define RX_EARLY_OFF (1 << 11)
381 #define RXCFG_DMA_SHIFT 8
382 /* Unlimited maximum PCI burst. */
383 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
384
385 RxMissed = 0x4c,
386 Cfg9346 = 0x50,
387 Config0 = 0x51,
388 Config1 = 0x52,
389 Config2 = 0x53,
390 #define PME_SIGNAL (1 << 5) /* 8168c and later */
391
392 Config3 = 0x54,
393 Config4 = 0x55,
394 Config5 = 0x56,
395 MultiIntr = 0x5c,
396 PHYAR = 0x60,
397 PHYstatus = 0x6c,
398 RxMaxSize = 0xda,
399 CPlusCmd = 0xe0,
400 IntrMitigate = 0xe2,
401 RxDescAddrLow = 0xe4,
402 RxDescAddrHigh = 0xe8,
403 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
404
405 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
406
407 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
408
409 #define TxPacketMax (8064 >> 7)
410 #define EarlySize 0x27
411
412 FuncEvent = 0xf0,
413 FuncEventMask = 0xf4,
414 FuncPresetState = 0xf8,
415 IBCR0 = 0xf8,
416 IBCR2 = 0xf9,
417 IBIMR0 = 0xfa,
418 IBISR0 = 0xfb,
419 FuncForceEvent = 0xfc,
420 };
421
422 enum rtl8110_registers {
423 TBICSR = 0x64,
424 TBI_ANAR = 0x68,
425 TBI_LPAR = 0x6a,
426 };
427
428 enum rtl8168_8101_registers {
429 CSIDR = 0x64,
430 CSIAR = 0x68,
431 #define CSIAR_FLAG 0x80000000
432 #define CSIAR_WRITE_CMD 0x80000000
433 #define CSIAR_BYTE_ENABLE 0x0f
434 #define CSIAR_BYTE_ENABLE_SHIFT 12
435 #define CSIAR_ADDR_MASK 0x0fff
436 #define CSIAR_FUNC_CARD 0x00000000
437 #define CSIAR_FUNC_SDIO 0x00010000
438 #define CSIAR_FUNC_NIC 0x00020000
439 #define CSIAR_FUNC_NIC2 0x00010000
440 PMCH = 0x6f,
441 EPHYAR = 0x80,
442 #define EPHYAR_FLAG 0x80000000
443 #define EPHYAR_WRITE_CMD 0x80000000
444 #define EPHYAR_REG_MASK 0x1f
445 #define EPHYAR_REG_SHIFT 16
446 #define EPHYAR_DATA_MASK 0xffff
447 DLLPR = 0xd0,
448 #define PFM_EN (1 << 6)
449 #define TX_10M_PS_EN (1 << 7)
450 DBG_REG = 0xd1,
451 #define FIX_NAK_1 (1 << 4)
452 #define FIX_NAK_2 (1 << 3)
453 TWSI = 0xd2,
454 MCU = 0xd3,
455 #define NOW_IS_OOB (1 << 7)
456 #define TX_EMPTY (1 << 5)
457 #define RX_EMPTY (1 << 4)
458 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
459 #define EN_NDP (1 << 3)
460 #define EN_OOB_RESET (1 << 2)
461 #define LINK_LIST_RDY (1 << 1)
462 EFUSEAR = 0xdc,
463 #define EFUSEAR_FLAG 0x80000000
464 #define EFUSEAR_WRITE_CMD 0x80000000
465 #define EFUSEAR_READ_CMD 0x00000000
466 #define EFUSEAR_REG_MASK 0x03ff
467 #define EFUSEAR_REG_SHIFT 8
468 #define EFUSEAR_DATA_MASK 0xff
469 MISC_1 = 0xf2,
470 #define PFM_D3COLD_EN (1 << 6)
471 };
472
473 enum rtl8168_registers {
474 LED_FREQ = 0x1a,
475 EEE_LED = 0x1b,
476 ERIDR = 0x70,
477 ERIAR = 0x74,
478 #define ERIAR_FLAG 0x80000000
479 #define ERIAR_WRITE_CMD 0x80000000
480 #define ERIAR_READ_CMD 0x00000000
481 #define ERIAR_ADDR_BYTE_ALIGN 4
482 #define ERIAR_TYPE_SHIFT 16
483 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
484 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
485 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
486 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
487 #define ERIAR_MASK_SHIFT 12
488 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
489 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
490 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
491 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
492 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
493 EPHY_RXER_NUM = 0x7c,
494 OCPDR = 0xb0, /* OCP GPHY access */
495 #define OCPDR_WRITE_CMD 0x80000000
496 #define OCPDR_READ_CMD 0x00000000
497 #define OCPDR_REG_MASK 0x7f
498 #define OCPDR_GPHY_REG_SHIFT 16
499 #define OCPDR_DATA_MASK 0xffff
500 OCPAR = 0xb4,
501 #define OCPAR_FLAG 0x80000000
502 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
503 #define OCPAR_GPHY_READ_CMD 0x0000f060
504 GPHY_OCP = 0xb8,
505 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
506 MISC = 0xf0, /* 8168e only. */
507 #define TXPLA_RST (1 << 29)
508 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
509 #define PWM_EN (1 << 22)
510 #define RXDV_GATED_EN (1 << 19)
511 #define EARLY_TALLY_EN (1 << 16)
512 };
513
514 enum rtl_register_content {
515 /* InterruptStatusBits */
516 SYSErr = 0x8000,
517 PCSTimeout = 0x4000,
518 SWInt = 0x0100,
519 TxDescUnavail = 0x0080,
520 RxFIFOOver = 0x0040,
521 LinkChg = 0x0020,
522 RxOverflow = 0x0010,
523 TxErr = 0x0008,
524 TxOK = 0x0004,
525 RxErr = 0x0002,
526 RxOK = 0x0001,
527
528 /* RxStatusDesc */
529 RxBOVF = (1 << 24),
530 RxFOVF = (1 << 23),
531 RxRWT = (1 << 22),
532 RxRES = (1 << 21),
533 RxRUNT = (1 << 20),
534 RxCRC = (1 << 19),
535
536 /* ChipCmdBits */
537 StopReq = 0x80,
538 CmdReset = 0x10,
539 CmdRxEnb = 0x08,
540 CmdTxEnb = 0x04,
541 RxBufEmpty = 0x01,
542
543 /* TXPoll register p.5 */
544 HPQ = 0x80, /* Poll cmd on the high prio queue */
545 NPQ = 0x40, /* Poll cmd on the low prio queue */
546 FSWInt = 0x01, /* Forced software interrupt */
547
548 /* Cfg9346Bits */
549 Cfg9346_Lock = 0x00,
550 Cfg9346_Unlock = 0xc0,
551
552 /* rx_mode_bits */
553 AcceptErr = 0x20,
554 AcceptRunt = 0x10,
555 AcceptBroadcast = 0x08,
556 AcceptMulticast = 0x04,
557 AcceptMyPhys = 0x02,
558 AcceptAllPhys = 0x01,
559 #define RX_CONFIG_ACCEPT_MASK 0x3f
560
561 /* TxConfigBits */
562 TxInterFrameGapShift = 24,
563 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
564
565 /* Config1 register p.24 */
566 LEDS1 = (1 << 7),
567 LEDS0 = (1 << 6),
568 Speed_down = (1 << 4),
569 MEMMAP = (1 << 3),
570 IOMAP = (1 << 2),
571 VPD = (1 << 1),
572 PMEnable = (1 << 0), /* Power Management Enable */
573
574 /* Config2 register p. 25 */
575 ClkReqEn = (1 << 7), /* Clock Request Enable */
576 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
577 PCI_Clock_66MHz = 0x01,
578 PCI_Clock_33MHz = 0x00,
579
580 /* Config3 register p.25 */
581 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
582 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
583 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
584 Rdy_to_L23 = (1 << 1), /* L23 Enable */
585 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
586
587 /* Config4 register */
588 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
589
590 /* Config5 register p.27 */
591 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
592 MWF = (1 << 5), /* Accept Multicast wakeup frame */
593 UWF = (1 << 4), /* Accept Unicast wakeup frame */
594 Spi_en = (1 << 3),
595 LanWake = (1 << 1), /* LanWake enable/disable */
596 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
597 ASPM_en = (1 << 0), /* ASPM enable */
598
599 /* TBICSR p.28 */
600 TBIReset = 0x80000000,
601 TBILoopback = 0x40000000,
602 TBINwEnable = 0x20000000,
603 TBINwRestart = 0x10000000,
604 TBILinkOk = 0x02000000,
605 TBINwComplete = 0x01000000,
606
607 /* CPlusCmd p.31 */
608 EnableBist = (1 << 15), // 8168 8101
609 Mac_dbgo_oe = (1 << 14), // 8168 8101
610 Normal_mode = (1 << 13), // unused
611 Force_half_dup = (1 << 12), // 8168 8101
612 Force_rxflow_en = (1 << 11), // 8168 8101
613 Force_txflow_en = (1 << 10), // 8168 8101
614 Cxpl_dbg_sel = (1 << 9), // 8168 8101
615 ASF = (1 << 8), // 8168 8101
616 PktCntrDisable = (1 << 7), // 8168 8101
617 Mac_dbgo_sel = 0x001c, // 8168
618 RxVlan = (1 << 6),
619 RxChkSum = (1 << 5),
620 PCIDAC = (1 << 4),
621 PCIMulRW = (1 << 3),
622 INTT_0 = 0x0000, // 8168
623 INTT_1 = 0x0001, // 8168
624 INTT_2 = 0x0002, // 8168
625 INTT_3 = 0x0003, // 8168
626
627 /* rtl8169_PHYstatus */
628 TBI_Enable = 0x80,
629 TxFlowCtrl = 0x40,
630 RxFlowCtrl = 0x20,
631 _1000bpsF = 0x10,
632 _100bps = 0x08,
633 _10bps = 0x04,
634 LinkStatus = 0x02,
635 FullDup = 0x01,
636
637 /* _TBICSRBit */
638 TBILinkOK = 0x02000000,
639
640 /* ResetCounterCommand */
641 CounterReset = 0x1,
642
643 /* DumpCounterCommand */
644 CounterDump = 0x8,
645
646 /* magic enable v2 */
647 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
648 };
649
650 enum rtl_desc_bit {
651 /* First doubleword. */
652 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
653 RingEnd = (1 << 30), /* End of descriptor ring */
654 FirstFrag = (1 << 29), /* First segment of a packet */
655 LastFrag = (1 << 28), /* Final segment of a packet */
656 };
657
658 /* Generic case. */
659 enum rtl_tx_desc_bit {
660 /* First doubleword. */
661 TD_LSO = (1 << 27), /* Large Send Offload */
662 #define TD_MSS_MAX 0x07ffu /* MSS value */
663
664 /* Second doubleword. */
665 TxVlanTag = (1 << 17), /* Add VLAN tag */
666 };
667
668 /* 8169, 8168b and 810x except 8102e. */
669 enum rtl_tx_desc_bit_0 {
670 /* First doubleword. */
671 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
672 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
673 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
674 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
675 };
676
677 /* 8102e, 8168c and beyond. */
678 enum rtl_tx_desc_bit_1 {
679 /* First doubleword. */
680 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
681 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
682 #define GTTCPHO_SHIFT 18
683 #define GTTCPHO_MAX 0x7fU
684
685 /* Second doubleword. */
686 #define TCPHO_SHIFT 18
687 #define TCPHO_MAX 0x3ffU
688 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
689 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
690 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
691 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
692 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
693 };
694
695 enum rtl_rx_desc_bit {
696 /* Rx private */
697 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
698 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
699
700 #define RxProtoUDP (PID1)
701 #define RxProtoTCP (PID0)
702 #define RxProtoIP (PID1 | PID0)
703 #define RxProtoMask RxProtoIP
704
705 IPFail = (1 << 16), /* IP checksum failed */
706 UDPFail = (1 << 15), /* UDP/IP checksum failed */
707 TCPFail = (1 << 14), /* TCP/IP checksum failed */
708 RxVlanTag = (1 << 16), /* VLAN tag available */
709 };
710
711 #define RsvdMask 0x3fffc000
712
713 struct TxDesc {
714 __le32 opts1;
715 __le32 opts2;
716 __le64 addr;
717 };
718
719 struct RxDesc {
720 __le32 opts1;
721 __le32 opts2;
722 __le64 addr;
723 };
724
725 struct ring_info {
726 struct sk_buff *skb;
727 u32 len;
728 u8 __pad[sizeof(void *) - sizeof(u32)];
729 };
730
731 enum features {
732 RTL_FEATURE_WOL = (1 << 0),
733 RTL_FEATURE_MSI = (1 << 1),
734 RTL_FEATURE_GMII = (1 << 2),
735 };
736
737 struct rtl8169_counters {
738 __le64 tx_packets;
739 __le64 rx_packets;
740 __le64 tx_errors;
741 __le32 rx_errors;
742 __le16 rx_missed;
743 __le16 align_errors;
744 __le32 tx_one_collision;
745 __le32 tx_multi_collision;
746 __le64 rx_unicast;
747 __le64 rx_broadcast;
748 __le32 rx_multicast;
749 __le16 tx_aborted;
750 __le16 tx_underun;
751 };
752
753 struct rtl8169_tc_offsets {
754 bool inited;
755 __le64 tx_errors;
756 __le32 tx_multi_collision;
757 __le16 tx_aborted;
758 };
759
760 enum rtl_flag {
761 RTL_FLAG_TASK_ENABLED,
762 RTL_FLAG_TASK_SLOW_PENDING,
763 RTL_FLAG_TASK_RESET_PENDING,
764 RTL_FLAG_TASK_PHY_PENDING,
765 RTL_FLAG_MAX
766 };
767
768 struct rtl8169_stats {
769 u64 packets;
770 u64 bytes;
771 struct u64_stats_sync syncp;
772 };
773
774 struct rtl8169_private {
775 void __iomem *mmio_addr; /* memory map physical address */
776 struct pci_dev *pci_dev;
777 struct net_device *dev;
778 struct napi_struct napi;
779 u32 msg_enable;
780 u16 txd_version;
781 u16 mac_version;
782 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
783 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
784 u32 dirty_tx;
785 struct rtl8169_stats rx_stats;
786 struct rtl8169_stats tx_stats;
787 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
788 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
789 dma_addr_t TxPhyAddr;
790 dma_addr_t RxPhyAddr;
791 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
792 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
793 struct timer_list timer;
794 u16 cp_cmd;
795
796 u16 event_slow;
797
798 struct mdio_ops {
799 void (*write)(struct rtl8169_private *, int, int);
800 int (*read)(struct rtl8169_private *, int);
801 } mdio_ops;
802
803 struct pll_power_ops {
804 void (*down)(struct rtl8169_private *);
805 void (*up)(struct rtl8169_private *);
806 } pll_power_ops;
807
808 struct jumbo_ops {
809 void (*enable)(struct rtl8169_private *);
810 void (*disable)(struct rtl8169_private *);
811 } jumbo_ops;
812
813 struct csi_ops {
814 void (*write)(struct rtl8169_private *, int, int);
815 u32 (*read)(struct rtl8169_private *, int);
816 } csi_ops;
817
818 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
819 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
820 void (*phy_reset_enable)(struct rtl8169_private *tp);
821 void (*hw_start)(struct net_device *);
822 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
823 unsigned int (*link_ok)(void __iomem *);
824 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
825 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
826
827 struct {
828 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
829 struct mutex mutex;
830 struct work_struct work;
831 } wk;
832
833 unsigned features;
834
835 struct mii_if_info mii;
836 dma_addr_t counters_phys_addr;
837 struct rtl8169_counters *counters;
838 struct rtl8169_tc_offsets tc_offset;
839 u32 saved_wolopts;
840 u32 opts1_mask;
841
842 struct rtl_fw {
843 const struct firmware *fw;
844
845 #define RTL_VER_SIZE 32
846
847 char version[RTL_VER_SIZE];
848
849 struct rtl_fw_phy_action {
850 __le32 *code;
851 size_t size;
852 } phy_action;
853 } *rtl_fw;
854 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
855
856 u32 ocp_base;
857 };
858
859 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
860 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
861 module_param(use_dac, int, 0);
862 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
863 module_param_named(debug, debug.msg_enable, int, 0);
864 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
865 MODULE_LICENSE("GPL");
866 MODULE_VERSION(RTL8169_VERSION);
867 MODULE_FIRMWARE(FIRMWARE_8168D_1);
868 MODULE_FIRMWARE(FIRMWARE_8168D_2);
869 MODULE_FIRMWARE(FIRMWARE_8168E_1);
870 MODULE_FIRMWARE(FIRMWARE_8168E_2);
871 MODULE_FIRMWARE(FIRMWARE_8168E_3);
872 MODULE_FIRMWARE(FIRMWARE_8105E_1);
873 MODULE_FIRMWARE(FIRMWARE_8168F_1);
874 MODULE_FIRMWARE(FIRMWARE_8168F_2);
875 MODULE_FIRMWARE(FIRMWARE_8402_1);
876 MODULE_FIRMWARE(FIRMWARE_8411_1);
877 MODULE_FIRMWARE(FIRMWARE_8411_2);
878 MODULE_FIRMWARE(FIRMWARE_8106E_1);
879 MODULE_FIRMWARE(FIRMWARE_8106E_2);
880 MODULE_FIRMWARE(FIRMWARE_8168G_2);
881 MODULE_FIRMWARE(FIRMWARE_8168G_3);
882 MODULE_FIRMWARE(FIRMWARE_8168H_1);
883 MODULE_FIRMWARE(FIRMWARE_8168H_2);
884 MODULE_FIRMWARE(FIRMWARE_8107E_1);
885 MODULE_FIRMWARE(FIRMWARE_8107E_2);
886
887 static void rtl_lock_work(struct rtl8169_private *tp)
888 {
889 mutex_lock(&tp->wk.mutex);
890 }
891
892 static void rtl_unlock_work(struct rtl8169_private *tp)
893 {
894 mutex_unlock(&tp->wk.mutex);
895 }
896
897 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
898 {
899 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
900 PCI_EXP_DEVCTL_READRQ, force);
901 }
902
903 struct rtl_cond {
904 bool (*check)(struct rtl8169_private *);
905 const char *msg;
906 };
907
908 static void rtl_udelay(unsigned int d)
909 {
910 udelay(d);
911 }
912
913 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
914 void (*delay)(unsigned int), unsigned int d, int n,
915 bool high)
916 {
917 int i;
918
919 for (i = 0; i < n; i++) {
920 delay(d);
921 if (c->check(tp) == high)
922 return true;
923 }
924 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
925 c->msg, !high, n, d);
926 return false;
927 }
928
929 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
930 const struct rtl_cond *c,
931 unsigned int d, int n)
932 {
933 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
934 }
935
936 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
937 const struct rtl_cond *c,
938 unsigned int d, int n)
939 {
940 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
941 }
942
943 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
944 const struct rtl_cond *c,
945 unsigned int d, int n)
946 {
947 return rtl_loop_wait(tp, c, msleep, d, n, true);
948 }
949
950 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
951 const struct rtl_cond *c,
952 unsigned int d, int n)
953 {
954 return rtl_loop_wait(tp, c, msleep, d, n, false);
955 }
956
957 #define DECLARE_RTL_COND(name) \
958 static bool name ## _check(struct rtl8169_private *); \
959 \
960 static const struct rtl_cond name = { \
961 .check = name ## _check, \
962 .msg = #name \
963 }; \
964 \
965 static bool name ## _check(struct rtl8169_private *tp)
966
967 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
968 {
969 if (reg & 0xffff0001) {
970 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
971 return true;
972 }
973 return false;
974 }
975
976 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
977 {
978 void __iomem *ioaddr = tp->mmio_addr;
979
980 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
981 }
982
983 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
984 {
985 void __iomem *ioaddr = tp->mmio_addr;
986
987 if (rtl_ocp_reg_failure(tp, reg))
988 return;
989
990 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
991
992 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
993 }
994
995 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
996 {
997 void __iomem *ioaddr = tp->mmio_addr;
998
999 if (rtl_ocp_reg_failure(tp, reg))
1000 return 0;
1001
1002 RTL_W32(GPHY_OCP, reg << 15);
1003
1004 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1005 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1006 }
1007
1008 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1009 {
1010 void __iomem *ioaddr = tp->mmio_addr;
1011
1012 if (rtl_ocp_reg_failure(tp, reg))
1013 return;
1014
1015 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1016 }
1017
1018 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1019 {
1020 void __iomem *ioaddr = tp->mmio_addr;
1021
1022 if (rtl_ocp_reg_failure(tp, reg))
1023 return 0;
1024
1025 RTL_W32(OCPDR, reg << 15);
1026
1027 return RTL_R32(OCPDR);
1028 }
1029
1030 #define OCP_STD_PHY_BASE 0xa400
1031
1032 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1033 {
1034 if (reg == 0x1f) {
1035 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1036 return;
1037 }
1038
1039 if (tp->ocp_base != OCP_STD_PHY_BASE)
1040 reg -= 0x10;
1041
1042 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1043 }
1044
1045 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1046 {
1047 if (tp->ocp_base != OCP_STD_PHY_BASE)
1048 reg -= 0x10;
1049
1050 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1051 }
1052
1053 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1054 {
1055 if (reg == 0x1f) {
1056 tp->ocp_base = value << 4;
1057 return;
1058 }
1059
1060 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1061 }
1062
1063 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1064 {
1065 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1066 }
1067
1068 DECLARE_RTL_COND(rtl_phyar_cond)
1069 {
1070 void __iomem *ioaddr = tp->mmio_addr;
1071
1072 return RTL_R32(PHYAR) & 0x80000000;
1073 }
1074
1075 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1076 {
1077 void __iomem *ioaddr = tp->mmio_addr;
1078
1079 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1080
1081 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1082 /*
1083 * According to hardware specs a 20us delay is required after write
1084 * complete indication, but before sending next command.
1085 */
1086 udelay(20);
1087 }
1088
1089 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1090 {
1091 void __iomem *ioaddr = tp->mmio_addr;
1092 int value;
1093
1094 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1095
1096 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1097 RTL_R32(PHYAR) & 0xffff : ~0;
1098
1099 /*
1100 * According to hardware specs a 20us delay is required after read
1101 * complete indication, but before sending next command.
1102 */
1103 udelay(20);
1104
1105 return value;
1106 }
1107
1108 DECLARE_RTL_COND(rtl_ocpar_cond)
1109 {
1110 void __iomem *ioaddr = tp->mmio_addr;
1111
1112 return RTL_R32(OCPAR) & OCPAR_FLAG;
1113 }
1114
1115 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1116 {
1117 void __iomem *ioaddr = tp->mmio_addr;
1118
1119 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1120 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1121 RTL_W32(EPHY_RXER_NUM, 0);
1122
1123 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1124 }
1125
1126 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1127 {
1128 r8168dp_1_mdio_access(tp, reg,
1129 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1130 }
1131
1132 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1133 {
1134 void __iomem *ioaddr = tp->mmio_addr;
1135
1136 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1137
1138 mdelay(1);
1139 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1140 RTL_W32(EPHY_RXER_NUM, 0);
1141
1142 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1143 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1144 }
1145
1146 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1147
1148 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1149 {
1150 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1151 }
1152
1153 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1154 {
1155 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1156 }
1157
1158 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1159 {
1160 void __iomem *ioaddr = tp->mmio_addr;
1161
1162 r8168dp_2_mdio_start(ioaddr);
1163
1164 r8169_mdio_write(tp, reg, value);
1165
1166 r8168dp_2_mdio_stop(ioaddr);
1167 }
1168
1169 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1170 {
1171 void __iomem *ioaddr = tp->mmio_addr;
1172 int value;
1173
1174 r8168dp_2_mdio_start(ioaddr);
1175
1176 value = r8169_mdio_read(tp, reg);
1177
1178 r8168dp_2_mdio_stop(ioaddr);
1179
1180 return value;
1181 }
1182
1183 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1184 {
1185 tp->mdio_ops.write(tp, location, val);
1186 }
1187
1188 static int rtl_readphy(struct rtl8169_private *tp, int location)
1189 {
1190 return tp->mdio_ops.read(tp, location);
1191 }
1192
1193 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1194 {
1195 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1196 }
1197
1198 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1199 {
1200 int val;
1201
1202 val = rtl_readphy(tp, reg_addr);
1203 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1204 }
1205
1206 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1207 int val)
1208 {
1209 struct rtl8169_private *tp = netdev_priv(dev);
1210
1211 rtl_writephy(tp, location, val);
1212 }
1213
1214 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1215 {
1216 struct rtl8169_private *tp = netdev_priv(dev);
1217
1218 return rtl_readphy(tp, location);
1219 }
1220
1221 DECLARE_RTL_COND(rtl_ephyar_cond)
1222 {
1223 void __iomem *ioaddr = tp->mmio_addr;
1224
1225 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1226 }
1227
1228 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1229 {
1230 void __iomem *ioaddr = tp->mmio_addr;
1231
1232 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1233 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1234
1235 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1236
1237 udelay(10);
1238 }
1239
1240 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1241 {
1242 void __iomem *ioaddr = tp->mmio_addr;
1243
1244 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1245
1246 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1247 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1248 }
1249
1250 DECLARE_RTL_COND(rtl_eriar_cond)
1251 {
1252 void __iomem *ioaddr = tp->mmio_addr;
1253
1254 return RTL_R32(ERIAR) & ERIAR_FLAG;
1255 }
1256
1257 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1258 u32 val, int type)
1259 {
1260 void __iomem *ioaddr = tp->mmio_addr;
1261
1262 BUG_ON((addr & 3) || (mask == 0));
1263 RTL_W32(ERIDR, val);
1264 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1265
1266 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1267 }
1268
1269 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1270 {
1271 void __iomem *ioaddr = tp->mmio_addr;
1272
1273 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1274
1275 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1276 RTL_R32(ERIDR) : ~0;
1277 }
1278
1279 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1280 u32 m, int type)
1281 {
1282 u32 val;
1283
1284 val = rtl_eri_read(tp, addr, type);
1285 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1286 }
1287
1288 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1289 {
1290 void __iomem *ioaddr = tp->mmio_addr;
1291
1292 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1293 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1294 RTL_R32(OCPDR) : ~0;
1295 }
1296
1297 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1298 {
1299 return rtl_eri_read(tp, reg, ERIAR_OOB);
1300 }
1301
1302 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1303 {
1304 switch (tp->mac_version) {
1305 case RTL_GIGA_MAC_VER_27:
1306 case RTL_GIGA_MAC_VER_28:
1307 case RTL_GIGA_MAC_VER_31:
1308 return r8168dp_ocp_read(tp, mask, reg);
1309 case RTL_GIGA_MAC_VER_49:
1310 case RTL_GIGA_MAC_VER_50:
1311 case RTL_GIGA_MAC_VER_51:
1312 return r8168ep_ocp_read(tp, mask, reg);
1313 default:
1314 BUG();
1315 return ~0;
1316 }
1317 }
1318
1319 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1320 u32 data)
1321 {
1322 void __iomem *ioaddr = tp->mmio_addr;
1323
1324 RTL_W32(OCPDR, data);
1325 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1326 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1327 }
1328
1329 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1330 u32 data)
1331 {
1332 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1333 data, ERIAR_OOB);
1334 }
1335
1336 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1337 {
1338 switch (tp->mac_version) {
1339 case RTL_GIGA_MAC_VER_27:
1340 case RTL_GIGA_MAC_VER_28:
1341 case RTL_GIGA_MAC_VER_31:
1342 r8168dp_ocp_write(tp, mask, reg, data);
1343 break;
1344 case RTL_GIGA_MAC_VER_49:
1345 case RTL_GIGA_MAC_VER_50:
1346 case RTL_GIGA_MAC_VER_51:
1347 r8168ep_ocp_write(tp, mask, reg, data);
1348 break;
1349 default:
1350 BUG();
1351 break;
1352 }
1353 }
1354
1355 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1356 {
1357 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1358
1359 ocp_write(tp, 0x1, 0x30, 0x00000001);
1360 }
1361
1362 #define OOB_CMD_RESET 0x00
1363 #define OOB_CMD_DRIVER_START 0x05
1364 #define OOB_CMD_DRIVER_STOP 0x06
1365
1366 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1367 {
1368 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1369 }
1370
1371 DECLARE_RTL_COND(rtl_ocp_read_cond)
1372 {
1373 u16 reg;
1374
1375 reg = rtl8168_get_ocp_reg(tp);
1376
1377 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1378 }
1379
1380 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1381 {
1382 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1383 }
1384
1385 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1386 {
1387 void __iomem *ioaddr = tp->mmio_addr;
1388
1389 return RTL_R8(IBISR0) & 0x02;
1390 }
1391
1392 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1393 {
1394 void __iomem *ioaddr = tp->mmio_addr;
1395
1396 RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);
1397 rtl_msleep_loop_wait_low(tp, &rtl_ocp_tx_cond, 50, 2000);
1398 RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);
1399 RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);
1400 }
1401
1402 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1403 {
1404 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1405 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1406 }
1407
1408 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1409 {
1410 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1411 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1412 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1413 }
1414
1415 static void rtl8168_driver_start(struct rtl8169_private *tp)
1416 {
1417 switch (tp->mac_version) {
1418 case RTL_GIGA_MAC_VER_27:
1419 case RTL_GIGA_MAC_VER_28:
1420 case RTL_GIGA_MAC_VER_31:
1421 rtl8168dp_driver_start(tp);
1422 break;
1423 case RTL_GIGA_MAC_VER_49:
1424 case RTL_GIGA_MAC_VER_50:
1425 case RTL_GIGA_MAC_VER_51:
1426 rtl8168ep_driver_start(tp);
1427 break;
1428 default:
1429 BUG();
1430 break;
1431 }
1432 }
1433
1434 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1435 {
1436 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1437 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1438 }
1439
1440 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1441 {
1442 rtl8168ep_stop_cmac(tp);
1443 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1444 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1445 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1446 }
1447
1448 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1449 {
1450 switch (tp->mac_version) {
1451 case RTL_GIGA_MAC_VER_27:
1452 case RTL_GIGA_MAC_VER_28:
1453 case RTL_GIGA_MAC_VER_31:
1454 rtl8168dp_driver_stop(tp);
1455 break;
1456 case RTL_GIGA_MAC_VER_49:
1457 case RTL_GIGA_MAC_VER_50:
1458 case RTL_GIGA_MAC_VER_51:
1459 rtl8168ep_driver_stop(tp);
1460 break;
1461 default:
1462 BUG();
1463 break;
1464 }
1465 }
1466
1467 static int r8168dp_check_dash(struct rtl8169_private *tp)
1468 {
1469 u16 reg = rtl8168_get_ocp_reg(tp);
1470
1471 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1472 }
1473
1474 static int r8168ep_check_dash(struct rtl8169_private *tp)
1475 {
1476 return (ocp_read(tp, 0x0f, 0x128) & 0x00000001) ? 1 : 0;
1477 }
1478
1479 static int r8168_check_dash(struct rtl8169_private *tp)
1480 {
1481 switch (tp->mac_version) {
1482 case RTL_GIGA_MAC_VER_27:
1483 case RTL_GIGA_MAC_VER_28:
1484 case RTL_GIGA_MAC_VER_31:
1485 return r8168dp_check_dash(tp);
1486 case RTL_GIGA_MAC_VER_49:
1487 case RTL_GIGA_MAC_VER_50:
1488 case RTL_GIGA_MAC_VER_51:
1489 return r8168ep_check_dash(tp);
1490 default:
1491 return 0;
1492 }
1493 }
1494
1495 struct exgmac_reg {
1496 u16 addr;
1497 u16 mask;
1498 u32 val;
1499 };
1500
1501 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1502 const struct exgmac_reg *r, int len)
1503 {
1504 while (len-- > 0) {
1505 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1506 r++;
1507 }
1508 }
1509
1510 DECLARE_RTL_COND(rtl_efusear_cond)
1511 {
1512 void __iomem *ioaddr = tp->mmio_addr;
1513
1514 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1515 }
1516
1517 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1518 {
1519 void __iomem *ioaddr = tp->mmio_addr;
1520
1521 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1522
1523 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1524 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1525 }
1526
1527 static u16 rtl_get_events(struct rtl8169_private *tp)
1528 {
1529 void __iomem *ioaddr = tp->mmio_addr;
1530
1531 return RTL_R16(IntrStatus);
1532 }
1533
1534 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1535 {
1536 void __iomem *ioaddr = tp->mmio_addr;
1537
1538 RTL_W16(IntrStatus, bits);
1539 mmiowb();
1540 }
1541
1542 static void rtl_irq_disable(struct rtl8169_private *tp)
1543 {
1544 void __iomem *ioaddr = tp->mmio_addr;
1545
1546 RTL_W16(IntrMask, 0);
1547 mmiowb();
1548 }
1549
1550 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1551 {
1552 void __iomem *ioaddr = tp->mmio_addr;
1553
1554 RTL_W16(IntrMask, bits);
1555 }
1556
1557 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1558 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1559 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1560
1561 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1562 {
1563 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1564 }
1565
1566 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1567 {
1568 void __iomem *ioaddr = tp->mmio_addr;
1569
1570 rtl_irq_disable(tp);
1571 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1572 RTL_R8(ChipCmd);
1573 }
1574
1575 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1576 {
1577 void __iomem *ioaddr = tp->mmio_addr;
1578
1579 return RTL_R32(TBICSR) & TBIReset;
1580 }
1581
1582 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1583 {
1584 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1585 }
1586
1587 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1588 {
1589 return RTL_R32(TBICSR) & TBILinkOk;
1590 }
1591
1592 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1593 {
1594 return RTL_R8(PHYstatus) & LinkStatus;
1595 }
1596
1597 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1598 {
1599 void __iomem *ioaddr = tp->mmio_addr;
1600
1601 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1602 }
1603
1604 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1605 {
1606 unsigned int val;
1607
1608 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1609 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1610 }
1611
1612 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1613 {
1614 void __iomem *ioaddr = tp->mmio_addr;
1615 struct net_device *dev = tp->dev;
1616
1617 if (!netif_running(dev))
1618 return;
1619
1620 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1621 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1622 if (RTL_R8(PHYstatus) & _1000bpsF) {
1623 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1624 ERIAR_EXGMAC);
1625 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1626 ERIAR_EXGMAC);
1627 } else if (RTL_R8(PHYstatus) & _100bps) {
1628 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1629 ERIAR_EXGMAC);
1630 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1631 ERIAR_EXGMAC);
1632 } else {
1633 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1634 ERIAR_EXGMAC);
1635 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1636 ERIAR_EXGMAC);
1637 }
1638 /* Reset packet filter */
1639 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1640 ERIAR_EXGMAC);
1641 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1642 ERIAR_EXGMAC);
1643 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1644 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1645 if (RTL_R8(PHYstatus) & _1000bpsF) {
1646 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1647 ERIAR_EXGMAC);
1648 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1649 ERIAR_EXGMAC);
1650 } else {
1651 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1652 ERIAR_EXGMAC);
1653 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1654 ERIAR_EXGMAC);
1655 }
1656 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1657 if (RTL_R8(PHYstatus) & _10bps) {
1658 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1659 ERIAR_EXGMAC);
1660 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1661 ERIAR_EXGMAC);
1662 } else {
1663 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1664 ERIAR_EXGMAC);
1665 }
1666 }
1667 }
1668
1669 static void __rtl8169_check_link_status(struct net_device *dev,
1670 struct rtl8169_private *tp,
1671 void __iomem *ioaddr, bool pm)
1672 {
1673 if (tp->link_ok(ioaddr)) {
1674 rtl_link_chg_patch(tp);
1675 /* This is to cancel a scheduled suspend if there's one. */
1676 if (pm)
1677 pm_request_resume(&tp->pci_dev->dev);
1678 netif_carrier_on(dev);
1679 if (net_ratelimit())
1680 netif_info(tp, ifup, dev, "link up\n");
1681 } else {
1682 netif_carrier_off(dev);
1683 netif_info(tp, ifdown, dev, "link down\n");
1684 if (pm)
1685 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1686 }
1687 }
1688
1689 static void rtl8169_check_link_status(struct net_device *dev,
1690 struct rtl8169_private *tp,
1691 void __iomem *ioaddr)
1692 {
1693 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1694 }
1695
1696 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1697
1698 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1699 {
1700 void __iomem *ioaddr = tp->mmio_addr;
1701 u8 options;
1702 u32 wolopts = 0;
1703
1704 options = RTL_R8(Config1);
1705 if (!(options & PMEnable))
1706 return 0;
1707
1708 options = RTL_R8(Config3);
1709 if (options & LinkUp)
1710 wolopts |= WAKE_PHY;
1711 switch (tp->mac_version) {
1712 case RTL_GIGA_MAC_VER_34:
1713 case RTL_GIGA_MAC_VER_35:
1714 case RTL_GIGA_MAC_VER_36:
1715 case RTL_GIGA_MAC_VER_37:
1716 case RTL_GIGA_MAC_VER_38:
1717 case RTL_GIGA_MAC_VER_40:
1718 case RTL_GIGA_MAC_VER_41:
1719 case RTL_GIGA_MAC_VER_42:
1720 case RTL_GIGA_MAC_VER_43:
1721 case RTL_GIGA_MAC_VER_44:
1722 case RTL_GIGA_MAC_VER_45:
1723 case RTL_GIGA_MAC_VER_46:
1724 case RTL_GIGA_MAC_VER_47:
1725 case RTL_GIGA_MAC_VER_48:
1726 case RTL_GIGA_MAC_VER_49:
1727 case RTL_GIGA_MAC_VER_50:
1728 case RTL_GIGA_MAC_VER_51:
1729 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1730 wolopts |= WAKE_MAGIC;
1731 break;
1732 default:
1733 if (options & MagicPacket)
1734 wolopts |= WAKE_MAGIC;
1735 break;
1736 }
1737
1738 options = RTL_R8(Config5);
1739 if (options & UWF)
1740 wolopts |= WAKE_UCAST;
1741 if (options & BWF)
1742 wolopts |= WAKE_BCAST;
1743 if (options & MWF)
1744 wolopts |= WAKE_MCAST;
1745
1746 return wolopts;
1747 }
1748
1749 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1750 {
1751 struct rtl8169_private *tp = netdev_priv(dev);
1752
1753 rtl_lock_work(tp);
1754
1755 wol->supported = WAKE_ANY;
1756 wol->wolopts = __rtl8169_get_wol(tp);
1757
1758 rtl_unlock_work(tp);
1759 }
1760
1761 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1762 {
1763 void __iomem *ioaddr = tp->mmio_addr;
1764 unsigned int i, tmp;
1765 static const struct {
1766 u32 opt;
1767 u16 reg;
1768 u8 mask;
1769 } cfg[] = {
1770 { WAKE_PHY, Config3, LinkUp },
1771 { WAKE_UCAST, Config5, UWF },
1772 { WAKE_BCAST, Config5, BWF },
1773 { WAKE_MCAST, Config5, MWF },
1774 { WAKE_ANY, Config5, LanWake },
1775 { WAKE_MAGIC, Config3, MagicPacket }
1776 };
1777 u8 options;
1778
1779 RTL_W8(Cfg9346, Cfg9346_Unlock);
1780
1781 switch (tp->mac_version) {
1782 case RTL_GIGA_MAC_VER_34:
1783 case RTL_GIGA_MAC_VER_35:
1784 case RTL_GIGA_MAC_VER_36:
1785 case RTL_GIGA_MAC_VER_37:
1786 case RTL_GIGA_MAC_VER_38:
1787 case RTL_GIGA_MAC_VER_40:
1788 case RTL_GIGA_MAC_VER_41:
1789 case RTL_GIGA_MAC_VER_42:
1790 case RTL_GIGA_MAC_VER_43:
1791 case RTL_GIGA_MAC_VER_44:
1792 case RTL_GIGA_MAC_VER_45:
1793 case RTL_GIGA_MAC_VER_46:
1794 case RTL_GIGA_MAC_VER_47:
1795 case RTL_GIGA_MAC_VER_48:
1796 case RTL_GIGA_MAC_VER_49:
1797 case RTL_GIGA_MAC_VER_50:
1798 case RTL_GIGA_MAC_VER_51:
1799 tmp = ARRAY_SIZE(cfg) - 1;
1800 if (wolopts & WAKE_MAGIC)
1801 rtl_w0w1_eri(tp,
1802 0x0dc,
1803 ERIAR_MASK_0100,
1804 MagicPacket_v2,
1805 0x0000,
1806 ERIAR_EXGMAC);
1807 else
1808 rtl_w0w1_eri(tp,
1809 0x0dc,
1810 ERIAR_MASK_0100,
1811 0x0000,
1812 MagicPacket_v2,
1813 ERIAR_EXGMAC);
1814 break;
1815 default:
1816 tmp = ARRAY_SIZE(cfg);
1817 break;
1818 }
1819
1820 for (i = 0; i < tmp; i++) {
1821 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1822 if (wolopts & cfg[i].opt)
1823 options |= cfg[i].mask;
1824 RTL_W8(cfg[i].reg, options);
1825 }
1826
1827 switch (tp->mac_version) {
1828 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1829 options = RTL_R8(Config1) & ~PMEnable;
1830 if (wolopts)
1831 options |= PMEnable;
1832 RTL_W8(Config1, options);
1833 break;
1834 default:
1835 options = RTL_R8(Config2) & ~PME_SIGNAL;
1836 if (wolopts)
1837 options |= PME_SIGNAL;
1838 RTL_W8(Config2, options);
1839 break;
1840 }
1841
1842 RTL_W8(Cfg9346, Cfg9346_Lock);
1843 }
1844
1845 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1846 {
1847 struct rtl8169_private *tp = netdev_priv(dev);
1848
1849 rtl_lock_work(tp);
1850
1851 if (wol->wolopts)
1852 tp->features |= RTL_FEATURE_WOL;
1853 else
1854 tp->features &= ~RTL_FEATURE_WOL;
1855 __rtl8169_set_wol(tp, wol->wolopts);
1856
1857 rtl_unlock_work(tp);
1858
1859 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1860
1861 return 0;
1862 }
1863
1864 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1865 {
1866 return rtl_chip_infos[tp->mac_version].fw_name;
1867 }
1868
1869 static void rtl8169_get_drvinfo(struct net_device *dev,
1870 struct ethtool_drvinfo *info)
1871 {
1872 struct rtl8169_private *tp = netdev_priv(dev);
1873 struct rtl_fw *rtl_fw = tp->rtl_fw;
1874
1875 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1876 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1877 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1878 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1879 if (!IS_ERR_OR_NULL(rtl_fw))
1880 strlcpy(info->fw_version, rtl_fw->version,
1881 sizeof(info->fw_version));
1882 }
1883
1884 static int rtl8169_get_regs_len(struct net_device *dev)
1885 {
1886 return R8169_REGS_SIZE;
1887 }
1888
1889 static int rtl8169_set_speed_tbi(struct net_device *dev,
1890 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1891 {
1892 struct rtl8169_private *tp = netdev_priv(dev);
1893 void __iomem *ioaddr = tp->mmio_addr;
1894 int ret = 0;
1895 u32 reg;
1896
1897 reg = RTL_R32(TBICSR);
1898 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1899 (duplex == DUPLEX_FULL)) {
1900 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1901 } else if (autoneg == AUTONEG_ENABLE)
1902 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1903 else {
1904 netif_warn(tp, link, dev,
1905 "incorrect speed setting refused in TBI mode\n");
1906 ret = -EOPNOTSUPP;
1907 }
1908
1909 return ret;
1910 }
1911
1912 static int rtl8169_set_speed_xmii(struct net_device *dev,
1913 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1914 {
1915 struct rtl8169_private *tp = netdev_priv(dev);
1916 int giga_ctrl, bmcr;
1917 int rc = -EINVAL;
1918
1919 rtl_writephy(tp, 0x1f, 0x0000);
1920
1921 if (autoneg == AUTONEG_ENABLE) {
1922 int auto_nego;
1923
1924 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1925 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1926 ADVERTISE_100HALF | ADVERTISE_100FULL);
1927
1928 if (adv & ADVERTISED_10baseT_Half)
1929 auto_nego |= ADVERTISE_10HALF;
1930 if (adv & ADVERTISED_10baseT_Full)
1931 auto_nego |= ADVERTISE_10FULL;
1932 if (adv & ADVERTISED_100baseT_Half)
1933 auto_nego |= ADVERTISE_100HALF;
1934 if (adv & ADVERTISED_100baseT_Full)
1935 auto_nego |= ADVERTISE_100FULL;
1936
1937 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1938
1939 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1940 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1941
1942 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1943 if (tp->mii.supports_gmii) {
1944 if (adv & ADVERTISED_1000baseT_Half)
1945 giga_ctrl |= ADVERTISE_1000HALF;
1946 if (adv & ADVERTISED_1000baseT_Full)
1947 giga_ctrl |= ADVERTISE_1000FULL;
1948 } else if (adv & (ADVERTISED_1000baseT_Half |
1949 ADVERTISED_1000baseT_Full)) {
1950 netif_info(tp, link, dev,
1951 "PHY does not support 1000Mbps\n");
1952 goto out;
1953 }
1954
1955 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1956
1957 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1958 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1959 } else {
1960 giga_ctrl = 0;
1961
1962 if (speed == SPEED_10)
1963 bmcr = 0;
1964 else if (speed == SPEED_100)
1965 bmcr = BMCR_SPEED100;
1966 else
1967 goto out;
1968
1969 if (duplex == DUPLEX_FULL)
1970 bmcr |= BMCR_FULLDPLX;
1971 }
1972
1973 rtl_writephy(tp, MII_BMCR, bmcr);
1974
1975 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1976 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1977 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1978 rtl_writephy(tp, 0x17, 0x2138);
1979 rtl_writephy(tp, 0x0e, 0x0260);
1980 } else {
1981 rtl_writephy(tp, 0x17, 0x2108);
1982 rtl_writephy(tp, 0x0e, 0x0000);
1983 }
1984 }
1985
1986 rc = 0;
1987 out:
1988 return rc;
1989 }
1990
1991 static int rtl8169_set_speed(struct net_device *dev,
1992 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1993 {
1994 struct rtl8169_private *tp = netdev_priv(dev);
1995 int ret;
1996
1997 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1998 if (ret < 0)
1999 goto out;
2000
2001 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
2002 (advertising & ADVERTISED_1000baseT_Full)) {
2003 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
2004 }
2005 out:
2006 return ret;
2007 }
2008
2009 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2010 {
2011 struct rtl8169_private *tp = netdev_priv(dev);
2012 int ret;
2013
2014 del_timer_sync(&tp->timer);
2015
2016 rtl_lock_work(tp);
2017 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
2018 cmd->duplex, cmd->advertising);
2019 rtl_unlock_work(tp);
2020
2021 return ret;
2022 }
2023
2024 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
2025 netdev_features_t features)
2026 {
2027 struct rtl8169_private *tp = netdev_priv(dev);
2028
2029 if (dev->mtu > TD_MSS_MAX)
2030 features &= ~NETIF_F_ALL_TSO;
2031
2032 if (dev->mtu > JUMBO_1K &&
2033 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
2034 features &= ~NETIF_F_IP_CSUM;
2035
2036 return features;
2037 }
2038
2039 static void __rtl8169_set_features(struct net_device *dev,
2040 netdev_features_t features)
2041 {
2042 struct rtl8169_private *tp = netdev_priv(dev);
2043 void __iomem *ioaddr = tp->mmio_addr;
2044 u32 rx_config;
2045
2046 rx_config = RTL_R32(RxConfig);
2047 if (features & NETIF_F_RXALL)
2048 rx_config |= (AcceptErr | AcceptRunt);
2049 else
2050 rx_config &= ~(AcceptErr | AcceptRunt);
2051
2052 RTL_W32(RxConfig, rx_config);
2053
2054 if (features & NETIF_F_RXCSUM)
2055 tp->cp_cmd |= RxChkSum;
2056 else
2057 tp->cp_cmd &= ~RxChkSum;
2058
2059 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2060 tp->cp_cmd |= RxVlan;
2061 else
2062 tp->cp_cmd &= ~RxVlan;
2063
2064 tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
2065
2066 RTL_W16(CPlusCmd, tp->cp_cmd);
2067 RTL_R16(CPlusCmd);
2068 }
2069
2070 static int rtl8169_set_features(struct net_device *dev,
2071 netdev_features_t features)
2072 {
2073 struct rtl8169_private *tp = netdev_priv(dev);
2074
2075 features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
2076
2077 rtl_lock_work(tp);
2078 if (features ^ dev->features)
2079 __rtl8169_set_features(dev, features);
2080 rtl_unlock_work(tp);
2081
2082 return 0;
2083 }
2084
2085
2086 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
2087 {
2088 return (skb_vlan_tag_present(skb)) ?
2089 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
2090 }
2091
2092 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
2093 {
2094 u32 opts2 = le32_to_cpu(desc->opts2);
2095
2096 if (opts2 & RxVlanTag)
2097 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
2098 }
2099
2100 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
2101 {
2102 struct rtl8169_private *tp = netdev_priv(dev);
2103 void __iomem *ioaddr = tp->mmio_addr;
2104 u32 status;
2105
2106 cmd->supported =
2107 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
2108 cmd->port = PORT_FIBRE;
2109 cmd->transceiver = XCVR_INTERNAL;
2110
2111 status = RTL_R32(TBICSR);
2112 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
2113 cmd->autoneg = !!(status & TBINwEnable);
2114
2115 ethtool_cmd_speed_set(cmd, SPEED_1000);
2116 cmd->duplex = DUPLEX_FULL; /* Always set */
2117
2118 return 0;
2119 }
2120
2121 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
2122 {
2123 struct rtl8169_private *tp = netdev_priv(dev);
2124
2125 return mii_ethtool_gset(&tp->mii, cmd);
2126 }
2127
2128 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2129 {
2130 struct rtl8169_private *tp = netdev_priv(dev);
2131 int rc;
2132
2133 rtl_lock_work(tp);
2134 rc = tp->get_settings(dev, cmd);
2135 rtl_unlock_work(tp);
2136
2137 return rc;
2138 }
2139
2140 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2141 void *p)
2142 {
2143 struct rtl8169_private *tp = netdev_priv(dev);
2144 u32 __iomem *data = tp->mmio_addr;
2145 u32 *dw = p;
2146 int i;
2147
2148 rtl_lock_work(tp);
2149 for (i = 0; i < R8169_REGS_SIZE; i += 4)
2150 memcpy_fromio(dw++, data++, 4);
2151 rtl_unlock_work(tp);
2152 }
2153
2154 static u32 rtl8169_get_msglevel(struct net_device *dev)
2155 {
2156 struct rtl8169_private *tp = netdev_priv(dev);
2157
2158 return tp->msg_enable;
2159 }
2160
2161 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2162 {
2163 struct rtl8169_private *tp = netdev_priv(dev);
2164
2165 tp->msg_enable = value;
2166 }
2167
2168 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2169 "tx_packets",
2170 "rx_packets",
2171 "tx_errors",
2172 "rx_errors",
2173 "rx_missed",
2174 "align_errors",
2175 "tx_single_collisions",
2176 "tx_multi_collisions",
2177 "unicast",
2178 "broadcast",
2179 "multicast",
2180 "tx_aborted",
2181 "tx_underrun",
2182 };
2183
2184 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
2185 {
2186 switch (sset) {
2187 case ETH_SS_STATS:
2188 return ARRAY_SIZE(rtl8169_gstrings);
2189 default:
2190 return -EOPNOTSUPP;
2191 }
2192 }
2193
2194 DECLARE_RTL_COND(rtl_counters_cond)
2195 {
2196 void __iomem *ioaddr = tp->mmio_addr;
2197
2198 return RTL_R32(CounterAddrLow) & (CounterReset | CounterDump);
2199 }
2200
2201 static bool rtl8169_do_counters(struct net_device *dev, u32 counter_cmd)
2202 {
2203 struct rtl8169_private *tp = netdev_priv(dev);
2204 void __iomem *ioaddr = tp->mmio_addr;
2205 dma_addr_t paddr = tp->counters_phys_addr;
2206 u32 cmd;
2207 bool ret;
2208
2209 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
2210 cmd = (u64)paddr & DMA_BIT_MASK(32);
2211 RTL_W32(CounterAddrLow, cmd);
2212 RTL_W32(CounterAddrLow, cmd | counter_cmd);
2213
2214 ret = rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
2215
2216 RTL_W32(CounterAddrLow, 0);
2217 RTL_W32(CounterAddrHigh, 0);
2218
2219 return ret;
2220 }
2221
2222 static bool rtl8169_reset_counters(struct net_device *dev)
2223 {
2224 struct rtl8169_private *tp = netdev_priv(dev);
2225
2226 /*
2227 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
2228 * tally counters.
2229 */
2230 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
2231 return true;
2232
2233 return rtl8169_do_counters(dev, CounterReset);
2234 }
2235
2236 static bool rtl8169_update_counters(struct net_device *dev)
2237 {
2238 struct rtl8169_private *tp = netdev_priv(dev);
2239 void __iomem *ioaddr = tp->mmio_addr;
2240
2241 /*
2242 * Some chips are unable to dump tally counters when the receiver
2243 * is disabled.
2244 */
2245 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
2246 return true;
2247
2248 return rtl8169_do_counters(dev, CounterDump);
2249 }
2250
2251 static bool rtl8169_init_counter_offsets(struct net_device *dev)
2252 {
2253 struct rtl8169_private *tp = netdev_priv(dev);
2254 struct rtl8169_counters *counters = tp->counters;
2255 bool ret = false;
2256
2257 /*
2258 * rtl8169_init_counter_offsets is called from rtl_open. On chip
2259 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
2260 * reset by a power cycle, while the counter values collected by the
2261 * driver are reset at every driver unload/load cycle.
2262 *
2263 * To make sure the HW values returned by @get_stats64 match the SW
2264 * values, we collect the initial values at first open(*) and use them
2265 * as offsets to normalize the values returned by @get_stats64.
2266 *
2267 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
2268 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
2269 * set at open time by rtl_hw_start.
2270 */
2271
2272 if (tp->tc_offset.inited)
2273 return true;
2274
2275 /* If both, reset and update fail, propagate to caller. */
2276 if (rtl8169_reset_counters(dev))
2277 ret = true;
2278
2279 if (rtl8169_update_counters(dev))
2280 ret = true;
2281
2282 tp->tc_offset.tx_errors = counters->tx_errors;
2283 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
2284 tp->tc_offset.tx_aborted = counters->tx_aborted;
2285 tp->tc_offset.inited = true;
2286
2287 return ret;
2288 }
2289
2290 static void rtl8169_get_ethtool_stats(struct net_device *dev,
2291 struct ethtool_stats *stats, u64 *data)
2292 {
2293 struct rtl8169_private *tp = netdev_priv(dev);
2294 struct rtl8169_counters *counters = tp->counters;
2295
2296 ASSERT_RTNL();
2297
2298 rtl8169_update_counters(dev);
2299
2300 data[0] = le64_to_cpu(counters->tx_packets);
2301 data[1] = le64_to_cpu(counters->rx_packets);
2302 data[2] = le64_to_cpu(counters->tx_errors);
2303 data[3] = le32_to_cpu(counters->rx_errors);
2304 data[4] = le16_to_cpu(counters->rx_missed);
2305 data[5] = le16_to_cpu(counters->align_errors);
2306 data[6] = le32_to_cpu(counters->tx_one_collision);
2307 data[7] = le32_to_cpu(counters->tx_multi_collision);
2308 data[8] = le64_to_cpu(counters->rx_unicast);
2309 data[9] = le64_to_cpu(counters->rx_broadcast);
2310 data[10] = le32_to_cpu(counters->rx_multicast);
2311 data[11] = le16_to_cpu(counters->tx_aborted);
2312 data[12] = le16_to_cpu(counters->tx_underun);
2313 }
2314
2315 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2316 {
2317 switch(stringset) {
2318 case ETH_SS_STATS:
2319 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2320 break;
2321 }
2322 }
2323
2324 static const struct ethtool_ops rtl8169_ethtool_ops = {
2325 .get_drvinfo = rtl8169_get_drvinfo,
2326 .get_regs_len = rtl8169_get_regs_len,
2327 .get_link = ethtool_op_get_link,
2328 .get_settings = rtl8169_get_settings,
2329 .set_settings = rtl8169_set_settings,
2330 .get_msglevel = rtl8169_get_msglevel,
2331 .set_msglevel = rtl8169_set_msglevel,
2332 .get_regs = rtl8169_get_regs,
2333 .get_wol = rtl8169_get_wol,
2334 .set_wol = rtl8169_set_wol,
2335 .get_strings = rtl8169_get_strings,
2336 .get_sset_count = rtl8169_get_sset_count,
2337 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2338 .get_ts_info = ethtool_op_get_ts_info,
2339 };
2340
2341 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2342 struct net_device *dev, u8 default_version)
2343 {
2344 void __iomem *ioaddr = tp->mmio_addr;
2345 /*
2346 * The driver currently handles the 8168Bf and the 8168Be identically
2347 * but they can be identified more specifically through the test below
2348 * if needed:
2349 *
2350 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2351 *
2352 * Same thing for the 8101Eb and the 8101Ec:
2353 *
2354 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2355 */
2356 static const struct rtl_mac_info {
2357 u32 mask;
2358 u32 val;
2359 int mac_version;
2360 } mac_info[] = {
2361 /* 8168EP family. */
2362 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2363 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2364 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2365
2366 /* 8168H family. */
2367 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2368 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2369
2370 /* 8168G family. */
2371 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
2372 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
2373 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2374 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2375
2376 /* 8168F family. */
2377 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
2378 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2379 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2380
2381 /* 8168E family. */
2382 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
2383 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2384 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2385 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2386
2387 /* 8168D family. */
2388 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2389 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
2390 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
2391
2392 /* 8168DP family. */
2393 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2394 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
2395 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
2396
2397 /* 8168C family. */
2398 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
2399 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
2400 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
2401 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
2402 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2403 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
2404 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
2405 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
2406 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
2407
2408 /* 8168B family. */
2409 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2410 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2411 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2412 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2413
2414 /* 8101 family. */
2415 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2416 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
2417 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
2418 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
2419 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2420 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2421 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2422 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2423 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2424 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2425 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2426 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2427 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
2428 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2429 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
2430 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2431 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2432 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
2433 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2434 /* FIXME: where did these entries come from ? -- FR */
2435 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2436 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2437
2438 /* 8110 family. */
2439 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2440 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2441 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2442 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2443 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2444 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2445
2446 /* Catch-all */
2447 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
2448 };
2449 const struct rtl_mac_info *p = mac_info;
2450 u32 reg;
2451
2452 reg = RTL_R32(TxConfig);
2453 while ((reg & p->mask) != p->val)
2454 p++;
2455 tp->mac_version = p->mac_version;
2456
2457 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2458 netif_notice(tp, probe, dev,
2459 "unknown MAC, using family default\n");
2460 tp->mac_version = default_version;
2461 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2462 tp->mac_version = tp->mii.supports_gmii ?
2463 RTL_GIGA_MAC_VER_42 :
2464 RTL_GIGA_MAC_VER_43;
2465 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2466 tp->mac_version = tp->mii.supports_gmii ?
2467 RTL_GIGA_MAC_VER_45 :
2468 RTL_GIGA_MAC_VER_47;
2469 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2470 tp->mac_version = tp->mii.supports_gmii ?
2471 RTL_GIGA_MAC_VER_46 :
2472 RTL_GIGA_MAC_VER_48;
2473 }
2474 }
2475
2476 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2477 {
2478 dprintk("mac_version = 0x%02x\n", tp->mac_version);
2479 }
2480
2481 struct phy_reg {
2482 u16 reg;
2483 u16 val;
2484 };
2485
2486 static void rtl_writephy_batch(struct rtl8169_private *tp,
2487 const struct phy_reg *regs, int len)
2488 {
2489 while (len-- > 0) {
2490 rtl_writephy(tp, regs->reg, regs->val);
2491 regs++;
2492 }
2493 }
2494
2495 #define PHY_READ 0x00000000
2496 #define PHY_DATA_OR 0x10000000
2497 #define PHY_DATA_AND 0x20000000
2498 #define PHY_BJMPN 0x30000000
2499 #define PHY_MDIO_CHG 0x40000000
2500 #define PHY_CLEAR_READCOUNT 0x70000000
2501 #define PHY_WRITE 0x80000000
2502 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2503 #define PHY_COMP_EQ_SKIPN 0xa0000000
2504 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2505 #define PHY_WRITE_PREVIOUS 0xc0000000
2506 #define PHY_SKIPN 0xd0000000
2507 #define PHY_DELAY_MS 0xe0000000
2508
2509 struct fw_info {
2510 u32 magic;
2511 char version[RTL_VER_SIZE];
2512 __le32 fw_start;
2513 __le32 fw_len;
2514 u8 chksum;
2515 } __packed;
2516
2517 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2518
2519 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2520 {
2521 const struct firmware *fw = rtl_fw->fw;
2522 struct fw_info *fw_info = (struct fw_info *)fw->data;
2523 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2524 char *version = rtl_fw->version;
2525 bool rc = false;
2526
2527 if (fw->size < FW_OPCODE_SIZE)
2528 goto out;
2529
2530 if (!fw_info->magic) {
2531 size_t i, size, start;
2532 u8 checksum = 0;
2533
2534 if (fw->size < sizeof(*fw_info))
2535 goto out;
2536
2537 for (i = 0; i < fw->size; i++)
2538 checksum += fw->data[i];
2539 if (checksum != 0)
2540 goto out;
2541
2542 start = le32_to_cpu(fw_info->fw_start);
2543 if (start > fw->size)
2544 goto out;
2545
2546 size = le32_to_cpu(fw_info->fw_len);
2547 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2548 goto out;
2549
2550 memcpy(version, fw_info->version, RTL_VER_SIZE);
2551
2552 pa->code = (__le32 *)(fw->data + start);
2553 pa->size = size;
2554 } else {
2555 if (fw->size % FW_OPCODE_SIZE)
2556 goto out;
2557
2558 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2559
2560 pa->code = (__le32 *)fw->data;
2561 pa->size = fw->size / FW_OPCODE_SIZE;
2562 }
2563 version[RTL_VER_SIZE - 1] = 0;
2564
2565 rc = true;
2566 out:
2567 return rc;
2568 }
2569
2570 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2571 struct rtl_fw_phy_action *pa)
2572 {
2573 bool rc = false;
2574 size_t index;
2575
2576 for (index = 0; index < pa->size; index++) {
2577 u32 action = le32_to_cpu(pa->code[index]);
2578 u32 regno = (action & 0x0fff0000) >> 16;
2579
2580 switch(action & 0xf0000000) {
2581 case PHY_READ:
2582 case PHY_DATA_OR:
2583 case PHY_DATA_AND:
2584 case PHY_MDIO_CHG:
2585 case PHY_CLEAR_READCOUNT:
2586 case PHY_WRITE:
2587 case PHY_WRITE_PREVIOUS:
2588 case PHY_DELAY_MS:
2589 break;
2590
2591 case PHY_BJMPN:
2592 if (regno > index) {
2593 netif_err(tp, ifup, tp->dev,
2594 "Out of range of firmware\n");
2595 goto out;
2596 }
2597 break;
2598 case PHY_READCOUNT_EQ_SKIP:
2599 if (index + 2 >= pa->size) {
2600 netif_err(tp, ifup, tp->dev,
2601 "Out of range of firmware\n");
2602 goto out;
2603 }
2604 break;
2605 case PHY_COMP_EQ_SKIPN:
2606 case PHY_COMP_NEQ_SKIPN:
2607 case PHY_SKIPN:
2608 if (index + 1 + regno >= pa->size) {
2609 netif_err(tp, ifup, tp->dev,
2610 "Out of range of firmware\n");
2611 goto out;
2612 }
2613 break;
2614
2615 default:
2616 netif_err(tp, ifup, tp->dev,
2617 "Invalid action 0x%08x\n", action);
2618 goto out;
2619 }
2620 }
2621 rc = true;
2622 out:
2623 return rc;
2624 }
2625
2626 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2627 {
2628 struct net_device *dev = tp->dev;
2629 int rc = -EINVAL;
2630
2631 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2632 netif_err(tp, ifup, dev, "invalid firmware\n");
2633 goto out;
2634 }
2635
2636 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2637 rc = 0;
2638 out:
2639 return rc;
2640 }
2641
2642 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2643 {
2644 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2645 struct mdio_ops org, *ops = &tp->mdio_ops;
2646 u32 predata, count;
2647 size_t index;
2648
2649 predata = count = 0;
2650 org.write = ops->write;
2651 org.read = ops->read;
2652
2653 for (index = 0; index < pa->size; ) {
2654 u32 action = le32_to_cpu(pa->code[index]);
2655 u32 data = action & 0x0000ffff;
2656 u32 regno = (action & 0x0fff0000) >> 16;
2657
2658 if (!action)
2659 break;
2660
2661 switch(action & 0xf0000000) {
2662 case PHY_READ:
2663 predata = rtl_readphy(tp, regno);
2664 count++;
2665 index++;
2666 break;
2667 case PHY_DATA_OR:
2668 predata |= data;
2669 index++;
2670 break;
2671 case PHY_DATA_AND:
2672 predata &= data;
2673 index++;
2674 break;
2675 case PHY_BJMPN:
2676 index -= regno;
2677 break;
2678 case PHY_MDIO_CHG:
2679 if (data == 0) {
2680 ops->write = org.write;
2681 ops->read = org.read;
2682 } else if (data == 1) {
2683 ops->write = mac_mcu_write;
2684 ops->read = mac_mcu_read;
2685 }
2686
2687 index++;
2688 break;
2689 case PHY_CLEAR_READCOUNT:
2690 count = 0;
2691 index++;
2692 break;
2693 case PHY_WRITE:
2694 rtl_writephy(tp, regno, data);
2695 index++;
2696 break;
2697 case PHY_READCOUNT_EQ_SKIP:
2698 index += (count == data) ? 2 : 1;
2699 break;
2700 case PHY_COMP_EQ_SKIPN:
2701 if (predata == data)
2702 index += regno;
2703 index++;
2704 break;
2705 case PHY_COMP_NEQ_SKIPN:
2706 if (predata != data)
2707 index += regno;
2708 index++;
2709 break;
2710 case PHY_WRITE_PREVIOUS:
2711 rtl_writephy(tp, regno, predata);
2712 index++;
2713 break;
2714 case PHY_SKIPN:
2715 index += regno + 1;
2716 break;
2717 case PHY_DELAY_MS:
2718 mdelay(data);
2719 index++;
2720 break;
2721
2722 default:
2723 BUG();
2724 }
2725 }
2726
2727 ops->write = org.write;
2728 ops->read = org.read;
2729 }
2730
2731 static void rtl_release_firmware(struct rtl8169_private *tp)
2732 {
2733 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2734 release_firmware(tp->rtl_fw->fw);
2735 kfree(tp->rtl_fw);
2736 }
2737 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2738 }
2739
2740 static void rtl_apply_firmware(struct rtl8169_private *tp)
2741 {
2742 struct rtl_fw *rtl_fw = tp->rtl_fw;
2743
2744 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2745 if (!IS_ERR_OR_NULL(rtl_fw))
2746 rtl_phy_write_fw(tp, rtl_fw);
2747 }
2748
2749 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2750 {
2751 if (rtl_readphy(tp, reg) != val)
2752 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2753 else
2754 rtl_apply_firmware(tp);
2755 }
2756
2757 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2758 {
2759 static const struct phy_reg phy_reg_init[] = {
2760 { 0x1f, 0x0001 },
2761 { 0x06, 0x006e },
2762 { 0x08, 0x0708 },
2763 { 0x15, 0x4000 },
2764 { 0x18, 0x65c7 },
2765
2766 { 0x1f, 0x0001 },
2767 { 0x03, 0x00a1 },
2768 { 0x02, 0x0008 },
2769 { 0x01, 0x0120 },
2770 { 0x00, 0x1000 },
2771 { 0x04, 0x0800 },
2772 { 0x04, 0x0000 },
2773
2774 { 0x03, 0xff41 },
2775 { 0x02, 0xdf60 },
2776 { 0x01, 0x0140 },
2777 { 0x00, 0x0077 },
2778 { 0x04, 0x7800 },
2779 { 0x04, 0x7000 },
2780
2781 { 0x03, 0x802f },
2782 { 0x02, 0x4f02 },
2783 { 0x01, 0x0409 },
2784 { 0x00, 0xf0f9 },
2785 { 0x04, 0x9800 },
2786 { 0x04, 0x9000 },
2787
2788 { 0x03, 0xdf01 },
2789 { 0x02, 0xdf20 },
2790 { 0x01, 0xff95 },
2791 { 0x00, 0xba00 },
2792 { 0x04, 0xa800 },
2793 { 0x04, 0xa000 },
2794
2795 { 0x03, 0xff41 },
2796 { 0x02, 0xdf20 },
2797 { 0x01, 0x0140 },
2798 { 0x00, 0x00bb },
2799 { 0x04, 0xb800 },
2800 { 0x04, 0xb000 },
2801
2802 { 0x03, 0xdf41 },
2803 { 0x02, 0xdc60 },
2804 { 0x01, 0x6340 },
2805 { 0x00, 0x007d },
2806 { 0x04, 0xd800 },
2807 { 0x04, 0xd000 },
2808
2809 { 0x03, 0xdf01 },
2810 { 0x02, 0xdf20 },
2811 { 0x01, 0x100a },
2812 { 0x00, 0xa0ff },
2813 { 0x04, 0xf800 },
2814 { 0x04, 0xf000 },
2815
2816 { 0x1f, 0x0000 },
2817 { 0x0b, 0x0000 },
2818 { 0x00, 0x9200 }
2819 };
2820
2821 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2822 }
2823
2824 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2825 {
2826 static const struct phy_reg phy_reg_init[] = {
2827 { 0x1f, 0x0002 },
2828 { 0x01, 0x90d0 },
2829 { 0x1f, 0x0000 }
2830 };
2831
2832 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2833 }
2834
2835 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2836 {
2837 struct pci_dev *pdev = tp->pci_dev;
2838
2839 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2840 (pdev->subsystem_device != 0xe000))
2841 return;
2842
2843 rtl_writephy(tp, 0x1f, 0x0001);
2844 rtl_writephy(tp, 0x10, 0xf01b);
2845 rtl_writephy(tp, 0x1f, 0x0000);
2846 }
2847
2848 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2849 {
2850 static const struct phy_reg phy_reg_init[] = {
2851 { 0x1f, 0x0001 },
2852 { 0x04, 0x0000 },
2853 { 0x03, 0x00a1 },
2854 { 0x02, 0x0008 },
2855 { 0x01, 0x0120 },
2856 { 0x00, 0x1000 },
2857 { 0x04, 0x0800 },
2858 { 0x04, 0x9000 },
2859 { 0x03, 0x802f },
2860 { 0x02, 0x4f02 },
2861 { 0x01, 0x0409 },
2862 { 0x00, 0xf099 },
2863 { 0x04, 0x9800 },
2864 { 0x04, 0xa000 },
2865 { 0x03, 0xdf01 },
2866 { 0x02, 0xdf20 },
2867 { 0x01, 0xff95 },
2868 { 0x00, 0xba00 },
2869 { 0x04, 0xa800 },
2870 { 0x04, 0xf000 },
2871 { 0x03, 0xdf01 },
2872 { 0x02, 0xdf20 },
2873 { 0x01, 0x101a },
2874 { 0x00, 0xa0ff },
2875 { 0x04, 0xf800 },
2876 { 0x04, 0x0000 },
2877 { 0x1f, 0x0000 },
2878
2879 { 0x1f, 0x0001 },
2880 { 0x10, 0xf41b },
2881 { 0x14, 0xfb54 },
2882 { 0x18, 0xf5c7 },
2883 { 0x1f, 0x0000 },
2884
2885 { 0x1f, 0x0001 },
2886 { 0x17, 0x0cc0 },
2887 { 0x1f, 0x0000 }
2888 };
2889
2890 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2891
2892 rtl8169scd_hw_phy_config_quirk(tp);
2893 }
2894
2895 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2896 {
2897 static const struct phy_reg phy_reg_init[] = {
2898 { 0x1f, 0x0001 },
2899 { 0x04, 0x0000 },
2900 { 0x03, 0x00a1 },
2901 { 0x02, 0x0008 },
2902 { 0x01, 0x0120 },
2903 { 0x00, 0x1000 },
2904 { 0x04, 0x0800 },
2905 { 0x04, 0x9000 },
2906 { 0x03, 0x802f },
2907 { 0x02, 0x4f02 },
2908 { 0x01, 0x0409 },
2909 { 0x00, 0xf099 },
2910 { 0x04, 0x9800 },
2911 { 0x04, 0xa000 },
2912 { 0x03, 0xdf01 },
2913 { 0x02, 0xdf20 },
2914 { 0x01, 0xff95 },
2915 { 0x00, 0xba00 },
2916 { 0x04, 0xa800 },
2917 { 0x04, 0xf000 },
2918 { 0x03, 0xdf01 },
2919 { 0x02, 0xdf20 },
2920 { 0x01, 0x101a },
2921 { 0x00, 0xa0ff },
2922 { 0x04, 0xf800 },
2923 { 0x04, 0x0000 },
2924 { 0x1f, 0x0000 },
2925
2926 { 0x1f, 0x0001 },
2927 { 0x0b, 0x8480 },
2928 { 0x1f, 0x0000 },
2929
2930 { 0x1f, 0x0001 },
2931 { 0x18, 0x67c7 },
2932 { 0x04, 0x2000 },
2933 { 0x03, 0x002f },
2934 { 0x02, 0x4360 },
2935 { 0x01, 0x0109 },
2936 { 0x00, 0x3022 },
2937 { 0x04, 0x2800 },
2938 { 0x1f, 0x0000 },
2939
2940 { 0x1f, 0x0001 },
2941 { 0x17, 0x0cc0 },
2942 { 0x1f, 0x0000 }
2943 };
2944
2945 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2946 }
2947
2948 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2949 {
2950 static const struct phy_reg phy_reg_init[] = {
2951 { 0x10, 0xf41b },
2952 { 0x1f, 0x0000 }
2953 };
2954
2955 rtl_writephy(tp, 0x1f, 0x0001);
2956 rtl_patchphy(tp, 0x16, 1 << 0);
2957
2958 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2959 }
2960
2961 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2962 {
2963 static const struct phy_reg phy_reg_init[] = {
2964 { 0x1f, 0x0001 },
2965 { 0x10, 0xf41b },
2966 { 0x1f, 0x0000 }
2967 };
2968
2969 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2970 }
2971
2972 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2973 {
2974 static const struct phy_reg phy_reg_init[] = {
2975 { 0x1f, 0x0000 },
2976 { 0x1d, 0x0f00 },
2977 { 0x1f, 0x0002 },
2978 { 0x0c, 0x1ec8 },
2979 { 0x1f, 0x0000 }
2980 };
2981
2982 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2983 }
2984
2985 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2986 {
2987 static const struct phy_reg phy_reg_init[] = {
2988 { 0x1f, 0x0001 },
2989 { 0x1d, 0x3d98 },
2990 { 0x1f, 0x0000 }
2991 };
2992
2993 rtl_writephy(tp, 0x1f, 0x0000);
2994 rtl_patchphy(tp, 0x14, 1 << 5);
2995 rtl_patchphy(tp, 0x0d, 1 << 5);
2996
2997 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2998 }
2999
3000 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
3001 {
3002 static const struct phy_reg phy_reg_init[] = {
3003 { 0x1f, 0x0001 },
3004 { 0x12, 0x2300 },
3005 { 0x1f, 0x0002 },
3006 { 0x00, 0x88d4 },
3007 { 0x01, 0x82b1 },
3008 { 0x03, 0x7002 },
3009 { 0x08, 0x9e30 },
3010 { 0x09, 0x01f0 },
3011 { 0x0a, 0x5500 },
3012 { 0x0c, 0x00c8 },
3013 { 0x1f, 0x0003 },
3014 { 0x12, 0xc096 },
3015 { 0x16, 0x000a },
3016 { 0x1f, 0x0000 },
3017 { 0x1f, 0x0000 },
3018 { 0x09, 0x2000 },
3019 { 0x09, 0x0000 }
3020 };
3021
3022 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3023
3024 rtl_patchphy(tp, 0x14, 1 << 5);
3025 rtl_patchphy(tp, 0x0d, 1 << 5);
3026 rtl_writephy(tp, 0x1f, 0x0000);
3027 }
3028
3029 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
3030 {
3031 static const struct phy_reg phy_reg_init[] = {
3032 { 0x1f, 0x0001 },
3033 { 0x12, 0x2300 },
3034 { 0x03, 0x802f },
3035 { 0x02, 0x4f02 },
3036 { 0x01, 0x0409 },
3037 { 0x00, 0xf099 },
3038 { 0x04, 0x9800 },
3039 { 0x04, 0x9000 },
3040 { 0x1d, 0x3d98 },
3041 { 0x1f, 0x0002 },
3042 { 0x0c, 0x7eb8 },
3043 { 0x06, 0x0761 },
3044 { 0x1f, 0x0003 },
3045 { 0x16, 0x0f0a },
3046 { 0x1f, 0x0000 }
3047 };
3048
3049 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3050
3051 rtl_patchphy(tp, 0x16, 1 << 0);
3052 rtl_patchphy(tp, 0x14, 1 << 5);
3053 rtl_patchphy(tp, 0x0d, 1 << 5);
3054 rtl_writephy(tp, 0x1f, 0x0000);
3055 }
3056
3057 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
3058 {
3059 static const struct phy_reg phy_reg_init[] = {
3060 { 0x1f, 0x0001 },
3061 { 0x12, 0x2300 },
3062 { 0x1d, 0x3d98 },
3063 { 0x1f, 0x0002 },
3064 { 0x0c, 0x7eb8 },
3065 { 0x06, 0x5461 },
3066 { 0x1f, 0x0003 },
3067 { 0x16, 0x0f0a },
3068 { 0x1f, 0x0000 }
3069 };
3070
3071 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3072
3073 rtl_patchphy(tp, 0x16, 1 << 0);
3074 rtl_patchphy(tp, 0x14, 1 << 5);
3075 rtl_patchphy(tp, 0x0d, 1 << 5);
3076 rtl_writephy(tp, 0x1f, 0x0000);
3077 }
3078
3079 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
3080 {
3081 rtl8168c_3_hw_phy_config(tp);
3082 }
3083
3084 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
3085 {
3086 static const struct phy_reg phy_reg_init_0[] = {
3087 /* Channel Estimation */
3088 { 0x1f, 0x0001 },
3089 { 0x06, 0x4064 },
3090 { 0x07, 0x2863 },
3091 { 0x08, 0x059c },
3092 { 0x09, 0x26b4 },
3093 { 0x0a, 0x6a19 },
3094 { 0x0b, 0xdcc8 },
3095 { 0x10, 0xf06d },
3096 { 0x14, 0x7f68 },
3097 { 0x18, 0x7fd9 },
3098 { 0x1c, 0xf0ff },
3099 { 0x1d, 0x3d9c },
3100 { 0x1f, 0x0003 },
3101 { 0x12, 0xf49f },
3102 { 0x13, 0x070b },
3103 { 0x1a, 0x05ad },
3104 { 0x14, 0x94c0 },
3105
3106 /*
3107 * Tx Error Issue
3108 * Enhance line driver power
3109 */
3110 { 0x1f, 0x0002 },
3111 { 0x06, 0x5561 },
3112 { 0x1f, 0x0005 },
3113 { 0x05, 0x8332 },
3114 { 0x06, 0x5561 },
3115
3116 /*
3117 * Can not link to 1Gbps with bad cable
3118 * Decrease SNR threshold form 21.07dB to 19.04dB
3119 */
3120 { 0x1f, 0x0001 },
3121 { 0x17, 0x0cc0 },
3122
3123 { 0x1f, 0x0000 },
3124 { 0x0d, 0xf880 }
3125 };
3126
3127 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3128
3129 /*
3130 * Rx Error Issue
3131 * Fine Tune Switching regulator parameter
3132 */
3133 rtl_writephy(tp, 0x1f, 0x0002);
3134 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3135 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
3136
3137 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3138 static const struct phy_reg phy_reg_init[] = {
3139 { 0x1f, 0x0002 },
3140 { 0x05, 0x669a },
3141 { 0x1f, 0x0005 },
3142 { 0x05, 0x8330 },
3143 { 0x06, 0x669a },
3144 { 0x1f, 0x0002 }
3145 };
3146 int val;
3147
3148 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3149
3150 val = rtl_readphy(tp, 0x0d);
3151
3152 if ((val & 0x00ff) != 0x006c) {
3153 static const u32 set[] = {
3154 0x0065, 0x0066, 0x0067, 0x0068,
3155 0x0069, 0x006a, 0x006b, 0x006c
3156 };
3157 int i;
3158
3159 rtl_writephy(tp, 0x1f, 0x0002);
3160
3161 val &= 0xff00;
3162 for (i = 0; i < ARRAY_SIZE(set); i++)
3163 rtl_writephy(tp, 0x0d, val | set[i]);
3164 }
3165 } else {
3166 static const struct phy_reg phy_reg_init[] = {
3167 { 0x1f, 0x0002 },
3168 { 0x05, 0x6662 },
3169 { 0x1f, 0x0005 },
3170 { 0x05, 0x8330 },
3171 { 0x06, 0x6662 }
3172 };
3173
3174 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3175 }
3176
3177 /* RSET couple improve */
3178 rtl_writephy(tp, 0x1f, 0x0002);
3179 rtl_patchphy(tp, 0x0d, 0x0300);
3180 rtl_patchphy(tp, 0x0f, 0x0010);
3181
3182 /* Fine tune PLL performance */
3183 rtl_writephy(tp, 0x1f, 0x0002);
3184 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3185 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3186
3187 rtl_writephy(tp, 0x1f, 0x0005);
3188 rtl_writephy(tp, 0x05, 0x001b);
3189
3190 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3191
3192 rtl_writephy(tp, 0x1f, 0x0000);
3193 }
3194
3195 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3196 {
3197 static const struct phy_reg phy_reg_init_0[] = {
3198 /* Channel Estimation */
3199 { 0x1f, 0x0001 },
3200 { 0x06, 0x4064 },
3201 { 0x07, 0x2863 },
3202 { 0x08, 0x059c },
3203 { 0x09, 0x26b4 },
3204 { 0x0a, 0x6a19 },
3205 { 0x0b, 0xdcc8 },
3206 { 0x10, 0xf06d },
3207 { 0x14, 0x7f68 },
3208 { 0x18, 0x7fd9 },
3209 { 0x1c, 0xf0ff },
3210 { 0x1d, 0x3d9c },
3211 { 0x1f, 0x0003 },
3212 { 0x12, 0xf49f },
3213 { 0x13, 0x070b },
3214 { 0x1a, 0x05ad },
3215 { 0x14, 0x94c0 },
3216
3217 /*
3218 * Tx Error Issue
3219 * Enhance line driver power
3220 */
3221 { 0x1f, 0x0002 },
3222 { 0x06, 0x5561 },
3223 { 0x1f, 0x0005 },
3224 { 0x05, 0x8332 },
3225 { 0x06, 0x5561 },
3226
3227 /*
3228 * Can not link to 1Gbps with bad cable
3229 * Decrease SNR threshold form 21.07dB to 19.04dB
3230 */
3231 { 0x1f, 0x0001 },
3232 { 0x17, 0x0cc0 },
3233
3234 { 0x1f, 0x0000 },
3235 { 0x0d, 0xf880 }
3236 };
3237
3238 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3239
3240 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3241 static const struct phy_reg phy_reg_init[] = {
3242 { 0x1f, 0x0002 },
3243 { 0x05, 0x669a },
3244 { 0x1f, 0x0005 },
3245 { 0x05, 0x8330 },
3246 { 0x06, 0x669a },
3247
3248 { 0x1f, 0x0002 }
3249 };
3250 int val;
3251
3252 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3253
3254 val = rtl_readphy(tp, 0x0d);
3255 if ((val & 0x00ff) != 0x006c) {
3256 static const u32 set[] = {
3257 0x0065, 0x0066, 0x0067, 0x0068,
3258 0x0069, 0x006a, 0x006b, 0x006c
3259 };
3260 int i;
3261
3262 rtl_writephy(tp, 0x1f, 0x0002);
3263
3264 val &= 0xff00;
3265 for (i = 0; i < ARRAY_SIZE(set); i++)
3266 rtl_writephy(tp, 0x0d, val | set[i]);
3267 }
3268 } else {
3269 static const struct phy_reg phy_reg_init[] = {
3270 { 0x1f, 0x0002 },
3271 { 0x05, 0x2642 },
3272 { 0x1f, 0x0005 },
3273 { 0x05, 0x8330 },
3274 { 0x06, 0x2642 }
3275 };
3276
3277 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3278 }
3279
3280 /* Fine tune PLL performance */
3281 rtl_writephy(tp, 0x1f, 0x0002);
3282 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3283 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3284
3285 /* Switching regulator Slew rate */
3286 rtl_writephy(tp, 0x1f, 0x0002);
3287 rtl_patchphy(tp, 0x0f, 0x0017);
3288
3289 rtl_writephy(tp, 0x1f, 0x0005);
3290 rtl_writephy(tp, 0x05, 0x001b);
3291
3292 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3293
3294 rtl_writephy(tp, 0x1f, 0x0000);
3295 }
3296
3297 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3298 {
3299 static const struct phy_reg phy_reg_init[] = {
3300 { 0x1f, 0x0002 },
3301 { 0x10, 0x0008 },
3302 { 0x0d, 0x006c },
3303
3304 { 0x1f, 0x0000 },
3305 { 0x0d, 0xf880 },
3306
3307 { 0x1f, 0x0001 },
3308 { 0x17, 0x0cc0 },
3309
3310 { 0x1f, 0x0001 },
3311 { 0x0b, 0xa4d8 },
3312 { 0x09, 0x281c },
3313 { 0x07, 0x2883 },
3314 { 0x0a, 0x6b35 },
3315 { 0x1d, 0x3da4 },
3316 { 0x1c, 0xeffd },
3317 { 0x14, 0x7f52 },
3318 { 0x18, 0x7fc6 },
3319 { 0x08, 0x0601 },
3320 { 0x06, 0x4063 },
3321 { 0x10, 0xf074 },
3322 { 0x1f, 0x0003 },
3323 { 0x13, 0x0789 },
3324 { 0x12, 0xf4bd },
3325 { 0x1a, 0x04fd },
3326 { 0x14, 0x84b0 },
3327 { 0x1f, 0x0000 },
3328 { 0x00, 0x9200 },
3329
3330 { 0x1f, 0x0005 },
3331 { 0x01, 0x0340 },
3332 { 0x1f, 0x0001 },
3333 { 0x04, 0x4000 },
3334 { 0x03, 0x1d21 },
3335 { 0x02, 0x0c32 },
3336 { 0x01, 0x0200 },
3337 { 0x00, 0x5554 },
3338 { 0x04, 0x4800 },
3339 { 0x04, 0x4000 },
3340 { 0x04, 0xf000 },
3341 { 0x03, 0xdf01 },
3342 { 0x02, 0xdf20 },
3343 { 0x01, 0x101a },
3344 { 0x00, 0xa0ff },
3345 { 0x04, 0xf800 },
3346 { 0x04, 0xf000 },
3347 { 0x1f, 0x0000 },
3348
3349 { 0x1f, 0x0007 },
3350 { 0x1e, 0x0023 },
3351 { 0x16, 0x0000 },
3352 { 0x1f, 0x0000 }
3353 };
3354
3355 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3356 }
3357
3358 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3359 {
3360 static const struct phy_reg phy_reg_init[] = {
3361 { 0x1f, 0x0001 },
3362 { 0x17, 0x0cc0 },
3363
3364 { 0x1f, 0x0007 },
3365 { 0x1e, 0x002d },
3366 { 0x18, 0x0040 },
3367 { 0x1f, 0x0000 }
3368 };
3369
3370 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3371 rtl_patchphy(tp, 0x0d, 1 << 5);
3372 }
3373
3374 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3375 {
3376 static const struct phy_reg phy_reg_init[] = {
3377 /* Enable Delay cap */
3378 { 0x1f, 0x0005 },
3379 { 0x05, 0x8b80 },
3380 { 0x06, 0xc896 },
3381 { 0x1f, 0x0000 },
3382
3383 /* Channel estimation fine tune */
3384 { 0x1f, 0x0001 },
3385 { 0x0b, 0x6c20 },
3386 { 0x07, 0x2872 },
3387 { 0x1c, 0xefff },
3388 { 0x1f, 0x0003 },
3389 { 0x14, 0x6420 },
3390 { 0x1f, 0x0000 },
3391
3392 /* Update PFM & 10M TX idle timer */
3393 { 0x1f, 0x0007 },
3394 { 0x1e, 0x002f },
3395 { 0x15, 0x1919 },
3396 { 0x1f, 0x0000 },
3397
3398 { 0x1f, 0x0007 },
3399 { 0x1e, 0x00ac },
3400 { 0x18, 0x0006 },
3401 { 0x1f, 0x0000 }
3402 };
3403
3404 rtl_apply_firmware(tp);
3405
3406 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3407
3408 /* DCO enable for 10M IDLE Power */
3409 rtl_writephy(tp, 0x1f, 0x0007);
3410 rtl_writephy(tp, 0x1e, 0x0023);
3411 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3412 rtl_writephy(tp, 0x1f, 0x0000);
3413
3414 /* For impedance matching */
3415 rtl_writephy(tp, 0x1f, 0x0002);
3416 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3417 rtl_writephy(tp, 0x1f, 0x0000);
3418
3419 /* PHY auto speed down */
3420 rtl_writephy(tp, 0x1f, 0x0007);
3421 rtl_writephy(tp, 0x1e, 0x002d);
3422 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3423 rtl_writephy(tp, 0x1f, 0x0000);
3424 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3425
3426 rtl_writephy(tp, 0x1f, 0x0005);
3427 rtl_writephy(tp, 0x05, 0x8b86);
3428 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3429 rtl_writephy(tp, 0x1f, 0x0000);
3430
3431 rtl_writephy(tp, 0x1f, 0x0005);
3432 rtl_writephy(tp, 0x05, 0x8b85);
3433 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3434 rtl_writephy(tp, 0x1f, 0x0007);
3435 rtl_writephy(tp, 0x1e, 0x0020);
3436 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3437 rtl_writephy(tp, 0x1f, 0x0006);
3438 rtl_writephy(tp, 0x00, 0x5a00);
3439 rtl_writephy(tp, 0x1f, 0x0000);
3440 rtl_writephy(tp, 0x0d, 0x0007);
3441 rtl_writephy(tp, 0x0e, 0x003c);
3442 rtl_writephy(tp, 0x0d, 0x4007);
3443 rtl_writephy(tp, 0x0e, 0x0000);
3444 rtl_writephy(tp, 0x0d, 0x0000);
3445 }
3446
3447 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3448 {
3449 const u16 w[] = {
3450 addr[0] | (addr[1] << 8),
3451 addr[2] | (addr[3] << 8),
3452 addr[4] | (addr[5] << 8)
3453 };
3454 const struct exgmac_reg e[] = {
3455 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3456 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3457 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3458 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3459 };
3460
3461 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3462 }
3463
3464 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3465 {
3466 static const struct phy_reg phy_reg_init[] = {
3467 /* Enable Delay cap */
3468 { 0x1f, 0x0004 },
3469 { 0x1f, 0x0007 },
3470 { 0x1e, 0x00ac },
3471 { 0x18, 0x0006 },
3472 { 0x1f, 0x0002 },
3473 { 0x1f, 0x0000 },
3474 { 0x1f, 0x0000 },
3475
3476 /* Channel estimation fine tune */
3477 { 0x1f, 0x0003 },
3478 { 0x09, 0xa20f },
3479 { 0x1f, 0x0000 },
3480 { 0x1f, 0x0000 },
3481
3482 /* Green Setting */
3483 { 0x1f, 0x0005 },
3484 { 0x05, 0x8b5b },
3485 { 0x06, 0x9222 },
3486 { 0x05, 0x8b6d },
3487 { 0x06, 0x8000 },
3488 { 0x05, 0x8b76 },
3489 { 0x06, 0x8000 },
3490 { 0x1f, 0x0000 }
3491 };
3492
3493 rtl_apply_firmware(tp);
3494
3495 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3496
3497 /* For 4-corner performance improve */
3498 rtl_writephy(tp, 0x1f, 0x0005);
3499 rtl_writephy(tp, 0x05, 0x8b80);
3500 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3501 rtl_writephy(tp, 0x1f, 0x0000);
3502
3503 /* PHY auto speed down */
3504 rtl_writephy(tp, 0x1f, 0x0004);
3505 rtl_writephy(tp, 0x1f, 0x0007);
3506 rtl_writephy(tp, 0x1e, 0x002d);
3507 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3508 rtl_writephy(tp, 0x1f, 0x0002);
3509 rtl_writephy(tp, 0x1f, 0x0000);
3510 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3511
3512 /* improve 10M EEE waveform */
3513 rtl_writephy(tp, 0x1f, 0x0005);
3514 rtl_writephy(tp, 0x05, 0x8b86);
3515 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3516 rtl_writephy(tp, 0x1f, 0x0000);
3517
3518 /* Improve 2-pair detection performance */
3519 rtl_writephy(tp, 0x1f, 0x0005);
3520 rtl_writephy(tp, 0x05, 0x8b85);
3521 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3522 rtl_writephy(tp, 0x1f, 0x0000);
3523
3524 /* EEE setting */
3525 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3526 rtl_writephy(tp, 0x1f, 0x0005);
3527 rtl_writephy(tp, 0x05, 0x8b85);
3528 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3529 rtl_writephy(tp, 0x1f, 0x0004);
3530 rtl_writephy(tp, 0x1f, 0x0007);
3531 rtl_writephy(tp, 0x1e, 0x0020);
3532 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3533 rtl_writephy(tp, 0x1f, 0x0002);
3534 rtl_writephy(tp, 0x1f, 0x0000);
3535 rtl_writephy(tp, 0x0d, 0x0007);
3536 rtl_writephy(tp, 0x0e, 0x003c);
3537 rtl_writephy(tp, 0x0d, 0x4007);
3538 rtl_writephy(tp, 0x0e, 0x0000);
3539 rtl_writephy(tp, 0x0d, 0x0000);
3540
3541 /* Green feature */
3542 rtl_writephy(tp, 0x1f, 0x0003);
3543 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3544 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3545 rtl_writephy(tp, 0x1f, 0x0000);
3546
3547 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3548 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3549 }
3550
3551 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3552 {
3553 /* For 4-corner performance improve */
3554 rtl_writephy(tp, 0x1f, 0x0005);
3555 rtl_writephy(tp, 0x05, 0x8b80);
3556 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3557 rtl_writephy(tp, 0x1f, 0x0000);
3558
3559 /* PHY auto speed down */
3560 rtl_writephy(tp, 0x1f, 0x0007);
3561 rtl_writephy(tp, 0x1e, 0x002d);
3562 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3563 rtl_writephy(tp, 0x1f, 0x0000);
3564 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3565
3566 /* Improve 10M EEE waveform */
3567 rtl_writephy(tp, 0x1f, 0x0005);
3568 rtl_writephy(tp, 0x05, 0x8b86);
3569 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3570 rtl_writephy(tp, 0x1f, 0x0000);
3571 }
3572
3573 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3574 {
3575 static const struct phy_reg phy_reg_init[] = {
3576 /* Channel estimation fine tune */
3577 { 0x1f, 0x0003 },
3578 { 0x09, 0xa20f },
3579 { 0x1f, 0x0000 },
3580
3581 /* Modify green table for giga & fnet */
3582 { 0x1f, 0x0005 },
3583 { 0x05, 0x8b55 },
3584 { 0x06, 0x0000 },
3585 { 0x05, 0x8b5e },
3586 { 0x06, 0x0000 },
3587 { 0x05, 0x8b67 },
3588 { 0x06, 0x0000 },
3589 { 0x05, 0x8b70 },
3590 { 0x06, 0x0000 },
3591 { 0x1f, 0x0000 },
3592 { 0x1f, 0x0007 },
3593 { 0x1e, 0x0078 },
3594 { 0x17, 0x0000 },
3595 { 0x19, 0x00fb },
3596 { 0x1f, 0x0000 },
3597
3598 /* Modify green table for 10M */
3599 { 0x1f, 0x0005 },
3600 { 0x05, 0x8b79 },
3601 { 0x06, 0xaa00 },
3602 { 0x1f, 0x0000 },
3603
3604 /* Disable hiimpedance detection (RTCT) */
3605 { 0x1f, 0x0003 },
3606 { 0x01, 0x328a },
3607 { 0x1f, 0x0000 }
3608 };
3609
3610 rtl_apply_firmware(tp);
3611
3612 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3613
3614 rtl8168f_hw_phy_config(tp);
3615
3616 /* Improve 2-pair detection performance */
3617 rtl_writephy(tp, 0x1f, 0x0005);
3618 rtl_writephy(tp, 0x05, 0x8b85);
3619 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3620 rtl_writephy(tp, 0x1f, 0x0000);
3621 }
3622
3623 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3624 {
3625 rtl_apply_firmware(tp);
3626
3627 rtl8168f_hw_phy_config(tp);
3628 }
3629
3630 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3631 {
3632 static const struct phy_reg phy_reg_init[] = {
3633 /* Channel estimation fine tune */
3634 { 0x1f, 0x0003 },
3635 { 0x09, 0xa20f },
3636 { 0x1f, 0x0000 },
3637
3638 /* Modify green table for giga & fnet */
3639 { 0x1f, 0x0005 },
3640 { 0x05, 0x8b55 },
3641 { 0x06, 0x0000 },
3642 { 0x05, 0x8b5e },
3643 { 0x06, 0x0000 },
3644 { 0x05, 0x8b67 },
3645 { 0x06, 0x0000 },
3646 { 0x05, 0x8b70 },
3647 { 0x06, 0x0000 },
3648 { 0x1f, 0x0000 },
3649 { 0x1f, 0x0007 },
3650 { 0x1e, 0x0078 },
3651 { 0x17, 0x0000 },
3652 { 0x19, 0x00aa },
3653 { 0x1f, 0x0000 },
3654
3655 /* Modify green table for 10M */
3656 { 0x1f, 0x0005 },
3657 { 0x05, 0x8b79 },
3658 { 0x06, 0xaa00 },
3659 { 0x1f, 0x0000 },
3660
3661 /* Disable hiimpedance detection (RTCT) */
3662 { 0x1f, 0x0003 },
3663 { 0x01, 0x328a },
3664 { 0x1f, 0x0000 }
3665 };
3666
3667
3668 rtl_apply_firmware(tp);
3669
3670 rtl8168f_hw_phy_config(tp);
3671
3672 /* Improve 2-pair detection performance */
3673 rtl_writephy(tp, 0x1f, 0x0005);
3674 rtl_writephy(tp, 0x05, 0x8b85);
3675 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3676 rtl_writephy(tp, 0x1f, 0x0000);
3677
3678 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3679
3680 /* Modify green table for giga */
3681 rtl_writephy(tp, 0x1f, 0x0005);
3682 rtl_writephy(tp, 0x05, 0x8b54);
3683 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3684 rtl_writephy(tp, 0x05, 0x8b5d);
3685 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3686 rtl_writephy(tp, 0x05, 0x8a7c);
3687 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3688 rtl_writephy(tp, 0x05, 0x8a7f);
3689 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3690 rtl_writephy(tp, 0x05, 0x8a82);
3691 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3692 rtl_writephy(tp, 0x05, 0x8a85);
3693 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3694 rtl_writephy(tp, 0x05, 0x8a88);
3695 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3696 rtl_writephy(tp, 0x1f, 0x0000);
3697
3698 /* uc same-seed solution */
3699 rtl_writephy(tp, 0x1f, 0x0005);
3700 rtl_writephy(tp, 0x05, 0x8b85);
3701 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3702 rtl_writephy(tp, 0x1f, 0x0000);
3703
3704 /* eee setting */
3705 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3706 rtl_writephy(tp, 0x1f, 0x0005);
3707 rtl_writephy(tp, 0x05, 0x8b85);
3708 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3709 rtl_writephy(tp, 0x1f, 0x0004);
3710 rtl_writephy(tp, 0x1f, 0x0007);
3711 rtl_writephy(tp, 0x1e, 0x0020);
3712 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3713 rtl_writephy(tp, 0x1f, 0x0000);
3714 rtl_writephy(tp, 0x0d, 0x0007);
3715 rtl_writephy(tp, 0x0e, 0x003c);
3716 rtl_writephy(tp, 0x0d, 0x4007);
3717 rtl_writephy(tp, 0x0e, 0x0000);
3718 rtl_writephy(tp, 0x0d, 0x0000);
3719
3720 /* Green feature */
3721 rtl_writephy(tp, 0x1f, 0x0003);
3722 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3723 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3724 rtl_writephy(tp, 0x1f, 0x0000);
3725 }
3726
3727 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3728 {
3729 rtl_apply_firmware(tp);
3730
3731 rtl_writephy(tp, 0x1f, 0x0a46);
3732 if (rtl_readphy(tp, 0x10) & 0x0100) {
3733 rtl_writephy(tp, 0x1f, 0x0bcc);
3734 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3735 } else {
3736 rtl_writephy(tp, 0x1f, 0x0bcc);
3737 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3738 }
3739
3740 rtl_writephy(tp, 0x1f, 0x0a46);
3741 if (rtl_readphy(tp, 0x13) & 0x0100) {
3742 rtl_writephy(tp, 0x1f, 0x0c41);
3743 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3744 } else {
3745 rtl_writephy(tp, 0x1f, 0x0c41);
3746 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3747 }
3748
3749 /* Enable PHY auto speed down */
3750 rtl_writephy(tp, 0x1f, 0x0a44);
3751 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3752
3753 rtl_writephy(tp, 0x1f, 0x0bcc);
3754 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3755 rtl_writephy(tp, 0x1f, 0x0a44);
3756 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3757 rtl_writephy(tp, 0x1f, 0x0a43);
3758 rtl_writephy(tp, 0x13, 0x8084);
3759 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3760 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3761
3762 /* EEE auto-fallback function */
3763 rtl_writephy(tp, 0x1f, 0x0a4b);
3764 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3765
3766 /* Enable UC LPF tune function */
3767 rtl_writephy(tp, 0x1f, 0x0a43);
3768 rtl_writephy(tp, 0x13, 0x8012);
3769 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3770
3771 rtl_writephy(tp, 0x1f, 0x0c42);
3772 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3773
3774 /* Improve SWR Efficiency */
3775 rtl_writephy(tp, 0x1f, 0x0bcd);
3776 rtl_writephy(tp, 0x14, 0x5065);
3777 rtl_writephy(tp, 0x14, 0xd065);
3778 rtl_writephy(tp, 0x1f, 0x0bc8);
3779 rtl_writephy(tp, 0x11, 0x5655);
3780 rtl_writephy(tp, 0x1f, 0x0bcd);
3781 rtl_writephy(tp, 0x14, 0x1065);
3782 rtl_writephy(tp, 0x14, 0x9065);
3783 rtl_writephy(tp, 0x14, 0x1065);
3784
3785 /* Check ALDPS bit, disable it if enabled */
3786 rtl_writephy(tp, 0x1f, 0x0a43);
3787 if (rtl_readphy(tp, 0x10) & 0x0004)
3788 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3789
3790 rtl_writephy(tp, 0x1f, 0x0000);
3791 }
3792
3793 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3794 {
3795 rtl_apply_firmware(tp);
3796 }
3797
3798 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3799 {
3800 u16 dout_tapbin;
3801 u32 data;
3802
3803 rtl_apply_firmware(tp);
3804
3805 /* CHN EST parameters adjust - giga master */
3806 rtl_writephy(tp, 0x1f, 0x0a43);
3807 rtl_writephy(tp, 0x13, 0x809b);
3808 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3809 rtl_writephy(tp, 0x13, 0x80a2);
3810 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3811 rtl_writephy(tp, 0x13, 0x80a4);
3812 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3813 rtl_writephy(tp, 0x13, 0x809c);
3814 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3815 rtl_writephy(tp, 0x1f, 0x0000);
3816
3817 /* CHN EST parameters adjust - giga slave */
3818 rtl_writephy(tp, 0x1f, 0x0a43);
3819 rtl_writephy(tp, 0x13, 0x80ad);
3820 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3821 rtl_writephy(tp, 0x13, 0x80b4);
3822 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3823 rtl_writephy(tp, 0x13, 0x80ac);
3824 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3825 rtl_writephy(tp, 0x1f, 0x0000);
3826
3827 /* CHN EST parameters adjust - fnet */
3828 rtl_writephy(tp, 0x1f, 0x0a43);
3829 rtl_writephy(tp, 0x13, 0x808e);
3830 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3831 rtl_writephy(tp, 0x13, 0x8090);
3832 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3833 rtl_writephy(tp, 0x13, 0x8092);
3834 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3835 rtl_writephy(tp, 0x1f, 0x0000);
3836
3837 /* enable R-tune & PGA-retune function */
3838 dout_tapbin = 0;
3839 rtl_writephy(tp, 0x1f, 0x0a46);
3840 data = rtl_readphy(tp, 0x13);
3841 data &= 3;
3842 data <<= 2;
3843 dout_tapbin |= data;
3844 data = rtl_readphy(tp, 0x12);
3845 data &= 0xc000;
3846 data >>= 14;
3847 dout_tapbin |= data;
3848 dout_tapbin = ~(dout_tapbin^0x08);
3849 dout_tapbin <<= 12;
3850 dout_tapbin &= 0xf000;
3851 rtl_writephy(tp, 0x1f, 0x0a43);
3852 rtl_writephy(tp, 0x13, 0x827a);
3853 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3854 rtl_writephy(tp, 0x13, 0x827b);
3855 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3856 rtl_writephy(tp, 0x13, 0x827c);
3857 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3858 rtl_writephy(tp, 0x13, 0x827d);
3859 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3860
3861 rtl_writephy(tp, 0x1f, 0x0a43);
3862 rtl_writephy(tp, 0x13, 0x0811);
3863 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3864 rtl_writephy(tp, 0x1f, 0x0a42);
3865 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3866 rtl_writephy(tp, 0x1f, 0x0000);
3867
3868 /* enable GPHY 10M */
3869 rtl_writephy(tp, 0x1f, 0x0a44);
3870 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3871 rtl_writephy(tp, 0x1f, 0x0000);
3872
3873 /* SAR ADC performance */
3874 rtl_writephy(tp, 0x1f, 0x0bca);
3875 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3876 rtl_writephy(tp, 0x1f, 0x0000);
3877
3878 rtl_writephy(tp, 0x1f, 0x0a43);
3879 rtl_writephy(tp, 0x13, 0x803f);
3880 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3881 rtl_writephy(tp, 0x13, 0x8047);
3882 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3883 rtl_writephy(tp, 0x13, 0x804f);
3884 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3885 rtl_writephy(tp, 0x13, 0x8057);
3886 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3887 rtl_writephy(tp, 0x13, 0x805f);
3888 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3889 rtl_writephy(tp, 0x13, 0x8067);
3890 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3891 rtl_writephy(tp, 0x13, 0x806f);
3892 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3893 rtl_writephy(tp, 0x1f, 0x0000);
3894
3895 /* disable phy pfm mode */
3896 rtl_writephy(tp, 0x1f, 0x0a44);
3897 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3898 rtl_writephy(tp, 0x1f, 0x0000);
3899
3900 /* Check ALDPS bit, disable it if enabled */
3901 rtl_writephy(tp, 0x1f, 0x0a43);
3902 if (rtl_readphy(tp, 0x10) & 0x0004)
3903 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3904
3905 rtl_writephy(tp, 0x1f, 0x0000);
3906 }
3907
3908 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3909 {
3910 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3911 u16 rlen;
3912 u32 data;
3913
3914 rtl_apply_firmware(tp);
3915
3916 /* CHIN EST parameter update */
3917 rtl_writephy(tp, 0x1f, 0x0a43);
3918 rtl_writephy(tp, 0x13, 0x808a);
3919 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3920 rtl_writephy(tp, 0x1f, 0x0000);
3921
3922 /* enable R-tune & PGA-retune function */
3923 rtl_writephy(tp, 0x1f, 0x0a43);
3924 rtl_writephy(tp, 0x13, 0x0811);
3925 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3926 rtl_writephy(tp, 0x1f, 0x0a42);
3927 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3928 rtl_writephy(tp, 0x1f, 0x0000);
3929
3930 /* enable GPHY 10M */
3931 rtl_writephy(tp, 0x1f, 0x0a44);
3932 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3933 rtl_writephy(tp, 0x1f, 0x0000);
3934
3935 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3936 data = r8168_mac_ocp_read(tp, 0xdd02);
3937 ioffset_p3 = ((data & 0x80)>>7);
3938 ioffset_p3 <<= 3;
3939
3940 data = r8168_mac_ocp_read(tp, 0xdd00);
3941 ioffset_p3 |= ((data & (0xe000))>>13);
3942 ioffset_p2 = ((data & (0x1e00))>>9);
3943 ioffset_p1 = ((data & (0x01e0))>>5);
3944 ioffset_p0 = ((data & 0x0010)>>4);
3945 ioffset_p0 <<= 3;
3946 ioffset_p0 |= (data & (0x07));
3947 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3948
3949 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3950 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3951 rtl_writephy(tp, 0x1f, 0x0bcf);
3952 rtl_writephy(tp, 0x16, data);
3953 rtl_writephy(tp, 0x1f, 0x0000);
3954 }
3955
3956 /* Modify rlen (TX LPF corner frequency) level */
3957 rtl_writephy(tp, 0x1f, 0x0bcd);
3958 data = rtl_readphy(tp, 0x16);
3959 data &= 0x000f;
3960 rlen = 0;
3961 if (data > 3)
3962 rlen = data - 3;
3963 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3964 rtl_writephy(tp, 0x17, data);
3965 rtl_writephy(tp, 0x1f, 0x0bcd);
3966 rtl_writephy(tp, 0x1f, 0x0000);
3967
3968 /* disable phy pfm mode */
3969 rtl_writephy(tp, 0x1f, 0x0a44);
3970 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3971 rtl_writephy(tp, 0x1f, 0x0000);
3972
3973 /* Check ALDPS bit, disable it if enabled */
3974 rtl_writephy(tp, 0x1f, 0x0a43);
3975 if (rtl_readphy(tp, 0x10) & 0x0004)
3976 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3977
3978 rtl_writephy(tp, 0x1f, 0x0000);
3979 }
3980
3981 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3982 {
3983 /* Enable PHY auto speed down */
3984 rtl_writephy(tp, 0x1f, 0x0a44);
3985 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3986 rtl_writephy(tp, 0x1f, 0x0000);
3987
3988 /* patch 10M & ALDPS */
3989 rtl_writephy(tp, 0x1f, 0x0bcc);
3990 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3991 rtl_writephy(tp, 0x1f, 0x0a44);
3992 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3993 rtl_writephy(tp, 0x1f, 0x0a43);
3994 rtl_writephy(tp, 0x13, 0x8084);
3995 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3996 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3997 rtl_writephy(tp, 0x1f, 0x0000);
3998
3999 /* Enable EEE auto-fallback function */
4000 rtl_writephy(tp, 0x1f, 0x0a4b);
4001 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
4002 rtl_writephy(tp, 0x1f, 0x0000);
4003
4004 /* Enable UC LPF tune function */
4005 rtl_writephy(tp, 0x1f, 0x0a43);
4006 rtl_writephy(tp, 0x13, 0x8012);
4007 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4008 rtl_writephy(tp, 0x1f, 0x0000);
4009
4010 /* set rg_sel_sdm_rate */
4011 rtl_writephy(tp, 0x1f, 0x0c42);
4012 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4013 rtl_writephy(tp, 0x1f, 0x0000);
4014
4015 /* Check ALDPS bit, disable it if enabled */
4016 rtl_writephy(tp, 0x1f, 0x0a43);
4017 if (rtl_readphy(tp, 0x10) & 0x0004)
4018 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4019
4020 rtl_writephy(tp, 0x1f, 0x0000);
4021 }
4022
4023 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
4024 {
4025 /* patch 10M & ALDPS */
4026 rtl_writephy(tp, 0x1f, 0x0bcc);
4027 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4028 rtl_writephy(tp, 0x1f, 0x0a44);
4029 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4030 rtl_writephy(tp, 0x1f, 0x0a43);
4031 rtl_writephy(tp, 0x13, 0x8084);
4032 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4033 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4034 rtl_writephy(tp, 0x1f, 0x0000);
4035
4036 /* Enable UC LPF tune function */
4037 rtl_writephy(tp, 0x1f, 0x0a43);
4038 rtl_writephy(tp, 0x13, 0x8012);
4039 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4040 rtl_writephy(tp, 0x1f, 0x0000);
4041
4042 /* Set rg_sel_sdm_rate */
4043 rtl_writephy(tp, 0x1f, 0x0c42);
4044 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4045 rtl_writephy(tp, 0x1f, 0x0000);
4046
4047 /* Channel estimation parameters */
4048 rtl_writephy(tp, 0x1f, 0x0a43);
4049 rtl_writephy(tp, 0x13, 0x80f3);
4050 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
4051 rtl_writephy(tp, 0x13, 0x80f0);
4052 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
4053 rtl_writephy(tp, 0x13, 0x80ef);
4054 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
4055 rtl_writephy(tp, 0x13, 0x80f6);
4056 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
4057 rtl_writephy(tp, 0x13, 0x80ec);
4058 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
4059 rtl_writephy(tp, 0x13, 0x80ed);
4060 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4061 rtl_writephy(tp, 0x13, 0x80f2);
4062 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
4063 rtl_writephy(tp, 0x13, 0x80f4);
4064 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
4065 rtl_writephy(tp, 0x1f, 0x0a43);
4066 rtl_writephy(tp, 0x13, 0x8110);
4067 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
4068 rtl_writephy(tp, 0x13, 0x810f);
4069 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
4070 rtl_writephy(tp, 0x13, 0x8111);
4071 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
4072 rtl_writephy(tp, 0x13, 0x8113);
4073 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4074 rtl_writephy(tp, 0x13, 0x8115);
4075 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4076 rtl_writephy(tp, 0x13, 0x810e);
4077 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4078 rtl_writephy(tp, 0x13, 0x810c);
4079 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4080 rtl_writephy(tp, 0x13, 0x810b);
4081 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4082 rtl_writephy(tp, 0x1f, 0x0a43);
4083 rtl_writephy(tp, 0x13, 0x80d1);
4084 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4085 rtl_writephy(tp, 0x13, 0x80cd);
4086 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4087 rtl_writephy(tp, 0x13, 0x80d3);
4088 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4089 rtl_writephy(tp, 0x13, 0x80d5);
4090 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4091 rtl_writephy(tp, 0x13, 0x80d7);
4092 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4093
4094 /* Force PWM-mode */
4095 rtl_writephy(tp, 0x1f, 0x0bcd);
4096 rtl_writephy(tp, 0x14, 0x5065);
4097 rtl_writephy(tp, 0x14, 0xd065);
4098 rtl_writephy(tp, 0x1f, 0x0bc8);
4099 rtl_writephy(tp, 0x12, 0x00ed);
4100 rtl_writephy(tp, 0x1f, 0x0bcd);
4101 rtl_writephy(tp, 0x14, 0x1065);
4102 rtl_writephy(tp, 0x14, 0x9065);
4103 rtl_writephy(tp, 0x14, 0x1065);
4104 rtl_writephy(tp, 0x1f, 0x0000);
4105
4106 /* Check ALDPS bit, disable it if enabled */
4107 rtl_writephy(tp, 0x1f, 0x0a43);
4108 if (rtl_readphy(tp, 0x10) & 0x0004)
4109 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4110
4111 rtl_writephy(tp, 0x1f, 0x0000);
4112 }
4113
4114 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
4115 {
4116 static const struct phy_reg phy_reg_init[] = {
4117 { 0x1f, 0x0003 },
4118 { 0x08, 0x441d },
4119 { 0x01, 0x9100 },
4120 { 0x1f, 0x0000 }
4121 };
4122
4123 rtl_writephy(tp, 0x1f, 0x0000);
4124 rtl_patchphy(tp, 0x11, 1 << 12);
4125 rtl_patchphy(tp, 0x19, 1 << 13);
4126 rtl_patchphy(tp, 0x10, 1 << 15);
4127
4128 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4129 }
4130
4131 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4132 {
4133 static const struct phy_reg phy_reg_init[] = {
4134 { 0x1f, 0x0005 },
4135 { 0x1a, 0x0000 },
4136 { 0x1f, 0x0000 },
4137
4138 { 0x1f, 0x0004 },
4139 { 0x1c, 0x0000 },
4140 { 0x1f, 0x0000 },
4141
4142 { 0x1f, 0x0001 },
4143 { 0x15, 0x7701 },
4144 { 0x1f, 0x0000 }
4145 };
4146
4147 /* Disable ALDPS before ram code */
4148 rtl_writephy(tp, 0x1f, 0x0000);
4149 rtl_writephy(tp, 0x18, 0x0310);
4150 msleep(100);
4151
4152 rtl_apply_firmware(tp);
4153
4154 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4155 }
4156
4157 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4158 {
4159 /* Disable ALDPS before setting firmware */
4160 rtl_writephy(tp, 0x1f, 0x0000);
4161 rtl_writephy(tp, 0x18, 0x0310);
4162 msleep(20);
4163
4164 rtl_apply_firmware(tp);
4165
4166 /* EEE setting */
4167 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4168 rtl_writephy(tp, 0x1f, 0x0004);
4169 rtl_writephy(tp, 0x10, 0x401f);
4170 rtl_writephy(tp, 0x19, 0x7030);
4171 rtl_writephy(tp, 0x1f, 0x0000);
4172 }
4173
4174 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4175 {
4176 static const struct phy_reg phy_reg_init[] = {
4177 { 0x1f, 0x0004 },
4178 { 0x10, 0xc07f },
4179 { 0x19, 0x7030 },
4180 { 0x1f, 0x0000 }
4181 };
4182
4183 /* Disable ALDPS before ram code */
4184 rtl_writephy(tp, 0x1f, 0x0000);
4185 rtl_writephy(tp, 0x18, 0x0310);
4186 msleep(100);
4187
4188 rtl_apply_firmware(tp);
4189
4190 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4191 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4192
4193 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4194 }
4195
4196 static void rtl_hw_phy_config(struct net_device *dev)
4197 {
4198 struct rtl8169_private *tp = netdev_priv(dev);
4199
4200 rtl8169_print_mac_version(tp);
4201
4202 switch (tp->mac_version) {
4203 case RTL_GIGA_MAC_VER_01:
4204 break;
4205 case RTL_GIGA_MAC_VER_02:
4206 case RTL_GIGA_MAC_VER_03:
4207 rtl8169s_hw_phy_config(tp);
4208 break;
4209 case RTL_GIGA_MAC_VER_04:
4210 rtl8169sb_hw_phy_config(tp);
4211 break;
4212 case RTL_GIGA_MAC_VER_05:
4213 rtl8169scd_hw_phy_config(tp);
4214 break;
4215 case RTL_GIGA_MAC_VER_06:
4216 rtl8169sce_hw_phy_config(tp);
4217 break;
4218 case RTL_GIGA_MAC_VER_07:
4219 case RTL_GIGA_MAC_VER_08:
4220 case RTL_GIGA_MAC_VER_09:
4221 rtl8102e_hw_phy_config(tp);
4222 break;
4223 case RTL_GIGA_MAC_VER_11:
4224 rtl8168bb_hw_phy_config(tp);
4225 break;
4226 case RTL_GIGA_MAC_VER_12:
4227 rtl8168bef_hw_phy_config(tp);
4228 break;
4229 case RTL_GIGA_MAC_VER_17:
4230 rtl8168bef_hw_phy_config(tp);
4231 break;
4232 case RTL_GIGA_MAC_VER_18:
4233 rtl8168cp_1_hw_phy_config(tp);
4234 break;
4235 case RTL_GIGA_MAC_VER_19:
4236 rtl8168c_1_hw_phy_config(tp);
4237 break;
4238 case RTL_GIGA_MAC_VER_20:
4239 rtl8168c_2_hw_phy_config(tp);
4240 break;
4241 case RTL_GIGA_MAC_VER_21:
4242 rtl8168c_3_hw_phy_config(tp);
4243 break;
4244 case RTL_GIGA_MAC_VER_22:
4245 rtl8168c_4_hw_phy_config(tp);
4246 break;
4247 case RTL_GIGA_MAC_VER_23:
4248 case RTL_GIGA_MAC_VER_24:
4249 rtl8168cp_2_hw_phy_config(tp);
4250 break;
4251 case RTL_GIGA_MAC_VER_25:
4252 rtl8168d_1_hw_phy_config(tp);
4253 break;
4254 case RTL_GIGA_MAC_VER_26:
4255 rtl8168d_2_hw_phy_config(tp);
4256 break;
4257 case RTL_GIGA_MAC_VER_27:
4258 rtl8168d_3_hw_phy_config(tp);
4259 break;
4260 case RTL_GIGA_MAC_VER_28:
4261 rtl8168d_4_hw_phy_config(tp);
4262 break;
4263 case RTL_GIGA_MAC_VER_29:
4264 case RTL_GIGA_MAC_VER_30:
4265 rtl8105e_hw_phy_config(tp);
4266 break;
4267 case RTL_GIGA_MAC_VER_31:
4268 /* None. */
4269 break;
4270 case RTL_GIGA_MAC_VER_32:
4271 case RTL_GIGA_MAC_VER_33:
4272 rtl8168e_1_hw_phy_config(tp);
4273 break;
4274 case RTL_GIGA_MAC_VER_34:
4275 rtl8168e_2_hw_phy_config(tp);
4276 break;
4277 case RTL_GIGA_MAC_VER_35:
4278 rtl8168f_1_hw_phy_config(tp);
4279 break;
4280 case RTL_GIGA_MAC_VER_36:
4281 rtl8168f_2_hw_phy_config(tp);
4282 break;
4283
4284 case RTL_GIGA_MAC_VER_37:
4285 rtl8402_hw_phy_config(tp);
4286 break;
4287
4288 case RTL_GIGA_MAC_VER_38:
4289 rtl8411_hw_phy_config(tp);
4290 break;
4291
4292 case RTL_GIGA_MAC_VER_39:
4293 rtl8106e_hw_phy_config(tp);
4294 break;
4295
4296 case RTL_GIGA_MAC_VER_40:
4297 rtl8168g_1_hw_phy_config(tp);
4298 break;
4299 case RTL_GIGA_MAC_VER_42:
4300 case RTL_GIGA_MAC_VER_43:
4301 case RTL_GIGA_MAC_VER_44:
4302 rtl8168g_2_hw_phy_config(tp);
4303 break;
4304 case RTL_GIGA_MAC_VER_45:
4305 case RTL_GIGA_MAC_VER_47:
4306 rtl8168h_1_hw_phy_config(tp);
4307 break;
4308 case RTL_GIGA_MAC_VER_46:
4309 case RTL_GIGA_MAC_VER_48:
4310 rtl8168h_2_hw_phy_config(tp);
4311 break;
4312
4313 case RTL_GIGA_MAC_VER_49:
4314 rtl8168ep_1_hw_phy_config(tp);
4315 break;
4316 case RTL_GIGA_MAC_VER_50:
4317 case RTL_GIGA_MAC_VER_51:
4318 rtl8168ep_2_hw_phy_config(tp);
4319 break;
4320
4321 case RTL_GIGA_MAC_VER_41:
4322 default:
4323 break;
4324 }
4325 }
4326
4327 static void rtl_phy_work(struct rtl8169_private *tp)
4328 {
4329 struct timer_list *timer = &tp->timer;
4330 void __iomem *ioaddr = tp->mmio_addr;
4331 unsigned long timeout = RTL8169_PHY_TIMEOUT;
4332
4333 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
4334
4335 if (tp->phy_reset_pending(tp)) {
4336 /*
4337 * A busy loop could burn quite a few cycles on nowadays CPU.
4338 * Let's delay the execution of the timer for a few ticks.
4339 */
4340 timeout = HZ/10;
4341 goto out_mod_timer;
4342 }
4343
4344 if (tp->link_ok(ioaddr))
4345 return;
4346
4347 netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
4348
4349 tp->phy_reset_enable(tp);
4350
4351 out_mod_timer:
4352 mod_timer(timer, jiffies + timeout);
4353 }
4354
4355 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4356 {
4357 if (!test_and_set_bit(flag, tp->wk.flags))
4358 schedule_work(&tp->wk.work);
4359 }
4360
4361 static void rtl8169_phy_timer(unsigned long __opaque)
4362 {
4363 struct net_device *dev = (struct net_device *)__opaque;
4364 struct rtl8169_private *tp = netdev_priv(dev);
4365
4366 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
4367 }
4368
4369 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
4370 void __iomem *ioaddr)
4371 {
4372 iounmap(ioaddr);
4373 pci_release_regions(pdev);
4374 pci_clear_mwi(pdev);
4375 pci_disable_device(pdev);
4376 free_netdev(dev);
4377 }
4378
4379 DECLARE_RTL_COND(rtl_phy_reset_cond)
4380 {
4381 return tp->phy_reset_pending(tp);
4382 }
4383
4384 static void rtl8169_phy_reset(struct net_device *dev,
4385 struct rtl8169_private *tp)
4386 {
4387 tp->phy_reset_enable(tp);
4388 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
4389 }
4390
4391 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4392 {
4393 void __iomem *ioaddr = tp->mmio_addr;
4394
4395 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4396 (RTL_R8(PHYstatus) & TBI_Enable);
4397 }
4398
4399 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4400 {
4401 void __iomem *ioaddr = tp->mmio_addr;
4402
4403 rtl_hw_phy_config(dev);
4404
4405 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4406 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4407 RTL_W8(0x82, 0x01);
4408 }
4409
4410 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4411
4412 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4413 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4414
4415 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4416 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4417 RTL_W8(0x82, 0x01);
4418 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4419 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4420 }
4421
4422 rtl8169_phy_reset(dev, tp);
4423
4424 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4425 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4426 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4427 (tp->mii.supports_gmii ?
4428 ADVERTISED_1000baseT_Half |
4429 ADVERTISED_1000baseT_Full : 0));
4430
4431 if (rtl_tbi_enabled(tp))
4432 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4433 }
4434
4435 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4436 {
4437 void __iomem *ioaddr = tp->mmio_addr;
4438
4439 rtl_lock_work(tp);
4440
4441 RTL_W8(Cfg9346, Cfg9346_Unlock);
4442
4443 RTL_W32(MAC4, addr[4] | addr[5] << 8);
4444 RTL_R32(MAC4);
4445
4446 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4447 RTL_R32(MAC0);
4448
4449 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4450 rtl_rar_exgmac_set(tp, addr);
4451
4452 RTL_W8(Cfg9346, Cfg9346_Lock);
4453
4454 rtl_unlock_work(tp);
4455 }
4456
4457 static int rtl_set_mac_address(struct net_device *dev, void *p)
4458 {
4459 struct rtl8169_private *tp = netdev_priv(dev);
4460 struct sockaddr *addr = p;
4461
4462 if (!is_valid_ether_addr(addr->sa_data))
4463 return -EADDRNOTAVAIL;
4464
4465 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4466
4467 rtl_rar_set(tp, dev->dev_addr);
4468
4469 return 0;
4470 }
4471
4472 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4473 {
4474 struct rtl8169_private *tp = netdev_priv(dev);
4475 struct mii_ioctl_data *data = if_mii(ifr);
4476
4477 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4478 }
4479
4480 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4481 struct mii_ioctl_data *data, int cmd)
4482 {
4483 switch (cmd) {
4484 case SIOCGMIIPHY:
4485 data->phy_id = 32; /* Internal PHY */
4486 return 0;
4487
4488 case SIOCGMIIREG:
4489 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
4490 return 0;
4491
4492 case SIOCSMIIREG:
4493 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
4494 return 0;
4495 }
4496 return -EOPNOTSUPP;
4497 }
4498
4499 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4500 {
4501 return -EOPNOTSUPP;
4502 }
4503
4504 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
4505 {
4506 if (tp->features & RTL_FEATURE_MSI) {
4507 pci_disable_msi(pdev);
4508 tp->features &= ~RTL_FEATURE_MSI;
4509 }
4510 }
4511
4512 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4513 {
4514 struct mdio_ops *ops = &tp->mdio_ops;
4515
4516 switch (tp->mac_version) {
4517 case RTL_GIGA_MAC_VER_27:
4518 ops->write = r8168dp_1_mdio_write;
4519 ops->read = r8168dp_1_mdio_read;
4520 break;
4521 case RTL_GIGA_MAC_VER_28:
4522 case RTL_GIGA_MAC_VER_31:
4523 ops->write = r8168dp_2_mdio_write;
4524 ops->read = r8168dp_2_mdio_read;
4525 break;
4526 case RTL_GIGA_MAC_VER_40:
4527 case RTL_GIGA_MAC_VER_41:
4528 case RTL_GIGA_MAC_VER_42:
4529 case RTL_GIGA_MAC_VER_43:
4530 case RTL_GIGA_MAC_VER_44:
4531 case RTL_GIGA_MAC_VER_45:
4532 case RTL_GIGA_MAC_VER_46:
4533 case RTL_GIGA_MAC_VER_47:
4534 case RTL_GIGA_MAC_VER_48:
4535 case RTL_GIGA_MAC_VER_49:
4536 case RTL_GIGA_MAC_VER_50:
4537 case RTL_GIGA_MAC_VER_51:
4538 ops->write = r8168g_mdio_write;
4539 ops->read = r8168g_mdio_read;
4540 break;
4541 default:
4542 ops->write = r8169_mdio_write;
4543 ops->read = r8169_mdio_read;
4544 break;
4545 }
4546 }
4547
4548 static void rtl_speed_down(struct rtl8169_private *tp)
4549 {
4550 u32 adv;
4551 int lpa;
4552
4553 rtl_writephy(tp, 0x1f, 0x0000);
4554 lpa = rtl_readphy(tp, MII_LPA);
4555
4556 if (lpa & (LPA_10HALF | LPA_10FULL))
4557 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4558 else if (lpa & (LPA_100HALF | LPA_100FULL))
4559 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4560 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4561 else
4562 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4563 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4564 (tp->mii.supports_gmii ?
4565 ADVERTISED_1000baseT_Half |
4566 ADVERTISED_1000baseT_Full : 0);
4567
4568 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4569 adv);
4570 }
4571
4572 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4573 {
4574 void __iomem *ioaddr = tp->mmio_addr;
4575
4576 switch (tp->mac_version) {
4577 case RTL_GIGA_MAC_VER_25:
4578 case RTL_GIGA_MAC_VER_26:
4579 case RTL_GIGA_MAC_VER_29:
4580 case RTL_GIGA_MAC_VER_30:
4581 case RTL_GIGA_MAC_VER_32:
4582 case RTL_GIGA_MAC_VER_33:
4583 case RTL_GIGA_MAC_VER_34:
4584 case RTL_GIGA_MAC_VER_37:
4585 case RTL_GIGA_MAC_VER_38:
4586 case RTL_GIGA_MAC_VER_39:
4587 case RTL_GIGA_MAC_VER_40:
4588 case RTL_GIGA_MAC_VER_41:
4589 case RTL_GIGA_MAC_VER_42:
4590 case RTL_GIGA_MAC_VER_43:
4591 case RTL_GIGA_MAC_VER_44:
4592 case RTL_GIGA_MAC_VER_45:
4593 case RTL_GIGA_MAC_VER_46:
4594 case RTL_GIGA_MAC_VER_47:
4595 case RTL_GIGA_MAC_VER_48:
4596 case RTL_GIGA_MAC_VER_49:
4597 case RTL_GIGA_MAC_VER_50:
4598 case RTL_GIGA_MAC_VER_51:
4599 RTL_W32(RxConfig, RTL_R32(RxConfig) |
4600 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4601 break;
4602 default:
4603 break;
4604 }
4605 }
4606
4607 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4608 {
4609 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4610 return false;
4611
4612 rtl_speed_down(tp);
4613 rtl_wol_suspend_quirk(tp);
4614
4615 return true;
4616 }
4617
4618 static void r810x_phy_power_down(struct rtl8169_private *tp)
4619 {
4620 rtl_writephy(tp, 0x1f, 0x0000);
4621 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4622 }
4623
4624 static void r810x_phy_power_up(struct rtl8169_private *tp)
4625 {
4626 rtl_writephy(tp, 0x1f, 0x0000);
4627 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4628 }
4629
4630 static void r810x_pll_power_down(struct rtl8169_private *tp)
4631 {
4632 void __iomem *ioaddr = tp->mmio_addr;
4633
4634 if (rtl_wol_pll_power_down(tp))
4635 return;
4636
4637 r810x_phy_power_down(tp);
4638
4639 switch (tp->mac_version) {
4640 case RTL_GIGA_MAC_VER_07:
4641 case RTL_GIGA_MAC_VER_08:
4642 case RTL_GIGA_MAC_VER_09:
4643 case RTL_GIGA_MAC_VER_10:
4644 case RTL_GIGA_MAC_VER_13:
4645 case RTL_GIGA_MAC_VER_16:
4646 break;
4647 default:
4648 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4649 break;
4650 }
4651 }
4652
4653 static void r810x_pll_power_up(struct rtl8169_private *tp)
4654 {
4655 void __iomem *ioaddr = tp->mmio_addr;
4656
4657 r810x_phy_power_up(tp);
4658
4659 switch (tp->mac_version) {
4660 case RTL_GIGA_MAC_VER_07:
4661 case RTL_GIGA_MAC_VER_08:
4662 case RTL_GIGA_MAC_VER_09:
4663 case RTL_GIGA_MAC_VER_10:
4664 case RTL_GIGA_MAC_VER_13:
4665 case RTL_GIGA_MAC_VER_16:
4666 break;
4667 case RTL_GIGA_MAC_VER_47:
4668 case RTL_GIGA_MAC_VER_48:
4669 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4670 break;
4671 default:
4672 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4673 break;
4674 }
4675 }
4676
4677 static void r8168_phy_power_up(struct rtl8169_private *tp)
4678 {
4679 rtl_writephy(tp, 0x1f, 0x0000);
4680 switch (tp->mac_version) {
4681 case RTL_GIGA_MAC_VER_11:
4682 case RTL_GIGA_MAC_VER_12:
4683 case RTL_GIGA_MAC_VER_17:
4684 case RTL_GIGA_MAC_VER_18:
4685 case RTL_GIGA_MAC_VER_19:
4686 case RTL_GIGA_MAC_VER_20:
4687 case RTL_GIGA_MAC_VER_21:
4688 case RTL_GIGA_MAC_VER_22:
4689 case RTL_GIGA_MAC_VER_23:
4690 case RTL_GIGA_MAC_VER_24:
4691 case RTL_GIGA_MAC_VER_25:
4692 case RTL_GIGA_MAC_VER_26:
4693 case RTL_GIGA_MAC_VER_27:
4694 case RTL_GIGA_MAC_VER_28:
4695 case RTL_GIGA_MAC_VER_31:
4696 rtl_writephy(tp, 0x0e, 0x0000);
4697 break;
4698 default:
4699 break;
4700 }
4701 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4702 }
4703
4704 static void r8168_phy_power_down(struct rtl8169_private *tp)
4705 {
4706 rtl_writephy(tp, 0x1f, 0x0000);
4707 switch (tp->mac_version) {
4708 case RTL_GIGA_MAC_VER_32:
4709 case RTL_GIGA_MAC_VER_33:
4710 case RTL_GIGA_MAC_VER_40:
4711 case RTL_GIGA_MAC_VER_41:
4712 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4713 break;
4714
4715 case RTL_GIGA_MAC_VER_11:
4716 case RTL_GIGA_MAC_VER_12:
4717 case RTL_GIGA_MAC_VER_17:
4718 case RTL_GIGA_MAC_VER_18:
4719 case RTL_GIGA_MAC_VER_19:
4720 case RTL_GIGA_MAC_VER_20:
4721 case RTL_GIGA_MAC_VER_21:
4722 case RTL_GIGA_MAC_VER_22:
4723 case RTL_GIGA_MAC_VER_23:
4724 case RTL_GIGA_MAC_VER_24:
4725 case RTL_GIGA_MAC_VER_25:
4726 case RTL_GIGA_MAC_VER_26:
4727 case RTL_GIGA_MAC_VER_27:
4728 case RTL_GIGA_MAC_VER_28:
4729 case RTL_GIGA_MAC_VER_31:
4730 rtl_writephy(tp, 0x0e, 0x0200);
4731 default:
4732 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4733 break;
4734 }
4735 }
4736
4737 static void r8168_pll_power_down(struct rtl8169_private *tp)
4738 {
4739 void __iomem *ioaddr = tp->mmio_addr;
4740
4741 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4742 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4743 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
4744 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
4745 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
4746 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
4747 r8168_check_dash(tp)) {
4748 return;
4749 }
4750
4751 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4752 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
4753 (RTL_R16(CPlusCmd) & ASF)) {
4754 return;
4755 }
4756
4757 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4758 tp->mac_version == RTL_GIGA_MAC_VER_33)
4759 rtl_ephy_write(tp, 0x19, 0xff64);
4760
4761 if (rtl_wol_pll_power_down(tp))
4762 return;
4763
4764 r8168_phy_power_down(tp);
4765
4766 switch (tp->mac_version) {
4767 case RTL_GIGA_MAC_VER_25:
4768 case RTL_GIGA_MAC_VER_26:
4769 case RTL_GIGA_MAC_VER_27:
4770 case RTL_GIGA_MAC_VER_28:
4771 case RTL_GIGA_MAC_VER_31:
4772 case RTL_GIGA_MAC_VER_32:
4773 case RTL_GIGA_MAC_VER_33:
4774 case RTL_GIGA_MAC_VER_44:
4775 case RTL_GIGA_MAC_VER_45:
4776 case RTL_GIGA_MAC_VER_46:
4777 case RTL_GIGA_MAC_VER_50:
4778 case RTL_GIGA_MAC_VER_51:
4779 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4780 break;
4781 case RTL_GIGA_MAC_VER_40:
4782 case RTL_GIGA_MAC_VER_41:
4783 case RTL_GIGA_MAC_VER_49:
4784 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4785 0xfc000000, ERIAR_EXGMAC);
4786 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4787 break;
4788 }
4789 }
4790
4791 static void r8168_pll_power_up(struct rtl8169_private *tp)
4792 {
4793 void __iomem *ioaddr = tp->mmio_addr;
4794
4795 switch (tp->mac_version) {
4796 case RTL_GIGA_MAC_VER_25:
4797 case RTL_GIGA_MAC_VER_26:
4798 case RTL_GIGA_MAC_VER_27:
4799 case RTL_GIGA_MAC_VER_28:
4800 case RTL_GIGA_MAC_VER_31:
4801 case RTL_GIGA_MAC_VER_32:
4802 case RTL_GIGA_MAC_VER_33:
4803 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4804 break;
4805 case RTL_GIGA_MAC_VER_44:
4806 case RTL_GIGA_MAC_VER_45:
4807 case RTL_GIGA_MAC_VER_46:
4808 case RTL_GIGA_MAC_VER_50:
4809 case RTL_GIGA_MAC_VER_51:
4810 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4811 break;
4812 case RTL_GIGA_MAC_VER_40:
4813 case RTL_GIGA_MAC_VER_41:
4814 case RTL_GIGA_MAC_VER_49:
4815 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4816 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4817 0x00000000, ERIAR_EXGMAC);
4818 break;
4819 }
4820
4821 r8168_phy_power_up(tp);
4822 }
4823
4824 static void rtl_generic_op(struct rtl8169_private *tp,
4825 void (*op)(struct rtl8169_private *))
4826 {
4827 if (op)
4828 op(tp);
4829 }
4830
4831 static void rtl_pll_power_down(struct rtl8169_private *tp)
4832 {
4833 rtl_generic_op(tp, tp->pll_power_ops.down);
4834 }
4835
4836 static void rtl_pll_power_up(struct rtl8169_private *tp)
4837 {
4838 rtl_generic_op(tp, tp->pll_power_ops.up);
4839 }
4840
4841 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4842 {
4843 struct pll_power_ops *ops = &tp->pll_power_ops;
4844
4845 switch (tp->mac_version) {
4846 case RTL_GIGA_MAC_VER_07:
4847 case RTL_GIGA_MAC_VER_08:
4848 case RTL_GIGA_MAC_VER_09:
4849 case RTL_GIGA_MAC_VER_10:
4850 case RTL_GIGA_MAC_VER_16:
4851 case RTL_GIGA_MAC_VER_29:
4852 case RTL_GIGA_MAC_VER_30:
4853 case RTL_GIGA_MAC_VER_37:
4854 case RTL_GIGA_MAC_VER_39:
4855 case RTL_GIGA_MAC_VER_43:
4856 case RTL_GIGA_MAC_VER_47:
4857 case RTL_GIGA_MAC_VER_48:
4858 ops->down = r810x_pll_power_down;
4859 ops->up = r810x_pll_power_up;
4860 break;
4861
4862 case RTL_GIGA_MAC_VER_11:
4863 case RTL_GIGA_MAC_VER_12:
4864 case RTL_GIGA_MAC_VER_17:
4865 case RTL_GIGA_MAC_VER_18:
4866 case RTL_GIGA_MAC_VER_19:
4867 case RTL_GIGA_MAC_VER_20:
4868 case RTL_GIGA_MAC_VER_21:
4869 case RTL_GIGA_MAC_VER_22:
4870 case RTL_GIGA_MAC_VER_23:
4871 case RTL_GIGA_MAC_VER_24:
4872 case RTL_GIGA_MAC_VER_25:
4873 case RTL_GIGA_MAC_VER_26:
4874 case RTL_GIGA_MAC_VER_27:
4875 case RTL_GIGA_MAC_VER_28:
4876 case RTL_GIGA_MAC_VER_31:
4877 case RTL_GIGA_MAC_VER_32:
4878 case RTL_GIGA_MAC_VER_33:
4879 case RTL_GIGA_MAC_VER_34:
4880 case RTL_GIGA_MAC_VER_35:
4881 case RTL_GIGA_MAC_VER_36:
4882 case RTL_GIGA_MAC_VER_38:
4883 case RTL_GIGA_MAC_VER_40:
4884 case RTL_GIGA_MAC_VER_41:
4885 case RTL_GIGA_MAC_VER_42:
4886 case RTL_GIGA_MAC_VER_44:
4887 case RTL_GIGA_MAC_VER_45:
4888 case RTL_GIGA_MAC_VER_46:
4889 case RTL_GIGA_MAC_VER_49:
4890 case RTL_GIGA_MAC_VER_50:
4891 case RTL_GIGA_MAC_VER_51:
4892 ops->down = r8168_pll_power_down;
4893 ops->up = r8168_pll_power_up;
4894 break;
4895
4896 default:
4897 ops->down = NULL;
4898 ops->up = NULL;
4899 break;
4900 }
4901 }
4902
4903 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4904 {
4905 void __iomem *ioaddr = tp->mmio_addr;
4906
4907 switch (tp->mac_version) {
4908 case RTL_GIGA_MAC_VER_01:
4909 case RTL_GIGA_MAC_VER_02:
4910 case RTL_GIGA_MAC_VER_03:
4911 case RTL_GIGA_MAC_VER_04:
4912 case RTL_GIGA_MAC_VER_05:
4913 case RTL_GIGA_MAC_VER_06:
4914 case RTL_GIGA_MAC_VER_10:
4915 case RTL_GIGA_MAC_VER_11:
4916 case RTL_GIGA_MAC_VER_12:
4917 case RTL_GIGA_MAC_VER_13:
4918 case RTL_GIGA_MAC_VER_14:
4919 case RTL_GIGA_MAC_VER_15:
4920 case RTL_GIGA_MAC_VER_16:
4921 case RTL_GIGA_MAC_VER_17:
4922 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4923 break;
4924 case RTL_GIGA_MAC_VER_18:
4925 case RTL_GIGA_MAC_VER_19:
4926 case RTL_GIGA_MAC_VER_20:
4927 case RTL_GIGA_MAC_VER_21:
4928 case RTL_GIGA_MAC_VER_22:
4929 case RTL_GIGA_MAC_VER_23:
4930 case RTL_GIGA_MAC_VER_24:
4931 case RTL_GIGA_MAC_VER_34:
4932 case RTL_GIGA_MAC_VER_35:
4933 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4934 break;
4935 case RTL_GIGA_MAC_VER_40:
4936 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4937 break;
4938 case RTL_GIGA_MAC_VER_41:
4939 case RTL_GIGA_MAC_VER_42:
4940 case RTL_GIGA_MAC_VER_43:
4941 case RTL_GIGA_MAC_VER_44:
4942 case RTL_GIGA_MAC_VER_45:
4943 case RTL_GIGA_MAC_VER_46:
4944 case RTL_GIGA_MAC_VER_47:
4945 case RTL_GIGA_MAC_VER_48:
4946 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
4947 break;
4948 case RTL_GIGA_MAC_VER_49:
4949 case RTL_GIGA_MAC_VER_50:
4950 case RTL_GIGA_MAC_VER_51:
4951 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4952 break;
4953 default:
4954 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4955 break;
4956 }
4957 }
4958
4959 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4960 {
4961 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4962 }
4963
4964 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4965 {
4966 void __iomem *ioaddr = tp->mmio_addr;
4967
4968 RTL_W8(Cfg9346, Cfg9346_Unlock);
4969 rtl_generic_op(tp, tp->jumbo_ops.enable);
4970 RTL_W8(Cfg9346, Cfg9346_Lock);
4971 }
4972
4973 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4974 {
4975 void __iomem *ioaddr = tp->mmio_addr;
4976
4977 RTL_W8(Cfg9346, Cfg9346_Unlock);
4978 rtl_generic_op(tp, tp->jumbo_ops.disable);
4979 RTL_W8(Cfg9346, Cfg9346_Lock);
4980 }
4981
4982 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4983 {
4984 void __iomem *ioaddr = tp->mmio_addr;
4985
4986 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4987 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4988 rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
4989 }
4990
4991 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4992 {
4993 void __iomem *ioaddr = tp->mmio_addr;
4994
4995 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4996 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4997 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4998 }
4999
5000 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
5001 {
5002 void __iomem *ioaddr = tp->mmio_addr;
5003
5004 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5005 }
5006
5007 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
5008 {
5009 void __iomem *ioaddr = tp->mmio_addr;
5010
5011 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5012 }
5013
5014 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
5015 {
5016 void __iomem *ioaddr = tp->mmio_addr;
5017
5018 RTL_W8(MaxTxPacketSize, 0x3f);
5019 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5020 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
5021 rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
5022 }
5023
5024 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
5025 {
5026 void __iomem *ioaddr = tp->mmio_addr;
5027
5028 RTL_W8(MaxTxPacketSize, 0x0c);
5029 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5030 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
5031 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5032 }
5033
5034 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
5035 {
5036 rtl_tx_performance_tweak(tp->pci_dev,
5037 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
5038 }
5039
5040 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
5041 {
5042 rtl_tx_performance_tweak(tp->pci_dev,
5043 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
5044 }
5045
5046 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
5047 {
5048 void __iomem *ioaddr = tp->mmio_addr;
5049
5050 r8168b_0_hw_jumbo_enable(tp);
5051
5052 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
5053 }
5054
5055 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
5056 {
5057 void __iomem *ioaddr = tp->mmio_addr;
5058
5059 r8168b_0_hw_jumbo_disable(tp);
5060
5061 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5062 }
5063
5064 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
5065 {
5066 struct jumbo_ops *ops = &tp->jumbo_ops;
5067
5068 switch (tp->mac_version) {
5069 case RTL_GIGA_MAC_VER_11:
5070 ops->disable = r8168b_0_hw_jumbo_disable;
5071 ops->enable = r8168b_0_hw_jumbo_enable;
5072 break;
5073 case RTL_GIGA_MAC_VER_12:
5074 case RTL_GIGA_MAC_VER_17:
5075 ops->disable = r8168b_1_hw_jumbo_disable;
5076 ops->enable = r8168b_1_hw_jumbo_enable;
5077 break;
5078 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
5079 case RTL_GIGA_MAC_VER_19:
5080 case RTL_GIGA_MAC_VER_20:
5081 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
5082 case RTL_GIGA_MAC_VER_22:
5083 case RTL_GIGA_MAC_VER_23:
5084 case RTL_GIGA_MAC_VER_24:
5085 case RTL_GIGA_MAC_VER_25:
5086 case RTL_GIGA_MAC_VER_26:
5087 ops->disable = r8168c_hw_jumbo_disable;
5088 ops->enable = r8168c_hw_jumbo_enable;
5089 break;
5090 case RTL_GIGA_MAC_VER_27:
5091 case RTL_GIGA_MAC_VER_28:
5092 ops->disable = r8168dp_hw_jumbo_disable;
5093 ops->enable = r8168dp_hw_jumbo_enable;
5094 break;
5095 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
5096 case RTL_GIGA_MAC_VER_32:
5097 case RTL_GIGA_MAC_VER_33:
5098 case RTL_GIGA_MAC_VER_34:
5099 ops->disable = r8168e_hw_jumbo_disable;
5100 ops->enable = r8168e_hw_jumbo_enable;
5101 break;
5102
5103 /*
5104 * No action needed for jumbo frames with 8169.
5105 * No jumbo for 810x at all.
5106 */
5107 case RTL_GIGA_MAC_VER_40:
5108 case RTL_GIGA_MAC_VER_41:
5109 case RTL_GIGA_MAC_VER_42:
5110 case RTL_GIGA_MAC_VER_43:
5111 case RTL_GIGA_MAC_VER_44:
5112 case RTL_GIGA_MAC_VER_45:
5113 case RTL_GIGA_MAC_VER_46:
5114 case RTL_GIGA_MAC_VER_47:
5115 case RTL_GIGA_MAC_VER_48:
5116 case RTL_GIGA_MAC_VER_49:
5117 case RTL_GIGA_MAC_VER_50:
5118 case RTL_GIGA_MAC_VER_51:
5119 default:
5120 ops->disable = NULL;
5121 ops->enable = NULL;
5122 break;
5123 }
5124 }
5125
5126 DECLARE_RTL_COND(rtl_chipcmd_cond)
5127 {
5128 void __iomem *ioaddr = tp->mmio_addr;
5129
5130 return RTL_R8(ChipCmd) & CmdReset;
5131 }
5132
5133 static void rtl_hw_reset(struct rtl8169_private *tp)
5134 {
5135 void __iomem *ioaddr = tp->mmio_addr;
5136
5137 RTL_W8(ChipCmd, CmdReset);
5138
5139 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
5140 }
5141
5142 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
5143 {
5144 struct rtl_fw *rtl_fw;
5145 const char *name;
5146 int rc = -ENOMEM;
5147
5148 name = rtl_lookup_firmware_name(tp);
5149 if (!name)
5150 goto out_no_firmware;
5151
5152 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
5153 if (!rtl_fw)
5154 goto err_warn;
5155
5156 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
5157 if (rc < 0)
5158 goto err_free;
5159
5160 rc = rtl_check_firmware(tp, rtl_fw);
5161 if (rc < 0)
5162 goto err_release_firmware;
5163
5164 tp->rtl_fw = rtl_fw;
5165 out:
5166 return;
5167
5168 err_release_firmware:
5169 release_firmware(rtl_fw->fw);
5170 err_free:
5171 kfree(rtl_fw);
5172 err_warn:
5173 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
5174 name, rc);
5175 out_no_firmware:
5176 tp->rtl_fw = NULL;
5177 goto out;
5178 }
5179
5180 static void rtl_request_firmware(struct rtl8169_private *tp)
5181 {
5182 if (IS_ERR(tp->rtl_fw))
5183 rtl_request_uncached_firmware(tp);
5184 }
5185
5186 static void rtl_rx_close(struct rtl8169_private *tp)
5187 {
5188 void __iomem *ioaddr = tp->mmio_addr;
5189
5190 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
5191 }
5192
5193 DECLARE_RTL_COND(rtl_npq_cond)
5194 {
5195 void __iomem *ioaddr = tp->mmio_addr;
5196
5197 return RTL_R8(TxPoll) & NPQ;
5198 }
5199
5200 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
5201 {
5202 void __iomem *ioaddr = tp->mmio_addr;
5203
5204 return RTL_R32(TxConfig) & TXCFG_EMPTY;
5205 }
5206
5207 static void rtl8169_hw_reset(struct rtl8169_private *tp)
5208 {
5209 void __iomem *ioaddr = tp->mmio_addr;
5210
5211 /* Disable interrupts */
5212 rtl8169_irq_mask_and_ack(tp);
5213
5214 rtl_rx_close(tp);
5215
5216 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5217 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5218 tp->mac_version == RTL_GIGA_MAC_VER_31) {
5219 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
5220 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
5221 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
5222 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
5223 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
5224 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
5225 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
5226 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
5227 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
5228 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
5229 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
5230 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
5231 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
5232 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
5233 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
5234 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5235 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5236 tp->mac_version == RTL_GIGA_MAC_VER_51) {
5237 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5238 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
5239 } else {
5240 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5241 udelay(100);
5242 }
5243
5244 rtl_hw_reset(tp);
5245 }
5246
5247 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
5248 {
5249 void __iomem *ioaddr = tp->mmio_addr;
5250
5251 /* Set DMA burst size and Interframe Gap Time */
5252 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5253 (InterFrameGap << TxInterFrameGapShift));
5254 }
5255
5256 static void rtl_hw_start(struct net_device *dev)
5257 {
5258 struct rtl8169_private *tp = netdev_priv(dev);
5259
5260 tp->hw_start(dev);
5261
5262 rtl_irq_enable_all(tp);
5263 }
5264
5265 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
5266 void __iomem *ioaddr)
5267 {
5268 /*
5269 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5270 * register to be written before TxDescAddrLow to work.
5271 * Switching from MMIO to I/O access fixes the issue as well.
5272 */
5273 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
5274 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
5275 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
5276 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
5277 }
5278
5279 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
5280 {
5281 u16 cmd;
5282
5283 cmd = RTL_R16(CPlusCmd);
5284 RTL_W16(CPlusCmd, cmd);
5285 return cmd;
5286 }
5287
5288 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
5289 {
5290 /* Low hurts. Let's disable the filtering. */
5291 RTL_W16(RxMaxSize, rx_buf_sz + 1);
5292 }
5293
5294 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
5295 {
5296 static const struct rtl_cfg2_info {
5297 u32 mac_version;
5298 u32 clk;
5299 u32 val;
5300 } cfg2_info [] = {
5301 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5302 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5303 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5304 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
5305 };
5306 const struct rtl_cfg2_info *p = cfg2_info;
5307 unsigned int i;
5308 u32 clk;
5309
5310 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
5311 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
5312 if ((p->mac_version == mac_version) && (p->clk == clk)) {
5313 RTL_W32(0x7c, p->val);
5314 break;
5315 }
5316 }
5317 }
5318
5319 static void rtl_set_rx_mode(struct net_device *dev)
5320 {
5321 struct rtl8169_private *tp = netdev_priv(dev);
5322 void __iomem *ioaddr = tp->mmio_addr;
5323 u32 mc_filter[2]; /* Multicast hash filter */
5324 int rx_mode;
5325 u32 tmp = 0;
5326
5327 if (dev->flags & IFF_PROMISC) {
5328 /* Unconditionally log net taps. */
5329 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5330 rx_mode =
5331 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5332 AcceptAllPhys;
5333 mc_filter[1] = mc_filter[0] = 0xffffffff;
5334 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5335 (dev->flags & IFF_ALLMULTI)) {
5336 /* Too many to filter perfectly -- accept all multicasts. */
5337 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5338 mc_filter[1] = mc_filter[0] = 0xffffffff;
5339 } else {
5340 struct netdev_hw_addr *ha;
5341
5342 rx_mode = AcceptBroadcast | AcceptMyPhys;
5343 mc_filter[1] = mc_filter[0] = 0;
5344 netdev_for_each_mc_addr(ha, dev) {
5345 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5346 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5347 rx_mode |= AcceptMulticast;
5348 }
5349 }
5350
5351 if (dev->features & NETIF_F_RXALL)
5352 rx_mode |= (AcceptErr | AcceptRunt);
5353
5354 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5355
5356 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5357 u32 data = mc_filter[0];
5358
5359 mc_filter[0] = swab32(mc_filter[1]);
5360 mc_filter[1] = swab32(data);
5361 }
5362
5363 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5364 mc_filter[1] = mc_filter[0] = 0xffffffff;
5365
5366 RTL_W32(MAR0 + 4, mc_filter[1]);
5367 RTL_W32(MAR0 + 0, mc_filter[0]);
5368
5369 RTL_W32(RxConfig, tmp);
5370 }
5371
5372 static void rtl_hw_start_8169(struct net_device *dev)
5373 {
5374 struct rtl8169_private *tp = netdev_priv(dev);
5375 void __iomem *ioaddr = tp->mmio_addr;
5376 struct pci_dev *pdev = tp->pci_dev;
5377
5378 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
5379 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
5380 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
5381 }
5382
5383 RTL_W8(Cfg9346, Cfg9346_Unlock);
5384 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5385 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5386 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5387 tp->mac_version == RTL_GIGA_MAC_VER_04)
5388 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5389
5390 rtl_init_rxcfg(tp);
5391
5392 RTL_W8(EarlyTxThres, NoEarlyTx);
5393
5394 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5395
5396 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5397 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5398 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5399 tp->mac_version == RTL_GIGA_MAC_VER_04)
5400 rtl_set_rx_tx_config_registers(tp);
5401
5402 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
5403
5404 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5405 tp->mac_version == RTL_GIGA_MAC_VER_03) {
5406 dprintk("Set MAC Reg C+CR Offset 0xe0. "
5407 "Bit-3 and bit-14 MUST be 1\n");
5408 tp->cp_cmd |= (1 << 14);
5409 }
5410
5411 RTL_W16(CPlusCmd, tp->cp_cmd);
5412
5413 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
5414
5415 /*
5416 * Undocumented corner. Supposedly:
5417 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5418 */
5419 RTL_W16(IntrMitigate, 0x0000);
5420
5421 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5422
5423 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5424 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5425 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5426 tp->mac_version != RTL_GIGA_MAC_VER_04) {
5427 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5428 rtl_set_rx_tx_config_registers(tp);
5429 }
5430
5431 RTL_W8(Cfg9346, Cfg9346_Lock);
5432
5433 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5434 RTL_R8(IntrMask);
5435
5436 RTL_W32(RxMissed, 0);
5437
5438 rtl_set_rx_mode(dev);
5439
5440 /* no early-rx interrupts */
5441 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5442 }
5443
5444 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5445 {
5446 if (tp->csi_ops.write)
5447 tp->csi_ops.write(tp, addr, value);
5448 }
5449
5450 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5451 {
5452 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
5453 }
5454
5455 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
5456 {
5457 u32 csi;
5458
5459 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5460 rtl_csi_write(tp, 0x070c, csi | bits);
5461 }
5462
5463 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5464 {
5465 rtl_csi_access_enable(tp, 0x17000000);
5466 }
5467
5468 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
5469 {
5470 rtl_csi_access_enable(tp, 0x27000000);
5471 }
5472
5473 DECLARE_RTL_COND(rtl_csiar_cond)
5474 {
5475 void __iomem *ioaddr = tp->mmio_addr;
5476
5477 return RTL_R32(CSIAR) & CSIAR_FLAG;
5478 }
5479
5480 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
5481 {
5482 void __iomem *ioaddr = tp->mmio_addr;
5483
5484 RTL_W32(CSIDR, value);
5485 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5486 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5487
5488 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5489 }
5490
5491 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
5492 {
5493 void __iomem *ioaddr = tp->mmio_addr;
5494
5495 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
5496 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5497
5498 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5499 RTL_R32(CSIDR) : ~0;
5500 }
5501
5502 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
5503 {
5504 void __iomem *ioaddr = tp->mmio_addr;
5505
5506 RTL_W32(CSIDR, value);
5507 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5508 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5509 CSIAR_FUNC_NIC);
5510
5511 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5512 }
5513
5514 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
5515 {
5516 void __iomem *ioaddr = tp->mmio_addr;
5517
5518 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5519 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5520
5521 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5522 RTL_R32(CSIDR) : ~0;
5523 }
5524
5525 static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5526 {
5527 void __iomem *ioaddr = tp->mmio_addr;
5528
5529 RTL_W32(CSIDR, value);
5530 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5531 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5532 CSIAR_FUNC_NIC2);
5533
5534 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5535 }
5536
5537 static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5538 {
5539 void __iomem *ioaddr = tp->mmio_addr;
5540
5541 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5542 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5543
5544 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5545 RTL_R32(CSIDR) : ~0;
5546 }
5547
5548 static void rtl_init_csi_ops(struct rtl8169_private *tp)
5549 {
5550 struct csi_ops *ops = &tp->csi_ops;
5551
5552 switch (tp->mac_version) {
5553 case RTL_GIGA_MAC_VER_01:
5554 case RTL_GIGA_MAC_VER_02:
5555 case RTL_GIGA_MAC_VER_03:
5556 case RTL_GIGA_MAC_VER_04:
5557 case RTL_GIGA_MAC_VER_05:
5558 case RTL_GIGA_MAC_VER_06:
5559 case RTL_GIGA_MAC_VER_10:
5560 case RTL_GIGA_MAC_VER_11:
5561 case RTL_GIGA_MAC_VER_12:
5562 case RTL_GIGA_MAC_VER_13:
5563 case RTL_GIGA_MAC_VER_14:
5564 case RTL_GIGA_MAC_VER_15:
5565 case RTL_GIGA_MAC_VER_16:
5566 case RTL_GIGA_MAC_VER_17:
5567 ops->write = NULL;
5568 ops->read = NULL;
5569 break;
5570
5571 case RTL_GIGA_MAC_VER_37:
5572 case RTL_GIGA_MAC_VER_38:
5573 ops->write = r8402_csi_write;
5574 ops->read = r8402_csi_read;
5575 break;
5576
5577 case RTL_GIGA_MAC_VER_44:
5578 ops->write = r8411_csi_write;
5579 ops->read = r8411_csi_read;
5580 break;
5581
5582 default:
5583 ops->write = r8169_csi_write;
5584 ops->read = r8169_csi_read;
5585 break;
5586 }
5587 }
5588
5589 struct ephy_info {
5590 unsigned int offset;
5591 u16 mask;
5592 u16 bits;
5593 };
5594
5595 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5596 int len)
5597 {
5598 u16 w;
5599
5600 while (len-- > 0) {
5601 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5602 rtl_ephy_write(tp, e->offset, w);
5603 e++;
5604 }
5605 }
5606
5607 static void rtl_disable_clock_request(struct pci_dev *pdev)
5608 {
5609 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
5610 PCI_EXP_LNKCTL_CLKREQ_EN);
5611 }
5612
5613 static void rtl_enable_clock_request(struct pci_dev *pdev)
5614 {
5615 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
5616 PCI_EXP_LNKCTL_CLKREQ_EN);
5617 }
5618
5619 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5620 {
5621 void __iomem *ioaddr = tp->mmio_addr;
5622 u8 data;
5623
5624 data = RTL_R8(Config3);
5625
5626 if (enable)
5627 data |= Rdy_to_L23;
5628 else
5629 data &= ~Rdy_to_L23;
5630
5631 RTL_W8(Config3, data);
5632 }
5633
5634 #define R8168_CPCMD_QUIRK_MASK (\
5635 EnableBist | \
5636 Mac_dbgo_oe | \
5637 Force_half_dup | \
5638 Force_rxflow_en | \
5639 Force_txflow_en | \
5640 Cxpl_dbg_sel | \
5641 ASF | \
5642 PktCntrDisable | \
5643 Mac_dbgo_sel)
5644
5645 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
5646 {
5647 void __iomem *ioaddr = tp->mmio_addr;
5648 struct pci_dev *pdev = tp->pci_dev;
5649
5650 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5651
5652 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5653
5654 if (tp->dev->mtu <= ETH_DATA_LEN) {
5655 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
5656 PCI_EXP_DEVCTL_NOSNOOP_EN);
5657 }
5658 }
5659
5660 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
5661 {
5662 void __iomem *ioaddr = tp->mmio_addr;
5663
5664 rtl_hw_start_8168bb(tp);
5665
5666 RTL_W8(MaxTxPacketSize, TxPacketMax);
5667
5668 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5669 }
5670
5671 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
5672 {
5673 void __iomem *ioaddr = tp->mmio_addr;
5674 struct pci_dev *pdev = tp->pci_dev;
5675
5676 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
5677
5678 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5679
5680 if (tp->dev->mtu <= ETH_DATA_LEN)
5681 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5682
5683 rtl_disable_clock_request(pdev);
5684
5685 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5686 }
5687
5688 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
5689 {
5690 static const struct ephy_info e_info_8168cp[] = {
5691 { 0x01, 0, 0x0001 },
5692 { 0x02, 0x0800, 0x1000 },
5693 { 0x03, 0, 0x0042 },
5694 { 0x06, 0x0080, 0x0000 },
5695 { 0x07, 0, 0x2000 }
5696 };
5697
5698 rtl_csi_access_enable_2(tp);
5699
5700 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
5701
5702 __rtl_hw_start_8168cp(tp);
5703 }
5704
5705 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
5706 {
5707 void __iomem *ioaddr = tp->mmio_addr;
5708 struct pci_dev *pdev = tp->pci_dev;
5709
5710 rtl_csi_access_enable_2(tp);
5711
5712 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5713
5714 if (tp->dev->mtu <= ETH_DATA_LEN)
5715 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5716
5717 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5718 }
5719
5720 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
5721 {
5722 void __iomem *ioaddr = tp->mmio_addr;
5723 struct pci_dev *pdev = tp->pci_dev;
5724
5725 rtl_csi_access_enable_2(tp);
5726
5727 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5728
5729 /* Magic. */
5730 RTL_W8(DBG_REG, 0x20);
5731
5732 RTL_W8(MaxTxPacketSize, TxPacketMax);
5733
5734 if (tp->dev->mtu <= ETH_DATA_LEN)
5735 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5736
5737 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5738 }
5739
5740 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
5741 {
5742 void __iomem *ioaddr = tp->mmio_addr;
5743 static const struct ephy_info e_info_8168c_1[] = {
5744 { 0x02, 0x0800, 0x1000 },
5745 { 0x03, 0, 0x0002 },
5746 { 0x06, 0x0080, 0x0000 }
5747 };
5748
5749 rtl_csi_access_enable_2(tp);
5750
5751 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5752
5753 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
5754
5755 __rtl_hw_start_8168cp(tp);
5756 }
5757
5758 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
5759 {
5760 static const struct ephy_info e_info_8168c_2[] = {
5761 { 0x01, 0, 0x0001 },
5762 { 0x03, 0x0400, 0x0220 }
5763 };
5764
5765 rtl_csi_access_enable_2(tp);
5766
5767 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
5768
5769 __rtl_hw_start_8168cp(tp);
5770 }
5771
5772 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
5773 {
5774 rtl_hw_start_8168c_2(tp);
5775 }
5776
5777 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5778 {
5779 rtl_csi_access_enable_2(tp);
5780
5781 __rtl_hw_start_8168cp(tp);
5782 }
5783
5784 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5785 {
5786 void __iomem *ioaddr = tp->mmio_addr;
5787 struct pci_dev *pdev = tp->pci_dev;
5788
5789 rtl_csi_access_enable_2(tp);
5790
5791 rtl_disable_clock_request(pdev);
5792
5793 RTL_W8(MaxTxPacketSize, TxPacketMax);
5794
5795 if (tp->dev->mtu <= ETH_DATA_LEN)
5796 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5797
5798 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5799 }
5800
5801 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5802 {
5803 void __iomem *ioaddr = tp->mmio_addr;
5804 struct pci_dev *pdev = tp->pci_dev;
5805
5806 rtl_csi_access_enable_1(tp);
5807
5808 if (tp->dev->mtu <= ETH_DATA_LEN)
5809 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5810
5811 RTL_W8(MaxTxPacketSize, TxPacketMax);
5812
5813 rtl_disable_clock_request(pdev);
5814 }
5815
5816 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5817 {
5818 void __iomem *ioaddr = tp->mmio_addr;
5819 struct pci_dev *pdev = tp->pci_dev;
5820 static const struct ephy_info e_info_8168d_4[] = {
5821 { 0x0b, 0x0000, 0x0048 },
5822 { 0x19, 0x0020, 0x0050 },
5823 { 0x0c, 0x0100, 0x0020 }
5824 };
5825
5826 rtl_csi_access_enable_1(tp);
5827
5828 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5829
5830 RTL_W8(MaxTxPacketSize, TxPacketMax);
5831
5832 rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
5833
5834 rtl_enable_clock_request(pdev);
5835 }
5836
5837 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5838 {
5839 void __iomem *ioaddr = tp->mmio_addr;
5840 struct pci_dev *pdev = tp->pci_dev;
5841 static const struct ephy_info e_info_8168e_1[] = {
5842 { 0x00, 0x0200, 0x0100 },
5843 { 0x00, 0x0000, 0x0004 },
5844 { 0x06, 0x0002, 0x0001 },
5845 { 0x06, 0x0000, 0x0030 },
5846 { 0x07, 0x0000, 0x2000 },
5847 { 0x00, 0x0000, 0x0020 },
5848 { 0x03, 0x5800, 0x2000 },
5849 { 0x03, 0x0000, 0x0001 },
5850 { 0x01, 0x0800, 0x1000 },
5851 { 0x07, 0x0000, 0x4000 },
5852 { 0x1e, 0x0000, 0x2000 },
5853 { 0x19, 0xffff, 0xfe6c },
5854 { 0x0a, 0x0000, 0x0040 }
5855 };
5856
5857 rtl_csi_access_enable_2(tp);
5858
5859 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5860
5861 if (tp->dev->mtu <= ETH_DATA_LEN)
5862 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5863
5864 RTL_W8(MaxTxPacketSize, TxPacketMax);
5865
5866 rtl_disable_clock_request(pdev);
5867
5868 /* Reset tx FIFO pointer */
5869 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5870 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
5871
5872 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5873 }
5874
5875 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5876 {
5877 void __iomem *ioaddr = tp->mmio_addr;
5878 struct pci_dev *pdev = tp->pci_dev;
5879 static const struct ephy_info e_info_8168e_2[] = {
5880 { 0x09, 0x0000, 0x0080 },
5881 { 0x19, 0x0000, 0x0224 }
5882 };
5883
5884 rtl_csi_access_enable_1(tp);
5885
5886 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5887
5888 if (tp->dev->mtu <= ETH_DATA_LEN)
5889 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5890
5891 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5892 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5893 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5894 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5895 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5896 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5897 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5898 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5899
5900 RTL_W8(MaxTxPacketSize, EarlySize);
5901
5902 rtl_disable_clock_request(pdev);
5903
5904 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5905 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5906
5907 /* Adjust EEE LED frequency */
5908 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5909
5910 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5911 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5912 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5913 }
5914
5915 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5916 {
5917 void __iomem *ioaddr = tp->mmio_addr;
5918 struct pci_dev *pdev = tp->pci_dev;
5919
5920 rtl_csi_access_enable_2(tp);
5921
5922 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5923
5924 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5925 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5926 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5927 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5928 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5929 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5930 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5931 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5932 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5933 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5934
5935 RTL_W8(MaxTxPacketSize, EarlySize);
5936
5937 rtl_disable_clock_request(pdev);
5938
5939 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5940 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5941 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5942 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5943 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5944 }
5945
5946 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5947 {
5948 void __iomem *ioaddr = tp->mmio_addr;
5949 static const struct ephy_info e_info_8168f_1[] = {
5950 { 0x06, 0x00c0, 0x0020 },
5951 { 0x08, 0x0001, 0x0002 },
5952 { 0x09, 0x0000, 0x0080 },
5953 { 0x19, 0x0000, 0x0224 }
5954 };
5955
5956 rtl_hw_start_8168f(tp);
5957
5958 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5959
5960 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5961
5962 /* Adjust EEE LED frequency */
5963 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5964 }
5965
5966 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5967 {
5968 static const struct ephy_info e_info_8168f_1[] = {
5969 { 0x06, 0x00c0, 0x0020 },
5970 { 0x0f, 0xffff, 0x5200 },
5971 { 0x1e, 0x0000, 0x4000 },
5972 { 0x19, 0x0000, 0x0224 }
5973 };
5974
5975 rtl_hw_start_8168f(tp);
5976 rtl_pcie_state_l2l3_enable(tp, false);
5977
5978 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5979
5980 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5981 }
5982
5983 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5984 {
5985 void __iomem *ioaddr = tp->mmio_addr;
5986 struct pci_dev *pdev = tp->pci_dev;
5987
5988 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5989
5990 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5991 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5992 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5993 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5994
5995 rtl_csi_access_enable_1(tp);
5996
5997 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5998
5999 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6000 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6001 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
6002
6003 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6004 RTL_W8(MaxTxPacketSize, EarlySize);
6005
6006 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6007 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6008
6009 /* Adjust EEE LED frequency */
6010 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6011
6012 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6013 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6014
6015 rtl_pcie_state_l2l3_enable(tp, false);
6016 }
6017
6018 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
6019 {
6020 void __iomem *ioaddr = tp->mmio_addr;
6021 static const struct ephy_info e_info_8168g_1[] = {
6022 { 0x00, 0x0000, 0x0008 },
6023 { 0x0c, 0x37d0, 0x0820 },
6024 { 0x1e, 0x0000, 0x0001 },
6025 { 0x19, 0x8000, 0x0000 }
6026 };
6027
6028 rtl_hw_start_8168g(tp);
6029
6030 /* disable aspm and clock request before access ephy */
6031 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6032 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6033 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
6034 }
6035
6036 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
6037 {
6038 void __iomem *ioaddr = tp->mmio_addr;
6039 static const struct ephy_info e_info_8168g_2[] = {
6040 { 0x00, 0x0000, 0x0008 },
6041 { 0x0c, 0x3df0, 0x0200 },
6042 { 0x19, 0xffff, 0xfc00 },
6043 { 0x1e, 0xffff, 0x20eb }
6044 };
6045
6046 rtl_hw_start_8168g(tp);
6047
6048 /* disable aspm and clock request before access ephy */
6049 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6050 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6051 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
6052 }
6053
6054 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
6055 {
6056 void __iomem *ioaddr = tp->mmio_addr;
6057 static const struct ephy_info e_info_8411_2[] = {
6058 { 0x00, 0x0000, 0x0008 },
6059 { 0x0c, 0x3df0, 0x0200 },
6060 { 0x0f, 0xffff, 0x5200 },
6061 { 0x19, 0x0020, 0x0000 },
6062 { 0x1e, 0x0000, 0x2000 }
6063 };
6064
6065 rtl_hw_start_8168g(tp);
6066
6067 /* disable aspm and clock request before access ephy */
6068 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6069 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6070 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
6071 }
6072
6073 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
6074 {
6075 void __iomem *ioaddr = tp->mmio_addr;
6076 struct pci_dev *pdev = tp->pci_dev;
6077 int rg_saw_cnt;
6078 u32 data;
6079 static const struct ephy_info e_info_8168h_1[] = {
6080 { 0x1e, 0x0800, 0x0001 },
6081 { 0x1d, 0x0000, 0x0800 },
6082 { 0x05, 0xffff, 0x2089 },
6083 { 0x06, 0xffff, 0x5881 },
6084 { 0x04, 0xffff, 0x154a },
6085 { 0x01, 0xffff, 0x068b }
6086 };
6087
6088 /* disable aspm and clock request before access ephy */
6089 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6090 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6091 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
6092
6093 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6094
6095 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6096 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6097 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6098 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6099
6100 rtl_csi_access_enable_1(tp);
6101
6102 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6103
6104 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6105 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6106
6107 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6108
6109 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6110
6111 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6112
6113 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6114 RTL_W8(MaxTxPacketSize, EarlySize);
6115
6116 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6117 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6118
6119 /* Adjust EEE LED frequency */
6120 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6121
6122 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6123 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6124
6125 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6126
6127 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6128
6129 rtl_pcie_state_l2l3_enable(tp, false);
6130
6131 rtl_writephy(tp, 0x1f, 0x0c42);
6132 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6133 rtl_writephy(tp, 0x1f, 0x0000);
6134 if (rg_saw_cnt > 0) {
6135 u16 sw_cnt_1ms_ini;
6136
6137 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
6138 sw_cnt_1ms_ini &= 0x0fff;
6139 data = r8168_mac_ocp_read(tp, 0xd412);
6140 data &= ~0x0fff;
6141 data |= sw_cnt_1ms_ini;
6142 r8168_mac_ocp_write(tp, 0xd412, data);
6143 }
6144
6145 data = r8168_mac_ocp_read(tp, 0xe056);
6146 data &= ~0xf0;
6147 data |= 0x70;
6148 r8168_mac_ocp_write(tp, 0xe056, data);
6149
6150 data = r8168_mac_ocp_read(tp, 0xe052);
6151 data &= ~0x6000;
6152 data |= 0x8008;
6153 r8168_mac_ocp_write(tp, 0xe052, data);
6154
6155 data = r8168_mac_ocp_read(tp, 0xe0d6);
6156 data &= ~0x01ff;
6157 data |= 0x017f;
6158 r8168_mac_ocp_write(tp, 0xe0d6, data);
6159
6160 data = r8168_mac_ocp_read(tp, 0xd420);
6161 data &= ~0x0fff;
6162 data |= 0x047f;
6163 r8168_mac_ocp_write(tp, 0xd420, data);
6164
6165 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
6166 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
6167 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
6168 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
6169 }
6170
6171 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
6172 {
6173 void __iomem *ioaddr = tp->mmio_addr;
6174 struct pci_dev *pdev = tp->pci_dev;
6175
6176 rtl8168ep_stop_cmac(tp);
6177
6178 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6179
6180 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6181 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
6182 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
6183 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6184
6185 rtl_csi_access_enable_1(tp);
6186
6187 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6188
6189 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6190 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6191
6192 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
6193
6194 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6195
6196 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6197 RTL_W8(MaxTxPacketSize, EarlySize);
6198
6199 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6200 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6201
6202 /* Adjust EEE LED frequency */
6203 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6204
6205 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6206
6207 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6208
6209 rtl_pcie_state_l2l3_enable(tp, false);
6210 }
6211
6212 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
6213 {
6214 void __iomem *ioaddr = tp->mmio_addr;
6215 static const struct ephy_info e_info_8168ep_1[] = {
6216 { 0x00, 0xffff, 0x10ab },
6217 { 0x06, 0xffff, 0xf030 },
6218 { 0x08, 0xffff, 0x2006 },
6219 { 0x0d, 0xffff, 0x1666 },
6220 { 0x0c, 0x3ff0, 0x0000 }
6221 };
6222
6223 /* disable aspm and clock request before access ephy */
6224 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6225 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6226 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
6227
6228 rtl_hw_start_8168ep(tp);
6229 }
6230
6231 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
6232 {
6233 void __iomem *ioaddr = tp->mmio_addr;
6234 static const struct ephy_info e_info_8168ep_2[] = {
6235 { 0x00, 0xffff, 0x10a3 },
6236 { 0x19, 0xffff, 0xfc00 },
6237 { 0x1e, 0xffff, 0x20ea }
6238 };
6239
6240 /* disable aspm and clock request before access ephy */
6241 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6242 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6243 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
6244
6245 rtl_hw_start_8168ep(tp);
6246
6247 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6248 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6249 }
6250
6251 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
6252 {
6253 void __iomem *ioaddr = tp->mmio_addr;
6254 u32 data;
6255 static const struct ephy_info e_info_8168ep_3[] = {
6256 { 0x00, 0xffff, 0x10a3 },
6257 { 0x19, 0xffff, 0x7c00 },
6258 { 0x1e, 0xffff, 0x20eb },
6259 { 0x0d, 0xffff, 0x1666 }
6260 };
6261
6262 /* disable aspm and clock request before access ephy */
6263 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6264 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6265 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
6266
6267 rtl_hw_start_8168ep(tp);
6268
6269 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6270 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6271
6272 data = r8168_mac_ocp_read(tp, 0xd3e2);
6273 data &= 0xf000;
6274 data |= 0x0271;
6275 r8168_mac_ocp_write(tp, 0xd3e2, data);
6276
6277 data = r8168_mac_ocp_read(tp, 0xd3e4);
6278 data &= 0xff00;
6279 r8168_mac_ocp_write(tp, 0xd3e4, data);
6280
6281 data = r8168_mac_ocp_read(tp, 0xe860);
6282 data |= 0x0080;
6283 r8168_mac_ocp_write(tp, 0xe860, data);
6284 }
6285
6286 static void rtl_hw_start_8168(struct net_device *dev)
6287 {
6288 struct rtl8169_private *tp = netdev_priv(dev);
6289 void __iomem *ioaddr = tp->mmio_addr;
6290
6291 RTL_W8(Cfg9346, Cfg9346_Unlock);
6292
6293 RTL_W8(MaxTxPacketSize, TxPacketMax);
6294
6295 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6296
6297 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
6298
6299 RTL_W16(CPlusCmd, tp->cp_cmd);
6300
6301 RTL_W16(IntrMitigate, 0x5151);
6302
6303 /* Work around for RxFIFO overflow. */
6304 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
6305 tp->event_slow |= RxFIFOOver | PCSTimeout;
6306 tp->event_slow &= ~RxOverflow;
6307 }
6308
6309 rtl_set_rx_tx_desc_registers(tp, ioaddr);
6310
6311 rtl_set_rx_tx_config_registers(tp);
6312
6313 RTL_R8(IntrMask);
6314
6315 switch (tp->mac_version) {
6316 case RTL_GIGA_MAC_VER_11:
6317 rtl_hw_start_8168bb(tp);
6318 break;
6319
6320 case RTL_GIGA_MAC_VER_12:
6321 case RTL_GIGA_MAC_VER_17:
6322 rtl_hw_start_8168bef(tp);
6323 break;
6324
6325 case RTL_GIGA_MAC_VER_18:
6326 rtl_hw_start_8168cp_1(tp);
6327 break;
6328
6329 case RTL_GIGA_MAC_VER_19:
6330 rtl_hw_start_8168c_1(tp);
6331 break;
6332
6333 case RTL_GIGA_MAC_VER_20:
6334 rtl_hw_start_8168c_2(tp);
6335 break;
6336
6337 case RTL_GIGA_MAC_VER_21:
6338 rtl_hw_start_8168c_3(tp);
6339 break;
6340
6341 case RTL_GIGA_MAC_VER_22:
6342 rtl_hw_start_8168c_4(tp);
6343 break;
6344
6345 case RTL_GIGA_MAC_VER_23:
6346 rtl_hw_start_8168cp_2(tp);
6347 break;
6348
6349 case RTL_GIGA_MAC_VER_24:
6350 rtl_hw_start_8168cp_3(tp);
6351 break;
6352
6353 case RTL_GIGA_MAC_VER_25:
6354 case RTL_GIGA_MAC_VER_26:
6355 case RTL_GIGA_MAC_VER_27:
6356 rtl_hw_start_8168d(tp);
6357 break;
6358
6359 case RTL_GIGA_MAC_VER_28:
6360 rtl_hw_start_8168d_4(tp);
6361 break;
6362
6363 case RTL_GIGA_MAC_VER_31:
6364 rtl_hw_start_8168dp(tp);
6365 break;
6366
6367 case RTL_GIGA_MAC_VER_32:
6368 case RTL_GIGA_MAC_VER_33:
6369 rtl_hw_start_8168e_1(tp);
6370 break;
6371 case RTL_GIGA_MAC_VER_34:
6372 rtl_hw_start_8168e_2(tp);
6373 break;
6374
6375 case RTL_GIGA_MAC_VER_35:
6376 case RTL_GIGA_MAC_VER_36:
6377 rtl_hw_start_8168f_1(tp);
6378 break;
6379
6380 case RTL_GIGA_MAC_VER_38:
6381 rtl_hw_start_8411(tp);
6382 break;
6383
6384 case RTL_GIGA_MAC_VER_40:
6385 case RTL_GIGA_MAC_VER_41:
6386 rtl_hw_start_8168g_1(tp);
6387 break;
6388 case RTL_GIGA_MAC_VER_42:
6389 rtl_hw_start_8168g_2(tp);
6390 break;
6391
6392 case RTL_GIGA_MAC_VER_44:
6393 rtl_hw_start_8411_2(tp);
6394 break;
6395
6396 case RTL_GIGA_MAC_VER_45:
6397 case RTL_GIGA_MAC_VER_46:
6398 rtl_hw_start_8168h_1(tp);
6399 break;
6400
6401 case RTL_GIGA_MAC_VER_49:
6402 rtl_hw_start_8168ep_1(tp);
6403 break;
6404
6405 case RTL_GIGA_MAC_VER_50:
6406 rtl_hw_start_8168ep_2(tp);
6407 break;
6408
6409 case RTL_GIGA_MAC_VER_51:
6410 rtl_hw_start_8168ep_3(tp);
6411 break;
6412
6413 default:
6414 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
6415 dev->name, tp->mac_version);
6416 break;
6417 }
6418
6419 RTL_W8(Cfg9346, Cfg9346_Lock);
6420
6421 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6422
6423 rtl_set_rx_mode(dev);
6424
6425 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6426 }
6427
6428 #define R810X_CPCMD_QUIRK_MASK (\
6429 EnableBist | \
6430 Mac_dbgo_oe | \
6431 Force_half_dup | \
6432 Force_rxflow_en | \
6433 Force_txflow_en | \
6434 Cxpl_dbg_sel | \
6435 ASF | \
6436 PktCntrDisable | \
6437 Mac_dbgo_sel)
6438
6439 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
6440 {
6441 void __iomem *ioaddr = tp->mmio_addr;
6442 struct pci_dev *pdev = tp->pci_dev;
6443 static const struct ephy_info e_info_8102e_1[] = {
6444 { 0x01, 0, 0x6e65 },
6445 { 0x02, 0, 0x091f },
6446 { 0x03, 0, 0xc2f9 },
6447 { 0x06, 0, 0xafb5 },
6448 { 0x07, 0, 0x0e00 },
6449 { 0x19, 0, 0xec80 },
6450 { 0x01, 0, 0x2e65 },
6451 { 0x01, 0, 0x6e65 }
6452 };
6453 u8 cfg1;
6454
6455 rtl_csi_access_enable_2(tp);
6456
6457 RTL_W8(DBG_REG, FIX_NAK_1);
6458
6459 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6460
6461 RTL_W8(Config1,
6462 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
6463 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6464
6465 cfg1 = RTL_R8(Config1);
6466 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
6467 RTL_W8(Config1, cfg1 & ~LEDS0);
6468
6469 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
6470 }
6471
6472 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
6473 {
6474 void __iomem *ioaddr = tp->mmio_addr;
6475 struct pci_dev *pdev = tp->pci_dev;
6476
6477 rtl_csi_access_enable_2(tp);
6478
6479 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6480
6481 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
6482 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6483 }
6484
6485 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
6486 {
6487 rtl_hw_start_8102e_2(tp);
6488
6489 rtl_ephy_write(tp, 0x03, 0xc2f9);
6490 }
6491
6492 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
6493 {
6494 void __iomem *ioaddr = tp->mmio_addr;
6495 static const struct ephy_info e_info_8105e_1[] = {
6496 { 0x07, 0, 0x4000 },
6497 { 0x19, 0, 0x0200 },
6498 { 0x19, 0, 0x0020 },
6499 { 0x1e, 0, 0x2000 },
6500 { 0x03, 0, 0x0001 },
6501 { 0x19, 0, 0x0100 },
6502 { 0x19, 0, 0x0004 },
6503 { 0x0a, 0, 0x0020 }
6504 };
6505
6506 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6507 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6508
6509 /* Disable Early Tally Counter */
6510 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
6511
6512 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6513 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
6514
6515 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
6516
6517 rtl_pcie_state_l2l3_enable(tp, false);
6518 }
6519
6520 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
6521 {
6522 rtl_hw_start_8105e_1(tp);
6523 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
6524 }
6525
6526 static void rtl_hw_start_8402(struct rtl8169_private *tp)
6527 {
6528 void __iomem *ioaddr = tp->mmio_addr;
6529 static const struct ephy_info e_info_8402[] = {
6530 { 0x19, 0xffff, 0xff64 },
6531 { 0x1e, 0, 0x4000 }
6532 };
6533
6534 rtl_csi_access_enable_2(tp);
6535
6536 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6537 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6538
6539 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6540 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6541
6542 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
6543
6544 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
6545
6546 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6547 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
6548 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6549 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6550 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6551 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6552 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
6553
6554 rtl_pcie_state_l2l3_enable(tp, false);
6555 }
6556
6557 static void rtl_hw_start_8106(struct rtl8169_private *tp)
6558 {
6559 void __iomem *ioaddr = tp->mmio_addr;
6560
6561 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6562 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6563
6564 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
6565 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6566 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6567
6568 rtl_pcie_state_l2l3_enable(tp, false);
6569 }
6570
6571 static void rtl_hw_start_8101(struct net_device *dev)
6572 {
6573 struct rtl8169_private *tp = netdev_priv(dev);
6574 void __iomem *ioaddr = tp->mmio_addr;
6575 struct pci_dev *pdev = tp->pci_dev;
6576
6577 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6578 tp->event_slow &= ~RxFIFOOver;
6579
6580 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
6581 tp->mac_version == RTL_GIGA_MAC_VER_16)
6582 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6583 PCI_EXP_DEVCTL_NOSNOOP_EN);
6584
6585 RTL_W8(Cfg9346, Cfg9346_Unlock);
6586
6587 RTL_W8(MaxTxPacketSize, TxPacketMax);
6588
6589 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6590
6591 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6592 RTL_W16(CPlusCmd, tp->cp_cmd);
6593
6594 rtl_set_rx_tx_desc_registers(tp, ioaddr);
6595
6596 rtl_set_rx_tx_config_registers(tp);
6597
6598 switch (tp->mac_version) {
6599 case RTL_GIGA_MAC_VER_07:
6600 rtl_hw_start_8102e_1(tp);
6601 break;
6602
6603 case RTL_GIGA_MAC_VER_08:
6604 rtl_hw_start_8102e_3(tp);
6605 break;
6606
6607 case RTL_GIGA_MAC_VER_09:
6608 rtl_hw_start_8102e_2(tp);
6609 break;
6610
6611 case RTL_GIGA_MAC_VER_29:
6612 rtl_hw_start_8105e_1(tp);
6613 break;
6614 case RTL_GIGA_MAC_VER_30:
6615 rtl_hw_start_8105e_2(tp);
6616 break;
6617
6618 case RTL_GIGA_MAC_VER_37:
6619 rtl_hw_start_8402(tp);
6620 break;
6621
6622 case RTL_GIGA_MAC_VER_39:
6623 rtl_hw_start_8106(tp);
6624 break;
6625 case RTL_GIGA_MAC_VER_43:
6626 rtl_hw_start_8168g_2(tp);
6627 break;
6628 case RTL_GIGA_MAC_VER_47:
6629 case RTL_GIGA_MAC_VER_48:
6630 rtl_hw_start_8168h_1(tp);
6631 break;
6632 }
6633
6634 RTL_W8(Cfg9346, Cfg9346_Lock);
6635
6636 RTL_W16(IntrMitigate, 0x0000);
6637
6638 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6639
6640 rtl_set_rx_mode(dev);
6641
6642 RTL_R8(IntrMask);
6643
6644 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6645 }
6646
6647 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6648 {
6649 struct rtl8169_private *tp = netdev_priv(dev);
6650
6651 if (new_mtu < ETH_ZLEN ||
6652 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
6653 return -EINVAL;
6654
6655 if (new_mtu > ETH_DATA_LEN)
6656 rtl_hw_jumbo_enable(tp);
6657 else
6658 rtl_hw_jumbo_disable(tp);
6659
6660 dev->mtu = new_mtu;
6661 netdev_update_features(dev);
6662
6663 return 0;
6664 }
6665
6666 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6667 {
6668 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
6669 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6670 }
6671
6672 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6673 void **data_buff, struct RxDesc *desc)
6674 {
6675 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
6676 DMA_FROM_DEVICE);
6677
6678 kfree(*data_buff);
6679 *data_buff = NULL;
6680 rtl8169_make_unusable_by_asic(desc);
6681 }
6682
6683 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
6684 {
6685 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6686
6687 /* Force memory writes to complete before releasing descriptor */
6688 dma_wmb();
6689
6690 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
6691 }
6692
6693 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
6694 u32 rx_buf_sz)
6695 {
6696 desc->addr = cpu_to_le64(mapping);
6697 rtl8169_mark_to_asic(desc, rx_buf_sz);
6698 }
6699
6700 static inline void *rtl8169_align(void *data)
6701 {
6702 return (void *)ALIGN((long)data, 16);
6703 }
6704
6705 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6706 struct RxDesc *desc)
6707 {
6708 void *data;
6709 dma_addr_t mapping;
6710 struct device *d = &tp->pci_dev->dev;
6711 struct net_device *dev = tp->dev;
6712 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
6713
6714 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
6715 if (!data)
6716 return NULL;
6717
6718 if (rtl8169_align(data) != data) {
6719 kfree(data);
6720 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
6721 if (!data)
6722 return NULL;
6723 }
6724
6725 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
6726 DMA_FROM_DEVICE);
6727 if (unlikely(dma_mapping_error(d, mapping))) {
6728 if (net_ratelimit())
6729 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
6730 goto err_out;
6731 }
6732
6733 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6734 return data;
6735
6736 err_out:
6737 kfree(data);
6738 return NULL;
6739 }
6740
6741 static void rtl8169_rx_clear(struct rtl8169_private *tp)
6742 {
6743 unsigned int i;
6744
6745 for (i = 0; i < NUM_RX_DESC; i++) {
6746 if (tp->Rx_databuff[i]) {
6747 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
6748 tp->RxDescArray + i);
6749 }
6750 }
6751 }
6752
6753 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
6754 {
6755 desc->opts1 |= cpu_to_le32(RingEnd);
6756 }
6757
6758 static int rtl8169_rx_fill(struct rtl8169_private *tp)
6759 {
6760 unsigned int i;
6761
6762 for (i = 0; i < NUM_RX_DESC; i++) {
6763 void *data;
6764
6765 if (tp->Rx_databuff[i])
6766 continue;
6767
6768 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6769 if (!data) {
6770 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
6771 goto err_out;
6772 }
6773 tp->Rx_databuff[i] = data;
6774 }
6775
6776 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6777 return 0;
6778
6779 err_out:
6780 rtl8169_rx_clear(tp);
6781 return -ENOMEM;
6782 }
6783
6784 static int rtl8169_init_ring(struct net_device *dev)
6785 {
6786 struct rtl8169_private *tp = netdev_priv(dev);
6787
6788 rtl8169_init_ring_indexes(tp);
6789
6790 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6791 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
6792
6793 return rtl8169_rx_fill(tp);
6794 }
6795
6796 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
6797 struct TxDesc *desc)
6798 {
6799 unsigned int len = tx_skb->len;
6800
6801 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6802
6803 desc->opts1 = 0x00;
6804 desc->opts2 = 0x00;
6805 desc->addr = 0x00;
6806 tx_skb->len = 0;
6807 }
6808
6809 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6810 unsigned int n)
6811 {
6812 unsigned int i;
6813
6814 for (i = 0; i < n; i++) {
6815 unsigned int entry = (start + i) % NUM_TX_DESC;
6816 struct ring_info *tx_skb = tp->tx_skb + entry;
6817 unsigned int len = tx_skb->len;
6818
6819 if (len) {
6820 struct sk_buff *skb = tx_skb->skb;
6821
6822 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6823 tp->TxDescArray + entry);
6824 if (skb) {
6825 tp->dev->stats.tx_dropped++;
6826 dev_kfree_skb_any(skb);
6827 tx_skb->skb = NULL;
6828 }
6829 }
6830 }
6831 }
6832
6833 static void rtl8169_tx_clear(struct rtl8169_private *tp)
6834 {
6835 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
6836 tp->cur_tx = tp->dirty_tx = 0;
6837 }
6838
6839 static void rtl_reset_work(struct rtl8169_private *tp)
6840 {
6841 struct net_device *dev = tp->dev;
6842 int i;
6843
6844 napi_disable(&tp->napi);
6845 netif_stop_queue(dev);
6846 synchronize_sched();
6847
6848 rtl8169_hw_reset(tp);
6849
6850 for (i = 0; i < NUM_RX_DESC; i++)
6851 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
6852
6853 rtl8169_tx_clear(tp);
6854 rtl8169_init_ring_indexes(tp);
6855
6856 napi_enable(&tp->napi);
6857 rtl_hw_start(dev);
6858 netif_wake_queue(dev);
6859 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
6860 }
6861
6862 static void rtl8169_tx_timeout(struct net_device *dev)
6863 {
6864 struct rtl8169_private *tp = netdev_priv(dev);
6865
6866 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6867 }
6868
6869 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
6870 u32 *opts)
6871 {
6872 struct skb_shared_info *info = skb_shinfo(skb);
6873 unsigned int cur_frag, entry;
6874 struct TxDesc *uninitialized_var(txd);
6875 struct device *d = &tp->pci_dev->dev;
6876
6877 entry = tp->cur_tx;
6878 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
6879 const skb_frag_t *frag = info->frags + cur_frag;
6880 dma_addr_t mapping;
6881 u32 status, len;
6882 void *addr;
6883
6884 entry = (entry + 1) % NUM_TX_DESC;
6885
6886 txd = tp->TxDescArray + entry;
6887 len = skb_frag_size(frag);
6888 addr = skb_frag_address(frag);
6889 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
6890 if (unlikely(dma_mapping_error(d, mapping))) {
6891 if (net_ratelimit())
6892 netif_err(tp, drv, tp->dev,
6893 "Failed to map TX fragments DMA!\n");
6894 goto err_out;
6895 }
6896
6897 /* Anti gcc 2.95.3 bugware (sic) */
6898 status = opts[0] | len |
6899 (RingEnd * !((entry + 1) % NUM_TX_DESC));
6900
6901 txd->opts1 = cpu_to_le32(status);
6902 txd->opts2 = cpu_to_le32(opts[1]);
6903 txd->addr = cpu_to_le64(mapping);
6904
6905 tp->tx_skb[entry].len = len;
6906 }
6907
6908 if (cur_frag) {
6909 tp->tx_skb[entry].skb = skb;
6910 txd->opts1 |= cpu_to_le32(LastFrag);
6911 }
6912
6913 return cur_frag;
6914
6915 err_out:
6916 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6917 return -EIO;
6918 }
6919
6920 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6921 {
6922 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6923 }
6924
6925 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6926 struct net_device *dev);
6927 /* r8169_csum_workaround()
6928 * The hw limites the value the transport offset. When the offset is out of the
6929 * range, calculate the checksum by sw.
6930 */
6931 static void r8169_csum_workaround(struct rtl8169_private *tp,
6932 struct sk_buff *skb)
6933 {
6934 if (skb_shinfo(skb)->gso_size) {
6935 netdev_features_t features = tp->dev->features;
6936 struct sk_buff *segs, *nskb;
6937
6938 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6939 segs = skb_gso_segment(skb, features);
6940 if (IS_ERR(segs) || !segs)
6941 goto drop;
6942
6943 do {
6944 nskb = segs;
6945 segs = segs->next;
6946 nskb->next = NULL;
6947 rtl8169_start_xmit(nskb, tp->dev);
6948 } while (segs);
6949
6950 dev_consume_skb_any(skb);
6951 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6952 if (skb_checksum_help(skb) < 0)
6953 goto drop;
6954
6955 rtl8169_start_xmit(skb, tp->dev);
6956 } else {
6957 struct net_device_stats *stats;
6958
6959 drop:
6960 stats = &tp->dev->stats;
6961 stats->tx_dropped++;
6962 dev_kfree_skb_any(skb);
6963 }
6964 }
6965
6966 /* msdn_giant_send_check()
6967 * According to the document of microsoft, the TCP Pseudo Header excludes the
6968 * packet length for IPv6 TCP large packets.
6969 */
6970 static int msdn_giant_send_check(struct sk_buff *skb)
6971 {
6972 const struct ipv6hdr *ipv6h;
6973 struct tcphdr *th;
6974 int ret;
6975
6976 ret = skb_cow_head(skb, 0);
6977 if (ret)
6978 return ret;
6979
6980 ipv6h = ipv6_hdr(skb);
6981 th = tcp_hdr(skb);
6982
6983 th->check = 0;
6984 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6985
6986 return ret;
6987 }
6988
6989 static inline __be16 get_protocol(struct sk_buff *skb)
6990 {
6991 __be16 protocol;
6992
6993 if (skb->protocol == htons(ETH_P_8021Q))
6994 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
6995 else
6996 protocol = skb->protocol;
6997
6998 return protocol;
6999 }
7000
7001 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
7002 struct sk_buff *skb, u32 *opts)
7003 {
7004 u32 mss = skb_shinfo(skb)->gso_size;
7005
7006 if (mss) {
7007 opts[0] |= TD_LSO;
7008 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
7009 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7010 const struct iphdr *ip = ip_hdr(skb);
7011
7012 if (ip->protocol == IPPROTO_TCP)
7013 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
7014 else if (ip->protocol == IPPROTO_UDP)
7015 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
7016 else
7017 WARN_ON_ONCE(1);
7018 }
7019
7020 return true;
7021 }
7022
7023 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
7024 struct sk_buff *skb, u32 *opts)
7025 {
7026 u32 transport_offset = (u32)skb_transport_offset(skb);
7027 u32 mss = skb_shinfo(skb)->gso_size;
7028
7029 if (mss) {
7030 if (transport_offset > GTTCPHO_MAX) {
7031 netif_warn(tp, tx_err, tp->dev,
7032 "Invalid transport offset 0x%x for TSO\n",
7033 transport_offset);
7034 return false;
7035 }
7036
7037 switch (get_protocol(skb)) {
7038 case htons(ETH_P_IP):
7039 opts[0] |= TD1_GTSENV4;
7040 break;
7041
7042 case htons(ETH_P_IPV6):
7043 if (msdn_giant_send_check(skb))
7044 return false;
7045
7046 opts[0] |= TD1_GTSENV6;
7047 break;
7048
7049 default:
7050 WARN_ON_ONCE(1);
7051 break;
7052 }
7053
7054 opts[0] |= transport_offset << GTTCPHO_SHIFT;
7055 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
7056 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7057 u8 ip_protocol;
7058
7059 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7060 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
7061
7062 if (transport_offset > TCPHO_MAX) {
7063 netif_warn(tp, tx_err, tp->dev,
7064 "Invalid transport offset 0x%x\n",
7065 transport_offset);
7066 return false;
7067 }
7068
7069 switch (get_protocol(skb)) {
7070 case htons(ETH_P_IP):
7071 opts[1] |= TD1_IPv4_CS;
7072 ip_protocol = ip_hdr(skb)->protocol;
7073 break;
7074
7075 case htons(ETH_P_IPV6):
7076 opts[1] |= TD1_IPv6_CS;
7077 ip_protocol = ipv6_hdr(skb)->nexthdr;
7078 break;
7079
7080 default:
7081 ip_protocol = IPPROTO_RAW;
7082 break;
7083 }
7084
7085 if (ip_protocol == IPPROTO_TCP)
7086 opts[1] |= TD1_TCP_CS;
7087 else if (ip_protocol == IPPROTO_UDP)
7088 opts[1] |= TD1_UDP_CS;
7089 else
7090 WARN_ON_ONCE(1);
7091
7092 opts[1] |= transport_offset << TCPHO_SHIFT;
7093 } else {
7094 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7095 return !eth_skb_pad(skb);
7096 }
7097
7098 return true;
7099 }
7100
7101 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7102 struct net_device *dev)
7103 {
7104 struct rtl8169_private *tp = netdev_priv(dev);
7105 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
7106 struct TxDesc *txd = tp->TxDescArray + entry;
7107 void __iomem *ioaddr = tp->mmio_addr;
7108 struct device *d = &tp->pci_dev->dev;
7109 dma_addr_t mapping;
7110 u32 status, len;
7111 u32 opts[2];
7112 int frags;
7113
7114 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
7115 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
7116 goto err_stop_0;
7117 }
7118
7119 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
7120 goto err_stop_0;
7121
7122 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
7123 opts[0] = DescOwn;
7124
7125 if (!tp->tso_csum(tp, skb, opts)) {
7126 r8169_csum_workaround(tp, skb);
7127 return NETDEV_TX_OK;
7128 }
7129
7130 len = skb_headlen(skb);
7131 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
7132 if (unlikely(dma_mapping_error(d, mapping))) {
7133 if (net_ratelimit())
7134 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
7135 goto err_dma_0;
7136 }
7137
7138 tp->tx_skb[entry].len = len;
7139 txd->addr = cpu_to_le64(mapping);
7140
7141 frags = rtl8169_xmit_frags(tp, skb, opts);
7142 if (frags < 0)
7143 goto err_dma_1;
7144 else if (frags)
7145 opts[0] |= FirstFrag;
7146 else {
7147 opts[0] |= FirstFrag | LastFrag;
7148 tp->tx_skb[entry].skb = skb;
7149 }
7150
7151 txd->opts2 = cpu_to_le32(opts[1]);
7152
7153 skb_tx_timestamp(skb);
7154
7155 /* Force memory writes to complete before releasing descriptor */
7156 dma_wmb();
7157
7158 /* Anti gcc 2.95.3 bugware (sic) */
7159 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
7160 txd->opts1 = cpu_to_le32(status);
7161
7162 /* Force all memory writes to complete before notifying device */
7163 wmb();
7164
7165 tp->cur_tx += frags + 1;
7166
7167 RTL_W8(TxPoll, NPQ);
7168
7169 mmiowb();
7170
7171 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7172 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7173 * not miss a ring update when it notices a stopped queue.
7174 */
7175 smp_wmb();
7176 netif_stop_queue(dev);
7177 /* Sync with rtl_tx:
7178 * - publish queue status and cur_tx ring index (write barrier)
7179 * - refresh dirty_tx ring index (read barrier).
7180 * May the current thread have a pessimistic view of the ring
7181 * status and forget to wake up queue, a racing rtl_tx thread
7182 * can't.
7183 */
7184 smp_mb();
7185 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
7186 netif_wake_queue(dev);
7187 }
7188
7189 return NETDEV_TX_OK;
7190
7191 err_dma_1:
7192 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
7193 err_dma_0:
7194 dev_kfree_skb_any(skb);
7195 dev->stats.tx_dropped++;
7196 return NETDEV_TX_OK;
7197
7198 err_stop_0:
7199 netif_stop_queue(dev);
7200 dev->stats.tx_dropped++;
7201 return NETDEV_TX_BUSY;
7202 }
7203
7204 static void rtl8169_pcierr_interrupt(struct net_device *dev)
7205 {
7206 struct rtl8169_private *tp = netdev_priv(dev);
7207 struct pci_dev *pdev = tp->pci_dev;
7208 u16 pci_status, pci_cmd;
7209
7210 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
7211 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
7212
7213 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7214 pci_cmd, pci_status);
7215
7216 /*
7217 * The recovery sequence below admits a very elaborated explanation:
7218 * - it seems to work;
7219 * - I did not see what else could be done;
7220 * - it makes iop3xx happy.
7221 *
7222 * Feel free to adjust to your needs.
7223 */
7224 if (pdev->broken_parity_status)
7225 pci_cmd &= ~PCI_COMMAND_PARITY;
7226 else
7227 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
7228
7229 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
7230
7231 pci_write_config_word(pdev, PCI_STATUS,
7232 pci_status & (PCI_STATUS_DETECTED_PARITY |
7233 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
7234 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
7235
7236 /* The infamous DAC f*ckup only happens at boot time */
7237 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
7238 void __iomem *ioaddr = tp->mmio_addr;
7239
7240 netif_info(tp, intr, dev, "disabling PCI DAC\n");
7241 tp->cp_cmd &= ~PCIDAC;
7242 RTL_W16(CPlusCmd, tp->cp_cmd);
7243 dev->features &= ~NETIF_F_HIGHDMA;
7244 }
7245
7246 rtl8169_hw_reset(tp);
7247
7248 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7249 }
7250
7251 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
7252 {
7253 unsigned int dirty_tx, tx_left;
7254
7255 dirty_tx = tp->dirty_tx;
7256 smp_rmb();
7257 tx_left = tp->cur_tx - dirty_tx;
7258
7259 while (tx_left > 0) {
7260 unsigned int entry = dirty_tx % NUM_TX_DESC;
7261 struct ring_info *tx_skb = tp->tx_skb + entry;
7262 u32 status;
7263
7264 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
7265 if (status & DescOwn)
7266 break;
7267
7268 /* This barrier is needed to keep us from reading
7269 * any other fields out of the Tx descriptor until
7270 * we know the status of DescOwn
7271 */
7272 dma_rmb();
7273
7274 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
7275 tp->TxDescArray + entry);
7276 if (status & LastFrag) {
7277 u64_stats_update_begin(&tp->tx_stats.syncp);
7278 tp->tx_stats.packets++;
7279 tp->tx_stats.bytes += tx_skb->skb->len;
7280 u64_stats_update_end(&tp->tx_stats.syncp);
7281 dev_kfree_skb_any(tx_skb->skb);
7282 tx_skb->skb = NULL;
7283 }
7284 dirty_tx++;
7285 tx_left--;
7286 }
7287
7288 if (tp->dirty_tx != dirty_tx) {
7289 tp->dirty_tx = dirty_tx;
7290 /* Sync with rtl8169_start_xmit:
7291 * - publish dirty_tx ring index (write barrier)
7292 * - refresh cur_tx ring index and queue status (read barrier)
7293 * May the current thread miss the stopped queue condition,
7294 * a racing xmit thread can only have a right view of the
7295 * ring status.
7296 */
7297 smp_mb();
7298 if (netif_queue_stopped(dev) &&
7299 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7300 netif_wake_queue(dev);
7301 }
7302 /*
7303 * 8168 hack: TxPoll requests are lost when the Tx packets are
7304 * too close. Let's kick an extra TxPoll request when a burst
7305 * of start_xmit activity is detected (if it is not detected,
7306 * it is slow enough). -- FR
7307 */
7308 if (tp->cur_tx != dirty_tx) {
7309 void __iomem *ioaddr = tp->mmio_addr;
7310
7311 RTL_W8(TxPoll, NPQ);
7312 }
7313 }
7314 }
7315
7316 static inline int rtl8169_fragmented_frame(u32 status)
7317 {
7318 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
7319 }
7320
7321 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
7322 {
7323 u32 status = opts1 & RxProtoMask;
7324
7325 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
7326 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
7327 skb->ip_summed = CHECKSUM_UNNECESSARY;
7328 else
7329 skb_checksum_none_assert(skb);
7330 }
7331
7332 static struct sk_buff *rtl8169_try_rx_copy(void *data,
7333 struct rtl8169_private *tp,
7334 int pkt_size,
7335 dma_addr_t addr)
7336 {
7337 struct sk_buff *skb;
7338 struct device *d = &tp->pci_dev->dev;
7339
7340 data = rtl8169_align(data);
7341 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
7342 prefetch(data);
7343 skb = napi_alloc_skb(&tp->napi, pkt_size);
7344 if (skb)
7345 memcpy(skb->data, data, pkt_size);
7346 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
7347
7348 return skb;
7349 }
7350
7351 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
7352 {
7353 unsigned int cur_rx, rx_left;
7354 unsigned int count;
7355
7356 cur_rx = tp->cur_rx;
7357
7358 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
7359 unsigned int entry = cur_rx % NUM_RX_DESC;
7360 struct RxDesc *desc = tp->RxDescArray + entry;
7361 u32 status;
7362
7363 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
7364 if (status & DescOwn)
7365 break;
7366
7367 /* This barrier is needed to keep us from reading
7368 * any other fields out of the Rx descriptor until
7369 * we know the status of DescOwn
7370 */
7371 dma_rmb();
7372
7373 if (unlikely(status & RxRES)) {
7374 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
7375 status);
7376 dev->stats.rx_errors++;
7377 if (status & (RxRWT | RxRUNT))
7378 dev->stats.rx_length_errors++;
7379 if (status & RxCRC)
7380 dev->stats.rx_crc_errors++;
7381 if (status & RxFOVF) {
7382 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7383 dev->stats.rx_fifo_errors++;
7384 }
7385 if ((status & (RxRUNT | RxCRC)) &&
7386 !(status & (RxRWT | RxFOVF)) &&
7387 (dev->features & NETIF_F_RXALL))
7388 goto process_pkt;
7389 } else {
7390 struct sk_buff *skb;
7391 dma_addr_t addr;
7392 int pkt_size;
7393
7394 process_pkt:
7395 addr = le64_to_cpu(desc->addr);
7396 if (likely(!(dev->features & NETIF_F_RXFCS)))
7397 pkt_size = (status & 0x00003fff) - 4;
7398 else
7399 pkt_size = status & 0x00003fff;
7400
7401 /*
7402 * The driver does not support incoming fragmented
7403 * frames. They are seen as a symptom of over-mtu
7404 * sized frames.
7405 */
7406 if (unlikely(rtl8169_fragmented_frame(status))) {
7407 dev->stats.rx_dropped++;
7408 dev->stats.rx_length_errors++;
7409 goto release_descriptor;
7410 }
7411
7412 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
7413 tp, pkt_size, addr);
7414 if (!skb) {
7415 dev->stats.rx_dropped++;
7416 goto release_descriptor;
7417 }
7418
7419 rtl8169_rx_csum(skb, status);
7420 skb_put(skb, pkt_size);
7421 skb->protocol = eth_type_trans(skb, dev);
7422
7423 rtl8169_rx_vlan_tag(desc, skb);
7424
7425 if (skb->pkt_type == PACKET_MULTICAST)
7426 dev->stats.multicast++;
7427
7428 napi_gro_receive(&tp->napi, skb);
7429
7430 u64_stats_update_begin(&tp->rx_stats.syncp);
7431 tp->rx_stats.packets++;
7432 tp->rx_stats.bytes += pkt_size;
7433 u64_stats_update_end(&tp->rx_stats.syncp);
7434 }
7435 release_descriptor:
7436 desc->opts2 = 0;
7437 rtl8169_mark_to_asic(desc, rx_buf_sz);
7438 }
7439
7440 count = cur_rx - tp->cur_rx;
7441 tp->cur_rx = cur_rx;
7442
7443 return count;
7444 }
7445
7446 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
7447 {
7448 struct net_device *dev = dev_instance;
7449 struct rtl8169_private *tp = netdev_priv(dev);
7450 int handled = 0;
7451 u16 status;
7452
7453 status = rtl_get_events(tp);
7454 if (status && status != 0xffff) {
7455 status &= RTL_EVENT_NAPI | tp->event_slow;
7456 if (status) {
7457 handled = 1;
7458
7459 rtl_irq_disable(tp);
7460 napi_schedule(&tp->napi);
7461 }
7462 }
7463 return IRQ_RETVAL(handled);
7464 }
7465
7466 /*
7467 * Workqueue context.
7468 */
7469 static void rtl_slow_event_work(struct rtl8169_private *tp)
7470 {
7471 struct net_device *dev = tp->dev;
7472 u16 status;
7473
7474 status = rtl_get_events(tp) & tp->event_slow;
7475 rtl_ack_events(tp, status);
7476
7477 if (unlikely(status & RxFIFOOver)) {
7478 switch (tp->mac_version) {
7479 /* Work around for rx fifo overflow */
7480 case RTL_GIGA_MAC_VER_11:
7481 netif_stop_queue(dev);
7482 /* XXX - Hack alert. See rtl_task(). */
7483 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
7484 default:
7485 break;
7486 }
7487 }
7488
7489 if (unlikely(status & SYSErr))
7490 rtl8169_pcierr_interrupt(dev);
7491
7492 if (status & LinkChg)
7493 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
7494
7495 rtl_irq_enable_all(tp);
7496 }
7497
7498 static void rtl_task(struct work_struct *work)
7499 {
7500 static const struct {
7501 int bitnr;
7502 void (*action)(struct rtl8169_private *);
7503 } rtl_work[] = {
7504 /* XXX - keep rtl_slow_event_work() as first element. */
7505 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
7506 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
7507 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
7508 };
7509 struct rtl8169_private *tp =
7510 container_of(work, struct rtl8169_private, wk.work);
7511 struct net_device *dev = tp->dev;
7512 int i;
7513
7514 rtl_lock_work(tp);
7515
7516 if (!netif_running(dev) ||
7517 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
7518 goto out_unlock;
7519
7520 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7521 bool pending;
7522
7523 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
7524 if (pending)
7525 rtl_work[i].action(tp);
7526 }
7527
7528 out_unlock:
7529 rtl_unlock_work(tp);
7530 }
7531
7532 static int rtl8169_poll(struct napi_struct *napi, int budget)
7533 {
7534 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7535 struct net_device *dev = tp->dev;
7536 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
7537 int work_done= 0;
7538 u16 status;
7539
7540 status = rtl_get_events(tp);
7541 rtl_ack_events(tp, status & ~tp->event_slow);
7542
7543 if (status & RTL_EVENT_NAPI_RX)
7544 work_done = rtl_rx(dev, tp, (u32) budget);
7545
7546 if (status & RTL_EVENT_NAPI_TX)
7547 rtl_tx(dev, tp);
7548
7549 if (status & tp->event_slow) {
7550 enable_mask &= ~tp->event_slow;
7551
7552 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7553 }
7554
7555 if (work_done < budget) {
7556 napi_complete(napi);
7557
7558 rtl_irq_enable(tp, enable_mask);
7559 mmiowb();
7560 }
7561
7562 return work_done;
7563 }
7564
7565 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
7566 {
7567 struct rtl8169_private *tp = netdev_priv(dev);
7568
7569 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7570 return;
7571
7572 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
7573 RTL_W32(RxMissed, 0);
7574 }
7575
7576 static void rtl8169_down(struct net_device *dev)
7577 {
7578 struct rtl8169_private *tp = netdev_priv(dev);
7579 void __iomem *ioaddr = tp->mmio_addr;
7580
7581 del_timer_sync(&tp->timer);
7582
7583 napi_disable(&tp->napi);
7584 netif_stop_queue(dev);
7585
7586 rtl8169_hw_reset(tp);
7587 /*
7588 * At this point device interrupts can not be enabled in any function,
7589 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7590 * and napi is disabled (rtl8169_poll).
7591 */
7592 rtl8169_rx_missed(dev, ioaddr);
7593
7594 /* Give a racing hard_start_xmit a few cycles to complete. */
7595 synchronize_sched();
7596
7597 rtl8169_tx_clear(tp);
7598
7599 rtl8169_rx_clear(tp);
7600
7601 rtl_pll_power_down(tp);
7602 }
7603
7604 static int rtl8169_close(struct net_device *dev)
7605 {
7606 struct rtl8169_private *tp = netdev_priv(dev);
7607 struct pci_dev *pdev = tp->pci_dev;
7608
7609 pm_runtime_get_sync(&pdev->dev);
7610
7611 /* Update counters before going down */
7612 rtl8169_update_counters(dev);
7613
7614 rtl_lock_work(tp);
7615 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7616
7617 rtl8169_down(dev);
7618 rtl_unlock_work(tp);
7619
7620 cancel_work_sync(&tp->wk.work);
7621
7622 free_irq(pdev->irq, dev);
7623
7624 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7625 tp->RxPhyAddr);
7626 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7627 tp->TxPhyAddr);
7628 tp->TxDescArray = NULL;
7629 tp->RxDescArray = NULL;
7630
7631 pm_runtime_put_sync(&pdev->dev);
7632
7633 return 0;
7634 }
7635
7636 #ifdef CONFIG_NET_POLL_CONTROLLER
7637 static void rtl8169_netpoll(struct net_device *dev)
7638 {
7639 struct rtl8169_private *tp = netdev_priv(dev);
7640
7641 rtl8169_interrupt(tp->pci_dev->irq, dev);
7642 }
7643 #endif
7644
7645 static int rtl_open(struct net_device *dev)
7646 {
7647 struct rtl8169_private *tp = netdev_priv(dev);
7648 void __iomem *ioaddr = tp->mmio_addr;
7649 struct pci_dev *pdev = tp->pci_dev;
7650 int retval = -ENOMEM;
7651
7652 pm_runtime_get_sync(&pdev->dev);
7653
7654 /*
7655 * Rx and Tx descriptors needs 256 bytes alignment.
7656 * dma_alloc_coherent provides more.
7657 */
7658 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7659 &tp->TxPhyAddr, GFP_KERNEL);
7660 if (!tp->TxDescArray)
7661 goto err_pm_runtime_put;
7662
7663 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7664 &tp->RxPhyAddr, GFP_KERNEL);
7665 if (!tp->RxDescArray)
7666 goto err_free_tx_0;
7667
7668 retval = rtl8169_init_ring(dev);
7669 if (retval < 0)
7670 goto err_free_rx_1;
7671
7672 INIT_WORK(&tp->wk.work, rtl_task);
7673
7674 smp_mb();
7675
7676 rtl_request_firmware(tp);
7677
7678 retval = request_irq(pdev->irq, rtl8169_interrupt,
7679 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
7680 dev->name, dev);
7681 if (retval < 0)
7682 goto err_release_fw_2;
7683
7684 rtl_lock_work(tp);
7685
7686 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7687
7688 napi_enable(&tp->napi);
7689
7690 rtl8169_init_phy(dev, tp);
7691
7692 __rtl8169_set_features(dev, dev->features);
7693
7694 rtl_pll_power_up(tp);
7695
7696 rtl_hw_start(dev);
7697
7698 if (!rtl8169_init_counter_offsets(dev))
7699 netif_warn(tp, hw, dev, "counter reset/update failed\n");
7700
7701 netif_start_queue(dev);
7702
7703 rtl_unlock_work(tp);
7704
7705 tp->saved_wolopts = 0;
7706 pm_runtime_put_noidle(&pdev->dev);
7707
7708 rtl8169_check_link_status(dev, tp, ioaddr);
7709 out:
7710 return retval;
7711
7712 err_release_fw_2:
7713 rtl_release_firmware(tp);
7714 rtl8169_rx_clear(tp);
7715 err_free_rx_1:
7716 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7717 tp->RxPhyAddr);
7718 tp->RxDescArray = NULL;
7719 err_free_tx_0:
7720 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7721 tp->TxPhyAddr);
7722 tp->TxDescArray = NULL;
7723 err_pm_runtime_put:
7724 pm_runtime_put_noidle(&pdev->dev);
7725 goto out;
7726 }
7727
7728 static struct rtnl_link_stats64 *
7729 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7730 {
7731 struct rtl8169_private *tp = netdev_priv(dev);
7732 void __iomem *ioaddr = tp->mmio_addr;
7733 struct rtl8169_counters *counters = tp->counters;
7734 unsigned int start;
7735
7736 if (netif_running(dev))
7737 rtl8169_rx_missed(dev, ioaddr);
7738
7739 do {
7740 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
7741 stats->rx_packets = tp->rx_stats.packets;
7742 stats->rx_bytes = tp->rx_stats.bytes;
7743 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
7744
7745 do {
7746 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
7747 stats->tx_packets = tp->tx_stats.packets;
7748 stats->tx_bytes = tp->tx_stats.bytes;
7749 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
7750
7751 stats->rx_dropped = dev->stats.rx_dropped;
7752 stats->tx_dropped = dev->stats.tx_dropped;
7753 stats->rx_length_errors = dev->stats.rx_length_errors;
7754 stats->rx_errors = dev->stats.rx_errors;
7755 stats->rx_crc_errors = dev->stats.rx_crc_errors;
7756 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
7757 stats->rx_missed_errors = dev->stats.rx_missed_errors;
7758 stats->multicast = dev->stats.multicast;
7759
7760 /*
7761 * Fetch additonal counter values missing in stats collected by driver
7762 * from tally counters.
7763 */
7764 rtl8169_update_counters(dev);
7765
7766 /*
7767 * Subtract values fetched during initalization.
7768 * See rtl8169_init_counter_offsets for a description why we do that.
7769 */
7770 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
7771 le64_to_cpu(tp->tc_offset.tx_errors);
7772 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
7773 le32_to_cpu(tp->tc_offset.tx_multi_collision);
7774 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
7775 le16_to_cpu(tp->tc_offset.tx_aborted);
7776
7777 return stats;
7778 }
7779
7780 static void rtl8169_net_suspend(struct net_device *dev)
7781 {
7782 struct rtl8169_private *tp = netdev_priv(dev);
7783
7784 if (!netif_running(dev))
7785 return;
7786
7787 netif_device_detach(dev);
7788 netif_stop_queue(dev);
7789
7790 rtl_lock_work(tp);
7791 napi_disable(&tp->napi);
7792 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7793 rtl_unlock_work(tp);
7794
7795 rtl_pll_power_down(tp);
7796 }
7797
7798 #ifdef CONFIG_PM
7799
7800 static int rtl8169_suspend(struct device *device)
7801 {
7802 struct pci_dev *pdev = to_pci_dev(device);
7803 struct net_device *dev = pci_get_drvdata(pdev);
7804
7805 rtl8169_net_suspend(dev);
7806
7807 return 0;
7808 }
7809
7810 static void __rtl8169_resume(struct net_device *dev)
7811 {
7812 struct rtl8169_private *tp = netdev_priv(dev);
7813
7814 netif_device_attach(dev);
7815
7816 rtl_pll_power_up(tp);
7817
7818 rtl_lock_work(tp);
7819 napi_enable(&tp->napi);
7820 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7821 rtl_unlock_work(tp);
7822
7823 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7824 }
7825
7826 static int rtl8169_resume(struct device *device)
7827 {
7828 struct pci_dev *pdev = to_pci_dev(device);
7829 struct net_device *dev = pci_get_drvdata(pdev);
7830 struct rtl8169_private *tp = netdev_priv(dev);
7831
7832 rtl8169_init_phy(dev, tp);
7833
7834 if (netif_running(dev))
7835 __rtl8169_resume(dev);
7836
7837 return 0;
7838 }
7839
7840 static int rtl8169_runtime_suspend(struct device *device)
7841 {
7842 struct pci_dev *pdev = to_pci_dev(device);
7843 struct net_device *dev = pci_get_drvdata(pdev);
7844 struct rtl8169_private *tp = netdev_priv(dev);
7845
7846 if (!tp->TxDescArray)
7847 return 0;
7848
7849 rtl_lock_work(tp);
7850 tp->saved_wolopts = __rtl8169_get_wol(tp);
7851 __rtl8169_set_wol(tp, WAKE_ANY);
7852 rtl_unlock_work(tp);
7853
7854 rtl8169_net_suspend(dev);
7855
7856 return 0;
7857 }
7858
7859 static int rtl8169_runtime_resume(struct device *device)
7860 {
7861 struct pci_dev *pdev = to_pci_dev(device);
7862 struct net_device *dev = pci_get_drvdata(pdev);
7863 struct rtl8169_private *tp = netdev_priv(dev);
7864
7865 if (!tp->TxDescArray)
7866 return 0;
7867
7868 rtl_lock_work(tp);
7869 __rtl8169_set_wol(tp, tp->saved_wolopts);
7870 tp->saved_wolopts = 0;
7871 rtl_unlock_work(tp);
7872
7873 rtl8169_init_phy(dev, tp);
7874
7875 __rtl8169_resume(dev);
7876
7877 return 0;
7878 }
7879
7880 static int rtl8169_runtime_idle(struct device *device)
7881 {
7882 struct pci_dev *pdev = to_pci_dev(device);
7883 struct net_device *dev = pci_get_drvdata(pdev);
7884 struct rtl8169_private *tp = netdev_priv(dev);
7885
7886 return tp->TxDescArray ? -EBUSY : 0;
7887 }
7888
7889 static const struct dev_pm_ops rtl8169_pm_ops = {
7890 .suspend = rtl8169_suspend,
7891 .resume = rtl8169_resume,
7892 .freeze = rtl8169_suspend,
7893 .thaw = rtl8169_resume,
7894 .poweroff = rtl8169_suspend,
7895 .restore = rtl8169_resume,
7896 .runtime_suspend = rtl8169_runtime_suspend,
7897 .runtime_resume = rtl8169_runtime_resume,
7898 .runtime_idle = rtl8169_runtime_idle,
7899 };
7900
7901 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
7902
7903 #else /* !CONFIG_PM */
7904
7905 #define RTL8169_PM_OPS NULL
7906
7907 #endif /* !CONFIG_PM */
7908
7909 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7910 {
7911 void __iomem *ioaddr = tp->mmio_addr;
7912
7913 /* WoL fails with 8168b when the receiver is disabled. */
7914 switch (tp->mac_version) {
7915 case RTL_GIGA_MAC_VER_11:
7916 case RTL_GIGA_MAC_VER_12:
7917 case RTL_GIGA_MAC_VER_17:
7918 pci_clear_master(tp->pci_dev);
7919
7920 RTL_W8(ChipCmd, CmdRxEnb);
7921 /* PCI commit */
7922 RTL_R8(ChipCmd);
7923 break;
7924 default:
7925 break;
7926 }
7927 }
7928
7929 static void rtl_shutdown(struct pci_dev *pdev)
7930 {
7931 struct net_device *dev = pci_get_drvdata(pdev);
7932 struct rtl8169_private *tp = netdev_priv(dev);
7933 struct device *d = &pdev->dev;
7934
7935 pm_runtime_get_sync(d);
7936
7937 rtl8169_net_suspend(dev);
7938
7939 /* Restore original MAC address */
7940 rtl_rar_set(tp, dev->perm_addr);
7941
7942 rtl8169_hw_reset(tp);
7943
7944 if (system_state == SYSTEM_POWER_OFF) {
7945 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
7946 rtl_wol_suspend_quirk(tp);
7947 rtl_wol_shutdown_quirk(tp);
7948 }
7949
7950 pci_wake_from_d3(pdev, true);
7951 pci_set_power_state(pdev, PCI_D3hot);
7952 }
7953
7954 pm_runtime_put_noidle(d);
7955 }
7956
7957 static void rtl_remove_one(struct pci_dev *pdev)
7958 {
7959 struct net_device *dev = pci_get_drvdata(pdev);
7960 struct rtl8169_private *tp = netdev_priv(dev);
7961
7962 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7963 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7964 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
7965 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
7966 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
7967 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
7968 r8168_check_dash(tp)) {
7969 rtl8168_driver_stop(tp);
7970 }
7971
7972 netif_napi_del(&tp->napi);
7973
7974 unregister_netdev(dev);
7975
7976 dma_free_coherent(&tp->pci_dev->dev, sizeof(*tp->counters),
7977 tp->counters, tp->counters_phys_addr);
7978
7979 rtl_release_firmware(tp);
7980
7981 if (pci_dev_run_wake(pdev))
7982 pm_runtime_get_noresume(&pdev->dev);
7983
7984 /* restore original MAC address */
7985 rtl_rar_set(tp, dev->perm_addr);
7986
7987 rtl_disable_msi(pdev, tp);
7988 rtl8169_release_board(pdev, dev, tp->mmio_addr);
7989 }
7990
7991 static const struct net_device_ops rtl_netdev_ops = {
7992 .ndo_open = rtl_open,
7993 .ndo_stop = rtl8169_close,
7994 .ndo_get_stats64 = rtl8169_get_stats64,
7995 .ndo_start_xmit = rtl8169_start_xmit,
7996 .ndo_tx_timeout = rtl8169_tx_timeout,
7997 .ndo_validate_addr = eth_validate_addr,
7998 .ndo_change_mtu = rtl8169_change_mtu,
7999 .ndo_fix_features = rtl8169_fix_features,
8000 .ndo_set_features = rtl8169_set_features,
8001 .ndo_set_mac_address = rtl_set_mac_address,
8002 .ndo_do_ioctl = rtl8169_ioctl,
8003 .ndo_set_rx_mode = rtl_set_rx_mode,
8004 #ifdef CONFIG_NET_POLL_CONTROLLER
8005 .ndo_poll_controller = rtl8169_netpoll,
8006 #endif
8007
8008 };
8009
8010 static const struct rtl_cfg_info {
8011 void (*hw_start)(struct net_device *);
8012 unsigned int region;
8013 unsigned int align;
8014 u16 event_slow;
8015 unsigned features;
8016 u8 default_ver;
8017 } rtl_cfg_infos [] = {
8018 [RTL_CFG_0] = {
8019 .hw_start = rtl_hw_start_8169,
8020 .region = 1,
8021 .align = 0,
8022 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
8023 .features = RTL_FEATURE_GMII,
8024 .default_ver = RTL_GIGA_MAC_VER_01,
8025 },
8026 [RTL_CFG_1] = {
8027 .hw_start = rtl_hw_start_8168,
8028 .region = 2,
8029 .align = 8,
8030 .event_slow = SYSErr | LinkChg | RxOverflow,
8031 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
8032 .default_ver = RTL_GIGA_MAC_VER_11,
8033 },
8034 [RTL_CFG_2] = {
8035 .hw_start = rtl_hw_start_8101,
8036 .region = 2,
8037 .align = 8,
8038 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
8039 PCSTimeout,
8040 .features = RTL_FEATURE_MSI,
8041 .default_ver = RTL_GIGA_MAC_VER_13,
8042 }
8043 };
8044
8045 /* Cfg9346_Unlock assumed. */
8046 static unsigned rtl_try_msi(struct rtl8169_private *tp,
8047 const struct rtl_cfg_info *cfg)
8048 {
8049 void __iomem *ioaddr = tp->mmio_addr;
8050 unsigned msi = 0;
8051 u8 cfg2;
8052
8053 cfg2 = RTL_R8(Config2) & ~MSIEnable;
8054 if (cfg->features & RTL_FEATURE_MSI) {
8055 if (pci_enable_msi(tp->pci_dev)) {
8056 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
8057 } else {
8058 cfg2 |= MSIEnable;
8059 msi = RTL_FEATURE_MSI;
8060 }
8061 }
8062 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
8063 RTL_W8(Config2, cfg2);
8064 return msi;
8065 }
8066
8067 DECLARE_RTL_COND(rtl_link_list_ready_cond)
8068 {
8069 void __iomem *ioaddr = tp->mmio_addr;
8070
8071 return RTL_R8(MCU) & LINK_LIST_RDY;
8072 }
8073
8074 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
8075 {
8076 void __iomem *ioaddr = tp->mmio_addr;
8077
8078 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
8079 }
8080
8081 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
8082 {
8083 void __iomem *ioaddr = tp->mmio_addr;
8084 u32 data;
8085
8086 tp->ocp_base = OCP_STD_PHY_BASE;
8087
8088 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
8089
8090 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
8091 return;
8092
8093 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
8094 return;
8095
8096 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
8097 msleep(1);
8098 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
8099
8100 data = r8168_mac_ocp_read(tp, 0xe8de);
8101 data &= ~(1 << 14);
8102 r8168_mac_ocp_write(tp, 0xe8de, data);
8103
8104 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8105 return;
8106
8107 data = r8168_mac_ocp_read(tp, 0xe8de);
8108 data |= (1 << 15);
8109 r8168_mac_ocp_write(tp, 0xe8de, data);
8110
8111 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8112 return;
8113 }
8114
8115 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
8116 {
8117 rtl8168ep_stop_cmac(tp);
8118 rtl_hw_init_8168g(tp);
8119 }
8120
8121 static void rtl_hw_initialize(struct rtl8169_private *tp)
8122 {
8123 switch (tp->mac_version) {
8124 case RTL_GIGA_MAC_VER_40:
8125 case RTL_GIGA_MAC_VER_41:
8126 case RTL_GIGA_MAC_VER_42:
8127 case RTL_GIGA_MAC_VER_43:
8128 case RTL_GIGA_MAC_VER_44:
8129 case RTL_GIGA_MAC_VER_45:
8130 case RTL_GIGA_MAC_VER_46:
8131 case RTL_GIGA_MAC_VER_47:
8132 case RTL_GIGA_MAC_VER_48:
8133 rtl_hw_init_8168g(tp);
8134 break;
8135 case RTL_GIGA_MAC_VER_49:
8136 case RTL_GIGA_MAC_VER_50:
8137 case RTL_GIGA_MAC_VER_51:
8138 rtl_hw_init_8168ep(tp);
8139 break;
8140 default:
8141 break;
8142 }
8143 }
8144
8145 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8146 {
8147 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
8148 const unsigned int region = cfg->region;
8149 struct rtl8169_private *tp;
8150 struct mii_if_info *mii;
8151 struct net_device *dev;
8152 void __iomem *ioaddr;
8153 int chipset, i;
8154 int rc;
8155
8156 if (netif_msg_drv(&debug)) {
8157 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
8158 MODULENAME, RTL8169_VERSION);
8159 }
8160
8161 dev = alloc_etherdev(sizeof (*tp));
8162 if (!dev) {
8163 rc = -ENOMEM;
8164 goto out;
8165 }
8166
8167 SET_NETDEV_DEV(dev, &pdev->dev);
8168 dev->netdev_ops = &rtl_netdev_ops;
8169 tp = netdev_priv(dev);
8170 tp->dev = dev;
8171 tp->pci_dev = pdev;
8172 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
8173
8174 mii = &tp->mii;
8175 mii->dev = dev;
8176 mii->mdio_read = rtl_mdio_read;
8177 mii->mdio_write = rtl_mdio_write;
8178 mii->phy_id_mask = 0x1f;
8179 mii->reg_num_mask = 0x1f;
8180 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
8181
8182 /* disable ASPM completely as that cause random device stop working
8183 * problems as well as full system hangs for some PCIe devices users */
8184 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
8185 PCIE_LINK_STATE_CLKPM);
8186
8187 /* enable device (incl. PCI PM wakeup and hotplug setup) */
8188 rc = pci_enable_device(pdev);
8189 if (rc < 0) {
8190 netif_err(tp, probe, dev, "enable failure\n");
8191 goto err_out_free_dev_1;
8192 }
8193
8194 if (pci_set_mwi(pdev) < 0)
8195 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
8196
8197 /* make sure PCI base addr 1 is MMIO */
8198 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
8199 netif_err(tp, probe, dev,
8200 "region #%d not an MMIO resource, aborting\n",
8201 region);
8202 rc = -ENODEV;
8203 goto err_out_mwi_2;
8204 }
8205
8206 /* check for weird/broken PCI region reporting */
8207 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
8208 netif_err(tp, probe, dev,
8209 "Invalid PCI region size(s), aborting\n");
8210 rc = -ENODEV;
8211 goto err_out_mwi_2;
8212 }
8213
8214 rc = pci_request_regions(pdev, MODULENAME);
8215 if (rc < 0) {
8216 netif_err(tp, probe, dev, "could not request regions\n");
8217 goto err_out_mwi_2;
8218 }
8219
8220 tp->cp_cmd = 0;
8221
8222 if ((sizeof(dma_addr_t) > 4) &&
8223 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
8224 tp->cp_cmd |= PCIDAC;
8225 dev->features |= NETIF_F_HIGHDMA;
8226 } else {
8227 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8228 if (rc < 0) {
8229 netif_err(tp, probe, dev, "DMA configuration failed\n");
8230 goto err_out_free_res_3;
8231 }
8232 }
8233
8234 /* ioremap MMIO region */
8235 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
8236 if (!ioaddr) {
8237 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
8238 rc = -EIO;
8239 goto err_out_free_res_3;
8240 }
8241 tp->mmio_addr = ioaddr;
8242
8243 if (!pci_is_pcie(pdev))
8244 netif_info(tp, probe, dev, "not PCI Express\n");
8245
8246 /* Identify chip attached to board */
8247 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
8248
8249 rtl_init_rxcfg(tp);
8250
8251 rtl_irq_disable(tp);
8252
8253 rtl_hw_initialize(tp);
8254
8255 rtl_hw_reset(tp);
8256
8257 rtl_ack_events(tp, 0xffff);
8258
8259 pci_set_master(pdev);
8260
8261 rtl_init_mdio_ops(tp);
8262 rtl_init_pll_power_ops(tp);
8263 rtl_init_jumbo_ops(tp);
8264 rtl_init_csi_ops(tp);
8265
8266 rtl8169_print_mac_version(tp);
8267
8268 chipset = tp->mac_version;
8269 tp->txd_version = rtl_chip_infos[chipset].txd_version;
8270
8271 RTL_W8(Cfg9346, Cfg9346_Unlock);
8272 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
8273 RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
8274 switch (tp->mac_version) {
8275 case RTL_GIGA_MAC_VER_34:
8276 case RTL_GIGA_MAC_VER_35:
8277 case RTL_GIGA_MAC_VER_36:
8278 case RTL_GIGA_MAC_VER_37:
8279 case RTL_GIGA_MAC_VER_38:
8280 case RTL_GIGA_MAC_VER_40:
8281 case RTL_GIGA_MAC_VER_41:
8282 case RTL_GIGA_MAC_VER_42:
8283 case RTL_GIGA_MAC_VER_43:
8284 case RTL_GIGA_MAC_VER_44:
8285 case RTL_GIGA_MAC_VER_45:
8286 case RTL_GIGA_MAC_VER_46:
8287 case RTL_GIGA_MAC_VER_47:
8288 case RTL_GIGA_MAC_VER_48:
8289 case RTL_GIGA_MAC_VER_49:
8290 case RTL_GIGA_MAC_VER_50:
8291 case RTL_GIGA_MAC_VER_51:
8292 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
8293 tp->features |= RTL_FEATURE_WOL;
8294 if ((RTL_R8(Config3) & LinkUp) != 0)
8295 tp->features |= RTL_FEATURE_WOL;
8296 break;
8297 default:
8298 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
8299 tp->features |= RTL_FEATURE_WOL;
8300 break;
8301 }
8302 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
8303 tp->features |= RTL_FEATURE_WOL;
8304 tp->features |= rtl_try_msi(tp, cfg);
8305 RTL_W8(Cfg9346, Cfg9346_Lock);
8306
8307 if (rtl_tbi_enabled(tp)) {
8308 tp->set_speed = rtl8169_set_speed_tbi;
8309 tp->get_settings = rtl8169_gset_tbi;
8310 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
8311 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
8312 tp->link_ok = rtl8169_tbi_link_ok;
8313 tp->do_ioctl = rtl_tbi_ioctl;
8314 } else {
8315 tp->set_speed = rtl8169_set_speed_xmii;
8316 tp->get_settings = rtl8169_gset_xmii;
8317 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
8318 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
8319 tp->link_ok = rtl8169_xmii_link_ok;
8320 tp->do_ioctl = rtl_xmii_ioctl;
8321 }
8322
8323 mutex_init(&tp->wk.mutex);
8324 u64_stats_init(&tp->rx_stats.syncp);
8325 u64_stats_init(&tp->tx_stats.syncp);
8326
8327 /* Get MAC address */
8328 if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
8329 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
8330 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
8331 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
8332 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
8333 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
8334 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
8335 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
8336 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
8337 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
8338 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
8339 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
8340 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
8341 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8342 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8343 tp->mac_version == RTL_GIGA_MAC_VER_51) {
8344 u16 mac_addr[3];
8345
8346 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
8347 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
8348
8349 if (is_valid_ether_addr((u8 *)mac_addr))
8350 rtl_rar_set(tp, (u8 *)mac_addr);
8351 }
8352 for (i = 0; i < ETH_ALEN; i++)
8353 dev->dev_addr[i] = RTL_R8(MAC0 + i);
8354
8355 dev->ethtool_ops = &rtl8169_ethtool_ops;
8356 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
8357
8358 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
8359
8360 /* don't enable SG, IP_CSUM and TSO by default - it might not work
8361 * properly for all devices */
8362 dev->features |= NETIF_F_RXCSUM |
8363 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
8364
8365 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8366 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
8367 NETIF_F_HW_VLAN_CTAG_RX;
8368 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8369 NETIF_F_HIGHDMA;
8370
8371 tp->cp_cmd |= RxChkSum | RxVlan;
8372
8373 /*
8374 * Pretend we are using VLANs; This bypasses a nasty bug where
8375 * Interrupts stop flowing on high load on 8110SCd controllers.
8376 */
8377 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
8378 /* Disallow toggling */
8379 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
8380
8381 if (tp->txd_version == RTL_TD_0)
8382 tp->tso_csum = rtl8169_tso_csum_v1;
8383 else if (tp->txd_version == RTL_TD_1) {
8384 tp->tso_csum = rtl8169_tso_csum_v2;
8385 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8386 } else
8387 WARN_ON_ONCE(1);
8388
8389 dev->hw_features |= NETIF_F_RXALL;
8390 dev->hw_features |= NETIF_F_RXFCS;
8391
8392 tp->hw_start = cfg->hw_start;
8393 tp->event_slow = cfg->event_slow;
8394
8395 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
8396 ~(RxBOVF | RxFOVF) : ~0;
8397
8398 init_timer(&tp->timer);
8399 tp->timer.data = (unsigned long) dev;
8400 tp->timer.function = rtl8169_phy_timer;
8401
8402 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
8403
8404 tp->counters = dma_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
8405 &tp->counters_phys_addr, GFP_KERNEL);
8406 if (!tp->counters) {
8407 rc = -ENOMEM;
8408 goto err_out_msi_4;
8409 }
8410
8411 rc = register_netdev(dev);
8412 if (rc < 0)
8413 goto err_out_cnt_5;
8414
8415 pci_set_drvdata(pdev, dev);
8416
8417 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
8418 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
8419 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
8420 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
8421 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
8422 "tx checksumming: %s]\n",
8423 rtl_chip_infos[chipset].jumbo_max,
8424 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
8425 }
8426
8427 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8428 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
8429 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8430 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8431 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8432 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
8433 r8168_check_dash(tp)) {
8434 rtl8168_driver_start(tp);
8435 }
8436
8437 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
8438
8439 if (pci_dev_run_wake(pdev))
8440 pm_runtime_put_noidle(&pdev->dev);
8441
8442 netif_carrier_off(dev);
8443
8444 out:
8445 return rc;
8446
8447 err_out_cnt_5:
8448 dma_free_coherent(&pdev->dev, sizeof(*tp->counters), tp->counters,
8449 tp->counters_phys_addr);
8450 err_out_msi_4:
8451 netif_napi_del(&tp->napi);
8452 rtl_disable_msi(pdev, tp);
8453 iounmap(ioaddr);
8454 err_out_free_res_3:
8455 pci_release_regions(pdev);
8456 err_out_mwi_2:
8457 pci_clear_mwi(pdev);
8458 pci_disable_device(pdev);
8459 err_out_free_dev_1:
8460 free_netdev(dev);
8461 goto out;
8462 }
8463
8464 static struct pci_driver rtl8169_pci_driver = {
8465 .name = MODULENAME,
8466 .id_table = rtl8169_pci_tbl,
8467 .probe = rtl_init_one,
8468 .remove = rtl_remove_one,
8469 .shutdown = rtl_shutdown,
8470 .driver.pm = RTL8169_PM_OPS,
8471 };
8472
8473 module_pci_driver(rtl8169_pci_driver);
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