2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/pci-aspm.h>
30 #include <linux/prefetch.h>
32 #include <asm/system.h>
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
45 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
47 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
50 #define assert(expr) \
52 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
53 #expr,__FILE__,__func__,__LINE__); \
55 #define dprintk(fmt, args...) \
56 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
58 #define assert(expr) do {} while (0)
59 #define dprintk(fmt, args...) do {} while (0)
60 #endif /* RTL8169_DEBUG */
62 #define R8169_MSG_DEFAULT \
63 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
65 #define TX_BUFFS_AVAIL(tp) \
66 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
68 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
69 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
70 static const int multicast_filter_limit
= 32;
72 #define MAX_READ_REQUEST_SHIFT 12
73 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
74 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
75 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
77 #define R8169_REGS_SIZE 256
78 #define R8169_NAPI_WEIGHT 64
79 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
80 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
81 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
82 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
83 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
85 #define RTL8169_TX_TIMEOUT (6*HZ)
86 #define RTL8169_PHY_TIMEOUT (10*HZ)
88 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
89 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
90 #define RTL_EEPROM_SIG_ADDR 0x0000
92 /* write/read MMIO register */
93 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
94 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
95 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
96 #define RTL_R8(reg) readb (ioaddr + (reg))
97 #define RTL_R16(reg) readw (ioaddr + (reg))
98 #define RTL_R32(reg) readl (ioaddr + (reg))
101 RTL_GIGA_MAC_VER_01
= 0,
137 RTL_GIGA_MAC_NONE
= 0xff,
140 enum rtl_tx_desc_version
{
145 #define JUMBO_1K ETH_DATA_LEN
146 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
147 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
148 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
149 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
151 #define _R(NAME,TD,FW,SZ,B) { \
159 static const struct {
161 enum rtl_tx_desc_version txd_version
;
165 } rtl_chip_infos
[] = {
167 [RTL_GIGA_MAC_VER_01
] =
168 _R("RTL8169", RTL_TD_0
, NULL
, JUMBO_7K
, true),
169 [RTL_GIGA_MAC_VER_02
] =
170 _R("RTL8169s", RTL_TD_0
, NULL
, JUMBO_7K
, true),
171 [RTL_GIGA_MAC_VER_03
] =
172 _R("RTL8110s", RTL_TD_0
, NULL
, JUMBO_7K
, true),
173 [RTL_GIGA_MAC_VER_04
] =
174 _R("RTL8169sb/8110sb", RTL_TD_0
, NULL
, JUMBO_7K
, true),
175 [RTL_GIGA_MAC_VER_05
] =
176 _R("RTL8169sc/8110sc", RTL_TD_0
, NULL
, JUMBO_7K
, true),
177 [RTL_GIGA_MAC_VER_06
] =
178 _R("RTL8169sc/8110sc", RTL_TD_0
, NULL
, JUMBO_7K
, true),
180 [RTL_GIGA_MAC_VER_07
] =
181 _R("RTL8102e", RTL_TD_1
, NULL
, JUMBO_1K
, true),
182 [RTL_GIGA_MAC_VER_08
] =
183 _R("RTL8102e", RTL_TD_1
, NULL
, JUMBO_1K
, true),
184 [RTL_GIGA_MAC_VER_09
] =
185 _R("RTL8102e", RTL_TD_1
, NULL
, JUMBO_1K
, true),
186 [RTL_GIGA_MAC_VER_10
] =
187 _R("RTL8101e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
188 [RTL_GIGA_MAC_VER_11
] =
189 _R("RTL8168b/8111b", RTL_TD_0
, NULL
, JUMBO_4K
, false),
190 [RTL_GIGA_MAC_VER_12
] =
191 _R("RTL8168b/8111b", RTL_TD_0
, NULL
, JUMBO_4K
, false),
192 [RTL_GIGA_MAC_VER_13
] =
193 _R("RTL8101e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
194 [RTL_GIGA_MAC_VER_14
] =
195 _R("RTL8100e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
196 [RTL_GIGA_MAC_VER_15
] =
197 _R("RTL8100e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
198 [RTL_GIGA_MAC_VER_16
] =
199 _R("RTL8101e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
200 [RTL_GIGA_MAC_VER_17
] =
201 _R("RTL8168b/8111b", RTL_TD_1
, NULL
, JUMBO_4K
, false),
202 [RTL_GIGA_MAC_VER_18
] =
203 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
, JUMBO_6K
, false),
204 [RTL_GIGA_MAC_VER_19
] =
205 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
206 [RTL_GIGA_MAC_VER_20
] =
207 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
208 [RTL_GIGA_MAC_VER_21
] =
209 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
210 [RTL_GIGA_MAC_VER_22
] =
211 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
212 [RTL_GIGA_MAC_VER_23
] =
213 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
, JUMBO_6K
, false),
214 [RTL_GIGA_MAC_VER_24
] =
215 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
, JUMBO_6K
, false),
216 [RTL_GIGA_MAC_VER_25
] =
217 _R("RTL8168d/8111d", RTL_TD_1
, FIRMWARE_8168D_1
,
219 [RTL_GIGA_MAC_VER_26
] =
220 _R("RTL8168d/8111d", RTL_TD_1
, FIRMWARE_8168D_2
,
222 [RTL_GIGA_MAC_VER_27
] =
223 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
, JUMBO_9K
, false),
224 [RTL_GIGA_MAC_VER_28
] =
225 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
, JUMBO_9K
, false),
226 [RTL_GIGA_MAC_VER_29
] =
227 _R("RTL8105e", RTL_TD_1
, FIRMWARE_8105E_1
,
229 [RTL_GIGA_MAC_VER_30
] =
230 _R("RTL8105e", RTL_TD_1
, FIRMWARE_8105E_1
,
232 [RTL_GIGA_MAC_VER_31
] =
233 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
, JUMBO_9K
, false),
234 [RTL_GIGA_MAC_VER_32
] =
235 _R("RTL8168e/8111e", RTL_TD_1
, FIRMWARE_8168E_1
,
237 [RTL_GIGA_MAC_VER_33
] =
238 _R("RTL8168e/8111e", RTL_TD_1
, FIRMWARE_8168E_2
,
240 [RTL_GIGA_MAC_VER_34
] =
241 _R("RTL8168evl/8111evl",RTL_TD_1
, FIRMWARE_8168E_3
,
243 [RTL_GIGA_MAC_VER_35
] =
244 _R("RTL8168f/8111f", RTL_TD_1
, FIRMWARE_8168F_1
,
246 [RTL_GIGA_MAC_VER_36
] =
247 _R("RTL8168f/8111f", RTL_TD_1
, FIRMWARE_8168F_2
,
258 static void rtl_hw_start_8169(struct net_device
*);
259 static void rtl_hw_start_8168(struct net_device
*);
260 static void rtl_hw_start_8101(struct net_device
*);
262 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl
) = {
263 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
264 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
265 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
266 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
267 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
268 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
269 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4302), 0, 0, RTL_CFG_0
},
270 { PCI_DEVICE(PCI_VENDOR_ID_AT
, 0xc107), 0, 0, RTL_CFG_0
},
271 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
272 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
273 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
275 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
279 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
281 static int rx_buf_sz
= 16383;
288 MAC0
= 0, /* Ethernet hardware address. */
290 MAR0
= 8, /* Multicast filter. */
291 CounterAddrLow
= 0x10,
292 CounterAddrHigh
= 0x14,
293 TxDescStartAddrLow
= 0x20,
294 TxDescStartAddrHigh
= 0x24,
295 TxHDescStartAddrLow
= 0x28,
296 TxHDescStartAddrHigh
= 0x2c,
305 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
306 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
309 #define RX128_INT_EN (1 << 15) /* 8111c and later */
310 #define RX_MULTI_EN (1 << 14) /* 8111c only */
311 #define RXCFG_FIFO_SHIFT 13
312 /* No threshold before first PCI xfer */
313 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
314 #define RXCFG_DMA_SHIFT 8
315 /* Unlimited maximum PCI burst. */
316 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
332 RxDescAddrLow
= 0xe4,
333 RxDescAddrHigh
= 0xe8,
334 EarlyTxThres
= 0xec, /* 8169. Unit of 32 bytes. */
336 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
338 MaxTxPacketSize
= 0xec, /* 8101/8168. Unit of 128 bytes. */
340 #define TxPacketMax (8064 >> 7)
341 #define EarlySize 0x27
344 FuncEventMask
= 0xf4,
345 FuncPresetState
= 0xf8,
346 FuncForceEvent
= 0xfc,
349 enum rtl8110_registers
{
355 enum rtl8168_8101_registers
{
358 #define CSIAR_FLAG 0x80000000
359 #define CSIAR_WRITE_CMD 0x80000000
360 #define CSIAR_BYTE_ENABLE 0x0f
361 #define CSIAR_BYTE_ENABLE_SHIFT 12
362 #define CSIAR_ADDR_MASK 0x0fff
365 #define EPHYAR_FLAG 0x80000000
366 #define EPHYAR_WRITE_CMD 0x80000000
367 #define EPHYAR_REG_MASK 0x1f
368 #define EPHYAR_REG_SHIFT 16
369 #define EPHYAR_DATA_MASK 0xffff
371 #define PFM_EN (1 << 6)
373 #define FIX_NAK_1 (1 << 4)
374 #define FIX_NAK_2 (1 << 3)
377 #define NOW_IS_OOB (1 << 7)
378 #define EN_NDP (1 << 3)
379 #define EN_OOB_RESET (1 << 2)
381 #define EFUSEAR_FLAG 0x80000000
382 #define EFUSEAR_WRITE_CMD 0x80000000
383 #define EFUSEAR_READ_CMD 0x00000000
384 #define EFUSEAR_REG_MASK 0x03ff
385 #define EFUSEAR_REG_SHIFT 8
386 #define EFUSEAR_DATA_MASK 0xff
389 enum rtl8168_registers
{
394 #define ERIAR_FLAG 0x80000000
395 #define ERIAR_WRITE_CMD 0x80000000
396 #define ERIAR_READ_CMD 0x00000000
397 #define ERIAR_ADDR_BYTE_ALIGN 4
398 #define ERIAR_TYPE_SHIFT 16
399 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
400 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
401 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
402 #define ERIAR_MASK_SHIFT 12
403 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
404 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
405 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
406 EPHY_RXER_NUM
= 0x7c,
407 OCPDR
= 0xb0, /* OCP GPHY access */
408 #define OCPDR_WRITE_CMD 0x80000000
409 #define OCPDR_READ_CMD 0x00000000
410 #define OCPDR_REG_MASK 0x7f
411 #define OCPDR_GPHY_REG_SHIFT 16
412 #define OCPDR_DATA_MASK 0xffff
414 #define OCPAR_FLAG 0x80000000
415 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
416 #define OCPAR_GPHY_READ_CMD 0x0000f060
417 RDSAR1
= 0xd0, /* 8168c only. Undocumented on 8168dp */
418 MISC
= 0xf0, /* 8168e only. */
419 #define TXPLA_RST (1 << 29)
420 #define PWM_EN (1 << 22)
423 enum rtl_register_content
{
424 /* InterruptStatusBits */
428 TxDescUnavail
= 0x0080,
452 /* TXPoll register p.5 */
453 HPQ
= 0x80, /* Poll cmd on the high prio queue */
454 NPQ
= 0x40, /* Poll cmd on the low prio queue */
455 FSWInt
= 0x01, /* Forced software interrupt */
459 Cfg9346_Unlock
= 0xc0,
464 AcceptBroadcast
= 0x08,
465 AcceptMulticast
= 0x04,
467 AcceptAllPhys
= 0x01,
468 #define RX_CONFIG_ACCEPT_MASK 0x3f
471 TxInterFrameGapShift
= 24,
472 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
474 /* Config1 register p.24 */
477 Speed_down
= (1 << 4),
481 PMEnable
= (1 << 0), /* Power Management Enable */
483 /* Config2 register p. 25 */
484 MSIEnable
= (1 << 5), /* 8169 only. Reserved in the 8168. */
485 PCI_Clock_66MHz
= 0x01,
486 PCI_Clock_33MHz
= 0x00,
488 /* Config3 register p.25 */
489 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
490 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
491 Jumbo_En0
= (1 << 2), /* 8168 only. Reserved in the 8168b */
492 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
494 /* Config4 register */
495 Jumbo_En1
= (1 << 1), /* 8168 only. Reserved in the 8168b */
497 /* Config5 register p.27 */
498 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
499 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
500 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
502 LanWake
= (1 << 1), /* LanWake enable/disable */
503 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
506 TBIReset
= 0x80000000,
507 TBILoopback
= 0x40000000,
508 TBINwEnable
= 0x20000000,
509 TBINwRestart
= 0x10000000,
510 TBILinkOk
= 0x02000000,
511 TBINwComplete
= 0x01000000,
514 EnableBist
= (1 << 15), // 8168 8101
515 Mac_dbgo_oe
= (1 << 14), // 8168 8101
516 Normal_mode
= (1 << 13), // unused
517 Force_half_dup
= (1 << 12), // 8168 8101
518 Force_rxflow_en
= (1 << 11), // 8168 8101
519 Force_txflow_en
= (1 << 10), // 8168 8101
520 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
521 ASF
= (1 << 8), // 8168 8101
522 PktCntrDisable
= (1 << 7), // 8168 8101
523 Mac_dbgo_sel
= 0x001c, // 8168
528 INTT_0
= 0x0000, // 8168
529 INTT_1
= 0x0001, // 8168
530 INTT_2
= 0x0002, // 8168
531 INTT_3
= 0x0003, // 8168
533 /* rtl8169_PHYstatus */
544 TBILinkOK
= 0x02000000,
546 /* DumpCounterCommand */
551 /* First doubleword. */
552 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
553 RingEnd
= (1 << 30), /* End of descriptor ring */
554 FirstFrag
= (1 << 29), /* First segment of a packet */
555 LastFrag
= (1 << 28), /* Final segment of a packet */
559 enum rtl_tx_desc_bit
{
560 /* First doubleword. */
561 TD_LSO
= (1 << 27), /* Large Send Offload */
562 #define TD_MSS_MAX 0x07ffu /* MSS value */
564 /* Second doubleword. */
565 TxVlanTag
= (1 << 17), /* Add VLAN tag */
568 /* 8169, 8168b and 810x except 8102e. */
569 enum rtl_tx_desc_bit_0
{
570 /* First doubleword. */
571 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
572 TD0_TCP_CS
= (1 << 16), /* Calculate TCP/IP checksum */
573 TD0_UDP_CS
= (1 << 17), /* Calculate UDP/IP checksum */
574 TD0_IP_CS
= (1 << 18), /* Calculate IP checksum */
577 /* 8102e, 8168c and beyond. */
578 enum rtl_tx_desc_bit_1
{
579 /* Second doubleword. */
580 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
581 TD1_IP_CS
= (1 << 29), /* Calculate IP checksum */
582 TD1_TCP_CS
= (1 << 30), /* Calculate TCP/IP checksum */
583 TD1_UDP_CS
= (1 << 31), /* Calculate UDP/IP checksum */
586 static const struct rtl_tx_desc_info
{
593 } tx_desc_info
[] = {
596 .udp
= TD0_IP_CS
| TD0_UDP_CS
,
597 .tcp
= TD0_IP_CS
| TD0_TCP_CS
599 .mss_shift
= TD0_MSS_SHIFT
,
604 .udp
= TD1_IP_CS
| TD1_UDP_CS
,
605 .tcp
= TD1_IP_CS
| TD1_TCP_CS
607 .mss_shift
= TD1_MSS_SHIFT
,
612 enum rtl_rx_desc_bit
{
614 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
615 PID0
= (1 << 17), /* Protocol ID bit 2/2 */
617 #define RxProtoUDP (PID1)
618 #define RxProtoTCP (PID0)
619 #define RxProtoIP (PID1 | PID0)
620 #define RxProtoMask RxProtoIP
622 IPFail
= (1 << 16), /* IP checksum failed */
623 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
624 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
625 RxVlanTag
= (1 << 16), /* VLAN tag available */
628 #define RsvdMask 0x3fffc000
645 u8 __pad
[sizeof(void *) - sizeof(u32
)];
649 RTL_FEATURE_WOL
= (1 << 0),
650 RTL_FEATURE_MSI
= (1 << 1),
651 RTL_FEATURE_GMII
= (1 << 2),
654 struct rtl8169_counters
{
661 __le32 tx_one_collision
;
662 __le32 tx_multi_collision
;
671 RTL_FLAG_TASK_ENABLED
,
672 RTL_FLAG_TASK_SLOW_PENDING
,
673 RTL_FLAG_TASK_RESET_PENDING
,
674 RTL_FLAG_TASK_PHY_PENDING
,
678 struct rtl8169_private
{
679 void __iomem
*mmio_addr
; /* memory map physical address */
680 struct pci_dev
*pci_dev
;
681 struct net_device
*dev
;
682 struct napi_struct napi
;
686 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
687 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
690 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
691 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
692 dma_addr_t TxPhyAddr
;
693 dma_addr_t RxPhyAddr
;
694 void *Rx_databuff
[NUM_RX_DESC
]; /* Rx data buffers */
695 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
696 struct timer_list timer
;
702 void (*write
)(void __iomem
*, int, int);
703 int (*read
)(void __iomem
*, int);
706 struct pll_power_ops
{
707 void (*down
)(struct rtl8169_private
*);
708 void (*up
)(struct rtl8169_private
*);
712 void (*enable
)(struct rtl8169_private
*);
713 void (*disable
)(struct rtl8169_private
*);
716 int (*set_speed
)(struct net_device
*, u8 aneg
, u16 sp
, u8 dpx
, u32 adv
);
717 int (*get_settings
)(struct net_device
*, struct ethtool_cmd
*);
718 void (*phy_reset_enable
)(struct rtl8169_private
*tp
);
719 void (*hw_start
)(struct net_device
*);
720 unsigned int (*phy_reset_pending
)(struct rtl8169_private
*tp
);
721 unsigned int (*link_ok
)(void __iomem
*);
722 int (*do_ioctl
)(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
);
725 DECLARE_BITMAP(flags
, RTL_FLAG_MAX
);
727 struct work_struct work
;
732 struct mii_if_info mii
;
733 struct rtl8169_counters counters
;
738 const struct firmware
*fw
;
740 #define RTL_VER_SIZE 32
742 char version
[RTL_VER_SIZE
];
744 struct rtl_fw_phy_action
{
749 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
752 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
753 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
754 module_param(use_dac
, int, 0);
755 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
756 module_param_named(debug
, debug
.msg_enable
, int, 0);
757 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
758 MODULE_LICENSE("GPL");
759 MODULE_VERSION(RTL8169_VERSION
);
760 MODULE_FIRMWARE(FIRMWARE_8168D_1
);
761 MODULE_FIRMWARE(FIRMWARE_8168D_2
);
762 MODULE_FIRMWARE(FIRMWARE_8168E_1
);
763 MODULE_FIRMWARE(FIRMWARE_8168E_2
);
764 MODULE_FIRMWARE(FIRMWARE_8168E_3
);
765 MODULE_FIRMWARE(FIRMWARE_8105E_1
);
766 MODULE_FIRMWARE(FIRMWARE_8168F_1
);
767 MODULE_FIRMWARE(FIRMWARE_8168F_2
);
769 static int rtl8169_open(struct net_device
*dev
);
770 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
771 struct net_device
*dev
);
772 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
);
773 static int rtl8169_init_ring(struct net_device
*dev
);
774 static void rtl_hw_start(struct net_device
*dev
);
775 static int rtl8169_close(struct net_device
*dev
);
776 static void rtl_set_rx_mode(struct net_device
*dev
);
777 static void rtl8169_tx_timeout(struct net_device
*dev
);
778 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
);
779 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
);
780 static void rtl8169_rx_clear(struct rtl8169_private
*tp
);
781 static int rtl8169_poll(struct napi_struct
*napi
, int budget
);
783 static void rtl_lock_work(struct rtl8169_private
*tp
)
785 mutex_lock(&tp
->wk
.mutex
);
788 static void rtl_unlock_work(struct rtl8169_private
*tp
)
790 mutex_unlock(&tp
->wk
.mutex
);
793 static void rtl_tx_performance_tweak(struct pci_dev
*pdev
, u16 force
)
795 int cap
= pci_pcie_cap(pdev
);
800 pci_read_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
801 ctl
= (ctl
& ~PCI_EXP_DEVCTL_READRQ
) | force
;
802 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
806 static u32
ocp_read(struct rtl8169_private
*tp
, u8 mask
, u16 reg
)
808 void __iomem
*ioaddr
= tp
->mmio_addr
;
811 RTL_W32(OCPAR
, ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
812 for (i
= 0; i
< 20; i
++) {
814 if (RTL_R32(OCPAR
) & OCPAR_FLAG
)
817 return RTL_R32(OCPDR
);
820 static void ocp_write(struct rtl8169_private
*tp
, u8 mask
, u16 reg
, u32 data
)
822 void __iomem
*ioaddr
= tp
->mmio_addr
;
825 RTL_W32(OCPDR
, data
);
826 RTL_W32(OCPAR
, OCPAR_FLAG
| ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
827 for (i
= 0; i
< 20; i
++) {
829 if ((RTL_R32(OCPAR
) & OCPAR_FLAG
) == 0)
834 static void rtl8168_oob_notify(struct rtl8169_private
*tp
, u8 cmd
)
836 void __iomem
*ioaddr
= tp
->mmio_addr
;
840 RTL_W32(ERIAR
, 0x800010e8);
842 for (i
= 0; i
< 5; i
++) {
844 if (!(RTL_R32(ERIAR
) & ERIAR_FLAG
))
848 ocp_write(tp
, 0x1, 0x30, 0x00000001);
851 #define OOB_CMD_RESET 0x00
852 #define OOB_CMD_DRIVER_START 0x05
853 #define OOB_CMD_DRIVER_STOP 0x06
855 static u16
rtl8168_get_ocp_reg(struct rtl8169_private
*tp
)
857 return (tp
->mac_version
== RTL_GIGA_MAC_VER_31
) ? 0xb8 : 0x10;
860 static void rtl8168_driver_start(struct rtl8169_private
*tp
)
865 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_START
);
867 reg
= rtl8168_get_ocp_reg(tp
);
869 for (i
= 0; i
< 10; i
++) {
871 if (ocp_read(tp
, 0x0f, reg
) & 0x00000800)
876 static void rtl8168_driver_stop(struct rtl8169_private
*tp
)
881 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_STOP
);
883 reg
= rtl8168_get_ocp_reg(tp
);
885 for (i
= 0; i
< 10; i
++) {
887 if ((ocp_read(tp
, 0x0f, reg
) & 0x00000800) == 0)
892 static int r8168dp_check_dash(struct rtl8169_private
*tp
)
894 u16 reg
= rtl8168_get_ocp_reg(tp
);
896 return (ocp_read(tp
, 0x0f, reg
) & 0x00008000) ? 1 : 0;
899 static void r8169_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
903 RTL_W32(PHYAR
, 0x80000000 | (reg_addr
& 0x1f) << 16 | (value
& 0xffff));
905 for (i
= 20; i
> 0; i
--) {
907 * Check if the RTL8169 has completed writing to the specified
910 if (!(RTL_R32(PHYAR
) & 0x80000000))
915 * According to hardware specs a 20us delay is required after write
916 * complete indication, but before sending next command.
921 static int r8169_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
925 RTL_W32(PHYAR
, 0x0 | (reg_addr
& 0x1f) << 16);
927 for (i
= 20; i
> 0; i
--) {
929 * Check if the RTL8169 has completed retrieving data from
930 * the specified MII register.
932 if (RTL_R32(PHYAR
) & 0x80000000) {
933 value
= RTL_R32(PHYAR
) & 0xffff;
939 * According to hardware specs a 20us delay is required after read
940 * complete indication, but before sending next command.
947 static void r8168dp_1_mdio_access(void __iomem
*ioaddr
, int reg_addr
, u32 data
)
951 RTL_W32(OCPDR
, data
|
952 ((reg_addr
& OCPDR_REG_MASK
) << OCPDR_GPHY_REG_SHIFT
));
953 RTL_W32(OCPAR
, OCPAR_GPHY_WRITE_CMD
);
954 RTL_W32(EPHY_RXER_NUM
, 0);
956 for (i
= 0; i
< 100; i
++) {
958 if (!(RTL_R32(OCPAR
) & OCPAR_FLAG
))
963 static void r8168dp_1_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
965 r8168dp_1_mdio_access(ioaddr
, reg_addr
, OCPDR_WRITE_CMD
|
966 (value
& OCPDR_DATA_MASK
));
969 static int r8168dp_1_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
973 r8168dp_1_mdio_access(ioaddr
, reg_addr
, OCPDR_READ_CMD
);
976 RTL_W32(OCPAR
, OCPAR_GPHY_READ_CMD
);
977 RTL_W32(EPHY_RXER_NUM
, 0);
979 for (i
= 0; i
< 100; i
++) {
981 if (RTL_R32(OCPAR
) & OCPAR_FLAG
)
985 return RTL_R32(OCPDR
) & OCPDR_DATA_MASK
;
988 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
990 static void r8168dp_2_mdio_start(void __iomem
*ioaddr
)
992 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT
);
995 static void r8168dp_2_mdio_stop(void __iomem
*ioaddr
)
997 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT
);
1000 static void r8168dp_2_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
1002 r8168dp_2_mdio_start(ioaddr
);
1004 r8169_mdio_write(ioaddr
, reg_addr
, value
);
1006 r8168dp_2_mdio_stop(ioaddr
);
1009 static int r8168dp_2_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
1013 r8168dp_2_mdio_start(ioaddr
);
1015 value
= r8169_mdio_read(ioaddr
, reg_addr
);
1017 r8168dp_2_mdio_stop(ioaddr
);
1022 static void rtl_writephy(struct rtl8169_private
*tp
, int location
, u32 val
)
1024 tp
->mdio_ops
.write(tp
->mmio_addr
, location
, val
);
1027 static int rtl_readphy(struct rtl8169_private
*tp
, int location
)
1029 return tp
->mdio_ops
.read(tp
->mmio_addr
, location
);
1032 static void rtl_patchphy(struct rtl8169_private
*tp
, int reg_addr
, int value
)
1034 rtl_writephy(tp
, reg_addr
, rtl_readphy(tp
, reg_addr
) | value
);
1037 static void rtl_w1w0_phy(struct rtl8169_private
*tp
, int reg_addr
, int p
, int m
)
1041 val
= rtl_readphy(tp
, reg_addr
);
1042 rtl_writephy(tp
, reg_addr
, (val
| p
) & ~m
);
1045 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
1048 struct rtl8169_private
*tp
= netdev_priv(dev
);
1050 rtl_writephy(tp
, location
, val
);
1053 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
1055 struct rtl8169_private
*tp
= netdev_priv(dev
);
1057 return rtl_readphy(tp
, location
);
1060 static void rtl_ephy_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
1064 RTL_W32(EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
1065 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
1067 for (i
= 0; i
< 100; i
++) {
1068 if (!(RTL_R32(EPHYAR
) & EPHYAR_FLAG
))
1074 static u16
rtl_ephy_read(void __iomem
*ioaddr
, int reg_addr
)
1079 RTL_W32(EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
1081 for (i
= 0; i
< 100; i
++) {
1082 if (RTL_R32(EPHYAR
) & EPHYAR_FLAG
) {
1083 value
= RTL_R32(EPHYAR
) & EPHYAR_DATA_MASK
;
1092 static void rtl_csi_write(void __iomem
*ioaddr
, int addr
, int value
)
1096 RTL_W32(CSIDR
, value
);
1097 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
1098 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
1100 for (i
= 0; i
< 100; i
++) {
1101 if (!(RTL_R32(CSIAR
) & CSIAR_FLAG
))
1107 static u32
rtl_csi_read(void __iomem
*ioaddr
, int addr
)
1112 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) |
1113 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
1115 for (i
= 0; i
< 100; i
++) {
1116 if (RTL_R32(CSIAR
) & CSIAR_FLAG
) {
1117 value
= RTL_R32(CSIDR
);
1127 void rtl_eri_write(void __iomem
*ioaddr
, int addr
, u32 mask
, u32 val
, int type
)
1131 BUG_ON((addr
& 3) || (mask
== 0));
1132 RTL_W32(ERIDR
, val
);
1133 RTL_W32(ERIAR
, ERIAR_WRITE_CMD
| type
| mask
| addr
);
1135 for (i
= 0; i
< 100; i
++) {
1136 if (!(RTL_R32(ERIAR
) & ERIAR_FLAG
))
1142 static u32
rtl_eri_read(void __iomem
*ioaddr
, int addr
, int type
)
1147 RTL_W32(ERIAR
, ERIAR_READ_CMD
| type
| ERIAR_MASK_1111
| addr
);
1149 for (i
= 0; i
< 100; i
++) {
1150 if (RTL_R32(ERIAR
) & ERIAR_FLAG
) {
1151 value
= RTL_R32(ERIDR
);
1161 rtl_w1w0_eri(void __iomem
*ioaddr
, int addr
, u32 mask
, u32 p
, u32 m
, int type
)
1165 val
= rtl_eri_read(ioaddr
, addr
, type
);
1166 rtl_eri_write(ioaddr
, addr
, mask
, (val
& ~m
) | p
, type
);
1175 static void rtl_write_exgmac_batch(void __iomem
*ioaddr
,
1176 const struct exgmac_reg
*r
, int len
)
1179 rtl_eri_write(ioaddr
, r
->addr
, r
->mask
, r
->val
, ERIAR_EXGMAC
);
1184 static u8
rtl8168d_efuse_read(void __iomem
*ioaddr
, int reg_addr
)
1189 RTL_W32(EFUSEAR
, (reg_addr
& EFUSEAR_REG_MASK
) << EFUSEAR_REG_SHIFT
);
1191 for (i
= 0; i
< 300; i
++) {
1192 if (RTL_R32(EFUSEAR
) & EFUSEAR_FLAG
) {
1193 value
= RTL_R32(EFUSEAR
) & EFUSEAR_DATA_MASK
;
1202 static u16
rtl_get_events(struct rtl8169_private
*tp
)
1204 void __iomem
*ioaddr
= tp
->mmio_addr
;
1206 return RTL_R16(IntrStatus
);
1209 static void rtl_ack_events(struct rtl8169_private
*tp
, u16 bits
)
1211 void __iomem
*ioaddr
= tp
->mmio_addr
;
1213 RTL_W16(IntrStatus
, bits
);
1217 static void rtl_irq_disable(struct rtl8169_private
*tp
)
1219 void __iomem
*ioaddr
= tp
->mmio_addr
;
1221 RTL_W16(IntrMask
, 0);
1225 static void rtl_irq_enable(struct rtl8169_private
*tp
, u16 bits
)
1227 void __iomem
*ioaddr
= tp
->mmio_addr
;
1229 RTL_W16(IntrMask
, bits
);
1232 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1233 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1234 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1236 static void rtl_irq_enable_all(struct rtl8169_private
*tp
)
1238 rtl_irq_enable(tp
, RTL_EVENT_NAPI
| tp
->event_slow
);
1241 static void rtl8169_irq_mask_and_ack(struct rtl8169_private
*tp
)
1243 void __iomem
*ioaddr
= tp
->mmio_addr
;
1245 rtl_irq_disable(tp
);
1246 rtl_ack_events(tp
, RTL_EVENT_NAPI
| tp
->event_slow
);
1250 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private
*tp
)
1252 void __iomem
*ioaddr
= tp
->mmio_addr
;
1254 return RTL_R32(TBICSR
) & TBIReset
;
1257 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private
*tp
)
1259 return rtl_readphy(tp
, MII_BMCR
) & BMCR_RESET
;
1262 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
1264 return RTL_R32(TBICSR
) & TBILinkOk
;
1267 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
1269 return RTL_R8(PHYstatus
) & LinkStatus
;
1272 static void rtl8169_tbi_reset_enable(struct rtl8169_private
*tp
)
1274 void __iomem
*ioaddr
= tp
->mmio_addr
;
1276 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
1279 static void rtl8169_xmii_reset_enable(struct rtl8169_private
*tp
)
1283 val
= rtl_readphy(tp
, MII_BMCR
) | BMCR_RESET
;
1284 rtl_writephy(tp
, MII_BMCR
, val
& 0xffff);
1287 static void rtl_link_chg_patch(struct rtl8169_private
*tp
)
1289 void __iomem
*ioaddr
= tp
->mmio_addr
;
1290 struct net_device
*dev
= tp
->dev
;
1292 if (!netif_running(dev
))
1295 if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
) {
1296 if (RTL_R8(PHYstatus
) & _1000bpsF
) {
1297 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1298 0x00000011, ERIAR_EXGMAC
);
1299 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1300 0x00000005, ERIAR_EXGMAC
);
1301 } else if (RTL_R8(PHYstatus
) & _100bps
) {
1302 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1303 0x0000001f, ERIAR_EXGMAC
);
1304 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1305 0x00000005, ERIAR_EXGMAC
);
1307 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1308 0x0000001f, ERIAR_EXGMAC
);
1309 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1310 0x0000003f, ERIAR_EXGMAC
);
1312 /* Reset packet filter */
1313 rtl_w1w0_eri(ioaddr
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01,
1315 rtl_w1w0_eri(ioaddr
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00,
1317 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_35
||
1318 tp
->mac_version
== RTL_GIGA_MAC_VER_36
) {
1319 if (RTL_R8(PHYstatus
) & _1000bpsF
) {
1320 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1321 0x00000011, ERIAR_EXGMAC
);
1322 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1323 0x00000005, ERIAR_EXGMAC
);
1325 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1326 0x0000001f, ERIAR_EXGMAC
);
1327 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1328 0x0000003f, ERIAR_EXGMAC
);
1333 static void __rtl8169_check_link_status(struct net_device
*dev
,
1334 struct rtl8169_private
*tp
,
1335 void __iomem
*ioaddr
, bool pm
)
1337 if (tp
->link_ok(ioaddr
)) {
1338 rtl_link_chg_patch(tp
);
1339 /* This is to cancel a scheduled suspend if there's one. */
1341 pm_request_resume(&tp
->pci_dev
->dev
);
1342 netif_carrier_on(dev
);
1343 if (net_ratelimit())
1344 netif_info(tp
, ifup
, dev
, "link up\n");
1346 netif_carrier_off(dev
);
1347 netif_info(tp
, ifdown
, dev
, "link down\n");
1349 pm_schedule_suspend(&tp
->pci_dev
->dev
, 5000);
1353 static void rtl8169_check_link_status(struct net_device
*dev
,
1354 struct rtl8169_private
*tp
,
1355 void __iomem
*ioaddr
)
1357 __rtl8169_check_link_status(dev
, tp
, ioaddr
, false);
1360 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1362 static u32
__rtl8169_get_wol(struct rtl8169_private
*tp
)
1364 void __iomem
*ioaddr
= tp
->mmio_addr
;
1368 options
= RTL_R8(Config1
);
1369 if (!(options
& PMEnable
))
1372 options
= RTL_R8(Config3
);
1373 if (options
& LinkUp
)
1374 wolopts
|= WAKE_PHY
;
1375 if (options
& MagicPacket
)
1376 wolopts
|= WAKE_MAGIC
;
1378 options
= RTL_R8(Config5
);
1380 wolopts
|= WAKE_UCAST
;
1382 wolopts
|= WAKE_BCAST
;
1384 wolopts
|= WAKE_MCAST
;
1389 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1391 struct rtl8169_private
*tp
= netdev_priv(dev
);
1395 wol
->supported
= WAKE_ANY
;
1396 wol
->wolopts
= __rtl8169_get_wol(tp
);
1398 rtl_unlock_work(tp
);
1401 static void __rtl8169_set_wol(struct rtl8169_private
*tp
, u32 wolopts
)
1403 void __iomem
*ioaddr
= tp
->mmio_addr
;
1405 static const struct {
1410 { WAKE_ANY
, Config1
, PMEnable
},
1411 { WAKE_PHY
, Config3
, LinkUp
},
1412 { WAKE_MAGIC
, Config3
, MagicPacket
},
1413 { WAKE_UCAST
, Config5
, UWF
},
1414 { WAKE_BCAST
, Config5
, BWF
},
1415 { WAKE_MCAST
, Config5
, MWF
},
1416 { WAKE_ANY
, Config5
, LanWake
}
1419 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1421 for (i
= 0; i
< ARRAY_SIZE(cfg
); i
++) {
1422 u8 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
1423 if (wolopts
& cfg
[i
].opt
)
1424 options
|= cfg
[i
].mask
;
1425 RTL_W8(cfg
[i
].reg
, options
);
1428 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1431 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1433 struct rtl8169_private
*tp
= netdev_priv(dev
);
1438 tp
->features
|= RTL_FEATURE_WOL
;
1440 tp
->features
&= ~RTL_FEATURE_WOL
;
1441 __rtl8169_set_wol(tp
, wol
->wolopts
);
1443 rtl_unlock_work(tp
);
1445 device_set_wakeup_enable(&tp
->pci_dev
->dev
, wol
->wolopts
);
1450 static const char *rtl_lookup_firmware_name(struct rtl8169_private
*tp
)
1452 return rtl_chip_infos
[tp
->mac_version
].fw_name
;
1455 static void rtl8169_get_drvinfo(struct net_device
*dev
,
1456 struct ethtool_drvinfo
*info
)
1458 struct rtl8169_private
*tp
= netdev_priv(dev
);
1459 struct rtl_fw
*rtl_fw
= tp
->rtl_fw
;
1461 strlcpy(info
->driver
, MODULENAME
, sizeof(info
->driver
));
1462 strlcpy(info
->version
, RTL8169_VERSION
, sizeof(info
->version
));
1463 strlcpy(info
->bus_info
, pci_name(tp
->pci_dev
), sizeof(info
->bus_info
));
1464 BUILD_BUG_ON(sizeof(info
->fw_version
) < sizeof(rtl_fw
->version
));
1465 if (!IS_ERR_OR_NULL(rtl_fw
))
1466 strlcpy(info
->fw_version
, rtl_fw
->version
,
1467 sizeof(info
->fw_version
));
1470 static int rtl8169_get_regs_len(struct net_device
*dev
)
1472 return R8169_REGS_SIZE
;
1475 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
1476 u8 autoneg
, u16 speed
, u8 duplex
, u32 ignored
)
1478 struct rtl8169_private
*tp
= netdev_priv(dev
);
1479 void __iomem
*ioaddr
= tp
->mmio_addr
;
1483 reg
= RTL_R32(TBICSR
);
1484 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
1485 (duplex
== DUPLEX_FULL
)) {
1486 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
1487 } else if (autoneg
== AUTONEG_ENABLE
)
1488 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
1490 netif_warn(tp
, link
, dev
,
1491 "incorrect speed setting refused in TBI mode\n");
1498 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
1499 u8 autoneg
, u16 speed
, u8 duplex
, u32 adv
)
1501 struct rtl8169_private
*tp
= netdev_priv(dev
);
1502 int giga_ctrl
, bmcr
;
1505 rtl_writephy(tp
, 0x1f, 0x0000);
1507 if (autoneg
== AUTONEG_ENABLE
) {
1510 auto_nego
= rtl_readphy(tp
, MII_ADVERTISE
);
1511 auto_nego
&= ~(ADVERTISE_10HALF
| ADVERTISE_10FULL
|
1512 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
1514 if (adv
& ADVERTISED_10baseT_Half
)
1515 auto_nego
|= ADVERTISE_10HALF
;
1516 if (adv
& ADVERTISED_10baseT_Full
)
1517 auto_nego
|= ADVERTISE_10FULL
;
1518 if (adv
& ADVERTISED_100baseT_Half
)
1519 auto_nego
|= ADVERTISE_100HALF
;
1520 if (adv
& ADVERTISED_100baseT_Full
)
1521 auto_nego
|= ADVERTISE_100FULL
;
1523 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
1525 giga_ctrl
= rtl_readphy(tp
, MII_CTRL1000
);
1526 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
1528 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1529 if (tp
->mii
.supports_gmii
) {
1530 if (adv
& ADVERTISED_1000baseT_Half
)
1531 giga_ctrl
|= ADVERTISE_1000HALF
;
1532 if (adv
& ADVERTISED_1000baseT_Full
)
1533 giga_ctrl
|= ADVERTISE_1000FULL
;
1534 } else if (adv
& (ADVERTISED_1000baseT_Half
|
1535 ADVERTISED_1000baseT_Full
)) {
1536 netif_info(tp
, link
, dev
,
1537 "PHY does not support 1000Mbps\n");
1541 bmcr
= BMCR_ANENABLE
| BMCR_ANRESTART
;
1543 rtl_writephy(tp
, MII_ADVERTISE
, auto_nego
);
1544 rtl_writephy(tp
, MII_CTRL1000
, giga_ctrl
);
1548 if (speed
== SPEED_10
)
1550 else if (speed
== SPEED_100
)
1551 bmcr
= BMCR_SPEED100
;
1555 if (duplex
== DUPLEX_FULL
)
1556 bmcr
|= BMCR_FULLDPLX
;
1559 rtl_writephy(tp
, MII_BMCR
, bmcr
);
1561 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
1562 tp
->mac_version
== RTL_GIGA_MAC_VER_03
) {
1563 if ((speed
== SPEED_100
) && (autoneg
!= AUTONEG_ENABLE
)) {
1564 rtl_writephy(tp
, 0x17, 0x2138);
1565 rtl_writephy(tp
, 0x0e, 0x0260);
1567 rtl_writephy(tp
, 0x17, 0x2108);
1568 rtl_writephy(tp
, 0x0e, 0x0000);
1577 static int rtl8169_set_speed(struct net_device
*dev
,
1578 u8 autoneg
, u16 speed
, u8 duplex
, u32 advertising
)
1580 struct rtl8169_private
*tp
= netdev_priv(dev
);
1583 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
, advertising
);
1587 if (netif_running(dev
) && (autoneg
== AUTONEG_ENABLE
) &&
1588 (advertising
& ADVERTISED_1000baseT_Full
)) {
1589 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
1595 static int rtl8169_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1597 struct rtl8169_private
*tp
= netdev_priv(dev
);
1600 del_timer_sync(&tp
->timer
);
1603 ret
= rtl8169_set_speed(dev
, cmd
->autoneg
, ethtool_cmd_speed(cmd
),
1604 cmd
->duplex
, cmd
->advertising
);
1605 rtl_unlock_work(tp
);
1610 static netdev_features_t
rtl8169_fix_features(struct net_device
*dev
,
1611 netdev_features_t features
)
1613 struct rtl8169_private
*tp
= netdev_priv(dev
);
1615 if (dev
->mtu
> TD_MSS_MAX
)
1616 features
&= ~NETIF_F_ALL_TSO
;
1618 if (dev
->mtu
> JUMBO_1K
&&
1619 !rtl_chip_infos
[tp
->mac_version
].jumbo_tx_csum
)
1620 features
&= ~NETIF_F_IP_CSUM
;
1625 static void __rtl8169_set_features(struct net_device
*dev
,
1626 netdev_features_t features
)
1628 struct rtl8169_private
*tp
= netdev_priv(dev
);
1630 void __iomem
*ioaddr
= tp
->mmio_addr
;
1632 if (features
& NETIF_F_RXCSUM
)
1633 tp
->cp_cmd
|= RxChkSum
;
1635 tp
->cp_cmd
&= ~RxChkSum
;
1637 if (dev
->features
& NETIF_F_HW_VLAN_RX
)
1638 tp
->cp_cmd
|= RxVlan
;
1640 tp
->cp_cmd
&= ~RxVlan
;
1642 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
1646 static int rtl8169_set_features(struct net_device
*dev
,
1647 netdev_features_t features
)
1649 struct rtl8169_private
*tp
= netdev_priv(dev
);
1652 __rtl8169_set_features(dev
, features
);
1653 rtl_unlock_work(tp
);
1659 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
1660 struct sk_buff
*skb
)
1662 return (vlan_tx_tag_present(skb
)) ?
1663 TxVlanTag
| swab16(vlan_tx_tag_get(skb
)) : 0x00;
1666 static void rtl8169_rx_vlan_tag(struct RxDesc
*desc
, struct sk_buff
*skb
)
1668 u32 opts2
= le32_to_cpu(desc
->opts2
);
1670 if (opts2
& RxVlanTag
)
1671 __vlan_hwaccel_put_tag(skb
, swab16(opts2
& 0xffff));
1676 static int rtl8169_gset_tbi(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1678 struct rtl8169_private
*tp
= netdev_priv(dev
);
1679 void __iomem
*ioaddr
= tp
->mmio_addr
;
1683 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
1684 cmd
->port
= PORT_FIBRE
;
1685 cmd
->transceiver
= XCVR_INTERNAL
;
1687 status
= RTL_R32(TBICSR
);
1688 cmd
->advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
1689 cmd
->autoneg
= !!(status
& TBINwEnable
);
1691 ethtool_cmd_speed_set(cmd
, SPEED_1000
);
1692 cmd
->duplex
= DUPLEX_FULL
; /* Always set */
1697 static int rtl8169_gset_xmii(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1699 struct rtl8169_private
*tp
= netdev_priv(dev
);
1701 return mii_ethtool_gset(&tp
->mii
, cmd
);
1704 static int rtl8169_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1706 struct rtl8169_private
*tp
= netdev_priv(dev
);
1710 rc
= tp
->get_settings(dev
, cmd
);
1711 rtl_unlock_work(tp
);
1716 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1719 struct rtl8169_private
*tp
= netdev_priv(dev
);
1721 if (regs
->len
> R8169_REGS_SIZE
)
1722 regs
->len
= R8169_REGS_SIZE
;
1725 memcpy_fromio(p
, tp
->mmio_addr
, regs
->len
);
1726 rtl_unlock_work(tp
);
1729 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
1731 struct rtl8169_private
*tp
= netdev_priv(dev
);
1733 return tp
->msg_enable
;
1736 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
1738 struct rtl8169_private
*tp
= netdev_priv(dev
);
1740 tp
->msg_enable
= value
;
1743 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
1750 "tx_single_collisions",
1751 "tx_multi_collisions",
1759 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
1763 return ARRAY_SIZE(rtl8169_gstrings
);
1769 static void rtl8169_update_counters(struct net_device
*dev
)
1771 struct rtl8169_private
*tp
= netdev_priv(dev
);
1772 void __iomem
*ioaddr
= tp
->mmio_addr
;
1773 struct device
*d
= &tp
->pci_dev
->dev
;
1774 struct rtl8169_counters
*counters
;
1780 * Some chips are unable to dump tally counters when the receiver
1783 if ((RTL_R8(ChipCmd
) & CmdRxEnb
) == 0)
1786 counters
= dma_alloc_coherent(d
, sizeof(*counters
), &paddr
, GFP_KERNEL
);
1790 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
1791 cmd
= (u64
)paddr
& DMA_BIT_MASK(32);
1792 RTL_W32(CounterAddrLow
, cmd
);
1793 RTL_W32(CounterAddrLow
, cmd
| CounterDump
);
1796 if ((RTL_R32(CounterAddrLow
) & CounterDump
) == 0) {
1797 memcpy(&tp
->counters
, counters
, sizeof(*counters
));
1803 RTL_W32(CounterAddrLow
, 0);
1804 RTL_W32(CounterAddrHigh
, 0);
1806 dma_free_coherent(d
, sizeof(*counters
), counters
, paddr
);
1809 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
1810 struct ethtool_stats
*stats
, u64
*data
)
1812 struct rtl8169_private
*tp
= netdev_priv(dev
);
1816 rtl8169_update_counters(dev
);
1818 data
[0] = le64_to_cpu(tp
->counters
.tx_packets
);
1819 data
[1] = le64_to_cpu(tp
->counters
.rx_packets
);
1820 data
[2] = le64_to_cpu(tp
->counters
.tx_errors
);
1821 data
[3] = le32_to_cpu(tp
->counters
.rx_errors
);
1822 data
[4] = le16_to_cpu(tp
->counters
.rx_missed
);
1823 data
[5] = le16_to_cpu(tp
->counters
.align_errors
);
1824 data
[6] = le32_to_cpu(tp
->counters
.tx_one_collision
);
1825 data
[7] = le32_to_cpu(tp
->counters
.tx_multi_collision
);
1826 data
[8] = le64_to_cpu(tp
->counters
.rx_unicast
);
1827 data
[9] = le64_to_cpu(tp
->counters
.rx_broadcast
);
1828 data
[10] = le32_to_cpu(tp
->counters
.rx_multicast
);
1829 data
[11] = le16_to_cpu(tp
->counters
.tx_aborted
);
1830 data
[12] = le16_to_cpu(tp
->counters
.tx_underun
);
1833 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1837 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
1842 static const struct ethtool_ops rtl8169_ethtool_ops
= {
1843 .get_drvinfo
= rtl8169_get_drvinfo
,
1844 .get_regs_len
= rtl8169_get_regs_len
,
1845 .get_link
= ethtool_op_get_link
,
1846 .get_settings
= rtl8169_get_settings
,
1847 .set_settings
= rtl8169_set_settings
,
1848 .get_msglevel
= rtl8169_get_msglevel
,
1849 .set_msglevel
= rtl8169_set_msglevel
,
1850 .get_regs
= rtl8169_get_regs
,
1851 .get_wol
= rtl8169_get_wol
,
1852 .set_wol
= rtl8169_set_wol
,
1853 .get_strings
= rtl8169_get_strings
,
1854 .get_sset_count
= rtl8169_get_sset_count
,
1855 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
1858 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
,
1859 struct net_device
*dev
, u8 default_version
)
1861 void __iomem
*ioaddr
= tp
->mmio_addr
;
1863 * The driver currently handles the 8168Bf and the 8168Be identically
1864 * but they can be identified more specifically through the test below
1867 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1869 * Same thing for the 8101Eb and the 8101Ec:
1871 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1873 static const struct rtl_mac_info
{
1879 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36
},
1880 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35
},
1883 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34
},
1884 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33
},
1885 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32
},
1886 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33
},
1889 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26
},
1890 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25
},
1891 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26
},
1893 /* 8168DP family. */
1894 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27
},
1895 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28
},
1896 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31
},
1899 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24
},
1900 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23
},
1901 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
1902 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24
},
1903 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
1904 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
1905 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21
},
1906 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22
},
1907 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22
},
1910 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
1911 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
1912 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
1913 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
1916 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30
},
1917 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30
},
1918 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29
},
1919 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30
},
1920 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09
},
1921 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09
},
1922 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08
},
1923 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08
},
1924 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07
},
1925 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07
},
1926 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
1927 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10
},
1928 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
1929 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09
},
1930 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09
},
1931 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
1932 /* FIXME: where did these entries come from ? -- FR */
1933 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
1934 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
1937 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
1938 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
1939 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
1940 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
1941 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
1942 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
1945 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE
}
1947 const struct rtl_mac_info
*p
= mac_info
;
1950 reg
= RTL_R32(TxConfig
);
1951 while ((reg
& p
->mask
) != p
->val
)
1953 tp
->mac_version
= p
->mac_version
;
1955 if (tp
->mac_version
== RTL_GIGA_MAC_NONE
) {
1956 netif_notice(tp
, probe
, dev
,
1957 "unknown MAC, using family default\n");
1958 tp
->mac_version
= default_version
;
1962 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
1964 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
1972 static void rtl_writephy_batch(struct rtl8169_private
*tp
,
1973 const struct phy_reg
*regs
, int len
)
1976 rtl_writephy(tp
, regs
->reg
, regs
->val
);
1981 #define PHY_READ 0x00000000
1982 #define PHY_DATA_OR 0x10000000
1983 #define PHY_DATA_AND 0x20000000
1984 #define PHY_BJMPN 0x30000000
1985 #define PHY_READ_EFUSE 0x40000000
1986 #define PHY_READ_MAC_BYTE 0x50000000
1987 #define PHY_WRITE_MAC_BYTE 0x60000000
1988 #define PHY_CLEAR_READCOUNT 0x70000000
1989 #define PHY_WRITE 0x80000000
1990 #define PHY_READCOUNT_EQ_SKIP 0x90000000
1991 #define PHY_COMP_EQ_SKIPN 0xa0000000
1992 #define PHY_COMP_NEQ_SKIPN 0xb0000000
1993 #define PHY_WRITE_PREVIOUS 0xc0000000
1994 #define PHY_SKIPN 0xd0000000
1995 #define PHY_DELAY_MS 0xe0000000
1996 #define PHY_WRITE_ERI_WORD 0xf0000000
2000 char version
[RTL_VER_SIZE
];
2006 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2008 static bool rtl_fw_format_ok(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
2010 const struct firmware
*fw
= rtl_fw
->fw
;
2011 struct fw_info
*fw_info
= (struct fw_info
*)fw
->data
;
2012 struct rtl_fw_phy_action
*pa
= &rtl_fw
->phy_action
;
2013 char *version
= rtl_fw
->version
;
2016 if (fw
->size
< FW_OPCODE_SIZE
)
2019 if (!fw_info
->magic
) {
2020 size_t i
, size
, start
;
2023 if (fw
->size
< sizeof(*fw_info
))
2026 for (i
= 0; i
< fw
->size
; i
++)
2027 checksum
+= fw
->data
[i
];
2031 start
= le32_to_cpu(fw_info
->fw_start
);
2032 if (start
> fw
->size
)
2035 size
= le32_to_cpu(fw_info
->fw_len
);
2036 if (size
> (fw
->size
- start
) / FW_OPCODE_SIZE
)
2039 memcpy(version
, fw_info
->version
, RTL_VER_SIZE
);
2041 pa
->code
= (__le32
*)(fw
->data
+ start
);
2044 if (fw
->size
% FW_OPCODE_SIZE
)
2047 strlcpy(version
, rtl_lookup_firmware_name(tp
), RTL_VER_SIZE
);
2049 pa
->code
= (__le32
*)fw
->data
;
2050 pa
->size
= fw
->size
/ FW_OPCODE_SIZE
;
2052 version
[RTL_VER_SIZE
- 1] = 0;
2059 static bool rtl_fw_data_ok(struct rtl8169_private
*tp
, struct net_device
*dev
,
2060 struct rtl_fw_phy_action
*pa
)
2065 for (index
= 0; index
< pa
->size
; index
++) {
2066 u32 action
= le32_to_cpu(pa
->code
[index
]);
2067 u32 regno
= (action
& 0x0fff0000) >> 16;
2069 switch(action
& 0xf0000000) {
2073 case PHY_READ_EFUSE
:
2074 case PHY_CLEAR_READCOUNT
:
2076 case PHY_WRITE_PREVIOUS
:
2081 if (regno
> index
) {
2082 netif_err(tp
, ifup
, tp
->dev
,
2083 "Out of range of firmware\n");
2087 case PHY_READCOUNT_EQ_SKIP
:
2088 if (index
+ 2 >= pa
->size
) {
2089 netif_err(tp
, ifup
, tp
->dev
,
2090 "Out of range of firmware\n");
2094 case PHY_COMP_EQ_SKIPN
:
2095 case PHY_COMP_NEQ_SKIPN
:
2097 if (index
+ 1 + regno
>= pa
->size
) {
2098 netif_err(tp
, ifup
, tp
->dev
,
2099 "Out of range of firmware\n");
2104 case PHY_READ_MAC_BYTE
:
2105 case PHY_WRITE_MAC_BYTE
:
2106 case PHY_WRITE_ERI_WORD
:
2108 netif_err(tp
, ifup
, tp
->dev
,
2109 "Invalid action 0x%08x\n", action
);
2118 static int rtl_check_firmware(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
2120 struct net_device
*dev
= tp
->dev
;
2123 if (!rtl_fw_format_ok(tp
, rtl_fw
)) {
2124 netif_err(tp
, ifup
, dev
, "invalid firwmare\n");
2128 if (rtl_fw_data_ok(tp
, dev
, &rtl_fw
->phy_action
))
2134 static void rtl_phy_write_fw(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
2136 struct rtl_fw_phy_action
*pa
= &rtl_fw
->phy_action
;
2140 predata
= count
= 0;
2142 for (index
= 0; index
< pa
->size
; ) {
2143 u32 action
= le32_to_cpu(pa
->code
[index
]);
2144 u32 data
= action
& 0x0000ffff;
2145 u32 regno
= (action
& 0x0fff0000) >> 16;
2150 switch(action
& 0xf0000000) {
2152 predata
= rtl_readphy(tp
, regno
);
2167 case PHY_READ_EFUSE
:
2168 predata
= rtl8168d_efuse_read(tp
->mmio_addr
, regno
);
2171 case PHY_CLEAR_READCOUNT
:
2176 rtl_writephy(tp
, regno
, data
);
2179 case PHY_READCOUNT_EQ_SKIP
:
2180 index
+= (count
== data
) ? 2 : 1;
2182 case PHY_COMP_EQ_SKIPN
:
2183 if (predata
== data
)
2187 case PHY_COMP_NEQ_SKIPN
:
2188 if (predata
!= data
)
2192 case PHY_WRITE_PREVIOUS
:
2193 rtl_writephy(tp
, regno
, predata
);
2204 case PHY_READ_MAC_BYTE
:
2205 case PHY_WRITE_MAC_BYTE
:
2206 case PHY_WRITE_ERI_WORD
:
2213 static void rtl_release_firmware(struct rtl8169_private
*tp
)
2215 if (!IS_ERR_OR_NULL(tp
->rtl_fw
)) {
2216 release_firmware(tp
->rtl_fw
->fw
);
2219 tp
->rtl_fw
= RTL_FIRMWARE_UNKNOWN
;
2222 static void rtl_apply_firmware(struct rtl8169_private
*tp
)
2224 struct rtl_fw
*rtl_fw
= tp
->rtl_fw
;
2226 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2227 if (!IS_ERR_OR_NULL(rtl_fw
))
2228 rtl_phy_write_fw(tp
, rtl_fw
);
2231 static void rtl_apply_firmware_cond(struct rtl8169_private
*tp
, u8 reg
, u16 val
)
2233 if (rtl_readphy(tp
, reg
) != val
)
2234 netif_warn(tp
, hw
, tp
->dev
, "chipset not ready for firmware\n");
2236 rtl_apply_firmware(tp
);
2239 static void rtl8169s_hw_phy_config(struct rtl8169_private
*tp
)
2241 static const struct phy_reg phy_reg_init
[] = {
2303 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2306 static void rtl8169sb_hw_phy_config(struct rtl8169_private
*tp
)
2308 static const struct phy_reg phy_reg_init
[] = {
2314 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2317 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private
*tp
)
2319 struct pci_dev
*pdev
= tp
->pci_dev
;
2321 if ((pdev
->subsystem_vendor
!= PCI_VENDOR_ID_GIGABYTE
) ||
2322 (pdev
->subsystem_device
!= 0xe000))
2325 rtl_writephy(tp
, 0x1f, 0x0001);
2326 rtl_writephy(tp
, 0x10, 0xf01b);
2327 rtl_writephy(tp
, 0x1f, 0x0000);
2330 static void rtl8169scd_hw_phy_config(struct rtl8169_private
*tp
)
2332 static const struct phy_reg phy_reg_init
[] = {
2372 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2374 rtl8169scd_hw_phy_config_quirk(tp
);
2377 static void rtl8169sce_hw_phy_config(struct rtl8169_private
*tp
)
2379 static const struct phy_reg phy_reg_init
[] = {
2427 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2430 static void rtl8168bb_hw_phy_config(struct rtl8169_private
*tp
)
2432 static const struct phy_reg phy_reg_init
[] = {
2437 rtl_writephy(tp
, 0x1f, 0x0001);
2438 rtl_patchphy(tp
, 0x16, 1 << 0);
2440 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2443 static void rtl8168bef_hw_phy_config(struct rtl8169_private
*tp
)
2445 static const struct phy_reg phy_reg_init
[] = {
2451 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2454 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private
*tp
)
2456 static const struct phy_reg phy_reg_init
[] = {
2464 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2467 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private
*tp
)
2469 static const struct phy_reg phy_reg_init
[] = {
2475 rtl_writephy(tp
, 0x1f, 0x0000);
2476 rtl_patchphy(tp
, 0x14, 1 << 5);
2477 rtl_patchphy(tp
, 0x0d, 1 << 5);
2479 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2482 static void rtl8168c_1_hw_phy_config(struct rtl8169_private
*tp
)
2484 static const struct phy_reg phy_reg_init
[] = {
2504 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2506 rtl_patchphy(tp
, 0x14, 1 << 5);
2507 rtl_patchphy(tp
, 0x0d, 1 << 5);
2508 rtl_writephy(tp
, 0x1f, 0x0000);
2511 static void rtl8168c_2_hw_phy_config(struct rtl8169_private
*tp
)
2513 static const struct phy_reg phy_reg_init
[] = {
2531 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2533 rtl_patchphy(tp
, 0x16, 1 << 0);
2534 rtl_patchphy(tp
, 0x14, 1 << 5);
2535 rtl_patchphy(tp
, 0x0d, 1 << 5);
2536 rtl_writephy(tp
, 0x1f, 0x0000);
2539 static void rtl8168c_3_hw_phy_config(struct rtl8169_private
*tp
)
2541 static const struct phy_reg phy_reg_init
[] = {
2553 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2555 rtl_patchphy(tp
, 0x16, 1 << 0);
2556 rtl_patchphy(tp
, 0x14, 1 << 5);
2557 rtl_patchphy(tp
, 0x0d, 1 << 5);
2558 rtl_writephy(tp
, 0x1f, 0x0000);
2561 static void rtl8168c_4_hw_phy_config(struct rtl8169_private
*tp
)
2563 rtl8168c_3_hw_phy_config(tp
);
2566 static void rtl8168d_1_hw_phy_config(struct rtl8169_private
*tp
)
2568 static const struct phy_reg phy_reg_init_0
[] = {
2569 /* Channel Estimation */
2590 * Enhance line driver power
2599 * Can not link to 1Gbps with bad cable
2600 * Decrease SNR threshold form 21.07dB to 19.04dB
2608 void __iomem
*ioaddr
= tp
->mmio_addr
;
2610 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2614 * Fine Tune Switching regulator parameter
2616 rtl_writephy(tp
, 0x1f, 0x0002);
2617 rtl_w1w0_phy(tp
, 0x0b, 0x0010, 0x00ef);
2618 rtl_w1w0_phy(tp
, 0x0c, 0xa200, 0x5d00);
2620 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2621 static const struct phy_reg phy_reg_init
[] = {
2631 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2633 val
= rtl_readphy(tp
, 0x0d);
2635 if ((val
& 0x00ff) != 0x006c) {
2636 static const u32 set
[] = {
2637 0x0065, 0x0066, 0x0067, 0x0068,
2638 0x0069, 0x006a, 0x006b, 0x006c
2642 rtl_writephy(tp
, 0x1f, 0x0002);
2645 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2646 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
2649 static const struct phy_reg phy_reg_init
[] = {
2657 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2660 /* RSET couple improve */
2661 rtl_writephy(tp
, 0x1f, 0x0002);
2662 rtl_patchphy(tp
, 0x0d, 0x0300);
2663 rtl_patchphy(tp
, 0x0f, 0x0010);
2665 /* Fine tune PLL performance */
2666 rtl_writephy(tp
, 0x1f, 0x0002);
2667 rtl_w1w0_phy(tp
, 0x02, 0x0100, 0x0600);
2668 rtl_w1w0_phy(tp
, 0x03, 0x0000, 0xe000);
2670 rtl_writephy(tp
, 0x1f, 0x0005);
2671 rtl_writephy(tp
, 0x05, 0x001b);
2673 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xbf00);
2675 rtl_writephy(tp
, 0x1f, 0x0000);
2678 static void rtl8168d_2_hw_phy_config(struct rtl8169_private
*tp
)
2680 static const struct phy_reg phy_reg_init_0
[] = {
2681 /* Channel Estimation */
2702 * Enhance line driver power
2711 * Can not link to 1Gbps with bad cable
2712 * Decrease SNR threshold form 21.07dB to 19.04dB
2720 void __iomem
*ioaddr
= tp
->mmio_addr
;
2722 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2724 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2725 static const struct phy_reg phy_reg_init
[] = {
2736 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2738 val
= rtl_readphy(tp
, 0x0d);
2739 if ((val
& 0x00ff) != 0x006c) {
2740 static const u32 set
[] = {
2741 0x0065, 0x0066, 0x0067, 0x0068,
2742 0x0069, 0x006a, 0x006b, 0x006c
2746 rtl_writephy(tp
, 0x1f, 0x0002);
2749 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2750 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
2753 static const struct phy_reg phy_reg_init
[] = {
2761 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2764 /* Fine tune PLL performance */
2765 rtl_writephy(tp
, 0x1f, 0x0002);
2766 rtl_w1w0_phy(tp
, 0x02, 0x0100, 0x0600);
2767 rtl_w1w0_phy(tp
, 0x03, 0x0000, 0xe000);
2769 /* Switching regulator Slew rate */
2770 rtl_writephy(tp
, 0x1f, 0x0002);
2771 rtl_patchphy(tp
, 0x0f, 0x0017);
2773 rtl_writephy(tp
, 0x1f, 0x0005);
2774 rtl_writephy(tp
, 0x05, 0x001b);
2776 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xb300);
2778 rtl_writephy(tp
, 0x1f, 0x0000);
2781 static void rtl8168d_3_hw_phy_config(struct rtl8169_private
*tp
)
2783 static const struct phy_reg phy_reg_init
[] = {
2839 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2842 static void rtl8168d_4_hw_phy_config(struct rtl8169_private
*tp
)
2844 static const struct phy_reg phy_reg_init
[] = {
2854 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2855 rtl_patchphy(tp
, 0x0d, 1 << 5);
2858 static void rtl8168e_1_hw_phy_config(struct rtl8169_private
*tp
)
2860 static const struct phy_reg phy_reg_init
[] = {
2861 /* Enable Delay cap */
2867 /* Channel estimation fine tune */
2876 /* Update PFM & 10M TX idle timer */
2888 rtl_apply_firmware(tp
);
2890 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2892 /* DCO enable for 10M IDLE Power */
2893 rtl_writephy(tp
, 0x1f, 0x0007);
2894 rtl_writephy(tp
, 0x1e, 0x0023);
2895 rtl_w1w0_phy(tp
, 0x17, 0x0006, 0x0000);
2896 rtl_writephy(tp
, 0x1f, 0x0000);
2898 /* For impedance matching */
2899 rtl_writephy(tp
, 0x1f, 0x0002);
2900 rtl_w1w0_phy(tp
, 0x08, 0x8000, 0x7f00);
2901 rtl_writephy(tp
, 0x1f, 0x0000);
2903 /* PHY auto speed down */
2904 rtl_writephy(tp
, 0x1f, 0x0007);
2905 rtl_writephy(tp
, 0x1e, 0x002d);
2906 rtl_w1w0_phy(tp
, 0x18, 0x0050, 0x0000);
2907 rtl_writephy(tp
, 0x1f, 0x0000);
2908 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
2910 rtl_writephy(tp
, 0x1f, 0x0005);
2911 rtl_writephy(tp
, 0x05, 0x8b86);
2912 rtl_w1w0_phy(tp
, 0x06, 0x0001, 0x0000);
2913 rtl_writephy(tp
, 0x1f, 0x0000);
2915 rtl_writephy(tp
, 0x1f, 0x0005);
2916 rtl_writephy(tp
, 0x05, 0x8b85);
2917 rtl_w1w0_phy(tp
, 0x06, 0x0000, 0x2000);
2918 rtl_writephy(tp
, 0x1f, 0x0007);
2919 rtl_writephy(tp
, 0x1e, 0x0020);
2920 rtl_w1w0_phy(tp
, 0x15, 0x0000, 0x1100);
2921 rtl_writephy(tp
, 0x1f, 0x0006);
2922 rtl_writephy(tp
, 0x00, 0x5a00);
2923 rtl_writephy(tp
, 0x1f, 0x0000);
2924 rtl_writephy(tp
, 0x0d, 0x0007);
2925 rtl_writephy(tp
, 0x0e, 0x003c);
2926 rtl_writephy(tp
, 0x0d, 0x4007);
2927 rtl_writephy(tp
, 0x0e, 0x0000);
2928 rtl_writephy(tp
, 0x0d, 0x0000);
2931 static void rtl8168e_2_hw_phy_config(struct rtl8169_private
*tp
)
2933 static const struct phy_reg phy_reg_init
[] = {
2934 /* Enable Delay cap */
2943 /* Channel estimation fine tune */
2960 rtl_apply_firmware(tp
);
2962 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2964 /* For 4-corner performance improve */
2965 rtl_writephy(tp
, 0x1f, 0x0005);
2966 rtl_writephy(tp
, 0x05, 0x8b80);
2967 rtl_w1w0_phy(tp
, 0x17, 0x0006, 0x0000);
2968 rtl_writephy(tp
, 0x1f, 0x0000);
2970 /* PHY auto speed down */
2971 rtl_writephy(tp
, 0x1f, 0x0004);
2972 rtl_writephy(tp
, 0x1f, 0x0007);
2973 rtl_writephy(tp
, 0x1e, 0x002d);
2974 rtl_w1w0_phy(tp
, 0x18, 0x0010, 0x0000);
2975 rtl_writephy(tp
, 0x1f, 0x0002);
2976 rtl_writephy(tp
, 0x1f, 0x0000);
2977 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
2979 /* improve 10M EEE waveform */
2980 rtl_writephy(tp
, 0x1f, 0x0005);
2981 rtl_writephy(tp
, 0x05, 0x8b86);
2982 rtl_w1w0_phy(tp
, 0x06, 0x0001, 0x0000);
2983 rtl_writephy(tp
, 0x1f, 0x0000);
2985 /* Improve 2-pair detection performance */
2986 rtl_writephy(tp
, 0x1f, 0x0005);
2987 rtl_writephy(tp
, 0x05, 0x8b85);
2988 rtl_w1w0_phy(tp
, 0x06, 0x4000, 0x0000);
2989 rtl_writephy(tp
, 0x1f, 0x0000);
2992 rtl_w1w0_eri(tp
->mmio_addr
, 0x1b0, ERIAR_MASK_1111
, 0x0000, 0x0003,
2994 rtl_writephy(tp
, 0x1f, 0x0005);
2995 rtl_writephy(tp
, 0x05, 0x8b85);
2996 rtl_w1w0_phy(tp
, 0x06, 0x0000, 0x2000);
2997 rtl_writephy(tp
, 0x1f, 0x0004);
2998 rtl_writephy(tp
, 0x1f, 0x0007);
2999 rtl_writephy(tp
, 0x1e, 0x0020);
3000 rtl_w1w0_phy(tp
, 0x15, 0x0000, 0x0100);
3001 rtl_writephy(tp
, 0x1f, 0x0002);
3002 rtl_writephy(tp
, 0x1f, 0x0000);
3003 rtl_writephy(tp
, 0x0d, 0x0007);
3004 rtl_writephy(tp
, 0x0e, 0x003c);
3005 rtl_writephy(tp
, 0x0d, 0x4007);
3006 rtl_writephy(tp
, 0x0e, 0x0000);
3007 rtl_writephy(tp
, 0x0d, 0x0000);
3010 rtl_writephy(tp
, 0x1f, 0x0003);
3011 rtl_w1w0_phy(tp
, 0x19, 0x0000, 0x0001);
3012 rtl_w1w0_phy(tp
, 0x10, 0x0000, 0x0400);
3013 rtl_writephy(tp
, 0x1f, 0x0000);
3016 static void rtl8168f_1_hw_phy_config(struct rtl8169_private
*tp
)
3018 static const struct phy_reg phy_reg_init
[] = {
3019 /* Channel estimation fine tune */
3024 /* Modify green table for giga & fnet */
3041 /* Modify green table for 10M */
3047 /* Disable hiimpedance detection (RTCT) */
3053 rtl_apply_firmware(tp
);
3055 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3057 /* For 4-corner performance improve */
3058 rtl_writephy(tp
, 0x1f, 0x0005);
3059 rtl_writephy(tp
, 0x05, 0x8b80);
3060 rtl_w1w0_phy(tp
, 0x06, 0x0006, 0x0000);
3061 rtl_writephy(tp
, 0x1f, 0x0000);
3063 /* PHY auto speed down */
3064 rtl_writephy(tp
, 0x1f, 0x0007);
3065 rtl_writephy(tp
, 0x1e, 0x002d);
3066 rtl_w1w0_phy(tp
, 0x18, 0x0010, 0x0000);
3067 rtl_writephy(tp
, 0x1f, 0x0000);
3068 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
3070 /* Improve 10M EEE waveform */
3071 rtl_writephy(tp
, 0x1f, 0x0005);
3072 rtl_writephy(tp
, 0x05, 0x8b86);
3073 rtl_w1w0_phy(tp
, 0x06, 0x0001, 0x0000);
3074 rtl_writephy(tp
, 0x1f, 0x0000);
3076 /* Improve 2-pair detection performance */
3077 rtl_writephy(tp
, 0x1f, 0x0005);
3078 rtl_writephy(tp
, 0x05, 0x8b85);
3079 rtl_w1w0_phy(tp
, 0x06, 0x4000, 0x0000);
3080 rtl_writephy(tp
, 0x1f, 0x0000);
3083 static void rtl8168f_2_hw_phy_config(struct rtl8169_private
*tp
)
3085 rtl_apply_firmware(tp
);
3087 /* For 4-corner performance improve */
3088 rtl_writephy(tp
, 0x1f, 0x0005);
3089 rtl_writephy(tp
, 0x05, 0x8b80);
3090 rtl_w1w0_phy(tp
, 0x06, 0x0006, 0x0000);
3091 rtl_writephy(tp
, 0x1f, 0x0000);
3093 /* PHY auto speed down */
3094 rtl_writephy(tp
, 0x1f, 0x0007);
3095 rtl_writephy(tp
, 0x1e, 0x002d);
3096 rtl_w1w0_phy(tp
, 0x18, 0x0010, 0x0000);
3097 rtl_writephy(tp
, 0x1f, 0x0000);
3098 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
3100 /* Improve 10M EEE waveform */
3101 rtl_writephy(tp
, 0x1f, 0x0005);
3102 rtl_writephy(tp
, 0x05, 0x8b86);
3103 rtl_w1w0_phy(tp
, 0x06, 0x0001, 0x0000);
3104 rtl_writephy(tp
, 0x1f, 0x0000);
3107 static void rtl8102e_hw_phy_config(struct rtl8169_private
*tp
)
3109 static const struct phy_reg phy_reg_init
[] = {
3116 rtl_writephy(tp
, 0x1f, 0x0000);
3117 rtl_patchphy(tp
, 0x11, 1 << 12);
3118 rtl_patchphy(tp
, 0x19, 1 << 13);
3119 rtl_patchphy(tp
, 0x10, 1 << 15);
3121 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3124 static void rtl8105e_hw_phy_config(struct rtl8169_private
*tp
)
3126 static const struct phy_reg phy_reg_init
[] = {
3140 /* Disable ALDPS before ram code */
3141 rtl_writephy(tp
, 0x1f, 0x0000);
3142 rtl_writephy(tp
, 0x18, 0x0310);
3145 rtl_apply_firmware(tp
);
3147 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3150 static void rtl_hw_phy_config(struct net_device
*dev
)
3152 struct rtl8169_private
*tp
= netdev_priv(dev
);
3154 rtl8169_print_mac_version(tp
);
3156 switch (tp
->mac_version
) {
3157 case RTL_GIGA_MAC_VER_01
:
3159 case RTL_GIGA_MAC_VER_02
:
3160 case RTL_GIGA_MAC_VER_03
:
3161 rtl8169s_hw_phy_config(tp
);
3163 case RTL_GIGA_MAC_VER_04
:
3164 rtl8169sb_hw_phy_config(tp
);
3166 case RTL_GIGA_MAC_VER_05
:
3167 rtl8169scd_hw_phy_config(tp
);
3169 case RTL_GIGA_MAC_VER_06
:
3170 rtl8169sce_hw_phy_config(tp
);
3172 case RTL_GIGA_MAC_VER_07
:
3173 case RTL_GIGA_MAC_VER_08
:
3174 case RTL_GIGA_MAC_VER_09
:
3175 rtl8102e_hw_phy_config(tp
);
3177 case RTL_GIGA_MAC_VER_11
:
3178 rtl8168bb_hw_phy_config(tp
);
3180 case RTL_GIGA_MAC_VER_12
:
3181 rtl8168bef_hw_phy_config(tp
);
3183 case RTL_GIGA_MAC_VER_17
:
3184 rtl8168bef_hw_phy_config(tp
);
3186 case RTL_GIGA_MAC_VER_18
:
3187 rtl8168cp_1_hw_phy_config(tp
);
3189 case RTL_GIGA_MAC_VER_19
:
3190 rtl8168c_1_hw_phy_config(tp
);
3192 case RTL_GIGA_MAC_VER_20
:
3193 rtl8168c_2_hw_phy_config(tp
);
3195 case RTL_GIGA_MAC_VER_21
:
3196 rtl8168c_3_hw_phy_config(tp
);
3198 case RTL_GIGA_MAC_VER_22
:
3199 rtl8168c_4_hw_phy_config(tp
);
3201 case RTL_GIGA_MAC_VER_23
:
3202 case RTL_GIGA_MAC_VER_24
:
3203 rtl8168cp_2_hw_phy_config(tp
);
3205 case RTL_GIGA_MAC_VER_25
:
3206 rtl8168d_1_hw_phy_config(tp
);
3208 case RTL_GIGA_MAC_VER_26
:
3209 rtl8168d_2_hw_phy_config(tp
);
3211 case RTL_GIGA_MAC_VER_27
:
3212 rtl8168d_3_hw_phy_config(tp
);
3214 case RTL_GIGA_MAC_VER_28
:
3215 rtl8168d_4_hw_phy_config(tp
);
3217 case RTL_GIGA_MAC_VER_29
:
3218 case RTL_GIGA_MAC_VER_30
:
3219 rtl8105e_hw_phy_config(tp
);
3221 case RTL_GIGA_MAC_VER_31
:
3224 case RTL_GIGA_MAC_VER_32
:
3225 case RTL_GIGA_MAC_VER_33
:
3226 rtl8168e_1_hw_phy_config(tp
);
3228 case RTL_GIGA_MAC_VER_34
:
3229 rtl8168e_2_hw_phy_config(tp
);
3231 case RTL_GIGA_MAC_VER_35
:
3232 rtl8168f_1_hw_phy_config(tp
);
3234 case RTL_GIGA_MAC_VER_36
:
3235 rtl8168f_2_hw_phy_config(tp
);
3243 static void rtl_phy_work(struct rtl8169_private
*tp
)
3245 struct timer_list
*timer
= &tp
->timer
;
3246 void __iomem
*ioaddr
= tp
->mmio_addr
;
3247 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
3249 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
3251 if (tp
->phy_reset_pending(tp
)) {
3253 * A busy loop could burn quite a few cycles on nowadays CPU.
3254 * Let's delay the execution of the timer for a few ticks.
3260 if (tp
->link_ok(ioaddr
))
3263 netif_warn(tp
, link
, tp
->dev
, "PHY reset until link up\n");
3265 tp
->phy_reset_enable(tp
);
3268 mod_timer(timer
, jiffies
+ timeout
);
3271 static void rtl_schedule_task(struct rtl8169_private
*tp
, enum rtl_flag flag
)
3273 if (!test_and_set_bit(flag
, tp
->wk
.flags
))
3274 schedule_work(&tp
->wk
.work
);
3277 static void rtl8169_phy_timer(unsigned long __opaque
)
3279 struct net_device
*dev
= (struct net_device
*)__opaque
;
3280 struct rtl8169_private
*tp
= netdev_priv(dev
);
3282 rtl_schedule_task(tp
, RTL_FLAG_TASK_PHY_PENDING
);
3285 #ifdef CONFIG_NET_POLL_CONTROLLER
3286 static void rtl8169_netpoll(struct net_device
*dev
)
3288 struct rtl8169_private
*tp
= netdev_priv(dev
);
3290 rtl8169_interrupt(tp
->pci_dev
->irq
, dev
);
3294 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
3295 void __iomem
*ioaddr
)
3298 pci_release_regions(pdev
);
3299 pci_clear_mwi(pdev
);
3300 pci_disable_device(pdev
);
3304 static void rtl8169_phy_reset(struct net_device
*dev
,
3305 struct rtl8169_private
*tp
)
3309 tp
->phy_reset_enable(tp
);
3310 for (i
= 0; i
< 100; i
++) {
3311 if (!tp
->phy_reset_pending(tp
))
3315 netif_err(tp
, link
, dev
, "PHY reset failed\n");
3318 static bool rtl_tbi_enabled(struct rtl8169_private
*tp
)
3320 void __iomem
*ioaddr
= tp
->mmio_addr
;
3322 return (tp
->mac_version
== RTL_GIGA_MAC_VER_01
) &&
3323 (RTL_R8(PHYstatus
) & TBI_Enable
);
3326 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
3328 void __iomem
*ioaddr
= tp
->mmio_addr
;
3330 rtl_hw_phy_config(dev
);
3332 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
3333 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3337 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
3339 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
3340 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
3342 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
3343 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3345 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3346 rtl_writephy(tp
, 0x0b, 0x0000); //w 0x0b 15 0 0
3349 rtl8169_phy_reset(dev
, tp
);
3351 rtl8169_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
,
3352 ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
3353 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
3354 (tp
->mii
.supports_gmii
?
3355 ADVERTISED_1000baseT_Half
|
3356 ADVERTISED_1000baseT_Full
: 0));
3358 if (rtl_tbi_enabled(tp
))
3359 netif_info(tp
, link
, dev
, "TBI auto-negotiating\n");
3362 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
3364 void __iomem
*ioaddr
= tp
->mmio_addr
;
3368 low
= addr
[0] | (addr
[1] << 8) | (addr
[2] << 16) | (addr
[3] << 24);
3369 high
= addr
[4] | (addr
[5] << 8);
3373 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3375 RTL_W32(MAC4
, high
);
3381 if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
) {
3382 const struct exgmac_reg e
[] = {
3383 { .addr
= 0xe0, ERIAR_MASK_1111
, .val
= low
},
3384 { .addr
= 0xe4, ERIAR_MASK_1111
, .val
= high
},
3385 { .addr
= 0xf0, ERIAR_MASK_1111
, .val
= low
<< 16 },
3386 { .addr
= 0xf4, ERIAR_MASK_1111
, .val
= high
<< 16 |
3390 rtl_write_exgmac_batch(ioaddr
, e
, ARRAY_SIZE(e
));
3393 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3395 rtl_unlock_work(tp
);
3398 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
3400 struct rtl8169_private
*tp
= netdev_priv(dev
);
3401 struct sockaddr
*addr
= p
;
3403 if (!is_valid_ether_addr(addr
->sa_data
))
3404 return -EADDRNOTAVAIL
;
3406 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
3408 rtl_rar_set(tp
, dev
->dev_addr
);
3413 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
3415 struct rtl8169_private
*tp
= netdev_priv(dev
);
3416 struct mii_ioctl_data
*data
= if_mii(ifr
);
3418 return netif_running(dev
) ? tp
->do_ioctl(tp
, data
, cmd
) : -ENODEV
;
3421 static int rtl_xmii_ioctl(struct rtl8169_private
*tp
,
3422 struct mii_ioctl_data
*data
, int cmd
)
3426 data
->phy_id
= 32; /* Internal PHY */
3430 data
->val_out
= rtl_readphy(tp
, data
->reg_num
& 0x1f);
3434 rtl_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
3440 static int rtl_tbi_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
3445 static const struct rtl_cfg_info
{
3446 void (*hw_start
)(struct net_device
*);
3447 unsigned int region
;
3452 } rtl_cfg_infos
[] = {
3454 .hw_start
= rtl_hw_start_8169
,
3457 .event_slow
= SYSErr
| LinkChg
| RxOverflow
| RxFIFOOver
,
3458 .features
= RTL_FEATURE_GMII
,
3459 .default_ver
= RTL_GIGA_MAC_VER_01
,
3462 .hw_start
= rtl_hw_start_8168
,
3465 .event_slow
= SYSErr
| LinkChg
| RxOverflow
,
3466 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
,
3467 .default_ver
= RTL_GIGA_MAC_VER_11
,
3470 .hw_start
= rtl_hw_start_8101
,
3473 .event_slow
= SYSErr
| LinkChg
| RxOverflow
| RxFIFOOver
|
3475 .features
= RTL_FEATURE_MSI
,
3476 .default_ver
= RTL_GIGA_MAC_VER_13
,
3480 /* Cfg9346_Unlock assumed. */
3481 static unsigned rtl_try_msi(struct rtl8169_private
*tp
,
3482 const struct rtl_cfg_info
*cfg
)
3484 void __iomem
*ioaddr
= tp
->mmio_addr
;
3488 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
3489 if (cfg
->features
& RTL_FEATURE_MSI
) {
3490 if (pci_enable_msi(tp
->pci_dev
)) {
3491 netif_info(tp
, hw
, tp
->dev
, "no MSI. Back to INTx.\n");
3494 msi
= RTL_FEATURE_MSI
;
3497 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
3498 RTL_W8(Config2
, cfg2
);
3502 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8169_private
*tp
)
3504 if (tp
->features
& RTL_FEATURE_MSI
) {
3505 pci_disable_msi(pdev
);
3506 tp
->features
&= ~RTL_FEATURE_MSI
;
3510 static const struct net_device_ops rtl8169_netdev_ops
= {
3511 .ndo_open
= rtl8169_open
,
3512 .ndo_stop
= rtl8169_close
,
3513 .ndo_get_stats
= rtl8169_get_stats
,
3514 .ndo_start_xmit
= rtl8169_start_xmit
,
3515 .ndo_tx_timeout
= rtl8169_tx_timeout
,
3516 .ndo_validate_addr
= eth_validate_addr
,
3517 .ndo_change_mtu
= rtl8169_change_mtu
,
3518 .ndo_fix_features
= rtl8169_fix_features
,
3519 .ndo_set_features
= rtl8169_set_features
,
3520 .ndo_set_mac_address
= rtl_set_mac_address
,
3521 .ndo_do_ioctl
= rtl8169_ioctl
,
3522 .ndo_set_rx_mode
= rtl_set_rx_mode
,
3523 #ifdef CONFIG_NET_POLL_CONTROLLER
3524 .ndo_poll_controller
= rtl8169_netpoll
,
3529 static void __devinit
rtl_init_mdio_ops(struct rtl8169_private
*tp
)
3531 struct mdio_ops
*ops
= &tp
->mdio_ops
;
3533 switch (tp
->mac_version
) {
3534 case RTL_GIGA_MAC_VER_27
:
3535 ops
->write
= r8168dp_1_mdio_write
;
3536 ops
->read
= r8168dp_1_mdio_read
;
3538 case RTL_GIGA_MAC_VER_28
:
3539 case RTL_GIGA_MAC_VER_31
:
3540 ops
->write
= r8168dp_2_mdio_write
;
3541 ops
->read
= r8168dp_2_mdio_read
;
3544 ops
->write
= r8169_mdio_write
;
3545 ops
->read
= r8169_mdio_read
;
3550 static void rtl_wol_suspend_quirk(struct rtl8169_private
*tp
)
3552 void __iomem
*ioaddr
= tp
->mmio_addr
;
3554 switch (tp
->mac_version
) {
3555 case RTL_GIGA_MAC_VER_29
:
3556 case RTL_GIGA_MAC_VER_30
:
3557 case RTL_GIGA_MAC_VER_32
:
3558 case RTL_GIGA_MAC_VER_33
:
3559 case RTL_GIGA_MAC_VER_34
:
3560 RTL_W32(RxConfig
, RTL_R32(RxConfig
) |
3561 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
);
3568 static bool rtl_wol_pll_power_down(struct rtl8169_private
*tp
)
3570 if (!(__rtl8169_get_wol(tp
) & WAKE_ANY
))
3573 rtl_writephy(tp
, 0x1f, 0x0000);
3574 rtl_writephy(tp
, MII_BMCR
, 0x0000);
3576 rtl_wol_suspend_quirk(tp
);
3581 static void r810x_phy_power_down(struct rtl8169_private
*tp
)
3583 rtl_writephy(tp
, 0x1f, 0x0000);
3584 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
3587 static void r810x_phy_power_up(struct rtl8169_private
*tp
)
3589 rtl_writephy(tp
, 0x1f, 0x0000);
3590 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
3593 static void r810x_pll_power_down(struct rtl8169_private
*tp
)
3595 if (rtl_wol_pll_power_down(tp
))
3598 r810x_phy_power_down(tp
);
3601 static void r810x_pll_power_up(struct rtl8169_private
*tp
)
3603 r810x_phy_power_up(tp
);
3606 static void r8168_phy_power_up(struct rtl8169_private
*tp
)
3608 rtl_writephy(tp
, 0x1f, 0x0000);
3609 switch (tp
->mac_version
) {
3610 case RTL_GIGA_MAC_VER_11
:
3611 case RTL_GIGA_MAC_VER_12
:
3612 case RTL_GIGA_MAC_VER_17
:
3613 case RTL_GIGA_MAC_VER_18
:
3614 case RTL_GIGA_MAC_VER_19
:
3615 case RTL_GIGA_MAC_VER_20
:
3616 case RTL_GIGA_MAC_VER_21
:
3617 case RTL_GIGA_MAC_VER_22
:
3618 case RTL_GIGA_MAC_VER_23
:
3619 case RTL_GIGA_MAC_VER_24
:
3620 case RTL_GIGA_MAC_VER_25
:
3621 case RTL_GIGA_MAC_VER_26
:
3622 case RTL_GIGA_MAC_VER_27
:
3623 case RTL_GIGA_MAC_VER_28
:
3624 case RTL_GIGA_MAC_VER_31
:
3625 rtl_writephy(tp
, 0x0e, 0x0000);
3630 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
3633 static void r8168_phy_power_down(struct rtl8169_private
*tp
)
3635 rtl_writephy(tp
, 0x1f, 0x0000);
3636 switch (tp
->mac_version
) {
3637 case RTL_GIGA_MAC_VER_32
:
3638 case RTL_GIGA_MAC_VER_33
:
3639 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
| BMCR_PDOWN
);
3642 case RTL_GIGA_MAC_VER_11
:
3643 case RTL_GIGA_MAC_VER_12
:
3644 case RTL_GIGA_MAC_VER_17
:
3645 case RTL_GIGA_MAC_VER_18
:
3646 case RTL_GIGA_MAC_VER_19
:
3647 case RTL_GIGA_MAC_VER_20
:
3648 case RTL_GIGA_MAC_VER_21
:
3649 case RTL_GIGA_MAC_VER_22
:
3650 case RTL_GIGA_MAC_VER_23
:
3651 case RTL_GIGA_MAC_VER_24
:
3652 case RTL_GIGA_MAC_VER_25
:
3653 case RTL_GIGA_MAC_VER_26
:
3654 case RTL_GIGA_MAC_VER_27
:
3655 case RTL_GIGA_MAC_VER_28
:
3656 case RTL_GIGA_MAC_VER_31
:
3657 rtl_writephy(tp
, 0x0e, 0x0200);
3659 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
3664 static void r8168_pll_power_down(struct rtl8169_private
*tp
)
3666 void __iomem
*ioaddr
= tp
->mmio_addr
;
3668 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3669 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3670 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) &&
3671 r8168dp_check_dash(tp
)) {
3675 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_23
||
3676 tp
->mac_version
== RTL_GIGA_MAC_VER_24
) &&
3677 (RTL_R16(CPlusCmd
) & ASF
)) {
3681 if (tp
->mac_version
== RTL_GIGA_MAC_VER_32
||
3682 tp
->mac_version
== RTL_GIGA_MAC_VER_33
)
3683 rtl_ephy_write(ioaddr
, 0x19, 0xff64);
3685 if (rtl_wol_pll_power_down(tp
))
3688 r8168_phy_power_down(tp
);
3690 switch (tp
->mac_version
) {
3691 case RTL_GIGA_MAC_VER_25
:
3692 case RTL_GIGA_MAC_VER_26
:
3693 case RTL_GIGA_MAC_VER_27
:
3694 case RTL_GIGA_MAC_VER_28
:
3695 case RTL_GIGA_MAC_VER_31
:
3696 case RTL_GIGA_MAC_VER_32
:
3697 case RTL_GIGA_MAC_VER_33
:
3698 RTL_W8(PMCH
, RTL_R8(PMCH
) & ~0x80);
3703 static void r8168_pll_power_up(struct rtl8169_private
*tp
)
3705 void __iomem
*ioaddr
= tp
->mmio_addr
;
3707 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3708 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3709 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) &&
3710 r8168dp_check_dash(tp
)) {
3714 switch (tp
->mac_version
) {
3715 case RTL_GIGA_MAC_VER_25
:
3716 case RTL_GIGA_MAC_VER_26
:
3717 case RTL_GIGA_MAC_VER_27
:
3718 case RTL_GIGA_MAC_VER_28
:
3719 case RTL_GIGA_MAC_VER_31
:
3720 case RTL_GIGA_MAC_VER_32
:
3721 case RTL_GIGA_MAC_VER_33
:
3722 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0x80);
3726 r8168_phy_power_up(tp
);
3729 static void rtl_generic_op(struct rtl8169_private
*tp
,
3730 void (*op
)(struct rtl8169_private
*))
3736 static void rtl_pll_power_down(struct rtl8169_private
*tp
)
3738 rtl_generic_op(tp
, tp
->pll_power_ops
.down
);
3741 static void rtl_pll_power_up(struct rtl8169_private
*tp
)
3743 rtl_generic_op(tp
, tp
->pll_power_ops
.up
);
3746 static void __devinit
rtl_init_pll_power_ops(struct rtl8169_private
*tp
)
3748 struct pll_power_ops
*ops
= &tp
->pll_power_ops
;
3750 switch (tp
->mac_version
) {
3751 case RTL_GIGA_MAC_VER_07
:
3752 case RTL_GIGA_MAC_VER_08
:
3753 case RTL_GIGA_MAC_VER_09
:
3754 case RTL_GIGA_MAC_VER_10
:
3755 case RTL_GIGA_MAC_VER_16
:
3756 case RTL_GIGA_MAC_VER_29
:
3757 case RTL_GIGA_MAC_VER_30
:
3758 ops
->down
= r810x_pll_power_down
;
3759 ops
->up
= r810x_pll_power_up
;
3762 case RTL_GIGA_MAC_VER_11
:
3763 case RTL_GIGA_MAC_VER_12
:
3764 case RTL_GIGA_MAC_VER_17
:
3765 case RTL_GIGA_MAC_VER_18
:
3766 case RTL_GIGA_MAC_VER_19
:
3767 case RTL_GIGA_MAC_VER_20
:
3768 case RTL_GIGA_MAC_VER_21
:
3769 case RTL_GIGA_MAC_VER_22
:
3770 case RTL_GIGA_MAC_VER_23
:
3771 case RTL_GIGA_MAC_VER_24
:
3772 case RTL_GIGA_MAC_VER_25
:
3773 case RTL_GIGA_MAC_VER_26
:
3774 case RTL_GIGA_MAC_VER_27
:
3775 case RTL_GIGA_MAC_VER_28
:
3776 case RTL_GIGA_MAC_VER_31
:
3777 case RTL_GIGA_MAC_VER_32
:
3778 case RTL_GIGA_MAC_VER_33
:
3779 case RTL_GIGA_MAC_VER_34
:
3780 case RTL_GIGA_MAC_VER_35
:
3781 case RTL_GIGA_MAC_VER_36
:
3782 ops
->down
= r8168_pll_power_down
;
3783 ops
->up
= r8168_pll_power_up
;
3793 static void rtl_init_rxcfg(struct rtl8169_private
*tp
)
3795 void __iomem
*ioaddr
= tp
->mmio_addr
;
3797 switch (tp
->mac_version
) {
3798 case RTL_GIGA_MAC_VER_01
:
3799 case RTL_GIGA_MAC_VER_02
:
3800 case RTL_GIGA_MAC_VER_03
:
3801 case RTL_GIGA_MAC_VER_04
:
3802 case RTL_GIGA_MAC_VER_05
:
3803 case RTL_GIGA_MAC_VER_06
:
3804 case RTL_GIGA_MAC_VER_10
:
3805 case RTL_GIGA_MAC_VER_11
:
3806 case RTL_GIGA_MAC_VER_12
:
3807 case RTL_GIGA_MAC_VER_13
:
3808 case RTL_GIGA_MAC_VER_14
:
3809 case RTL_GIGA_MAC_VER_15
:
3810 case RTL_GIGA_MAC_VER_16
:
3811 case RTL_GIGA_MAC_VER_17
:
3812 RTL_W32(RxConfig
, RX_FIFO_THRESH
| RX_DMA_BURST
);
3814 case RTL_GIGA_MAC_VER_18
:
3815 case RTL_GIGA_MAC_VER_19
:
3816 case RTL_GIGA_MAC_VER_20
:
3817 case RTL_GIGA_MAC_VER_21
:
3818 case RTL_GIGA_MAC_VER_22
:
3819 case RTL_GIGA_MAC_VER_23
:
3820 case RTL_GIGA_MAC_VER_24
:
3821 RTL_W32(RxConfig
, RX128_INT_EN
| RX_MULTI_EN
| RX_DMA_BURST
);
3824 RTL_W32(RxConfig
, RX128_INT_EN
| RX_DMA_BURST
);
3829 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
3831 tp
->dirty_tx
= tp
->dirty_rx
= tp
->cur_tx
= tp
->cur_rx
= 0;
3834 static void rtl_hw_jumbo_enable(struct rtl8169_private
*tp
)
3836 rtl_generic_op(tp
, tp
->jumbo_ops
.enable
);
3839 static void rtl_hw_jumbo_disable(struct rtl8169_private
*tp
)
3841 rtl_generic_op(tp
, tp
->jumbo_ops
.disable
);
3844 static void r8168c_hw_jumbo_enable(struct rtl8169_private
*tp
)
3846 void __iomem
*ioaddr
= tp
->mmio_addr
;
3848 RTL_W8(Config3
, RTL_R8(Config3
) | Jumbo_En0
);
3849 RTL_W8(Config4
, RTL_R8(Config4
) | Jumbo_En1
);
3850 rtl_tx_performance_tweak(tp
->pci_dev
, 0x2 << MAX_READ_REQUEST_SHIFT
);
3853 static void r8168c_hw_jumbo_disable(struct rtl8169_private
*tp
)
3855 void __iomem
*ioaddr
= tp
->mmio_addr
;
3857 RTL_W8(Config3
, RTL_R8(Config3
) & ~Jumbo_En0
);
3858 RTL_W8(Config4
, RTL_R8(Config4
) & ~Jumbo_En1
);
3859 rtl_tx_performance_tweak(tp
->pci_dev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3862 static void r8168dp_hw_jumbo_enable(struct rtl8169_private
*tp
)
3864 void __iomem
*ioaddr
= tp
->mmio_addr
;
3866 RTL_W8(Config3
, RTL_R8(Config3
) | Jumbo_En0
);
3869 static void r8168dp_hw_jumbo_disable(struct rtl8169_private
*tp
)
3871 void __iomem
*ioaddr
= tp
->mmio_addr
;
3873 RTL_W8(Config3
, RTL_R8(Config3
) & ~Jumbo_En0
);
3876 static void r8168e_hw_jumbo_enable(struct rtl8169_private
*tp
)
3878 void __iomem
*ioaddr
= tp
->mmio_addr
;
3880 RTL_W8(MaxTxPacketSize
, 0x3f);
3881 RTL_W8(Config3
, RTL_R8(Config3
) | Jumbo_En0
);
3882 RTL_W8(Config4
, RTL_R8(Config4
) | 0x01);
3883 rtl_tx_performance_tweak(tp
->pci_dev
, 0x2 << MAX_READ_REQUEST_SHIFT
);
3886 static void r8168e_hw_jumbo_disable(struct rtl8169_private
*tp
)
3888 void __iomem
*ioaddr
= tp
->mmio_addr
;
3890 RTL_W8(MaxTxPacketSize
, 0x0c);
3891 RTL_W8(Config3
, RTL_R8(Config3
) & ~Jumbo_En0
);
3892 RTL_W8(Config4
, RTL_R8(Config4
) & ~0x01);
3893 rtl_tx_performance_tweak(tp
->pci_dev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3896 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private
*tp
)
3898 rtl_tx_performance_tweak(tp
->pci_dev
,
3899 (0x2 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
3902 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private
*tp
)
3904 rtl_tx_performance_tweak(tp
->pci_dev
,
3905 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
3908 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private
*tp
)
3910 void __iomem
*ioaddr
= tp
->mmio_addr
;
3912 r8168b_0_hw_jumbo_enable(tp
);
3914 RTL_W8(Config4
, RTL_R8(Config4
) | (1 << 0));
3917 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private
*tp
)
3919 void __iomem
*ioaddr
= tp
->mmio_addr
;
3921 r8168b_0_hw_jumbo_disable(tp
);
3923 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
3926 static void __devinit
rtl_init_jumbo_ops(struct rtl8169_private
*tp
)
3928 struct jumbo_ops
*ops
= &tp
->jumbo_ops
;
3930 switch (tp
->mac_version
) {
3931 case RTL_GIGA_MAC_VER_11
:
3932 ops
->disable
= r8168b_0_hw_jumbo_disable
;
3933 ops
->enable
= r8168b_0_hw_jumbo_enable
;
3935 case RTL_GIGA_MAC_VER_12
:
3936 case RTL_GIGA_MAC_VER_17
:
3937 ops
->disable
= r8168b_1_hw_jumbo_disable
;
3938 ops
->enable
= r8168b_1_hw_jumbo_enable
;
3940 case RTL_GIGA_MAC_VER_18
: /* Wild guess. Needs info from Realtek. */
3941 case RTL_GIGA_MAC_VER_19
:
3942 case RTL_GIGA_MAC_VER_20
:
3943 case RTL_GIGA_MAC_VER_21
: /* Wild guess. Needs info from Realtek. */
3944 case RTL_GIGA_MAC_VER_22
:
3945 case RTL_GIGA_MAC_VER_23
:
3946 case RTL_GIGA_MAC_VER_24
:
3947 case RTL_GIGA_MAC_VER_25
:
3948 case RTL_GIGA_MAC_VER_26
:
3949 ops
->disable
= r8168c_hw_jumbo_disable
;
3950 ops
->enable
= r8168c_hw_jumbo_enable
;
3952 case RTL_GIGA_MAC_VER_27
:
3953 case RTL_GIGA_MAC_VER_28
:
3954 ops
->disable
= r8168dp_hw_jumbo_disable
;
3955 ops
->enable
= r8168dp_hw_jumbo_enable
;
3957 case RTL_GIGA_MAC_VER_31
: /* Wild guess. Needs info from Realtek. */
3958 case RTL_GIGA_MAC_VER_32
:
3959 case RTL_GIGA_MAC_VER_33
:
3960 case RTL_GIGA_MAC_VER_34
:
3961 ops
->disable
= r8168e_hw_jumbo_disable
;
3962 ops
->enable
= r8168e_hw_jumbo_enable
;
3966 * No action needed for jumbo frames with 8169.
3967 * No jumbo for 810x at all.
3970 ops
->disable
= NULL
;
3976 static void rtl_hw_reset(struct rtl8169_private
*tp
)
3978 void __iomem
*ioaddr
= tp
->mmio_addr
;
3981 /* Soft reset the chip. */
3982 RTL_W8(ChipCmd
, CmdReset
);
3984 /* Check that the chip has finished the reset. */
3985 for (i
= 0; i
< 100; i
++) {
3986 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
3992 static int __devinit
3993 rtl8169_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
3995 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
3996 const unsigned int region
= cfg
->region
;
3997 struct rtl8169_private
*tp
;
3998 struct mii_if_info
*mii
;
3999 struct net_device
*dev
;
4000 void __iomem
*ioaddr
;
4004 if (netif_msg_drv(&debug
)) {
4005 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
4006 MODULENAME
, RTL8169_VERSION
);
4009 dev
= alloc_etherdev(sizeof (*tp
));
4015 SET_NETDEV_DEV(dev
, &pdev
->dev
);
4016 dev
->netdev_ops
= &rtl8169_netdev_ops
;
4017 tp
= netdev_priv(dev
);
4020 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
4024 mii
->mdio_read
= rtl_mdio_read
;
4025 mii
->mdio_write
= rtl_mdio_write
;
4026 mii
->phy_id_mask
= 0x1f;
4027 mii
->reg_num_mask
= 0x1f;
4028 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
4030 /* disable ASPM completely as that cause random device stop working
4031 * problems as well as full system hangs for some PCIe devices users */
4032 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
| PCIE_LINK_STATE_L1
|
4033 PCIE_LINK_STATE_CLKPM
);
4035 /* enable device (incl. PCI PM wakeup and hotplug setup) */
4036 rc
= pci_enable_device(pdev
);
4038 netif_err(tp
, probe
, dev
, "enable failure\n");
4039 goto err_out_free_dev_1
;
4042 if (pci_set_mwi(pdev
) < 0)
4043 netif_info(tp
, probe
, dev
, "Mem-Wr-Inval unavailable\n");
4045 /* make sure PCI base addr 1 is MMIO */
4046 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
4047 netif_err(tp
, probe
, dev
,
4048 "region #%d not an MMIO resource, aborting\n",
4054 /* check for weird/broken PCI region reporting */
4055 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
4056 netif_err(tp
, probe
, dev
,
4057 "Invalid PCI region size(s), aborting\n");
4062 rc
= pci_request_regions(pdev
, MODULENAME
);
4064 netif_err(tp
, probe
, dev
, "could not request regions\n");
4068 tp
->cp_cmd
= RxChkSum
;
4070 if ((sizeof(dma_addr_t
) > 4) &&
4071 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) && use_dac
) {
4072 tp
->cp_cmd
|= PCIDAC
;
4073 dev
->features
|= NETIF_F_HIGHDMA
;
4075 rc
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
4077 netif_err(tp
, probe
, dev
, "DMA configuration failed\n");
4078 goto err_out_free_res_3
;
4082 /* ioremap MMIO region */
4083 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
4085 netif_err(tp
, probe
, dev
, "cannot remap MMIO, aborting\n");
4087 goto err_out_free_res_3
;
4089 tp
->mmio_addr
= ioaddr
;
4091 if (!pci_is_pcie(pdev
))
4092 netif_info(tp
, probe
, dev
, "not PCI Express\n");
4094 /* Identify chip attached to board */
4095 rtl8169_get_mac_version(tp
, dev
, cfg
->default_ver
);
4099 rtl_irq_disable(tp
);
4103 rtl_ack_events(tp
, 0xffff);
4105 pci_set_master(pdev
);
4108 * Pretend we are using VLANs; This bypasses a nasty bug where
4109 * Interrupts stop flowing on high load on 8110SCd controllers.
4111 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
4112 tp
->cp_cmd
|= RxVlan
;
4114 rtl_init_mdio_ops(tp
);
4115 rtl_init_pll_power_ops(tp
);
4116 rtl_init_jumbo_ops(tp
);
4118 rtl8169_print_mac_version(tp
);
4120 chipset
= tp
->mac_version
;
4121 tp
->txd_version
= rtl_chip_infos
[chipset
].txd_version
;
4123 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4124 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
4125 RTL_W8(Config5
, RTL_R8(Config5
) & PMEStatus
);
4126 if ((RTL_R8(Config3
) & (LinkUp
| MagicPacket
)) != 0)
4127 tp
->features
|= RTL_FEATURE_WOL
;
4128 if ((RTL_R8(Config5
) & (UWF
| BWF
| MWF
)) != 0)
4129 tp
->features
|= RTL_FEATURE_WOL
;
4130 tp
->features
|= rtl_try_msi(tp
, cfg
);
4131 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4133 if (rtl_tbi_enabled(tp
)) {
4134 tp
->set_speed
= rtl8169_set_speed_tbi
;
4135 tp
->get_settings
= rtl8169_gset_tbi
;
4136 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
4137 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
4138 tp
->link_ok
= rtl8169_tbi_link_ok
;
4139 tp
->do_ioctl
= rtl_tbi_ioctl
;
4141 tp
->set_speed
= rtl8169_set_speed_xmii
;
4142 tp
->get_settings
= rtl8169_gset_xmii
;
4143 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
4144 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
4145 tp
->link_ok
= rtl8169_xmii_link_ok
;
4146 tp
->do_ioctl
= rtl_xmii_ioctl
;
4149 mutex_init(&tp
->wk
.mutex
);
4151 /* Get MAC address */
4152 for (i
= 0; i
< ETH_ALEN
; i
++)
4153 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
4154 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
4156 SET_ETHTOOL_OPS(dev
, &rtl8169_ethtool_ops
);
4157 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
4158 dev
->irq
= pdev
->irq
;
4159 dev
->base_addr
= (unsigned long) ioaddr
;
4161 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, R8169_NAPI_WEIGHT
);
4163 /* don't enable SG, IP_CSUM and TSO by default - it might not work
4164 * properly for all devices */
4165 dev
->features
|= NETIF_F_RXCSUM
|
4166 NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
4168 dev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
4169 NETIF_F_RXCSUM
| NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
4170 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
4173 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
4174 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
4175 dev
->hw_features
&= ~NETIF_F_HW_VLAN_RX
;
4177 tp
->hw_start
= cfg
->hw_start
;
4178 tp
->event_slow
= cfg
->event_slow
;
4180 tp
->opts1_mask
= (tp
->mac_version
!= RTL_GIGA_MAC_VER_01
) ?
4181 ~(RxBOVF
| RxFOVF
) : ~0;
4183 init_timer(&tp
->timer
);
4184 tp
->timer
.data
= (unsigned long) dev
;
4185 tp
->timer
.function
= rtl8169_phy_timer
;
4187 tp
->rtl_fw
= RTL_FIRMWARE_UNKNOWN
;
4189 rc
= register_netdev(dev
);
4193 pci_set_drvdata(pdev
, dev
);
4195 netif_info(tp
, probe
, dev
, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
4196 rtl_chip_infos
[chipset
].name
, dev
->base_addr
, dev
->dev_addr
,
4197 (u32
)(RTL_R32(TxConfig
) & 0x9cf0f8ff), dev
->irq
);
4198 if (rtl_chip_infos
[chipset
].jumbo_max
!= JUMBO_1K
) {
4199 netif_info(tp
, probe
, dev
, "jumbo features [frames: %d bytes, "
4200 "tx checksumming: %s]\n",
4201 rtl_chip_infos
[chipset
].jumbo_max
,
4202 rtl_chip_infos
[chipset
].jumbo_tx_csum
? "ok" : "ko");
4205 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
4206 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
4207 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
4208 rtl8168_driver_start(tp
);
4211 device_set_wakeup_enable(&pdev
->dev
, tp
->features
& RTL_FEATURE_WOL
);
4213 if (pci_dev_run_wake(pdev
))
4214 pm_runtime_put_noidle(&pdev
->dev
);
4216 netif_carrier_off(dev
);
4222 rtl_disable_msi(pdev
, tp
);
4225 pci_release_regions(pdev
);
4227 pci_clear_mwi(pdev
);
4228 pci_disable_device(pdev
);
4234 static void __devexit
rtl8169_remove_one(struct pci_dev
*pdev
)
4236 struct net_device
*dev
= pci_get_drvdata(pdev
);
4237 struct rtl8169_private
*tp
= netdev_priv(dev
);
4239 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
4240 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
4241 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
4242 rtl8168_driver_stop(tp
);
4245 cancel_work_sync(&tp
->wk
.work
);
4247 unregister_netdev(dev
);
4249 rtl_release_firmware(tp
);
4251 if (pci_dev_run_wake(pdev
))
4252 pm_runtime_get_noresume(&pdev
->dev
);
4254 /* restore original MAC address */
4255 rtl_rar_set(tp
, dev
->perm_addr
);
4257 rtl_disable_msi(pdev
, tp
);
4258 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
4259 pci_set_drvdata(pdev
, NULL
);
4262 static void rtl_request_uncached_firmware(struct rtl8169_private
*tp
)
4264 struct rtl_fw
*rtl_fw
;
4268 name
= rtl_lookup_firmware_name(tp
);
4270 goto out_no_firmware
;
4272 rtl_fw
= kzalloc(sizeof(*rtl_fw
), GFP_KERNEL
);
4276 rc
= request_firmware(&rtl_fw
->fw
, name
, &tp
->pci_dev
->dev
);
4280 rc
= rtl_check_firmware(tp
, rtl_fw
);
4282 goto err_release_firmware
;
4284 tp
->rtl_fw
= rtl_fw
;
4288 err_release_firmware
:
4289 release_firmware(rtl_fw
->fw
);
4293 netif_warn(tp
, ifup
, tp
->dev
, "unable to load firmware patch %s (%d)\n",
4300 static void rtl_request_firmware(struct rtl8169_private
*tp
)
4302 if (IS_ERR(tp
->rtl_fw
))
4303 rtl_request_uncached_firmware(tp
);
4306 static void rtl_task(struct work_struct
*);
4308 static int rtl8169_open(struct net_device
*dev
)
4310 struct rtl8169_private
*tp
= netdev_priv(dev
);
4311 void __iomem
*ioaddr
= tp
->mmio_addr
;
4312 struct pci_dev
*pdev
= tp
->pci_dev
;
4313 int retval
= -ENOMEM
;
4315 pm_runtime_get_sync(&pdev
->dev
);
4318 * Rx and Tx desscriptors needs 256 bytes alignment.
4319 * dma_alloc_coherent provides more.
4321 tp
->TxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
,
4322 &tp
->TxPhyAddr
, GFP_KERNEL
);
4323 if (!tp
->TxDescArray
)
4324 goto err_pm_runtime_put
;
4326 tp
->RxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
,
4327 &tp
->RxPhyAddr
, GFP_KERNEL
);
4328 if (!tp
->RxDescArray
)
4331 retval
= rtl8169_init_ring(dev
);
4335 INIT_WORK(&tp
->wk
.work
, rtl_task
);
4339 rtl_request_firmware(tp
);
4341 retval
= request_irq(dev
->irq
, rtl8169_interrupt
,
4342 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
4345 goto err_release_fw_2
;
4349 set_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
4351 napi_enable(&tp
->napi
);
4353 rtl8169_init_phy(dev
, tp
);
4355 __rtl8169_set_features(dev
, dev
->features
);
4357 rtl_pll_power_up(tp
);
4361 netif_start_queue(dev
);
4363 rtl_unlock_work(tp
);
4365 tp
->saved_wolopts
= 0;
4366 pm_runtime_put_noidle(&pdev
->dev
);
4368 rtl8169_check_link_status(dev
, tp
, ioaddr
);
4373 rtl_release_firmware(tp
);
4374 rtl8169_rx_clear(tp
);
4376 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
4378 tp
->RxDescArray
= NULL
;
4380 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
4382 tp
->TxDescArray
= NULL
;
4384 pm_runtime_put_noidle(&pdev
->dev
);
4388 static void rtl_rx_close(struct rtl8169_private
*tp
)
4390 void __iomem
*ioaddr
= tp
->mmio_addr
;
4392 RTL_W32(RxConfig
, RTL_R32(RxConfig
) & ~RX_CONFIG_ACCEPT_MASK
);
4395 static void rtl8169_hw_reset(struct rtl8169_private
*tp
)
4397 void __iomem
*ioaddr
= tp
->mmio_addr
;
4399 /* Disable interrupts */
4400 rtl8169_irq_mask_and_ack(tp
);
4404 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
4405 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
4406 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
4407 while (RTL_R8(TxPoll
) & NPQ
)
4409 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
||
4410 tp
->mac_version
== RTL_GIGA_MAC_VER_35
||
4411 tp
->mac_version
== RTL_GIGA_MAC_VER_36
) {
4412 RTL_W8(ChipCmd
, RTL_R8(ChipCmd
) | StopReq
);
4413 while (!(RTL_R32(TxConfig
) & TXCFG_EMPTY
))
4416 RTL_W8(ChipCmd
, RTL_R8(ChipCmd
) | StopReq
);
4423 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
4425 void __iomem
*ioaddr
= tp
->mmio_addr
;
4427 /* Set DMA burst size and Interframe Gap Time */
4428 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
4429 (InterFrameGap
<< TxInterFrameGapShift
));
4432 static void rtl_hw_start(struct net_device
*dev
)
4434 struct rtl8169_private
*tp
= netdev_priv(dev
);
4438 rtl_irq_enable_all(tp
);
4441 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
4442 void __iomem
*ioaddr
)
4445 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4446 * register to be written before TxDescAddrLow to work.
4447 * Switching from MMIO to I/O access fixes the issue as well.
4449 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
4450 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_BIT_MASK(32));
4451 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
4452 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_BIT_MASK(32));
4455 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
4459 cmd
= RTL_R16(CPlusCmd
);
4460 RTL_W16(CPlusCmd
, cmd
);
4464 static void rtl_set_rx_max_size(void __iomem
*ioaddr
, unsigned int rx_buf_sz
)
4466 /* Low hurts. Let's disable the filtering. */
4467 RTL_W16(RxMaxSize
, rx_buf_sz
+ 1);
4470 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
4472 static const struct rtl_cfg2_info
{
4477 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
4478 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
4479 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
4480 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
4482 const struct rtl_cfg2_info
*p
= cfg2_info
;
4486 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
4487 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
4488 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
4489 RTL_W32(0x7c, p
->val
);
4495 static void rtl_hw_start_8169(struct net_device
*dev
)
4497 struct rtl8169_private
*tp
= netdev_priv(dev
);
4498 void __iomem
*ioaddr
= tp
->mmio_addr
;
4499 struct pci_dev
*pdev
= tp
->pci_dev
;
4501 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
4502 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
4503 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
4506 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4507 if (tp
->mac_version
== RTL_GIGA_MAC_VER_01
||
4508 tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
4509 tp
->mac_version
== RTL_GIGA_MAC_VER_03
||
4510 tp
->mac_version
== RTL_GIGA_MAC_VER_04
)
4511 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4515 RTL_W8(EarlyTxThres
, NoEarlyTx
);
4517 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
4519 if (tp
->mac_version
== RTL_GIGA_MAC_VER_01
||
4520 tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
4521 tp
->mac_version
== RTL_GIGA_MAC_VER_03
||
4522 tp
->mac_version
== RTL_GIGA_MAC_VER_04
)
4523 rtl_set_rx_tx_config_registers(tp
);
4525 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
4527 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
4528 tp
->mac_version
== RTL_GIGA_MAC_VER_03
) {
4529 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4530 "Bit-3 and bit-14 MUST be 1\n");
4531 tp
->cp_cmd
|= (1 << 14);
4534 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4536 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
4539 * Undocumented corner. Supposedly:
4540 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4542 RTL_W16(IntrMitigate
, 0x0000);
4544 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
4546 if (tp
->mac_version
!= RTL_GIGA_MAC_VER_01
&&
4547 tp
->mac_version
!= RTL_GIGA_MAC_VER_02
&&
4548 tp
->mac_version
!= RTL_GIGA_MAC_VER_03
&&
4549 tp
->mac_version
!= RTL_GIGA_MAC_VER_04
) {
4550 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4551 rtl_set_rx_tx_config_registers(tp
);
4554 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4556 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4559 RTL_W32(RxMissed
, 0);
4561 rtl_set_rx_mode(dev
);
4563 /* no early-rx interrupts */
4564 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
4567 static void rtl_csi_access_enable(void __iomem
*ioaddr
, u32 bits
)
4571 csi
= rtl_csi_read(ioaddr
, 0x070c) & 0x00ffffff;
4572 rtl_csi_write(ioaddr
, 0x070c, csi
| bits
);
4575 static void rtl_csi_access_enable_1(void __iomem
*ioaddr
)
4577 rtl_csi_access_enable(ioaddr
, 0x17000000);
4580 static void rtl_csi_access_enable_2(void __iomem
*ioaddr
)
4582 rtl_csi_access_enable(ioaddr
, 0x27000000);
4586 unsigned int offset
;
4591 static void rtl_ephy_init(void __iomem
*ioaddr
, const struct ephy_info
*e
, int len
)
4596 w
= (rtl_ephy_read(ioaddr
, e
->offset
) & ~e
->mask
) | e
->bits
;
4597 rtl_ephy_write(ioaddr
, e
->offset
, w
);
4602 static void rtl_disable_clock_request(struct pci_dev
*pdev
)
4604 int cap
= pci_pcie_cap(pdev
);
4609 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
4610 ctl
&= ~PCI_EXP_LNKCTL_CLKREQ_EN
;
4611 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
4615 static void rtl_enable_clock_request(struct pci_dev
*pdev
)
4617 int cap
= pci_pcie_cap(pdev
);
4622 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
4623 ctl
|= PCI_EXP_LNKCTL_CLKREQ_EN
;
4624 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
4628 #define R8168_CPCMD_QUIRK_MASK (\
4639 static void rtl_hw_start_8168bb(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4641 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4643 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4645 rtl_tx_performance_tweak(pdev
,
4646 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
4649 static void rtl_hw_start_8168bef(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4651 rtl_hw_start_8168bb(ioaddr
, pdev
);
4653 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4655 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
4658 static void __rtl_hw_start_8168cp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4660 RTL_W8(Config1
, RTL_R8(Config1
) | Speed_down
);
4662 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4664 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4666 rtl_disable_clock_request(pdev
);
4668 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4671 static void rtl_hw_start_8168cp_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4673 static const struct ephy_info e_info_8168cp
[] = {
4674 { 0x01, 0, 0x0001 },
4675 { 0x02, 0x0800, 0x1000 },
4676 { 0x03, 0, 0x0042 },
4677 { 0x06, 0x0080, 0x0000 },
4681 rtl_csi_access_enable_2(ioaddr
);
4683 rtl_ephy_init(ioaddr
, e_info_8168cp
, ARRAY_SIZE(e_info_8168cp
));
4685 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4688 static void rtl_hw_start_8168cp_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4690 rtl_csi_access_enable_2(ioaddr
);
4692 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4694 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4696 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4699 static void rtl_hw_start_8168cp_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4701 rtl_csi_access_enable_2(ioaddr
);
4703 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4706 RTL_W8(DBG_REG
, 0x20);
4708 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4710 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4712 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4715 static void rtl_hw_start_8168c_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4717 static const struct ephy_info e_info_8168c_1
[] = {
4718 { 0x02, 0x0800, 0x1000 },
4719 { 0x03, 0, 0x0002 },
4720 { 0x06, 0x0080, 0x0000 }
4723 rtl_csi_access_enable_2(ioaddr
);
4725 RTL_W8(DBG_REG
, 0x06 | FIX_NAK_1
| FIX_NAK_2
);
4727 rtl_ephy_init(ioaddr
, e_info_8168c_1
, ARRAY_SIZE(e_info_8168c_1
));
4729 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4732 static void rtl_hw_start_8168c_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4734 static const struct ephy_info e_info_8168c_2
[] = {
4735 { 0x01, 0, 0x0001 },
4736 { 0x03, 0x0400, 0x0220 }
4739 rtl_csi_access_enable_2(ioaddr
);
4741 rtl_ephy_init(ioaddr
, e_info_8168c_2
, ARRAY_SIZE(e_info_8168c_2
));
4743 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4746 static void rtl_hw_start_8168c_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4748 rtl_hw_start_8168c_2(ioaddr
, pdev
);
4751 static void rtl_hw_start_8168c_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4753 rtl_csi_access_enable_2(ioaddr
);
4755 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4758 static void rtl_hw_start_8168d(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4760 rtl_csi_access_enable_2(ioaddr
);
4762 rtl_disable_clock_request(pdev
);
4764 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4766 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4768 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4771 static void rtl_hw_start_8168dp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4773 rtl_csi_access_enable_1(ioaddr
);
4775 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4777 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4779 rtl_disable_clock_request(pdev
);
4782 static void rtl_hw_start_8168d_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4784 static const struct ephy_info e_info_8168d_4
[] = {
4786 { 0x19, 0x20, 0x50 },
4791 rtl_csi_access_enable_1(ioaddr
);
4793 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4795 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4797 for (i
= 0; i
< ARRAY_SIZE(e_info_8168d_4
); i
++) {
4798 const struct ephy_info
*e
= e_info_8168d_4
+ i
;
4801 w
= rtl_ephy_read(ioaddr
, e
->offset
);
4802 rtl_ephy_write(ioaddr
, 0x03, (w
& e
->mask
) | e
->bits
);
4805 rtl_enable_clock_request(pdev
);
4808 static void rtl_hw_start_8168e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4810 static const struct ephy_info e_info_8168e_1
[] = {
4811 { 0x00, 0x0200, 0x0100 },
4812 { 0x00, 0x0000, 0x0004 },
4813 { 0x06, 0x0002, 0x0001 },
4814 { 0x06, 0x0000, 0x0030 },
4815 { 0x07, 0x0000, 0x2000 },
4816 { 0x00, 0x0000, 0x0020 },
4817 { 0x03, 0x5800, 0x2000 },
4818 { 0x03, 0x0000, 0x0001 },
4819 { 0x01, 0x0800, 0x1000 },
4820 { 0x07, 0x0000, 0x4000 },
4821 { 0x1e, 0x0000, 0x2000 },
4822 { 0x19, 0xffff, 0xfe6c },
4823 { 0x0a, 0x0000, 0x0040 }
4826 rtl_csi_access_enable_2(ioaddr
);
4828 rtl_ephy_init(ioaddr
, e_info_8168e_1
, ARRAY_SIZE(e_info_8168e_1
));
4830 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4832 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4834 rtl_disable_clock_request(pdev
);
4836 /* Reset tx FIFO pointer */
4837 RTL_W32(MISC
, RTL_R32(MISC
) | TXPLA_RST
);
4838 RTL_W32(MISC
, RTL_R32(MISC
) & ~TXPLA_RST
);
4840 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
4843 static void rtl_hw_start_8168e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4845 static const struct ephy_info e_info_8168e_2
[] = {
4846 { 0x09, 0x0000, 0x0080 },
4847 { 0x19, 0x0000, 0x0224 }
4850 rtl_csi_access_enable_1(ioaddr
);
4852 rtl_ephy_init(ioaddr
, e_info_8168e_2
, ARRAY_SIZE(e_info_8168e_2
));
4854 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4856 rtl_eri_write(ioaddr
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4857 rtl_eri_write(ioaddr
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4858 rtl_eri_write(ioaddr
, 0xc8, ERIAR_MASK_1111
, 0x00100002, ERIAR_EXGMAC
);
4859 rtl_eri_write(ioaddr
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
4860 rtl_eri_write(ioaddr
, 0xcc, ERIAR_MASK_1111
, 0x00000050, ERIAR_EXGMAC
);
4861 rtl_eri_write(ioaddr
, 0xd0, ERIAR_MASK_1111
, 0x07ff0060, ERIAR_EXGMAC
);
4862 rtl_w1w0_eri(ioaddr
, 0x1b0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
4863 rtl_w1w0_eri(ioaddr
, 0x0d4, ERIAR_MASK_0011
, 0x0c00, 0xff00,
4866 RTL_W8(MaxTxPacketSize
, EarlySize
);
4868 rtl_disable_clock_request(pdev
);
4870 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
4871 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
4873 /* Adjust EEE LED frequency */
4874 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
4876 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
4877 RTL_W32(MISC
, RTL_R32(MISC
) | PWM_EN
);
4878 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
4881 static void rtl_hw_start_8168f_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4883 static const struct ephy_info e_info_8168f_1
[] = {
4884 { 0x06, 0x00c0, 0x0020 },
4885 { 0x08, 0x0001, 0x0002 },
4886 { 0x09, 0x0000, 0x0080 },
4887 { 0x19, 0x0000, 0x0224 }
4890 rtl_csi_access_enable_1(ioaddr
);
4892 rtl_ephy_init(ioaddr
, e_info_8168f_1
, ARRAY_SIZE(e_info_8168f_1
));
4894 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4896 rtl_eri_write(ioaddr
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4897 rtl_eri_write(ioaddr
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4898 rtl_eri_write(ioaddr
, 0xc8, ERIAR_MASK_1111
, 0x00100002, ERIAR_EXGMAC
);
4899 rtl_eri_write(ioaddr
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
4900 rtl_w1w0_eri(ioaddr
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01, ERIAR_EXGMAC
);
4901 rtl_w1w0_eri(ioaddr
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00, ERIAR_EXGMAC
);
4902 rtl_w1w0_eri(ioaddr
, 0x1b0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
4903 rtl_w1w0_eri(ioaddr
, 0x1d0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
4904 rtl_eri_write(ioaddr
, 0xcc, ERIAR_MASK_1111
, 0x00000050, ERIAR_EXGMAC
);
4905 rtl_eri_write(ioaddr
, 0xd0, ERIAR_MASK_1111
, 0x00000060, ERIAR_EXGMAC
);
4906 rtl_w1w0_eri(ioaddr
, 0x0d4, ERIAR_MASK_0011
, 0x0c00, 0xff00,
4909 RTL_W8(MaxTxPacketSize
, EarlySize
);
4911 rtl_disable_clock_request(pdev
);
4913 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
4914 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
4916 /* Adjust EEE LED frequency */
4917 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
4919 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
4920 RTL_W32(MISC
, RTL_R32(MISC
) | PWM_EN
);
4921 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
4924 static void rtl_hw_start_8168(struct net_device
*dev
)
4926 struct rtl8169_private
*tp
= netdev_priv(dev
);
4927 void __iomem
*ioaddr
= tp
->mmio_addr
;
4928 struct pci_dev
*pdev
= tp
->pci_dev
;
4930 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4932 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4934 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
4936 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
4938 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4940 RTL_W16(IntrMitigate
, 0x5151);
4942 /* Work around for RxFIFO overflow. */
4943 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
) {
4944 tp
->event_slow
|= RxFIFOOver
| PCSTimeout
;
4945 tp
->event_slow
&= ~RxOverflow
;
4948 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
4950 rtl_set_rx_mode(dev
);
4952 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
4953 (InterFrameGap
<< TxInterFrameGapShift
));
4957 switch (tp
->mac_version
) {
4958 case RTL_GIGA_MAC_VER_11
:
4959 rtl_hw_start_8168bb(ioaddr
, pdev
);
4962 case RTL_GIGA_MAC_VER_12
:
4963 case RTL_GIGA_MAC_VER_17
:
4964 rtl_hw_start_8168bef(ioaddr
, pdev
);
4967 case RTL_GIGA_MAC_VER_18
:
4968 rtl_hw_start_8168cp_1(ioaddr
, pdev
);
4971 case RTL_GIGA_MAC_VER_19
:
4972 rtl_hw_start_8168c_1(ioaddr
, pdev
);
4975 case RTL_GIGA_MAC_VER_20
:
4976 rtl_hw_start_8168c_2(ioaddr
, pdev
);
4979 case RTL_GIGA_MAC_VER_21
:
4980 rtl_hw_start_8168c_3(ioaddr
, pdev
);
4983 case RTL_GIGA_MAC_VER_22
:
4984 rtl_hw_start_8168c_4(ioaddr
, pdev
);
4987 case RTL_GIGA_MAC_VER_23
:
4988 rtl_hw_start_8168cp_2(ioaddr
, pdev
);
4991 case RTL_GIGA_MAC_VER_24
:
4992 rtl_hw_start_8168cp_3(ioaddr
, pdev
);
4995 case RTL_GIGA_MAC_VER_25
:
4996 case RTL_GIGA_MAC_VER_26
:
4997 case RTL_GIGA_MAC_VER_27
:
4998 rtl_hw_start_8168d(ioaddr
, pdev
);
5001 case RTL_GIGA_MAC_VER_28
:
5002 rtl_hw_start_8168d_4(ioaddr
, pdev
);
5005 case RTL_GIGA_MAC_VER_31
:
5006 rtl_hw_start_8168dp(ioaddr
, pdev
);
5009 case RTL_GIGA_MAC_VER_32
:
5010 case RTL_GIGA_MAC_VER_33
:
5011 rtl_hw_start_8168e_1(ioaddr
, pdev
);
5013 case RTL_GIGA_MAC_VER_34
:
5014 rtl_hw_start_8168e_2(ioaddr
, pdev
);
5017 case RTL_GIGA_MAC_VER_35
:
5018 case RTL_GIGA_MAC_VER_36
:
5019 rtl_hw_start_8168f_1(ioaddr
, pdev
);
5023 printk(KERN_ERR PFX
"%s: unknown chipset (mac_version = %d).\n",
5024 dev
->name
, tp
->mac_version
);
5028 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
5030 RTL_W8(Cfg9346
, Cfg9346_Lock
);
5032 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
5035 #define R810X_CPCMD_QUIRK_MASK (\
5046 static void rtl_hw_start_8102e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
5048 static const struct ephy_info e_info_8102e_1
[] = {
5049 { 0x01, 0, 0x6e65 },
5050 { 0x02, 0, 0x091f },
5051 { 0x03, 0, 0xc2f9 },
5052 { 0x06, 0, 0xafb5 },
5053 { 0x07, 0, 0x0e00 },
5054 { 0x19, 0, 0xec80 },
5055 { 0x01, 0, 0x2e65 },
5060 rtl_csi_access_enable_2(ioaddr
);
5062 RTL_W8(DBG_REG
, FIX_NAK_1
);
5064 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5067 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
5068 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
5070 cfg1
= RTL_R8(Config1
);
5071 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
5072 RTL_W8(Config1
, cfg1
& ~LEDS0
);
5074 rtl_ephy_init(ioaddr
, e_info_8102e_1
, ARRAY_SIZE(e_info_8102e_1
));
5077 static void rtl_hw_start_8102e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
5079 rtl_csi_access_enable_2(ioaddr
);
5081 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5083 RTL_W8(Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
5084 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
5087 static void rtl_hw_start_8102e_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
5089 rtl_hw_start_8102e_2(ioaddr
, pdev
);
5091 rtl_ephy_write(ioaddr
, 0x03, 0xc2f9);
5094 static void rtl_hw_start_8105e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
5096 static const struct ephy_info e_info_8105e_1
[] = {
5097 { 0x07, 0, 0x4000 },
5098 { 0x19, 0, 0x0200 },
5099 { 0x19, 0, 0x0020 },
5100 { 0x1e, 0, 0x2000 },
5101 { 0x03, 0, 0x0001 },
5102 { 0x19, 0, 0x0100 },
5103 { 0x19, 0, 0x0004 },
5107 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5108 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) | 0x002800);
5110 /* Disable Early Tally Counter */
5111 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) & ~0x010000);
5113 RTL_W8(MCU
, RTL_R8(MCU
) | EN_NDP
| EN_OOB_RESET
);
5114 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
5116 rtl_ephy_init(ioaddr
, e_info_8105e_1
, ARRAY_SIZE(e_info_8105e_1
));
5119 static void rtl_hw_start_8105e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
5121 rtl_hw_start_8105e_1(ioaddr
, pdev
);
5122 rtl_ephy_write(ioaddr
, 0x1e, rtl_ephy_read(ioaddr
, 0x1e) | 0x8000);
5125 static void rtl_hw_start_8101(struct net_device
*dev
)
5127 struct rtl8169_private
*tp
= netdev_priv(dev
);
5128 void __iomem
*ioaddr
= tp
->mmio_addr
;
5129 struct pci_dev
*pdev
= tp
->pci_dev
;
5131 if (tp
->mac_version
>= RTL_GIGA_MAC_VER_30
)
5132 tp
->event_slow
&= ~RxFIFOOver
;
5134 if (tp
->mac_version
== RTL_GIGA_MAC_VER_13
||
5135 tp
->mac_version
== RTL_GIGA_MAC_VER_16
) {
5136 int cap
= pci_pcie_cap(pdev
);
5139 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
,
5140 PCI_EXP_DEVCTL_NOSNOOP_EN
);
5144 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
5146 switch (tp
->mac_version
) {
5147 case RTL_GIGA_MAC_VER_07
:
5148 rtl_hw_start_8102e_1(ioaddr
, pdev
);
5151 case RTL_GIGA_MAC_VER_08
:
5152 rtl_hw_start_8102e_3(ioaddr
, pdev
);
5155 case RTL_GIGA_MAC_VER_09
:
5156 rtl_hw_start_8102e_2(ioaddr
, pdev
);
5159 case RTL_GIGA_MAC_VER_29
:
5160 rtl_hw_start_8105e_1(ioaddr
, pdev
);
5162 case RTL_GIGA_MAC_VER_30
:
5163 rtl_hw_start_8105e_2(ioaddr
, pdev
);
5167 RTL_W8(Cfg9346
, Cfg9346_Lock
);
5169 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
5171 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
5173 tp
->cp_cmd
&= ~R810X_CPCMD_QUIRK_MASK
;
5174 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
5176 RTL_W16(IntrMitigate
, 0x0000);
5178 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
5180 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
5181 rtl_set_rx_tx_config_registers(tp
);
5185 rtl_set_rx_mode(dev
);
5187 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
5190 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
5192 struct rtl8169_private
*tp
= netdev_priv(dev
);
5194 if (new_mtu
< ETH_ZLEN
||
5195 new_mtu
> rtl_chip_infos
[tp
->mac_version
].jumbo_max
)
5198 if (new_mtu
> ETH_DATA_LEN
)
5199 rtl_hw_jumbo_enable(tp
);
5201 rtl_hw_jumbo_disable(tp
);
5204 netdev_update_features(dev
);
5209 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
5211 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
5212 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
5215 static void rtl8169_free_rx_databuff(struct rtl8169_private
*tp
,
5216 void **data_buff
, struct RxDesc
*desc
)
5218 dma_unmap_single(&tp
->pci_dev
->dev
, le64_to_cpu(desc
->addr
), rx_buf_sz
,
5223 rtl8169_make_unusable_by_asic(desc
);
5226 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
5228 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
5230 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
5233 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
5236 desc
->addr
= cpu_to_le64(mapping
);
5238 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5241 static inline void *rtl8169_align(void *data
)
5243 return (void *)ALIGN((long)data
, 16);
5246 static struct sk_buff
*rtl8169_alloc_rx_data(struct rtl8169_private
*tp
,
5247 struct RxDesc
*desc
)
5251 struct device
*d
= &tp
->pci_dev
->dev
;
5252 struct net_device
*dev
= tp
->dev
;
5253 int node
= dev
->dev
.parent
? dev_to_node(dev
->dev
.parent
) : -1;
5255 data
= kmalloc_node(rx_buf_sz
, GFP_KERNEL
, node
);
5259 if (rtl8169_align(data
) != data
) {
5261 data
= kmalloc_node(rx_buf_sz
+ 15, GFP_KERNEL
, node
);
5266 mapping
= dma_map_single(d
, rtl8169_align(data
), rx_buf_sz
,
5268 if (unlikely(dma_mapping_error(d
, mapping
))) {
5269 if (net_ratelimit())
5270 netif_err(tp
, drv
, tp
->dev
, "Failed to map RX DMA!\n");
5274 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
5282 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
5286 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
5287 if (tp
->Rx_databuff
[i
]) {
5288 rtl8169_free_rx_databuff(tp
, tp
->Rx_databuff
+ i
,
5289 tp
->RxDescArray
+ i
);
5294 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
5296 desc
->opts1
|= cpu_to_le32(RingEnd
);
5299 static int rtl8169_rx_fill(struct rtl8169_private
*tp
)
5303 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
5306 if (tp
->Rx_databuff
[i
])
5309 data
= rtl8169_alloc_rx_data(tp
, tp
->RxDescArray
+ i
);
5311 rtl8169_make_unusable_by_asic(tp
->RxDescArray
+ i
);
5314 tp
->Rx_databuff
[i
] = data
;
5317 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
5321 rtl8169_rx_clear(tp
);
5325 static int rtl8169_init_ring(struct net_device
*dev
)
5327 struct rtl8169_private
*tp
= netdev_priv(dev
);
5329 rtl8169_init_ring_indexes(tp
);
5331 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
5332 memset(tp
->Rx_databuff
, 0x0, NUM_RX_DESC
* sizeof(void *));
5334 return rtl8169_rx_fill(tp
);
5337 static void rtl8169_unmap_tx_skb(struct device
*d
, struct ring_info
*tx_skb
,
5338 struct TxDesc
*desc
)
5340 unsigned int len
= tx_skb
->len
;
5342 dma_unmap_single(d
, le64_to_cpu(desc
->addr
), len
, DMA_TO_DEVICE
);
5350 static void rtl8169_tx_clear_range(struct rtl8169_private
*tp
, u32 start
,
5355 for (i
= 0; i
< n
; i
++) {
5356 unsigned int entry
= (start
+ i
) % NUM_TX_DESC
;
5357 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
5358 unsigned int len
= tx_skb
->len
;
5361 struct sk_buff
*skb
= tx_skb
->skb
;
5363 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
5364 tp
->TxDescArray
+ entry
);
5366 tp
->dev
->stats
.tx_dropped
++;
5374 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
5376 rtl8169_tx_clear_range(tp
, tp
->dirty_tx
, NUM_TX_DESC
);
5377 tp
->cur_tx
= tp
->dirty_tx
= 0;
5380 static void rtl_reset_work(struct rtl8169_private
*tp
)
5382 struct net_device
*dev
= tp
->dev
;
5385 napi_disable(&tp
->napi
);
5386 netif_stop_queue(dev
);
5387 synchronize_sched();
5389 rtl8169_hw_reset(tp
);
5391 for (i
= 0; i
< NUM_RX_DESC
; i
++)
5392 rtl8169_mark_to_asic(tp
->RxDescArray
+ i
, rx_buf_sz
);
5394 rtl8169_tx_clear(tp
);
5395 rtl8169_init_ring_indexes(tp
);
5397 napi_enable(&tp
->napi
);
5399 netif_wake_queue(dev
);
5400 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
5403 static void rtl8169_tx_timeout(struct net_device
*dev
)
5405 struct rtl8169_private
*tp
= netdev_priv(dev
);
5407 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
5410 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
5413 struct skb_shared_info
*info
= skb_shinfo(skb
);
5414 unsigned int cur_frag
, entry
;
5415 struct TxDesc
* uninitialized_var(txd
);
5416 struct device
*d
= &tp
->pci_dev
->dev
;
5419 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
5420 const skb_frag_t
*frag
= info
->frags
+ cur_frag
;
5425 entry
= (entry
+ 1) % NUM_TX_DESC
;
5427 txd
= tp
->TxDescArray
+ entry
;
5428 len
= skb_frag_size(frag
);
5429 addr
= skb_frag_address(frag
);
5430 mapping
= dma_map_single(d
, addr
, len
, DMA_TO_DEVICE
);
5431 if (unlikely(dma_mapping_error(d
, mapping
))) {
5432 if (net_ratelimit())
5433 netif_err(tp
, drv
, tp
->dev
,
5434 "Failed to map TX fragments DMA!\n");
5438 /* Anti gcc 2.95.3 bugware (sic) */
5439 status
= opts
[0] | len
|
5440 (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
5442 txd
->opts1
= cpu_to_le32(status
);
5443 txd
->opts2
= cpu_to_le32(opts
[1]);
5444 txd
->addr
= cpu_to_le64(mapping
);
5446 tp
->tx_skb
[entry
].len
= len
;
5450 tp
->tx_skb
[entry
].skb
= skb
;
5451 txd
->opts1
|= cpu_to_le32(LastFrag
);
5457 rtl8169_tx_clear_range(tp
, tp
->cur_tx
+ 1, cur_frag
);
5461 static inline void rtl8169_tso_csum(struct rtl8169_private
*tp
,
5462 struct sk_buff
*skb
, u32
*opts
)
5464 const struct rtl_tx_desc_info
*info
= tx_desc_info
+ tp
->txd_version
;
5465 u32 mss
= skb_shinfo(skb
)->gso_size
;
5466 int offset
= info
->opts_offset
;
5470 opts
[offset
] |= min(mss
, TD_MSS_MAX
) << info
->mss_shift
;
5471 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5472 const struct iphdr
*ip
= ip_hdr(skb
);
5474 if (ip
->protocol
== IPPROTO_TCP
)
5475 opts
[offset
] |= info
->checksum
.tcp
;
5476 else if (ip
->protocol
== IPPROTO_UDP
)
5477 opts
[offset
] |= info
->checksum
.udp
;
5483 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
5484 struct net_device
*dev
)
5486 struct rtl8169_private
*tp
= netdev_priv(dev
);
5487 unsigned int entry
= tp
->cur_tx
% NUM_TX_DESC
;
5488 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
5489 void __iomem
*ioaddr
= tp
->mmio_addr
;
5490 struct device
*d
= &tp
->pci_dev
->dev
;
5496 if (unlikely(TX_BUFFS_AVAIL(tp
) < skb_shinfo(skb
)->nr_frags
)) {
5497 netif_err(tp
, drv
, dev
, "BUG! Tx Ring full when queue awake!\n");
5501 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
5504 len
= skb_headlen(skb
);
5505 mapping
= dma_map_single(d
, skb
->data
, len
, DMA_TO_DEVICE
);
5506 if (unlikely(dma_mapping_error(d
, mapping
))) {
5507 if (net_ratelimit())
5508 netif_err(tp
, drv
, dev
, "Failed to map TX DMA!\n");
5512 tp
->tx_skb
[entry
].len
= len
;
5513 txd
->addr
= cpu_to_le64(mapping
);
5515 opts
[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp
, skb
));
5518 rtl8169_tso_csum(tp
, skb
, opts
);
5520 frags
= rtl8169_xmit_frags(tp
, skb
, opts
);
5524 opts
[0] |= FirstFrag
;
5526 opts
[0] |= FirstFrag
| LastFrag
;
5527 tp
->tx_skb
[entry
].skb
= skb
;
5530 txd
->opts2
= cpu_to_le32(opts
[1]);
5534 /* Anti gcc 2.95.3 bugware (sic) */
5535 status
= opts
[0] | len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
5536 txd
->opts1
= cpu_to_le32(status
);
5538 tp
->cur_tx
+= frags
+ 1;
5542 RTL_W8(TxPoll
, NPQ
);
5546 if (TX_BUFFS_AVAIL(tp
) < MAX_SKB_FRAGS
) {
5547 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5548 * not miss a ring update when it notices a stopped queue.
5551 netif_stop_queue(dev
);
5552 /* Sync with rtl_tx:
5553 * - publish queue status and cur_tx ring index (write barrier)
5554 * - refresh dirty_tx ring index (read barrier).
5555 * May the current thread have a pessimistic view of the ring
5556 * status and forget to wake up queue, a racing rtl_tx thread
5560 if (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)
5561 netif_wake_queue(dev
);
5564 return NETDEV_TX_OK
;
5567 rtl8169_unmap_tx_skb(d
, tp
->tx_skb
+ entry
, txd
);
5570 dev
->stats
.tx_dropped
++;
5571 return NETDEV_TX_OK
;
5574 netif_stop_queue(dev
);
5575 dev
->stats
.tx_dropped
++;
5576 return NETDEV_TX_BUSY
;
5579 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
5581 struct rtl8169_private
*tp
= netdev_priv(dev
);
5582 struct pci_dev
*pdev
= tp
->pci_dev
;
5583 u16 pci_status
, pci_cmd
;
5585 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
5586 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
5588 netif_err(tp
, intr
, dev
, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5589 pci_cmd
, pci_status
);
5592 * The recovery sequence below admits a very elaborated explanation:
5593 * - it seems to work;
5594 * - I did not see what else could be done;
5595 * - it makes iop3xx happy.
5597 * Feel free to adjust to your needs.
5599 if (pdev
->broken_parity_status
)
5600 pci_cmd
&= ~PCI_COMMAND_PARITY
;
5602 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
5604 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
5606 pci_write_config_word(pdev
, PCI_STATUS
,
5607 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
5608 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
5609 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
5611 /* The infamous DAC f*ckup only happens at boot time */
5612 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->dirty_rx
&& !tp
->cur_rx
) {
5613 void __iomem
*ioaddr
= tp
->mmio_addr
;
5615 netif_info(tp
, intr
, dev
, "disabling PCI DAC\n");
5616 tp
->cp_cmd
&= ~PCIDAC
;
5617 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
5618 dev
->features
&= ~NETIF_F_HIGHDMA
;
5621 rtl8169_hw_reset(tp
);
5623 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
5626 static void rtl_tx(struct net_device
*dev
, struct rtl8169_private
*tp
)
5628 unsigned int dirty_tx
, tx_left
;
5630 dirty_tx
= tp
->dirty_tx
;
5632 tx_left
= tp
->cur_tx
- dirty_tx
;
5634 while (tx_left
> 0) {
5635 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
5636 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
5640 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
5641 if (status
& DescOwn
)
5644 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
5645 tp
->TxDescArray
+ entry
);
5646 if (status
& LastFrag
) {
5647 dev
->stats
.tx_packets
++;
5648 dev
->stats
.tx_bytes
+= tx_skb
->skb
->len
;
5649 dev_kfree_skb(tx_skb
->skb
);
5656 if (tp
->dirty_tx
!= dirty_tx
) {
5657 tp
->dirty_tx
= dirty_tx
;
5658 /* Sync with rtl8169_start_xmit:
5659 * - publish dirty_tx ring index (write barrier)
5660 * - refresh cur_tx ring index and queue status (read barrier)
5661 * May the current thread miss the stopped queue condition,
5662 * a racing xmit thread can only have a right view of the
5666 if (netif_queue_stopped(dev
) &&
5667 (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)) {
5668 netif_wake_queue(dev
);
5671 * 8168 hack: TxPoll requests are lost when the Tx packets are
5672 * too close. Let's kick an extra TxPoll request when a burst
5673 * of start_xmit activity is detected (if it is not detected,
5674 * it is slow enough). -- FR
5676 if (tp
->cur_tx
!= dirty_tx
) {
5677 void __iomem
*ioaddr
= tp
->mmio_addr
;
5679 RTL_W8(TxPoll
, NPQ
);
5684 static inline int rtl8169_fragmented_frame(u32 status
)
5686 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
5689 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, u32 opts1
)
5691 u32 status
= opts1
& RxProtoMask
;
5693 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
5694 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)))
5695 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
5697 skb_checksum_none_assert(skb
);
5700 static struct sk_buff
*rtl8169_try_rx_copy(void *data
,
5701 struct rtl8169_private
*tp
,
5705 struct sk_buff
*skb
;
5706 struct device
*d
= &tp
->pci_dev
->dev
;
5708 data
= rtl8169_align(data
);
5709 dma_sync_single_for_cpu(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
5711 skb
= netdev_alloc_skb_ip_align(tp
->dev
, pkt_size
);
5713 memcpy(skb
->data
, data
, pkt_size
);
5714 dma_sync_single_for_device(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
5719 static int rtl_rx(struct net_device
*dev
, struct rtl8169_private
*tp
, u32 budget
)
5721 unsigned int cur_rx
, rx_left
;
5724 cur_rx
= tp
->cur_rx
;
5725 rx_left
= NUM_RX_DESC
+ tp
->dirty_rx
- cur_rx
;
5726 rx_left
= min(rx_left
, budget
);
5728 for (; rx_left
> 0; rx_left
--, cur_rx
++) {
5729 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
5730 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
5734 status
= le32_to_cpu(desc
->opts1
) & tp
->opts1_mask
;
5736 if (status
& DescOwn
)
5738 if (unlikely(status
& RxRES
)) {
5739 netif_info(tp
, rx_err
, dev
, "Rx ERROR. status = %08x\n",
5741 dev
->stats
.rx_errors
++;
5742 if (status
& (RxRWT
| RxRUNT
))
5743 dev
->stats
.rx_length_errors
++;
5745 dev
->stats
.rx_crc_errors
++;
5746 if (status
& RxFOVF
) {
5747 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
5748 dev
->stats
.rx_fifo_errors
++;
5750 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5752 struct sk_buff
*skb
;
5753 dma_addr_t addr
= le64_to_cpu(desc
->addr
);
5754 int pkt_size
= (status
& 0x00003fff) - 4;
5757 * The driver does not support incoming fragmented
5758 * frames. They are seen as a symptom of over-mtu
5761 if (unlikely(rtl8169_fragmented_frame(status
))) {
5762 dev
->stats
.rx_dropped
++;
5763 dev
->stats
.rx_length_errors
++;
5764 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5768 skb
= rtl8169_try_rx_copy(tp
->Rx_databuff
[entry
],
5769 tp
, pkt_size
, addr
);
5770 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5772 dev
->stats
.rx_dropped
++;
5776 rtl8169_rx_csum(skb
, status
);
5777 skb_put(skb
, pkt_size
);
5778 skb
->protocol
= eth_type_trans(skb
, dev
);
5780 rtl8169_rx_vlan_tag(desc
, skb
);
5782 napi_gro_receive(&tp
->napi
, skb
);
5784 dev
->stats
.rx_bytes
+= pkt_size
;
5785 dev
->stats
.rx_packets
++;
5788 /* Work around for AMD plateform. */
5789 if ((desc
->opts2
& cpu_to_le32(0xfffe000)) &&
5790 (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)) {
5796 count
= cur_rx
- tp
->cur_rx
;
5797 tp
->cur_rx
= cur_rx
;
5799 tp
->dirty_rx
+= count
;
5804 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
5806 struct net_device
*dev
= dev_instance
;
5807 struct rtl8169_private
*tp
= netdev_priv(dev
);
5811 status
= rtl_get_events(tp
);
5812 if (status
&& status
!= 0xffff) {
5813 status
&= RTL_EVENT_NAPI
| tp
->event_slow
;
5817 rtl_irq_disable(tp
);
5818 napi_schedule(&tp
->napi
);
5821 return IRQ_RETVAL(handled
);
5825 * Workqueue context.
5827 static void rtl_slow_event_work(struct rtl8169_private
*tp
)
5829 struct net_device
*dev
= tp
->dev
;
5832 status
= rtl_get_events(tp
) & tp
->event_slow
;
5833 rtl_ack_events(tp
, status
);
5835 if (unlikely(status
& RxFIFOOver
)) {
5836 switch (tp
->mac_version
) {
5837 /* Work around for rx fifo overflow */
5838 case RTL_GIGA_MAC_VER_11
:
5839 netif_stop_queue(dev
);
5840 /* XXX - Hack alert. See rtl_task(). */
5841 set_bit(RTL_FLAG_TASK_RESET_PENDING
, tp
->wk
.flags
);
5847 if (unlikely(status
& SYSErr
))
5848 rtl8169_pcierr_interrupt(dev
);
5850 if (status
& LinkChg
)
5851 __rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
, true);
5853 napi_disable(&tp
->napi
);
5854 rtl_irq_disable(tp
);
5856 napi_enable(&tp
->napi
);
5857 napi_schedule(&tp
->napi
);
5860 static void rtl_task(struct work_struct
*work
)
5862 static const struct {
5864 void (*action
)(struct rtl8169_private
*);
5866 /* XXX - keep rtl_slow_event_work() as first element. */
5867 { RTL_FLAG_TASK_SLOW_PENDING
, rtl_slow_event_work
},
5868 { RTL_FLAG_TASK_RESET_PENDING
, rtl_reset_work
},
5869 { RTL_FLAG_TASK_PHY_PENDING
, rtl_phy_work
}
5871 struct rtl8169_private
*tp
=
5872 container_of(work
, struct rtl8169_private
, wk
.work
);
5873 struct net_device
*dev
= tp
->dev
;
5878 if (!netif_running(dev
) ||
5879 !test_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
))
5882 for (i
= 0; i
< ARRAY_SIZE(rtl_work
); i
++) {
5885 pending
= test_and_clear_bit(rtl_work
[i
].bitnr
, tp
->wk
.flags
);
5887 rtl_work
[i
].action(tp
);
5891 rtl_unlock_work(tp
);
5894 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
5896 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
5897 struct net_device
*dev
= tp
->dev
;
5898 u16 enable_mask
= RTL_EVENT_NAPI
| tp
->event_slow
;
5902 status
= rtl_get_events(tp
);
5903 rtl_ack_events(tp
, status
& ~tp
->event_slow
);
5905 if (status
& RTL_EVENT_NAPI_RX
)
5906 work_done
= rtl_rx(dev
, tp
, (u32
) budget
);
5908 if (status
& RTL_EVENT_NAPI_TX
)
5911 if (status
& tp
->event_slow
) {
5912 enable_mask
&= ~tp
->event_slow
;
5914 rtl_schedule_task(tp
, RTL_FLAG_TASK_SLOW_PENDING
);
5917 if (work_done
< budget
) {
5918 napi_complete(napi
);
5920 rtl_irq_enable(tp
, enable_mask
);
5927 static void rtl8169_rx_missed(struct net_device
*dev
, void __iomem
*ioaddr
)
5929 struct rtl8169_private
*tp
= netdev_priv(dev
);
5931 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
5934 dev
->stats
.rx_missed_errors
+= (RTL_R32(RxMissed
) & 0xffffff);
5935 RTL_W32(RxMissed
, 0);
5938 static void rtl8169_down(struct net_device
*dev
)
5940 struct rtl8169_private
*tp
= netdev_priv(dev
);
5941 void __iomem
*ioaddr
= tp
->mmio_addr
;
5943 del_timer_sync(&tp
->timer
);
5945 napi_disable(&tp
->napi
);
5946 netif_stop_queue(dev
);
5948 rtl8169_hw_reset(tp
);
5950 * At this point device interrupts can not be enabled in any function,
5951 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
5952 * and napi is disabled (rtl8169_poll).
5954 rtl8169_rx_missed(dev
, ioaddr
);
5956 /* Give a racing hard_start_xmit a few cycles to complete. */
5957 synchronize_sched();
5959 rtl8169_tx_clear(tp
);
5961 rtl8169_rx_clear(tp
);
5963 rtl_pll_power_down(tp
);
5966 static int rtl8169_close(struct net_device
*dev
)
5968 struct rtl8169_private
*tp
= netdev_priv(dev
);
5969 struct pci_dev
*pdev
= tp
->pci_dev
;
5971 pm_runtime_get_sync(&pdev
->dev
);
5973 /* Update counters before going down */
5974 rtl8169_update_counters(dev
);
5977 clear_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
5980 rtl_unlock_work(tp
);
5982 free_irq(dev
->irq
, dev
);
5984 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
5986 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
5988 tp
->TxDescArray
= NULL
;
5989 tp
->RxDescArray
= NULL
;
5991 pm_runtime_put_sync(&pdev
->dev
);
5996 static void rtl_set_rx_mode(struct net_device
*dev
)
5998 struct rtl8169_private
*tp
= netdev_priv(dev
);
5999 void __iomem
*ioaddr
= tp
->mmio_addr
;
6000 u32 mc_filter
[2]; /* Multicast hash filter */
6004 if (dev
->flags
& IFF_PROMISC
) {
6005 /* Unconditionally log net taps. */
6006 netif_notice(tp
, link
, dev
, "Promiscuous mode enabled\n");
6008 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
6010 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
6011 } else if ((netdev_mc_count(dev
) > multicast_filter_limit
) ||
6012 (dev
->flags
& IFF_ALLMULTI
)) {
6013 /* Too many to filter perfectly -- accept all multicasts. */
6014 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
6015 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
6017 struct netdev_hw_addr
*ha
;
6019 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
6020 mc_filter
[1] = mc_filter
[0] = 0;
6021 netdev_for_each_mc_addr(ha
, dev
) {
6022 int bit_nr
= ether_crc(ETH_ALEN
, ha
->addr
) >> 26;
6023 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
6024 rx_mode
|= AcceptMulticast
;
6028 tmp
= (RTL_R32(RxConfig
) & ~RX_CONFIG_ACCEPT_MASK
) | rx_mode
;
6030 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
6031 u32 data
= mc_filter
[0];
6033 mc_filter
[0] = swab32(mc_filter
[1]);
6034 mc_filter
[1] = swab32(data
);
6037 RTL_W32(MAR0
+ 4, mc_filter
[1]);
6038 RTL_W32(MAR0
+ 0, mc_filter
[0]);
6040 RTL_W32(RxConfig
, tmp
);
6044 * rtl8169_get_stats - Get rtl8169 read/write statistics
6045 * @dev: The Ethernet Device to get statistics for
6047 * Get TX/RX statistics for rtl8169
6049 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
)
6051 struct rtl8169_private
*tp
= netdev_priv(dev
);
6052 void __iomem
*ioaddr
= tp
->mmio_addr
;
6054 if (netif_running(dev
))
6055 rtl8169_rx_missed(dev
, ioaddr
);
6060 static void rtl8169_net_suspend(struct net_device
*dev
)
6062 struct rtl8169_private
*tp
= netdev_priv(dev
);
6064 if (!netif_running(dev
))
6067 netif_device_detach(dev
);
6068 netif_stop_queue(dev
);
6071 napi_disable(&tp
->napi
);
6072 clear_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
6073 rtl_unlock_work(tp
);
6075 rtl_pll_power_down(tp
);
6080 static int rtl8169_suspend(struct device
*device
)
6082 struct pci_dev
*pdev
= to_pci_dev(device
);
6083 struct net_device
*dev
= pci_get_drvdata(pdev
);
6085 rtl8169_net_suspend(dev
);
6090 static void __rtl8169_resume(struct net_device
*dev
)
6092 struct rtl8169_private
*tp
= netdev_priv(dev
);
6094 netif_device_attach(dev
);
6096 rtl_pll_power_up(tp
);
6098 set_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
6100 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
6103 static int rtl8169_resume(struct device
*device
)
6105 struct pci_dev
*pdev
= to_pci_dev(device
);
6106 struct net_device
*dev
= pci_get_drvdata(pdev
);
6107 struct rtl8169_private
*tp
= netdev_priv(dev
);
6109 rtl8169_init_phy(dev
, tp
);
6111 if (netif_running(dev
))
6112 __rtl8169_resume(dev
);
6117 static int rtl8169_runtime_suspend(struct device
*device
)
6119 struct pci_dev
*pdev
= to_pci_dev(device
);
6120 struct net_device
*dev
= pci_get_drvdata(pdev
);
6121 struct rtl8169_private
*tp
= netdev_priv(dev
);
6123 if (!tp
->TxDescArray
)
6127 tp
->saved_wolopts
= __rtl8169_get_wol(tp
);
6128 __rtl8169_set_wol(tp
, WAKE_ANY
);
6129 rtl_unlock_work(tp
);
6131 rtl8169_net_suspend(dev
);
6136 static int rtl8169_runtime_resume(struct device
*device
)
6138 struct pci_dev
*pdev
= to_pci_dev(device
);
6139 struct net_device
*dev
= pci_get_drvdata(pdev
);
6140 struct rtl8169_private
*tp
= netdev_priv(dev
);
6142 if (!tp
->TxDescArray
)
6146 __rtl8169_set_wol(tp
, tp
->saved_wolopts
);
6147 tp
->saved_wolopts
= 0;
6148 rtl_unlock_work(tp
);
6150 rtl8169_init_phy(dev
, tp
);
6152 __rtl8169_resume(dev
);
6157 static int rtl8169_runtime_idle(struct device
*device
)
6159 struct pci_dev
*pdev
= to_pci_dev(device
);
6160 struct net_device
*dev
= pci_get_drvdata(pdev
);
6161 struct rtl8169_private
*tp
= netdev_priv(dev
);
6163 return tp
->TxDescArray
? -EBUSY
: 0;
6166 static const struct dev_pm_ops rtl8169_pm_ops
= {
6167 .suspend
= rtl8169_suspend
,
6168 .resume
= rtl8169_resume
,
6169 .freeze
= rtl8169_suspend
,
6170 .thaw
= rtl8169_resume
,
6171 .poweroff
= rtl8169_suspend
,
6172 .restore
= rtl8169_resume
,
6173 .runtime_suspend
= rtl8169_runtime_suspend
,
6174 .runtime_resume
= rtl8169_runtime_resume
,
6175 .runtime_idle
= rtl8169_runtime_idle
,
6178 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
6180 #else /* !CONFIG_PM */
6182 #define RTL8169_PM_OPS NULL
6184 #endif /* !CONFIG_PM */
6186 static void rtl_wol_shutdown_quirk(struct rtl8169_private
*tp
)
6188 void __iomem
*ioaddr
= tp
->mmio_addr
;
6190 /* WoL fails with 8168b when the receiver is disabled. */
6191 switch (tp
->mac_version
) {
6192 case RTL_GIGA_MAC_VER_11
:
6193 case RTL_GIGA_MAC_VER_12
:
6194 case RTL_GIGA_MAC_VER_17
:
6195 pci_clear_master(tp
->pci_dev
);
6197 RTL_W8(ChipCmd
, CmdRxEnb
);
6206 static void rtl_shutdown(struct pci_dev
*pdev
)
6208 struct net_device
*dev
= pci_get_drvdata(pdev
);
6209 struct rtl8169_private
*tp
= netdev_priv(dev
);
6211 rtl8169_net_suspend(dev
);
6213 /* Restore original MAC address */
6214 rtl_rar_set(tp
, dev
->perm_addr
);
6216 rtl8169_hw_reset(tp
);
6218 if (system_state
== SYSTEM_POWER_OFF
) {
6219 if (__rtl8169_get_wol(tp
) & WAKE_ANY
) {
6220 rtl_wol_suspend_quirk(tp
);
6221 rtl_wol_shutdown_quirk(tp
);
6224 pci_wake_from_d3(pdev
, true);
6225 pci_set_power_state(pdev
, PCI_D3hot
);
6229 static struct pci_driver rtl8169_pci_driver
= {
6231 .id_table
= rtl8169_pci_tbl
,
6232 .probe
= rtl8169_init_one
,
6233 .remove
= __devexit_p(rtl8169_remove_one
),
6234 .shutdown
= rtl_shutdown
,
6235 .driver
.pm
= RTL8169_PM_OPS
,
6238 static int __init
rtl8169_init_module(void)
6240 return pci_register_driver(&rtl8169_pci_driver
);
6243 static void __exit
rtl8169_cleanup_module(void)
6245 pci_unregister_driver(&rtl8169_pci_driver
);
6248 module_init(rtl8169_init_module
);
6249 module_exit(rtl8169_cleanup_module
);