1 // SPDX-License-Identifier: GPL-2.0-only
3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
7 * Copyright (c) a lot of people too. Please respect their work.
9 * See MAINTAINERS file for support contact information.
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/pci.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/ethtool.h>
20 #include <linux/phy.h>
21 #include <linux/if_vlan.h>
22 #include <linux/crc32.h>
26 #include <linux/tcp.h>
27 #include <linux/interrupt.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/firmware.h>
31 #include <linux/prefetch.h>
32 #include <linux/pci-aspm.h>
33 #include <linux/ipv6.h>
34 #include <net/ip6_checksum.h>
36 #define MODULENAME "r8169"
38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
53 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
54 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
55 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
56 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
58 #define R8169_MSG_DEFAULT \
59 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
61 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
62 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
63 static const int multicast_filter_limit
= 32;
65 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
66 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
68 #define R8169_REGS_SIZE 256
69 #define R8169_RX_BUF_SIZE (SZ_16K - 1)
70 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
71 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
72 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
73 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
75 /* write/read MMIO register */
76 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
77 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
78 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
79 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
80 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
81 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
84 RTL_GIGA_MAC_VER_01
= 0,
135 RTL_GIGA_MAC_NONE
= 0xff,
138 #define JUMBO_1K ETH_DATA_LEN
139 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
140 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
141 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
142 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
144 static const struct {
147 } rtl_chip_infos
[] = {
149 [RTL_GIGA_MAC_VER_01
] = {"RTL8169" },
150 [RTL_GIGA_MAC_VER_02
] = {"RTL8169s" },
151 [RTL_GIGA_MAC_VER_03
] = {"RTL8110s" },
152 [RTL_GIGA_MAC_VER_04
] = {"RTL8169sb/8110sb" },
153 [RTL_GIGA_MAC_VER_05
] = {"RTL8169sc/8110sc" },
154 [RTL_GIGA_MAC_VER_06
] = {"RTL8169sc/8110sc" },
156 [RTL_GIGA_MAC_VER_07
] = {"RTL8102e" },
157 [RTL_GIGA_MAC_VER_08
] = {"RTL8102e" },
158 [RTL_GIGA_MAC_VER_09
] = {"RTL8102e" },
159 [RTL_GIGA_MAC_VER_10
] = {"RTL8101e" },
160 [RTL_GIGA_MAC_VER_11
] = {"RTL8168b/8111b" },
161 [RTL_GIGA_MAC_VER_12
] = {"RTL8168b/8111b" },
162 [RTL_GIGA_MAC_VER_13
] = {"RTL8101e" },
163 [RTL_GIGA_MAC_VER_14
] = {"RTL8100e" },
164 [RTL_GIGA_MAC_VER_15
] = {"RTL8100e" },
165 [RTL_GIGA_MAC_VER_16
] = {"RTL8101e" },
166 [RTL_GIGA_MAC_VER_17
] = {"RTL8168b/8111b" },
167 [RTL_GIGA_MAC_VER_18
] = {"RTL8168cp/8111cp" },
168 [RTL_GIGA_MAC_VER_19
] = {"RTL8168c/8111c" },
169 [RTL_GIGA_MAC_VER_20
] = {"RTL8168c/8111c" },
170 [RTL_GIGA_MAC_VER_21
] = {"RTL8168c/8111c" },
171 [RTL_GIGA_MAC_VER_22
] = {"RTL8168c/8111c" },
172 [RTL_GIGA_MAC_VER_23
] = {"RTL8168cp/8111cp" },
173 [RTL_GIGA_MAC_VER_24
] = {"RTL8168cp/8111cp" },
174 [RTL_GIGA_MAC_VER_25
] = {"RTL8168d/8111d", FIRMWARE_8168D_1
},
175 [RTL_GIGA_MAC_VER_26
] = {"RTL8168d/8111d", FIRMWARE_8168D_2
},
176 [RTL_GIGA_MAC_VER_27
] = {"RTL8168dp/8111dp" },
177 [RTL_GIGA_MAC_VER_28
] = {"RTL8168dp/8111dp" },
178 [RTL_GIGA_MAC_VER_29
] = {"RTL8105e", FIRMWARE_8105E_1
},
179 [RTL_GIGA_MAC_VER_30
] = {"RTL8105e", FIRMWARE_8105E_1
},
180 [RTL_GIGA_MAC_VER_31
] = {"RTL8168dp/8111dp" },
181 [RTL_GIGA_MAC_VER_32
] = {"RTL8168e/8111e", FIRMWARE_8168E_1
},
182 [RTL_GIGA_MAC_VER_33
] = {"RTL8168e/8111e", FIRMWARE_8168E_2
},
183 [RTL_GIGA_MAC_VER_34
] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3
},
184 [RTL_GIGA_MAC_VER_35
] = {"RTL8168f/8111f", FIRMWARE_8168F_1
},
185 [RTL_GIGA_MAC_VER_36
] = {"RTL8168f/8111f", FIRMWARE_8168F_2
},
186 [RTL_GIGA_MAC_VER_37
] = {"RTL8402", FIRMWARE_8402_1
},
187 [RTL_GIGA_MAC_VER_38
] = {"RTL8411", FIRMWARE_8411_1
},
188 [RTL_GIGA_MAC_VER_39
] = {"RTL8106e", FIRMWARE_8106E_1
},
189 [RTL_GIGA_MAC_VER_40
] = {"RTL8168g/8111g", FIRMWARE_8168G_2
},
190 [RTL_GIGA_MAC_VER_41
] = {"RTL8168g/8111g" },
191 [RTL_GIGA_MAC_VER_42
] = {"RTL8168g/8111g", FIRMWARE_8168G_3
},
192 [RTL_GIGA_MAC_VER_43
] = {"RTL8106e", FIRMWARE_8106E_2
},
193 [RTL_GIGA_MAC_VER_44
] = {"RTL8411", FIRMWARE_8411_2
},
194 [RTL_GIGA_MAC_VER_45
] = {"RTL8168h/8111h", FIRMWARE_8168H_1
},
195 [RTL_GIGA_MAC_VER_46
] = {"RTL8168h/8111h", FIRMWARE_8168H_2
},
196 [RTL_GIGA_MAC_VER_47
] = {"RTL8107e", FIRMWARE_8107E_1
},
197 [RTL_GIGA_MAC_VER_48
] = {"RTL8107e", FIRMWARE_8107E_2
},
198 [RTL_GIGA_MAC_VER_49
] = {"RTL8168ep/8111ep" },
199 [RTL_GIGA_MAC_VER_50
] = {"RTL8168ep/8111ep" },
200 [RTL_GIGA_MAC_VER_51
] = {"RTL8168ep/8111ep" },
209 static const struct pci_device_id rtl8169_pci_tbl
[] = {
210 { PCI_VDEVICE(REALTEK
, 0x2502), RTL_CFG_1
},
211 { PCI_VDEVICE(REALTEK
, 0x2600), RTL_CFG_1
},
212 { PCI_VDEVICE(REALTEK
, 0x8129), RTL_CFG_0
},
213 { PCI_VDEVICE(REALTEK
, 0x8136), RTL_CFG_2
},
214 { PCI_VDEVICE(REALTEK
, 0x8161), RTL_CFG_1
},
215 { PCI_VDEVICE(REALTEK
, 0x8167), RTL_CFG_0
},
216 { PCI_VDEVICE(REALTEK
, 0x8168), RTL_CFG_1
},
217 { PCI_VDEVICE(NCUBE
, 0x8168), RTL_CFG_1
},
218 { PCI_VDEVICE(REALTEK
, 0x8169), RTL_CFG_0
},
219 { PCI_VENDOR_ID_DLINK
, 0x4300,
220 PCI_VENDOR_ID_DLINK
, 0x4b10, 0, 0, RTL_CFG_1
},
221 { PCI_VDEVICE(DLINK
, 0x4300), RTL_CFG_0
},
222 { PCI_VDEVICE(DLINK
, 0x4302), RTL_CFG_0
},
223 { PCI_VDEVICE(AT
, 0xc107), RTL_CFG_0
},
224 { PCI_VDEVICE(USR
, 0x0116), RTL_CFG_0
},
225 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
226 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
228 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
232 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
239 MAC0
= 0, /* Ethernet hardware address. */
241 MAR0
= 8, /* Multicast filter. */
242 CounterAddrLow
= 0x10,
243 CounterAddrHigh
= 0x14,
244 TxDescStartAddrLow
= 0x20,
245 TxDescStartAddrHigh
= 0x24,
246 TxHDescStartAddrLow
= 0x28,
247 TxHDescStartAddrHigh
= 0x2c,
256 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
257 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
260 #define RX128_INT_EN (1 << 15) /* 8111c and later */
261 #define RX_MULTI_EN (1 << 14) /* 8111c only */
262 #define RXCFG_FIFO_SHIFT 13
263 /* No threshold before first PCI xfer */
264 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
265 #define RX_EARLY_OFF (1 << 11)
266 #define RXCFG_DMA_SHIFT 8
267 /* Unlimited maximum PCI burst. */
268 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
275 #define PME_SIGNAL (1 << 5) /* 8168c and later */
287 #define RTL_COALESCE_MASK 0x0f
288 #define RTL_COALESCE_SHIFT 4
289 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
290 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
292 RxDescAddrLow
= 0xe4,
293 RxDescAddrHigh
= 0xe8,
294 EarlyTxThres
= 0xec, /* 8169. Unit of 32 bytes. */
296 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
298 MaxTxPacketSize
= 0xec, /* 8101/8168. Unit of 128 bytes. */
300 #define TxPacketMax (8064 >> 7)
301 #define EarlySize 0x27
304 FuncEventMask
= 0xf4,
305 FuncPresetState
= 0xf8,
310 FuncForceEvent
= 0xfc,
313 enum rtl8168_8101_registers
{
316 #define CSIAR_FLAG 0x80000000
317 #define CSIAR_WRITE_CMD 0x80000000
318 #define CSIAR_BYTE_ENABLE 0x0000f000
319 #define CSIAR_ADDR_MASK 0x00000fff
322 #define EPHYAR_FLAG 0x80000000
323 #define EPHYAR_WRITE_CMD 0x80000000
324 #define EPHYAR_REG_MASK 0x1f
325 #define EPHYAR_REG_SHIFT 16
326 #define EPHYAR_DATA_MASK 0xffff
328 #define PFM_EN (1 << 6)
329 #define TX_10M_PS_EN (1 << 7)
331 #define FIX_NAK_1 (1 << 4)
332 #define FIX_NAK_2 (1 << 3)
335 #define NOW_IS_OOB (1 << 7)
336 #define TX_EMPTY (1 << 5)
337 #define RX_EMPTY (1 << 4)
338 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
339 #define EN_NDP (1 << 3)
340 #define EN_OOB_RESET (1 << 2)
341 #define LINK_LIST_RDY (1 << 1)
343 #define EFUSEAR_FLAG 0x80000000
344 #define EFUSEAR_WRITE_CMD 0x80000000
345 #define EFUSEAR_READ_CMD 0x00000000
346 #define EFUSEAR_REG_MASK 0x03ff
347 #define EFUSEAR_REG_SHIFT 8
348 #define EFUSEAR_DATA_MASK 0xff
350 #define PFM_D3COLD_EN (1 << 6)
353 enum rtl8168_registers
{
358 #define ERIAR_FLAG 0x80000000
359 #define ERIAR_WRITE_CMD 0x80000000
360 #define ERIAR_READ_CMD 0x00000000
361 #define ERIAR_ADDR_BYTE_ALIGN 4
362 #define ERIAR_TYPE_SHIFT 16
363 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
364 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
365 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
366 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
367 #define ERIAR_MASK_SHIFT 12
368 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
369 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
370 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
371 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
372 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
373 EPHY_RXER_NUM
= 0x7c,
374 OCPDR
= 0xb0, /* OCP GPHY access */
375 #define OCPDR_WRITE_CMD 0x80000000
376 #define OCPDR_READ_CMD 0x00000000
377 #define OCPDR_REG_MASK 0x7f
378 #define OCPDR_GPHY_REG_SHIFT 16
379 #define OCPDR_DATA_MASK 0xffff
381 #define OCPAR_FLAG 0x80000000
382 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
383 #define OCPAR_GPHY_READ_CMD 0x0000f060
385 RDSAR1
= 0xd0, /* 8168c only. Undocumented on 8168dp */
386 MISC
= 0xf0, /* 8168e only. */
387 #define TXPLA_RST (1 << 29)
388 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
389 #define PWM_EN (1 << 22)
390 #define RXDV_GATED_EN (1 << 19)
391 #define EARLY_TALLY_EN (1 << 16)
394 enum rtl_register_content
{
395 /* InterruptStatusBits */
399 TxDescUnavail
= 0x0080,
423 /* TXPoll register p.5 */
424 HPQ
= 0x80, /* Poll cmd on the high prio queue */
425 NPQ
= 0x40, /* Poll cmd on the low prio queue */
426 FSWInt
= 0x01, /* Forced software interrupt */
430 Cfg9346_Unlock
= 0xc0,
435 AcceptBroadcast
= 0x08,
436 AcceptMulticast
= 0x04,
438 AcceptAllPhys
= 0x01,
439 #define RX_CONFIG_ACCEPT_MASK 0x3f
442 TxInterFrameGapShift
= 24,
443 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
445 /* Config1 register p.24 */
448 Speed_down
= (1 << 4),
452 PMEnable
= (1 << 0), /* Power Management Enable */
454 /* Config2 register p. 25 */
455 ClkReqEn
= (1 << 7), /* Clock Request Enable */
456 MSIEnable
= (1 << 5), /* 8169 only. Reserved in the 8168. */
457 PCI_Clock_66MHz
= 0x01,
458 PCI_Clock_33MHz
= 0x00,
460 /* Config3 register p.25 */
461 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
462 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
463 Jumbo_En0
= (1 << 2), /* 8168 only. Reserved in the 8168b */
464 Rdy_to_L23
= (1 << 1), /* L23 Enable */
465 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
467 /* Config4 register */
468 Jumbo_En1
= (1 << 1), /* 8168 only. Reserved in the 8168b */
470 /* Config5 register p.27 */
471 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
472 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
473 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
475 LanWake
= (1 << 1), /* LanWake enable/disable */
476 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
477 ASPM_en
= (1 << 0), /* ASPM enable */
480 EnableBist
= (1 << 15), // 8168 8101
481 Mac_dbgo_oe
= (1 << 14), // 8168 8101
482 Normal_mode
= (1 << 13), // unused
483 Force_half_dup
= (1 << 12), // 8168 8101
484 Force_rxflow_en
= (1 << 11), // 8168 8101
485 Force_txflow_en
= (1 << 10), // 8168 8101
486 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
487 ASF
= (1 << 8), // 8168 8101
488 PktCntrDisable
= (1 << 7), // 8168 8101
489 Mac_dbgo_sel
= 0x001c, // 8168
494 #define INTT_MASK GENMASK(1, 0)
496 /* rtl8169_PHYstatus */
507 TBILinkOK
= 0x02000000,
509 /* ResetCounterCommand */
512 /* DumpCounterCommand */
515 /* magic enable v2 */
516 MagicPacket_v2
= (1 << 16), /* Wake up when receives a Magic Packet */
520 /* First doubleword. */
521 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
522 RingEnd
= (1 << 30), /* End of descriptor ring */
523 FirstFrag
= (1 << 29), /* First segment of a packet */
524 LastFrag
= (1 << 28), /* Final segment of a packet */
528 enum rtl_tx_desc_bit
{
529 /* First doubleword. */
530 TD_LSO
= (1 << 27), /* Large Send Offload */
531 #define TD_MSS_MAX 0x07ffu /* MSS value */
533 /* Second doubleword. */
534 TxVlanTag
= (1 << 17), /* Add VLAN tag */
537 /* 8169, 8168b and 810x except 8102e. */
538 enum rtl_tx_desc_bit_0
{
539 /* First doubleword. */
540 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
541 TD0_TCP_CS
= (1 << 16), /* Calculate TCP/IP checksum */
542 TD0_UDP_CS
= (1 << 17), /* Calculate UDP/IP checksum */
543 TD0_IP_CS
= (1 << 18), /* Calculate IP checksum */
546 /* 8102e, 8168c and beyond. */
547 enum rtl_tx_desc_bit_1
{
548 /* First doubleword. */
549 TD1_GTSENV4
= (1 << 26), /* Giant Send for IPv4 */
550 TD1_GTSENV6
= (1 << 25), /* Giant Send for IPv6 */
551 #define GTTCPHO_SHIFT 18
552 #define GTTCPHO_MAX 0x7fU
554 /* Second doubleword. */
555 #define TCPHO_SHIFT 18
556 #define TCPHO_MAX 0x3ffU
557 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
558 TD1_IPv6_CS
= (1 << 28), /* Calculate IPv6 checksum */
559 TD1_IPv4_CS
= (1 << 29), /* Calculate IPv4 checksum */
560 TD1_TCP_CS
= (1 << 30), /* Calculate TCP/IP checksum */
561 TD1_UDP_CS
= (1 << 31), /* Calculate UDP/IP checksum */
564 enum rtl_rx_desc_bit
{
566 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
567 PID0
= (1 << 17), /* Protocol ID bit 0/2 */
569 #define RxProtoUDP (PID1)
570 #define RxProtoTCP (PID0)
571 #define RxProtoIP (PID1 | PID0)
572 #define RxProtoMask RxProtoIP
574 IPFail
= (1 << 16), /* IP checksum failed */
575 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
576 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
577 RxVlanTag
= (1 << 16), /* VLAN tag available */
580 #define RsvdMask 0x3fffc000
581 #define CPCMD_QUIRK_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
600 struct rtl8169_counters
{
607 __le32 tx_one_collision
;
608 __le32 tx_multi_collision
;
616 struct rtl8169_tc_offsets
{
619 __le32 tx_multi_collision
;
624 RTL_FLAG_TASK_ENABLED
= 0,
625 RTL_FLAG_TASK_RESET_PENDING
,
629 struct rtl8169_stats
{
632 struct u64_stats_sync syncp
;
635 struct rtl8169_private
{
636 void __iomem
*mmio_addr
; /* memory map physical address */
637 struct pci_dev
*pci_dev
;
638 struct net_device
*dev
;
639 struct phy_device
*phydev
;
640 struct napi_struct napi
;
643 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
644 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
646 struct rtl8169_stats rx_stats
;
647 struct rtl8169_stats tx_stats
;
648 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
649 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
650 dma_addr_t TxPhyAddr
;
651 dma_addr_t RxPhyAddr
;
652 void *Rx_databuff
[NUM_RX_DESC
]; /* Rx data buffers */
653 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
657 const struct rtl_coalesce_info
*coalesce_info
;
661 void (*write
)(struct rtl8169_private
*, int, int);
662 int (*read
)(struct rtl8169_private
*, int);
666 void (*enable
)(struct rtl8169_private
*);
667 void (*disable
)(struct rtl8169_private
*);
670 void (*hw_start
)(struct rtl8169_private
*tp
);
671 bool (*tso_csum
)(struct rtl8169_private
*, struct sk_buff
*, u32
*);
674 DECLARE_BITMAP(flags
, RTL_FLAG_MAX
);
676 struct work_struct work
;
679 unsigned irq_enabled
:1;
680 unsigned supports_gmii
:1;
681 dma_addr_t counters_phys_addr
;
682 struct rtl8169_counters
*counters
;
683 struct rtl8169_tc_offsets tc_offset
;
688 const struct firmware
*fw
;
690 #define RTL_VER_SIZE 32
692 char version
[RTL_VER_SIZE
];
694 struct rtl_fw_phy_action
{
703 typedef void (*rtl_generic_fct
)(struct rtl8169_private
*tp
);
705 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
706 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
707 module_param_named(debug
, debug
.msg_enable
, int, 0);
708 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
709 MODULE_SOFTDEP("pre: realtek");
710 MODULE_LICENSE("GPL");
711 MODULE_FIRMWARE(FIRMWARE_8168D_1
);
712 MODULE_FIRMWARE(FIRMWARE_8168D_2
);
713 MODULE_FIRMWARE(FIRMWARE_8168E_1
);
714 MODULE_FIRMWARE(FIRMWARE_8168E_2
);
715 MODULE_FIRMWARE(FIRMWARE_8168E_3
);
716 MODULE_FIRMWARE(FIRMWARE_8105E_1
);
717 MODULE_FIRMWARE(FIRMWARE_8168F_1
);
718 MODULE_FIRMWARE(FIRMWARE_8168F_2
);
719 MODULE_FIRMWARE(FIRMWARE_8402_1
);
720 MODULE_FIRMWARE(FIRMWARE_8411_1
);
721 MODULE_FIRMWARE(FIRMWARE_8411_2
);
722 MODULE_FIRMWARE(FIRMWARE_8106E_1
);
723 MODULE_FIRMWARE(FIRMWARE_8106E_2
);
724 MODULE_FIRMWARE(FIRMWARE_8168G_2
);
725 MODULE_FIRMWARE(FIRMWARE_8168G_3
);
726 MODULE_FIRMWARE(FIRMWARE_8168H_1
);
727 MODULE_FIRMWARE(FIRMWARE_8168H_2
);
728 MODULE_FIRMWARE(FIRMWARE_8107E_1
);
729 MODULE_FIRMWARE(FIRMWARE_8107E_2
);
731 static inline struct device
*tp_to_dev(struct rtl8169_private
*tp
)
733 return &tp
->pci_dev
->dev
;
736 static void rtl_lock_work(struct rtl8169_private
*tp
)
738 mutex_lock(&tp
->wk
.mutex
);
741 static void rtl_unlock_work(struct rtl8169_private
*tp
)
743 mutex_unlock(&tp
->wk
.mutex
);
746 static void rtl_lock_config_regs(struct rtl8169_private
*tp
)
748 RTL_W8(tp
, Cfg9346
, Cfg9346_Lock
);
751 static void rtl_unlock_config_regs(struct rtl8169_private
*tp
)
753 RTL_W8(tp
, Cfg9346
, Cfg9346_Unlock
);
756 static void rtl_tx_performance_tweak(struct rtl8169_private
*tp
, u16 force
)
758 pcie_capability_clear_and_set_word(tp
->pci_dev
, PCI_EXP_DEVCTL
,
759 PCI_EXP_DEVCTL_READRQ
, force
);
763 bool (*check
)(struct rtl8169_private
*);
767 static void rtl_udelay(unsigned int d
)
772 static bool rtl_loop_wait(struct rtl8169_private
*tp
, const struct rtl_cond
*c
,
773 void (*delay
)(unsigned int), unsigned int d
, int n
,
778 for (i
= 0; i
< n
; i
++) {
779 if (c
->check(tp
) == high
)
783 netif_err(tp
, drv
, tp
->dev
, "%s == %d (loop: %d, delay: %d).\n",
784 c
->msg
, !high
, n
, d
);
788 static bool rtl_udelay_loop_wait_high(struct rtl8169_private
*tp
,
789 const struct rtl_cond
*c
,
790 unsigned int d
, int n
)
792 return rtl_loop_wait(tp
, c
, rtl_udelay
, d
, n
, true);
795 static bool rtl_udelay_loop_wait_low(struct rtl8169_private
*tp
,
796 const struct rtl_cond
*c
,
797 unsigned int d
, int n
)
799 return rtl_loop_wait(tp
, c
, rtl_udelay
, d
, n
, false);
802 static bool rtl_msleep_loop_wait_high(struct rtl8169_private
*tp
,
803 const struct rtl_cond
*c
,
804 unsigned int d
, int n
)
806 return rtl_loop_wait(tp
, c
, msleep
, d
, n
, true);
809 static bool rtl_msleep_loop_wait_low(struct rtl8169_private
*tp
,
810 const struct rtl_cond
*c
,
811 unsigned int d
, int n
)
813 return rtl_loop_wait(tp
, c
, msleep
, d
, n
, false);
816 #define DECLARE_RTL_COND(name) \
817 static bool name ## _check(struct rtl8169_private *); \
819 static const struct rtl_cond name = { \
820 .check = name ## _check, \
824 static bool name ## _check(struct rtl8169_private *tp)
826 static bool rtl_ocp_reg_failure(struct rtl8169_private
*tp
, u32 reg
)
828 if (reg
& 0xffff0001) {
829 netif_err(tp
, drv
, tp
->dev
, "Invalid ocp reg %x!\n", reg
);
835 DECLARE_RTL_COND(rtl_ocp_gphy_cond
)
837 return RTL_R32(tp
, GPHY_OCP
) & OCPAR_FLAG
;
840 static void r8168_phy_ocp_write(struct rtl8169_private
*tp
, u32 reg
, u32 data
)
842 if (rtl_ocp_reg_failure(tp
, reg
))
845 RTL_W32(tp
, GPHY_OCP
, OCPAR_FLAG
| (reg
<< 15) | data
);
847 rtl_udelay_loop_wait_low(tp
, &rtl_ocp_gphy_cond
, 25, 10);
850 static u16
r8168_phy_ocp_read(struct rtl8169_private
*tp
, u32 reg
)
852 if (rtl_ocp_reg_failure(tp
, reg
))
855 RTL_W32(tp
, GPHY_OCP
, reg
<< 15);
857 return rtl_udelay_loop_wait_high(tp
, &rtl_ocp_gphy_cond
, 25, 10) ?
858 (RTL_R32(tp
, GPHY_OCP
) & 0xffff) : ~0;
861 static void r8168_mac_ocp_write(struct rtl8169_private
*tp
, u32 reg
, u32 data
)
863 if (rtl_ocp_reg_failure(tp
, reg
))
866 RTL_W32(tp
, OCPDR
, OCPAR_FLAG
| (reg
<< 15) | data
);
869 static u16
r8168_mac_ocp_read(struct rtl8169_private
*tp
, u32 reg
)
871 if (rtl_ocp_reg_failure(tp
, reg
))
874 RTL_W32(tp
, OCPDR
, reg
<< 15);
876 return RTL_R32(tp
, OCPDR
);
879 #define OCP_STD_PHY_BASE 0xa400
881 static void r8168g_mdio_write(struct rtl8169_private
*tp
, int reg
, int value
)
884 tp
->ocp_base
= value
? value
<< 4 : OCP_STD_PHY_BASE
;
888 if (tp
->ocp_base
!= OCP_STD_PHY_BASE
)
891 r8168_phy_ocp_write(tp
, tp
->ocp_base
+ reg
* 2, value
);
894 static int r8168g_mdio_read(struct rtl8169_private
*tp
, int reg
)
896 if (tp
->ocp_base
!= OCP_STD_PHY_BASE
)
899 return r8168_phy_ocp_read(tp
, tp
->ocp_base
+ reg
* 2);
902 static void mac_mcu_write(struct rtl8169_private
*tp
, int reg
, int value
)
905 tp
->ocp_base
= value
<< 4;
909 r8168_mac_ocp_write(tp
, tp
->ocp_base
+ reg
, value
);
912 static int mac_mcu_read(struct rtl8169_private
*tp
, int reg
)
914 return r8168_mac_ocp_read(tp
, tp
->ocp_base
+ reg
);
917 DECLARE_RTL_COND(rtl_phyar_cond
)
919 return RTL_R32(tp
, PHYAR
) & 0x80000000;
922 static void r8169_mdio_write(struct rtl8169_private
*tp
, int reg
, int value
)
924 RTL_W32(tp
, PHYAR
, 0x80000000 | (reg
& 0x1f) << 16 | (value
& 0xffff));
926 rtl_udelay_loop_wait_low(tp
, &rtl_phyar_cond
, 25, 20);
928 * According to hardware specs a 20us delay is required after write
929 * complete indication, but before sending next command.
934 static int r8169_mdio_read(struct rtl8169_private
*tp
, int reg
)
938 RTL_W32(tp
, PHYAR
, 0x0 | (reg
& 0x1f) << 16);
940 value
= rtl_udelay_loop_wait_high(tp
, &rtl_phyar_cond
, 25, 20) ?
941 RTL_R32(tp
, PHYAR
) & 0xffff : ~0;
944 * According to hardware specs a 20us delay is required after read
945 * complete indication, but before sending next command.
952 DECLARE_RTL_COND(rtl_ocpar_cond
)
954 return RTL_R32(tp
, OCPAR
) & OCPAR_FLAG
;
957 static void r8168dp_1_mdio_access(struct rtl8169_private
*tp
, int reg
, u32 data
)
959 RTL_W32(tp
, OCPDR
, data
| ((reg
& OCPDR_REG_MASK
) << OCPDR_GPHY_REG_SHIFT
));
960 RTL_W32(tp
, OCPAR
, OCPAR_GPHY_WRITE_CMD
);
961 RTL_W32(tp
, EPHY_RXER_NUM
, 0);
963 rtl_udelay_loop_wait_low(tp
, &rtl_ocpar_cond
, 1000, 100);
966 static void r8168dp_1_mdio_write(struct rtl8169_private
*tp
, int reg
, int value
)
968 r8168dp_1_mdio_access(tp
, reg
,
969 OCPDR_WRITE_CMD
| (value
& OCPDR_DATA_MASK
));
972 static int r8168dp_1_mdio_read(struct rtl8169_private
*tp
, int reg
)
974 r8168dp_1_mdio_access(tp
, reg
, OCPDR_READ_CMD
);
977 RTL_W32(tp
, OCPAR
, OCPAR_GPHY_READ_CMD
);
978 RTL_W32(tp
, EPHY_RXER_NUM
, 0);
980 return rtl_udelay_loop_wait_high(tp
, &rtl_ocpar_cond
, 1000, 100) ?
981 RTL_R32(tp
, OCPDR
) & OCPDR_DATA_MASK
: ~0;
984 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
986 static void r8168dp_2_mdio_start(struct rtl8169_private
*tp
)
988 RTL_W32(tp
, 0xd0, RTL_R32(tp
, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT
);
991 static void r8168dp_2_mdio_stop(struct rtl8169_private
*tp
)
993 RTL_W32(tp
, 0xd0, RTL_R32(tp
, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT
);
996 static void r8168dp_2_mdio_write(struct rtl8169_private
*tp
, int reg
, int value
)
998 r8168dp_2_mdio_start(tp
);
1000 r8169_mdio_write(tp
, reg
, value
);
1002 r8168dp_2_mdio_stop(tp
);
1005 static int r8168dp_2_mdio_read(struct rtl8169_private
*tp
, int reg
)
1009 r8168dp_2_mdio_start(tp
);
1011 value
= r8169_mdio_read(tp
, reg
);
1013 r8168dp_2_mdio_stop(tp
);
1018 static void rtl_writephy(struct rtl8169_private
*tp
, int location
, u32 val
)
1020 tp
->mdio_ops
.write(tp
, location
, val
);
1023 static int rtl_readphy(struct rtl8169_private
*tp
, int location
)
1025 return tp
->mdio_ops
.read(tp
, location
);
1028 static void rtl_patchphy(struct rtl8169_private
*tp
, int reg_addr
, int value
)
1030 rtl_writephy(tp
, reg_addr
, rtl_readphy(tp
, reg_addr
) | value
);
1033 static void rtl_w0w1_phy(struct rtl8169_private
*tp
, int reg_addr
, int p
, int m
)
1037 val
= rtl_readphy(tp
, reg_addr
);
1038 rtl_writephy(tp
, reg_addr
, (val
& ~m
) | p
);
1041 DECLARE_RTL_COND(rtl_ephyar_cond
)
1043 return RTL_R32(tp
, EPHYAR
) & EPHYAR_FLAG
;
1046 static void rtl_ephy_write(struct rtl8169_private
*tp
, int reg_addr
, int value
)
1048 RTL_W32(tp
, EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
1049 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
1051 rtl_udelay_loop_wait_low(tp
, &rtl_ephyar_cond
, 10, 100);
1056 static u16
rtl_ephy_read(struct rtl8169_private
*tp
, int reg_addr
)
1058 RTL_W32(tp
, EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
1060 return rtl_udelay_loop_wait_high(tp
, &rtl_ephyar_cond
, 10, 100) ?
1061 RTL_R32(tp
, EPHYAR
) & EPHYAR_DATA_MASK
: ~0;
1064 DECLARE_RTL_COND(rtl_eriar_cond
)
1066 return RTL_R32(tp
, ERIAR
) & ERIAR_FLAG
;
1069 static void _rtl_eri_write(struct rtl8169_private
*tp
, int addr
, u32 mask
,
1072 BUG_ON((addr
& 3) || (mask
== 0));
1073 RTL_W32(tp
, ERIDR
, val
);
1074 RTL_W32(tp
, ERIAR
, ERIAR_WRITE_CMD
| type
| mask
| addr
);
1076 rtl_udelay_loop_wait_low(tp
, &rtl_eriar_cond
, 100, 100);
1079 static void rtl_eri_write(struct rtl8169_private
*tp
, int addr
, u32 mask
,
1082 _rtl_eri_write(tp
, addr
, mask
, val
, ERIAR_EXGMAC
);
1085 static u32
_rtl_eri_read(struct rtl8169_private
*tp
, int addr
, int type
)
1087 RTL_W32(tp
, ERIAR
, ERIAR_READ_CMD
| type
| ERIAR_MASK_1111
| addr
);
1089 return rtl_udelay_loop_wait_high(tp
, &rtl_eriar_cond
, 100, 100) ?
1090 RTL_R32(tp
, ERIDR
) : ~0;
1093 static u32
rtl_eri_read(struct rtl8169_private
*tp
, int addr
)
1095 return _rtl_eri_read(tp
, addr
, ERIAR_EXGMAC
);
1098 static void rtl_w0w1_eri(struct rtl8169_private
*tp
, int addr
, u32 mask
, u32 p
,
1103 val
= rtl_eri_read(tp
, addr
);
1104 rtl_eri_write(tp
, addr
, mask
, (val
& ~m
) | p
);
1107 static void rtl_eri_set_bits(struct rtl8169_private
*tp
, int addr
, u32 mask
,
1110 rtl_w0w1_eri(tp
, addr
, mask
, p
, 0);
1113 static void rtl_eri_clear_bits(struct rtl8169_private
*tp
, int addr
, u32 mask
,
1116 rtl_w0w1_eri(tp
, addr
, mask
, 0, m
);
1119 static u32
r8168dp_ocp_read(struct rtl8169_private
*tp
, u8 mask
, u16 reg
)
1121 RTL_W32(tp
, OCPAR
, ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
1122 return rtl_udelay_loop_wait_high(tp
, &rtl_ocpar_cond
, 100, 20) ?
1123 RTL_R32(tp
, OCPDR
) : ~0;
1126 static u32
r8168ep_ocp_read(struct rtl8169_private
*tp
, u8 mask
, u16 reg
)
1128 return _rtl_eri_read(tp
, reg
, ERIAR_OOB
);
1131 static void r8168dp_ocp_write(struct rtl8169_private
*tp
, u8 mask
, u16 reg
,
1134 RTL_W32(tp
, OCPDR
, data
);
1135 RTL_W32(tp
, OCPAR
, OCPAR_FLAG
| ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
1136 rtl_udelay_loop_wait_low(tp
, &rtl_ocpar_cond
, 100, 20);
1139 static void r8168ep_ocp_write(struct rtl8169_private
*tp
, u8 mask
, u16 reg
,
1142 _rtl_eri_write(tp
, reg
, ((u32
)mask
& 0x0f) << ERIAR_MASK_SHIFT
,
1146 static void r8168dp_oob_notify(struct rtl8169_private
*tp
, u8 cmd
)
1148 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_0001
, cmd
);
1150 r8168dp_ocp_write(tp
, 0x1, 0x30, 0x00000001);
1153 #define OOB_CMD_RESET 0x00
1154 #define OOB_CMD_DRIVER_START 0x05
1155 #define OOB_CMD_DRIVER_STOP 0x06
1157 static u16
rtl8168_get_ocp_reg(struct rtl8169_private
*tp
)
1159 return (tp
->mac_version
== RTL_GIGA_MAC_VER_31
) ? 0xb8 : 0x10;
1162 DECLARE_RTL_COND(rtl_dp_ocp_read_cond
)
1166 reg
= rtl8168_get_ocp_reg(tp
);
1168 return r8168dp_ocp_read(tp
, 0x0f, reg
) & 0x00000800;
1171 DECLARE_RTL_COND(rtl_ep_ocp_read_cond
)
1173 return r8168ep_ocp_read(tp
, 0x0f, 0x124) & 0x00000001;
1176 DECLARE_RTL_COND(rtl_ocp_tx_cond
)
1178 return RTL_R8(tp
, IBISR0
) & 0x20;
1181 static void rtl8168ep_stop_cmac(struct rtl8169_private
*tp
)
1183 RTL_W8(tp
, IBCR2
, RTL_R8(tp
, IBCR2
) & ~0x01);
1184 rtl_msleep_loop_wait_high(tp
, &rtl_ocp_tx_cond
, 50, 2000);
1185 RTL_W8(tp
, IBISR0
, RTL_R8(tp
, IBISR0
) | 0x20);
1186 RTL_W8(tp
, IBCR0
, RTL_R8(tp
, IBCR0
) & ~0x01);
1189 static void rtl8168dp_driver_start(struct rtl8169_private
*tp
)
1191 r8168dp_oob_notify(tp
, OOB_CMD_DRIVER_START
);
1192 rtl_msleep_loop_wait_high(tp
, &rtl_dp_ocp_read_cond
, 10, 10);
1195 static void rtl8168ep_driver_start(struct rtl8169_private
*tp
)
1197 r8168ep_ocp_write(tp
, 0x01, 0x180, OOB_CMD_DRIVER_START
);
1198 r8168ep_ocp_write(tp
, 0x01, 0x30,
1199 r8168ep_ocp_read(tp
, 0x01, 0x30) | 0x01);
1200 rtl_msleep_loop_wait_high(tp
, &rtl_ep_ocp_read_cond
, 10, 10);
1203 static void rtl8168_driver_start(struct rtl8169_private
*tp
)
1205 switch (tp
->mac_version
) {
1206 case RTL_GIGA_MAC_VER_27
:
1207 case RTL_GIGA_MAC_VER_28
:
1208 case RTL_GIGA_MAC_VER_31
:
1209 rtl8168dp_driver_start(tp
);
1211 case RTL_GIGA_MAC_VER_49
:
1212 case RTL_GIGA_MAC_VER_50
:
1213 case RTL_GIGA_MAC_VER_51
:
1214 rtl8168ep_driver_start(tp
);
1222 static void rtl8168dp_driver_stop(struct rtl8169_private
*tp
)
1224 r8168dp_oob_notify(tp
, OOB_CMD_DRIVER_STOP
);
1225 rtl_msleep_loop_wait_low(tp
, &rtl_dp_ocp_read_cond
, 10, 10);
1228 static void rtl8168ep_driver_stop(struct rtl8169_private
*tp
)
1230 rtl8168ep_stop_cmac(tp
);
1231 r8168ep_ocp_write(tp
, 0x01, 0x180, OOB_CMD_DRIVER_STOP
);
1232 r8168ep_ocp_write(tp
, 0x01, 0x30,
1233 r8168ep_ocp_read(tp
, 0x01, 0x30) | 0x01);
1234 rtl_msleep_loop_wait_low(tp
, &rtl_ep_ocp_read_cond
, 10, 10);
1237 static void rtl8168_driver_stop(struct rtl8169_private
*tp
)
1239 switch (tp
->mac_version
) {
1240 case RTL_GIGA_MAC_VER_27
:
1241 case RTL_GIGA_MAC_VER_28
:
1242 case RTL_GIGA_MAC_VER_31
:
1243 rtl8168dp_driver_stop(tp
);
1245 case RTL_GIGA_MAC_VER_49
:
1246 case RTL_GIGA_MAC_VER_50
:
1247 case RTL_GIGA_MAC_VER_51
:
1248 rtl8168ep_driver_stop(tp
);
1256 static bool r8168dp_check_dash(struct rtl8169_private
*tp
)
1258 u16 reg
= rtl8168_get_ocp_reg(tp
);
1260 return !!(r8168dp_ocp_read(tp
, 0x0f, reg
) & 0x00008000);
1263 static bool r8168ep_check_dash(struct rtl8169_private
*tp
)
1265 return !!(r8168ep_ocp_read(tp
, 0x0f, 0x128) & 0x00000001);
1268 static bool r8168_check_dash(struct rtl8169_private
*tp
)
1270 switch (tp
->mac_version
) {
1271 case RTL_GIGA_MAC_VER_27
:
1272 case RTL_GIGA_MAC_VER_28
:
1273 case RTL_GIGA_MAC_VER_31
:
1274 return r8168dp_check_dash(tp
);
1275 case RTL_GIGA_MAC_VER_49
:
1276 case RTL_GIGA_MAC_VER_50
:
1277 case RTL_GIGA_MAC_VER_51
:
1278 return r8168ep_check_dash(tp
);
1284 static void rtl_reset_packet_filter(struct rtl8169_private
*tp
)
1286 rtl_eri_clear_bits(tp
, 0xdc, ERIAR_MASK_0001
, BIT(0));
1287 rtl_eri_set_bits(tp
, 0xdc, ERIAR_MASK_0001
, BIT(0));
1290 DECLARE_RTL_COND(rtl_efusear_cond
)
1292 return RTL_R32(tp
, EFUSEAR
) & EFUSEAR_FLAG
;
1295 static u8
rtl8168d_efuse_read(struct rtl8169_private
*tp
, int reg_addr
)
1297 RTL_W32(tp
, EFUSEAR
, (reg_addr
& EFUSEAR_REG_MASK
) << EFUSEAR_REG_SHIFT
);
1299 return rtl_udelay_loop_wait_high(tp
, &rtl_efusear_cond
, 100, 300) ?
1300 RTL_R32(tp
, EFUSEAR
) & EFUSEAR_DATA_MASK
: ~0;
1303 static void rtl_ack_events(struct rtl8169_private
*tp
, u16 bits
)
1305 RTL_W16(tp
, IntrStatus
, bits
);
1308 static void rtl_irq_disable(struct rtl8169_private
*tp
)
1310 RTL_W16(tp
, IntrMask
, 0);
1311 tp
->irq_enabled
= 0;
1314 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1315 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1316 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1318 static void rtl_irq_enable(struct rtl8169_private
*tp
)
1320 tp
->irq_enabled
= 1;
1321 RTL_W16(tp
, IntrMask
, tp
->irq_mask
);
1324 static void rtl8169_irq_mask_and_ack(struct rtl8169_private
*tp
)
1326 rtl_irq_disable(tp
);
1327 rtl_ack_events(tp
, 0xffff);
1329 RTL_R8(tp
, ChipCmd
);
1332 static void rtl_link_chg_patch(struct rtl8169_private
*tp
)
1334 struct net_device
*dev
= tp
->dev
;
1335 struct phy_device
*phydev
= tp
->phydev
;
1337 if (!netif_running(dev
))
1340 if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
||
1341 tp
->mac_version
== RTL_GIGA_MAC_VER_38
) {
1342 if (phydev
->speed
== SPEED_1000
) {
1343 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x00000011);
1344 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x00000005);
1345 } else if (phydev
->speed
== SPEED_100
) {
1346 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x0000001f);
1347 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x00000005);
1349 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x0000001f);
1350 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x0000003f);
1352 rtl_reset_packet_filter(tp
);
1353 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_35
||
1354 tp
->mac_version
== RTL_GIGA_MAC_VER_36
) {
1355 if (phydev
->speed
== SPEED_1000
) {
1356 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x00000011);
1357 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x00000005);
1359 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x0000001f);
1360 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x0000003f);
1362 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_37
) {
1363 if (phydev
->speed
== SPEED_10
) {
1364 rtl_eri_write(tp
, 0x1d0, ERIAR_MASK_0011
, 0x4d02);
1365 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_0011
, 0x0060a);
1367 rtl_eri_write(tp
, 0x1d0, ERIAR_MASK_0011
, 0x0000);
1372 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1374 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1376 struct rtl8169_private
*tp
= netdev_priv(dev
);
1379 wol
->supported
= WAKE_ANY
;
1380 wol
->wolopts
= tp
->saved_wolopts
;
1381 rtl_unlock_work(tp
);
1384 static void __rtl8169_set_wol(struct rtl8169_private
*tp
, u32 wolopts
)
1386 unsigned int i
, tmp
;
1387 static const struct {
1392 { WAKE_PHY
, Config3
, LinkUp
},
1393 { WAKE_UCAST
, Config5
, UWF
},
1394 { WAKE_BCAST
, Config5
, BWF
},
1395 { WAKE_MCAST
, Config5
, MWF
},
1396 { WAKE_ANY
, Config5
, LanWake
},
1397 { WAKE_MAGIC
, Config3
, MagicPacket
}
1401 rtl_unlock_config_regs(tp
);
1403 switch (tp
->mac_version
) {
1404 case RTL_GIGA_MAC_VER_34
... RTL_GIGA_MAC_VER_38
:
1405 case RTL_GIGA_MAC_VER_40
... RTL_GIGA_MAC_VER_51
:
1406 tmp
= ARRAY_SIZE(cfg
) - 1;
1407 if (wolopts
& WAKE_MAGIC
)
1408 rtl_eri_set_bits(tp
, 0x0dc, ERIAR_MASK_0100
,
1411 rtl_eri_clear_bits(tp
, 0x0dc, ERIAR_MASK_0100
,
1415 tmp
= ARRAY_SIZE(cfg
);
1419 for (i
= 0; i
< tmp
; i
++) {
1420 options
= RTL_R8(tp
, cfg
[i
].reg
) & ~cfg
[i
].mask
;
1421 if (wolopts
& cfg
[i
].opt
)
1422 options
|= cfg
[i
].mask
;
1423 RTL_W8(tp
, cfg
[i
].reg
, options
);
1426 switch (tp
->mac_version
) {
1427 case RTL_GIGA_MAC_VER_01
... RTL_GIGA_MAC_VER_17
:
1428 options
= RTL_R8(tp
, Config1
) & ~PMEnable
;
1430 options
|= PMEnable
;
1431 RTL_W8(tp
, Config1
, options
);
1434 options
= RTL_R8(tp
, Config2
) & ~PME_SIGNAL
;
1436 options
|= PME_SIGNAL
;
1437 RTL_W8(tp
, Config2
, options
);
1441 rtl_lock_config_regs(tp
);
1443 device_set_wakeup_enable(tp_to_dev(tp
), wolopts
);
1446 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1448 struct rtl8169_private
*tp
= netdev_priv(dev
);
1449 struct device
*d
= tp_to_dev(tp
);
1451 if (wol
->wolopts
& ~WAKE_ANY
)
1454 pm_runtime_get_noresume(d
);
1458 tp
->saved_wolopts
= wol
->wolopts
;
1460 if (pm_runtime_active(d
))
1461 __rtl8169_set_wol(tp
, tp
->saved_wolopts
);
1463 rtl_unlock_work(tp
);
1465 pm_runtime_put_noidle(d
);
1470 static void rtl8169_get_drvinfo(struct net_device
*dev
,
1471 struct ethtool_drvinfo
*info
)
1473 struct rtl8169_private
*tp
= netdev_priv(dev
);
1474 struct rtl_fw
*rtl_fw
= tp
->rtl_fw
;
1476 strlcpy(info
->driver
, MODULENAME
, sizeof(info
->driver
));
1477 strlcpy(info
->bus_info
, pci_name(tp
->pci_dev
), sizeof(info
->bus_info
));
1478 BUILD_BUG_ON(sizeof(info
->fw_version
) < sizeof(rtl_fw
->version
));
1480 strlcpy(info
->fw_version
, rtl_fw
->version
,
1481 sizeof(info
->fw_version
));
1484 static int rtl8169_get_regs_len(struct net_device
*dev
)
1486 return R8169_REGS_SIZE
;
1489 static netdev_features_t
rtl8169_fix_features(struct net_device
*dev
,
1490 netdev_features_t features
)
1492 struct rtl8169_private
*tp
= netdev_priv(dev
);
1494 if (dev
->mtu
> TD_MSS_MAX
)
1495 features
&= ~NETIF_F_ALL_TSO
;
1497 if (dev
->mtu
> JUMBO_1K
&&
1498 tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
1499 features
&= ~NETIF_F_IP_CSUM
;
1504 static int rtl8169_set_features(struct net_device
*dev
,
1505 netdev_features_t features
)
1507 struct rtl8169_private
*tp
= netdev_priv(dev
);
1512 rx_config
= RTL_R32(tp
, RxConfig
);
1513 if (features
& NETIF_F_RXALL
)
1514 rx_config
|= (AcceptErr
| AcceptRunt
);
1516 rx_config
&= ~(AcceptErr
| AcceptRunt
);
1518 RTL_W32(tp
, RxConfig
, rx_config
);
1520 if (features
& NETIF_F_RXCSUM
)
1521 tp
->cp_cmd
|= RxChkSum
;
1523 tp
->cp_cmd
&= ~RxChkSum
;
1525 if (features
& NETIF_F_HW_VLAN_CTAG_RX
)
1526 tp
->cp_cmd
|= RxVlan
;
1528 tp
->cp_cmd
&= ~RxVlan
;
1530 RTL_W16(tp
, CPlusCmd
, tp
->cp_cmd
);
1531 RTL_R16(tp
, CPlusCmd
);
1533 rtl_unlock_work(tp
);
1538 static inline u32
rtl8169_tx_vlan_tag(struct sk_buff
*skb
)
1540 return (skb_vlan_tag_present(skb
)) ?
1541 TxVlanTag
| swab16(skb_vlan_tag_get(skb
)) : 0x00;
1544 static void rtl8169_rx_vlan_tag(struct RxDesc
*desc
, struct sk_buff
*skb
)
1546 u32 opts2
= le32_to_cpu(desc
->opts2
);
1548 if (opts2
& RxVlanTag
)
1549 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
), swab16(opts2
& 0xffff));
1552 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1555 struct rtl8169_private
*tp
= netdev_priv(dev
);
1556 u32 __iomem
*data
= tp
->mmio_addr
;
1561 for (i
= 0; i
< R8169_REGS_SIZE
; i
+= 4)
1562 memcpy_fromio(dw
++, data
++, 4);
1563 rtl_unlock_work(tp
);
1566 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
1568 struct rtl8169_private
*tp
= netdev_priv(dev
);
1570 return tp
->msg_enable
;
1573 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
1575 struct rtl8169_private
*tp
= netdev_priv(dev
);
1577 tp
->msg_enable
= value
;
1580 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
1587 "tx_single_collisions",
1588 "tx_multi_collisions",
1596 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
1600 return ARRAY_SIZE(rtl8169_gstrings
);
1606 DECLARE_RTL_COND(rtl_counters_cond
)
1608 return RTL_R32(tp
, CounterAddrLow
) & (CounterReset
| CounterDump
);
1611 static bool rtl8169_do_counters(struct rtl8169_private
*tp
, u32 counter_cmd
)
1613 dma_addr_t paddr
= tp
->counters_phys_addr
;
1616 RTL_W32(tp
, CounterAddrHigh
, (u64
)paddr
>> 32);
1617 RTL_R32(tp
, CounterAddrHigh
);
1618 cmd
= (u64
)paddr
& DMA_BIT_MASK(32);
1619 RTL_W32(tp
, CounterAddrLow
, cmd
);
1620 RTL_W32(tp
, CounterAddrLow
, cmd
| counter_cmd
);
1622 return rtl_udelay_loop_wait_low(tp
, &rtl_counters_cond
, 10, 1000);
1625 static bool rtl8169_reset_counters(struct rtl8169_private
*tp
)
1628 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1631 if (tp
->mac_version
< RTL_GIGA_MAC_VER_19
)
1634 return rtl8169_do_counters(tp
, CounterReset
);
1637 static bool rtl8169_update_counters(struct rtl8169_private
*tp
)
1639 u8 val
= RTL_R8(tp
, ChipCmd
);
1642 * Some chips are unable to dump tally counters when the receiver
1643 * is disabled. If 0xff chip may be in a PCI power-save state.
1645 if (!(val
& CmdRxEnb
) || val
== 0xff)
1648 return rtl8169_do_counters(tp
, CounterDump
);
1651 static bool rtl8169_init_counter_offsets(struct rtl8169_private
*tp
)
1653 struct rtl8169_counters
*counters
= tp
->counters
;
1657 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1658 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1659 * reset by a power cycle, while the counter values collected by the
1660 * driver are reset at every driver unload/load cycle.
1662 * To make sure the HW values returned by @get_stats64 match the SW
1663 * values, we collect the initial values at first open(*) and use them
1664 * as offsets to normalize the values returned by @get_stats64.
1666 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1667 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1668 * set at open time by rtl_hw_start.
1671 if (tp
->tc_offset
.inited
)
1674 /* If both, reset and update fail, propagate to caller. */
1675 if (rtl8169_reset_counters(tp
))
1678 if (rtl8169_update_counters(tp
))
1681 tp
->tc_offset
.tx_errors
= counters
->tx_errors
;
1682 tp
->tc_offset
.tx_multi_collision
= counters
->tx_multi_collision
;
1683 tp
->tc_offset
.tx_aborted
= counters
->tx_aborted
;
1684 tp
->tc_offset
.inited
= true;
1689 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
1690 struct ethtool_stats
*stats
, u64
*data
)
1692 struct rtl8169_private
*tp
= netdev_priv(dev
);
1693 struct device
*d
= tp_to_dev(tp
);
1694 struct rtl8169_counters
*counters
= tp
->counters
;
1698 pm_runtime_get_noresume(d
);
1700 if (pm_runtime_active(d
))
1701 rtl8169_update_counters(tp
);
1703 pm_runtime_put_noidle(d
);
1705 data
[0] = le64_to_cpu(counters
->tx_packets
);
1706 data
[1] = le64_to_cpu(counters
->rx_packets
);
1707 data
[2] = le64_to_cpu(counters
->tx_errors
);
1708 data
[3] = le32_to_cpu(counters
->rx_errors
);
1709 data
[4] = le16_to_cpu(counters
->rx_missed
);
1710 data
[5] = le16_to_cpu(counters
->align_errors
);
1711 data
[6] = le32_to_cpu(counters
->tx_one_collision
);
1712 data
[7] = le32_to_cpu(counters
->tx_multi_collision
);
1713 data
[8] = le64_to_cpu(counters
->rx_unicast
);
1714 data
[9] = le64_to_cpu(counters
->rx_broadcast
);
1715 data
[10] = le32_to_cpu(counters
->rx_multicast
);
1716 data
[11] = le16_to_cpu(counters
->tx_aborted
);
1717 data
[12] = le16_to_cpu(counters
->tx_underun
);
1720 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1724 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
1730 * Interrupt coalescing
1732 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1733 * > 8169, 8168 and 810x line of chipsets
1735 * 8169, 8168, and 8136(810x) serial chipsets support it.
1737 * > 2 - the Tx timer unit at gigabit speed
1739 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1740 * (0xe0) bit 1 and bit 0.
1743 * bit[1:0] \ speed 1000M 100M 10M
1744 * 0 0 320ns 2.56us 40.96us
1745 * 0 1 2.56us 20.48us 327.7us
1746 * 1 0 5.12us 40.96us 655.4us
1747 * 1 1 10.24us 81.92us 1.31ms
1750 * bit[1:0] \ speed 1000M 100M 10M
1751 * 0 0 5us 2.56us 40.96us
1752 * 0 1 40us 20.48us 327.7us
1753 * 1 0 80us 40.96us 655.4us
1754 * 1 1 160us 81.92us 1.31ms
1757 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1758 struct rtl_coalesce_scale
{
1763 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1764 struct rtl_coalesce_info
{
1766 struct rtl_coalesce_scale scalev
[4]; /* each CPlusCmd[0:1] case */
1769 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1770 #define rxtx_x1822(r, t) { \
1773 {{(r)*8*2, (t)*8*2}}, \
1774 {{(r)*8*2*2, (t)*8*2*2}}, \
1776 static const struct rtl_coalesce_info rtl_coalesce_info_8169
[] = {
1777 /* speed delays: rx00 tx00 */
1778 { SPEED_10
, rxtx_x1822(40960, 40960) },
1779 { SPEED_100
, rxtx_x1822( 2560, 2560) },
1780 { SPEED_1000
, rxtx_x1822( 320, 320) },
1784 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136
[] = {
1785 /* speed delays: rx00 tx00 */
1786 { SPEED_10
, rxtx_x1822(40960, 40960) },
1787 { SPEED_100
, rxtx_x1822( 2560, 2560) },
1788 { SPEED_1000
, rxtx_x1822( 5000, 5000) },
1793 /* get rx/tx scale vector corresponding to current speed */
1794 static const struct rtl_coalesce_info
*rtl_coalesce_info(struct net_device
*dev
)
1796 struct rtl8169_private
*tp
= netdev_priv(dev
);
1797 struct ethtool_link_ksettings ecmd
;
1798 const struct rtl_coalesce_info
*ci
;
1801 rc
= phy_ethtool_get_link_ksettings(dev
, &ecmd
);
1805 for (ci
= tp
->coalesce_info
; ci
->speed
!= 0; ci
++) {
1806 if (ecmd
.base
.speed
== ci
->speed
) {
1811 return ERR_PTR(-ELNRNG
);
1814 static int rtl_get_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
1816 struct rtl8169_private
*tp
= netdev_priv(dev
);
1817 const struct rtl_coalesce_info
*ci
;
1818 const struct rtl_coalesce_scale
*scale
;
1822 } coal_settings
[] = {
1823 { &ec
->rx_max_coalesced_frames
, &ec
->rx_coalesce_usecs
},
1824 { &ec
->tx_max_coalesced_frames
, &ec
->tx_coalesce_usecs
}
1825 }, *p
= coal_settings
;
1829 memset(ec
, 0, sizeof(*ec
));
1831 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1832 ci
= rtl_coalesce_info(dev
);
1836 scale
= &ci
->scalev
[tp
->cp_cmd
& INTT_MASK
];
1838 /* read IntrMitigate and adjust according to scale */
1839 for (w
= RTL_R16(tp
, IntrMitigate
); w
; w
>>= RTL_COALESCE_SHIFT
, p
++) {
1840 *p
->max_frames
= (w
& RTL_COALESCE_MASK
) << 2;
1841 w
>>= RTL_COALESCE_SHIFT
;
1842 *p
->usecs
= w
& RTL_COALESCE_MASK
;
1845 for (i
= 0; i
< 2; i
++) {
1846 p
= coal_settings
+ i
;
1847 *p
->usecs
= (*p
->usecs
* scale
->nsecs
[i
]) / 1000;
1850 * ethtool_coalesce says it is illegal to set both usecs and
1853 if (!*p
->usecs
&& !*p
->max_frames
)
1860 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1861 static const struct rtl_coalesce_scale
*rtl_coalesce_choose_scale(
1862 struct net_device
*dev
, u32 nsec
, u16
*cp01
)
1864 const struct rtl_coalesce_info
*ci
;
1867 ci
= rtl_coalesce_info(dev
);
1869 return ERR_CAST(ci
);
1871 for (i
= 0; i
< 4; i
++) {
1872 u32 rxtx_maxscale
= max(ci
->scalev
[i
].nsecs
[0],
1873 ci
->scalev
[i
].nsecs
[1]);
1874 if (nsec
<= rxtx_maxscale
* RTL_COALESCE_T_MAX
) {
1876 return &ci
->scalev
[i
];
1880 return ERR_PTR(-EINVAL
);
1883 static int rtl_set_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
1885 struct rtl8169_private
*tp
= netdev_priv(dev
);
1886 const struct rtl_coalesce_scale
*scale
;
1890 } coal_settings
[] = {
1891 { ec
->rx_max_coalesced_frames
, ec
->rx_coalesce_usecs
},
1892 { ec
->tx_max_coalesced_frames
, ec
->tx_coalesce_usecs
}
1893 }, *p
= coal_settings
;
1897 scale
= rtl_coalesce_choose_scale(dev
,
1898 max(p
[0].usecs
, p
[1].usecs
) * 1000, &cp01
);
1900 return PTR_ERR(scale
);
1902 for (i
= 0; i
< 2; i
++, p
++) {
1906 * accept max_frames=1 we returned in rtl_get_coalesce.
1907 * accept it not only when usecs=0 because of e.g. the following scenario:
1909 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1910 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1911 * - then user does `ethtool -C eth0 rx-usecs 100`
1913 * since ethtool sends to kernel whole ethtool_coalesce
1914 * settings, if we do not handle rx_usecs=!0, rx_frames=1
1915 * we'll reject it below in `frames % 4 != 0`.
1917 if (p
->frames
== 1) {
1921 units
= p
->usecs
* 1000 / scale
->nsecs
[i
];
1922 if (p
->frames
> RTL_COALESCE_FRAME_MAX
|| p
->frames
% 4)
1925 w
<<= RTL_COALESCE_SHIFT
;
1927 w
<<= RTL_COALESCE_SHIFT
;
1928 w
|= p
->frames
>> 2;
1933 RTL_W16(tp
, IntrMitigate
, swab16(w
));
1935 tp
->cp_cmd
= (tp
->cp_cmd
& ~INTT_MASK
) | cp01
;
1936 RTL_W16(tp
, CPlusCmd
, tp
->cp_cmd
);
1937 RTL_R16(tp
, CPlusCmd
);
1939 rtl_unlock_work(tp
);
1944 static int rtl_get_eee_supp(struct rtl8169_private
*tp
)
1946 struct phy_device
*phydev
= tp
->phydev
;
1949 switch (tp
->mac_version
) {
1950 case RTL_GIGA_MAC_VER_34
:
1951 case RTL_GIGA_MAC_VER_35
:
1952 case RTL_GIGA_MAC_VER_36
:
1953 case RTL_GIGA_MAC_VER_38
:
1954 ret
= phy_read_mmd(phydev
, MDIO_MMD_PCS
, MDIO_PCS_EEE_ABLE
);
1956 case RTL_GIGA_MAC_VER_40
... RTL_GIGA_MAC_VER_51
:
1957 phy_write(phydev
, 0x1f, 0x0a5c);
1958 ret
= phy_read(phydev
, 0x12);
1959 phy_write(phydev
, 0x1f, 0x0000);
1962 ret
= -EPROTONOSUPPORT
;
1969 static int rtl_get_eee_lpadv(struct rtl8169_private
*tp
)
1971 struct phy_device
*phydev
= tp
->phydev
;
1974 switch (tp
->mac_version
) {
1975 case RTL_GIGA_MAC_VER_34
:
1976 case RTL_GIGA_MAC_VER_35
:
1977 case RTL_GIGA_MAC_VER_36
:
1978 case RTL_GIGA_MAC_VER_38
:
1979 ret
= phy_read_mmd(phydev
, MDIO_MMD_AN
, MDIO_AN_EEE_LPABLE
);
1981 case RTL_GIGA_MAC_VER_40
... RTL_GIGA_MAC_VER_51
:
1982 phy_write(phydev
, 0x1f, 0x0a5d);
1983 ret
= phy_read(phydev
, 0x11);
1984 phy_write(phydev
, 0x1f, 0x0000);
1987 ret
= -EPROTONOSUPPORT
;
1994 static int rtl_get_eee_adv(struct rtl8169_private
*tp
)
1996 struct phy_device
*phydev
= tp
->phydev
;
1999 switch (tp
->mac_version
) {
2000 case RTL_GIGA_MAC_VER_34
:
2001 case RTL_GIGA_MAC_VER_35
:
2002 case RTL_GIGA_MAC_VER_36
:
2003 case RTL_GIGA_MAC_VER_38
:
2004 ret
= phy_read_mmd(phydev
, MDIO_MMD_AN
, MDIO_AN_EEE_ADV
);
2006 case RTL_GIGA_MAC_VER_40
... RTL_GIGA_MAC_VER_51
:
2007 phy_write(phydev
, 0x1f, 0x0a5d);
2008 ret
= phy_read(phydev
, 0x10);
2009 phy_write(phydev
, 0x1f, 0x0000);
2012 ret
= -EPROTONOSUPPORT
;
2019 static int rtl_set_eee_adv(struct rtl8169_private
*tp
, int val
)
2021 struct phy_device
*phydev
= tp
->phydev
;
2024 switch (tp
->mac_version
) {
2025 case RTL_GIGA_MAC_VER_34
:
2026 case RTL_GIGA_MAC_VER_35
:
2027 case RTL_GIGA_MAC_VER_36
:
2028 case RTL_GIGA_MAC_VER_38
:
2029 ret
= phy_write_mmd(phydev
, MDIO_MMD_AN
, MDIO_AN_EEE_ADV
, val
);
2031 case RTL_GIGA_MAC_VER_40
... RTL_GIGA_MAC_VER_51
:
2032 phy_write(phydev
, 0x1f, 0x0a5d);
2033 phy_write(phydev
, 0x10, val
);
2034 phy_write(phydev
, 0x1f, 0x0000);
2037 ret
= -EPROTONOSUPPORT
;
2044 static int rtl8169_get_eee(struct net_device
*dev
, struct ethtool_eee
*data
)
2046 struct rtl8169_private
*tp
= netdev_priv(dev
);
2047 struct device
*d
= tp_to_dev(tp
);
2050 pm_runtime_get_noresume(d
);
2052 if (!pm_runtime_active(d
)) {
2057 /* Get Supported EEE */
2058 ret
= rtl_get_eee_supp(tp
);
2061 data
->supported
= mmd_eee_cap_to_ethtool_sup_t(ret
);
2063 /* Get advertisement EEE */
2064 ret
= rtl_get_eee_adv(tp
);
2067 data
->advertised
= mmd_eee_adv_to_ethtool_adv_t(ret
);
2068 data
->eee_enabled
= !!data
->advertised
;
2070 /* Get LP advertisement EEE */
2071 ret
= rtl_get_eee_lpadv(tp
);
2074 data
->lp_advertised
= mmd_eee_adv_to_ethtool_adv_t(ret
);
2075 data
->eee_active
= !!(data
->advertised
& data
->lp_advertised
);
2077 pm_runtime_put_noidle(d
);
2078 return ret
< 0 ? ret
: 0;
2081 static int rtl8169_set_eee(struct net_device
*dev
, struct ethtool_eee
*data
)
2083 struct rtl8169_private
*tp
= netdev_priv(dev
);
2084 struct device
*d
= tp_to_dev(tp
);
2085 int old_adv
, adv
= 0, cap
, ret
;
2087 pm_runtime_get_noresume(d
);
2089 if (!dev
->phydev
|| !pm_runtime_active(d
)) {
2094 if (dev
->phydev
->autoneg
== AUTONEG_DISABLE
||
2095 dev
->phydev
->duplex
!= DUPLEX_FULL
) {
2096 ret
= -EPROTONOSUPPORT
;
2100 /* Get Supported EEE */
2101 ret
= rtl_get_eee_supp(tp
);
2106 ret
= rtl_get_eee_adv(tp
);
2111 if (data
->eee_enabled
) {
2112 adv
= !data
->advertised
? cap
:
2113 ethtool_adv_to_mmd_eee_adv_t(data
->advertised
) & cap
;
2114 /* Mask prohibited EEE modes */
2115 adv
&= ~dev
->phydev
->eee_broken_modes
;
2118 if (old_adv
!= adv
) {
2119 ret
= rtl_set_eee_adv(tp
, adv
);
2123 /* Restart autonegotiation so the new modes get sent to the
2126 ret
= phy_restart_aneg(dev
->phydev
);
2130 pm_runtime_put_noidle(d
);
2131 return ret
< 0 ? ret
: 0;
2134 static const struct ethtool_ops rtl8169_ethtool_ops
= {
2135 .get_drvinfo
= rtl8169_get_drvinfo
,
2136 .get_regs_len
= rtl8169_get_regs_len
,
2137 .get_link
= ethtool_op_get_link
,
2138 .get_coalesce
= rtl_get_coalesce
,
2139 .set_coalesce
= rtl_set_coalesce
,
2140 .get_msglevel
= rtl8169_get_msglevel
,
2141 .set_msglevel
= rtl8169_set_msglevel
,
2142 .get_regs
= rtl8169_get_regs
,
2143 .get_wol
= rtl8169_get_wol
,
2144 .set_wol
= rtl8169_set_wol
,
2145 .get_strings
= rtl8169_get_strings
,
2146 .get_sset_count
= rtl8169_get_sset_count
,
2147 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
2148 .get_ts_info
= ethtool_op_get_ts_info
,
2149 .nway_reset
= phy_ethtool_nway_reset
,
2150 .get_eee
= rtl8169_get_eee
,
2151 .set_eee
= rtl8169_set_eee
,
2152 .get_link_ksettings
= phy_ethtool_get_link_ksettings
,
2153 .set_link_ksettings
= phy_ethtool_set_link_ksettings
,
2156 static void rtl_enable_eee(struct rtl8169_private
*tp
)
2158 int supported
= rtl_get_eee_supp(tp
);
2161 rtl_set_eee_adv(tp
, supported
);
2164 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
)
2167 * The driver currently handles the 8168Bf and the 8168Be identically
2168 * but they can be identified more specifically through the test below
2171 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2173 * Same thing for the 8101Eb and the 8101Ec:
2175 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2177 static const struct rtl_mac_info
{
2182 /* 8168EP family. */
2183 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51
},
2184 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50
},
2185 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49
},
2188 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46
},
2189 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45
},
2192 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44
},
2193 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42
},
2194 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41
},
2195 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40
},
2198 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38
},
2199 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36
},
2200 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35
},
2203 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34
},
2204 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32
},
2205 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33
},
2208 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25
},
2209 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26
},
2211 /* 8168DP family. */
2212 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27
},
2213 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28
},
2214 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31
},
2217 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23
},
2218 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18
},
2219 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24
},
2220 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19
},
2221 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20
},
2222 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21
},
2223 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22
},
2226 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12
},
2227 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17
},
2228 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11
},
2231 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39
},
2232 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37
},
2233 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29
},
2234 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30
},
2235 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08
},
2236 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08
},
2237 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07
},
2238 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07
},
2239 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13
},
2240 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10
},
2241 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16
},
2242 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09
},
2243 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09
},
2244 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16
},
2245 /* FIXME: where did these entries come from ? -- FR */
2246 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15
},
2247 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14
},
2250 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06
},
2251 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05
},
2252 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04
},
2253 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03
},
2254 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02
},
2255 { 0xfc8, 0x000, RTL_GIGA_MAC_VER_01
},
2258 { 0x000, 0x000, RTL_GIGA_MAC_NONE
}
2260 const struct rtl_mac_info
*p
= mac_info
;
2261 u16 reg
= RTL_R32(tp
, TxConfig
) >> 20;
2263 while ((reg
& p
->mask
) != p
->val
)
2265 tp
->mac_version
= p
->mac_version
;
2267 if (tp
->mac_version
== RTL_GIGA_MAC_NONE
) {
2268 dev_err(tp_to_dev(tp
), "unknown chip XID %03x\n", reg
& 0xfcf);
2269 } else if (!tp
->supports_gmii
) {
2270 if (tp
->mac_version
== RTL_GIGA_MAC_VER_42
)
2271 tp
->mac_version
= RTL_GIGA_MAC_VER_43
;
2272 else if (tp
->mac_version
== RTL_GIGA_MAC_VER_45
)
2273 tp
->mac_version
= RTL_GIGA_MAC_VER_47
;
2274 else if (tp
->mac_version
== RTL_GIGA_MAC_VER_46
)
2275 tp
->mac_version
= RTL_GIGA_MAC_VER_48
;
2284 static void __rtl_writephy_batch(struct rtl8169_private
*tp
,
2285 const struct phy_reg
*regs
, int len
)
2288 rtl_writephy(tp
, regs
->reg
, regs
->val
);
2293 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a))
2295 #define PHY_READ 0x00000000
2296 #define PHY_DATA_OR 0x10000000
2297 #define PHY_DATA_AND 0x20000000
2298 #define PHY_BJMPN 0x30000000
2299 #define PHY_MDIO_CHG 0x40000000
2300 #define PHY_CLEAR_READCOUNT 0x70000000
2301 #define PHY_WRITE 0x80000000
2302 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2303 #define PHY_COMP_EQ_SKIPN 0xa0000000
2304 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2305 #define PHY_WRITE_PREVIOUS 0xc0000000
2306 #define PHY_SKIPN 0xd0000000
2307 #define PHY_DELAY_MS 0xe0000000
2311 char version
[RTL_VER_SIZE
];
2317 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2319 static bool rtl_fw_format_ok(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
2321 const struct firmware
*fw
= rtl_fw
->fw
;
2322 struct fw_info
*fw_info
= (struct fw_info
*)fw
->data
;
2323 struct rtl_fw_phy_action
*pa
= &rtl_fw
->phy_action
;
2324 char *version
= rtl_fw
->version
;
2327 if (fw
->size
< FW_OPCODE_SIZE
)
2330 if (!fw_info
->magic
) {
2331 size_t i
, size
, start
;
2334 if (fw
->size
< sizeof(*fw_info
))
2337 for (i
= 0; i
< fw
->size
; i
++)
2338 checksum
+= fw
->data
[i
];
2342 start
= le32_to_cpu(fw_info
->fw_start
);
2343 if (start
> fw
->size
)
2346 size
= le32_to_cpu(fw_info
->fw_len
);
2347 if (size
> (fw
->size
- start
) / FW_OPCODE_SIZE
)
2350 memcpy(version
, fw_info
->version
, RTL_VER_SIZE
);
2352 pa
->code
= (__le32
*)(fw
->data
+ start
);
2355 if (fw
->size
% FW_OPCODE_SIZE
)
2358 strlcpy(version
, tp
->fw_name
, RTL_VER_SIZE
);
2360 pa
->code
= (__le32
*)fw
->data
;
2361 pa
->size
= fw
->size
/ FW_OPCODE_SIZE
;
2363 version
[RTL_VER_SIZE
- 1] = 0;
2370 static bool rtl_fw_data_ok(struct rtl8169_private
*tp
, struct net_device
*dev
,
2371 struct rtl_fw_phy_action
*pa
)
2376 for (index
= 0; index
< pa
->size
; index
++) {
2377 u32 action
= le32_to_cpu(pa
->code
[index
]);
2378 u32 regno
= (action
& 0x0fff0000) >> 16;
2380 switch(action
& 0xf0000000) {
2385 case PHY_CLEAR_READCOUNT
:
2387 case PHY_WRITE_PREVIOUS
:
2392 if (regno
> index
) {
2393 netif_err(tp
, ifup
, tp
->dev
,
2394 "Out of range of firmware\n");
2398 case PHY_READCOUNT_EQ_SKIP
:
2399 if (index
+ 2 >= pa
->size
) {
2400 netif_err(tp
, ifup
, tp
->dev
,
2401 "Out of range of firmware\n");
2405 case PHY_COMP_EQ_SKIPN
:
2406 case PHY_COMP_NEQ_SKIPN
:
2408 if (index
+ 1 + regno
>= pa
->size
) {
2409 netif_err(tp
, ifup
, tp
->dev
,
2410 "Out of range of firmware\n");
2416 netif_err(tp
, ifup
, tp
->dev
,
2417 "Invalid action 0x%08x\n", action
);
2426 static int rtl_check_firmware(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
2428 struct net_device
*dev
= tp
->dev
;
2431 if (!rtl_fw_format_ok(tp
, rtl_fw
)) {
2432 netif_err(tp
, ifup
, dev
, "invalid firmware\n");
2436 if (rtl_fw_data_ok(tp
, dev
, &rtl_fw
->phy_action
))
2442 static void rtl_phy_write_fw(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
2444 struct rtl_fw_phy_action
*pa
= &rtl_fw
->phy_action
;
2445 struct mdio_ops org
, *ops
= &tp
->mdio_ops
;
2449 predata
= count
= 0;
2450 org
.write
= ops
->write
;
2451 org
.read
= ops
->read
;
2453 for (index
= 0; index
< pa
->size
; ) {
2454 u32 action
= le32_to_cpu(pa
->code
[index
]);
2455 u32 data
= action
& 0x0000ffff;
2456 u32 regno
= (action
& 0x0fff0000) >> 16;
2461 switch(action
& 0xf0000000) {
2463 predata
= rtl_readphy(tp
, regno
);
2480 ops
->write
= org
.write
;
2481 ops
->read
= org
.read
;
2482 } else if (data
== 1) {
2483 ops
->write
= mac_mcu_write
;
2484 ops
->read
= mac_mcu_read
;
2489 case PHY_CLEAR_READCOUNT
:
2494 rtl_writephy(tp
, regno
, data
);
2497 case PHY_READCOUNT_EQ_SKIP
:
2498 index
+= (count
== data
) ? 2 : 1;
2500 case PHY_COMP_EQ_SKIPN
:
2501 if (predata
== data
)
2505 case PHY_COMP_NEQ_SKIPN
:
2506 if (predata
!= data
)
2510 case PHY_WRITE_PREVIOUS
:
2511 rtl_writephy(tp
, regno
, predata
);
2527 ops
->write
= org
.write
;
2528 ops
->read
= org
.read
;
2531 static void rtl_release_firmware(struct rtl8169_private
*tp
)
2534 release_firmware(tp
->rtl_fw
->fw
);
2540 static void rtl_apply_firmware(struct rtl8169_private
*tp
)
2542 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2544 rtl_phy_write_fw(tp
, tp
->rtl_fw
);
2547 static void rtl_apply_firmware_cond(struct rtl8169_private
*tp
, u8 reg
, u16 val
)
2549 if (rtl_readphy(tp
, reg
) != val
)
2550 netif_warn(tp
, hw
, tp
->dev
, "chipset not ready for firmware\n");
2552 rtl_apply_firmware(tp
);
2555 static void rtl8168_config_eee_mac(struct rtl8169_private
*tp
)
2557 /* Adjust EEE LED frequency */
2558 if (tp
->mac_version
!= RTL_GIGA_MAC_VER_38
)
2559 RTL_W8(tp
, EEE_LED
, RTL_R8(tp
, EEE_LED
) & ~0x07);
2561 rtl_eri_set_bits(tp
, 0x1b0, ERIAR_MASK_1111
, 0x0003);
2564 static void rtl8168f_config_eee_phy(struct rtl8169_private
*tp
)
2566 struct phy_device
*phydev
= tp
->phydev
;
2568 phy_write(phydev
, 0x1f, 0x0007);
2569 phy_write(phydev
, 0x1e, 0x0020);
2570 phy_set_bits(phydev
, 0x15, BIT(8));
2572 phy_write(phydev
, 0x1f, 0x0005);
2573 phy_write(phydev
, 0x05, 0x8b85);
2574 phy_set_bits(phydev
, 0x06, BIT(13));
2576 phy_write(phydev
, 0x1f, 0x0000);
2579 static void rtl8168g_config_eee_phy(struct rtl8169_private
*tp
)
2581 phy_write(tp
->phydev
, 0x1f, 0x0a43);
2582 phy_set_bits(tp
->phydev
, 0x11, BIT(4));
2583 phy_write(tp
->phydev
, 0x1f, 0x0000);
2586 static void rtl8169s_hw_phy_config(struct rtl8169_private
*tp
)
2588 static const struct phy_reg phy_reg_init
[] = {
2650 rtl_writephy_batch(tp
, phy_reg_init
);
2653 static void rtl8169sb_hw_phy_config(struct rtl8169_private
*tp
)
2655 static const struct phy_reg phy_reg_init
[] = {
2661 rtl_writephy_batch(tp
, phy_reg_init
);
2664 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private
*tp
)
2666 struct pci_dev
*pdev
= tp
->pci_dev
;
2668 if ((pdev
->subsystem_vendor
!= PCI_VENDOR_ID_GIGABYTE
) ||
2669 (pdev
->subsystem_device
!= 0xe000))
2672 rtl_writephy(tp
, 0x1f, 0x0001);
2673 rtl_writephy(tp
, 0x10, 0xf01b);
2674 rtl_writephy(tp
, 0x1f, 0x0000);
2677 static void rtl8169scd_hw_phy_config(struct rtl8169_private
*tp
)
2679 static const struct phy_reg phy_reg_init
[] = {
2719 rtl_writephy_batch(tp
, phy_reg_init
);
2721 rtl8169scd_hw_phy_config_quirk(tp
);
2724 static void rtl8169sce_hw_phy_config(struct rtl8169_private
*tp
)
2726 static const struct phy_reg phy_reg_init
[] = {
2774 rtl_writephy_batch(tp
, phy_reg_init
);
2777 static void rtl8168bb_hw_phy_config(struct rtl8169_private
*tp
)
2779 static const struct phy_reg phy_reg_init
[] = {
2784 rtl_writephy(tp
, 0x1f, 0x0001);
2785 rtl_patchphy(tp
, 0x16, 1 << 0);
2787 rtl_writephy_batch(tp
, phy_reg_init
);
2790 static void rtl8168bef_hw_phy_config(struct rtl8169_private
*tp
)
2792 static const struct phy_reg phy_reg_init
[] = {
2798 rtl_writephy_batch(tp
, phy_reg_init
);
2801 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private
*tp
)
2803 static const struct phy_reg phy_reg_init
[] = {
2811 rtl_writephy_batch(tp
, phy_reg_init
);
2814 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private
*tp
)
2816 static const struct phy_reg phy_reg_init
[] = {
2822 rtl_writephy(tp
, 0x1f, 0x0000);
2823 rtl_patchphy(tp
, 0x14, 1 << 5);
2824 rtl_patchphy(tp
, 0x0d, 1 << 5);
2826 rtl_writephy_batch(tp
, phy_reg_init
);
2829 static void rtl8168c_1_hw_phy_config(struct rtl8169_private
*tp
)
2831 static const struct phy_reg phy_reg_init
[] = {
2851 rtl_writephy_batch(tp
, phy_reg_init
);
2853 rtl_patchphy(tp
, 0x14, 1 << 5);
2854 rtl_patchphy(tp
, 0x0d, 1 << 5);
2855 rtl_writephy(tp
, 0x1f, 0x0000);
2858 static void rtl8168c_2_hw_phy_config(struct rtl8169_private
*tp
)
2860 static const struct phy_reg phy_reg_init
[] = {
2878 rtl_writephy_batch(tp
, phy_reg_init
);
2880 rtl_patchphy(tp
, 0x16, 1 << 0);
2881 rtl_patchphy(tp
, 0x14, 1 << 5);
2882 rtl_patchphy(tp
, 0x0d, 1 << 5);
2883 rtl_writephy(tp
, 0x1f, 0x0000);
2886 static void rtl8168c_3_hw_phy_config(struct rtl8169_private
*tp
)
2888 static const struct phy_reg phy_reg_init
[] = {
2900 rtl_writephy_batch(tp
, phy_reg_init
);
2902 rtl_patchphy(tp
, 0x16, 1 << 0);
2903 rtl_patchphy(tp
, 0x14, 1 << 5);
2904 rtl_patchphy(tp
, 0x0d, 1 << 5);
2905 rtl_writephy(tp
, 0x1f, 0x0000);
2908 static void rtl8168c_4_hw_phy_config(struct rtl8169_private
*tp
)
2910 rtl8168c_3_hw_phy_config(tp
);
2913 static void rtl8168d_1_hw_phy_config(struct rtl8169_private
*tp
)
2915 static const struct phy_reg phy_reg_init_0
[] = {
2916 /* Channel Estimation */
2937 * Enhance line driver power
2946 * Can not link to 1Gbps with bad cable
2947 * Decrease SNR threshold form 21.07dB to 19.04dB
2956 rtl_writephy_batch(tp
, phy_reg_init_0
);
2960 * Fine Tune Switching regulator parameter
2962 rtl_writephy(tp
, 0x1f, 0x0002);
2963 rtl_w0w1_phy(tp
, 0x0b, 0x0010, 0x00ef);
2964 rtl_w0w1_phy(tp
, 0x0c, 0xa200, 0x5d00);
2966 if (rtl8168d_efuse_read(tp
, 0x01) == 0xb1) {
2967 static const struct phy_reg phy_reg_init
[] = {
2977 rtl_writephy_batch(tp
, phy_reg_init
);
2979 val
= rtl_readphy(tp
, 0x0d);
2981 if ((val
& 0x00ff) != 0x006c) {
2982 static const u32 set
[] = {
2983 0x0065, 0x0066, 0x0067, 0x0068,
2984 0x0069, 0x006a, 0x006b, 0x006c
2988 rtl_writephy(tp
, 0x1f, 0x0002);
2991 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2992 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
2995 static const struct phy_reg phy_reg_init
[] = {
3003 rtl_writephy_batch(tp
, phy_reg_init
);
3006 /* RSET couple improve */
3007 rtl_writephy(tp
, 0x1f, 0x0002);
3008 rtl_patchphy(tp
, 0x0d, 0x0300);
3009 rtl_patchphy(tp
, 0x0f, 0x0010);
3011 /* Fine tune PLL performance */
3012 rtl_writephy(tp
, 0x1f, 0x0002);
3013 rtl_w0w1_phy(tp
, 0x02, 0x0100, 0x0600);
3014 rtl_w0w1_phy(tp
, 0x03, 0x0000, 0xe000);
3016 rtl_writephy(tp
, 0x1f, 0x0005);
3017 rtl_writephy(tp
, 0x05, 0x001b);
3019 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xbf00);
3021 rtl_writephy(tp
, 0x1f, 0x0000);
3024 static void rtl8168d_2_hw_phy_config(struct rtl8169_private
*tp
)
3026 static const struct phy_reg phy_reg_init_0
[] = {
3027 /* Channel Estimation */
3048 * Enhance line driver power
3057 * Can not link to 1Gbps with bad cable
3058 * Decrease SNR threshold form 21.07dB to 19.04dB
3067 rtl_writephy_batch(tp
, phy_reg_init_0
);
3069 if (rtl8168d_efuse_read(tp
, 0x01) == 0xb1) {
3070 static const struct phy_reg phy_reg_init
[] = {
3081 rtl_writephy_batch(tp
, phy_reg_init
);
3083 val
= rtl_readphy(tp
, 0x0d);
3084 if ((val
& 0x00ff) != 0x006c) {
3085 static const u32 set
[] = {
3086 0x0065, 0x0066, 0x0067, 0x0068,
3087 0x0069, 0x006a, 0x006b, 0x006c
3091 rtl_writephy(tp
, 0x1f, 0x0002);
3094 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
3095 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
3098 static const struct phy_reg phy_reg_init
[] = {
3106 rtl_writephy_batch(tp
, phy_reg_init
);
3109 /* Fine tune PLL performance */
3110 rtl_writephy(tp
, 0x1f, 0x0002);
3111 rtl_w0w1_phy(tp
, 0x02, 0x0100, 0x0600);
3112 rtl_w0w1_phy(tp
, 0x03, 0x0000, 0xe000);
3114 /* Switching regulator Slew rate */
3115 rtl_writephy(tp
, 0x1f, 0x0002);
3116 rtl_patchphy(tp
, 0x0f, 0x0017);
3118 rtl_writephy(tp
, 0x1f, 0x0005);
3119 rtl_writephy(tp
, 0x05, 0x001b);
3121 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xb300);
3123 rtl_writephy(tp
, 0x1f, 0x0000);
3126 static void rtl8168d_3_hw_phy_config(struct rtl8169_private
*tp
)
3128 static const struct phy_reg phy_reg_init
[] = {
3184 rtl_writephy_batch(tp
, phy_reg_init
);
3187 static void rtl8168d_4_hw_phy_config(struct rtl8169_private
*tp
)
3189 static const struct phy_reg phy_reg_init
[] = {
3199 rtl_writephy_batch(tp
, phy_reg_init
);
3200 rtl_patchphy(tp
, 0x0d, 1 << 5);
3203 static void rtl8168e_1_hw_phy_config(struct rtl8169_private
*tp
)
3205 static const struct phy_reg phy_reg_init
[] = {
3206 /* Enable Delay cap */
3212 /* Channel estimation fine tune */
3221 /* Update PFM & 10M TX idle timer */
3233 rtl_apply_firmware(tp
);
3235 rtl_writephy_batch(tp
, phy_reg_init
);
3237 /* DCO enable for 10M IDLE Power */
3238 rtl_writephy(tp
, 0x1f, 0x0007);
3239 rtl_writephy(tp
, 0x1e, 0x0023);
3240 rtl_w0w1_phy(tp
, 0x17, 0x0006, 0x0000);
3241 rtl_writephy(tp
, 0x1f, 0x0000);
3243 /* For impedance matching */
3244 rtl_writephy(tp
, 0x1f, 0x0002);
3245 rtl_w0w1_phy(tp
, 0x08, 0x8000, 0x7f00);
3246 rtl_writephy(tp
, 0x1f, 0x0000);
3248 /* PHY auto speed down */
3249 rtl_writephy(tp
, 0x1f, 0x0007);
3250 rtl_writephy(tp
, 0x1e, 0x002d);
3251 rtl_w0w1_phy(tp
, 0x18, 0x0050, 0x0000);
3252 rtl_writephy(tp
, 0x1f, 0x0000);
3253 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
3255 rtl_writephy(tp
, 0x1f, 0x0005);
3256 rtl_writephy(tp
, 0x05, 0x8b86);
3257 rtl_w0w1_phy(tp
, 0x06, 0x0001, 0x0000);
3258 rtl_writephy(tp
, 0x1f, 0x0000);
3260 rtl_writephy(tp
, 0x1f, 0x0005);
3261 rtl_writephy(tp
, 0x05, 0x8b85);
3262 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x2000);
3263 rtl_writephy(tp
, 0x1f, 0x0007);
3264 rtl_writephy(tp
, 0x1e, 0x0020);
3265 rtl_w0w1_phy(tp
, 0x15, 0x0000, 0x1100);
3266 rtl_writephy(tp
, 0x1f, 0x0006);
3267 rtl_writephy(tp
, 0x00, 0x5a00);
3268 rtl_writephy(tp
, 0x1f, 0x0000);
3269 rtl_writephy(tp
, 0x0d, 0x0007);
3270 rtl_writephy(tp
, 0x0e, 0x003c);
3271 rtl_writephy(tp
, 0x0d, 0x4007);
3272 rtl_writephy(tp
, 0x0e, 0x0000);
3273 rtl_writephy(tp
, 0x0d, 0x0000);
3276 static void rtl_rar_exgmac_set(struct rtl8169_private
*tp
, u8
*addr
)
3279 addr
[0] | (addr
[1] << 8),
3280 addr
[2] | (addr
[3] << 8),
3281 addr
[4] | (addr
[5] << 8)
3284 rtl_eri_write(tp
, 0xe0, ERIAR_MASK_1111
, w
[0] | (w
[1] << 16));
3285 rtl_eri_write(tp
, 0xe4, ERIAR_MASK_1111
, w
[2]);
3286 rtl_eri_write(tp
, 0xf0, ERIAR_MASK_1111
, w
[0] << 16);
3287 rtl_eri_write(tp
, 0xf4, ERIAR_MASK_1111
, w
[1] | (w
[2] << 16));
3290 static void rtl8168e_2_hw_phy_config(struct rtl8169_private
*tp
)
3292 static const struct phy_reg phy_reg_init
[] = {
3293 /* Enable Delay cap */
3302 /* Channel estimation fine tune */
3319 rtl_apply_firmware(tp
);
3321 rtl_writephy_batch(tp
, phy_reg_init
);
3323 /* For 4-corner performance improve */
3324 rtl_writephy(tp
, 0x1f, 0x0005);
3325 rtl_writephy(tp
, 0x05, 0x8b80);
3326 rtl_w0w1_phy(tp
, 0x17, 0x0006, 0x0000);
3327 rtl_writephy(tp
, 0x1f, 0x0000);
3329 /* PHY auto speed down */
3330 rtl_writephy(tp
, 0x1f, 0x0004);
3331 rtl_writephy(tp
, 0x1f, 0x0007);
3332 rtl_writephy(tp
, 0x1e, 0x002d);
3333 rtl_w0w1_phy(tp
, 0x18, 0x0010, 0x0000);
3334 rtl_writephy(tp
, 0x1f, 0x0002);
3335 rtl_writephy(tp
, 0x1f, 0x0000);
3336 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
3338 /* improve 10M EEE waveform */
3339 rtl_writephy(tp
, 0x1f, 0x0005);
3340 rtl_writephy(tp
, 0x05, 0x8b86);
3341 rtl_w0w1_phy(tp
, 0x06, 0x0001, 0x0000);
3342 rtl_writephy(tp
, 0x1f, 0x0000);
3344 /* Improve 2-pair detection performance */
3345 rtl_writephy(tp
, 0x1f, 0x0005);
3346 rtl_writephy(tp
, 0x05, 0x8b85);
3347 rtl_w0w1_phy(tp
, 0x06, 0x4000, 0x0000);
3348 rtl_writephy(tp
, 0x1f, 0x0000);
3350 rtl8168f_config_eee_phy(tp
);
3354 rtl_writephy(tp
, 0x1f, 0x0003);
3355 rtl_w0w1_phy(tp
, 0x19, 0x0001, 0x0000);
3356 rtl_w0w1_phy(tp
, 0x10, 0x0400, 0x0000);
3357 rtl_writephy(tp
, 0x1f, 0x0000);
3358 rtl_writephy(tp
, 0x1f, 0x0005);
3359 rtl_w0w1_phy(tp
, 0x01, 0x0100, 0x0000);
3360 rtl_writephy(tp
, 0x1f, 0x0000);
3362 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3363 rtl_rar_exgmac_set(tp
, tp
->dev
->dev_addr
);
3366 static void rtl8168f_hw_phy_config(struct rtl8169_private
*tp
)
3368 /* For 4-corner performance improve */
3369 rtl_writephy(tp
, 0x1f, 0x0005);
3370 rtl_writephy(tp
, 0x05, 0x8b80);
3371 rtl_w0w1_phy(tp
, 0x06, 0x0006, 0x0000);
3372 rtl_writephy(tp
, 0x1f, 0x0000);
3374 /* PHY auto speed down */
3375 rtl_writephy(tp
, 0x1f, 0x0007);
3376 rtl_writephy(tp
, 0x1e, 0x002d);
3377 rtl_w0w1_phy(tp
, 0x18, 0x0010, 0x0000);
3378 rtl_writephy(tp
, 0x1f, 0x0000);
3379 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
3381 /* Improve 10M EEE waveform */
3382 rtl_writephy(tp
, 0x1f, 0x0005);
3383 rtl_writephy(tp
, 0x05, 0x8b86);
3384 rtl_w0w1_phy(tp
, 0x06, 0x0001, 0x0000);
3385 rtl_writephy(tp
, 0x1f, 0x0000);
3387 rtl8168f_config_eee_phy(tp
);
3391 static void rtl8168f_1_hw_phy_config(struct rtl8169_private
*tp
)
3393 static const struct phy_reg phy_reg_init
[] = {
3394 /* Channel estimation fine tune */
3399 /* Modify green table for giga & fnet */
3416 /* Modify green table for 10M */
3422 /* Disable hiimpedance detection (RTCT) */
3428 rtl_apply_firmware(tp
);
3430 rtl_writephy_batch(tp
, phy_reg_init
);
3432 rtl8168f_hw_phy_config(tp
);
3434 /* Improve 2-pair detection performance */
3435 rtl_writephy(tp
, 0x1f, 0x0005);
3436 rtl_writephy(tp
, 0x05, 0x8b85);
3437 rtl_w0w1_phy(tp
, 0x06, 0x4000, 0x0000);
3438 rtl_writephy(tp
, 0x1f, 0x0000);
3441 static void rtl8168f_2_hw_phy_config(struct rtl8169_private
*tp
)
3443 rtl_apply_firmware(tp
);
3445 rtl8168f_hw_phy_config(tp
);
3448 static void rtl8411_hw_phy_config(struct rtl8169_private
*tp
)
3450 static const struct phy_reg phy_reg_init
[] = {
3451 /* Channel estimation fine tune */
3456 /* Modify green table for giga & fnet */
3473 /* Modify green table for 10M */
3479 /* Disable hiimpedance detection (RTCT) */
3486 rtl_apply_firmware(tp
);
3488 rtl8168f_hw_phy_config(tp
);
3490 /* Improve 2-pair detection performance */
3491 rtl_writephy(tp
, 0x1f, 0x0005);
3492 rtl_writephy(tp
, 0x05, 0x8b85);
3493 rtl_w0w1_phy(tp
, 0x06, 0x4000, 0x0000);
3494 rtl_writephy(tp
, 0x1f, 0x0000);
3496 rtl_writephy_batch(tp
, phy_reg_init
);
3498 /* Modify green table for giga */
3499 rtl_writephy(tp
, 0x1f, 0x0005);
3500 rtl_writephy(tp
, 0x05, 0x8b54);
3501 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0800);
3502 rtl_writephy(tp
, 0x05, 0x8b5d);
3503 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0800);
3504 rtl_writephy(tp
, 0x05, 0x8a7c);
3505 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0100);
3506 rtl_writephy(tp
, 0x05, 0x8a7f);
3507 rtl_w0w1_phy(tp
, 0x06, 0x0100, 0x0000);
3508 rtl_writephy(tp
, 0x05, 0x8a82);
3509 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0100);
3510 rtl_writephy(tp
, 0x05, 0x8a85);
3511 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0100);
3512 rtl_writephy(tp
, 0x05, 0x8a88);
3513 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0100);
3514 rtl_writephy(tp
, 0x1f, 0x0000);
3516 /* uc same-seed solution */
3517 rtl_writephy(tp
, 0x1f, 0x0005);
3518 rtl_writephy(tp
, 0x05, 0x8b85);
3519 rtl_w0w1_phy(tp
, 0x06, 0x8000, 0x0000);
3520 rtl_writephy(tp
, 0x1f, 0x0000);
3523 rtl_writephy(tp
, 0x1f, 0x0003);
3524 rtl_w0w1_phy(tp
, 0x19, 0x0000, 0x0001);
3525 rtl_w0w1_phy(tp
, 0x10, 0x0000, 0x0400);
3526 rtl_writephy(tp
, 0x1f, 0x0000);
3529 static void rtl8168g_disable_aldps(struct rtl8169_private
*tp
)
3531 phy_write(tp
->phydev
, 0x1f, 0x0a43);
3532 phy_clear_bits(tp
->phydev
, 0x10, BIT(2));
3535 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private
*tp
)
3537 struct phy_device
*phydev
= tp
->phydev
;
3539 phy_write(phydev
, 0x1f, 0x0bcc);
3540 phy_clear_bits(phydev
, 0x14, BIT(8));
3542 phy_write(phydev
, 0x1f, 0x0a44);
3543 phy_set_bits(phydev
, 0x11, BIT(7) | BIT(6));
3545 phy_write(phydev
, 0x1f, 0x0a43);
3546 phy_write(phydev
, 0x13, 0x8084);
3547 phy_clear_bits(phydev
, 0x14, BIT(14) | BIT(13));
3548 phy_set_bits(phydev
, 0x10, BIT(12) | BIT(1) | BIT(0));
3550 phy_write(phydev
, 0x1f, 0x0000);
3553 static void rtl8168g_1_hw_phy_config(struct rtl8169_private
*tp
)
3555 rtl_apply_firmware(tp
);
3557 rtl_writephy(tp
, 0x1f, 0x0a46);
3558 if (rtl_readphy(tp
, 0x10) & 0x0100) {
3559 rtl_writephy(tp
, 0x1f, 0x0bcc);
3560 rtl_w0w1_phy(tp
, 0x12, 0x0000, 0x8000);
3562 rtl_writephy(tp
, 0x1f, 0x0bcc);
3563 rtl_w0w1_phy(tp
, 0x12, 0x8000, 0x0000);
3566 rtl_writephy(tp
, 0x1f, 0x0a46);
3567 if (rtl_readphy(tp
, 0x13) & 0x0100) {
3568 rtl_writephy(tp
, 0x1f, 0x0c41);
3569 rtl_w0w1_phy(tp
, 0x15, 0x0002, 0x0000);
3571 rtl_writephy(tp
, 0x1f, 0x0c41);
3572 rtl_w0w1_phy(tp
, 0x15, 0x0000, 0x0002);
3575 /* Enable PHY auto speed down */
3576 rtl_writephy(tp
, 0x1f, 0x0a44);
3577 rtl_w0w1_phy(tp
, 0x11, 0x000c, 0x0000);
3579 rtl8168g_phy_adjust_10m_aldps(tp
);
3581 /* EEE auto-fallback function */
3582 rtl_writephy(tp
, 0x1f, 0x0a4b);
3583 rtl_w0w1_phy(tp
, 0x11, 0x0004, 0x0000);
3585 /* Enable UC LPF tune function */
3586 rtl_writephy(tp
, 0x1f, 0x0a43);
3587 rtl_writephy(tp
, 0x13, 0x8012);
3588 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
3590 rtl_writephy(tp
, 0x1f, 0x0c42);
3591 rtl_w0w1_phy(tp
, 0x11, 0x4000, 0x2000);
3593 /* Improve SWR Efficiency */
3594 rtl_writephy(tp
, 0x1f, 0x0bcd);
3595 rtl_writephy(tp
, 0x14, 0x5065);
3596 rtl_writephy(tp
, 0x14, 0xd065);
3597 rtl_writephy(tp
, 0x1f, 0x0bc8);
3598 rtl_writephy(tp
, 0x11, 0x5655);
3599 rtl_writephy(tp
, 0x1f, 0x0bcd);
3600 rtl_writephy(tp
, 0x14, 0x1065);
3601 rtl_writephy(tp
, 0x14, 0x9065);
3602 rtl_writephy(tp
, 0x14, 0x1065);
3604 rtl8168g_disable_aldps(tp
);
3605 rtl8168g_config_eee_phy(tp
);
3609 static void rtl8168g_2_hw_phy_config(struct rtl8169_private
*tp
)
3611 rtl_apply_firmware(tp
);
3612 rtl8168g_config_eee_phy(tp
);
3616 static void rtl8168h_1_hw_phy_config(struct rtl8169_private
*tp
)
3621 rtl_apply_firmware(tp
);
3623 /* CHN EST parameters adjust - giga master */
3624 rtl_writephy(tp
, 0x1f, 0x0a43);
3625 rtl_writephy(tp
, 0x13, 0x809b);
3626 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0xf800);
3627 rtl_writephy(tp
, 0x13, 0x80a2);
3628 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0xff00);
3629 rtl_writephy(tp
, 0x13, 0x80a4);
3630 rtl_w0w1_phy(tp
, 0x14, 0x8500, 0xff00);
3631 rtl_writephy(tp
, 0x13, 0x809c);
3632 rtl_w0w1_phy(tp
, 0x14, 0xbd00, 0xff00);
3633 rtl_writephy(tp
, 0x1f, 0x0000);
3635 /* CHN EST parameters adjust - giga slave */
3636 rtl_writephy(tp
, 0x1f, 0x0a43);
3637 rtl_writephy(tp
, 0x13, 0x80ad);
3638 rtl_w0w1_phy(tp
, 0x14, 0x7000, 0xf800);
3639 rtl_writephy(tp
, 0x13, 0x80b4);
3640 rtl_w0w1_phy(tp
, 0x14, 0x5000, 0xff00);
3641 rtl_writephy(tp
, 0x13, 0x80ac);
3642 rtl_w0w1_phy(tp
, 0x14, 0x4000, 0xff00);
3643 rtl_writephy(tp
, 0x1f, 0x0000);
3645 /* CHN EST parameters adjust - fnet */
3646 rtl_writephy(tp
, 0x1f, 0x0a43);
3647 rtl_writephy(tp
, 0x13, 0x808e);
3648 rtl_w0w1_phy(tp
, 0x14, 0x1200, 0xff00);
3649 rtl_writephy(tp
, 0x13, 0x8090);
3650 rtl_w0w1_phy(tp
, 0x14, 0xe500, 0xff00);
3651 rtl_writephy(tp
, 0x13, 0x8092);
3652 rtl_w0w1_phy(tp
, 0x14, 0x9f00, 0xff00);
3653 rtl_writephy(tp
, 0x1f, 0x0000);
3655 /* enable R-tune & PGA-retune function */
3657 rtl_writephy(tp
, 0x1f, 0x0a46);
3658 data
= rtl_readphy(tp
, 0x13);
3661 dout_tapbin
|= data
;
3662 data
= rtl_readphy(tp
, 0x12);
3665 dout_tapbin
|= data
;
3666 dout_tapbin
= ~(dout_tapbin
^0x08);
3668 dout_tapbin
&= 0xf000;
3669 rtl_writephy(tp
, 0x1f, 0x0a43);
3670 rtl_writephy(tp
, 0x13, 0x827a);
3671 rtl_w0w1_phy(tp
, 0x14, dout_tapbin
, 0xf000);
3672 rtl_writephy(tp
, 0x13, 0x827b);
3673 rtl_w0w1_phy(tp
, 0x14, dout_tapbin
, 0xf000);
3674 rtl_writephy(tp
, 0x13, 0x827c);
3675 rtl_w0w1_phy(tp
, 0x14, dout_tapbin
, 0xf000);
3676 rtl_writephy(tp
, 0x13, 0x827d);
3677 rtl_w0w1_phy(tp
, 0x14, dout_tapbin
, 0xf000);
3679 rtl_writephy(tp
, 0x1f, 0x0a43);
3680 rtl_writephy(tp
, 0x13, 0x0811);
3681 rtl_w0w1_phy(tp
, 0x14, 0x0800, 0x0000);
3682 rtl_writephy(tp
, 0x1f, 0x0a42);
3683 rtl_w0w1_phy(tp
, 0x16, 0x0002, 0x0000);
3684 rtl_writephy(tp
, 0x1f, 0x0000);
3686 /* enable GPHY 10M */
3687 rtl_writephy(tp
, 0x1f, 0x0a44);
3688 rtl_w0w1_phy(tp
, 0x11, 0x0800, 0x0000);
3689 rtl_writephy(tp
, 0x1f, 0x0000);
3691 /* SAR ADC performance */
3692 rtl_writephy(tp
, 0x1f, 0x0bca);
3693 rtl_w0w1_phy(tp
, 0x17, 0x4000, 0x3000);
3694 rtl_writephy(tp
, 0x1f, 0x0000);
3696 rtl_writephy(tp
, 0x1f, 0x0a43);
3697 rtl_writephy(tp
, 0x13, 0x803f);
3698 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3699 rtl_writephy(tp
, 0x13, 0x8047);
3700 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3701 rtl_writephy(tp
, 0x13, 0x804f);
3702 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3703 rtl_writephy(tp
, 0x13, 0x8057);
3704 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3705 rtl_writephy(tp
, 0x13, 0x805f);
3706 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3707 rtl_writephy(tp
, 0x13, 0x8067);
3708 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3709 rtl_writephy(tp
, 0x13, 0x806f);
3710 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3711 rtl_writephy(tp
, 0x1f, 0x0000);
3713 /* disable phy pfm mode */
3714 rtl_writephy(tp
, 0x1f, 0x0a44);
3715 rtl_w0w1_phy(tp
, 0x11, 0x0000, 0x0080);
3716 rtl_writephy(tp
, 0x1f, 0x0000);
3718 rtl8168g_disable_aldps(tp
);
3719 rtl8168g_config_eee_phy(tp
);
3723 static void rtl8168h_2_hw_phy_config(struct rtl8169_private
*tp
)
3725 u16 ioffset_p3
, ioffset_p2
, ioffset_p1
, ioffset_p0
;
3729 rtl_apply_firmware(tp
);
3731 /* CHIN EST parameter update */
3732 rtl_writephy(tp
, 0x1f, 0x0a43);
3733 rtl_writephy(tp
, 0x13, 0x808a);
3734 rtl_w0w1_phy(tp
, 0x14, 0x000a, 0x003f);
3735 rtl_writephy(tp
, 0x1f, 0x0000);
3737 /* enable R-tune & PGA-retune function */
3738 rtl_writephy(tp
, 0x1f, 0x0a43);
3739 rtl_writephy(tp
, 0x13, 0x0811);
3740 rtl_w0w1_phy(tp
, 0x14, 0x0800, 0x0000);
3741 rtl_writephy(tp
, 0x1f, 0x0a42);
3742 rtl_w0w1_phy(tp
, 0x16, 0x0002, 0x0000);
3743 rtl_writephy(tp
, 0x1f, 0x0000);
3745 /* enable GPHY 10M */
3746 rtl_writephy(tp
, 0x1f, 0x0a44);
3747 rtl_w0w1_phy(tp
, 0x11, 0x0800, 0x0000);
3748 rtl_writephy(tp
, 0x1f, 0x0000);
3750 r8168_mac_ocp_write(tp
, 0xdd02, 0x807d);
3751 data
= r8168_mac_ocp_read(tp
, 0xdd02);
3752 ioffset_p3
= ((data
& 0x80)>>7);
3755 data
= r8168_mac_ocp_read(tp
, 0xdd00);
3756 ioffset_p3
|= ((data
& (0xe000))>>13);
3757 ioffset_p2
= ((data
& (0x1e00))>>9);
3758 ioffset_p1
= ((data
& (0x01e0))>>5);
3759 ioffset_p0
= ((data
& 0x0010)>>4);
3761 ioffset_p0
|= (data
& (0x07));
3762 data
= (ioffset_p3
<<12)|(ioffset_p2
<<8)|(ioffset_p1
<<4)|(ioffset_p0
);
3764 if ((ioffset_p3
!= 0x0f) || (ioffset_p2
!= 0x0f) ||
3765 (ioffset_p1
!= 0x0f) || (ioffset_p0
!= 0x0f)) {
3766 rtl_writephy(tp
, 0x1f, 0x0bcf);
3767 rtl_writephy(tp
, 0x16, data
);
3768 rtl_writephy(tp
, 0x1f, 0x0000);
3771 /* Modify rlen (TX LPF corner frequency) level */
3772 rtl_writephy(tp
, 0x1f, 0x0bcd);
3773 data
= rtl_readphy(tp
, 0x16);
3778 data
= rlen
| (rlen
<<4) | (rlen
<<8) | (rlen
<<12);
3779 rtl_writephy(tp
, 0x17, data
);
3780 rtl_writephy(tp
, 0x1f, 0x0bcd);
3781 rtl_writephy(tp
, 0x1f, 0x0000);
3783 /* disable phy pfm mode */
3784 rtl_writephy(tp
, 0x1f, 0x0a44);
3785 rtl_w0w1_phy(tp
, 0x11, 0x0000, 0x0080);
3786 rtl_writephy(tp
, 0x1f, 0x0000);
3788 rtl8168g_disable_aldps(tp
);
3789 rtl8168g_config_eee_phy(tp
);
3793 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private
*tp
)
3795 /* Enable PHY auto speed down */
3796 rtl_writephy(tp
, 0x1f, 0x0a44);
3797 rtl_w0w1_phy(tp
, 0x11, 0x000c, 0x0000);
3798 rtl_writephy(tp
, 0x1f, 0x0000);
3800 rtl8168g_phy_adjust_10m_aldps(tp
);
3802 /* Enable EEE auto-fallback function */
3803 rtl_writephy(tp
, 0x1f, 0x0a4b);
3804 rtl_w0w1_phy(tp
, 0x11, 0x0004, 0x0000);
3805 rtl_writephy(tp
, 0x1f, 0x0000);
3807 /* Enable UC LPF tune function */
3808 rtl_writephy(tp
, 0x1f, 0x0a43);
3809 rtl_writephy(tp
, 0x13, 0x8012);
3810 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
3811 rtl_writephy(tp
, 0x1f, 0x0000);
3813 /* set rg_sel_sdm_rate */
3814 rtl_writephy(tp
, 0x1f, 0x0c42);
3815 rtl_w0w1_phy(tp
, 0x11, 0x4000, 0x2000);
3816 rtl_writephy(tp
, 0x1f, 0x0000);
3818 rtl8168g_disable_aldps(tp
);
3819 rtl8168g_config_eee_phy(tp
);
3823 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private
*tp
)
3825 rtl8168g_phy_adjust_10m_aldps(tp
);
3827 /* Enable UC LPF tune function */
3828 rtl_writephy(tp
, 0x1f, 0x0a43);
3829 rtl_writephy(tp
, 0x13, 0x8012);
3830 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
3831 rtl_writephy(tp
, 0x1f, 0x0000);
3833 /* Set rg_sel_sdm_rate */
3834 rtl_writephy(tp
, 0x1f, 0x0c42);
3835 rtl_w0w1_phy(tp
, 0x11, 0x4000, 0x2000);
3836 rtl_writephy(tp
, 0x1f, 0x0000);
3838 /* Channel estimation parameters */
3839 rtl_writephy(tp
, 0x1f, 0x0a43);
3840 rtl_writephy(tp
, 0x13, 0x80f3);
3841 rtl_w0w1_phy(tp
, 0x14, 0x8b00, ~0x8bff);
3842 rtl_writephy(tp
, 0x13, 0x80f0);
3843 rtl_w0w1_phy(tp
, 0x14, 0x3a00, ~0x3aff);
3844 rtl_writephy(tp
, 0x13, 0x80ef);
3845 rtl_w0w1_phy(tp
, 0x14, 0x0500, ~0x05ff);
3846 rtl_writephy(tp
, 0x13, 0x80f6);
3847 rtl_w0w1_phy(tp
, 0x14, 0x6e00, ~0x6eff);
3848 rtl_writephy(tp
, 0x13, 0x80ec);
3849 rtl_w0w1_phy(tp
, 0x14, 0x6800, ~0x68ff);
3850 rtl_writephy(tp
, 0x13, 0x80ed);
3851 rtl_w0w1_phy(tp
, 0x14, 0x7c00, ~0x7cff);
3852 rtl_writephy(tp
, 0x13, 0x80f2);
3853 rtl_w0w1_phy(tp
, 0x14, 0xf400, ~0xf4ff);
3854 rtl_writephy(tp
, 0x13, 0x80f4);
3855 rtl_w0w1_phy(tp
, 0x14, 0x8500, ~0x85ff);
3856 rtl_writephy(tp
, 0x1f, 0x0a43);
3857 rtl_writephy(tp
, 0x13, 0x8110);
3858 rtl_w0w1_phy(tp
, 0x14, 0xa800, ~0xa8ff);
3859 rtl_writephy(tp
, 0x13, 0x810f);
3860 rtl_w0w1_phy(tp
, 0x14, 0x1d00, ~0x1dff);
3861 rtl_writephy(tp
, 0x13, 0x8111);
3862 rtl_w0w1_phy(tp
, 0x14, 0xf500, ~0xf5ff);
3863 rtl_writephy(tp
, 0x13, 0x8113);
3864 rtl_w0w1_phy(tp
, 0x14, 0x6100, ~0x61ff);
3865 rtl_writephy(tp
, 0x13, 0x8115);
3866 rtl_w0w1_phy(tp
, 0x14, 0x9200, ~0x92ff);
3867 rtl_writephy(tp
, 0x13, 0x810e);
3868 rtl_w0w1_phy(tp
, 0x14, 0x0400, ~0x04ff);
3869 rtl_writephy(tp
, 0x13, 0x810c);
3870 rtl_w0w1_phy(tp
, 0x14, 0x7c00, ~0x7cff);
3871 rtl_writephy(tp
, 0x13, 0x810b);
3872 rtl_w0w1_phy(tp
, 0x14, 0x5a00, ~0x5aff);
3873 rtl_writephy(tp
, 0x1f, 0x0a43);
3874 rtl_writephy(tp
, 0x13, 0x80d1);
3875 rtl_w0w1_phy(tp
, 0x14, 0xff00, ~0xffff);
3876 rtl_writephy(tp
, 0x13, 0x80cd);
3877 rtl_w0w1_phy(tp
, 0x14, 0x9e00, ~0x9eff);
3878 rtl_writephy(tp
, 0x13, 0x80d3);
3879 rtl_w0w1_phy(tp
, 0x14, 0x0e00, ~0x0eff);
3880 rtl_writephy(tp
, 0x13, 0x80d5);
3881 rtl_w0w1_phy(tp
, 0x14, 0xca00, ~0xcaff);
3882 rtl_writephy(tp
, 0x13, 0x80d7);
3883 rtl_w0w1_phy(tp
, 0x14, 0x8400, ~0x84ff);
3885 /* Force PWM-mode */
3886 rtl_writephy(tp
, 0x1f, 0x0bcd);
3887 rtl_writephy(tp
, 0x14, 0x5065);
3888 rtl_writephy(tp
, 0x14, 0xd065);
3889 rtl_writephy(tp
, 0x1f, 0x0bc8);
3890 rtl_writephy(tp
, 0x12, 0x00ed);
3891 rtl_writephy(tp
, 0x1f, 0x0bcd);
3892 rtl_writephy(tp
, 0x14, 0x1065);
3893 rtl_writephy(tp
, 0x14, 0x9065);
3894 rtl_writephy(tp
, 0x14, 0x1065);
3895 rtl_writephy(tp
, 0x1f, 0x0000);
3897 rtl8168g_disable_aldps(tp
);
3898 rtl8168g_config_eee_phy(tp
);
3902 static void rtl8102e_hw_phy_config(struct rtl8169_private
*tp
)
3904 static const struct phy_reg phy_reg_init
[] = {
3911 rtl_writephy(tp
, 0x1f, 0x0000);
3912 rtl_patchphy(tp
, 0x11, 1 << 12);
3913 rtl_patchphy(tp
, 0x19, 1 << 13);
3914 rtl_patchphy(tp
, 0x10, 1 << 15);
3916 rtl_writephy_batch(tp
, phy_reg_init
);
3919 static void rtl8105e_hw_phy_config(struct rtl8169_private
*tp
)
3921 static const struct phy_reg phy_reg_init
[] = {
3935 /* Disable ALDPS before ram code */
3936 rtl_writephy(tp
, 0x1f, 0x0000);
3937 rtl_writephy(tp
, 0x18, 0x0310);
3940 rtl_apply_firmware(tp
);
3942 rtl_writephy_batch(tp
, phy_reg_init
);
3945 static void rtl8402_hw_phy_config(struct rtl8169_private
*tp
)
3947 /* Disable ALDPS before setting firmware */
3948 rtl_writephy(tp
, 0x1f, 0x0000);
3949 rtl_writephy(tp
, 0x18, 0x0310);
3952 rtl_apply_firmware(tp
);
3955 rtl_eri_write(tp
, 0x1b0, ERIAR_MASK_0011
, 0x0000);
3956 rtl_writephy(tp
, 0x1f, 0x0004);
3957 rtl_writephy(tp
, 0x10, 0x401f);
3958 rtl_writephy(tp
, 0x19, 0x7030);
3959 rtl_writephy(tp
, 0x1f, 0x0000);
3962 static void rtl8106e_hw_phy_config(struct rtl8169_private
*tp
)
3964 static const struct phy_reg phy_reg_init
[] = {
3971 /* Disable ALDPS before ram code */
3972 rtl_writephy(tp
, 0x1f, 0x0000);
3973 rtl_writephy(tp
, 0x18, 0x0310);
3976 rtl_apply_firmware(tp
);
3978 rtl_eri_write(tp
, 0x1b0, ERIAR_MASK_0011
, 0x0000);
3979 rtl_writephy_batch(tp
, phy_reg_init
);
3981 rtl_eri_write(tp
, 0x1d0, ERIAR_MASK_0011
, 0x0000);
3984 static void rtl_hw_phy_config(struct net_device
*dev
)
3986 static const rtl_generic_fct phy_configs
[] = {
3988 [RTL_GIGA_MAC_VER_01
] = NULL
,
3989 [RTL_GIGA_MAC_VER_02
] = rtl8169s_hw_phy_config
,
3990 [RTL_GIGA_MAC_VER_03
] = rtl8169s_hw_phy_config
,
3991 [RTL_GIGA_MAC_VER_04
] = rtl8169sb_hw_phy_config
,
3992 [RTL_GIGA_MAC_VER_05
] = rtl8169scd_hw_phy_config
,
3993 [RTL_GIGA_MAC_VER_06
] = rtl8169sce_hw_phy_config
,
3994 /* PCI-E devices. */
3995 [RTL_GIGA_MAC_VER_07
] = rtl8102e_hw_phy_config
,
3996 [RTL_GIGA_MAC_VER_08
] = rtl8102e_hw_phy_config
,
3997 [RTL_GIGA_MAC_VER_09
] = rtl8102e_hw_phy_config
,
3998 [RTL_GIGA_MAC_VER_10
] = NULL
,
3999 [RTL_GIGA_MAC_VER_11
] = rtl8168bb_hw_phy_config
,
4000 [RTL_GIGA_MAC_VER_12
] = rtl8168bef_hw_phy_config
,
4001 [RTL_GIGA_MAC_VER_13
] = NULL
,
4002 [RTL_GIGA_MAC_VER_14
] = NULL
,
4003 [RTL_GIGA_MAC_VER_15
] = NULL
,
4004 [RTL_GIGA_MAC_VER_16
] = NULL
,
4005 [RTL_GIGA_MAC_VER_17
] = rtl8168bef_hw_phy_config
,
4006 [RTL_GIGA_MAC_VER_18
] = rtl8168cp_1_hw_phy_config
,
4007 [RTL_GIGA_MAC_VER_19
] = rtl8168c_1_hw_phy_config
,
4008 [RTL_GIGA_MAC_VER_20
] = rtl8168c_2_hw_phy_config
,
4009 [RTL_GIGA_MAC_VER_21
] = rtl8168c_3_hw_phy_config
,
4010 [RTL_GIGA_MAC_VER_22
] = rtl8168c_4_hw_phy_config
,
4011 [RTL_GIGA_MAC_VER_23
] = rtl8168cp_2_hw_phy_config
,
4012 [RTL_GIGA_MAC_VER_24
] = rtl8168cp_2_hw_phy_config
,
4013 [RTL_GIGA_MAC_VER_25
] = rtl8168d_1_hw_phy_config
,
4014 [RTL_GIGA_MAC_VER_26
] = rtl8168d_2_hw_phy_config
,
4015 [RTL_GIGA_MAC_VER_27
] = rtl8168d_3_hw_phy_config
,
4016 [RTL_GIGA_MAC_VER_28
] = rtl8168d_4_hw_phy_config
,
4017 [RTL_GIGA_MAC_VER_29
] = rtl8105e_hw_phy_config
,
4018 [RTL_GIGA_MAC_VER_30
] = rtl8105e_hw_phy_config
,
4019 [RTL_GIGA_MAC_VER_31
] = NULL
,
4020 [RTL_GIGA_MAC_VER_32
] = rtl8168e_1_hw_phy_config
,
4021 [RTL_GIGA_MAC_VER_33
] = rtl8168e_1_hw_phy_config
,
4022 [RTL_GIGA_MAC_VER_34
] = rtl8168e_2_hw_phy_config
,
4023 [RTL_GIGA_MAC_VER_35
] = rtl8168f_1_hw_phy_config
,
4024 [RTL_GIGA_MAC_VER_36
] = rtl8168f_2_hw_phy_config
,
4025 [RTL_GIGA_MAC_VER_37
] = rtl8402_hw_phy_config
,
4026 [RTL_GIGA_MAC_VER_38
] = rtl8411_hw_phy_config
,
4027 [RTL_GIGA_MAC_VER_39
] = rtl8106e_hw_phy_config
,
4028 [RTL_GIGA_MAC_VER_40
] = rtl8168g_1_hw_phy_config
,
4029 [RTL_GIGA_MAC_VER_41
] = NULL
,
4030 [RTL_GIGA_MAC_VER_42
] = rtl8168g_2_hw_phy_config
,
4031 [RTL_GIGA_MAC_VER_43
] = rtl8168g_2_hw_phy_config
,
4032 [RTL_GIGA_MAC_VER_44
] = rtl8168g_2_hw_phy_config
,
4033 [RTL_GIGA_MAC_VER_45
] = rtl8168h_1_hw_phy_config
,
4034 [RTL_GIGA_MAC_VER_46
] = rtl8168h_2_hw_phy_config
,
4035 [RTL_GIGA_MAC_VER_47
] = rtl8168h_1_hw_phy_config
,
4036 [RTL_GIGA_MAC_VER_48
] = rtl8168h_2_hw_phy_config
,
4037 [RTL_GIGA_MAC_VER_49
] = rtl8168ep_1_hw_phy_config
,
4038 [RTL_GIGA_MAC_VER_50
] = rtl8168ep_2_hw_phy_config
,
4039 [RTL_GIGA_MAC_VER_51
] = rtl8168ep_2_hw_phy_config
,
4041 struct rtl8169_private
*tp
= netdev_priv(dev
);
4043 if (phy_configs
[tp
->mac_version
])
4044 phy_configs
[tp
->mac_version
](tp
);
4047 static void rtl_schedule_task(struct rtl8169_private
*tp
, enum rtl_flag flag
)
4049 if (!test_and_set_bit(flag
, tp
->wk
.flags
))
4050 schedule_work(&tp
->wk
.work
);
4053 static bool rtl_tbi_enabled(struct rtl8169_private
*tp
)
4055 return (tp
->mac_version
== RTL_GIGA_MAC_VER_01
) &&
4056 (RTL_R8(tp
, PHYstatus
) & TBI_Enable
);
4059 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
4061 rtl_hw_phy_config(dev
);
4063 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
4064 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
4065 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
4066 netif_dbg(tp
, drv
, dev
,
4067 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4068 RTL_W8(tp
, 0x82, 0x01);
4071 /* We may have called phy_speed_down before */
4072 phy_speed_up(tp
->phydev
);
4074 genphy_soft_reset(tp
->phydev
);
4077 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
4081 rtl_unlock_config_regs(tp
);
4083 RTL_W32(tp
, MAC4
, addr
[4] | addr
[5] << 8);
4086 RTL_W32(tp
, MAC0
, addr
[0] | addr
[1] << 8 | addr
[2] << 16 | addr
[3] << 24);
4089 if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
)
4090 rtl_rar_exgmac_set(tp
, addr
);
4092 rtl_lock_config_regs(tp
);
4094 rtl_unlock_work(tp
);
4097 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
4099 struct rtl8169_private
*tp
= netdev_priv(dev
);
4100 struct device
*d
= tp_to_dev(tp
);
4103 ret
= eth_mac_addr(dev
, p
);
4107 pm_runtime_get_noresume(d
);
4109 if (pm_runtime_active(d
))
4110 rtl_rar_set(tp
, dev
->dev_addr
);
4112 pm_runtime_put_noidle(d
);
4117 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
4119 struct rtl8169_private
*tp
= netdev_priv(dev
);
4121 if (!netif_running(dev
))
4124 return phy_mii_ioctl(tp
->phydev
, ifr
, cmd
);
4127 static void rtl_init_mdio_ops(struct rtl8169_private
*tp
)
4129 struct mdio_ops
*ops
= &tp
->mdio_ops
;
4131 switch (tp
->mac_version
) {
4132 case RTL_GIGA_MAC_VER_27
:
4133 ops
->write
= r8168dp_1_mdio_write
;
4134 ops
->read
= r8168dp_1_mdio_read
;
4136 case RTL_GIGA_MAC_VER_28
:
4137 case RTL_GIGA_MAC_VER_31
:
4138 ops
->write
= r8168dp_2_mdio_write
;
4139 ops
->read
= r8168dp_2_mdio_read
;
4141 case RTL_GIGA_MAC_VER_40
... RTL_GIGA_MAC_VER_51
:
4142 ops
->write
= r8168g_mdio_write
;
4143 ops
->read
= r8168g_mdio_read
;
4146 ops
->write
= r8169_mdio_write
;
4147 ops
->read
= r8169_mdio_read
;
4152 static void rtl_wol_suspend_quirk(struct rtl8169_private
*tp
)
4154 switch (tp
->mac_version
) {
4155 case RTL_GIGA_MAC_VER_25
:
4156 case RTL_GIGA_MAC_VER_26
:
4157 case RTL_GIGA_MAC_VER_29
:
4158 case RTL_GIGA_MAC_VER_30
:
4159 case RTL_GIGA_MAC_VER_32
:
4160 case RTL_GIGA_MAC_VER_33
:
4161 case RTL_GIGA_MAC_VER_34
:
4162 case RTL_GIGA_MAC_VER_37
... RTL_GIGA_MAC_VER_51
:
4163 RTL_W32(tp
, RxConfig
, RTL_R32(tp
, RxConfig
) |
4164 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
);
4171 static void r8168_pll_power_down(struct rtl8169_private
*tp
)
4173 if (r8168_check_dash(tp
))
4176 if (tp
->mac_version
== RTL_GIGA_MAC_VER_32
||
4177 tp
->mac_version
== RTL_GIGA_MAC_VER_33
)
4178 rtl_ephy_write(tp
, 0x19, 0xff64);
4180 if (device_may_wakeup(tp_to_dev(tp
))) {
4181 phy_speed_down(tp
->phydev
, false);
4182 rtl_wol_suspend_quirk(tp
);
4186 switch (tp
->mac_version
) {
4187 case RTL_GIGA_MAC_VER_25
... RTL_GIGA_MAC_VER_33
:
4188 case RTL_GIGA_MAC_VER_37
:
4189 case RTL_GIGA_MAC_VER_39
:
4190 case RTL_GIGA_MAC_VER_43
:
4191 case RTL_GIGA_MAC_VER_44
:
4192 case RTL_GIGA_MAC_VER_45
:
4193 case RTL_GIGA_MAC_VER_46
:
4194 case RTL_GIGA_MAC_VER_47
:
4195 case RTL_GIGA_MAC_VER_48
:
4196 case RTL_GIGA_MAC_VER_50
:
4197 case RTL_GIGA_MAC_VER_51
:
4198 RTL_W8(tp
, PMCH
, RTL_R8(tp
, PMCH
) & ~0x80);
4200 case RTL_GIGA_MAC_VER_40
:
4201 case RTL_GIGA_MAC_VER_41
:
4202 case RTL_GIGA_MAC_VER_49
:
4203 rtl_eri_clear_bits(tp
, 0x1a8, ERIAR_MASK_1111
, 0xfc000000);
4204 RTL_W8(tp
, PMCH
, RTL_R8(tp
, PMCH
) & ~0x80);
4209 static void r8168_pll_power_up(struct rtl8169_private
*tp
)
4211 switch (tp
->mac_version
) {
4212 case RTL_GIGA_MAC_VER_25
... RTL_GIGA_MAC_VER_33
:
4213 case RTL_GIGA_MAC_VER_37
:
4214 case RTL_GIGA_MAC_VER_39
:
4215 case RTL_GIGA_MAC_VER_43
:
4216 RTL_W8(tp
, PMCH
, RTL_R8(tp
, PMCH
) | 0x80);
4218 case RTL_GIGA_MAC_VER_44
:
4219 case RTL_GIGA_MAC_VER_45
:
4220 case RTL_GIGA_MAC_VER_46
:
4221 case RTL_GIGA_MAC_VER_47
:
4222 case RTL_GIGA_MAC_VER_48
:
4223 case RTL_GIGA_MAC_VER_50
:
4224 case RTL_GIGA_MAC_VER_51
:
4225 RTL_W8(tp
, PMCH
, RTL_R8(tp
, PMCH
) | 0xc0);
4227 case RTL_GIGA_MAC_VER_40
:
4228 case RTL_GIGA_MAC_VER_41
:
4229 case RTL_GIGA_MAC_VER_49
:
4230 RTL_W8(tp
, PMCH
, RTL_R8(tp
, PMCH
) | 0xc0);
4231 rtl_eri_set_bits(tp
, 0x1a8, ERIAR_MASK_1111
, 0xfc000000);
4235 phy_resume(tp
->phydev
);
4236 /* give MAC/PHY some time to resume */
4240 static void rtl_pll_power_down(struct rtl8169_private
*tp
)
4242 switch (tp
->mac_version
) {
4243 case RTL_GIGA_MAC_VER_01
... RTL_GIGA_MAC_VER_06
:
4244 case RTL_GIGA_MAC_VER_13
... RTL_GIGA_MAC_VER_15
:
4247 r8168_pll_power_down(tp
);
4251 static void rtl_pll_power_up(struct rtl8169_private
*tp
)
4253 switch (tp
->mac_version
) {
4254 case RTL_GIGA_MAC_VER_01
... RTL_GIGA_MAC_VER_06
:
4255 case RTL_GIGA_MAC_VER_13
... RTL_GIGA_MAC_VER_15
:
4258 r8168_pll_power_up(tp
);
4262 static void rtl_init_rxcfg(struct rtl8169_private
*tp
)
4264 switch (tp
->mac_version
) {
4265 case RTL_GIGA_MAC_VER_01
... RTL_GIGA_MAC_VER_06
:
4266 case RTL_GIGA_MAC_VER_10
... RTL_GIGA_MAC_VER_17
:
4267 RTL_W32(tp
, RxConfig
, RX_FIFO_THRESH
| RX_DMA_BURST
);
4269 case RTL_GIGA_MAC_VER_18
... RTL_GIGA_MAC_VER_24
:
4270 case RTL_GIGA_MAC_VER_34
... RTL_GIGA_MAC_VER_36
:
4271 case RTL_GIGA_MAC_VER_38
:
4272 RTL_W32(tp
, RxConfig
, RX128_INT_EN
| RX_MULTI_EN
| RX_DMA_BURST
);
4274 case RTL_GIGA_MAC_VER_40
... RTL_GIGA_MAC_VER_51
:
4275 RTL_W32(tp
, RxConfig
, RX128_INT_EN
| RX_MULTI_EN
| RX_DMA_BURST
| RX_EARLY_OFF
);
4278 RTL_W32(tp
, RxConfig
, RX128_INT_EN
| RX_DMA_BURST
);
4283 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
4285 tp
->dirty_tx
= tp
->cur_tx
= tp
->cur_rx
= 0;
4288 static void rtl_hw_jumbo_enable(struct rtl8169_private
*tp
)
4290 if (tp
->jumbo_ops
.enable
) {
4291 rtl_unlock_config_regs(tp
);
4292 tp
->jumbo_ops
.enable(tp
);
4293 rtl_lock_config_regs(tp
);
4297 static void rtl_hw_jumbo_disable(struct rtl8169_private
*tp
)
4299 if (tp
->jumbo_ops
.disable
) {
4300 rtl_unlock_config_regs(tp
);
4301 tp
->jumbo_ops
.disable(tp
);
4302 rtl_lock_config_regs(tp
);
4306 static void r8168c_hw_jumbo_enable(struct rtl8169_private
*tp
)
4308 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) | Jumbo_En0
);
4309 RTL_W8(tp
, Config4
, RTL_R8(tp
, Config4
) | Jumbo_En1
);
4310 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_512B
);
4313 static void r8168c_hw_jumbo_disable(struct rtl8169_private
*tp
)
4315 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) & ~Jumbo_En0
);
4316 RTL_W8(tp
, Config4
, RTL_R8(tp
, Config4
) & ~Jumbo_En1
);
4317 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
4320 static void r8168dp_hw_jumbo_enable(struct rtl8169_private
*tp
)
4322 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) | Jumbo_En0
);
4325 static void r8168dp_hw_jumbo_disable(struct rtl8169_private
*tp
)
4327 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) & ~Jumbo_En0
);
4330 static void r8168e_hw_jumbo_enable(struct rtl8169_private
*tp
)
4332 RTL_W8(tp
, MaxTxPacketSize
, 0x3f);
4333 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) | Jumbo_En0
);
4334 RTL_W8(tp
, Config4
, RTL_R8(tp
, Config4
) | 0x01);
4335 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_512B
);
4338 static void r8168e_hw_jumbo_disable(struct rtl8169_private
*tp
)
4340 RTL_W8(tp
, MaxTxPacketSize
, 0x0c);
4341 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) & ~Jumbo_En0
);
4342 RTL_W8(tp
, Config4
, RTL_R8(tp
, Config4
) & ~0x01);
4343 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
4346 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private
*tp
)
4348 rtl_tx_performance_tweak(tp
,
4349 PCI_EXP_DEVCTL_READRQ_512B
| PCI_EXP_DEVCTL_NOSNOOP_EN
);
4352 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private
*tp
)
4354 rtl_tx_performance_tweak(tp
,
4355 PCI_EXP_DEVCTL_READRQ_4096B
| PCI_EXP_DEVCTL_NOSNOOP_EN
);
4358 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private
*tp
)
4360 r8168b_0_hw_jumbo_enable(tp
);
4362 RTL_W8(tp
, Config4
, RTL_R8(tp
, Config4
) | (1 << 0));
4365 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private
*tp
)
4367 r8168b_0_hw_jumbo_disable(tp
);
4369 RTL_W8(tp
, Config4
, RTL_R8(tp
, Config4
) & ~(1 << 0));
4372 static void rtl_init_jumbo_ops(struct rtl8169_private
*tp
)
4374 struct jumbo_ops
*ops
= &tp
->jumbo_ops
;
4376 switch (tp
->mac_version
) {
4377 case RTL_GIGA_MAC_VER_11
:
4378 ops
->disable
= r8168b_0_hw_jumbo_disable
;
4379 ops
->enable
= r8168b_0_hw_jumbo_enable
;
4381 case RTL_GIGA_MAC_VER_12
:
4382 case RTL_GIGA_MAC_VER_17
:
4383 ops
->disable
= r8168b_1_hw_jumbo_disable
;
4384 ops
->enable
= r8168b_1_hw_jumbo_enable
;
4386 case RTL_GIGA_MAC_VER_18
: /* Wild guess. Needs info from Realtek. */
4387 case RTL_GIGA_MAC_VER_19
:
4388 case RTL_GIGA_MAC_VER_20
:
4389 case RTL_GIGA_MAC_VER_21
: /* Wild guess. Needs info from Realtek. */
4390 case RTL_GIGA_MAC_VER_22
:
4391 case RTL_GIGA_MAC_VER_23
:
4392 case RTL_GIGA_MAC_VER_24
:
4393 case RTL_GIGA_MAC_VER_25
:
4394 case RTL_GIGA_MAC_VER_26
:
4395 ops
->disable
= r8168c_hw_jumbo_disable
;
4396 ops
->enable
= r8168c_hw_jumbo_enable
;
4398 case RTL_GIGA_MAC_VER_27
:
4399 case RTL_GIGA_MAC_VER_28
:
4400 ops
->disable
= r8168dp_hw_jumbo_disable
;
4401 ops
->enable
= r8168dp_hw_jumbo_enable
;
4403 case RTL_GIGA_MAC_VER_31
: /* Wild guess. Needs info from Realtek. */
4404 case RTL_GIGA_MAC_VER_32
:
4405 case RTL_GIGA_MAC_VER_33
:
4406 case RTL_GIGA_MAC_VER_34
:
4407 ops
->disable
= r8168e_hw_jumbo_disable
;
4408 ops
->enable
= r8168e_hw_jumbo_enable
;
4412 * No action needed for jumbo frames with 8169.
4413 * No jumbo for 810x at all.
4415 case RTL_GIGA_MAC_VER_40
... RTL_GIGA_MAC_VER_51
:
4417 ops
->disable
= NULL
;
4423 DECLARE_RTL_COND(rtl_chipcmd_cond
)
4425 return RTL_R8(tp
, ChipCmd
) & CmdReset
;
4428 static void rtl_hw_reset(struct rtl8169_private
*tp
)
4430 RTL_W8(tp
, ChipCmd
, CmdReset
);
4432 rtl_udelay_loop_wait_low(tp
, &rtl_chipcmd_cond
, 100, 100);
4435 static void rtl_request_firmware(struct rtl8169_private
*tp
)
4437 struct rtl_fw
*rtl_fw
;
4440 /* firmware loaded already or no firmware available */
4441 if (tp
->rtl_fw
|| !tp
->fw_name
)
4444 rtl_fw
= kzalloc(sizeof(*rtl_fw
), GFP_KERNEL
);
4448 rc
= request_firmware(&rtl_fw
->fw
, tp
->fw_name
, tp_to_dev(tp
));
4452 rc
= rtl_check_firmware(tp
, rtl_fw
);
4454 goto err_release_firmware
;
4456 tp
->rtl_fw
= rtl_fw
;
4460 err_release_firmware
:
4461 release_firmware(rtl_fw
->fw
);
4465 netif_warn(tp
, ifup
, tp
->dev
, "unable to load firmware patch %s (%d)\n",
4469 static void rtl_rx_close(struct rtl8169_private
*tp
)
4471 RTL_W32(tp
, RxConfig
, RTL_R32(tp
, RxConfig
) & ~RX_CONFIG_ACCEPT_MASK
);
4474 DECLARE_RTL_COND(rtl_npq_cond
)
4476 return RTL_R8(tp
, TxPoll
) & NPQ
;
4479 DECLARE_RTL_COND(rtl_txcfg_empty_cond
)
4481 return RTL_R32(tp
, TxConfig
) & TXCFG_EMPTY
;
4484 static void rtl8169_hw_reset(struct rtl8169_private
*tp
)
4486 /* Disable interrupts */
4487 rtl8169_irq_mask_and_ack(tp
);
4491 switch (tp
->mac_version
) {
4492 case RTL_GIGA_MAC_VER_27
:
4493 case RTL_GIGA_MAC_VER_28
:
4494 case RTL_GIGA_MAC_VER_31
:
4495 rtl_udelay_loop_wait_low(tp
, &rtl_npq_cond
, 20, 42*42);
4497 case RTL_GIGA_MAC_VER_34
... RTL_GIGA_MAC_VER_38
:
4498 case RTL_GIGA_MAC_VER_40
... RTL_GIGA_MAC_VER_51
:
4499 RTL_W8(tp
, ChipCmd
, RTL_R8(tp
, ChipCmd
) | StopReq
);
4500 rtl_udelay_loop_wait_high(tp
, &rtl_txcfg_empty_cond
, 100, 666);
4503 RTL_W8(tp
, ChipCmd
, RTL_R8(tp
, ChipCmd
) | StopReq
);
4511 static void rtl_set_tx_config_registers(struct rtl8169_private
*tp
)
4513 u32 val
= TX_DMA_BURST
<< TxDMAShift
|
4514 InterFrameGap
<< TxInterFrameGapShift
;
4516 if (tp
->mac_version
>= RTL_GIGA_MAC_VER_34
&&
4517 tp
->mac_version
!= RTL_GIGA_MAC_VER_39
)
4518 val
|= TXCFG_AUTO_FIFO
;
4520 RTL_W32(tp
, TxConfig
, val
);
4523 static void rtl_set_rx_max_size(struct rtl8169_private
*tp
)
4525 /* Low hurts. Let's disable the filtering. */
4526 RTL_W16(tp
, RxMaxSize
, R8169_RX_BUF_SIZE
+ 1);
4529 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
)
4532 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4533 * register to be written before TxDescAddrLow to work.
4534 * Switching from MMIO to I/O access fixes the issue as well.
4536 RTL_W32(tp
, TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
4537 RTL_W32(tp
, TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_BIT_MASK(32));
4538 RTL_W32(tp
, RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
4539 RTL_W32(tp
, RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_BIT_MASK(32));
4542 static void rtl8169_set_magic_reg(struct rtl8169_private
*tp
, unsigned mac_version
)
4546 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
4548 else if (tp
->mac_version
== RTL_GIGA_MAC_VER_06
)
4553 if (RTL_R8(tp
, Config2
) & PCI_Clock_66MHz
)
4556 RTL_W32(tp
, 0x7c, val
);
4559 static void rtl_set_rx_mode(struct net_device
*dev
)
4561 struct rtl8169_private
*tp
= netdev_priv(dev
);
4562 u32 mc_filter
[2]; /* Multicast hash filter */
4566 if (dev
->flags
& IFF_PROMISC
) {
4567 /* Unconditionally log net taps. */
4568 netif_notice(tp
, link
, dev
, "Promiscuous mode enabled\n");
4570 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
4572 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
4573 } else if ((netdev_mc_count(dev
) > multicast_filter_limit
) ||
4574 (dev
->flags
& IFF_ALLMULTI
)) {
4575 /* Too many to filter perfectly -- accept all multicasts. */
4576 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
4577 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
4579 struct netdev_hw_addr
*ha
;
4581 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
4582 mc_filter
[1] = mc_filter
[0] = 0;
4583 netdev_for_each_mc_addr(ha
, dev
) {
4584 int bit_nr
= ether_crc(ETH_ALEN
, ha
->addr
) >> 26;
4585 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
4586 rx_mode
|= AcceptMulticast
;
4590 if (dev
->features
& NETIF_F_RXALL
)
4591 rx_mode
|= (AcceptErr
| AcceptRunt
);
4593 tmp
= (RTL_R32(tp
, RxConfig
) & ~RX_CONFIG_ACCEPT_MASK
) | rx_mode
;
4595 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
4596 u32 data
= mc_filter
[0];
4598 mc_filter
[0] = swab32(mc_filter
[1]);
4599 mc_filter
[1] = swab32(data
);
4602 if (tp
->mac_version
== RTL_GIGA_MAC_VER_35
)
4603 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
4605 RTL_W32(tp
, MAR0
+ 4, mc_filter
[1]);
4606 RTL_W32(tp
, MAR0
+ 0, mc_filter
[0]);
4608 RTL_W32(tp
, RxConfig
, tmp
);
4611 static void rtl_hw_start(struct rtl8169_private
*tp
)
4613 rtl_unlock_config_regs(tp
);
4617 rtl_set_rx_max_size(tp
);
4618 rtl_set_rx_tx_desc_registers(tp
);
4619 rtl_lock_config_regs(tp
);
4621 /* disable interrupt coalescing */
4622 RTL_W16(tp
, IntrMitigate
, 0x0000);
4623 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4624 RTL_R8(tp
, IntrMask
);
4625 RTL_W8(tp
, ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4627 rtl_set_tx_config_registers(tp
);
4629 rtl_set_rx_mode(tp
->dev
);
4630 /* no early-rx interrupts */
4631 RTL_W16(tp
, MultiIntr
, RTL_R16(tp
, MultiIntr
) & 0xf000);
4635 static void rtl_hw_start_8169(struct rtl8169_private
*tp
)
4637 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
4638 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
4640 RTL_W8(tp
, EarlyTxThres
, NoEarlyTx
);
4642 tp
->cp_cmd
|= PCIMulRW
;
4644 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
4645 tp
->mac_version
== RTL_GIGA_MAC_VER_03
) {
4646 netif_dbg(tp
, drv
, tp
->dev
,
4647 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4648 tp
->cp_cmd
|= (1 << 14);
4651 RTL_W16(tp
, CPlusCmd
, tp
->cp_cmd
);
4653 rtl8169_set_magic_reg(tp
, tp
->mac_version
);
4655 RTL_W32(tp
, RxMissed
, 0);
4658 DECLARE_RTL_COND(rtl_csiar_cond
)
4660 return RTL_R32(tp
, CSIAR
) & CSIAR_FLAG
;
4663 static void rtl_csi_write(struct rtl8169_private
*tp
, int addr
, int value
)
4665 u32 func
= PCI_FUNC(tp
->pci_dev
->devfn
);
4667 RTL_W32(tp
, CSIDR
, value
);
4668 RTL_W32(tp
, CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
4669 CSIAR_BYTE_ENABLE
| func
<< 16);
4671 rtl_udelay_loop_wait_low(tp
, &rtl_csiar_cond
, 10, 100);
4674 static u32
rtl_csi_read(struct rtl8169_private
*tp
, int addr
)
4676 u32 func
= PCI_FUNC(tp
->pci_dev
->devfn
);
4678 RTL_W32(tp
, CSIAR
, (addr
& CSIAR_ADDR_MASK
) | func
<< 16 |
4681 return rtl_udelay_loop_wait_high(tp
, &rtl_csiar_cond
, 10, 100) ?
4682 RTL_R32(tp
, CSIDR
) : ~0;
4685 static void rtl_csi_access_enable(struct rtl8169_private
*tp
, u8 val
)
4687 struct pci_dev
*pdev
= tp
->pci_dev
;
4690 /* According to Realtek the value at config space address 0x070f
4691 * controls the L0s/L1 entrance latency. We try standard ECAM access
4692 * first and if it fails fall back to CSI.
4694 if (pdev
->cfg_size
> 0x070f &&
4695 pci_write_config_byte(pdev
, 0x070f, val
) == PCIBIOS_SUCCESSFUL
)
4698 netdev_notice_once(tp
->dev
,
4699 "No native access to PCI extended config space, falling back to CSI\n");
4700 csi
= rtl_csi_read(tp
, 0x070c) & 0x00ffffff;
4701 rtl_csi_write(tp
, 0x070c, csi
| val
<< 24);
4704 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private
*tp
)
4706 rtl_csi_access_enable(tp
, 0x27);
4710 unsigned int offset
;
4715 static void __rtl_ephy_init(struct rtl8169_private
*tp
,
4716 const struct ephy_info
*e
, int len
)
4721 w
= (rtl_ephy_read(tp
, e
->offset
) & ~e
->mask
) | e
->bits
;
4722 rtl_ephy_write(tp
, e
->offset
, w
);
4727 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
4729 static void rtl_disable_clock_request(struct rtl8169_private
*tp
)
4731 pcie_capability_clear_word(tp
->pci_dev
, PCI_EXP_LNKCTL
,
4732 PCI_EXP_LNKCTL_CLKREQ_EN
);
4735 static void rtl_enable_clock_request(struct rtl8169_private
*tp
)
4737 pcie_capability_set_word(tp
->pci_dev
, PCI_EXP_LNKCTL
,
4738 PCI_EXP_LNKCTL_CLKREQ_EN
);
4741 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private
*tp
)
4743 /* work around an issue when PCI reset occurs during L2/L3 state */
4744 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) & ~Rdy_to_L23
);
4747 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private
*tp
, bool enable
)
4750 RTL_W8(tp
, Config5
, RTL_R8(tp
, Config5
) | ASPM_en
);
4751 RTL_W8(tp
, Config2
, RTL_R8(tp
, Config2
) | ClkReqEn
);
4753 RTL_W8(tp
, Config2
, RTL_R8(tp
, Config2
) & ~ClkReqEn
);
4754 RTL_W8(tp
, Config5
, RTL_R8(tp
, Config5
) & ~ASPM_en
);
4760 static void rtl_set_fifo_size(struct rtl8169_private
*tp
, u16 rx_stat
,
4761 u16 tx_stat
, u16 rx_dyn
, u16 tx_dyn
)
4763 /* Usage of dynamic vs. static FIFO is controlled by bit
4764 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
4766 rtl_eri_write(tp
, 0xc8, ERIAR_MASK_1111
, (rx_stat
<< 16) | rx_dyn
);
4767 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_1111
, (tx_stat
<< 16) | tx_dyn
);
4770 static void rtl8168g_set_pause_thresholds(struct rtl8169_private
*tp
,
4773 /* FIFO thresholds for pause flow control */
4774 rtl_eri_write(tp
, 0xcc, ERIAR_MASK_0001
, low
);
4775 rtl_eri_write(tp
, 0xd0, ERIAR_MASK_0001
, high
);
4778 static void rtl_hw_start_8168bb(struct rtl8169_private
*tp
)
4780 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) & ~Beacon_en
);
4782 tp
->cp_cmd
&= CPCMD_QUIRK_MASK
;
4783 RTL_W16(tp
, CPlusCmd
, tp
->cp_cmd
);
4785 if (tp
->dev
->mtu
<= ETH_DATA_LEN
) {
4786 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
|
4787 PCI_EXP_DEVCTL_NOSNOOP_EN
);
4791 static void rtl_hw_start_8168bef(struct rtl8169_private
*tp
)
4793 rtl_hw_start_8168bb(tp
);
4795 RTL_W8(tp
, MaxTxPacketSize
, TxPacketMax
);
4797 RTL_W8(tp
, Config4
, RTL_R8(tp
, Config4
) & ~(1 << 0));
4800 static void __rtl_hw_start_8168cp(struct rtl8169_private
*tp
)
4802 RTL_W8(tp
, Config1
, RTL_R8(tp
, Config1
) | Speed_down
);
4804 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) & ~Beacon_en
);
4806 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
4807 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
4809 rtl_disable_clock_request(tp
);
4811 tp
->cp_cmd
&= CPCMD_QUIRK_MASK
;
4812 RTL_W16(tp
, CPlusCmd
, tp
->cp_cmd
);
4815 static void rtl_hw_start_8168cp_1(struct rtl8169_private
*tp
)
4817 static const struct ephy_info e_info_8168cp
[] = {
4818 { 0x01, 0, 0x0001 },
4819 { 0x02, 0x0800, 0x1000 },
4820 { 0x03, 0, 0x0042 },
4821 { 0x06, 0x0080, 0x0000 },
4825 rtl_set_def_aspm_entry_latency(tp
);
4827 rtl_ephy_init(tp
, e_info_8168cp
);
4829 __rtl_hw_start_8168cp(tp
);
4832 static void rtl_hw_start_8168cp_2(struct rtl8169_private
*tp
)
4834 rtl_set_def_aspm_entry_latency(tp
);
4836 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) & ~Beacon_en
);
4838 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
4839 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
4841 tp
->cp_cmd
&= CPCMD_QUIRK_MASK
;
4842 RTL_W16(tp
, CPlusCmd
, tp
->cp_cmd
);
4845 static void rtl_hw_start_8168cp_3(struct rtl8169_private
*tp
)
4847 rtl_set_def_aspm_entry_latency(tp
);
4849 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) & ~Beacon_en
);
4852 RTL_W8(tp
, DBG_REG
, 0x20);
4854 RTL_W8(tp
, MaxTxPacketSize
, TxPacketMax
);
4856 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
4857 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
4859 tp
->cp_cmd
&= CPCMD_QUIRK_MASK
;
4860 RTL_W16(tp
, CPlusCmd
, tp
->cp_cmd
);
4863 static void rtl_hw_start_8168c_1(struct rtl8169_private
*tp
)
4865 static const struct ephy_info e_info_8168c_1
[] = {
4866 { 0x02, 0x0800, 0x1000 },
4867 { 0x03, 0, 0x0002 },
4868 { 0x06, 0x0080, 0x0000 }
4871 rtl_set_def_aspm_entry_latency(tp
);
4873 RTL_W8(tp
, DBG_REG
, 0x06 | FIX_NAK_1
| FIX_NAK_2
);
4875 rtl_ephy_init(tp
, e_info_8168c_1
);
4877 __rtl_hw_start_8168cp(tp
);
4880 static void rtl_hw_start_8168c_2(struct rtl8169_private
*tp
)
4882 static const struct ephy_info e_info_8168c_2
[] = {
4883 { 0x01, 0, 0x0001 },
4884 { 0x03, 0x0400, 0x0220 }
4887 rtl_set_def_aspm_entry_latency(tp
);
4889 rtl_ephy_init(tp
, e_info_8168c_2
);
4891 __rtl_hw_start_8168cp(tp
);
4894 static void rtl_hw_start_8168c_3(struct rtl8169_private
*tp
)
4896 rtl_hw_start_8168c_2(tp
);
4899 static void rtl_hw_start_8168c_4(struct rtl8169_private
*tp
)
4901 rtl_set_def_aspm_entry_latency(tp
);
4903 __rtl_hw_start_8168cp(tp
);
4906 static void rtl_hw_start_8168d(struct rtl8169_private
*tp
)
4908 rtl_set_def_aspm_entry_latency(tp
);
4910 rtl_disable_clock_request(tp
);
4912 RTL_W8(tp
, MaxTxPacketSize
, TxPacketMax
);
4914 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
4915 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
4917 tp
->cp_cmd
&= CPCMD_QUIRK_MASK
;
4918 RTL_W16(tp
, CPlusCmd
, tp
->cp_cmd
);
4921 static void rtl_hw_start_8168dp(struct rtl8169_private
*tp
)
4923 rtl_set_def_aspm_entry_latency(tp
);
4925 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
4926 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
4928 RTL_W8(tp
, MaxTxPacketSize
, TxPacketMax
);
4930 rtl_disable_clock_request(tp
);
4933 static void rtl_hw_start_8168d_4(struct rtl8169_private
*tp
)
4935 static const struct ephy_info e_info_8168d_4
[] = {
4936 { 0x0b, 0x0000, 0x0048 },
4937 { 0x19, 0x0020, 0x0050 },
4938 { 0x0c, 0x0100, 0x0020 }
4941 rtl_set_def_aspm_entry_latency(tp
);
4943 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
4945 RTL_W8(tp
, MaxTxPacketSize
, TxPacketMax
);
4947 rtl_ephy_init(tp
, e_info_8168d_4
);
4949 rtl_enable_clock_request(tp
);
4952 static void rtl_hw_start_8168e_1(struct rtl8169_private
*tp
)
4954 static const struct ephy_info e_info_8168e_1
[] = {
4955 { 0x00, 0x0200, 0x0100 },
4956 { 0x00, 0x0000, 0x0004 },
4957 { 0x06, 0x0002, 0x0001 },
4958 { 0x06, 0x0000, 0x0030 },
4959 { 0x07, 0x0000, 0x2000 },
4960 { 0x00, 0x0000, 0x0020 },
4961 { 0x03, 0x5800, 0x2000 },
4962 { 0x03, 0x0000, 0x0001 },
4963 { 0x01, 0x0800, 0x1000 },
4964 { 0x07, 0x0000, 0x4000 },
4965 { 0x1e, 0x0000, 0x2000 },
4966 { 0x19, 0xffff, 0xfe6c },
4967 { 0x0a, 0x0000, 0x0040 }
4970 rtl_set_def_aspm_entry_latency(tp
);
4972 rtl_ephy_init(tp
, e_info_8168e_1
);
4974 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
4975 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
4977 RTL_W8(tp
, MaxTxPacketSize
, TxPacketMax
);
4979 rtl_disable_clock_request(tp
);
4981 /* Reset tx FIFO pointer */
4982 RTL_W32(tp
, MISC
, RTL_R32(tp
, MISC
) | TXPLA_RST
);
4983 RTL_W32(tp
, MISC
, RTL_R32(tp
, MISC
) & ~TXPLA_RST
);
4985 RTL_W8(tp
, Config5
, RTL_R8(tp
, Config5
) & ~Spi_en
);
4988 static void rtl_hw_start_8168e_2(struct rtl8169_private
*tp
)
4990 static const struct ephy_info e_info_8168e_2
[] = {
4991 { 0x09, 0x0000, 0x0080 },
4992 { 0x19, 0x0000, 0x0224 }
4995 rtl_set_def_aspm_entry_latency(tp
);
4997 rtl_ephy_init(tp
, e_info_8168e_2
);
4999 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
5000 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
5002 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000);
5003 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000);
5004 rtl_set_fifo_size(tp
, 0x10, 0x10, 0x02, 0x06);
5005 rtl_eri_write(tp
, 0xcc, ERIAR_MASK_1111
, 0x00000050);
5006 rtl_eri_write(tp
, 0xd0, ERIAR_MASK_1111
, 0x07ff0060);
5007 rtl_eri_set_bits(tp
, 0x1b0, ERIAR_MASK_0001
, BIT(4));
5008 rtl_w0w1_eri(tp
, 0x0d4, ERIAR_MASK_0011
, 0x0c00, 0xff00);
5010 RTL_W8(tp
, MaxTxPacketSize
, EarlySize
);
5012 rtl_disable_clock_request(tp
);
5014 RTL_W8(tp
, MCU
, RTL_R8(tp
, MCU
) & ~NOW_IS_OOB
);
5016 rtl8168_config_eee_mac(tp
);
5018 RTL_W8(tp
, DLLPR
, RTL_R8(tp
, DLLPR
) | PFM_EN
);
5019 RTL_W32(tp
, MISC
, RTL_R32(tp
, MISC
) | PWM_EN
);
5020 RTL_W8(tp
, Config5
, RTL_R8(tp
, Config5
) & ~Spi_en
);
5022 rtl_hw_aspm_clkreq_enable(tp
, true);
5025 static void rtl_hw_start_8168f(struct rtl8169_private
*tp
)
5027 rtl_set_def_aspm_entry_latency(tp
);
5029 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
5031 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000);
5032 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000);
5033 rtl_set_fifo_size(tp
, 0x10, 0x10, 0x02, 0x06);
5034 rtl_reset_packet_filter(tp
);
5035 rtl_eri_set_bits(tp
, 0x1b0, ERIAR_MASK_0001
, BIT(4));
5036 rtl_eri_set_bits(tp
, 0x1d0, ERIAR_MASK_0001
, BIT(4));
5037 rtl_eri_write(tp
, 0xcc, ERIAR_MASK_1111
, 0x00000050);
5038 rtl_eri_write(tp
, 0xd0, ERIAR_MASK_1111
, 0x00000060);
5040 RTL_W8(tp
, MaxTxPacketSize
, EarlySize
);
5042 rtl_disable_clock_request(tp
);
5044 RTL_W8(tp
, MCU
, RTL_R8(tp
, MCU
) & ~NOW_IS_OOB
);
5045 RTL_W8(tp
, DLLPR
, RTL_R8(tp
, DLLPR
) | PFM_EN
);
5046 RTL_W32(tp
, MISC
, RTL_R32(tp
, MISC
) | PWM_EN
);
5047 RTL_W8(tp
, Config5
, RTL_R8(tp
, Config5
) & ~Spi_en
);
5049 rtl8168_config_eee_mac(tp
);
5052 static void rtl_hw_start_8168f_1(struct rtl8169_private
*tp
)
5054 static const struct ephy_info e_info_8168f_1
[] = {
5055 { 0x06, 0x00c0, 0x0020 },
5056 { 0x08, 0x0001, 0x0002 },
5057 { 0x09, 0x0000, 0x0080 },
5058 { 0x19, 0x0000, 0x0224 }
5061 rtl_hw_start_8168f(tp
);
5063 rtl_ephy_init(tp
, e_info_8168f_1
);
5065 rtl_w0w1_eri(tp
, 0x0d4, ERIAR_MASK_0011
, 0x0c00, 0xff00);
5068 static void rtl_hw_start_8411(struct rtl8169_private
*tp
)
5070 static const struct ephy_info e_info_8168f_1
[] = {
5071 { 0x06, 0x00c0, 0x0020 },
5072 { 0x0f, 0xffff, 0x5200 },
5073 { 0x1e, 0x0000, 0x4000 },
5074 { 0x19, 0x0000, 0x0224 }
5077 rtl_hw_start_8168f(tp
);
5078 rtl_pcie_state_l2l3_disable(tp
);
5080 rtl_ephy_init(tp
, e_info_8168f_1
);
5082 rtl_eri_set_bits(tp
, 0x0d4, ERIAR_MASK_0011
, 0x0c00);
5085 static void rtl_hw_start_8168g(struct rtl8169_private
*tp
)
5087 rtl_set_fifo_size(tp
, 0x08, 0x10, 0x02, 0x06);
5088 rtl8168g_set_pause_thresholds(tp
, 0x38, 0x48);
5090 rtl_set_def_aspm_entry_latency(tp
);
5092 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
5094 rtl_reset_packet_filter(tp
);
5095 rtl_eri_write(tp
, 0x2f8, ERIAR_MASK_0011
, 0x1d8f);
5097 RTL_W32(tp
, MISC
, RTL_R32(tp
, MISC
) & ~RXDV_GATED_EN
);
5098 RTL_W8(tp
, MaxTxPacketSize
, EarlySize
);
5100 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000);
5101 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000);
5103 rtl8168_config_eee_mac(tp
);
5105 rtl_w0w1_eri(tp
, 0x2fc, ERIAR_MASK_0001
, 0x01, 0x06);
5106 rtl_eri_clear_bits(tp
, 0x1b0, ERIAR_MASK_0011
, BIT(12));
5108 rtl_pcie_state_l2l3_disable(tp
);
5111 static void rtl_hw_start_8168g_1(struct rtl8169_private
*tp
)
5113 static const struct ephy_info e_info_8168g_1
[] = {
5114 { 0x00, 0x0000, 0x0008 },
5115 { 0x0c, 0x37d0, 0x0820 },
5116 { 0x1e, 0x0000, 0x0001 },
5117 { 0x19, 0x8000, 0x0000 }
5120 rtl_hw_start_8168g(tp
);
5122 /* disable aspm and clock request before access ephy */
5123 rtl_hw_aspm_clkreq_enable(tp
, false);
5124 rtl_ephy_init(tp
, e_info_8168g_1
);
5125 rtl_hw_aspm_clkreq_enable(tp
, true);
5128 static void rtl_hw_start_8168g_2(struct rtl8169_private
*tp
)
5130 static const struct ephy_info e_info_8168g_2
[] = {
5131 { 0x00, 0x0000, 0x0008 },
5132 { 0x0c, 0x3df0, 0x0200 },
5133 { 0x19, 0xffff, 0xfc00 },
5134 { 0x1e, 0xffff, 0x20eb }
5137 rtl_hw_start_8168g(tp
);
5139 /* disable aspm and clock request before access ephy */
5140 RTL_W8(tp
, Config2
, RTL_R8(tp
, Config2
) & ~ClkReqEn
);
5141 RTL_W8(tp
, Config5
, RTL_R8(tp
, Config5
) & ~ASPM_en
);
5142 rtl_ephy_init(tp
, e_info_8168g_2
);
5145 static void rtl_hw_start_8411_2(struct rtl8169_private
*tp
)
5147 static const struct ephy_info e_info_8411_2
[] = {
5148 { 0x00, 0x0000, 0x0008 },
5149 { 0x0c, 0x3df0, 0x0200 },
5150 { 0x0f, 0xffff, 0x5200 },
5151 { 0x19, 0x0020, 0x0000 },
5152 { 0x1e, 0x0000, 0x2000 }
5155 rtl_hw_start_8168g(tp
);
5157 /* disable aspm and clock request before access ephy */
5158 rtl_hw_aspm_clkreq_enable(tp
, false);
5159 rtl_ephy_init(tp
, e_info_8411_2
);
5160 rtl_hw_aspm_clkreq_enable(tp
, true);
5163 static void rtl_hw_start_8168h_1(struct rtl8169_private
*tp
)
5167 static const struct ephy_info e_info_8168h_1
[] = {
5168 { 0x1e, 0x0800, 0x0001 },
5169 { 0x1d, 0x0000, 0x0800 },
5170 { 0x05, 0xffff, 0x2089 },
5171 { 0x06, 0xffff, 0x5881 },
5172 { 0x04, 0xffff, 0x154a },
5173 { 0x01, 0xffff, 0x068b }
5176 /* disable aspm and clock request before access ephy */
5177 rtl_hw_aspm_clkreq_enable(tp
, false);
5178 rtl_ephy_init(tp
, e_info_8168h_1
);
5180 rtl_set_fifo_size(tp
, 0x08, 0x10, 0x02, 0x06);
5181 rtl8168g_set_pause_thresholds(tp
, 0x38, 0x48);
5183 rtl_set_def_aspm_entry_latency(tp
);
5185 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
5187 rtl_reset_packet_filter(tp
);
5189 rtl_eri_set_bits(tp
, 0xdc, ERIAR_MASK_1111
, BIT(4));
5191 rtl_eri_set_bits(tp
, 0xd4, ERIAR_MASK_1111
, 0x1f00);
5193 rtl_eri_write(tp
, 0x5f0, ERIAR_MASK_0011
, 0x4f87);
5195 RTL_W32(tp
, MISC
, RTL_R32(tp
, MISC
) & ~RXDV_GATED_EN
);
5196 RTL_W8(tp
, MaxTxPacketSize
, EarlySize
);
5198 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000);
5199 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000);
5201 rtl8168_config_eee_mac(tp
);
5203 RTL_W8(tp
, DLLPR
, RTL_R8(tp
, DLLPR
) & ~PFM_EN
);
5204 RTL_W8(tp
, MISC_1
, RTL_R8(tp
, MISC_1
) & ~PFM_D3COLD_EN
);
5206 RTL_W8(tp
, DLLPR
, RTL_R8(tp
, DLLPR
) & ~TX_10M_PS_EN
);
5208 rtl_eri_clear_bits(tp
, 0x1b0, ERIAR_MASK_0011
, BIT(12));
5210 rtl_pcie_state_l2l3_disable(tp
);
5212 rtl_writephy(tp
, 0x1f, 0x0c42);
5213 rg_saw_cnt
= (rtl_readphy(tp
, 0x13) & 0x3fff);
5214 rtl_writephy(tp
, 0x1f, 0x0000);
5215 if (rg_saw_cnt
> 0) {
5218 sw_cnt_1ms_ini
= 16000000/rg_saw_cnt
;
5219 sw_cnt_1ms_ini
&= 0x0fff;
5220 data
= r8168_mac_ocp_read(tp
, 0xd412);
5222 data
|= sw_cnt_1ms_ini
;
5223 r8168_mac_ocp_write(tp
, 0xd412, data
);
5226 data
= r8168_mac_ocp_read(tp
, 0xe056);
5229 r8168_mac_ocp_write(tp
, 0xe056, data
);
5231 data
= r8168_mac_ocp_read(tp
, 0xe052);
5234 r8168_mac_ocp_write(tp
, 0xe052, data
);
5236 data
= r8168_mac_ocp_read(tp
, 0xe0d6);
5239 r8168_mac_ocp_write(tp
, 0xe0d6, data
);
5241 data
= r8168_mac_ocp_read(tp
, 0xd420);
5244 r8168_mac_ocp_write(tp
, 0xd420, data
);
5246 r8168_mac_ocp_write(tp
, 0xe63e, 0x0001);
5247 r8168_mac_ocp_write(tp
, 0xe63e, 0x0000);
5248 r8168_mac_ocp_write(tp
, 0xc094, 0x0000);
5249 r8168_mac_ocp_write(tp
, 0xc09e, 0x0000);
5251 rtl_hw_aspm_clkreq_enable(tp
, true);
5254 static void rtl_hw_start_8168ep(struct rtl8169_private
*tp
)
5256 rtl8168ep_stop_cmac(tp
);
5258 rtl_set_fifo_size(tp
, 0x08, 0x10, 0x02, 0x06);
5259 rtl8168g_set_pause_thresholds(tp
, 0x2f, 0x5f);
5261 rtl_set_def_aspm_entry_latency(tp
);
5263 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
5265 rtl_reset_packet_filter(tp
);
5267 rtl_eri_set_bits(tp
, 0xd4, ERIAR_MASK_1111
, 0x1f80);
5269 rtl_eri_write(tp
, 0x5f0, ERIAR_MASK_0011
, 0x4f87);
5271 RTL_W32(tp
, MISC
, RTL_R32(tp
, MISC
) & ~RXDV_GATED_EN
);
5272 RTL_W8(tp
, MaxTxPacketSize
, EarlySize
);
5274 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000);
5275 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000);
5277 rtl8168_config_eee_mac(tp
);
5279 rtl_w0w1_eri(tp
, 0x2fc, ERIAR_MASK_0001
, 0x01, 0x06);
5281 RTL_W8(tp
, DLLPR
, RTL_R8(tp
, DLLPR
) & ~TX_10M_PS_EN
);
5283 rtl_pcie_state_l2l3_disable(tp
);
5286 static void rtl_hw_start_8168ep_1(struct rtl8169_private
*tp
)
5288 static const struct ephy_info e_info_8168ep_1
[] = {
5289 { 0x00, 0xffff, 0x10ab },
5290 { 0x06, 0xffff, 0xf030 },
5291 { 0x08, 0xffff, 0x2006 },
5292 { 0x0d, 0xffff, 0x1666 },
5293 { 0x0c, 0x3ff0, 0x0000 }
5296 /* disable aspm and clock request before access ephy */
5297 rtl_hw_aspm_clkreq_enable(tp
, false);
5298 rtl_ephy_init(tp
, e_info_8168ep_1
);
5300 rtl_hw_start_8168ep(tp
);
5302 rtl_hw_aspm_clkreq_enable(tp
, true);
5305 static void rtl_hw_start_8168ep_2(struct rtl8169_private
*tp
)
5307 static const struct ephy_info e_info_8168ep_2
[] = {
5308 { 0x00, 0xffff, 0x10a3 },
5309 { 0x19, 0xffff, 0xfc00 },
5310 { 0x1e, 0xffff, 0x20ea }
5313 /* disable aspm and clock request before access ephy */
5314 rtl_hw_aspm_clkreq_enable(tp
, false);
5315 rtl_ephy_init(tp
, e_info_8168ep_2
);
5317 rtl_hw_start_8168ep(tp
);
5319 RTL_W8(tp
, DLLPR
, RTL_R8(tp
, DLLPR
) & ~PFM_EN
);
5320 RTL_W8(tp
, MISC_1
, RTL_R8(tp
, MISC_1
) & ~PFM_D3COLD_EN
);
5322 rtl_hw_aspm_clkreq_enable(tp
, true);
5325 static void rtl_hw_start_8168ep_3(struct rtl8169_private
*tp
)
5328 static const struct ephy_info e_info_8168ep_3
[] = {
5329 { 0x00, 0xffff, 0x10a3 },
5330 { 0x19, 0xffff, 0x7c00 },
5331 { 0x1e, 0xffff, 0x20eb },
5332 { 0x0d, 0xffff, 0x1666 }
5335 /* disable aspm and clock request before access ephy */
5336 rtl_hw_aspm_clkreq_enable(tp
, false);
5337 rtl_ephy_init(tp
, e_info_8168ep_3
);
5339 rtl_hw_start_8168ep(tp
);
5341 RTL_W8(tp
, DLLPR
, RTL_R8(tp
, DLLPR
) & ~PFM_EN
);
5342 RTL_W8(tp
, MISC_1
, RTL_R8(tp
, MISC_1
) & ~PFM_D3COLD_EN
);
5344 data
= r8168_mac_ocp_read(tp
, 0xd3e2);
5347 r8168_mac_ocp_write(tp
, 0xd3e2, data
);
5349 data
= r8168_mac_ocp_read(tp
, 0xd3e4);
5351 r8168_mac_ocp_write(tp
, 0xd3e4, data
);
5353 data
= r8168_mac_ocp_read(tp
, 0xe860);
5355 r8168_mac_ocp_write(tp
, 0xe860, data
);
5357 rtl_hw_aspm_clkreq_enable(tp
, true);
5360 static void rtl_hw_start_8102e_1(struct rtl8169_private
*tp
)
5362 static const struct ephy_info e_info_8102e_1
[] = {
5363 { 0x01, 0, 0x6e65 },
5364 { 0x02, 0, 0x091f },
5365 { 0x03, 0, 0xc2f9 },
5366 { 0x06, 0, 0xafb5 },
5367 { 0x07, 0, 0x0e00 },
5368 { 0x19, 0, 0xec80 },
5369 { 0x01, 0, 0x2e65 },
5374 rtl_set_def_aspm_entry_latency(tp
);
5376 RTL_W8(tp
, DBG_REG
, FIX_NAK_1
);
5378 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
5381 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
5382 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) & ~Beacon_en
);
5384 cfg1
= RTL_R8(tp
, Config1
);
5385 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
5386 RTL_W8(tp
, Config1
, cfg1
& ~LEDS0
);
5388 rtl_ephy_init(tp
, e_info_8102e_1
);
5391 static void rtl_hw_start_8102e_2(struct rtl8169_private
*tp
)
5393 rtl_set_def_aspm_entry_latency(tp
);
5395 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
5397 RTL_W8(tp
, Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
5398 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) & ~Beacon_en
);
5401 static void rtl_hw_start_8102e_3(struct rtl8169_private
*tp
)
5403 rtl_hw_start_8102e_2(tp
);
5405 rtl_ephy_write(tp
, 0x03, 0xc2f9);
5408 static void rtl_hw_start_8105e_1(struct rtl8169_private
*tp
)
5410 static const struct ephy_info e_info_8105e_1
[] = {
5411 { 0x07, 0, 0x4000 },
5412 { 0x19, 0, 0x0200 },
5413 { 0x19, 0, 0x0020 },
5414 { 0x1e, 0, 0x2000 },
5415 { 0x03, 0, 0x0001 },
5416 { 0x19, 0, 0x0100 },
5417 { 0x19, 0, 0x0004 },
5421 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5422 RTL_W32(tp
, FuncEvent
, RTL_R32(tp
, FuncEvent
) | 0x002800);
5424 /* Disable Early Tally Counter */
5425 RTL_W32(tp
, FuncEvent
, RTL_R32(tp
, FuncEvent
) & ~0x010000);
5427 RTL_W8(tp
, MCU
, RTL_R8(tp
, MCU
) | EN_NDP
| EN_OOB_RESET
);
5428 RTL_W8(tp
, DLLPR
, RTL_R8(tp
, DLLPR
) | PFM_EN
);
5430 rtl_ephy_init(tp
, e_info_8105e_1
);
5432 rtl_pcie_state_l2l3_disable(tp
);
5435 static void rtl_hw_start_8105e_2(struct rtl8169_private
*tp
)
5437 rtl_hw_start_8105e_1(tp
);
5438 rtl_ephy_write(tp
, 0x1e, rtl_ephy_read(tp
, 0x1e) | 0x8000);
5441 static void rtl_hw_start_8402(struct rtl8169_private
*tp
)
5443 static const struct ephy_info e_info_8402
[] = {
5444 { 0x19, 0xffff, 0xff64 },
5448 rtl_set_def_aspm_entry_latency(tp
);
5450 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5451 RTL_W32(tp
, FuncEvent
, RTL_R32(tp
, FuncEvent
) | 0x002800);
5453 RTL_W8(tp
, MCU
, RTL_R8(tp
, MCU
) & ~NOW_IS_OOB
);
5455 rtl_ephy_init(tp
, e_info_8402
);
5457 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
5459 rtl_set_fifo_size(tp
, 0x00, 0x00, 0x02, 0x06);
5460 rtl_reset_packet_filter(tp
);
5461 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000);
5462 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000);
5463 rtl_w0w1_eri(tp
, 0x0d4, ERIAR_MASK_0011
, 0x0e00, 0xff00);
5465 rtl_pcie_state_l2l3_disable(tp
);
5468 static void rtl_hw_start_8106(struct rtl8169_private
*tp
)
5470 rtl_hw_aspm_clkreq_enable(tp
, false);
5472 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5473 RTL_W32(tp
, FuncEvent
, RTL_R32(tp
, FuncEvent
) | 0x002800);
5475 RTL_W32(tp
, MISC
, (RTL_R32(tp
, MISC
) | DISABLE_LAN_EN
) & ~EARLY_TALLY_EN
);
5476 RTL_W8(tp
, MCU
, RTL_R8(tp
, MCU
) | EN_NDP
| EN_OOB_RESET
);
5477 RTL_W8(tp
, DLLPR
, RTL_R8(tp
, DLLPR
) & ~PFM_EN
);
5479 rtl_pcie_state_l2l3_disable(tp
);
5480 rtl_hw_aspm_clkreq_enable(tp
, true);
5483 static void rtl_hw_config(struct rtl8169_private
*tp
)
5485 static const rtl_generic_fct hw_configs
[] = {
5486 [RTL_GIGA_MAC_VER_07
] = rtl_hw_start_8102e_1
,
5487 [RTL_GIGA_MAC_VER_08
] = rtl_hw_start_8102e_3
,
5488 [RTL_GIGA_MAC_VER_09
] = rtl_hw_start_8102e_2
,
5489 [RTL_GIGA_MAC_VER_10
] = NULL
,
5490 [RTL_GIGA_MAC_VER_11
] = rtl_hw_start_8168bb
,
5491 [RTL_GIGA_MAC_VER_12
] = rtl_hw_start_8168bef
,
5492 [RTL_GIGA_MAC_VER_13
] = NULL
,
5493 [RTL_GIGA_MAC_VER_14
] = NULL
,
5494 [RTL_GIGA_MAC_VER_15
] = NULL
,
5495 [RTL_GIGA_MAC_VER_16
] = NULL
,
5496 [RTL_GIGA_MAC_VER_17
] = rtl_hw_start_8168bef
,
5497 [RTL_GIGA_MAC_VER_18
] = rtl_hw_start_8168cp_1
,
5498 [RTL_GIGA_MAC_VER_19
] = rtl_hw_start_8168c_1
,
5499 [RTL_GIGA_MAC_VER_20
] = rtl_hw_start_8168c_2
,
5500 [RTL_GIGA_MAC_VER_21
] = rtl_hw_start_8168c_3
,
5501 [RTL_GIGA_MAC_VER_22
] = rtl_hw_start_8168c_4
,
5502 [RTL_GIGA_MAC_VER_23
] = rtl_hw_start_8168cp_2
,
5503 [RTL_GIGA_MAC_VER_24
] = rtl_hw_start_8168cp_3
,
5504 [RTL_GIGA_MAC_VER_25
] = rtl_hw_start_8168d
,
5505 [RTL_GIGA_MAC_VER_26
] = rtl_hw_start_8168d
,
5506 [RTL_GIGA_MAC_VER_27
] = rtl_hw_start_8168d
,
5507 [RTL_GIGA_MAC_VER_28
] = rtl_hw_start_8168d_4
,
5508 [RTL_GIGA_MAC_VER_29
] = rtl_hw_start_8105e_1
,
5509 [RTL_GIGA_MAC_VER_30
] = rtl_hw_start_8105e_2
,
5510 [RTL_GIGA_MAC_VER_31
] = rtl_hw_start_8168dp
,
5511 [RTL_GIGA_MAC_VER_32
] = rtl_hw_start_8168e_1
,
5512 [RTL_GIGA_MAC_VER_33
] = rtl_hw_start_8168e_1
,
5513 [RTL_GIGA_MAC_VER_34
] = rtl_hw_start_8168e_2
,
5514 [RTL_GIGA_MAC_VER_35
] = rtl_hw_start_8168f_1
,
5515 [RTL_GIGA_MAC_VER_36
] = rtl_hw_start_8168f_1
,
5516 [RTL_GIGA_MAC_VER_37
] = rtl_hw_start_8402
,
5517 [RTL_GIGA_MAC_VER_38
] = rtl_hw_start_8411
,
5518 [RTL_GIGA_MAC_VER_39
] = rtl_hw_start_8106
,
5519 [RTL_GIGA_MAC_VER_40
] = rtl_hw_start_8168g_1
,
5520 [RTL_GIGA_MAC_VER_41
] = rtl_hw_start_8168g_1
,
5521 [RTL_GIGA_MAC_VER_42
] = rtl_hw_start_8168g_2
,
5522 [RTL_GIGA_MAC_VER_43
] = rtl_hw_start_8168g_2
,
5523 [RTL_GIGA_MAC_VER_44
] = rtl_hw_start_8411_2
,
5524 [RTL_GIGA_MAC_VER_45
] = rtl_hw_start_8168h_1
,
5525 [RTL_GIGA_MAC_VER_46
] = rtl_hw_start_8168h_1
,
5526 [RTL_GIGA_MAC_VER_47
] = rtl_hw_start_8168h_1
,
5527 [RTL_GIGA_MAC_VER_48
] = rtl_hw_start_8168h_1
,
5528 [RTL_GIGA_MAC_VER_49
] = rtl_hw_start_8168ep_1
,
5529 [RTL_GIGA_MAC_VER_50
] = rtl_hw_start_8168ep_2
,
5530 [RTL_GIGA_MAC_VER_51
] = rtl_hw_start_8168ep_3
,
5533 if (hw_configs
[tp
->mac_version
])
5534 hw_configs
[tp
->mac_version
](tp
);
5537 static void rtl_hw_start_8168(struct rtl8169_private
*tp
)
5539 RTL_W8(tp
, MaxTxPacketSize
, TxPacketMax
);
5541 /* Workaround for RxFIFO overflow. */
5542 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
) {
5543 tp
->irq_mask
|= RxFIFOOver
;
5544 tp
->irq_mask
&= ~RxOverflow
;
5550 static void rtl_hw_start_8101(struct rtl8169_private
*tp
)
5552 if (tp
->mac_version
>= RTL_GIGA_MAC_VER_30
)
5553 tp
->irq_mask
&= ~RxFIFOOver
;
5555 if (tp
->mac_version
== RTL_GIGA_MAC_VER_13
||
5556 tp
->mac_version
== RTL_GIGA_MAC_VER_16
)
5557 pcie_capability_set_word(tp
->pci_dev
, PCI_EXP_DEVCTL
,
5558 PCI_EXP_DEVCTL_NOSNOOP_EN
);
5560 RTL_W8(tp
, MaxTxPacketSize
, TxPacketMax
);
5562 tp
->cp_cmd
&= CPCMD_QUIRK_MASK
;
5563 RTL_W16(tp
, CPlusCmd
, tp
->cp_cmd
);
5568 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
5570 struct rtl8169_private
*tp
= netdev_priv(dev
);
5572 if (new_mtu
> ETH_DATA_LEN
)
5573 rtl_hw_jumbo_enable(tp
);
5575 rtl_hw_jumbo_disable(tp
);
5578 netdev_update_features(dev
);
5583 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
5585 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
5586 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
5589 static void rtl8169_free_rx_databuff(struct rtl8169_private
*tp
,
5590 void **data_buff
, struct RxDesc
*desc
)
5592 dma_unmap_single(tp_to_dev(tp
), le64_to_cpu(desc
->addr
),
5593 R8169_RX_BUF_SIZE
, DMA_FROM_DEVICE
);
5597 rtl8169_make_unusable_by_asic(desc
);
5600 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
)
5602 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
5604 /* Force memory writes to complete before releasing descriptor */
5607 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| R8169_RX_BUF_SIZE
);
5610 static struct sk_buff
*rtl8169_alloc_rx_data(struct rtl8169_private
*tp
,
5611 struct RxDesc
*desc
)
5615 struct device
*d
= tp_to_dev(tp
);
5616 int node
= dev_to_node(d
);
5618 data
= kmalloc_node(R8169_RX_BUF_SIZE
, GFP_KERNEL
, node
);
5622 /* Memory should be properly aligned, but better check. */
5623 if (!IS_ALIGNED((unsigned long)data
, 8)) {
5624 netdev_err_once(tp
->dev
, "RX buffer not 8-byte-aligned\n");
5628 mapping
= dma_map_single(d
, data
, R8169_RX_BUF_SIZE
, DMA_FROM_DEVICE
);
5629 if (unlikely(dma_mapping_error(d
, mapping
))) {
5630 if (net_ratelimit())
5631 netif_err(tp
, drv
, tp
->dev
, "Failed to map RX DMA!\n");
5635 desc
->addr
= cpu_to_le64(mapping
);
5636 rtl8169_mark_to_asic(desc
);
5644 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
5648 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
5649 if (tp
->Rx_databuff
[i
]) {
5650 rtl8169_free_rx_databuff(tp
, tp
->Rx_databuff
+ i
,
5651 tp
->RxDescArray
+ i
);
5656 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
5658 desc
->opts1
|= cpu_to_le32(RingEnd
);
5661 static int rtl8169_rx_fill(struct rtl8169_private
*tp
)
5665 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
5668 data
= rtl8169_alloc_rx_data(tp
, tp
->RxDescArray
+ i
);
5670 rtl8169_make_unusable_by_asic(tp
->RxDescArray
+ i
);
5673 tp
->Rx_databuff
[i
] = data
;
5676 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
5680 rtl8169_rx_clear(tp
);
5684 static int rtl8169_init_ring(struct rtl8169_private
*tp
)
5686 rtl8169_init_ring_indexes(tp
);
5688 memset(tp
->tx_skb
, 0, sizeof(tp
->tx_skb
));
5689 memset(tp
->Rx_databuff
, 0, sizeof(tp
->Rx_databuff
));
5691 return rtl8169_rx_fill(tp
);
5694 static void rtl8169_unmap_tx_skb(struct device
*d
, struct ring_info
*tx_skb
,
5695 struct TxDesc
*desc
)
5697 unsigned int len
= tx_skb
->len
;
5699 dma_unmap_single(d
, le64_to_cpu(desc
->addr
), len
, DMA_TO_DEVICE
);
5707 static void rtl8169_tx_clear_range(struct rtl8169_private
*tp
, u32 start
,
5712 for (i
= 0; i
< n
; i
++) {
5713 unsigned int entry
= (start
+ i
) % NUM_TX_DESC
;
5714 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
5715 unsigned int len
= tx_skb
->len
;
5718 struct sk_buff
*skb
= tx_skb
->skb
;
5720 rtl8169_unmap_tx_skb(tp_to_dev(tp
), tx_skb
,
5721 tp
->TxDescArray
+ entry
);
5723 dev_consume_skb_any(skb
);
5730 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
5732 rtl8169_tx_clear_range(tp
, tp
->dirty_tx
, NUM_TX_DESC
);
5733 tp
->cur_tx
= tp
->dirty_tx
= 0;
5734 netdev_reset_queue(tp
->dev
);
5737 static void rtl_reset_work(struct rtl8169_private
*tp
)
5739 struct net_device
*dev
= tp
->dev
;
5742 napi_disable(&tp
->napi
);
5743 netif_stop_queue(dev
);
5746 rtl8169_hw_reset(tp
);
5748 for (i
= 0; i
< NUM_RX_DESC
; i
++)
5749 rtl8169_mark_to_asic(tp
->RxDescArray
+ i
);
5751 rtl8169_tx_clear(tp
);
5752 rtl8169_init_ring_indexes(tp
);
5754 napi_enable(&tp
->napi
);
5756 netif_wake_queue(dev
);
5759 static void rtl8169_tx_timeout(struct net_device
*dev
)
5761 struct rtl8169_private
*tp
= netdev_priv(dev
);
5763 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
5766 static __le32
rtl8169_get_txd_opts1(u32 opts0
, u32 len
, unsigned int entry
)
5768 u32 status
= opts0
| len
;
5770 if (entry
== NUM_TX_DESC
- 1)
5773 return cpu_to_le32(status
);
5776 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
5779 struct skb_shared_info
*info
= skb_shinfo(skb
);
5780 unsigned int cur_frag
, entry
;
5781 struct TxDesc
*uninitialized_var(txd
);
5782 struct device
*d
= tp_to_dev(tp
);
5785 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
5786 const skb_frag_t
*frag
= info
->frags
+ cur_frag
;
5791 entry
= (entry
+ 1) % NUM_TX_DESC
;
5793 txd
= tp
->TxDescArray
+ entry
;
5794 len
= skb_frag_size(frag
);
5795 addr
= skb_frag_address(frag
);
5796 mapping
= dma_map_single(d
, addr
, len
, DMA_TO_DEVICE
);
5797 if (unlikely(dma_mapping_error(d
, mapping
))) {
5798 if (net_ratelimit())
5799 netif_err(tp
, drv
, tp
->dev
,
5800 "Failed to map TX fragments DMA!\n");
5804 txd
->opts1
= rtl8169_get_txd_opts1(opts
[0], len
, entry
);
5805 txd
->opts2
= cpu_to_le32(opts
[1]);
5806 txd
->addr
= cpu_to_le64(mapping
);
5808 tp
->tx_skb
[entry
].len
= len
;
5812 tp
->tx_skb
[entry
].skb
= skb
;
5813 txd
->opts1
|= cpu_to_le32(LastFrag
);
5819 rtl8169_tx_clear_range(tp
, tp
->cur_tx
+ 1, cur_frag
);
5823 static bool rtl_test_hw_pad_bug(struct rtl8169_private
*tp
, struct sk_buff
*skb
)
5825 return skb
->len
< ETH_ZLEN
&& tp
->mac_version
== RTL_GIGA_MAC_VER_34
;
5828 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
5829 struct net_device
*dev
);
5830 /* r8169_csum_workaround()
5831 * The hw limites the value the transport offset. When the offset is out of the
5832 * range, calculate the checksum by sw.
5834 static void r8169_csum_workaround(struct rtl8169_private
*tp
,
5835 struct sk_buff
*skb
)
5837 if (skb_shinfo(skb
)->gso_size
) {
5838 netdev_features_t features
= tp
->dev
->features
;
5839 struct sk_buff
*segs
, *nskb
;
5841 features
&= ~(NETIF_F_SG
| NETIF_F_IPV6_CSUM
| NETIF_F_TSO6
);
5842 segs
= skb_gso_segment(skb
, features
);
5843 if (IS_ERR(segs
) || !segs
)
5850 rtl8169_start_xmit(nskb
, tp
->dev
);
5853 dev_consume_skb_any(skb
);
5854 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5855 if (skb_checksum_help(skb
) < 0)
5858 rtl8169_start_xmit(skb
, tp
->dev
);
5860 struct net_device_stats
*stats
;
5863 stats
= &tp
->dev
->stats
;
5864 stats
->tx_dropped
++;
5865 dev_kfree_skb_any(skb
);
5869 /* msdn_giant_send_check()
5870 * According to the document of microsoft, the TCP Pseudo Header excludes the
5871 * packet length for IPv6 TCP large packets.
5873 static int msdn_giant_send_check(struct sk_buff
*skb
)
5875 const struct ipv6hdr
*ipv6h
;
5879 ret
= skb_cow_head(skb
, 0);
5883 ipv6h
= ipv6_hdr(skb
);
5887 th
->check
= ~tcp_v6_check(0, &ipv6h
->saddr
, &ipv6h
->daddr
, 0);
5892 static bool rtl8169_tso_csum_v1(struct rtl8169_private
*tp
,
5893 struct sk_buff
*skb
, u32
*opts
)
5895 u32 mss
= skb_shinfo(skb
)->gso_size
;
5899 opts
[0] |= min(mss
, TD_MSS_MAX
) << TD0_MSS_SHIFT
;
5900 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5901 const struct iphdr
*ip
= ip_hdr(skb
);
5903 if (ip
->protocol
== IPPROTO_TCP
)
5904 opts
[0] |= TD0_IP_CS
| TD0_TCP_CS
;
5905 else if (ip
->protocol
== IPPROTO_UDP
)
5906 opts
[0] |= TD0_IP_CS
| TD0_UDP_CS
;
5914 static bool rtl8169_tso_csum_v2(struct rtl8169_private
*tp
,
5915 struct sk_buff
*skb
, u32
*opts
)
5917 u32 transport_offset
= (u32
)skb_transport_offset(skb
);
5918 u32 mss
= skb_shinfo(skb
)->gso_size
;
5921 if (transport_offset
> GTTCPHO_MAX
) {
5922 netif_warn(tp
, tx_err
, tp
->dev
,
5923 "Invalid transport offset 0x%x for TSO\n",
5928 switch (vlan_get_protocol(skb
)) {
5929 case htons(ETH_P_IP
):
5930 opts
[0] |= TD1_GTSENV4
;
5933 case htons(ETH_P_IPV6
):
5934 if (msdn_giant_send_check(skb
))
5937 opts
[0] |= TD1_GTSENV6
;
5945 opts
[0] |= transport_offset
<< GTTCPHO_SHIFT
;
5946 opts
[1] |= min(mss
, TD_MSS_MAX
) << TD1_MSS_SHIFT
;
5947 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5950 if (unlikely(rtl_test_hw_pad_bug(tp
, skb
)))
5951 return !(skb_checksum_help(skb
) || eth_skb_pad(skb
));
5953 if (transport_offset
> TCPHO_MAX
) {
5954 netif_warn(tp
, tx_err
, tp
->dev
,
5955 "Invalid transport offset 0x%x\n",
5960 switch (vlan_get_protocol(skb
)) {
5961 case htons(ETH_P_IP
):
5962 opts
[1] |= TD1_IPv4_CS
;
5963 ip_protocol
= ip_hdr(skb
)->protocol
;
5966 case htons(ETH_P_IPV6
):
5967 opts
[1] |= TD1_IPv6_CS
;
5968 ip_protocol
= ipv6_hdr(skb
)->nexthdr
;
5972 ip_protocol
= IPPROTO_RAW
;
5976 if (ip_protocol
== IPPROTO_TCP
)
5977 opts
[1] |= TD1_TCP_CS
;
5978 else if (ip_protocol
== IPPROTO_UDP
)
5979 opts
[1] |= TD1_UDP_CS
;
5983 opts
[1] |= transport_offset
<< TCPHO_SHIFT
;
5985 if (unlikely(rtl_test_hw_pad_bug(tp
, skb
)))
5986 return !eth_skb_pad(skb
);
5992 static bool rtl_tx_slots_avail(struct rtl8169_private
*tp
,
5993 unsigned int nr_frags
)
5995 unsigned int slots_avail
= tp
->dirty_tx
+ NUM_TX_DESC
- tp
->cur_tx
;
5997 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
5998 return slots_avail
> nr_frags
;
6001 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
6002 struct net_device
*dev
)
6004 struct rtl8169_private
*tp
= netdev_priv(dev
);
6005 unsigned int entry
= tp
->cur_tx
% NUM_TX_DESC
;
6006 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
6007 struct device
*d
= tp_to_dev(tp
);
6012 if (unlikely(!rtl_tx_slots_avail(tp
, skb_shinfo(skb
)->nr_frags
))) {
6013 netif_err(tp
, drv
, dev
, "BUG! Tx Ring full when queue awake!\n");
6017 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
6020 opts
[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb
));
6023 if (!tp
->tso_csum(tp
, skb
, opts
)) {
6024 r8169_csum_workaround(tp
, skb
);
6025 return NETDEV_TX_OK
;
6028 len
= skb_headlen(skb
);
6029 mapping
= dma_map_single(d
, skb
->data
, len
, DMA_TO_DEVICE
);
6030 if (unlikely(dma_mapping_error(d
, mapping
))) {
6031 if (net_ratelimit())
6032 netif_err(tp
, drv
, dev
, "Failed to map TX DMA!\n");
6036 tp
->tx_skb
[entry
].len
= len
;
6037 txd
->addr
= cpu_to_le64(mapping
);
6039 frags
= rtl8169_xmit_frags(tp
, skb
, opts
);
6043 opts
[0] |= FirstFrag
;
6045 opts
[0] |= FirstFrag
| LastFrag
;
6046 tp
->tx_skb
[entry
].skb
= skb
;
6049 txd
->opts2
= cpu_to_le32(opts
[1]);
6051 netdev_sent_queue(dev
, skb
->len
);
6053 skb_tx_timestamp(skb
);
6055 /* Force memory writes to complete before releasing descriptor */
6058 txd
->opts1
= rtl8169_get_txd_opts1(opts
[0], len
, entry
);
6060 /* Force all memory writes to complete before notifying device */
6063 tp
->cur_tx
+= frags
+ 1;
6065 RTL_W8(tp
, TxPoll
, NPQ
);
6067 if (!rtl_tx_slots_avail(tp
, MAX_SKB_FRAGS
)) {
6068 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6069 * not miss a ring update when it notices a stopped queue.
6072 netif_stop_queue(dev
);
6073 /* Sync with rtl_tx:
6074 * - publish queue status and cur_tx ring index (write barrier)
6075 * - refresh dirty_tx ring index (read barrier).
6076 * May the current thread have a pessimistic view of the ring
6077 * status and forget to wake up queue, a racing rtl_tx thread
6081 if (rtl_tx_slots_avail(tp
, MAX_SKB_FRAGS
))
6082 netif_start_queue(dev
);
6085 return NETDEV_TX_OK
;
6088 rtl8169_unmap_tx_skb(d
, tp
->tx_skb
+ entry
, txd
);
6090 dev_kfree_skb_any(skb
);
6091 dev
->stats
.tx_dropped
++;
6092 return NETDEV_TX_OK
;
6095 netif_stop_queue(dev
);
6096 dev
->stats
.tx_dropped
++;
6097 return NETDEV_TX_BUSY
;
6100 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
6102 struct rtl8169_private
*tp
= netdev_priv(dev
);
6103 struct pci_dev
*pdev
= tp
->pci_dev
;
6104 u16 pci_status
, pci_cmd
;
6106 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
6107 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
6109 netif_err(tp
, intr
, dev
, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6110 pci_cmd
, pci_status
);
6113 * The recovery sequence below admits a very elaborated explanation:
6114 * - it seems to work;
6115 * - I did not see what else could be done;
6116 * - it makes iop3xx happy.
6118 * Feel free to adjust to your needs.
6120 if (pdev
->broken_parity_status
)
6121 pci_cmd
&= ~PCI_COMMAND_PARITY
;
6123 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
6125 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
6127 pci_write_config_word(pdev
, PCI_STATUS
,
6128 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
6129 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
6130 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
6132 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
6135 static void rtl_tx(struct net_device
*dev
, struct rtl8169_private
*tp
,
6138 unsigned int dirty_tx
, tx_left
, bytes_compl
= 0, pkts_compl
= 0;
6140 dirty_tx
= tp
->dirty_tx
;
6142 tx_left
= tp
->cur_tx
- dirty_tx
;
6144 while (tx_left
> 0) {
6145 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
6146 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
6149 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
6150 if (status
& DescOwn
)
6153 /* This barrier is needed to keep us from reading
6154 * any other fields out of the Tx descriptor until
6155 * we know the status of DescOwn
6159 rtl8169_unmap_tx_skb(tp_to_dev(tp
), tx_skb
,
6160 tp
->TxDescArray
+ entry
);
6161 if (status
& LastFrag
) {
6163 bytes_compl
+= tx_skb
->skb
->len
;
6164 napi_consume_skb(tx_skb
->skb
, budget
);
6171 if (tp
->dirty_tx
!= dirty_tx
) {
6172 netdev_completed_queue(dev
, pkts_compl
, bytes_compl
);
6174 u64_stats_update_begin(&tp
->tx_stats
.syncp
);
6175 tp
->tx_stats
.packets
+= pkts_compl
;
6176 tp
->tx_stats
.bytes
+= bytes_compl
;
6177 u64_stats_update_end(&tp
->tx_stats
.syncp
);
6179 tp
->dirty_tx
= dirty_tx
;
6180 /* Sync with rtl8169_start_xmit:
6181 * - publish dirty_tx ring index (write barrier)
6182 * - refresh cur_tx ring index and queue status (read barrier)
6183 * May the current thread miss the stopped queue condition,
6184 * a racing xmit thread can only have a right view of the
6188 if (netif_queue_stopped(dev
) &&
6189 rtl_tx_slots_avail(tp
, MAX_SKB_FRAGS
)) {
6190 netif_wake_queue(dev
);
6193 * 8168 hack: TxPoll requests are lost when the Tx packets are
6194 * too close. Let's kick an extra TxPoll request when a burst
6195 * of start_xmit activity is detected (if it is not detected,
6196 * it is slow enough). -- FR
6198 if (tp
->cur_tx
!= dirty_tx
)
6199 RTL_W8(tp
, TxPoll
, NPQ
);
6203 static inline int rtl8169_fragmented_frame(u32 status
)
6205 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
6208 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, u32 opts1
)
6210 u32 status
= opts1
& RxProtoMask
;
6212 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
6213 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)))
6214 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
6216 skb_checksum_none_assert(skb
);
6219 static struct sk_buff
*rtl8169_try_rx_copy(void *data
,
6220 struct rtl8169_private
*tp
,
6224 struct sk_buff
*skb
;
6225 struct device
*d
= tp_to_dev(tp
);
6227 dma_sync_single_for_cpu(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
6229 skb
= napi_alloc_skb(&tp
->napi
, pkt_size
);
6231 skb_copy_to_linear_data(skb
, data
, pkt_size
);
6232 dma_sync_single_for_device(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
6237 static int rtl_rx(struct net_device
*dev
, struct rtl8169_private
*tp
, u32 budget
)
6239 unsigned int cur_rx
, rx_left
;
6242 cur_rx
= tp
->cur_rx
;
6244 for (rx_left
= min(budget
, NUM_RX_DESC
); rx_left
> 0; rx_left
--, cur_rx
++) {
6245 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
6246 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
6249 status
= le32_to_cpu(desc
->opts1
);
6250 if (status
& DescOwn
)
6253 /* This barrier is needed to keep us from reading
6254 * any other fields out of the Rx descriptor until
6255 * we know the status of DescOwn
6259 if (unlikely(status
& RxRES
)) {
6260 netif_info(tp
, rx_err
, dev
, "Rx ERROR. status = %08x\n",
6262 dev
->stats
.rx_errors
++;
6263 if (status
& (RxRWT
| RxRUNT
))
6264 dev
->stats
.rx_length_errors
++;
6266 dev
->stats
.rx_crc_errors
++;
6267 /* RxFOVF is a reserved bit on later chip versions */
6268 if (tp
->mac_version
== RTL_GIGA_MAC_VER_01
&&
6270 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
6271 dev
->stats
.rx_fifo_errors
++;
6272 } else if (status
& (RxRUNT
| RxCRC
) &&
6273 !(status
& RxRWT
) &&
6274 dev
->features
& NETIF_F_RXALL
) {
6278 struct sk_buff
*skb
;
6283 addr
= le64_to_cpu(desc
->addr
);
6284 if (likely(!(dev
->features
& NETIF_F_RXFCS
)))
6285 pkt_size
= (status
& 0x00003fff) - 4;
6287 pkt_size
= status
& 0x00003fff;
6290 * The driver does not support incoming fragmented
6291 * frames. They are seen as a symptom of over-mtu
6294 if (unlikely(rtl8169_fragmented_frame(status
))) {
6295 dev
->stats
.rx_dropped
++;
6296 dev
->stats
.rx_length_errors
++;
6297 goto release_descriptor
;
6300 skb
= rtl8169_try_rx_copy(tp
->Rx_databuff
[entry
],
6301 tp
, pkt_size
, addr
);
6303 dev
->stats
.rx_dropped
++;
6304 goto release_descriptor
;
6307 rtl8169_rx_csum(skb
, status
);
6308 skb_put(skb
, pkt_size
);
6309 skb
->protocol
= eth_type_trans(skb
, dev
);
6311 rtl8169_rx_vlan_tag(desc
, skb
);
6313 if (skb
->pkt_type
== PACKET_MULTICAST
)
6314 dev
->stats
.multicast
++;
6316 napi_gro_receive(&tp
->napi
, skb
);
6318 u64_stats_update_begin(&tp
->rx_stats
.syncp
);
6319 tp
->rx_stats
.packets
++;
6320 tp
->rx_stats
.bytes
+= pkt_size
;
6321 u64_stats_update_end(&tp
->rx_stats
.syncp
);
6325 rtl8169_mark_to_asic(desc
);
6328 count
= cur_rx
- tp
->cur_rx
;
6329 tp
->cur_rx
= cur_rx
;
6334 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
6336 struct rtl8169_private
*tp
= dev_instance
;
6337 u16 status
= RTL_R16(tp
, IntrStatus
);
6339 if (!tp
->irq_enabled
|| status
== 0xffff || !(status
& tp
->irq_mask
))
6342 if (unlikely(status
& SYSErr
)) {
6343 rtl8169_pcierr_interrupt(tp
->dev
);
6347 if (status
& LinkChg
)
6348 phy_mac_interrupt(tp
->phydev
);
6350 if (unlikely(status
& RxFIFOOver
&&
6351 tp
->mac_version
== RTL_GIGA_MAC_VER_11
)) {
6352 netif_stop_queue(tp
->dev
);
6353 /* XXX - Hack alert. See rtl_task(). */
6354 set_bit(RTL_FLAG_TASK_RESET_PENDING
, tp
->wk
.flags
);
6357 rtl_irq_disable(tp
);
6358 napi_schedule_irqoff(&tp
->napi
);
6360 rtl_ack_events(tp
, status
);
6365 static void rtl_task(struct work_struct
*work
)
6367 static const struct {
6369 void (*action
)(struct rtl8169_private
*);
6371 { RTL_FLAG_TASK_RESET_PENDING
, rtl_reset_work
},
6373 struct rtl8169_private
*tp
=
6374 container_of(work
, struct rtl8169_private
, wk
.work
);
6375 struct net_device
*dev
= tp
->dev
;
6380 if (!netif_running(dev
) ||
6381 !test_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
))
6384 for (i
= 0; i
< ARRAY_SIZE(rtl_work
); i
++) {
6387 pending
= test_and_clear_bit(rtl_work
[i
].bitnr
, tp
->wk
.flags
);
6389 rtl_work
[i
].action(tp
);
6393 rtl_unlock_work(tp
);
6396 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
6398 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
6399 struct net_device
*dev
= tp
->dev
;
6402 work_done
= rtl_rx(dev
, tp
, (u32
) budget
);
6404 rtl_tx(dev
, tp
, budget
);
6406 if (work_done
< budget
) {
6407 napi_complete_done(napi
, work_done
);
6414 static void rtl8169_rx_missed(struct net_device
*dev
)
6416 struct rtl8169_private
*tp
= netdev_priv(dev
);
6418 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
6421 dev
->stats
.rx_missed_errors
+= RTL_R32(tp
, RxMissed
) & 0xffffff;
6422 RTL_W32(tp
, RxMissed
, 0);
6425 static void r8169_phylink_handler(struct net_device
*ndev
)
6427 struct rtl8169_private
*tp
= netdev_priv(ndev
);
6429 if (netif_carrier_ok(ndev
)) {
6430 rtl_link_chg_patch(tp
);
6431 pm_request_resume(&tp
->pci_dev
->dev
);
6433 pm_runtime_idle(&tp
->pci_dev
->dev
);
6436 if (net_ratelimit())
6437 phy_print_status(tp
->phydev
);
6440 static int r8169_phy_connect(struct rtl8169_private
*tp
)
6442 struct phy_device
*phydev
= tp
->phydev
;
6443 phy_interface_t phy_mode
;
6446 phy_mode
= tp
->supports_gmii
? PHY_INTERFACE_MODE_GMII
:
6447 PHY_INTERFACE_MODE_MII
;
6449 ret
= phy_connect_direct(tp
->dev
, phydev
, r8169_phylink_handler
,
6454 if (!tp
->supports_gmii
)
6455 phy_set_max_speed(phydev
, SPEED_100
);
6457 phy_support_asym_pause(phydev
);
6459 phy_attached_info(phydev
);
6464 static void rtl8169_down(struct net_device
*dev
)
6466 struct rtl8169_private
*tp
= netdev_priv(dev
);
6468 phy_stop(tp
->phydev
);
6470 napi_disable(&tp
->napi
);
6471 netif_stop_queue(dev
);
6473 rtl8169_hw_reset(tp
);
6475 * At this point device interrupts can not be enabled in any function,
6476 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6477 * and napi is disabled (rtl8169_poll).
6479 rtl8169_rx_missed(dev
);
6481 /* Give a racing hard_start_xmit a few cycles to complete. */
6484 rtl8169_tx_clear(tp
);
6486 rtl8169_rx_clear(tp
);
6488 rtl_pll_power_down(tp
);
6491 static int rtl8169_close(struct net_device
*dev
)
6493 struct rtl8169_private
*tp
= netdev_priv(dev
);
6494 struct pci_dev
*pdev
= tp
->pci_dev
;
6496 pm_runtime_get_sync(&pdev
->dev
);
6498 /* Update counters before going down */
6499 rtl8169_update_counters(tp
);
6502 /* Clear all task flags */
6503 bitmap_zero(tp
->wk
.flags
, RTL_FLAG_MAX
);
6506 rtl_unlock_work(tp
);
6508 cancel_work_sync(&tp
->wk
.work
);
6510 phy_disconnect(tp
->phydev
);
6512 pci_free_irq(pdev
, 0, tp
);
6514 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
6516 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
6518 tp
->TxDescArray
= NULL
;
6519 tp
->RxDescArray
= NULL
;
6521 pm_runtime_put_sync(&pdev
->dev
);
6526 #ifdef CONFIG_NET_POLL_CONTROLLER
6527 static void rtl8169_netpoll(struct net_device
*dev
)
6529 struct rtl8169_private
*tp
= netdev_priv(dev
);
6531 rtl8169_interrupt(pci_irq_vector(tp
->pci_dev
, 0), tp
);
6535 static int rtl_open(struct net_device
*dev
)
6537 struct rtl8169_private
*tp
= netdev_priv(dev
);
6538 struct pci_dev
*pdev
= tp
->pci_dev
;
6539 int retval
= -ENOMEM
;
6541 pm_runtime_get_sync(&pdev
->dev
);
6544 * Rx and Tx descriptors needs 256 bytes alignment.
6545 * dma_alloc_coherent provides more.
6547 tp
->TxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
,
6548 &tp
->TxPhyAddr
, GFP_KERNEL
);
6549 if (!tp
->TxDescArray
)
6550 goto err_pm_runtime_put
;
6552 tp
->RxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
,
6553 &tp
->RxPhyAddr
, GFP_KERNEL
);
6554 if (!tp
->RxDescArray
)
6557 retval
= rtl8169_init_ring(tp
);
6561 rtl_request_firmware(tp
);
6563 retval
= pci_request_irq(pdev
, 0, rtl8169_interrupt
, NULL
, tp
,
6566 goto err_release_fw_2
;
6568 retval
= r8169_phy_connect(tp
);
6574 set_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
6576 napi_enable(&tp
->napi
);
6578 rtl8169_init_phy(dev
, tp
);
6580 rtl_pll_power_up(tp
);
6584 if (!rtl8169_init_counter_offsets(tp
))
6585 netif_warn(tp
, hw
, dev
, "counter reset/update failed\n");
6587 phy_start(tp
->phydev
);
6588 netif_start_queue(dev
);
6590 rtl_unlock_work(tp
);
6592 pm_runtime_put_sync(&pdev
->dev
);
6597 pci_free_irq(pdev
, 0, tp
);
6599 rtl_release_firmware(tp
);
6600 rtl8169_rx_clear(tp
);
6602 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
6604 tp
->RxDescArray
= NULL
;
6606 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
6608 tp
->TxDescArray
= NULL
;
6610 pm_runtime_put_noidle(&pdev
->dev
);
6615 rtl8169_get_stats64(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
6617 struct rtl8169_private
*tp
= netdev_priv(dev
);
6618 struct pci_dev
*pdev
= tp
->pci_dev
;
6619 struct rtl8169_counters
*counters
= tp
->counters
;
6622 pm_runtime_get_noresume(&pdev
->dev
);
6624 if (netif_running(dev
) && pm_runtime_active(&pdev
->dev
))
6625 rtl8169_rx_missed(dev
);
6628 start
= u64_stats_fetch_begin_irq(&tp
->rx_stats
.syncp
);
6629 stats
->rx_packets
= tp
->rx_stats
.packets
;
6630 stats
->rx_bytes
= tp
->rx_stats
.bytes
;
6631 } while (u64_stats_fetch_retry_irq(&tp
->rx_stats
.syncp
, start
));
6634 start
= u64_stats_fetch_begin_irq(&tp
->tx_stats
.syncp
);
6635 stats
->tx_packets
= tp
->tx_stats
.packets
;
6636 stats
->tx_bytes
= tp
->tx_stats
.bytes
;
6637 } while (u64_stats_fetch_retry_irq(&tp
->tx_stats
.syncp
, start
));
6639 stats
->rx_dropped
= dev
->stats
.rx_dropped
;
6640 stats
->tx_dropped
= dev
->stats
.tx_dropped
;
6641 stats
->rx_length_errors
= dev
->stats
.rx_length_errors
;
6642 stats
->rx_errors
= dev
->stats
.rx_errors
;
6643 stats
->rx_crc_errors
= dev
->stats
.rx_crc_errors
;
6644 stats
->rx_fifo_errors
= dev
->stats
.rx_fifo_errors
;
6645 stats
->rx_missed_errors
= dev
->stats
.rx_missed_errors
;
6646 stats
->multicast
= dev
->stats
.multicast
;
6649 * Fetch additonal counter values missing in stats collected by driver
6650 * from tally counters.
6652 if (pm_runtime_active(&pdev
->dev
))
6653 rtl8169_update_counters(tp
);
6656 * Subtract values fetched during initalization.
6657 * See rtl8169_init_counter_offsets for a description why we do that.
6659 stats
->tx_errors
= le64_to_cpu(counters
->tx_errors
) -
6660 le64_to_cpu(tp
->tc_offset
.tx_errors
);
6661 stats
->collisions
= le32_to_cpu(counters
->tx_multi_collision
) -
6662 le32_to_cpu(tp
->tc_offset
.tx_multi_collision
);
6663 stats
->tx_aborted_errors
= le16_to_cpu(counters
->tx_aborted
) -
6664 le16_to_cpu(tp
->tc_offset
.tx_aborted
);
6666 pm_runtime_put_noidle(&pdev
->dev
);
6669 static void rtl8169_net_suspend(struct net_device
*dev
)
6671 struct rtl8169_private
*tp
= netdev_priv(dev
);
6673 if (!netif_running(dev
))
6676 phy_stop(tp
->phydev
);
6677 netif_device_detach(dev
);
6680 napi_disable(&tp
->napi
);
6681 /* Clear all task flags */
6682 bitmap_zero(tp
->wk
.flags
, RTL_FLAG_MAX
);
6684 rtl_unlock_work(tp
);
6686 rtl_pll_power_down(tp
);
6691 static int rtl8169_suspend(struct device
*device
)
6693 struct net_device
*dev
= dev_get_drvdata(device
);
6694 struct rtl8169_private
*tp
= netdev_priv(dev
);
6696 rtl8169_net_suspend(dev
);
6697 clk_disable_unprepare(tp
->clk
);
6702 static void __rtl8169_resume(struct net_device
*dev
)
6704 struct rtl8169_private
*tp
= netdev_priv(dev
);
6706 netif_device_attach(dev
);
6708 rtl_pll_power_up(tp
);
6709 rtl8169_init_phy(dev
, tp
);
6711 phy_start(tp
->phydev
);
6714 napi_enable(&tp
->napi
);
6715 set_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
6717 rtl_unlock_work(tp
);
6720 static int rtl8169_resume(struct device
*device
)
6722 struct net_device
*dev
= dev_get_drvdata(device
);
6723 struct rtl8169_private
*tp
= netdev_priv(dev
);
6725 clk_prepare_enable(tp
->clk
);
6727 if (netif_running(dev
))
6728 __rtl8169_resume(dev
);
6733 static int rtl8169_runtime_suspend(struct device
*device
)
6735 struct net_device
*dev
= dev_get_drvdata(device
);
6736 struct rtl8169_private
*tp
= netdev_priv(dev
);
6738 if (!tp
->TxDescArray
)
6742 __rtl8169_set_wol(tp
, WAKE_ANY
);
6743 rtl_unlock_work(tp
);
6745 rtl8169_net_suspend(dev
);
6747 /* Update counters before going runtime suspend */
6748 rtl8169_rx_missed(dev
);
6749 rtl8169_update_counters(tp
);
6754 static int rtl8169_runtime_resume(struct device
*device
)
6756 struct net_device
*dev
= dev_get_drvdata(device
);
6757 struct rtl8169_private
*tp
= netdev_priv(dev
);
6758 rtl_rar_set(tp
, dev
->dev_addr
);
6760 if (!tp
->TxDescArray
)
6764 __rtl8169_set_wol(tp
, tp
->saved_wolopts
);
6765 rtl_unlock_work(tp
);
6767 __rtl8169_resume(dev
);
6772 static int rtl8169_runtime_idle(struct device
*device
)
6774 struct net_device
*dev
= dev_get_drvdata(device
);
6776 if (!netif_running(dev
) || !netif_carrier_ok(dev
))
6777 pm_schedule_suspend(device
, 10000);
6782 static const struct dev_pm_ops rtl8169_pm_ops
= {
6783 .suspend
= rtl8169_suspend
,
6784 .resume
= rtl8169_resume
,
6785 .freeze
= rtl8169_suspend
,
6786 .thaw
= rtl8169_resume
,
6787 .poweroff
= rtl8169_suspend
,
6788 .restore
= rtl8169_resume
,
6789 .runtime_suspend
= rtl8169_runtime_suspend
,
6790 .runtime_resume
= rtl8169_runtime_resume
,
6791 .runtime_idle
= rtl8169_runtime_idle
,
6794 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
6796 #else /* !CONFIG_PM */
6798 #define RTL8169_PM_OPS NULL
6800 #endif /* !CONFIG_PM */
6802 static void rtl_wol_shutdown_quirk(struct rtl8169_private
*tp
)
6804 /* WoL fails with 8168b when the receiver is disabled. */
6805 switch (tp
->mac_version
) {
6806 case RTL_GIGA_MAC_VER_11
:
6807 case RTL_GIGA_MAC_VER_12
:
6808 case RTL_GIGA_MAC_VER_17
:
6809 pci_clear_master(tp
->pci_dev
);
6811 RTL_W8(tp
, ChipCmd
, CmdRxEnb
);
6813 RTL_R8(tp
, ChipCmd
);
6820 static void rtl_shutdown(struct pci_dev
*pdev
)
6822 struct net_device
*dev
= pci_get_drvdata(pdev
);
6823 struct rtl8169_private
*tp
= netdev_priv(dev
);
6825 rtl8169_net_suspend(dev
);
6827 /* Restore original MAC address */
6828 rtl_rar_set(tp
, dev
->perm_addr
);
6830 rtl8169_hw_reset(tp
);
6832 if (system_state
== SYSTEM_POWER_OFF
) {
6833 if (tp
->saved_wolopts
) {
6834 rtl_wol_suspend_quirk(tp
);
6835 rtl_wol_shutdown_quirk(tp
);
6838 pci_wake_from_d3(pdev
, true);
6839 pci_set_power_state(pdev
, PCI_D3hot
);
6843 static void rtl_remove_one(struct pci_dev
*pdev
)
6845 struct net_device
*dev
= pci_get_drvdata(pdev
);
6846 struct rtl8169_private
*tp
= netdev_priv(dev
);
6848 if (r8168_check_dash(tp
))
6849 rtl8168_driver_stop(tp
);
6851 netif_napi_del(&tp
->napi
);
6853 unregister_netdev(dev
);
6854 mdiobus_unregister(tp
->phydev
->mdio
.bus
);
6856 rtl_release_firmware(tp
);
6858 if (pci_dev_run_wake(pdev
))
6859 pm_runtime_get_noresume(&pdev
->dev
);
6861 /* restore original MAC address */
6862 rtl_rar_set(tp
, dev
->perm_addr
);
6865 static const struct net_device_ops rtl_netdev_ops
= {
6866 .ndo_open
= rtl_open
,
6867 .ndo_stop
= rtl8169_close
,
6868 .ndo_get_stats64
= rtl8169_get_stats64
,
6869 .ndo_start_xmit
= rtl8169_start_xmit
,
6870 .ndo_tx_timeout
= rtl8169_tx_timeout
,
6871 .ndo_validate_addr
= eth_validate_addr
,
6872 .ndo_change_mtu
= rtl8169_change_mtu
,
6873 .ndo_fix_features
= rtl8169_fix_features
,
6874 .ndo_set_features
= rtl8169_set_features
,
6875 .ndo_set_mac_address
= rtl_set_mac_address
,
6876 .ndo_do_ioctl
= rtl8169_ioctl
,
6877 .ndo_set_rx_mode
= rtl_set_rx_mode
,
6878 #ifdef CONFIG_NET_POLL_CONTROLLER
6879 .ndo_poll_controller
= rtl8169_netpoll
,
6884 static const struct rtl_cfg_info
{
6885 void (*hw_start
)(struct rtl8169_private
*tp
);
6887 unsigned int has_gmii
:1;
6888 const struct rtl_coalesce_info
*coalesce_info
;
6889 } rtl_cfg_infos
[] = {
6891 .hw_start
= rtl_hw_start_8169
,
6892 .irq_mask
= SYSErr
| LinkChg
| RxOverflow
| RxFIFOOver
,
6894 .coalesce_info
= rtl_coalesce_info_8169
,
6897 .hw_start
= rtl_hw_start_8168
,
6898 .irq_mask
= LinkChg
| RxOverflow
,
6900 .coalesce_info
= rtl_coalesce_info_8168_8136
,
6903 .hw_start
= rtl_hw_start_8101
,
6904 .irq_mask
= LinkChg
| RxOverflow
| RxFIFOOver
,
6905 .coalesce_info
= rtl_coalesce_info_8168_8136
,
6909 static int rtl_alloc_irq(struct rtl8169_private
*tp
)
6913 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
6914 rtl_unlock_config_regs(tp
);
6915 RTL_W8(tp
, Config2
, RTL_R8(tp
, Config2
) & ~MSIEnable
);
6916 rtl_lock_config_regs(tp
);
6917 flags
= PCI_IRQ_LEGACY
;
6919 flags
= PCI_IRQ_ALL_TYPES
;
6922 return pci_alloc_irq_vectors(tp
->pci_dev
, 1, 1, flags
);
6925 static void rtl_read_mac_address(struct rtl8169_private
*tp
,
6926 u8 mac_addr
[ETH_ALEN
])
6930 /* Get MAC address */
6931 switch (tp
->mac_version
) {
6932 case RTL_GIGA_MAC_VER_35
... RTL_GIGA_MAC_VER_38
:
6933 case RTL_GIGA_MAC_VER_40
... RTL_GIGA_MAC_VER_51
:
6934 value
= rtl_eri_read(tp
, 0xe0);
6935 mac_addr
[0] = (value
>> 0) & 0xff;
6936 mac_addr
[1] = (value
>> 8) & 0xff;
6937 mac_addr
[2] = (value
>> 16) & 0xff;
6938 mac_addr
[3] = (value
>> 24) & 0xff;
6940 value
= rtl_eri_read(tp
, 0xe4);
6941 mac_addr
[4] = (value
>> 0) & 0xff;
6942 mac_addr
[5] = (value
>> 8) & 0xff;
6949 DECLARE_RTL_COND(rtl_link_list_ready_cond
)
6951 return RTL_R8(tp
, MCU
) & LINK_LIST_RDY
;
6954 DECLARE_RTL_COND(rtl_rxtx_empty_cond
)
6956 return (RTL_R8(tp
, MCU
) & RXTX_EMPTY
) == RXTX_EMPTY
;
6959 static int r8169_mdio_read_reg(struct mii_bus
*mii_bus
, int phyaddr
, int phyreg
)
6961 struct rtl8169_private
*tp
= mii_bus
->priv
;
6966 return rtl_readphy(tp
, phyreg
);
6969 static int r8169_mdio_write_reg(struct mii_bus
*mii_bus
, int phyaddr
,
6970 int phyreg
, u16 val
)
6972 struct rtl8169_private
*tp
= mii_bus
->priv
;
6977 rtl_writephy(tp
, phyreg
, val
);
6982 static int r8169_mdio_register(struct rtl8169_private
*tp
)
6984 struct pci_dev
*pdev
= tp
->pci_dev
;
6985 struct mii_bus
*new_bus
;
6988 new_bus
= devm_mdiobus_alloc(&pdev
->dev
);
6992 new_bus
->name
= "r8169";
6994 new_bus
->parent
= &pdev
->dev
;
6995 new_bus
->irq
[0] = PHY_IGNORE_INTERRUPT
;
6996 snprintf(new_bus
->id
, MII_BUS_ID_SIZE
, "r8169-%x", pci_dev_id(pdev
));
6998 new_bus
->read
= r8169_mdio_read_reg
;
6999 new_bus
->write
= r8169_mdio_write_reg
;
7001 ret
= mdiobus_register(new_bus
);
7005 tp
->phydev
= mdiobus_get_phy(new_bus
, 0);
7007 mdiobus_unregister(new_bus
);
7011 /* PHY will be woken up in rtl_open() */
7012 phy_suspend(tp
->phydev
);
7017 static void rtl_hw_init_8168g(struct rtl8169_private
*tp
)
7021 tp
->ocp_base
= OCP_STD_PHY_BASE
;
7023 RTL_W32(tp
, MISC
, RTL_R32(tp
, MISC
) | RXDV_GATED_EN
);
7025 if (!rtl_udelay_loop_wait_high(tp
, &rtl_txcfg_empty_cond
, 100, 42))
7028 if (!rtl_udelay_loop_wait_high(tp
, &rtl_rxtx_empty_cond
, 100, 42))
7031 RTL_W8(tp
, ChipCmd
, RTL_R8(tp
, ChipCmd
) & ~(CmdTxEnb
| CmdRxEnb
));
7033 RTL_W8(tp
, MCU
, RTL_R8(tp
, MCU
) & ~NOW_IS_OOB
);
7035 data
= r8168_mac_ocp_read(tp
, 0xe8de);
7037 r8168_mac_ocp_write(tp
, 0xe8de, data
);
7039 if (!rtl_udelay_loop_wait_high(tp
, &rtl_link_list_ready_cond
, 100, 42))
7042 data
= r8168_mac_ocp_read(tp
, 0xe8de);
7044 r8168_mac_ocp_write(tp
, 0xe8de, data
);
7046 if (!rtl_udelay_loop_wait_high(tp
, &rtl_link_list_ready_cond
, 100, 42))
7050 static void rtl_hw_init_8168ep(struct rtl8169_private
*tp
)
7052 rtl8168ep_stop_cmac(tp
);
7053 rtl_hw_init_8168g(tp
);
7056 static void rtl_hw_initialize(struct rtl8169_private
*tp
)
7058 switch (tp
->mac_version
) {
7059 case RTL_GIGA_MAC_VER_40
... RTL_GIGA_MAC_VER_48
:
7060 rtl_hw_init_8168g(tp
);
7062 case RTL_GIGA_MAC_VER_49
... RTL_GIGA_MAC_VER_51
:
7063 rtl_hw_init_8168ep(tp
);
7070 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
7071 static bool rtl_chip_supports_csum_v2(struct rtl8169_private
*tp
)
7073 switch (tp
->mac_version
) {
7074 case RTL_GIGA_MAC_VER_01
... RTL_GIGA_MAC_VER_06
:
7075 case RTL_GIGA_MAC_VER_10
... RTL_GIGA_MAC_VER_17
:
7082 static int rtl_jumbo_max(struct rtl8169_private
*tp
)
7084 /* Non-GBit versions don't support jumbo frames */
7085 if (!tp
->supports_gmii
)
7088 switch (tp
->mac_version
) {
7090 case RTL_GIGA_MAC_VER_01
... RTL_GIGA_MAC_VER_06
:
7093 case RTL_GIGA_MAC_VER_11
:
7094 case RTL_GIGA_MAC_VER_12
:
7095 case RTL_GIGA_MAC_VER_17
:
7098 case RTL_GIGA_MAC_VER_18
... RTL_GIGA_MAC_VER_24
:
7105 static void rtl_disable_clk(void *data
)
7107 clk_disable_unprepare(data
);
7110 static int rtl_get_ether_clk(struct rtl8169_private
*tp
)
7112 struct device
*d
= tp_to_dev(tp
);
7116 clk
= devm_clk_get(d
, "ether_clk");
7120 /* clk-core allows NULL (for suspend / resume) */
7122 else if (rc
!= -EPROBE_DEFER
)
7123 dev_err(d
, "failed to get clk: %d\n", rc
);
7126 rc
= clk_prepare_enable(clk
);
7128 dev_err(d
, "failed to enable clk: %d\n", rc
);
7130 rc
= devm_add_action_or_reset(d
, rtl_disable_clk
, clk
);
7136 static int rtl_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
7138 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
7139 /* align to u16 for is_valid_ether_addr() */
7140 u8 mac_addr
[ETH_ALEN
] __aligned(2) = {};
7141 struct rtl8169_private
*tp
;
7142 struct net_device
*dev
;
7143 int chipset
, region
, i
;
7146 dev
= devm_alloc_etherdev(&pdev
->dev
, sizeof (*tp
));
7150 SET_NETDEV_DEV(dev
, &pdev
->dev
);
7151 dev
->netdev_ops
= &rtl_netdev_ops
;
7152 tp
= netdev_priv(dev
);
7155 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
7156 tp
->supports_gmii
= cfg
->has_gmii
;
7158 /* Get the *optional* external "ether_clk" used on some boards */
7159 rc
= rtl_get_ether_clk(tp
);
7163 /* Disable ASPM completely as that cause random device stop working
7164 * problems as well as full system hangs for some PCIe devices users.
7166 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
| PCIE_LINK_STATE_L1
);
7168 /* enable device (incl. PCI PM wakeup and hotplug setup) */
7169 rc
= pcim_enable_device(pdev
);
7171 dev_err(&pdev
->dev
, "enable failure\n");
7175 if (pcim_set_mwi(pdev
) < 0)
7176 dev_info(&pdev
->dev
, "Mem-Wr-Inval unavailable\n");
7178 /* use first MMIO region */
7179 region
= ffs(pci_select_bars(pdev
, IORESOURCE_MEM
)) - 1;
7181 dev_err(&pdev
->dev
, "no MMIO resource found\n");
7185 /* check for weird/broken PCI region reporting */
7186 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
7187 dev_err(&pdev
->dev
, "Invalid PCI region size(s), aborting\n");
7191 rc
= pcim_iomap_regions(pdev
, BIT(region
), MODULENAME
);
7193 dev_err(&pdev
->dev
, "cannot remap MMIO, aborting\n");
7197 tp
->mmio_addr
= pcim_iomap_table(pdev
)[region
];
7199 /* Identify chip attached to board */
7200 rtl8169_get_mac_version(tp
);
7201 if (tp
->mac_version
== RTL_GIGA_MAC_NONE
)
7204 if (rtl_tbi_enabled(tp
)) {
7205 dev_err(&pdev
->dev
, "TBI fiber mode not supported\n");
7209 tp
->cp_cmd
= RTL_R16(tp
, CPlusCmd
);
7211 if (sizeof(dma_addr_t
) > 4 && tp
->mac_version
>= RTL_GIGA_MAC_VER_18
&&
7212 !dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64))) {
7213 dev
->features
|= NETIF_F_HIGHDMA
;
7215 rc
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
7217 dev_err(&pdev
->dev
, "DMA configuration failed\n");
7224 rtl8169_irq_mask_and_ack(tp
);
7226 rtl_hw_initialize(tp
);
7230 pci_set_master(pdev
);
7232 rtl_init_mdio_ops(tp
);
7233 rtl_init_jumbo_ops(tp
);
7235 chipset
= tp
->mac_version
;
7237 rc
= rtl_alloc_irq(tp
);
7239 dev_err(&pdev
->dev
, "Can't allocate interrupt\n");
7243 mutex_init(&tp
->wk
.mutex
);
7244 INIT_WORK(&tp
->wk
.work
, rtl_task
);
7245 u64_stats_init(&tp
->rx_stats
.syncp
);
7246 u64_stats_init(&tp
->tx_stats
.syncp
);
7248 /* get MAC address */
7249 rc
= eth_platform_get_mac_address(&pdev
->dev
, mac_addr
);
7251 rtl_read_mac_address(tp
, mac_addr
);
7253 if (is_valid_ether_addr(mac_addr
))
7254 rtl_rar_set(tp
, mac_addr
);
7256 for (i
= 0; i
< ETH_ALEN
; i
++)
7257 dev
->dev_addr
[i
] = RTL_R8(tp
, MAC0
+ i
);
7259 dev
->ethtool_ops
= &rtl8169_ethtool_ops
;
7261 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, NAPI_POLL_WEIGHT
);
7263 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7264 * properly for all devices */
7265 dev
->features
|= NETIF_F_RXCSUM
|
7266 NETIF_F_HW_VLAN_CTAG_TX
| NETIF_F_HW_VLAN_CTAG_RX
;
7268 dev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
7269 NETIF_F_RXCSUM
| NETIF_F_HW_VLAN_CTAG_TX
|
7270 NETIF_F_HW_VLAN_CTAG_RX
;
7271 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
7273 dev
->priv_flags
|= IFF_LIVE_ADDR_CHANGE
;
7275 tp
->cp_cmd
|= RxChkSum
| RxVlan
;
7278 * Pretend we are using VLANs; This bypasses a nasty bug where
7279 * Interrupts stop flowing on high load on 8110SCd controllers.
7281 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
7282 /* Disallow toggling */
7283 dev
->hw_features
&= ~NETIF_F_HW_VLAN_CTAG_RX
;
7285 if (rtl_chip_supports_csum_v2(tp
)) {
7286 tp
->tso_csum
= rtl8169_tso_csum_v2
;
7287 dev
->hw_features
|= NETIF_F_IPV6_CSUM
| NETIF_F_TSO6
;
7289 tp
->tso_csum
= rtl8169_tso_csum_v1
;
7292 dev
->hw_features
|= NETIF_F_RXALL
;
7293 dev
->hw_features
|= NETIF_F_RXFCS
;
7295 /* MTU range: 60 - hw-specific max */
7296 dev
->min_mtu
= ETH_ZLEN
;
7297 jumbo_max
= rtl_jumbo_max(tp
);
7298 dev
->max_mtu
= jumbo_max
;
7300 tp
->hw_start
= cfg
->hw_start
;
7301 tp
->irq_mask
= RTL_EVENT_NAPI
| cfg
->irq_mask
;
7302 tp
->coalesce_info
= cfg
->coalesce_info
;
7304 tp
->fw_name
= rtl_chip_infos
[chipset
].fw_name
;
7306 tp
->counters
= dmam_alloc_coherent (&pdev
->dev
, sizeof(*tp
->counters
),
7307 &tp
->counters_phys_addr
,
7312 pci_set_drvdata(pdev
, dev
);
7314 rc
= r8169_mdio_register(tp
);
7318 /* chip gets powered up in rtl_open() */
7319 rtl_pll_power_down(tp
);
7321 rc
= register_netdev(dev
);
7323 goto err_mdio_unregister
;
7325 netif_info(tp
, probe
, dev
, "%s, %pM, XID %03x, IRQ %d\n",
7326 rtl_chip_infos
[chipset
].name
, dev
->dev_addr
,
7327 (RTL_R32(tp
, TxConfig
) >> 20) & 0xfcf,
7328 pci_irq_vector(pdev
, 0));
7330 if (jumbo_max
> JUMBO_1K
)
7331 netif_info(tp
, probe
, dev
,
7332 "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7333 jumbo_max
, tp
->mac_version
<= RTL_GIGA_MAC_VER_06
?
7336 if (r8168_check_dash(tp
))
7337 rtl8168_driver_start(tp
);
7339 if (pci_dev_run_wake(pdev
))
7340 pm_runtime_put_sync(&pdev
->dev
);
7344 err_mdio_unregister
:
7345 mdiobus_unregister(tp
->phydev
->mdio
.bus
);
7349 static struct pci_driver rtl8169_pci_driver
= {
7351 .id_table
= rtl8169_pci_tbl
,
7352 .probe
= rtl_init_one
,
7353 .remove
= rtl_remove_one
,
7354 .shutdown
= rtl_shutdown
,
7355 .driver
.pm
= RTL8169_PM_OPS
,
7358 module_pci_driver(rtl8169_pci_driver
);