2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28 #include <linux/pci-aspm.h>
29 #include <linux/prefetch.h>
30 #include <linux/ipv6.h>
31 #include <net/ip6_checksum.h>
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
45 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
47 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
48 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
49 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
50 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
51 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
52 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
53 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
54 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
55 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
56 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
57 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
58 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
61 #define assert(expr) \
63 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
64 #expr,__FILE__,__func__,__LINE__); \
66 #define dprintk(fmt, args...) \
67 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
69 #define assert(expr) do {} while (0)
70 #define dprintk(fmt, args...) do {} while (0)
71 #endif /* RTL8169_DEBUG */
73 #define R8169_MSG_DEFAULT \
74 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
76 #define TX_SLOTS_AVAIL(tp) \
77 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
79 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
80 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
81 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
83 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
84 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
85 static const int multicast_filter_limit
= 32;
87 #define MAX_READ_REQUEST_SHIFT 12
88 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
89 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
91 #define R8169_REGS_SIZE 256
92 #define R8169_NAPI_WEIGHT 64
93 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
94 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
95 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
96 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
98 #define RTL8169_TX_TIMEOUT (6*HZ)
99 #define RTL8169_PHY_TIMEOUT (10*HZ)
101 /* write/read MMIO register */
102 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
103 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
104 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
105 #define RTL_R8(reg) readb (ioaddr + (reg))
106 #define RTL_R16(reg) readw (ioaddr + (reg))
107 #define RTL_R32(reg) readl (ioaddr + (reg))
110 RTL_GIGA_MAC_VER_01
= 0,
161 RTL_GIGA_MAC_NONE
= 0xff,
164 enum rtl_tx_desc_version
{
169 #define JUMBO_1K ETH_DATA_LEN
170 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
171 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
172 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
173 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
175 #define _R(NAME,TD,FW,SZ,B) { \
183 static const struct {
185 enum rtl_tx_desc_version txd_version
;
189 } rtl_chip_infos
[] = {
191 [RTL_GIGA_MAC_VER_01
] =
192 _R("RTL8169", RTL_TD_0
, NULL
, JUMBO_7K
, true),
193 [RTL_GIGA_MAC_VER_02
] =
194 _R("RTL8169s", RTL_TD_0
, NULL
, JUMBO_7K
, true),
195 [RTL_GIGA_MAC_VER_03
] =
196 _R("RTL8110s", RTL_TD_0
, NULL
, JUMBO_7K
, true),
197 [RTL_GIGA_MAC_VER_04
] =
198 _R("RTL8169sb/8110sb", RTL_TD_0
, NULL
, JUMBO_7K
, true),
199 [RTL_GIGA_MAC_VER_05
] =
200 _R("RTL8169sc/8110sc", RTL_TD_0
, NULL
, JUMBO_7K
, true),
201 [RTL_GIGA_MAC_VER_06
] =
202 _R("RTL8169sc/8110sc", RTL_TD_0
, NULL
, JUMBO_7K
, true),
204 [RTL_GIGA_MAC_VER_07
] =
205 _R("RTL8102e", RTL_TD_1
, NULL
, JUMBO_1K
, true),
206 [RTL_GIGA_MAC_VER_08
] =
207 _R("RTL8102e", RTL_TD_1
, NULL
, JUMBO_1K
, true),
208 [RTL_GIGA_MAC_VER_09
] =
209 _R("RTL8102e", RTL_TD_1
, NULL
, JUMBO_1K
, true),
210 [RTL_GIGA_MAC_VER_10
] =
211 _R("RTL8101e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
212 [RTL_GIGA_MAC_VER_11
] =
213 _R("RTL8168b/8111b", RTL_TD_0
, NULL
, JUMBO_4K
, false),
214 [RTL_GIGA_MAC_VER_12
] =
215 _R("RTL8168b/8111b", RTL_TD_0
, NULL
, JUMBO_4K
, false),
216 [RTL_GIGA_MAC_VER_13
] =
217 _R("RTL8101e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
218 [RTL_GIGA_MAC_VER_14
] =
219 _R("RTL8100e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
220 [RTL_GIGA_MAC_VER_15
] =
221 _R("RTL8100e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
222 [RTL_GIGA_MAC_VER_16
] =
223 _R("RTL8101e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
224 [RTL_GIGA_MAC_VER_17
] =
225 _R("RTL8168b/8111b", RTL_TD_0
, NULL
, JUMBO_4K
, false),
226 [RTL_GIGA_MAC_VER_18
] =
227 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
, JUMBO_6K
, false),
228 [RTL_GIGA_MAC_VER_19
] =
229 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
230 [RTL_GIGA_MAC_VER_20
] =
231 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
232 [RTL_GIGA_MAC_VER_21
] =
233 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
234 [RTL_GIGA_MAC_VER_22
] =
235 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
236 [RTL_GIGA_MAC_VER_23
] =
237 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
, JUMBO_6K
, false),
238 [RTL_GIGA_MAC_VER_24
] =
239 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
, JUMBO_6K
, false),
240 [RTL_GIGA_MAC_VER_25
] =
241 _R("RTL8168d/8111d", RTL_TD_1
, FIRMWARE_8168D_1
,
243 [RTL_GIGA_MAC_VER_26
] =
244 _R("RTL8168d/8111d", RTL_TD_1
, FIRMWARE_8168D_2
,
246 [RTL_GIGA_MAC_VER_27
] =
247 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
, JUMBO_9K
, false),
248 [RTL_GIGA_MAC_VER_28
] =
249 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
, JUMBO_9K
, false),
250 [RTL_GIGA_MAC_VER_29
] =
251 _R("RTL8105e", RTL_TD_1
, FIRMWARE_8105E_1
,
253 [RTL_GIGA_MAC_VER_30
] =
254 _R("RTL8105e", RTL_TD_1
, FIRMWARE_8105E_1
,
256 [RTL_GIGA_MAC_VER_31
] =
257 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
, JUMBO_9K
, false),
258 [RTL_GIGA_MAC_VER_32
] =
259 _R("RTL8168e/8111e", RTL_TD_1
, FIRMWARE_8168E_1
,
261 [RTL_GIGA_MAC_VER_33
] =
262 _R("RTL8168e/8111e", RTL_TD_1
, FIRMWARE_8168E_2
,
264 [RTL_GIGA_MAC_VER_34
] =
265 _R("RTL8168evl/8111evl",RTL_TD_1
, FIRMWARE_8168E_3
,
267 [RTL_GIGA_MAC_VER_35
] =
268 _R("RTL8168f/8111f", RTL_TD_1
, FIRMWARE_8168F_1
,
270 [RTL_GIGA_MAC_VER_36
] =
271 _R("RTL8168f/8111f", RTL_TD_1
, FIRMWARE_8168F_2
,
273 [RTL_GIGA_MAC_VER_37
] =
274 _R("RTL8402", RTL_TD_1
, FIRMWARE_8402_1
,
276 [RTL_GIGA_MAC_VER_38
] =
277 _R("RTL8411", RTL_TD_1
, FIRMWARE_8411_1
,
279 [RTL_GIGA_MAC_VER_39
] =
280 _R("RTL8106e", RTL_TD_1
, FIRMWARE_8106E_1
,
282 [RTL_GIGA_MAC_VER_40
] =
283 _R("RTL8168g/8111g", RTL_TD_1
, FIRMWARE_8168G_2
,
285 [RTL_GIGA_MAC_VER_41
] =
286 _R("RTL8168g/8111g", RTL_TD_1
, NULL
, JUMBO_9K
, false),
287 [RTL_GIGA_MAC_VER_42
] =
288 _R("RTL8168g/8111g", RTL_TD_1
, FIRMWARE_8168G_3
,
290 [RTL_GIGA_MAC_VER_43
] =
291 _R("RTL8106e", RTL_TD_1
, FIRMWARE_8106E_2
,
293 [RTL_GIGA_MAC_VER_44
] =
294 _R("RTL8411", RTL_TD_1
, FIRMWARE_8411_2
,
296 [RTL_GIGA_MAC_VER_45
] =
297 _R("RTL8168h/8111h", RTL_TD_1
, FIRMWARE_8168H_1
,
299 [RTL_GIGA_MAC_VER_46
] =
300 _R("RTL8168h/8111h", RTL_TD_1
, FIRMWARE_8168H_2
,
302 [RTL_GIGA_MAC_VER_47
] =
303 _R("RTL8107e", RTL_TD_1
, FIRMWARE_8107E_1
,
305 [RTL_GIGA_MAC_VER_48
] =
306 _R("RTL8107e", RTL_TD_1
, FIRMWARE_8107E_2
,
308 [RTL_GIGA_MAC_VER_49
] =
309 _R("RTL8168ep/8111ep", RTL_TD_1
, NULL
,
311 [RTL_GIGA_MAC_VER_50
] =
312 _R("RTL8168ep/8111ep", RTL_TD_1
, NULL
,
314 [RTL_GIGA_MAC_VER_51
] =
315 _R("RTL8168ep/8111ep", RTL_TD_1
, NULL
,
326 static const struct pci_device_id rtl8169_pci_tbl
[] = {
327 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
328 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
329 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8161), 0, 0, RTL_CFG_1
},
330 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
331 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
332 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
333 { PCI_VENDOR_ID_DLINK
, 0x4300,
334 PCI_VENDOR_ID_DLINK
, 0x4b10, 0, 0, RTL_CFG_1
},
335 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
336 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4302), 0, 0, RTL_CFG_0
},
337 { PCI_DEVICE(PCI_VENDOR_ID_AT
, 0xc107), 0, 0, RTL_CFG_0
},
338 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
339 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
340 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
342 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
346 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
348 static int rx_buf_sz
= 16383;
349 static int use_dac
= -1;
355 MAC0
= 0, /* Ethernet hardware address. */
357 MAR0
= 8, /* Multicast filter. */
358 CounterAddrLow
= 0x10,
359 CounterAddrHigh
= 0x14,
360 TxDescStartAddrLow
= 0x20,
361 TxDescStartAddrHigh
= 0x24,
362 TxHDescStartAddrLow
= 0x28,
363 TxHDescStartAddrHigh
= 0x2c,
372 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
373 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
376 #define RX128_INT_EN (1 << 15) /* 8111c and later */
377 #define RX_MULTI_EN (1 << 14) /* 8111c only */
378 #define RXCFG_FIFO_SHIFT 13
379 /* No threshold before first PCI xfer */
380 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
381 #define RX_EARLY_OFF (1 << 11)
382 #define RXCFG_DMA_SHIFT 8
383 /* Unlimited maximum PCI burst. */
384 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
391 #define PME_SIGNAL (1 << 5) /* 8168c and later */
403 #define RTL_COALESCE_MASK 0x0f
404 #define RTL_COALESCE_SHIFT 4
405 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
406 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
408 RxDescAddrLow
= 0xe4,
409 RxDescAddrHigh
= 0xe8,
410 EarlyTxThres
= 0xec, /* 8169. Unit of 32 bytes. */
412 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
414 MaxTxPacketSize
= 0xec, /* 8101/8168. Unit of 128 bytes. */
416 #define TxPacketMax (8064 >> 7)
417 #define EarlySize 0x27
420 FuncEventMask
= 0xf4,
421 FuncPresetState
= 0xf8,
426 FuncForceEvent
= 0xfc,
429 enum rtl8110_registers
{
435 enum rtl8168_8101_registers
{
438 #define CSIAR_FLAG 0x80000000
439 #define CSIAR_WRITE_CMD 0x80000000
440 #define CSIAR_BYTE_ENABLE 0x0f
441 #define CSIAR_BYTE_ENABLE_SHIFT 12
442 #define CSIAR_ADDR_MASK 0x0fff
443 #define CSIAR_FUNC_CARD 0x00000000
444 #define CSIAR_FUNC_SDIO 0x00010000
445 #define CSIAR_FUNC_NIC 0x00020000
446 #define CSIAR_FUNC_NIC2 0x00010000
449 #define EPHYAR_FLAG 0x80000000
450 #define EPHYAR_WRITE_CMD 0x80000000
451 #define EPHYAR_REG_MASK 0x1f
452 #define EPHYAR_REG_SHIFT 16
453 #define EPHYAR_DATA_MASK 0xffff
455 #define PFM_EN (1 << 6)
456 #define TX_10M_PS_EN (1 << 7)
458 #define FIX_NAK_1 (1 << 4)
459 #define FIX_NAK_2 (1 << 3)
462 #define NOW_IS_OOB (1 << 7)
463 #define TX_EMPTY (1 << 5)
464 #define RX_EMPTY (1 << 4)
465 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
466 #define EN_NDP (1 << 3)
467 #define EN_OOB_RESET (1 << 2)
468 #define LINK_LIST_RDY (1 << 1)
470 #define EFUSEAR_FLAG 0x80000000
471 #define EFUSEAR_WRITE_CMD 0x80000000
472 #define EFUSEAR_READ_CMD 0x00000000
473 #define EFUSEAR_REG_MASK 0x03ff
474 #define EFUSEAR_REG_SHIFT 8
475 #define EFUSEAR_DATA_MASK 0xff
477 #define PFM_D3COLD_EN (1 << 6)
480 enum rtl8168_registers
{
485 #define ERIAR_FLAG 0x80000000
486 #define ERIAR_WRITE_CMD 0x80000000
487 #define ERIAR_READ_CMD 0x00000000
488 #define ERIAR_ADDR_BYTE_ALIGN 4
489 #define ERIAR_TYPE_SHIFT 16
490 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
491 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
492 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
493 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
494 #define ERIAR_MASK_SHIFT 12
495 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
496 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
497 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
498 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
499 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
500 EPHY_RXER_NUM
= 0x7c,
501 OCPDR
= 0xb0, /* OCP GPHY access */
502 #define OCPDR_WRITE_CMD 0x80000000
503 #define OCPDR_READ_CMD 0x00000000
504 #define OCPDR_REG_MASK 0x7f
505 #define OCPDR_GPHY_REG_SHIFT 16
506 #define OCPDR_DATA_MASK 0xffff
508 #define OCPAR_FLAG 0x80000000
509 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
510 #define OCPAR_GPHY_READ_CMD 0x0000f060
512 RDSAR1
= 0xd0, /* 8168c only. Undocumented on 8168dp */
513 MISC
= 0xf0, /* 8168e only. */
514 #define TXPLA_RST (1 << 29)
515 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
516 #define PWM_EN (1 << 22)
517 #define RXDV_GATED_EN (1 << 19)
518 #define EARLY_TALLY_EN (1 << 16)
521 enum rtl_register_content
{
522 /* InterruptStatusBits */
526 TxDescUnavail
= 0x0080,
550 /* TXPoll register p.5 */
551 HPQ
= 0x80, /* Poll cmd on the high prio queue */
552 NPQ
= 0x40, /* Poll cmd on the low prio queue */
553 FSWInt
= 0x01, /* Forced software interrupt */
557 Cfg9346_Unlock
= 0xc0,
562 AcceptBroadcast
= 0x08,
563 AcceptMulticast
= 0x04,
565 AcceptAllPhys
= 0x01,
566 #define RX_CONFIG_ACCEPT_MASK 0x3f
569 TxInterFrameGapShift
= 24,
570 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
572 /* Config1 register p.24 */
575 Speed_down
= (1 << 4),
579 PMEnable
= (1 << 0), /* Power Management Enable */
581 /* Config2 register p. 25 */
582 ClkReqEn
= (1 << 7), /* Clock Request Enable */
583 MSIEnable
= (1 << 5), /* 8169 only. Reserved in the 8168. */
584 PCI_Clock_66MHz
= 0x01,
585 PCI_Clock_33MHz
= 0x00,
587 /* Config3 register p.25 */
588 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
589 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
590 Jumbo_En0
= (1 << 2), /* 8168 only. Reserved in the 8168b */
591 Rdy_to_L23
= (1 << 1), /* L23 Enable */
592 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
594 /* Config4 register */
595 Jumbo_En1
= (1 << 1), /* 8168 only. Reserved in the 8168b */
597 /* Config5 register p.27 */
598 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
599 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
600 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
602 LanWake
= (1 << 1), /* LanWake enable/disable */
603 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
604 ASPM_en
= (1 << 0), /* ASPM enable */
607 TBIReset
= 0x80000000,
608 TBILoopback
= 0x40000000,
609 TBINwEnable
= 0x20000000,
610 TBINwRestart
= 0x10000000,
611 TBILinkOk
= 0x02000000,
612 TBINwComplete
= 0x01000000,
615 EnableBist
= (1 << 15), // 8168 8101
616 Mac_dbgo_oe
= (1 << 14), // 8168 8101
617 Normal_mode
= (1 << 13), // unused
618 Force_half_dup
= (1 << 12), // 8168 8101
619 Force_rxflow_en
= (1 << 11), // 8168 8101
620 Force_txflow_en
= (1 << 10), // 8168 8101
621 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
622 ASF
= (1 << 8), // 8168 8101
623 PktCntrDisable
= (1 << 7), // 8168 8101
624 Mac_dbgo_sel
= 0x001c, // 8168
629 INTT_0
= 0x0000, // 8168
630 INTT_1
= 0x0001, // 8168
631 INTT_2
= 0x0002, // 8168
632 INTT_3
= 0x0003, // 8168
634 /* rtl8169_PHYstatus */
645 TBILinkOK
= 0x02000000,
647 /* ResetCounterCommand */
650 /* DumpCounterCommand */
653 /* magic enable v2 */
654 MagicPacket_v2
= (1 << 16), /* Wake up when receives a Magic Packet */
658 /* First doubleword. */
659 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
660 RingEnd
= (1 << 30), /* End of descriptor ring */
661 FirstFrag
= (1 << 29), /* First segment of a packet */
662 LastFrag
= (1 << 28), /* Final segment of a packet */
666 enum rtl_tx_desc_bit
{
667 /* First doubleword. */
668 TD_LSO
= (1 << 27), /* Large Send Offload */
669 #define TD_MSS_MAX 0x07ffu /* MSS value */
671 /* Second doubleword. */
672 TxVlanTag
= (1 << 17), /* Add VLAN tag */
675 /* 8169, 8168b and 810x except 8102e. */
676 enum rtl_tx_desc_bit_0
{
677 /* First doubleword. */
678 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
679 TD0_TCP_CS
= (1 << 16), /* Calculate TCP/IP checksum */
680 TD0_UDP_CS
= (1 << 17), /* Calculate UDP/IP checksum */
681 TD0_IP_CS
= (1 << 18), /* Calculate IP checksum */
684 /* 8102e, 8168c and beyond. */
685 enum rtl_tx_desc_bit_1
{
686 /* First doubleword. */
687 TD1_GTSENV4
= (1 << 26), /* Giant Send for IPv4 */
688 TD1_GTSENV6
= (1 << 25), /* Giant Send for IPv6 */
689 #define GTTCPHO_SHIFT 18
690 #define GTTCPHO_MAX 0x7fU
692 /* Second doubleword. */
693 #define TCPHO_SHIFT 18
694 #define TCPHO_MAX 0x3ffU
695 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
696 TD1_IPv6_CS
= (1 << 28), /* Calculate IPv6 checksum */
697 TD1_IPv4_CS
= (1 << 29), /* Calculate IPv4 checksum */
698 TD1_TCP_CS
= (1 << 30), /* Calculate TCP/IP checksum */
699 TD1_UDP_CS
= (1 << 31), /* Calculate UDP/IP checksum */
702 enum rtl_rx_desc_bit
{
704 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
705 PID0
= (1 << 17), /* Protocol ID bit 0/2 */
707 #define RxProtoUDP (PID1)
708 #define RxProtoTCP (PID0)
709 #define RxProtoIP (PID1 | PID0)
710 #define RxProtoMask RxProtoIP
712 IPFail
= (1 << 16), /* IP checksum failed */
713 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
714 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
715 RxVlanTag
= (1 << 16), /* VLAN tag available */
718 #define RsvdMask 0x3fffc000
735 u8 __pad
[sizeof(void *) - sizeof(u32
)];
739 RTL_FEATURE_WOL
= (1 << 0),
740 RTL_FEATURE_MSI
= (1 << 1),
741 RTL_FEATURE_GMII
= (1 << 2),
744 struct rtl8169_counters
{
751 __le32 tx_one_collision
;
752 __le32 tx_multi_collision
;
760 struct rtl8169_tc_offsets
{
763 __le32 tx_multi_collision
;
768 RTL_FLAG_TASK_ENABLED
,
769 RTL_FLAG_TASK_SLOW_PENDING
,
770 RTL_FLAG_TASK_RESET_PENDING
,
771 RTL_FLAG_TASK_PHY_PENDING
,
775 struct rtl8169_stats
{
778 struct u64_stats_sync syncp
;
781 struct rtl8169_private
{
782 void __iomem
*mmio_addr
; /* memory map physical address */
783 struct pci_dev
*pci_dev
;
784 struct net_device
*dev
;
785 struct napi_struct napi
;
789 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
790 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
792 struct rtl8169_stats rx_stats
;
793 struct rtl8169_stats tx_stats
;
794 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
795 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
796 dma_addr_t TxPhyAddr
;
797 dma_addr_t RxPhyAddr
;
798 void *Rx_databuff
[NUM_RX_DESC
]; /* Rx data buffers */
799 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
800 struct timer_list timer
;
804 const struct rtl_coalesce_info
*coalesce_info
;
807 void (*write
)(struct rtl8169_private
*, int, int);
808 int (*read
)(struct rtl8169_private
*, int);
811 struct pll_power_ops
{
812 void (*down
)(struct rtl8169_private
*);
813 void (*up
)(struct rtl8169_private
*);
817 void (*enable
)(struct rtl8169_private
*);
818 void (*disable
)(struct rtl8169_private
*);
822 void (*write
)(struct rtl8169_private
*, int, int);
823 u32 (*read
)(struct rtl8169_private
*, int);
826 int (*set_speed
)(struct net_device
*, u8 aneg
, u16 sp
, u8 dpx
, u32 adv
);
827 int (*get_link_ksettings
)(struct net_device
*,
828 struct ethtool_link_ksettings
*);
829 void (*phy_reset_enable
)(struct rtl8169_private
*tp
);
830 void (*hw_start
)(struct net_device
*);
831 unsigned int (*phy_reset_pending
)(struct rtl8169_private
*tp
);
832 unsigned int (*link_ok
)(void __iomem
*);
833 int (*do_ioctl
)(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
);
834 bool (*tso_csum
)(struct rtl8169_private
*, struct sk_buff
*, u32
*);
837 DECLARE_BITMAP(flags
, RTL_FLAG_MAX
);
839 struct work_struct work
;
844 struct mii_if_info mii
;
845 dma_addr_t counters_phys_addr
;
846 struct rtl8169_counters
*counters
;
847 struct rtl8169_tc_offsets tc_offset
;
852 const struct firmware
*fw
;
854 #define RTL_VER_SIZE 32
856 char version
[RTL_VER_SIZE
];
858 struct rtl_fw_phy_action
{
863 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
868 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
869 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
870 module_param(use_dac
, int, 0);
871 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
872 module_param_named(debug
, debug
.msg_enable
, int, 0);
873 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
874 MODULE_LICENSE("GPL");
875 MODULE_VERSION(RTL8169_VERSION
);
876 MODULE_FIRMWARE(FIRMWARE_8168D_1
);
877 MODULE_FIRMWARE(FIRMWARE_8168D_2
);
878 MODULE_FIRMWARE(FIRMWARE_8168E_1
);
879 MODULE_FIRMWARE(FIRMWARE_8168E_2
);
880 MODULE_FIRMWARE(FIRMWARE_8168E_3
);
881 MODULE_FIRMWARE(FIRMWARE_8105E_1
);
882 MODULE_FIRMWARE(FIRMWARE_8168F_1
);
883 MODULE_FIRMWARE(FIRMWARE_8168F_2
);
884 MODULE_FIRMWARE(FIRMWARE_8402_1
);
885 MODULE_FIRMWARE(FIRMWARE_8411_1
);
886 MODULE_FIRMWARE(FIRMWARE_8411_2
);
887 MODULE_FIRMWARE(FIRMWARE_8106E_1
);
888 MODULE_FIRMWARE(FIRMWARE_8106E_2
);
889 MODULE_FIRMWARE(FIRMWARE_8168G_2
);
890 MODULE_FIRMWARE(FIRMWARE_8168G_3
);
891 MODULE_FIRMWARE(FIRMWARE_8168H_1
);
892 MODULE_FIRMWARE(FIRMWARE_8168H_2
);
893 MODULE_FIRMWARE(FIRMWARE_8107E_1
);
894 MODULE_FIRMWARE(FIRMWARE_8107E_2
);
896 static void rtl_lock_work(struct rtl8169_private
*tp
)
898 mutex_lock(&tp
->wk
.mutex
);
901 static void rtl_unlock_work(struct rtl8169_private
*tp
)
903 mutex_unlock(&tp
->wk
.mutex
);
906 static void rtl_tx_performance_tweak(struct pci_dev
*pdev
, u16 force
)
908 pcie_capability_clear_and_set_word(pdev
, PCI_EXP_DEVCTL
,
909 PCI_EXP_DEVCTL_READRQ
, force
);
913 bool (*check
)(struct rtl8169_private
*);
917 static void rtl_udelay(unsigned int d
)
922 static bool rtl_loop_wait(struct rtl8169_private
*tp
, const struct rtl_cond
*c
,
923 void (*delay
)(unsigned int), unsigned int d
, int n
,
928 for (i
= 0; i
< n
; i
++) {
930 if (c
->check(tp
) == high
)
933 netif_err(tp
, drv
, tp
->dev
, "%s == %d (loop: %d, delay: %d).\n",
934 c
->msg
, !high
, n
, d
);
938 static bool rtl_udelay_loop_wait_high(struct rtl8169_private
*tp
,
939 const struct rtl_cond
*c
,
940 unsigned int d
, int n
)
942 return rtl_loop_wait(tp
, c
, rtl_udelay
, d
, n
, true);
945 static bool rtl_udelay_loop_wait_low(struct rtl8169_private
*tp
,
946 const struct rtl_cond
*c
,
947 unsigned int d
, int n
)
949 return rtl_loop_wait(tp
, c
, rtl_udelay
, d
, n
, false);
952 static bool rtl_msleep_loop_wait_high(struct rtl8169_private
*tp
,
953 const struct rtl_cond
*c
,
954 unsigned int d
, int n
)
956 return rtl_loop_wait(tp
, c
, msleep
, d
, n
, true);
959 static bool rtl_msleep_loop_wait_low(struct rtl8169_private
*tp
,
960 const struct rtl_cond
*c
,
961 unsigned int d
, int n
)
963 return rtl_loop_wait(tp
, c
, msleep
, d
, n
, false);
966 #define DECLARE_RTL_COND(name) \
967 static bool name ## _check(struct rtl8169_private *); \
969 static const struct rtl_cond name = { \
970 .check = name ## _check, \
974 static bool name ## _check(struct rtl8169_private *tp)
976 static bool rtl_ocp_reg_failure(struct rtl8169_private
*tp
, u32 reg
)
978 if (reg
& 0xffff0001) {
979 netif_err(tp
, drv
, tp
->dev
, "Invalid ocp reg %x!\n", reg
);
985 DECLARE_RTL_COND(rtl_ocp_gphy_cond
)
987 void __iomem
*ioaddr
= tp
->mmio_addr
;
989 return RTL_R32(GPHY_OCP
) & OCPAR_FLAG
;
992 static void r8168_phy_ocp_write(struct rtl8169_private
*tp
, u32 reg
, u32 data
)
994 void __iomem
*ioaddr
= tp
->mmio_addr
;
996 if (rtl_ocp_reg_failure(tp
, reg
))
999 RTL_W32(GPHY_OCP
, OCPAR_FLAG
| (reg
<< 15) | data
);
1001 rtl_udelay_loop_wait_low(tp
, &rtl_ocp_gphy_cond
, 25, 10);
1004 static u16
r8168_phy_ocp_read(struct rtl8169_private
*tp
, u32 reg
)
1006 void __iomem
*ioaddr
= tp
->mmio_addr
;
1008 if (rtl_ocp_reg_failure(tp
, reg
))
1011 RTL_W32(GPHY_OCP
, reg
<< 15);
1013 return rtl_udelay_loop_wait_high(tp
, &rtl_ocp_gphy_cond
, 25, 10) ?
1014 (RTL_R32(GPHY_OCP
) & 0xffff) : ~0;
1017 static void r8168_mac_ocp_write(struct rtl8169_private
*tp
, u32 reg
, u32 data
)
1019 void __iomem
*ioaddr
= tp
->mmio_addr
;
1021 if (rtl_ocp_reg_failure(tp
, reg
))
1024 RTL_W32(OCPDR
, OCPAR_FLAG
| (reg
<< 15) | data
);
1027 static u16
r8168_mac_ocp_read(struct rtl8169_private
*tp
, u32 reg
)
1029 void __iomem
*ioaddr
= tp
->mmio_addr
;
1031 if (rtl_ocp_reg_failure(tp
, reg
))
1034 RTL_W32(OCPDR
, reg
<< 15);
1036 return RTL_R32(OCPDR
);
1039 #define OCP_STD_PHY_BASE 0xa400
1041 static void r8168g_mdio_write(struct rtl8169_private
*tp
, int reg
, int value
)
1044 tp
->ocp_base
= value
? value
<< 4 : OCP_STD_PHY_BASE
;
1048 if (tp
->ocp_base
!= OCP_STD_PHY_BASE
)
1051 r8168_phy_ocp_write(tp
, tp
->ocp_base
+ reg
* 2, value
);
1054 static int r8168g_mdio_read(struct rtl8169_private
*tp
, int reg
)
1056 if (tp
->ocp_base
!= OCP_STD_PHY_BASE
)
1059 return r8168_phy_ocp_read(tp
, tp
->ocp_base
+ reg
* 2);
1062 static void mac_mcu_write(struct rtl8169_private
*tp
, int reg
, int value
)
1065 tp
->ocp_base
= value
<< 4;
1069 r8168_mac_ocp_write(tp
, tp
->ocp_base
+ reg
, value
);
1072 static int mac_mcu_read(struct rtl8169_private
*tp
, int reg
)
1074 return r8168_mac_ocp_read(tp
, tp
->ocp_base
+ reg
);
1077 DECLARE_RTL_COND(rtl_phyar_cond
)
1079 void __iomem
*ioaddr
= tp
->mmio_addr
;
1081 return RTL_R32(PHYAR
) & 0x80000000;
1084 static void r8169_mdio_write(struct rtl8169_private
*tp
, int reg
, int value
)
1086 void __iomem
*ioaddr
= tp
->mmio_addr
;
1088 RTL_W32(PHYAR
, 0x80000000 | (reg
& 0x1f) << 16 | (value
& 0xffff));
1090 rtl_udelay_loop_wait_low(tp
, &rtl_phyar_cond
, 25, 20);
1092 * According to hardware specs a 20us delay is required after write
1093 * complete indication, but before sending next command.
1098 static int r8169_mdio_read(struct rtl8169_private
*tp
, int reg
)
1100 void __iomem
*ioaddr
= tp
->mmio_addr
;
1103 RTL_W32(PHYAR
, 0x0 | (reg
& 0x1f) << 16);
1105 value
= rtl_udelay_loop_wait_high(tp
, &rtl_phyar_cond
, 25, 20) ?
1106 RTL_R32(PHYAR
) & 0xffff : ~0;
1109 * According to hardware specs a 20us delay is required after read
1110 * complete indication, but before sending next command.
1117 DECLARE_RTL_COND(rtl_ocpar_cond
)
1119 void __iomem
*ioaddr
= tp
->mmio_addr
;
1121 return RTL_R32(OCPAR
) & OCPAR_FLAG
;
1124 static void r8168dp_1_mdio_access(struct rtl8169_private
*tp
, int reg
, u32 data
)
1126 void __iomem
*ioaddr
= tp
->mmio_addr
;
1128 RTL_W32(OCPDR
, data
| ((reg
& OCPDR_REG_MASK
) << OCPDR_GPHY_REG_SHIFT
));
1129 RTL_W32(OCPAR
, OCPAR_GPHY_WRITE_CMD
);
1130 RTL_W32(EPHY_RXER_NUM
, 0);
1132 rtl_udelay_loop_wait_low(tp
, &rtl_ocpar_cond
, 1000, 100);
1135 static void r8168dp_1_mdio_write(struct rtl8169_private
*tp
, int reg
, int value
)
1137 r8168dp_1_mdio_access(tp
, reg
,
1138 OCPDR_WRITE_CMD
| (value
& OCPDR_DATA_MASK
));
1141 static int r8168dp_1_mdio_read(struct rtl8169_private
*tp
, int reg
)
1143 void __iomem
*ioaddr
= tp
->mmio_addr
;
1145 r8168dp_1_mdio_access(tp
, reg
, OCPDR_READ_CMD
);
1148 RTL_W32(OCPAR
, OCPAR_GPHY_READ_CMD
);
1149 RTL_W32(EPHY_RXER_NUM
, 0);
1151 return rtl_udelay_loop_wait_high(tp
, &rtl_ocpar_cond
, 1000, 100) ?
1152 RTL_R32(OCPDR
) & OCPDR_DATA_MASK
: ~0;
1155 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1157 static void r8168dp_2_mdio_start(void __iomem
*ioaddr
)
1159 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT
);
1162 static void r8168dp_2_mdio_stop(void __iomem
*ioaddr
)
1164 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT
);
1167 static void r8168dp_2_mdio_write(struct rtl8169_private
*tp
, int reg
, int value
)
1169 void __iomem
*ioaddr
= tp
->mmio_addr
;
1171 r8168dp_2_mdio_start(ioaddr
);
1173 r8169_mdio_write(tp
, reg
, value
);
1175 r8168dp_2_mdio_stop(ioaddr
);
1178 static int r8168dp_2_mdio_read(struct rtl8169_private
*tp
, int reg
)
1180 void __iomem
*ioaddr
= tp
->mmio_addr
;
1183 r8168dp_2_mdio_start(ioaddr
);
1185 value
= r8169_mdio_read(tp
, reg
);
1187 r8168dp_2_mdio_stop(ioaddr
);
1192 static void rtl_writephy(struct rtl8169_private
*tp
, int location
, u32 val
)
1194 tp
->mdio_ops
.write(tp
, location
, val
);
1197 static int rtl_readphy(struct rtl8169_private
*tp
, int location
)
1199 return tp
->mdio_ops
.read(tp
, location
);
1202 static void rtl_patchphy(struct rtl8169_private
*tp
, int reg_addr
, int value
)
1204 rtl_writephy(tp
, reg_addr
, rtl_readphy(tp
, reg_addr
) | value
);
1207 static void rtl_w0w1_phy(struct rtl8169_private
*tp
, int reg_addr
, int p
, int m
)
1211 val
= rtl_readphy(tp
, reg_addr
);
1212 rtl_writephy(tp
, reg_addr
, (val
& ~m
) | p
);
1215 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
1218 struct rtl8169_private
*tp
= netdev_priv(dev
);
1220 rtl_writephy(tp
, location
, val
);
1223 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
1225 struct rtl8169_private
*tp
= netdev_priv(dev
);
1227 return rtl_readphy(tp
, location
);
1230 DECLARE_RTL_COND(rtl_ephyar_cond
)
1232 void __iomem
*ioaddr
= tp
->mmio_addr
;
1234 return RTL_R32(EPHYAR
) & EPHYAR_FLAG
;
1237 static void rtl_ephy_write(struct rtl8169_private
*tp
, int reg_addr
, int value
)
1239 void __iomem
*ioaddr
= tp
->mmio_addr
;
1241 RTL_W32(EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
1242 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
1244 rtl_udelay_loop_wait_low(tp
, &rtl_ephyar_cond
, 10, 100);
1249 static u16
rtl_ephy_read(struct rtl8169_private
*tp
, int reg_addr
)
1251 void __iomem
*ioaddr
= tp
->mmio_addr
;
1253 RTL_W32(EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
1255 return rtl_udelay_loop_wait_high(tp
, &rtl_ephyar_cond
, 10, 100) ?
1256 RTL_R32(EPHYAR
) & EPHYAR_DATA_MASK
: ~0;
1259 DECLARE_RTL_COND(rtl_eriar_cond
)
1261 void __iomem
*ioaddr
= tp
->mmio_addr
;
1263 return RTL_R32(ERIAR
) & ERIAR_FLAG
;
1266 static void rtl_eri_write(struct rtl8169_private
*tp
, int addr
, u32 mask
,
1269 void __iomem
*ioaddr
= tp
->mmio_addr
;
1271 BUG_ON((addr
& 3) || (mask
== 0));
1272 RTL_W32(ERIDR
, val
);
1273 RTL_W32(ERIAR
, ERIAR_WRITE_CMD
| type
| mask
| addr
);
1275 rtl_udelay_loop_wait_low(tp
, &rtl_eriar_cond
, 100, 100);
1278 static u32
rtl_eri_read(struct rtl8169_private
*tp
, int addr
, int type
)
1280 void __iomem
*ioaddr
= tp
->mmio_addr
;
1282 RTL_W32(ERIAR
, ERIAR_READ_CMD
| type
| ERIAR_MASK_1111
| addr
);
1284 return rtl_udelay_loop_wait_high(tp
, &rtl_eriar_cond
, 100, 100) ?
1285 RTL_R32(ERIDR
) : ~0;
1288 static void rtl_w0w1_eri(struct rtl8169_private
*tp
, int addr
, u32 mask
, u32 p
,
1293 val
= rtl_eri_read(tp
, addr
, type
);
1294 rtl_eri_write(tp
, addr
, mask
, (val
& ~m
) | p
, type
);
1297 static u32
r8168dp_ocp_read(struct rtl8169_private
*tp
, u8 mask
, u16 reg
)
1299 void __iomem
*ioaddr
= tp
->mmio_addr
;
1301 RTL_W32(OCPAR
, ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
1302 return rtl_udelay_loop_wait_high(tp
, &rtl_ocpar_cond
, 100, 20) ?
1303 RTL_R32(OCPDR
) : ~0;
1306 static u32
r8168ep_ocp_read(struct rtl8169_private
*tp
, u8 mask
, u16 reg
)
1308 return rtl_eri_read(tp
, reg
, ERIAR_OOB
);
1311 static u32
ocp_read(struct rtl8169_private
*tp
, u8 mask
, u16 reg
)
1313 switch (tp
->mac_version
) {
1314 case RTL_GIGA_MAC_VER_27
:
1315 case RTL_GIGA_MAC_VER_28
:
1316 case RTL_GIGA_MAC_VER_31
:
1317 return r8168dp_ocp_read(tp
, mask
, reg
);
1318 case RTL_GIGA_MAC_VER_49
:
1319 case RTL_GIGA_MAC_VER_50
:
1320 case RTL_GIGA_MAC_VER_51
:
1321 return r8168ep_ocp_read(tp
, mask
, reg
);
1328 static void r8168dp_ocp_write(struct rtl8169_private
*tp
, u8 mask
, u16 reg
,
1331 void __iomem
*ioaddr
= tp
->mmio_addr
;
1333 RTL_W32(OCPDR
, data
);
1334 RTL_W32(OCPAR
, OCPAR_FLAG
| ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
1335 rtl_udelay_loop_wait_low(tp
, &rtl_ocpar_cond
, 100, 20);
1338 static void r8168ep_ocp_write(struct rtl8169_private
*tp
, u8 mask
, u16 reg
,
1341 rtl_eri_write(tp
, reg
, ((u32
)mask
& 0x0f) << ERIAR_MASK_SHIFT
,
1345 static void ocp_write(struct rtl8169_private
*tp
, u8 mask
, u16 reg
, u32 data
)
1347 switch (tp
->mac_version
) {
1348 case RTL_GIGA_MAC_VER_27
:
1349 case RTL_GIGA_MAC_VER_28
:
1350 case RTL_GIGA_MAC_VER_31
:
1351 r8168dp_ocp_write(tp
, mask
, reg
, data
);
1353 case RTL_GIGA_MAC_VER_49
:
1354 case RTL_GIGA_MAC_VER_50
:
1355 case RTL_GIGA_MAC_VER_51
:
1356 r8168ep_ocp_write(tp
, mask
, reg
, data
);
1364 static void rtl8168_oob_notify(struct rtl8169_private
*tp
, u8 cmd
)
1366 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_0001
, cmd
, ERIAR_EXGMAC
);
1368 ocp_write(tp
, 0x1, 0x30, 0x00000001);
1371 #define OOB_CMD_RESET 0x00
1372 #define OOB_CMD_DRIVER_START 0x05
1373 #define OOB_CMD_DRIVER_STOP 0x06
1375 static u16
rtl8168_get_ocp_reg(struct rtl8169_private
*tp
)
1377 return (tp
->mac_version
== RTL_GIGA_MAC_VER_31
) ? 0xb8 : 0x10;
1380 DECLARE_RTL_COND(rtl_ocp_read_cond
)
1384 reg
= rtl8168_get_ocp_reg(tp
);
1386 return ocp_read(tp
, 0x0f, reg
) & 0x00000800;
1389 DECLARE_RTL_COND(rtl_ep_ocp_read_cond
)
1391 return ocp_read(tp
, 0x0f, 0x124) & 0x00000001;
1394 DECLARE_RTL_COND(rtl_ocp_tx_cond
)
1396 void __iomem
*ioaddr
= tp
->mmio_addr
;
1398 return RTL_R8(IBISR0
) & 0x02;
1401 static void rtl8168ep_stop_cmac(struct rtl8169_private
*tp
)
1403 void __iomem
*ioaddr
= tp
->mmio_addr
;
1405 RTL_W8(IBCR2
, RTL_R8(IBCR2
) & ~0x01);
1406 rtl_msleep_loop_wait_low(tp
, &rtl_ocp_tx_cond
, 50, 2000);
1407 RTL_W8(IBISR0
, RTL_R8(IBISR0
) | 0x20);
1408 RTL_W8(IBCR0
, RTL_R8(IBCR0
) & ~0x01);
1411 static void rtl8168dp_driver_start(struct rtl8169_private
*tp
)
1413 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_START
);
1414 rtl_msleep_loop_wait_high(tp
, &rtl_ocp_read_cond
, 10, 10);
1417 static void rtl8168ep_driver_start(struct rtl8169_private
*tp
)
1419 ocp_write(tp
, 0x01, 0x180, OOB_CMD_DRIVER_START
);
1420 ocp_write(tp
, 0x01, 0x30, ocp_read(tp
, 0x01, 0x30) | 0x01);
1421 rtl_msleep_loop_wait_high(tp
, &rtl_ep_ocp_read_cond
, 10, 10);
1424 static void rtl8168_driver_start(struct rtl8169_private
*tp
)
1426 switch (tp
->mac_version
) {
1427 case RTL_GIGA_MAC_VER_27
:
1428 case RTL_GIGA_MAC_VER_28
:
1429 case RTL_GIGA_MAC_VER_31
:
1430 rtl8168dp_driver_start(tp
);
1432 case RTL_GIGA_MAC_VER_49
:
1433 case RTL_GIGA_MAC_VER_50
:
1434 case RTL_GIGA_MAC_VER_51
:
1435 rtl8168ep_driver_start(tp
);
1443 static void rtl8168dp_driver_stop(struct rtl8169_private
*tp
)
1445 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_STOP
);
1446 rtl_msleep_loop_wait_low(tp
, &rtl_ocp_read_cond
, 10, 10);
1449 static void rtl8168ep_driver_stop(struct rtl8169_private
*tp
)
1451 rtl8168ep_stop_cmac(tp
);
1452 ocp_write(tp
, 0x01, 0x180, OOB_CMD_DRIVER_STOP
);
1453 ocp_write(tp
, 0x01, 0x30, ocp_read(tp
, 0x01, 0x30) | 0x01);
1454 rtl_msleep_loop_wait_low(tp
, &rtl_ep_ocp_read_cond
, 10, 10);
1457 static void rtl8168_driver_stop(struct rtl8169_private
*tp
)
1459 switch (tp
->mac_version
) {
1460 case RTL_GIGA_MAC_VER_27
:
1461 case RTL_GIGA_MAC_VER_28
:
1462 case RTL_GIGA_MAC_VER_31
:
1463 rtl8168dp_driver_stop(tp
);
1465 case RTL_GIGA_MAC_VER_49
:
1466 case RTL_GIGA_MAC_VER_50
:
1467 case RTL_GIGA_MAC_VER_51
:
1468 rtl8168ep_driver_stop(tp
);
1476 static int r8168dp_check_dash(struct rtl8169_private
*tp
)
1478 u16 reg
= rtl8168_get_ocp_reg(tp
);
1480 return (ocp_read(tp
, 0x0f, reg
) & 0x00008000) ? 1 : 0;
1483 static int r8168ep_check_dash(struct rtl8169_private
*tp
)
1485 return (ocp_read(tp
, 0x0f, 0x128) & 0x00000001) ? 1 : 0;
1488 static int r8168_check_dash(struct rtl8169_private
*tp
)
1490 switch (tp
->mac_version
) {
1491 case RTL_GIGA_MAC_VER_27
:
1492 case RTL_GIGA_MAC_VER_28
:
1493 case RTL_GIGA_MAC_VER_31
:
1494 return r8168dp_check_dash(tp
);
1495 case RTL_GIGA_MAC_VER_49
:
1496 case RTL_GIGA_MAC_VER_50
:
1497 case RTL_GIGA_MAC_VER_51
:
1498 return r8168ep_check_dash(tp
);
1510 static void rtl_write_exgmac_batch(struct rtl8169_private
*tp
,
1511 const struct exgmac_reg
*r
, int len
)
1514 rtl_eri_write(tp
, r
->addr
, r
->mask
, r
->val
, ERIAR_EXGMAC
);
1519 DECLARE_RTL_COND(rtl_efusear_cond
)
1521 void __iomem
*ioaddr
= tp
->mmio_addr
;
1523 return RTL_R32(EFUSEAR
) & EFUSEAR_FLAG
;
1526 static u8
rtl8168d_efuse_read(struct rtl8169_private
*tp
, int reg_addr
)
1528 void __iomem
*ioaddr
= tp
->mmio_addr
;
1530 RTL_W32(EFUSEAR
, (reg_addr
& EFUSEAR_REG_MASK
) << EFUSEAR_REG_SHIFT
);
1532 return rtl_udelay_loop_wait_high(tp
, &rtl_efusear_cond
, 100, 300) ?
1533 RTL_R32(EFUSEAR
) & EFUSEAR_DATA_MASK
: ~0;
1536 static u16
rtl_get_events(struct rtl8169_private
*tp
)
1538 void __iomem
*ioaddr
= tp
->mmio_addr
;
1540 return RTL_R16(IntrStatus
);
1543 static void rtl_ack_events(struct rtl8169_private
*tp
, u16 bits
)
1545 void __iomem
*ioaddr
= tp
->mmio_addr
;
1547 RTL_W16(IntrStatus
, bits
);
1551 static void rtl_irq_disable(struct rtl8169_private
*tp
)
1553 void __iomem
*ioaddr
= tp
->mmio_addr
;
1555 RTL_W16(IntrMask
, 0);
1559 static void rtl_irq_enable(struct rtl8169_private
*tp
, u16 bits
)
1561 void __iomem
*ioaddr
= tp
->mmio_addr
;
1563 RTL_W16(IntrMask
, bits
);
1566 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1567 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1568 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1570 static void rtl_irq_enable_all(struct rtl8169_private
*tp
)
1572 rtl_irq_enable(tp
, RTL_EVENT_NAPI
| tp
->event_slow
);
1575 static void rtl8169_irq_mask_and_ack(struct rtl8169_private
*tp
)
1577 void __iomem
*ioaddr
= tp
->mmio_addr
;
1579 rtl_irq_disable(tp
);
1580 rtl_ack_events(tp
, RTL_EVENT_NAPI
| tp
->event_slow
);
1584 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private
*tp
)
1586 void __iomem
*ioaddr
= tp
->mmio_addr
;
1588 return RTL_R32(TBICSR
) & TBIReset
;
1591 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private
*tp
)
1593 return rtl_readphy(tp
, MII_BMCR
) & BMCR_RESET
;
1596 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
1598 return RTL_R32(TBICSR
) & TBILinkOk
;
1601 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
1603 return RTL_R8(PHYstatus
) & LinkStatus
;
1606 static void rtl8169_tbi_reset_enable(struct rtl8169_private
*tp
)
1608 void __iomem
*ioaddr
= tp
->mmio_addr
;
1610 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
1613 static void rtl8169_xmii_reset_enable(struct rtl8169_private
*tp
)
1617 val
= rtl_readphy(tp
, MII_BMCR
) | BMCR_RESET
;
1618 rtl_writephy(tp
, MII_BMCR
, val
& 0xffff);
1621 static void rtl_link_chg_patch(struct rtl8169_private
*tp
)
1623 void __iomem
*ioaddr
= tp
->mmio_addr
;
1624 struct net_device
*dev
= tp
->dev
;
1626 if (!netif_running(dev
))
1629 if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
||
1630 tp
->mac_version
== RTL_GIGA_MAC_VER_38
) {
1631 if (RTL_R8(PHYstatus
) & _1000bpsF
) {
1632 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x00000011,
1634 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x00000005,
1636 } else if (RTL_R8(PHYstatus
) & _100bps
) {
1637 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x0000001f,
1639 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x00000005,
1642 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x0000001f,
1644 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x0000003f,
1647 /* Reset packet filter */
1648 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01,
1650 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00,
1652 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_35
||
1653 tp
->mac_version
== RTL_GIGA_MAC_VER_36
) {
1654 if (RTL_R8(PHYstatus
) & _1000bpsF
) {
1655 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x00000011,
1657 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x00000005,
1660 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x0000001f,
1662 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x0000003f,
1665 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_37
) {
1666 if (RTL_R8(PHYstatus
) & _10bps
) {
1667 rtl_eri_write(tp
, 0x1d0, ERIAR_MASK_0011
, 0x4d02,
1669 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_0011
, 0x0060,
1672 rtl_eri_write(tp
, 0x1d0, ERIAR_MASK_0011
, 0x0000,
1678 static void __rtl8169_check_link_status(struct net_device
*dev
,
1679 struct rtl8169_private
*tp
,
1680 void __iomem
*ioaddr
, bool pm
)
1682 if (tp
->link_ok(ioaddr
)) {
1683 rtl_link_chg_patch(tp
);
1684 /* This is to cancel a scheduled suspend if there's one. */
1686 pm_request_resume(&tp
->pci_dev
->dev
);
1687 netif_carrier_on(dev
);
1688 if (net_ratelimit())
1689 netif_info(tp
, ifup
, dev
, "link up\n");
1691 netif_carrier_off(dev
);
1692 netif_info(tp
, ifdown
, dev
, "link down\n");
1694 pm_schedule_suspend(&tp
->pci_dev
->dev
, 5000);
1698 static void rtl8169_check_link_status(struct net_device
*dev
,
1699 struct rtl8169_private
*tp
,
1700 void __iomem
*ioaddr
)
1702 __rtl8169_check_link_status(dev
, tp
, ioaddr
, false);
1705 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1707 static u32
__rtl8169_get_wol(struct rtl8169_private
*tp
)
1709 void __iomem
*ioaddr
= tp
->mmio_addr
;
1713 options
= RTL_R8(Config1
);
1714 if (!(options
& PMEnable
))
1717 options
= RTL_R8(Config3
);
1718 if (options
& LinkUp
)
1719 wolopts
|= WAKE_PHY
;
1720 switch (tp
->mac_version
) {
1721 case RTL_GIGA_MAC_VER_34
:
1722 case RTL_GIGA_MAC_VER_35
:
1723 case RTL_GIGA_MAC_VER_36
:
1724 case RTL_GIGA_MAC_VER_37
:
1725 case RTL_GIGA_MAC_VER_38
:
1726 case RTL_GIGA_MAC_VER_40
:
1727 case RTL_GIGA_MAC_VER_41
:
1728 case RTL_GIGA_MAC_VER_42
:
1729 case RTL_GIGA_MAC_VER_43
:
1730 case RTL_GIGA_MAC_VER_44
:
1731 case RTL_GIGA_MAC_VER_45
:
1732 case RTL_GIGA_MAC_VER_46
:
1733 case RTL_GIGA_MAC_VER_47
:
1734 case RTL_GIGA_MAC_VER_48
:
1735 case RTL_GIGA_MAC_VER_49
:
1736 case RTL_GIGA_MAC_VER_50
:
1737 case RTL_GIGA_MAC_VER_51
:
1738 if (rtl_eri_read(tp
, 0xdc, ERIAR_EXGMAC
) & MagicPacket_v2
)
1739 wolopts
|= WAKE_MAGIC
;
1742 if (options
& MagicPacket
)
1743 wolopts
|= WAKE_MAGIC
;
1747 options
= RTL_R8(Config5
);
1749 wolopts
|= WAKE_UCAST
;
1751 wolopts
|= WAKE_BCAST
;
1753 wolopts
|= WAKE_MCAST
;
1758 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1760 struct rtl8169_private
*tp
= netdev_priv(dev
);
1761 struct device
*d
= &tp
->pci_dev
->dev
;
1763 pm_runtime_get_noresume(d
);
1767 wol
->supported
= WAKE_ANY
;
1768 if (pm_runtime_active(d
))
1769 wol
->wolopts
= __rtl8169_get_wol(tp
);
1771 wol
->wolopts
= tp
->saved_wolopts
;
1773 rtl_unlock_work(tp
);
1775 pm_runtime_put_noidle(d
);
1778 static void __rtl8169_set_wol(struct rtl8169_private
*tp
, u32 wolopts
)
1780 void __iomem
*ioaddr
= tp
->mmio_addr
;
1781 unsigned int i
, tmp
;
1782 static const struct {
1787 { WAKE_PHY
, Config3
, LinkUp
},
1788 { WAKE_UCAST
, Config5
, UWF
},
1789 { WAKE_BCAST
, Config5
, BWF
},
1790 { WAKE_MCAST
, Config5
, MWF
},
1791 { WAKE_ANY
, Config5
, LanWake
},
1792 { WAKE_MAGIC
, Config3
, MagicPacket
}
1796 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1798 switch (tp
->mac_version
) {
1799 case RTL_GIGA_MAC_VER_34
:
1800 case RTL_GIGA_MAC_VER_35
:
1801 case RTL_GIGA_MAC_VER_36
:
1802 case RTL_GIGA_MAC_VER_37
:
1803 case RTL_GIGA_MAC_VER_38
:
1804 case RTL_GIGA_MAC_VER_40
:
1805 case RTL_GIGA_MAC_VER_41
:
1806 case RTL_GIGA_MAC_VER_42
:
1807 case RTL_GIGA_MAC_VER_43
:
1808 case RTL_GIGA_MAC_VER_44
:
1809 case RTL_GIGA_MAC_VER_45
:
1810 case RTL_GIGA_MAC_VER_46
:
1811 case RTL_GIGA_MAC_VER_47
:
1812 case RTL_GIGA_MAC_VER_48
:
1813 case RTL_GIGA_MAC_VER_49
:
1814 case RTL_GIGA_MAC_VER_50
:
1815 case RTL_GIGA_MAC_VER_51
:
1816 tmp
= ARRAY_SIZE(cfg
) - 1;
1817 if (wolopts
& WAKE_MAGIC
)
1833 tmp
= ARRAY_SIZE(cfg
);
1837 for (i
= 0; i
< tmp
; i
++) {
1838 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
1839 if (wolopts
& cfg
[i
].opt
)
1840 options
|= cfg
[i
].mask
;
1841 RTL_W8(cfg
[i
].reg
, options
);
1844 switch (tp
->mac_version
) {
1845 case RTL_GIGA_MAC_VER_01
... RTL_GIGA_MAC_VER_17
:
1846 options
= RTL_R8(Config1
) & ~PMEnable
;
1848 options
|= PMEnable
;
1849 RTL_W8(Config1
, options
);
1852 options
= RTL_R8(Config2
) & ~PME_SIGNAL
;
1854 options
|= PME_SIGNAL
;
1855 RTL_W8(Config2
, options
);
1859 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1862 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1864 struct rtl8169_private
*tp
= netdev_priv(dev
);
1865 struct device
*d
= &tp
->pci_dev
->dev
;
1867 pm_runtime_get_noresume(d
);
1872 tp
->features
|= RTL_FEATURE_WOL
;
1874 tp
->features
&= ~RTL_FEATURE_WOL
;
1875 if (pm_runtime_active(d
))
1876 __rtl8169_set_wol(tp
, wol
->wolopts
);
1878 tp
->saved_wolopts
= wol
->wolopts
;
1880 rtl_unlock_work(tp
);
1882 device_set_wakeup_enable(&tp
->pci_dev
->dev
, wol
->wolopts
);
1884 pm_runtime_put_noidle(d
);
1889 static const char *rtl_lookup_firmware_name(struct rtl8169_private
*tp
)
1891 return rtl_chip_infos
[tp
->mac_version
].fw_name
;
1894 static void rtl8169_get_drvinfo(struct net_device
*dev
,
1895 struct ethtool_drvinfo
*info
)
1897 struct rtl8169_private
*tp
= netdev_priv(dev
);
1898 struct rtl_fw
*rtl_fw
= tp
->rtl_fw
;
1900 strlcpy(info
->driver
, MODULENAME
, sizeof(info
->driver
));
1901 strlcpy(info
->version
, RTL8169_VERSION
, sizeof(info
->version
));
1902 strlcpy(info
->bus_info
, pci_name(tp
->pci_dev
), sizeof(info
->bus_info
));
1903 BUILD_BUG_ON(sizeof(info
->fw_version
) < sizeof(rtl_fw
->version
));
1904 if (!IS_ERR_OR_NULL(rtl_fw
))
1905 strlcpy(info
->fw_version
, rtl_fw
->version
,
1906 sizeof(info
->fw_version
));
1909 static int rtl8169_get_regs_len(struct net_device
*dev
)
1911 return R8169_REGS_SIZE
;
1914 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
1915 u8 autoneg
, u16 speed
, u8 duplex
, u32 ignored
)
1917 struct rtl8169_private
*tp
= netdev_priv(dev
);
1918 void __iomem
*ioaddr
= tp
->mmio_addr
;
1922 reg
= RTL_R32(TBICSR
);
1923 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
1924 (duplex
== DUPLEX_FULL
)) {
1925 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
1926 } else if (autoneg
== AUTONEG_ENABLE
)
1927 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
1929 netif_warn(tp
, link
, dev
,
1930 "incorrect speed setting refused in TBI mode\n");
1937 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
1938 u8 autoneg
, u16 speed
, u8 duplex
, u32 adv
)
1940 struct rtl8169_private
*tp
= netdev_priv(dev
);
1941 int giga_ctrl
, bmcr
;
1944 rtl_writephy(tp
, 0x1f, 0x0000);
1946 if (autoneg
== AUTONEG_ENABLE
) {
1949 auto_nego
= rtl_readphy(tp
, MII_ADVERTISE
);
1950 auto_nego
&= ~(ADVERTISE_10HALF
| ADVERTISE_10FULL
|
1951 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
1953 if (adv
& ADVERTISED_10baseT_Half
)
1954 auto_nego
|= ADVERTISE_10HALF
;
1955 if (adv
& ADVERTISED_10baseT_Full
)
1956 auto_nego
|= ADVERTISE_10FULL
;
1957 if (adv
& ADVERTISED_100baseT_Half
)
1958 auto_nego
|= ADVERTISE_100HALF
;
1959 if (adv
& ADVERTISED_100baseT_Full
)
1960 auto_nego
|= ADVERTISE_100FULL
;
1962 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
1964 giga_ctrl
= rtl_readphy(tp
, MII_CTRL1000
);
1965 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
1967 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1968 if (tp
->mii
.supports_gmii
) {
1969 if (adv
& ADVERTISED_1000baseT_Half
)
1970 giga_ctrl
|= ADVERTISE_1000HALF
;
1971 if (adv
& ADVERTISED_1000baseT_Full
)
1972 giga_ctrl
|= ADVERTISE_1000FULL
;
1973 } else if (adv
& (ADVERTISED_1000baseT_Half
|
1974 ADVERTISED_1000baseT_Full
)) {
1975 netif_info(tp
, link
, dev
,
1976 "PHY does not support 1000Mbps\n");
1980 bmcr
= BMCR_ANENABLE
| BMCR_ANRESTART
;
1982 rtl_writephy(tp
, MII_ADVERTISE
, auto_nego
);
1983 rtl_writephy(tp
, MII_CTRL1000
, giga_ctrl
);
1985 if (speed
== SPEED_10
)
1987 else if (speed
== SPEED_100
)
1988 bmcr
= BMCR_SPEED100
;
1992 if (duplex
== DUPLEX_FULL
)
1993 bmcr
|= BMCR_FULLDPLX
;
1996 rtl_writephy(tp
, MII_BMCR
, bmcr
);
1998 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
1999 tp
->mac_version
== RTL_GIGA_MAC_VER_03
) {
2000 if ((speed
== SPEED_100
) && (autoneg
!= AUTONEG_ENABLE
)) {
2001 rtl_writephy(tp
, 0x17, 0x2138);
2002 rtl_writephy(tp
, 0x0e, 0x0260);
2004 rtl_writephy(tp
, 0x17, 0x2108);
2005 rtl_writephy(tp
, 0x0e, 0x0000);
2014 static int rtl8169_set_speed(struct net_device
*dev
,
2015 u8 autoneg
, u16 speed
, u8 duplex
, u32 advertising
)
2017 struct rtl8169_private
*tp
= netdev_priv(dev
);
2020 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
, advertising
);
2024 if (netif_running(dev
) && (autoneg
== AUTONEG_ENABLE
) &&
2025 (advertising
& ADVERTISED_1000baseT_Full
) &&
2026 !pci_is_pcie(tp
->pci_dev
)) {
2027 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
2033 static netdev_features_t
rtl8169_fix_features(struct net_device
*dev
,
2034 netdev_features_t features
)
2036 struct rtl8169_private
*tp
= netdev_priv(dev
);
2038 if (dev
->mtu
> TD_MSS_MAX
)
2039 features
&= ~NETIF_F_ALL_TSO
;
2041 if (dev
->mtu
> JUMBO_1K
&&
2042 !rtl_chip_infos
[tp
->mac_version
].jumbo_tx_csum
)
2043 features
&= ~NETIF_F_IP_CSUM
;
2048 static void __rtl8169_set_features(struct net_device
*dev
,
2049 netdev_features_t features
)
2051 struct rtl8169_private
*tp
= netdev_priv(dev
);
2052 void __iomem
*ioaddr
= tp
->mmio_addr
;
2055 rx_config
= RTL_R32(RxConfig
);
2056 if (features
& NETIF_F_RXALL
)
2057 rx_config
|= (AcceptErr
| AcceptRunt
);
2059 rx_config
&= ~(AcceptErr
| AcceptRunt
);
2061 RTL_W32(RxConfig
, rx_config
);
2063 if (features
& NETIF_F_RXCSUM
)
2064 tp
->cp_cmd
|= RxChkSum
;
2066 tp
->cp_cmd
&= ~RxChkSum
;
2068 if (features
& NETIF_F_HW_VLAN_CTAG_RX
)
2069 tp
->cp_cmd
|= RxVlan
;
2071 tp
->cp_cmd
&= ~RxVlan
;
2073 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) & ~(RxVlan
| RxChkSum
);
2075 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2079 static int rtl8169_set_features(struct net_device
*dev
,
2080 netdev_features_t features
)
2082 struct rtl8169_private
*tp
= netdev_priv(dev
);
2084 features
&= NETIF_F_RXALL
| NETIF_F_RXCSUM
| NETIF_F_HW_VLAN_CTAG_RX
;
2087 if (features
^ dev
->features
)
2088 __rtl8169_set_features(dev
, features
);
2089 rtl_unlock_work(tp
);
2095 static inline u32
rtl8169_tx_vlan_tag(struct sk_buff
*skb
)
2097 return (skb_vlan_tag_present(skb
)) ?
2098 TxVlanTag
| swab16(skb_vlan_tag_get(skb
)) : 0x00;
2101 static void rtl8169_rx_vlan_tag(struct RxDesc
*desc
, struct sk_buff
*skb
)
2103 u32 opts2
= le32_to_cpu(desc
->opts2
);
2105 if (opts2
& RxVlanTag
)
2106 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
), swab16(opts2
& 0xffff));
2109 static int rtl8169_get_link_ksettings_tbi(struct net_device
*dev
,
2110 struct ethtool_link_ksettings
*cmd
)
2112 struct rtl8169_private
*tp
= netdev_priv(dev
);
2113 void __iomem
*ioaddr
= tp
->mmio_addr
;
2115 u32 supported
, advertising
;
2118 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
2119 cmd
->base
.port
= PORT_FIBRE
;
2121 status
= RTL_R32(TBICSR
);
2122 advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
2123 cmd
->base
.autoneg
= !!(status
& TBINwEnable
);
2125 cmd
->base
.speed
= SPEED_1000
;
2126 cmd
->base
.duplex
= DUPLEX_FULL
; /* Always set */
2128 ethtool_convert_legacy_u32_to_link_mode(cmd
->link_modes
.supported
,
2130 ethtool_convert_legacy_u32_to_link_mode(cmd
->link_modes
.advertising
,
2136 static int rtl8169_get_link_ksettings_xmii(struct net_device
*dev
,
2137 struct ethtool_link_ksettings
*cmd
)
2139 struct rtl8169_private
*tp
= netdev_priv(dev
);
2141 mii_ethtool_get_link_ksettings(&tp
->mii
, cmd
);
2146 static int rtl8169_get_link_ksettings(struct net_device
*dev
,
2147 struct ethtool_link_ksettings
*cmd
)
2149 struct rtl8169_private
*tp
= netdev_priv(dev
);
2153 rc
= tp
->get_link_ksettings(dev
, cmd
);
2154 rtl_unlock_work(tp
);
2159 static int rtl8169_set_link_ksettings(struct net_device
*dev
,
2160 const struct ethtool_link_ksettings
*cmd
)
2162 struct rtl8169_private
*tp
= netdev_priv(dev
);
2166 if (!ethtool_convert_link_mode_to_legacy_u32(&advertising
,
2167 cmd
->link_modes
.advertising
))
2170 del_timer_sync(&tp
->timer
);
2173 rc
= rtl8169_set_speed(dev
, cmd
->base
.autoneg
, cmd
->base
.speed
,
2174 cmd
->base
.duplex
, advertising
);
2175 rtl_unlock_work(tp
);
2180 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
2183 struct rtl8169_private
*tp
= netdev_priv(dev
);
2184 u32 __iomem
*data
= tp
->mmio_addr
;
2189 for (i
= 0; i
< R8169_REGS_SIZE
; i
+= 4)
2190 memcpy_fromio(dw
++, data
++, 4);
2191 rtl_unlock_work(tp
);
2194 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
2196 struct rtl8169_private
*tp
= netdev_priv(dev
);
2198 return tp
->msg_enable
;
2201 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
2203 struct rtl8169_private
*tp
= netdev_priv(dev
);
2205 tp
->msg_enable
= value
;
2208 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
2215 "tx_single_collisions",
2216 "tx_multi_collisions",
2224 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
2228 return ARRAY_SIZE(rtl8169_gstrings
);
2234 DECLARE_RTL_COND(rtl_counters_cond
)
2236 void __iomem
*ioaddr
= tp
->mmio_addr
;
2238 return RTL_R32(CounterAddrLow
) & (CounterReset
| CounterDump
);
2241 static bool rtl8169_do_counters(struct net_device
*dev
, u32 counter_cmd
)
2243 struct rtl8169_private
*tp
= netdev_priv(dev
);
2244 void __iomem
*ioaddr
= tp
->mmio_addr
;
2245 dma_addr_t paddr
= tp
->counters_phys_addr
;
2249 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
2250 cmd
= (u64
)paddr
& DMA_BIT_MASK(32);
2251 RTL_W32(CounterAddrLow
, cmd
);
2252 RTL_W32(CounterAddrLow
, cmd
| counter_cmd
);
2254 ret
= rtl_udelay_loop_wait_low(tp
, &rtl_counters_cond
, 10, 1000);
2256 RTL_W32(CounterAddrLow
, 0);
2257 RTL_W32(CounterAddrHigh
, 0);
2262 static bool rtl8169_reset_counters(struct net_device
*dev
)
2264 struct rtl8169_private
*tp
= netdev_priv(dev
);
2267 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
2270 if (tp
->mac_version
< RTL_GIGA_MAC_VER_19
)
2273 return rtl8169_do_counters(dev
, CounterReset
);
2276 static bool rtl8169_update_counters(struct net_device
*dev
)
2278 struct rtl8169_private
*tp
= netdev_priv(dev
);
2279 void __iomem
*ioaddr
= tp
->mmio_addr
;
2282 * Some chips are unable to dump tally counters when the receiver
2285 if ((RTL_R8(ChipCmd
) & CmdRxEnb
) == 0)
2288 return rtl8169_do_counters(dev
, CounterDump
);
2291 static bool rtl8169_init_counter_offsets(struct net_device
*dev
)
2293 struct rtl8169_private
*tp
= netdev_priv(dev
);
2294 struct rtl8169_counters
*counters
= tp
->counters
;
2298 * rtl8169_init_counter_offsets is called from rtl_open. On chip
2299 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
2300 * reset by a power cycle, while the counter values collected by the
2301 * driver are reset at every driver unload/load cycle.
2303 * To make sure the HW values returned by @get_stats64 match the SW
2304 * values, we collect the initial values at first open(*) and use them
2305 * as offsets to normalize the values returned by @get_stats64.
2307 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
2308 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
2309 * set at open time by rtl_hw_start.
2312 if (tp
->tc_offset
.inited
)
2315 /* If both, reset and update fail, propagate to caller. */
2316 if (rtl8169_reset_counters(dev
))
2319 if (rtl8169_update_counters(dev
))
2322 tp
->tc_offset
.tx_errors
= counters
->tx_errors
;
2323 tp
->tc_offset
.tx_multi_collision
= counters
->tx_multi_collision
;
2324 tp
->tc_offset
.tx_aborted
= counters
->tx_aborted
;
2325 tp
->tc_offset
.inited
= true;
2330 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
2331 struct ethtool_stats
*stats
, u64
*data
)
2333 struct rtl8169_private
*tp
= netdev_priv(dev
);
2334 struct device
*d
= &tp
->pci_dev
->dev
;
2335 struct rtl8169_counters
*counters
= tp
->counters
;
2339 pm_runtime_get_noresume(d
);
2341 if (pm_runtime_active(d
))
2342 rtl8169_update_counters(dev
);
2344 pm_runtime_put_noidle(d
);
2346 data
[0] = le64_to_cpu(counters
->tx_packets
);
2347 data
[1] = le64_to_cpu(counters
->rx_packets
);
2348 data
[2] = le64_to_cpu(counters
->tx_errors
);
2349 data
[3] = le32_to_cpu(counters
->rx_errors
);
2350 data
[4] = le16_to_cpu(counters
->rx_missed
);
2351 data
[5] = le16_to_cpu(counters
->align_errors
);
2352 data
[6] = le32_to_cpu(counters
->tx_one_collision
);
2353 data
[7] = le32_to_cpu(counters
->tx_multi_collision
);
2354 data
[8] = le64_to_cpu(counters
->rx_unicast
);
2355 data
[9] = le64_to_cpu(counters
->rx_broadcast
);
2356 data
[10] = le32_to_cpu(counters
->rx_multicast
);
2357 data
[11] = le16_to_cpu(counters
->tx_aborted
);
2358 data
[12] = le16_to_cpu(counters
->tx_underun
);
2361 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
2365 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
2370 static int rtl8169_nway_reset(struct net_device
*dev
)
2372 struct rtl8169_private
*tp
= netdev_priv(dev
);
2374 return mii_nway_restart(&tp
->mii
);
2378 * Interrupt coalescing
2380 * > 1 - the availability of the IntrMitigate (0xe2) register through the
2381 * > 8169, 8168 and 810x line of chipsets
2383 * 8169, 8168, and 8136(810x) serial chipsets support it.
2385 * > 2 - the Tx timer unit at gigabit speed
2387 * The unit of the timer depends on both the speed and the setting of CPlusCmd
2388 * (0xe0) bit 1 and bit 0.
2391 * bit[1:0] \ speed 1000M 100M 10M
2392 * 0 0 320ns 2.56us 40.96us
2393 * 0 1 2.56us 20.48us 327.7us
2394 * 1 0 5.12us 40.96us 655.4us
2395 * 1 1 10.24us 81.92us 1.31ms
2398 * bit[1:0] \ speed 1000M 100M 10M
2399 * 0 0 5us 2.56us 40.96us
2400 * 0 1 40us 20.48us 327.7us
2401 * 1 0 80us 40.96us 655.4us
2402 * 1 1 160us 81.92us 1.31ms
2405 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
2406 struct rtl_coalesce_scale
{
2411 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
2412 struct rtl_coalesce_info
{
2414 struct rtl_coalesce_scale scalev
[4]; /* each CPlusCmd[0:1] case */
2417 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
2418 #define rxtx_x1822(r, t) { \
2421 {{(r)*8*2, (t)*8*2}}, \
2422 {{(r)*8*2*2, (t)*8*2*2}}, \
2424 static const struct rtl_coalesce_info rtl_coalesce_info_8169
[] = {
2425 /* speed delays: rx00 tx00 */
2426 { SPEED_10
, rxtx_x1822(40960, 40960) },
2427 { SPEED_100
, rxtx_x1822( 2560, 2560) },
2428 { SPEED_1000
, rxtx_x1822( 320, 320) },
2432 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136
[] = {
2433 /* speed delays: rx00 tx00 */
2434 { SPEED_10
, rxtx_x1822(40960, 40960) },
2435 { SPEED_100
, rxtx_x1822( 2560, 2560) },
2436 { SPEED_1000
, rxtx_x1822( 5000, 5000) },
2441 /* get rx/tx scale vector corresponding to current speed */
2442 static const struct rtl_coalesce_info
*rtl_coalesce_info(struct net_device
*dev
)
2444 struct rtl8169_private
*tp
= netdev_priv(dev
);
2445 struct ethtool_link_ksettings ecmd
;
2446 const struct rtl_coalesce_info
*ci
;
2449 rc
= rtl8169_get_link_ksettings(dev
, &ecmd
);
2453 for (ci
= tp
->coalesce_info
; ci
->speed
!= 0; ci
++) {
2454 if (ecmd
.base
.speed
== ci
->speed
) {
2459 return ERR_PTR(-ELNRNG
);
2462 static int rtl_get_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
2464 struct rtl8169_private
*tp
= netdev_priv(dev
);
2465 void __iomem
*ioaddr
= tp
->mmio_addr
;
2466 const struct rtl_coalesce_info
*ci
;
2467 const struct rtl_coalesce_scale
*scale
;
2471 } coal_settings
[] = {
2472 { &ec
->rx_max_coalesced_frames
, &ec
->rx_coalesce_usecs
},
2473 { &ec
->tx_max_coalesced_frames
, &ec
->tx_coalesce_usecs
}
2474 }, *p
= coal_settings
;
2478 memset(ec
, 0, sizeof(*ec
));
2480 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
2481 ci
= rtl_coalesce_info(dev
);
2485 scale
= &ci
->scalev
[RTL_R16(CPlusCmd
) & 3];
2487 /* read IntrMitigate and adjust according to scale */
2488 for (w
= RTL_R16(IntrMitigate
); w
; w
>>= RTL_COALESCE_SHIFT
, p
++) {
2489 *p
->max_frames
= (w
& RTL_COALESCE_MASK
) << 2;
2490 w
>>= RTL_COALESCE_SHIFT
;
2491 *p
->usecs
= w
& RTL_COALESCE_MASK
;
2494 for (i
= 0; i
< 2; i
++) {
2495 p
= coal_settings
+ i
;
2496 *p
->usecs
= (*p
->usecs
* scale
->nsecs
[i
]) / 1000;
2499 * ethtool_coalesce says it is illegal to set both usecs and
2502 if (!*p
->usecs
&& !*p
->max_frames
)
2509 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
2510 static const struct rtl_coalesce_scale
*rtl_coalesce_choose_scale(
2511 struct net_device
*dev
, u32 nsec
, u16
*cp01
)
2513 const struct rtl_coalesce_info
*ci
;
2516 ci
= rtl_coalesce_info(dev
);
2518 return ERR_CAST(ci
);
2520 for (i
= 0; i
< 4; i
++) {
2521 u32 rxtx_maxscale
= max(ci
->scalev
[i
].nsecs
[0],
2522 ci
->scalev
[i
].nsecs
[1]);
2523 if (nsec
<= rxtx_maxscale
* RTL_COALESCE_T_MAX
) {
2525 return &ci
->scalev
[i
];
2529 return ERR_PTR(-EINVAL
);
2532 static int rtl_set_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
2534 struct rtl8169_private
*tp
= netdev_priv(dev
);
2535 void __iomem
*ioaddr
= tp
->mmio_addr
;
2536 const struct rtl_coalesce_scale
*scale
;
2540 } coal_settings
[] = {
2541 { ec
->rx_max_coalesced_frames
, ec
->rx_coalesce_usecs
},
2542 { ec
->tx_max_coalesced_frames
, ec
->tx_coalesce_usecs
}
2543 }, *p
= coal_settings
;
2547 scale
= rtl_coalesce_choose_scale(dev
,
2548 max(p
[0].usecs
, p
[1].usecs
) * 1000, &cp01
);
2550 return PTR_ERR(scale
);
2552 for (i
= 0; i
< 2; i
++, p
++) {
2556 * accept max_frames=1 we returned in rtl_get_coalesce.
2557 * accept it not only when usecs=0 because of e.g. the following scenario:
2559 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2560 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2561 * - then user does `ethtool -C eth0 rx-usecs 100`
2563 * since ethtool sends to kernel whole ethtool_coalesce
2564 * settings, if we do not handle rx_usecs=!0, rx_frames=1
2565 * we'll reject it below in `frames % 4 != 0`.
2567 if (p
->frames
== 1) {
2571 units
= p
->usecs
* 1000 / scale
->nsecs
[i
];
2572 if (p
->frames
> RTL_COALESCE_FRAME_MAX
|| p
->frames
% 4)
2575 w
<<= RTL_COALESCE_SHIFT
;
2577 w
<<= RTL_COALESCE_SHIFT
;
2578 w
|= p
->frames
>> 2;
2583 RTL_W16(IntrMitigate
, swab16(w
));
2585 tp
->cp_cmd
= (tp
->cp_cmd
& ~3) | cp01
;
2586 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2589 rtl_unlock_work(tp
);
2594 static const struct ethtool_ops rtl8169_ethtool_ops
= {
2595 .get_drvinfo
= rtl8169_get_drvinfo
,
2596 .get_regs_len
= rtl8169_get_regs_len
,
2597 .get_link
= ethtool_op_get_link
,
2598 .get_coalesce
= rtl_get_coalesce
,
2599 .set_coalesce
= rtl_set_coalesce
,
2600 .get_msglevel
= rtl8169_get_msglevel
,
2601 .set_msglevel
= rtl8169_set_msglevel
,
2602 .get_regs
= rtl8169_get_regs
,
2603 .get_wol
= rtl8169_get_wol
,
2604 .set_wol
= rtl8169_set_wol
,
2605 .get_strings
= rtl8169_get_strings
,
2606 .get_sset_count
= rtl8169_get_sset_count
,
2607 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
2608 .get_ts_info
= ethtool_op_get_ts_info
,
2609 .nway_reset
= rtl8169_nway_reset
,
2610 .get_link_ksettings
= rtl8169_get_link_ksettings
,
2611 .set_link_ksettings
= rtl8169_set_link_ksettings
,
2614 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
,
2615 struct net_device
*dev
, u8 default_version
)
2617 void __iomem
*ioaddr
= tp
->mmio_addr
;
2619 * The driver currently handles the 8168Bf and the 8168Be identically
2620 * but they can be identified more specifically through the test below
2623 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2625 * Same thing for the 8101Eb and the 8101Ec:
2627 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2629 static const struct rtl_mac_info
{
2634 /* 8168EP family. */
2635 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51
},
2636 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50
},
2637 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49
},
2640 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46
},
2641 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45
},
2644 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44
},
2645 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42
},
2646 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41
},
2647 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40
},
2650 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38
},
2651 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36
},
2652 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35
},
2655 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34
},
2656 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33
},
2657 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32
},
2658 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33
},
2661 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26
},
2662 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25
},
2663 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26
},
2665 /* 8168DP family. */
2666 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27
},
2667 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28
},
2668 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31
},
2671 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24
},
2672 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23
},
2673 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
2674 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24
},
2675 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
2676 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
2677 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21
},
2678 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22
},
2679 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22
},
2682 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
2683 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
2684 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
2685 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
2688 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39
},
2689 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39
},
2690 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37
},
2691 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30
},
2692 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30
},
2693 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29
},
2694 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30
},
2695 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09
},
2696 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09
},
2697 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08
},
2698 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08
},
2699 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07
},
2700 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07
},
2701 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
2702 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10
},
2703 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
2704 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09
},
2705 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09
},
2706 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
2707 /* FIXME: where did these entries come from ? -- FR */
2708 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
2709 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
2712 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
2713 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
2714 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
2715 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
2716 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
2717 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
2720 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE
}
2722 const struct rtl_mac_info
*p
= mac_info
;
2725 reg
= RTL_R32(TxConfig
);
2726 while ((reg
& p
->mask
) != p
->val
)
2728 tp
->mac_version
= p
->mac_version
;
2730 if (tp
->mac_version
== RTL_GIGA_MAC_NONE
) {
2731 netif_notice(tp
, probe
, dev
,
2732 "unknown MAC, using family default\n");
2733 tp
->mac_version
= default_version
;
2734 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_42
) {
2735 tp
->mac_version
= tp
->mii
.supports_gmii
?
2736 RTL_GIGA_MAC_VER_42
:
2737 RTL_GIGA_MAC_VER_43
;
2738 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_45
) {
2739 tp
->mac_version
= tp
->mii
.supports_gmii
?
2740 RTL_GIGA_MAC_VER_45
:
2741 RTL_GIGA_MAC_VER_47
;
2742 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_46
) {
2743 tp
->mac_version
= tp
->mii
.supports_gmii
?
2744 RTL_GIGA_MAC_VER_46
:
2745 RTL_GIGA_MAC_VER_48
;
2749 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
2751 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
2759 static void rtl_writephy_batch(struct rtl8169_private
*tp
,
2760 const struct phy_reg
*regs
, int len
)
2763 rtl_writephy(tp
, regs
->reg
, regs
->val
);
2768 #define PHY_READ 0x00000000
2769 #define PHY_DATA_OR 0x10000000
2770 #define PHY_DATA_AND 0x20000000
2771 #define PHY_BJMPN 0x30000000
2772 #define PHY_MDIO_CHG 0x40000000
2773 #define PHY_CLEAR_READCOUNT 0x70000000
2774 #define PHY_WRITE 0x80000000
2775 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2776 #define PHY_COMP_EQ_SKIPN 0xa0000000
2777 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2778 #define PHY_WRITE_PREVIOUS 0xc0000000
2779 #define PHY_SKIPN 0xd0000000
2780 #define PHY_DELAY_MS 0xe0000000
2784 char version
[RTL_VER_SIZE
];
2790 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2792 static bool rtl_fw_format_ok(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
2794 const struct firmware
*fw
= rtl_fw
->fw
;
2795 struct fw_info
*fw_info
= (struct fw_info
*)fw
->data
;
2796 struct rtl_fw_phy_action
*pa
= &rtl_fw
->phy_action
;
2797 char *version
= rtl_fw
->version
;
2800 if (fw
->size
< FW_OPCODE_SIZE
)
2803 if (!fw_info
->magic
) {
2804 size_t i
, size
, start
;
2807 if (fw
->size
< sizeof(*fw_info
))
2810 for (i
= 0; i
< fw
->size
; i
++)
2811 checksum
+= fw
->data
[i
];
2815 start
= le32_to_cpu(fw_info
->fw_start
);
2816 if (start
> fw
->size
)
2819 size
= le32_to_cpu(fw_info
->fw_len
);
2820 if (size
> (fw
->size
- start
) / FW_OPCODE_SIZE
)
2823 memcpy(version
, fw_info
->version
, RTL_VER_SIZE
);
2825 pa
->code
= (__le32
*)(fw
->data
+ start
);
2828 if (fw
->size
% FW_OPCODE_SIZE
)
2831 strlcpy(version
, rtl_lookup_firmware_name(tp
), RTL_VER_SIZE
);
2833 pa
->code
= (__le32
*)fw
->data
;
2834 pa
->size
= fw
->size
/ FW_OPCODE_SIZE
;
2836 version
[RTL_VER_SIZE
- 1] = 0;
2843 static bool rtl_fw_data_ok(struct rtl8169_private
*tp
, struct net_device
*dev
,
2844 struct rtl_fw_phy_action
*pa
)
2849 for (index
= 0; index
< pa
->size
; index
++) {
2850 u32 action
= le32_to_cpu(pa
->code
[index
]);
2851 u32 regno
= (action
& 0x0fff0000) >> 16;
2853 switch(action
& 0xf0000000) {
2858 case PHY_CLEAR_READCOUNT
:
2860 case PHY_WRITE_PREVIOUS
:
2865 if (regno
> index
) {
2866 netif_err(tp
, ifup
, tp
->dev
,
2867 "Out of range of firmware\n");
2871 case PHY_READCOUNT_EQ_SKIP
:
2872 if (index
+ 2 >= pa
->size
) {
2873 netif_err(tp
, ifup
, tp
->dev
,
2874 "Out of range of firmware\n");
2878 case PHY_COMP_EQ_SKIPN
:
2879 case PHY_COMP_NEQ_SKIPN
:
2881 if (index
+ 1 + regno
>= pa
->size
) {
2882 netif_err(tp
, ifup
, tp
->dev
,
2883 "Out of range of firmware\n");
2889 netif_err(tp
, ifup
, tp
->dev
,
2890 "Invalid action 0x%08x\n", action
);
2899 static int rtl_check_firmware(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
2901 struct net_device
*dev
= tp
->dev
;
2904 if (!rtl_fw_format_ok(tp
, rtl_fw
)) {
2905 netif_err(tp
, ifup
, dev
, "invalid firmware\n");
2909 if (rtl_fw_data_ok(tp
, dev
, &rtl_fw
->phy_action
))
2915 static void rtl_phy_write_fw(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
2917 struct rtl_fw_phy_action
*pa
= &rtl_fw
->phy_action
;
2918 struct mdio_ops org
, *ops
= &tp
->mdio_ops
;
2922 predata
= count
= 0;
2923 org
.write
= ops
->write
;
2924 org
.read
= ops
->read
;
2926 for (index
= 0; index
< pa
->size
; ) {
2927 u32 action
= le32_to_cpu(pa
->code
[index
]);
2928 u32 data
= action
& 0x0000ffff;
2929 u32 regno
= (action
& 0x0fff0000) >> 16;
2934 switch(action
& 0xf0000000) {
2936 predata
= rtl_readphy(tp
, regno
);
2953 ops
->write
= org
.write
;
2954 ops
->read
= org
.read
;
2955 } else if (data
== 1) {
2956 ops
->write
= mac_mcu_write
;
2957 ops
->read
= mac_mcu_read
;
2962 case PHY_CLEAR_READCOUNT
:
2967 rtl_writephy(tp
, regno
, data
);
2970 case PHY_READCOUNT_EQ_SKIP
:
2971 index
+= (count
== data
) ? 2 : 1;
2973 case PHY_COMP_EQ_SKIPN
:
2974 if (predata
== data
)
2978 case PHY_COMP_NEQ_SKIPN
:
2979 if (predata
!= data
)
2983 case PHY_WRITE_PREVIOUS
:
2984 rtl_writephy(tp
, regno
, predata
);
3000 ops
->write
= org
.write
;
3001 ops
->read
= org
.read
;
3004 static void rtl_release_firmware(struct rtl8169_private
*tp
)
3006 if (!IS_ERR_OR_NULL(tp
->rtl_fw
)) {
3007 release_firmware(tp
->rtl_fw
->fw
);
3010 tp
->rtl_fw
= RTL_FIRMWARE_UNKNOWN
;
3013 static void rtl_apply_firmware(struct rtl8169_private
*tp
)
3015 struct rtl_fw
*rtl_fw
= tp
->rtl_fw
;
3017 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
3018 if (!IS_ERR_OR_NULL(rtl_fw
))
3019 rtl_phy_write_fw(tp
, rtl_fw
);
3022 static void rtl_apply_firmware_cond(struct rtl8169_private
*tp
, u8 reg
, u16 val
)
3024 if (rtl_readphy(tp
, reg
) != val
)
3025 netif_warn(tp
, hw
, tp
->dev
, "chipset not ready for firmware\n");
3027 rtl_apply_firmware(tp
);
3030 static void rtl8169s_hw_phy_config(struct rtl8169_private
*tp
)
3032 static const struct phy_reg phy_reg_init
[] = {
3094 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3097 static void rtl8169sb_hw_phy_config(struct rtl8169_private
*tp
)
3099 static const struct phy_reg phy_reg_init
[] = {
3105 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3108 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private
*tp
)
3110 struct pci_dev
*pdev
= tp
->pci_dev
;
3112 if ((pdev
->subsystem_vendor
!= PCI_VENDOR_ID_GIGABYTE
) ||
3113 (pdev
->subsystem_device
!= 0xe000))
3116 rtl_writephy(tp
, 0x1f, 0x0001);
3117 rtl_writephy(tp
, 0x10, 0xf01b);
3118 rtl_writephy(tp
, 0x1f, 0x0000);
3121 static void rtl8169scd_hw_phy_config(struct rtl8169_private
*tp
)
3123 static const struct phy_reg phy_reg_init
[] = {
3163 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3165 rtl8169scd_hw_phy_config_quirk(tp
);
3168 static void rtl8169sce_hw_phy_config(struct rtl8169_private
*tp
)
3170 static const struct phy_reg phy_reg_init
[] = {
3218 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3221 static void rtl8168bb_hw_phy_config(struct rtl8169_private
*tp
)
3223 static const struct phy_reg phy_reg_init
[] = {
3228 rtl_writephy(tp
, 0x1f, 0x0001);
3229 rtl_patchphy(tp
, 0x16, 1 << 0);
3231 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3234 static void rtl8168bef_hw_phy_config(struct rtl8169_private
*tp
)
3236 static const struct phy_reg phy_reg_init
[] = {
3242 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3245 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private
*tp
)
3247 static const struct phy_reg phy_reg_init
[] = {
3255 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3258 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private
*tp
)
3260 static const struct phy_reg phy_reg_init
[] = {
3266 rtl_writephy(tp
, 0x1f, 0x0000);
3267 rtl_patchphy(tp
, 0x14, 1 << 5);
3268 rtl_patchphy(tp
, 0x0d, 1 << 5);
3270 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3273 static void rtl8168c_1_hw_phy_config(struct rtl8169_private
*tp
)
3275 static const struct phy_reg phy_reg_init
[] = {
3295 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3297 rtl_patchphy(tp
, 0x14, 1 << 5);
3298 rtl_patchphy(tp
, 0x0d, 1 << 5);
3299 rtl_writephy(tp
, 0x1f, 0x0000);
3302 static void rtl8168c_2_hw_phy_config(struct rtl8169_private
*tp
)
3304 static const struct phy_reg phy_reg_init
[] = {
3322 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3324 rtl_patchphy(tp
, 0x16, 1 << 0);
3325 rtl_patchphy(tp
, 0x14, 1 << 5);
3326 rtl_patchphy(tp
, 0x0d, 1 << 5);
3327 rtl_writephy(tp
, 0x1f, 0x0000);
3330 static void rtl8168c_3_hw_phy_config(struct rtl8169_private
*tp
)
3332 static const struct phy_reg phy_reg_init
[] = {
3344 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3346 rtl_patchphy(tp
, 0x16, 1 << 0);
3347 rtl_patchphy(tp
, 0x14, 1 << 5);
3348 rtl_patchphy(tp
, 0x0d, 1 << 5);
3349 rtl_writephy(tp
, 0x1f, 0x0000);
3352 static void rtl8168c_4_hw_phy_config(struct rtl8169_private
*tp
)
3354 rtl8168c_3_hw_phy_config(tp
);
3357 static void rtl8168d_1_hw_phy_config(struct rtl8169_private
*tp
)
3359 static const struct phy_reg phy_reg_init_0
[] = {
3360 /* Channel Estimation */
3381 * Enhance line driver power
3390 * Can not link to 1Gbps with bad cable
3391 * Decrease SNR threshold form 21.07dB to 19.04dB
3400 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
3404 * Fine Tune Switching regulator parameter
3406 rtl_writephy(tp
, 0x1f, 0x0002);
3407 rtl_w0w1_phy(tp
, 0x0b, 0x0010, 0x00ef);
3408 rtl_w0w1_phy(tp
, 0x0c, 0xa200, 0x5d00);
3410 if (rtl8168d_efuse_read(tp
, 0x01) == 0xb1) {
3411 static const struct phy_reg phy_reg_init
[] = {
3421 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3423 val
= rtl_readphy(tp
, 0x0d);
3425 if ((val
& 0x00ff) != 0x006c) {
3426 static const u32 set
[] = {
3427 0x0065, 0x0066, 0x0067, 0x0068,
3428 0x0069, 0x006a, 0x006b, 0x006c
3432 rtl_writephy(tp
, 0x1f, 0x0002);
3435 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
3436 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
3439 static const struct phy_reg phy_reg_init
[] = {
3447 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3450 /* RSET couple improve */
3451 rtl_writephy(tp
, 0x1f, 0x0002);
3452 rtl_patchphy(tp
, 0x0d, 0x0300);
3453 rtl_patchphy(tp
, 0x0f, 0x0010);
3455 /* Fine tune PLL performance */
3456 rtl_writephy(tp
, 0x1f, 0x0002);
3457 rtl_w0w1_phy(tp
, 0x02, 0x0100, 0x0600);
3458 rtl_w0w1_phy(tp
, 0x03, 0x0000, 0xe000);
3460 rtl_writephy(tp
, 0x1f, 0x0005);
3461 rtl_writephy(tp
, 0x05, 0x001b);
3463 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xbf00);
3465 rtl_writephy(tp
, 0x1f, 0x0000);
3468 static void rtl8168d_2_hw_phy_config(struct rtl8169_private
*tp
)
3470 static const struct phy_reg phy_reg_init_0
[] = {
3471 /* Channel Estimation */
3492 * Enhance line driver power
3501 * Can not link to 1Gbps with bad cable
3502 * Decrease SNR threshold form 21.07dB to 19.04dB
3511 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
3513 if (rtl8168d_efuse_read(tp
, 0x01) == 0xb1) {
3514 static const struct phy_reg phy_reg_init
[] = {
3525 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3527 val
= rtl_readphy(tp
, 0x0d);
3528 if ((val
& 0x00ff) != 0x006c) {
3529 static const u32 set
[] = {
3530 0x0065, 0x0066, 0x0067, 0x0068,
3531 0x0069, 0x006a, 0x006b, 0x006c
3535 rtl_writephy(tp
, 0x1f, 0x0002);
3538 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
3539 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
3542 static const struct phy_reg phy_reg_init
[] = {
3550 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3553 /* Fine tune PLL performance */
3554 rtl_writephy(tp
, 0x1f, 0x0002);
3555 rtl_w0w1_phy(tp
, 0x02, 0x0100, 0x0600);
3556 rtl_w0w1_phy(tp
, 0x03, 0x0000, 0xe000);
3558 /* Switching regulator Slew rate */
3559 rtl_writephy(tp
, 0x1f, 0x0002);
3560 rtl_patchphy(tp
, 0x0f, 0x0017);
3562 rtl_writephy(tp
, 0x1f, 0x0005);
3563 rtl_writephy(tp
, 0x05, 0x001b);
3565 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xb300);
3567 rtl_writephy(tp
, 0x1f, 0x0000);
3570 static void rtl8168d_3_hw_phy_config(struct rtl8169_private
*tp
)
3572 static const struct phy_reg phy_reg_init
[] = {
3628 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3631 static void rtl8168d_4_hw_phy_config(struct rtl8169_private
*tp
)
3633 static const struct phy_reg phy_reg_init
[] = {
3643 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3644 rtl_patchphy(tp
, 0x0d, 1 << 5);
3647 static void rtl8168e_1_hw_phy_config(struct rtl8169_private
*tp
)
3649 static const struct phy_reg phy_reg_init
[] = {
3650 /* Enable Delay cap */
3656 /* Channel estimation fine tune */
3665 /* Update PFM & 10M TX idle timer */
3677 rtl_apply_firmware(tp
);
3679 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3681 /* DCO enable for 10M IDLE Power */
3682 rtl_writephy(tp
, 0x1f, 0x0007);
3683 rtl_writephy(tp
, 0x1e, 0x0023);
3684 rtl_w0w1_phy(tp
, 0x17, 0x0006, 0x0000);
3685 rtl_writephy(tp
, 0x1f, 0x0000);
3687 /* For impedance matching */
3688 rtl_writephy(tp
, 0x1f, 0x0002);
3689 rtl_w0w1_phy(tp
, 0x08, 0x8000, 0x7f00);
3690 rtl_writephy(tp
, 0x1f, 0x0000);
3692 /* PHY auto speed down */
3693 rtl_writephy(tp
, 0x1f, 0x0007);
3694 rtl_writephy(tp
, 0x1e, 0x002d);
3695 rtl_w0w1_phy(tp
, 0x18, 0x0050, 0x0000);
3696 rtl_writephy(tp
, 0x1f, 0x0000);
3697 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
3699 rtl_writephy(tp
, 0x1f, 0x0005);
3700 rtl_writephy(tp
, 0x05, 0x8b86);
3701 rtl_w0w1_phy(tp
, 0x06, 0x0001, 0x0000);
3702 rtl_writephy(tp
, 0x1f, 0x0000);
3704 rtl_writephy(tp
, 0x1f, 0x0005);
3705 rtl_writephy(tp
, 0x05, 0x8b85);
3706 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x2000);
3707 rtl_writephy(tp
, 0x1f, 0x0007);
3708 rtl_writephy(tp
, 0x1e, 0x0020);
3709 rtl_w0w1_phy(tp
, 0x15, 0x0000, 0x1100);
3710 rtl_writephy(tp
, 0x1f, 0x0006);
3711 rtl_writephy(tp
, 0x00, 0x5a00);
3712 rtl_writephy(tp
, 0x1f, 0x0000);
3713 rtl_writephy(tp
, 0x0d, 0x0007);
3714 rtl_writephy(tp
, 0x0e, 0x003c);
3715 rtl_writephy(tp
, 0x0d, 0x4007);
3716 rtl_writephy(tp
, 0x0e, 0x0000);
3717 rtl_writephy(tp
, 0x0d, 0x0000);
3720 static void rtl_rar_exgmac_set(struct rtl8169_private
*tp
, u8
*addr
)
3723 addr
[0] | (addr
[1] << 8),
3724 addr
[2] | (addr
[3] << 8),
3725 addr
[4] | (addr
[5] << 8)
3727 const struct exgmac_reg e
[] = {
3728 { .addr
= 0xe0, ERIAR_MASK_1111
, .val
= w
[0] | (w
[1] << 16) },
3729 { .addr
= 0xe4, ERIAR_MASK_1111
, .val
= w
[2] },
3730 { .addr
= 0xf0, ERIAR_MASK_1111
, .val
= w
[0] << 16 },
3731 { .addr
= 0xf4, ERIAR_MASK_1111
, .val
= w
[1] | (w
[2] << 16) }
3734 rtl_write_exgmac_batch(tp
, e
, ARRAY_SIZE(e
));
3737 static void rtl8168e_2_hw_phy_config(struct rtl8169_private
*tp
)
3739 static const struct phy_reg phy_reg_init
[] = {
3740 /* Enable Delay cap */
3749 /* Channel estimation fine tune */
3766 rtl_apply_firmware(tp
);
3768 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3770 /* For 4-corner performance improve */
3771 rtl_writephy(tp
, 0x1f, 0x0005);
3772 rtl_writephy(tp
, 0x05, 0x8b80);
3773 rtl_w0w1_phy(tp
, 0x17, 0x0006, 0x0000);
3774 rtl_writephy(tp
, 0x1f, 0x0000);
3776 /* PHY auto speed down */
3777 rtl_writephy(tp
, 0x1f, 0x0004);
3778 rtl_writephy(tp
, 0x1f, 0x0007);
3779 rtl_writephy(tp
, 0x1e, 0x002d);
3780 rtl_w0w1_phy(tp
, 0x18, 0x0010, 0x0000);
3781 rtl_writephy(tp
, 0x1f, 0x0002);
3782 rtl_writephy(tp
, 0x1f, 0x0000);
3783 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
3785 /* improve 10M EEE waveform */
3786 rtl_writephy(tp
, 0x1f, 0x0005);
3787 rtl_writephy(tp
, 0x05, 0x8b86);
3788 rtl_w0w1_phy(tp
, 0x06, 0x0001, 0x0000);
3789 rtl_writephy(tp
, 0x1f, 0x0000);
3791 /* Improve 2-pair detection performance */
3792 rtl_writephy(tp
, 0x1f, 0x0005);
3793 rtl_writephy(tp
, 0x05, 0x8b85);
3794 rtl_w0w1_phy(tp
, 0x06, 0x4000, 0x0000);
3795 rtl_writephy(tp
, 0x1f, 0x0000);
3798 rtl_w0w1_eri(tp
, 0x1b0, ERIAR_MASK_1111
, 0x0003, 0x0000, ERIAR_EXGMAC
);
3799 rtl_writephy(tp
, 0x1f, 0x0005);
3800 rtl_writephy(tp
, 0x05, 0x8b85);
3801 rtl_w0w1_phy(tp
, 0x06, 0x2000, 0x0000);
3802 rtl_writephy(tp
, 0x1f, 0x0004);
3803 rtl_writephy(tp
, 0x1f, 0x0007);
3804 rtl_writephy(tp
, 0x1e, 0x0020);
3805 rtl_w0w1_phy(tp
, 0x15, 0x0100, 0x0000);
3806 rtl_writephy(tp
, 0x1f, 0x0002);
3807 rtl_writephy(tp
, 0x1f, 0x0000);
3808 rtl_writephy(tp
, 0x0d, 0x0007);
3809 rtl_writephy(tp
, 0x0e, 0x003c);
3810 rtl_writephy(tp
, 0x0d, 0x4007);
3811 rtl_writephy(tp
, 0x0e, 0x0006);
3812 rtl_writephy(tp
, 0x0d, 0x0000);
3815 rtl_writephy(tp
, 0x1f, 0x0003);
3816 rtl_w0w1_phy(tp
, 0x19, 0x0001, 0x0000);
3817 rtl_w0w1_phy(tp
, 0x10, 0x0400, 0x0000);
3818 rtl_writephy(tp
, 0x1f, 0x0000);
3819 rtl_writephy(tp
, 0x1f, 0x0005);
3820 rtl_w0w1_phy(tp
, 0x01, 0x0100, 0x0000);
3821 rtl_writephy(tp
, 0x1f, 0x0000);
3822 /* soft-reset phy */
3823 rtl_writephy(tp
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
| BMCR_ANRESTART
);
3825 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3826 rtl_rar_exgmac_set(tp
, tp
->dev
->dev_addr
);
3829 static void rtl8168f_hw_phy_config(struct rtl8169_private
*tp
)
3831 /* For 4-corner performance improve */
3832 rtl_writephy(tp
, 0x1f, 0x0005);
3833 rtl_writephy(tp
, 0x05, 0x8b80);
3834 rtl_w0w1_phy(tp
, 0x06, 0x0006, 0x0000);
3835 rtl_writephy(tp
, 0x1f, 0x0000);
3837 /* PHY auto speed down */
3838 rtl_writephy(tp
, 0x1f, 0x0007);
3839 rtl_writephy(tp
, 0x1e, 0x002d);
3840 rtl_w0w1_phy(tp
, 0x18, 0x0010, 0x0000);
3841 rtl_writephy(tp
, 0x1f, 0x0000);
3842 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
3844 /* Improve 10M EEE waveform */
3845 rtl_writephy(tp
, 0x1f, 0x0005);
3846 rtl_writephy(tp
, 0x05, 0x8b86);
3847 rtl_w0w1_phy(tp
, 0x06, 0x0001, 0x0000);
3848 rtl_writephy(tp
, 0x1f, 0x0000);
3851 static void rtl8168f_1_hw_phy_config(struct rtl8169_private
*tp
)
3853 static const struct phy_reg phy_reg_init
[] = {
3854 /* Channel estimation fine tune */
3859 /* Modify green table for giga & fnet */
3876 /* Modify green table for 10M */
3882 /* Disable hiimpedance detection (RTCT) */
3888 rtl_apply_firmware(tp
);
3890 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3892 rtl8168f_hw_phy_config(tp
);
3894 /* Improve 2-pair detection performance */
3895 rtl_writephy(tp
, 0x1f, 0x0005);
3896 rtl_writephy(tp
, 0x05, 0x8b85);
3897 rtl_w0w1_phy(tp
, 0x06, 0x4000, 0x0000);
3898 rtl_writephy(tp
, 0x1f, 0x0000);
3901 static void rtl8168f_2_hw_phy_config(struct rtl8169_private
*tp
)
3903 rtl_apply_firmware(tp
);
3905 rtl8168f_hw_phy_config(tp
);
3908 static void rtl8411_hw_phy_config(struct rtl8169_private
*tp
)
3910 static const struct phy_reg phy_reg_init
[] = {
3911 /* Channel estimation fine tune */
3916 /* Modify green table for giga & fnet */
3933 /* Modify green table for 10M */
3939 /* Disable hiimpedance detection (RTCT) */
3946 rtl_apply_firmware(tp
);
3948 rtl8168f_hw_phy_config(tp
);
3950 /* Improve 2-pair detection performance */
3951 rtl_writephy(tp
, 0x1f, 0x0005);
3952 rtl_writephy(tp
, 0x05, 0x8b85);
3953 rtl_w0w1_phy(tp
, 0x06, 0x4000, 0x0000);
3954 rtl_writephy(tp
, 0x1f, 0x0000);
3956 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3958 /* Modify green table for giga */
3959 rtl_writephy(tp
, 0x1f, 0x0005);
3960 rtl_writephy(tp
, 0x05, 0x8b54);
3961 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0800);
3962 rtl_writephy(tp
, 0x05, 0x8b5d);
3963 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0800);
3964 rtl_writephy(tp
, 0x05, 0x8a7c);
3965 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0100);
3966 rtl_writephy(tp
, 0x05, 0x8a7f);
3967 rtl_w0w1_phy(tp
, 0x06, 0x0100, 0x0000);
3968 rtl_writephy(tp
, 0x05, 0x8a82);
3969 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0100);
3970 rtl_writephy(tp
, 0x05, 0x8a85);
3971 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0100);
3972 rtl_writephy(tp
, 0x05, 0x8a88);
3973 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0100);
3974 rtl_writephy(tp
, 0x1f, 0x0000);
3976 /* uc same-seed solution */
3977 rtl_writephy(tp
, 0x1f, 0x0005);
3978 rtl_writephy(tp
, 0x05, 0x8b85);
3979 rtl_w0w1_phy(tp
, 0x06, 0x8000, 0x0000);
3980 rtl_writephy(tp
, 0x1f, 0x0000);
3983 rtl_w0w1_eri(tp
, 0x1b0, ERIAR_MASK_0001
, 0x00, 0x03, ERIAR_EXGMAC
);
3984 rtl_writephy(tp
, 0x1f, 0x0005);
3985 rtl_writephy(tp
, 0x05, 0x8b85);
3986 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x2000);
3987 rtl_writephy(tp
, 0x1f, 0x0004);
3988 rtl_writephy(tp
, 0x1f, 0x0007);
3989 rtl_writephy(tp
, 0x1e, 0x0020);
3990 rtl_w0w1_phy(tp
, 0x15, 0x0000, 0x0100);
3991 rtl_writephy(tp
, 0x1f, 0x0000);
3992 rtl_writephy(tp
, 0x0d, 0x0007);
3993 rtl_writephy(tp
, 0x0e, 0x003c);
3994 rtl_writephy(tp
, 0x0d, 0x4007);
3995 rtl_writephy(tp
, 0x0e, 0x0000);
3996 rtl_writephy(tp
, 0x0d, 0x0000);
3999 rtl_writephy(tp
, 0x1f, 0x0003);
4000 rtl_w0w1_phy(tp
, 0x19, 0x0000, 0x0001);
4001 rtl_w0w1_phy(tp
, 0x10, 0x0000, 0x0400);
4002 rtl_writephy(tp
, 0x1f, 0x0000);
4005 static void rtl8168g_1_hw_phy_config(struct rtl8169_private
*tp
)
4007 rtl_apply_firmware(tp
);
4009 rtl_writephy(tp
, 0x1f, 0x0a46);
4010 if (rtl_readphy(tp
, 0x10) & 0x0100) {
4011 rtl_writephy(tp
, 0x1f, 0x0bcc);
4012 rtl_w0w1_phy(tp
, 0x12, 0x0000, 0x8000);
4014 rtl_writephy(tp
, 0x1f, 0x0bcc);
4015 rtl_w0w1_phy(tp
, 0x12, 0x8000, 0x0000);
4018 rtl_writephy(tp
, 0x1f, 0x0a46);
4019 if (rtl_readphy(tp
, 0x13) & 0x0100) {
4020 rtl_writephy(tp
, 0x1f, 0x0c41);
4021 rtl_w0w1_phy(tp
, 0x15, 0x0002, 0x0000);
4023 rtl_writephy(tp
, 0x1f, 0x0c41);
4024 rtl_w0w1_phy(tp
, 0x15, 0x0000, 0x0002);
4027 /* Enable PHY auto speed down */
4028 rtl_writephy(tp
, 0x1f, 0x0a44);
4029 rtl_w0w1_phy(tp
, 0x11, 0x000c, 0x0000);
4031 rtl_writephy(tp
, 0x1f, 0x0bcc);
4032 rtl_w0w1_phy(tp
, 0x14, 0x0100, 0x0000);
4033 rtl_writephy(tp
, 0x1f, 0x0a44);
4034 rtl_w0w1_phy(tp
, 0x11, 0x00c0, 0x0000);
4035 rtl_writephy(tp
, 0x1f, 0x0a43);
4036 rtl_writephy(tp
, 0x13, 0x8084);
4037 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x6000);
4038 rtl_w0w1_phy(tp
, 0x10, 0x1003, 0x0000);
4040 /* EEE auto-fallback function */
4041 rtl_writephy(tp
, 0x1f, 0x0a4b);
4042 rtl_w0w1_phy(tp
, 0x11, 0x0004, 0x0000);
4044 /* Enable UC LPF tune function */
4045 rtl_writephy(tp
, 0x1f, 0x0a43);
4046 rtl_writephy(tp
, 0x13, 0x8012);
4047 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
4049 rtl_writephy(tp
, 0x1f, 0x0c42);
4050 rtl_w0w1_phy(tp
, 0x11, 0x4000, 0x2000);
4052 /* Improve SWR Efficiency */
4053 rtl_writephy(tp
, 0x1f, 0x0bcd);
4054 rtl_writephy(tp
, 0x14, 0x5065);
4055 rtl_writephy(tp
, 0x14, 0xd065);
4056 rtl_writephy(tp
, 0x1f, 0x0bc8);
4057 rtl_writephy(tp
, 0x11, 0x5655);
4058 rtl_writephy(tp
, 0x1f, 0x0bcd);
4059 rtl_writephy(tp
, 0x14, 0x1065);
4060 rtl_writephy(tp
, 0x14, 0x9065);
4061 rtl_writephy(tp
, 0x14, 0x1065);
4063 /* Check ALDPS bit, disable it if enabled */
4064 rtl_writephy(tp
, 0x1f, 0x0a43);
4065 if (rtl_readphy(tp
, 0x10) & 0x0004)
4066 rtl_w0w1_phy(tp
, 0x10, 0x0000, 0x0004);
4068 rtl_writephy(tp
, 0x1f, 0x0000);
4071 static void rtl8168g_2_hw_phy_config(struct rtl8169_private
*tp
)
4073 rtl_apply_firmware(tp
);
4076 static void rtl8168h_1_hw_phy_config(struct rtl8169_private
*tp
)
4081 rtl_apply_firmware(tp
);
4083 /* CHN EST parameters adjust - giga master */
4084 rtl_writephy(tp
, 0x1f, 0x0a43);
4085 rtl_writephy(tp
, 0x13, 0x809b);
4086 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0xf800);
4087 rtl_writephy(tp
, 0x13, 0x80a2);
4088 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0xff00);
4089 rtl_writephy(tp
, 0x13, 0x80a4);
4090 rtl_w0w1_phy(tp
, 0x14, 0x8500, 0xff00);
4091 rtl_writephy(tp
, 0x13, 0x809c);
4092 rtl_w0w1_phy(tp
, 0x14, 0xbd00, 0xff00);
4093 rtl_writephy(tp
, 0x1f, 0x0000);
4095 /* CHN EST parameters adjust - giga slave */
4096 rtl_writephy(tp
, 0x1f, 0x0a43);
4097 rtl_writephy(tp
, 0x13, 0x80ad);
4098 rtl_w0w1_phy(tp
, 0x14, 0x7000, 0xf800);
4099 rtl_writephy(tp
, 0x13, 0x80b4);
4100 rtl_w0w1_phy(tp
, 0x14, 0x5000, 0xff00);
4101 rtl_writephy(tp
, 0x13, 0x80ac);
4102 rtl_w0w1_phy(tp
, 0x14, 0x4000, 0xff00);
4103 rtl_writephy(tp
, 0x1f, 0x0000);
4105 /* CHN EST parameters adjust - fnet */
4106 rtl_writephy(tp
, 0x1f, 0x0a43);
4107 rtl_writephy(tp
, 0x13, 0x808e);
4108 rtl_w0w1_phy(tp
, 0x14, 0x1200, 0xff00);
4109 rtl_writephy(tp
, 0x13, 0x8090);
4110 rtl_w0w1_phy(tp
, 0x14, 0xe500, 0xff00);
4111 rtl_writephy(tp
, 0x13, 0x8092);
4112 rtl_w0w1_phy(tp
, 0x14, 0x9f00, 0xff00);
4113 rtl_writephy(tp
, 0x1f, 0x0000);
4115 /* enable R-tune & PGA-retune function */
4117 rtl_writephy(tp
, 0x1f, 0x0a46);
4118 data
= rtl_readphy(tp
, 0x13);
4121 dout_tapbin
|= data
;
4122 data
= rtl_readphy(tp
, 0x12);
4125 dout_tapbin
|= data
;
4126 dout_tapbin
= ~(dout_tapbin
^0x08);
4128 dout_tapbin
&= 0xf000;
4129 rtl_writephy(tp
, 0x1f, 0x0a43);
4130 rtl_writephy(tp
, 0x13, 0x827a);
4131 rtl_w0w1_phy(tp
, 0x14, dout_tapbin
, 0xf000);
4132 rtl_writephy(tp
, 0x13, 0x827b);
4133 rtl_w0w1_phy(tp
, 0x14, dout_tapbin
, 0xf000);
4134 rtl_writephy(tp
, 0x13, 0x827c);
4135 rtl_w0w1_phy(tp
, 0x14, dout_tapbin
, 0xf000);
4136 rtl_writephy(tp
, 0x13, 0x827d);
4137 rtl_w0w1_phy(tp
, 0x14, dout_tapbin
, 0xf000);
4139 rtl_writephy(tp
, 0x1f, 0x0a43);
4140 rtl_writephy(tp
, 0x13, 0x0811);
4141 rtl_w0w1_phy(tp
, 0x14, 0x0800, 0x0000);
4142 rtl_writephy(tp
, 0x1f, 0x0a42);
4143 rtl_w0w1_phy(tp
, 0x16, 0x0002, 0x0000);
4144 rtl_writephy(tp
, 0x1f, 0x0000);
4146 /* enable GPHY 10M */
4147 rtl_writephy(tp
, 0x1f, 0x0a44);
4148 rtl_w0w1_phy(tp
, 0x11, 0x0800, 0x0000);
4149 rtl_writephy(tp
, 0x1f, 0x0000);
4151 /* SAR ADC performance */
4152 rtl_writephy(tp
, 0x1f, 0x0bca);
4153 rtl_w0w1_phy(tp
, 0x17, 0x4000, 0x3000);
4154 rtl_writephy(tp
, 0x1f, 0x0000);
4156 rtl_writephy(tp
, 0x1f, 0x0a43);
4157 rtl_writephy(tp
, 0x13, 0x803f);
4158 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
4159 rtl_writephy(tp
, 0x13, 0x8047);
4160 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
4161 rtl_writephy(tp
, 0x13, 0x804f);
4162 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
4163 rtl_writephy(tp
, 0x13, 0x8057);
4164 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
4165 rtl_writephy(tp
, 0x13, 0x805f);
4166 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
4167 rtl_writephy(tp
, 0x13, 0x8067);
4168 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
4169 rtl_writephy(tp
, 0x13, 0x806f);
4170 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
4171 rtl_writephy(tp
, 0x1f, 0x0000);
4173 /* disable phy pfm mode */
4174 rtl_writephy(tp
, 0x1f, 0x0a44);
4175 rtl_w0w1_phy(tp
, 0x11, 0x0000, 0x0080);
4176 rtl_writephy(tp
, 0x1f, 0x0000);
4178 /* Check ALDPS bit, disable it if enabled */
4179 rtl_writephy(tp
, 0x1f, 0x0a43);
4180 if (rtl_readphy(tp
, 0x10) & 0x0004)
4181 rtl_w0w1_phy(tp
, 0x10, 0x0000, 0x0004);
4183 rtl_writephy(tp
, 0x1f, 0x0000);
4186 static void rtl8168h_2_hw_phy_config(struct rtl8169_private
*tp
)
4188 u16 ioffset_p3
, ioffset_p2
, ioffset_p1
, ioffset_p0
;
4192 rtl_apply_firmware(tp
);
4194 /* CHIN EST parameter update */
4195 rtl_writephy(tp
, 0x1f, 0x0a43);
4196 rtl_writephy(tp
, 0x13, 0x808a);
4197 rtl_w0w1_phy(tp
, 0x14, 0x000a, 0x003f);
4198 rtl_writephy(tp
, 0x1f, 0x0000);
4200 /* enable R-tune & PGA-retune function */
4201 rtl_writephy(tp
, 0x1f, 0x0a43);
4202 rtl_writephy(tp
, 0x13, 0x0811);
4203 rtl_w0w1_phy(tp
, 0x14, 0x0800, 0x0000);
4204 rtl_writephy(tp
, 0x1f, 0x0a42);
4205 rtl_w0w1_phy(tp
, 0x16, 0x0002, 0x0000);
4206 rtl_writephy(tp
, 0x1f, 0x0000);
4208 /* enable GPHY 10M */
4209 rtl_writephy(tp
, 0x1f, 0x0a44);
4210 rtl_w0w1_phy(tp
, 0x11, 0x0800, 0x0000);
4211 rtl_writephy(tp
, 0x1f, 0x0000);
4213 r8168_mac_ocp_write(tp
, 0xdd02, 0x807d);
4214 data
= r8168_mac_ocp_read(tp
, 0xdd02);
4215 ioffset_p3
= ((data
& 0x80)>>7);
4218 data
= r8168_mac_ocp_read(tp
, 0xdd00);
4219 ioffset_p3
|= ((data
& (0xe000))>>13);
4220 ioffset_p2
= ((data
& (0x1e00))>>9);
4221 ioffset_p1
= ((data
& (0x01e0))>>5);
4222 ioffset_p0
= ((data
& 0x0010)>>4);
4224 ioffset_p0
|= (data
& (0x07));
4225 data
= (ioffset_p3
<<12)|(ioffset_p2
<<8)|(ioffset_p1
<<4)|(ioffset_p0
);
4227 if ((ioffset_p3
!= 0x0f) || (ioffset_p2
!= 0x0f) ||
4228 (ioffset_p1
!= 0x0f) || (ioffset_p0
!= 0x0f)) {
4229 rtl_writephy(tp
, 0x1f, 0x0bcf);
4230 rtl_writephy(tp
, 0x16, data
);
4231 rtl_writephy(tp
, 0x1f, 0x0000);
4234 /* Modify rlen (TX LPF corner frequency) level */
4235 rtl_writephy(tp
, 0x1f, 0x0bcd);
4236 data
= rtl_readphy(tp
, 0x16);
4241 data
= rlen
| (rlen
<<4) | (rlen
<<8) | (rlen
<<12);
4242 rtl_writephy(tp
, 0x17, data
);
4243 rtl_writephy(tp
, 0x1f, 0x0bcd);
4244 rtl_writephy(tp
, 0x1f, 0x0000);
4246 /* disable phy pfm mode */
4247 rtl_writephy(tp
, 0x1f, 0x0a44);
4248 rtl_w0w1_phy(tp
, 0x11, 0x0000, 0x0080);
4249 rtl_writephy(tp
, 0x1f, 0x0000);
4251 /* Check ALDPS bit, disable it if enabled */
4252 rtl_writephy(tp
, 0x1f, 0x0a43);
4253 if (rtl_readphy(tp
, 0x10) & 0x0004)
4254 rtl_w0w1_phy(tp
, 0x10, 0x0000, 0x0004);
4256 rtl_writephy(tp
, 0x1f, 0x0000);
4259 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private
*tp
)
4261 /* Enable PHY auto speed down */
4262 rtl_writephy(tp
, 0x1f, 0x0a44);
4263 rtl_w0w1_phy(tp
, 0x11, 0x000c, 0x0000);
4264 rtl_writephy(tp
, 0x1f, 0x0000);
4266 /* patch 10M & ALDPS */
4267 rtl_writephy(tp
, 0x1f, 0x0bcc);
4268 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x0100);
4269 rtl_writephy(tp
, 0x1f, 0x0a44);
4270 rtl_w0w1_phy(tp
, 0x11, 0x00c0, 0x0000);
4271 rtl_writephy(tp
, 0x1f, 0x0a43);
4272 rtl_writephy(tp
, 0x13, 0x8084);
4273 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x6000);
4274 rtl_w0w1_phy(tp
, 0x10, 0x1003, 0x0000);
4275 rtl_writephy(tp
, 0x1f, 0x0000);
4277 /* Enable EEE auto-fallback function */
4278 rtl_writephy(tp
, 0x1f, 0x0a4b);
4279 rtl_w0w1_phy(tp
, 0x11, 0x0004, 0x0000);
4280 rtl_writephy(tp
, 0x1f, 0x0000);
4282 /* Enable UC LPF tune function */
4283 rtl_writephy(tp
, 0x1f, 0x0a43);
4284 rtl_writephy(tp
, 0x13, 0x8012);
4285 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
4286 rtl_writephy(tp
, 0x1f, 0x0000);
4288 /* set rg_sel_sdm_rate */
4289 rtl_writephy(tp
, 0x1f, 0x0c42);
4290 rtl_w0w1_phy(tp
, 0x11, 0x4000, 0x2000);
4291 rtl_writephy(tp
, 0x1f, 0x0000);
4293 /* Check ALDPS bit, disable it if enabled */
4294 rtl_writephy(tp
, 0x1f, 0x0a43);
4295 if (rtl_readphy(tp
, 0x10) & 0x0004)
4296 rtl_w0w1_phy(tp
, 0x10, 0x0000, 0x0004);
4298 rtl_writephy(tp
, 0x1f, 0x0000);
4301 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private
*tp
)
4303 /* patch 10M & ALDPS */
4304 rtl_writephy(tp
, 0x1f, 0x0bcc);
4305 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x0100);
4306 rtl_writephy(tp
, 0x1f, 0x0a44);
4307 rtl_w0w1_phy(tp
, 0x11, 0x00c0, 0x0000);
4308 rtl_writephy(tp
, 0x1f, 0x0a43);
4309 rtl_writephy(tp
, 0x13, 0x8084);
4310 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x6000);
4311 rtl_w0w1_phy(tp
, 0x10, 0x1003, 0x0000);
4312 rtl_writephy(tp
, 0x1f, 0x0000);
4314 /* Enable UC LPF tune function */
4315 rtl_writephy(tp
, 0x1f, 0x0a43);
4316 rtl_writephy(tp
, 0x13, 0x8012);
4317 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
4318 rtl_writephy(tp
, 0x1f, 0x0000);
4320 /* Set rg_sel_sdm_rate */
4321 rtl_writephy(tp
, 0x1f, 0x0c42);
4322 rtl_w0w1_phy(tp
, 0x11, 0x4000, 0x2000);
4323 rtl_writephy(tp
, 0x1f, 0x0000);
4325 /* Channel estimation parameters */
4326 rtl_writephy(tp
, 0x1f, 0x0a43);
4327 rtl_writephy(tp
, 0x13, 0x80f3);
4328 rtl_w0w1_phy(tp
, 0x14, 0x8b00, ~0x8bff);
4329 rtl_writephy(tp
, 0x13, 0x80f0);
4330 rtl_w0w1_phy(tp
, 0x14, 0x3a00, ~0x3aff);
4331 rtl_writephy(tp
, 0x13, 0x80ef);
4332 rtl_w0w1_phy(tp
, 0x14, 0x0500, ~0x05ff);
4333 rtl_writephy(tp
, 0x13, 0x80f6);
4334 rtl_w0w1_phy(tp
, 0x14, 0x6e00, ~0x6eff);
4335 rtl_writephy(tp
, 0x13, 0x80ec);
4336 rtl_w0w1_phy(tp
, 0x14, 0x6800, ~0x68ff);
4337 rtl_writephy(tp
, 0x13, 0x80ed);
4338 rtl_w0w1_phy(tp
, 0x14, 0x7c00, ~0x7cff);
4339 rtl_writephy(tp
, 0x13, 0x80f2);
4340 rtl_w0w1_phy(tp
, 0x14, 0xf400, ~0xf4ff);
4341 rtl_writephy(tp
, 0x13, 0x80f4);
4342 rtl_w0w1_phy(tp
, 0x14, 0x8500, ~0x85ff);
4343 rtl_writephy(tp
, 0x1f, 0x0a43);
4344 rtl_writephy(tp
, 0x13, 0x8110);
4345 rtl_w0w1_phy(tp
, 0x14, 0xa800, ~0xa8ff);
4346 rtl_writephy(tp
, 0x13, 0x810f);
4347 rtl_w0w1_phy(tp
, 0x14, 0x1d00, ~0x1dff);
4348 rtl_writephy(tp
, 0x13, 0x8111);
4349 rtl_w0w1_phy(tp
, 0x14, 0xf500, ~0xf5ff);
4350 rtl_writephy(tp
, 0x13, 0x8113);
4351 rtl_w0w1_phy(tp
, 0x14, 0x6100, ~0x61ff);
4352 rtl_writephy(tp
, 0x13, 0x8115);
4353 rtl_w0w1_phy(tp
, 0x14, 0x9200, ~0x92ff);
4354 rtl_writephy(tp
, 0x13, 0x810e);
4355 rtl_w0w1_phy(tp
, 0x14, 0x0400, ~0x04ff);
4356 rtl_writephy(tp
, 0x13, 0x810c);
4357 rtl_w0w1_phy(tp
, 0x14, 0x7c00, ~0x7cff);
4358 rtl_writephy(tp
, 0x13, 0x810b);
4359 rtl_w0w1_phy(tp
, 0x14, 0x5a00, ~0x5aff);
4360 rtl_writephy(tp
, 0x1f, 0x0a43);
4361 rtl_writephy(tp
, 0x13, 0x80d1);
4362 rtl_w0w1_phy(tp
, 0x14, 0xff00, ~0xffff);
4363 rtl_writephy(tp
, 0x13, 0x80cd);
4364 rtl_w0w1_phy(tp
, 0x14, 0x9e00, ~0x9eff);
4365 rtl_writephy(tp
, 0x13, 0x80d3);
4366 rtl_w0w1_phy(tp
, 0x14, 0x0e00, ~0x0eff);
4367 rtl_writephy(tp
, 0x13, 0x80d5);
4368 rtl_w0w1_phy(tp
, 0x14, 0xca00, ~0xcaff);
4369 rtl_writephy(tp
, 0x13, 0x80d7);
4370 rtl_w0w1_phy(tp
, 0x14, 0x8400, ~0x84ff);
4372 /* Force PWM-mode */
4373 rtl_writephy(tp
, 0x1f, 0x0bcd);
4374 rtl_writephy(tp
, 0x14, 0x5065);
4375 rtl_writephy(tp
, 0x14, 0xd065);
4376 rtl_writephy(tp
, 0x1f, 0x0bc8);
4377 rtl_writephy(tp
, 0x12, 0x00ed);
4378 rtl_writephy(tp
, 0x1f, 0x0bcd);
4379 rtl_writephy(tp
, 0x14, 0x1065);
4380 rtl_writephy(tp
, 0x14, 0x9065);
4381 rtl_writephy(tp
, 0x14, 0x1065);
4382 rtl_writephy(tp
, 0x1f, 0x0000);
4384 /* Check ALDPS bit, disable it if enabled */
4385 rtl_writephy(tp
, 0x1f, 0x0a43);
4386 if (rtl_readphy(tp
, 0x10) & 0x0004)
4387 rtl_w0w1_phy(tp
, 0x10, 0x0000, 0x0004);
4389 rtl_writephy(tp
, 0x1f, 0x0000);
4392 static void rtl8102e_hw_phy_config(struct rtl8169_private
*tp
)
4394 static const struct phy_reg phy_reg_init
[] = {
4401 rtl_writephy(tp
, 0x1f, 0x0000);
4402 rtl_patchphy(tp
, 0x11, 1 << 12);
4403 rtl_patchphy(tp
, 0x19, 1 << 13);
4404 rtl_patchphy(tp
, 0x10, 1 << 15);
4406 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
4409 static void rtl8105e_hw_phy_config(struct rtl8169_private
*tp
)
4411 static const struct phy_reg phy_reg_init
[] = {
4425 /* Disable ALDPS before ram code */
4426 rtl_writephy(tp
, 0x1f, 0x0000);
4427 rtl_writephy(tp
, 0x18, 0x0310);
4430 rtl_apply_firmware(tp
);
4432 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
4435 static void rtl8402_hw_phy_config(struct rtl8169_private
*tp
)
4437 /* Disable ALDPS before setting firmware */
4438 rtl_writephy(tp
, 0x1f, 0x0000);
4439 rtl_writephy(tp
, 0x18, 0x0310);
4442 rtl_apply_firmware(tp
);
4445 rtl_eri_write(tp
, 0x1b0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4446 rtl_writephy(tp
, 0x1f, 0x0004);
4447 rtl_writephy(tp
, 0x10, 0x401f);
4448 rtl_writephy(tp
, 0x19, 0x7030);
4449 rtl_writephy(tp
, 0x1f, 0x0000);
4452 static void rtl8106e_hw_phy_config(struct rtl8169_private
*tp
)
4454 static const struct phy_reg phy_reg_init
[] = {
4461 /* Disable ALDPS before ram code */
4462 rtl_writephy(tp
, 0x1f, 0x0000);
4463 rtl_writephy(tp
, 0x18, 0x0310);
4466 rtl_apply_firmware(tp
);
4468 rtl_eri_write(tp
, 0x1b0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4469 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
4471 rtl_eri_write(tp
, 0x1d0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4474 static void rtl_hw_phy_config(struct net_device
*dev
)
4476 struct rtl8169_private
*tp
= netdev_priv(dev
);
4478 rtl8169_print_mac_version(tp
);
4480 switch (tp
->mac_version
) {
4481 case RTL_GIGA_MAC_VER_01
:
4483 case RTL_GIGA_MAC_VER_02
:
4484 case RTL_GIGA_MAC_VER_03
:
4485 rtl8169s_hw_phy_config(tp
);
4487 case RTL_GIGA_MAC_VER_04
:
4488 rtl8169sb_hw_phy_config(tp
);
4490 case RTL_GIGA_MAC_VER_05
:
4491 rtl8169scd_hw_phy_config(tp
);
4493 case RTL_GIGA_MAC_VER_06
:
4494 rtl8169sce_hw_phy_config(tp
);
4496 case RTL_GIGA_MAC_VER_07
:
4497 case RTL_GIGA_MAC_VER_08
:
4498 case RTL_GIGA_MAC_VER_09
:
4499 rtl8102e_hw_phy_config(tp
);
4501 case RTL_GIGA_MAC_VER_11
:
4502 rtl8168bb_hw_phy_config(tp
);
4504 case RTL_GIGA_MAC_VER_12
:
4505 rtl8168bef_hw_phy_config(tp
);
4507 case RTL_GIGA_MAC_VER_17
:
4508 rtl8168bef_hw_phy_config(tp
);
4510 case RTL_GIGA_MAC_VER_18
:
4511 rtl8168cp_1_hw_phy_config(tp
);
4513 case RTL_GIGA_MAC_VER_19
:
4514 rtl8168c_1_hw_phy_config(tp
);
4516 case RTL_GIGA_MAC_VER_20
:
4517 rtl8168c_2_hw_phy_config(tp
);
4519 case RTL_GIGA_MAC_VER_21
:
4520 rtl8168c_3_hw_phy_config(tp
);
4522 case RTL_GIGA_MAC_VER_22
:
4523 rtl8168c_4_hw_phy_config(tp
);
4525 case RTL_GIGA_MAC_VER_23
:
4526 case RTL_GIGA_MAC_VER_24
:
4527 rtl8168cp_2_hw_phy_config(tp
);
4529 case RTL_GIGA_MAC_VER_25
:
4530 rtl8168d_1_hw_phy_config(tp
);
4532 case RTL_GIGA_MAC_VER_26
:
4533 rtl8168d_2_hw_phy_config(tp
);
4535 case RTL_GIGA_MAC_VER_27
:
4536 rtl8168d_3_hw_phy_config(tp
);
4538 case RTL_GIGA_MAC_VER_28
:
4539 rtl8168d_4_hw_phy_config(tp
);
4541 case RTL_GIGA_MAC_VER_29
:
4542 case RTL_GIGA_MAC_VER_30
:
4543 rtl8105e_hw_phy_config(tp
);
4545 case RTL_GIGA_MAC_VER_31
:
4548 case RTL_GIGA_MAC_VER_32
:
4549 case RTL_GIGA_MAC_VER_33
:
4550 rtl8168e_1_hw_phy_config(tp
);
4552 case RTL_GIGA_MAC_VER_34
:
4553 rtl8168e_2_hw_phy_config(tp
);
4555 case RTL_GIGA_MAC_VER_35
:
4556 rtl8168f_1_hw_phy_config(tp
);
4558 case RTL_GIGA_MAC_VER_36
:
4559 rtl8168f_2_hw_phy_config(tp
);
4562 case RTL_GIGA_MAC_VER_37
:
4563 rtl8402_hw_phy_config(tp
);
4566 case RTL_GIGA_MAC_VER_38
:
4567 rtl8411_hw_phy_config(tp
);
4570 case RTL_GIGA_MAC_VER_39
:
4571 rtl8106e_hw_phy_config(tp
);
4574 case RTL_GIGA_MAC_VER_40
:
4575 rtl8168g_1_hw_phy_config(tp
);
4577 case RTL_GIGA_MAC_VER_42
:
4578 case RTL_GIGA_MAC_VER_43
:
4579 case RTL_GIGA_MAC_VER_44
:
4580 rtl8168g_2_hw_phy_config(tp
);
4582 case RTL_GIGA_MAC_VER_45
:
4583 case RTL_GIGA_MAC_VER_47
:
4584 rtl8168h_1_hw_phy_config(tp
);
4586 case RTL_GIGA_MAC_VER_46
:
4587 case RTL_GIGA_MAC_VER_48
:
4588 rtl8168h_2_hw_phy_config(tp
);
4591 case RTL_GIGA_MAC_VER_49
:
4592 rtl8168ep_1_hw_phy_config(tp
);
4594 case RTL_GIGA_MAC_VER_50
:
4595 case RTL_GIGA_MAC_VER_51
:
4596 rtl8168ep_2_hw_phy_config(tp
);
4599 case RTL_GIGA_MAC_VER_41
:
4605 static void rtl_phy_work(struct rtl8169_private
*tp
)
4607 struct timer_list
*timer
= &tp
->timer
;
4608 void __iomem
*ioaddr
= tp
->mmio_addr
;
4609 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
4611 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
4613 if (tp
->phy_reset_pending(tp
)) {
4615 * A busy loop could burn quite a few cycles on nowadays CPU.
4616 * Let's delay the execution of the timer for a few ticks.
4622 if (tp
->link_ok(ioaddr
))
4625 netif_dbg(tp
, link
, tp
->dev
, "PHY reset until link up\n");
4627 tp
->phy_reset_enable(tp
);
4630 mod_timer(timer
, jiffies
+ timeout
);
4633 static void rtl_schedule_task(struct rtl8169_private
*tp
, enum rtl_flag flag
)
4635 if (!test_and_set_bit(flag
, tp
->wk
.flags
))
4636 schedule_work(&tp
->wk
.work
);
4639 static void rtl8169_phy_timer(struct timer_list
*t
)
4641 struct rtl8169_private
*tp
= from_timer(tp
, t
, timer
);
4643 rtl_schedule_task(tp
, RTL_FLAG_TASK_PHY_PENDING
);
4646 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
4647 void __iomem
*ioaddr
)
4650 pci_release_regions(pdev
);
4651 pci_clear_mwi(pdev
);
4652 pci_disable_device(pdev
);
4656 DECLARE_RTL_COND(rtl_phy_reset_cond
)
4658 return tp
->phy_reset_pending(tp
);
4661 static void rtl8169_phy_reset(struct net_device
*dev
,
4662 struct rtl8169_private
*tp
)
4664 tp
->phy_reset_enable(tp
);
4665 rtl_msleep_loop_wait_low(tp
, &rtl_phy_reset_cond
, 1, 100);
4668 static bool rtl_tbi_enabled(struct rtl8169_private
*tp
)
4670 void __iomem
*ioaddr
= tp
->mmio_addr
;
4672 return (tp
->mac_version
== RTL_GIGA_MAC_VER_01
) &&
4673 (RTL_R8(PHYstatus
) & TBI_Enable
);
4676 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
4678 void __iomem
*ioaddr
= tp
->mmio_addr
;
4680 rtl_hw_phy_config(dev
);
4682 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
4683 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4687 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
4689 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
4690 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
4692 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
4693 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4695 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4696 rtl_writephy(tp
, 0x0b, 0x0000); //w 0x0b 15 0 0
4699 rtl8169_phy_reset(dev
, tp
);
4701 rtl8169_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
,
4702 ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
4703 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
4704 (tp
->mii
.supports_gmii
?
4705 ADVERTISED_1000baseT_Half
|
4706 ADVERTISED_1000baseT_Full
: 0));
4708 if (rtl_tbi_enabled(tp
))
4709 netif_info(tp
, link
, dev
, "TBI auto-negotiating\n");
4712 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
4714 void __iomem
*ioaddr
= tp
->mmio_addr
;
4718 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4720 RTL_W32(MAC4
, addr
[4] | addr
[5] << 8);
4723 RTL_W32(MAC0
, addr
[0] | addr
[1] << 8 | addr
[2] << 16 | addr
[3] << 24);
4726 if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
)
4727 rtl_rar_exgmac_set(tp
, addr
);
4729 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4731 rtl_unlock_work(tp
);
4734 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
4736 struct rtl8169_private
*tp
= netdev_priv(dev
);
4737 struct device
*d
= &tp
->pci_dev
->dev
;
4738 struct sockaddr
*addr
= p
;
4740 if (!is_valid_ether_addr(addr
->sa_data
))
4741 return -EADDRNOTAVAIL
;
4743 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
4745 pm_runtime_get_noresume(d
);
4747 if (pm_runtime_active(d
))
4748 rtl_rar_set(tp
, dev
->dev_addr
);
4750 pm_runtime_put_noidle(d
);
4755 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
4757 struct rtl8169_private
*tp
= netdev_priv(dev
);
4758 struct mii_ioctl_data
*data
= if_mii(ifr
);
4760 return netif_running(dev
) ? tp
->do_ioctl(tp
, data
, cmd
) : -ENODEV
;
4763 static int rtl_xmii_ioctl(struct rtl8169_private
*tp
,
4764 struct mii_ioctl_data
*data
, int cmd
)
4768 data
->phy_id
= 32; /* Internal PHY */
4772 data
->val_out
= rtl_readphy(tp
, data
->reg_num
& 0x1f);
4776 rtl_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
4782 static int rtl_tbi_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
4787 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8169_private
*tp
)
4789 if (tp
->features
& RTL_FEATURE_MSI
) {
4790 pci_disable_msi(pdev
);
4791 tp
->features
&= ~RTL_FEATURE_MSI
;
4795 static void rtl_init_mdio_ops(struct rtl8169_private
*tp
)
4797 struct mdio_ops
*ops
= &tp
->mdio_ops
;
4799 switch (tp
->mac_version
) {
4800 case RTL_GIGA_MAC_VER_27
:
4801 ops
->write
= r8168dp_1_mdio_write
;
4802 ops
->read
= r8168dp_1_mdio_read
;
4804 case RTL_GIGA_MAC_VER_28
:
4805 case RTL_GIGA_MAC_VER_31
:
4806 ops
->write
= r8168dp_2_mdio_write
;
4807 ops
->read
= r8168dp_2_mdio_read
;
4809 case RTL_GIGA_MAC_VER_40
:
4810 case RTL_GIGA_MAC_VER_41
:
4811 case RTL_GIGA_MAC_VER_42
:
4812 case RTL_GIGA_MAC_VER_43
:
4813 case RTL_GIGA_MAC_VER_44
:
4814 case RTL_GIGA_MAC_VER_45
:
4815 case RTL_GIGA_MAC_VER_46
:
4816 case RTL_GIGA_MAC_VER_47
:
4817 case RTL_GIGA_MAC_VER_48
:
4818 case RTL_GIGA_MAC_VER_49
:
4819 case RTL_GIGA_MAC_VER_50
:
4820 case RTL_GIGA_MAC_VER_51
:
4821 ops
->write
= r8168g_mdio_write
;
4822 ops
->read
= r8168g_mdio_read
;
4825 ops
->write
= r8169_mdio_write
;
4826 ops
->read
= r8169_mdio_read
;
4831 static void rtl_speed_down(struct rtl8169_private
*tp
)
4836 rtl_writephy(tp
, 0x1f, 0x0000);
4837 lpa
= rtl_readphy(tp
, MII_LPA
);
4839 if (lpa
& (LPA_10HALF
| LPA_10FULL
))
4840 adv
= ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
;
4841 else if (lpa
& (LPA_100HALF
| LPA_100FULL
))
4842 adv
= ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
4843 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
;
4845 adv
= ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
4846 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
4847 (tp
->mii
.supports_gmii
?
4848 ADVERTISED_1000baseT_Half
|
4849 ADVERTISED_1000baseT_Full
: 0);
4851 rtl8169_set_speed(tp
->dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
,
4855 static void rtl_wol_suspend_quirk(struct rtl8169_private
*tp
)
4857 void __iomem
*ioaddr
= tp
->mmio_addr
;
4859 switch (tp
->mac_version
) {
4860 case RTL_GIGA_MAC_VER_25
:
4861 case RTL_GIGA_MAC_VER_26
:
4862 case RTL_GIGA_MAC_VER_29
:
4863 case RTL_GIGA_MAC_VER_30
:
4864 case RTL_GIGA_MAC_VER_32
:
4865 case RTL_GIGA_MAC_VER_33
:
4866 case RTL_GIGA_MAC_VER_34
:
4867 case RTL_GIGA_MAC_VER_37
:
4868 case RTL_GIGA_MAC_VER_38
:
4869 case RTL_GIGA_MAC_VER_39
:
4870 case RTL_GIGA_MAC_VER_40
:
4871 case RTL_GIGA_MAC_VER_41
:
4872 case RTL_GIGA_MAC_VER_42
:
4873 case RTL_GIGA_MAC_VER_43
:
4874 case RTL_GIGA_MAC_VER_44
:
4875 case RTL_GIGA_MAC_VER_45
:
4876 case RTL_GIGA_MAC_VER_46
:
4877 case RTL_GIGA_MAC_VER_47
:
4878 case RTL_GIGA_MAC_VER_48
:
4879 case RTL_GIGA_MAC_VER_49
:
4880 case RTL_GIGA_MAC_VER_50
:
4881 case RTL_GIGA_MAC_VER_51
:
4882 RTL_W32(RxConfig
, RTL_R32(RxConfig
) |
4883 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
);
4890 static bool rtl_wol_pll_power_down(struct rtl8169_private
*tp
)
4892 if (!(__rtl8169_get_wol(tp
) & WAKE_ANY
))
4896 rtl_wol_suspend_quirk(tp
);
4901 static void r810x_phy_power_down(struct rtl8169_private
*tp
)
4903 rtl_writephy(tp
, 0x1f, 0x0000);
4904 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
4907 static void r810x_phy_power_up(struct rtl8169_private
*tp
)
4909 rtl_writephy(tp
, 0x1f, 0x0000);
4910 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
4913 static void r810x_pll_power_down(struct rtl8169_private
*tp
)
4915 void __iomem
*ioaddr
= tp
->mmio_addr
;
4917 if (rtl_wol_pll_power_down(tp
))
4920 r810x_phy_power_down(tp
);
4922 switch (tp
->mac_version
) {
4923 case RTL_GIGA_MAC_VER_07
:
4924 case RTL_GIGA_MAC_VER_08
:
4925 case RTL_GIGA_MAC_VER_09
:
4926 case RTL_GIGA_MAC_VER_10
:
4927 case RTL_GIGA_MAC_VER_13
:
4928 case RTL_GIGA_MAC_VER_16
:
4931 RTL_W8(PMCH
, RTL_R8(PMCH
) & ~0x80);
4936 static void r810x_pll_power_up(struct rtl8169_private
*tp
)
4938 void __iomem
*ioaddr
= tp
->mmio_addr
;
4940 r810x_phy_power_up(tp
);
4942 switch (tp
->mac_version
) {
4943 case RTL_GIGA_MAC_VER_07
:
4944 case RTL_GIGA_MAC_VER_08
:
4945 case RTL_GIGA_MAC_VER_09
:
4946 case RTL_GIGA_MAC_VER_10
:
4947 case RTL_GIGA_MAC_VER_13
:
4948 case RTL_GIGA_MAC_VER_16
:
4950 case RTL_GIGA_MAC_VER_47
:
4951 case RTL_GIGA_MAC_VER_48
:
4952 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0xc0);
4955 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0x80);
4960 static void r8168_phy_power_up(struct rtl8169_private
*tp
)
4962 rtl_writephy(tp
, 0x1f, 0x0000);
4963 switch (tp
->mac_version
) {
4964 case RTL_GIGA_MAC_VER_11
:
4965 case RTL_GIGA_MAC_VER_12
:
4966 case RTL_GIGA_MAC_VER_17
:
4967 case RTL_GIGA_MAC_VER_18
:
4968 case RTL_GIGA_MAC_VER_19
:
4969 case RTL_GIGA_MAC_VER_20
:
4970 case RTL_GIGA_MAC_VER_21
:
4971 case RTL_GIGA_MAC_VER_22
:
4972 case RTL_GIGA_MAC_VER_23
:
4973 case RTL_GIGA_MAC_VER_24
:
4974 case RTL_GIGA_MAC_VER_25
:
4975 case RTL_GIGA_MAC_VER_26
:
4976 case RTL_GIGA_MAC_VER_27
:
4977 case RTL_GIGA_MAC_VER_28
:
4978 case RTL_GIGA_MAC_VER_31
:
4979 rtl_writephy(tp
, 0x0e, 0x0000);
4984 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
4987 static void r8168_phy_power_down(struct rtl8169_private
*tp
)
4989 rtl_writephy(tp
, 0x1f, 0x0000);
4990 switch (tp
->mac_version
) {
4991 case RTL_GIGA_MAC_VER_32
:
4992 case RTL_GIGA_MAC_VER_33
:
4993 case RTL_GIGA_MAC_VER_40
:
4994 case RTL_GIGA_MAC_VER_41
:
4995 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
| BMCR_PDOWN
);
4998 case RTL_GIGA_MAC_VER_11
:
4999 case RTL_GIGA_MAC_VER_12
:
5000 case RTL_GIGA_MAC_VER_17
:
5001 case RTL_GIGA_MAC_VER_18
:
5002 case RTL_GIGA_MAC_VER_19
:
5003 case RTL_GIGA_MAC_VER_20
:
5004 case RTL_GIGA_MAC_VER_21
:
5005 case RTL_GIGA_MAC_VER_22
:
5006 case RTL_GIGA_MAC_VER_23
:
5007 case RTL_GIGA_MAC_VER_24
:
5008 case RTL_GIGA_MAC_VER_25
:
5009 case RTL_GIGA_MAC_VER_26
:
5010 case RTL_GIGA_MAC_VER_27
:
5011 case RTL_GIGA_MAC_VER_28
:
5012 case RTL_GIGA_MAC_VER_31
:
5013 rtl_writephy(tp
, 0x0e, 0x0200);
5015 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
5020 static void r8168_pll_power_down(struct rtl8169_private
*tp
)
5022 void __iomem
*ioaddr
= tp
->mmio_addr
;
5024 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
5025 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
5026 tp
->mac_version
== RTL_GIGA_MAC_VER_31
||
5027 tp
->mac_version
== RTL_GIGA_MAC_VER_49
||
5028 tp
->mac_version
== RTL_GIGA_MAC_VER_50
||
5029 tp
->mac_version
== RTL_GIGA_MAC_VER_51
) &&
5030 r8168_check_dash(tp
)) {
5034 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_23
||
5035 tp
->mac_version
== RTL_GIGA_MAC_VER_24
) &&
5036 (RTL_R16(CPlusCmd
) & ASF
)) {
5040 if (tp
->mac_version
== RTL_GIGA_MAC_VER_32
||
5041 tp
->mac_version
== RTL_GIGA_MAC_VER_33
)
5042 rtl_ephy_write(tp
, 0x19, 0xff64);
5044 if (rtl_wol_pll_power_down(tp
))
5047 r8168_phy_power_down(tp
);
5049 switch (tp
->mac_version
) {
5050 case RTL_GIGA_MAC_VER_25
:
5051 case RTL_GIGA_MAC_VER_26
:
5052 case RTL_GIGA_MAC_VER_27
:
5053 case RTL_GIGA_MAC_VER_28
:
5054 case RTL_GIGA_MAC_VER_31
:
5055 case RTL_GIGA_MAC_VER_32
:
5056 case RTL_GIGA_MAC_VER_33
:
5057 case RTL_GIGA_MAC_VER_44
:
5058 case RTL_GIGA_MAC_VER_45
:
5059 case RTL_GIGA_MAC_VER_46
:
5060 case RTL_GIGA_MAC_VER_50
:
5061 case RTL_GIGA_MAC_VER_51
:
5062 RTL_W8(PMCH
, RTL_R8(PMCH
) & ~0x80);
5064 case RTL_GIGA_MAC_VER_40
:
5065 case RTL_GIGA_MAC_VER_41
:
5066 case RTL_GIGA_MAC_VER_49
:
5067 rtl_w0w1_eri(tp
, 0x1a8, ERIAR_MASK_1111
, 0x00000000,
5068 0xfc000000, ERIAR_EXGMAC
);
5069 RTL_W8(PMCH
, RTL_R8(PMCH
) & ~0x80);
5074 static void r8168_pll_power_up(struct rtl8169_private
*tp
)
5076 void __iomem
*ioaddr
= tp
->mmio_addr
;
5078 switch (tp
->mac_version
) {
5079 case RTL_GIGA_MAC_VER_25
:
5080 case RTL_GIGA_MAC_VER_26
:
5081 case RTL_GIGA_MAC_VER_27
:
5082 case RTL_GIGA_MAC_VER_28
:
5083 case RTL_GIGA_MAC_VER_31
:
5084 case RTL_GIGA_MAC_VER_32
:
5085 case RTL_GIGA_MAC_VER_33
:
5086 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0x80);
5088 case RTL_GIGA_MAC_VER_44
:
5089 case RTL_GIGA_MAC_VER_45
:
5090 case RTL_GIGA_MAC_VER_46
:
5091 case RTL_GIGA_MAC_VER_50
:
5092 case RTL_GIGA_MAC_VER_51
:
5093 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0xc0);
5095 case RTL_GIGA_MAC_VER_40
:
5096 case RTL_GIGA_MAC_VER_41
:
5097 case RTL_GIGA_MAC_VER_49
:
5098 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0xc0);
5099 rtl_w0w1_eri(tp
, 0x1a8, ERIAR_MASK_1111
, 0xfc000000,
5100 0x00000000, ERIAR_EXGMAC
);
5104 r8168_phy_power_up(tp
);
5107 static void rtl_generic_op(struct rtl8169_private
*tp
,
5108 void (*op
)(struct rtl8169_private
*))
5114 static void rtl_pll_power_down(struct rtl8169_private
*tp
)
5116 rtl_generic_op(tp
, tp
->pll_power_ops
.down
);
5119 static void rtl_pll_power_up(struct rtl8169_private
*tp
)
5121 rtl_generic_op(tp
, tp
->pll_power_ops
.up
);
5124 static void rtl_init_pll_power_ops(struct rtl8169_private
*tp
)
5126 struct pll_power_ops
*ops
= &tp
->pll_power_ops
;
5128 switch (tp
->mac_version
) {
5129 case RTL_GIGA_MAC_VER_07
:
5130 case RTL_GIGA_MAC_VER_08
:
5131 case RTL_GIGA_MAC_VER_09
:
5132 case RTL_GIGA_MAC_VER_10
:
5133 case RTL_GIGA_MAC_VER_16
:
5134 case RTL_GIGA_MAC_VER_29
:
5135 case RTL_GIGA_MAC_VER_30
:
5136 case RTL_GIGA_MAC_VER_37
:
5137 case RTL_GIGA_MAC_VER_39
:
5138 case RTL_GIGA_MAC_VER_43
:
5139 case RTL_GIGA_MAC_VER_47
:
5140 case RTL_GIGA_MAC_VER_48
:
5141 ops
->down
= r810x_pll_power_down
;
5142 ops
->up
= r810x_pll_power_up
;
5145 case RTL_GIGA_MAC_VER_11
:
5146 case RTL_GIGA_MAC_VER_12
:
5147 case RTL_GIGA_MAC_VER_17
:
5148 case RTL_GIGA_MAC_VER_18
:
5149 case RTL_GIGA_MAC_VER_19
:
5150 case RTL_GIGA_MAC_VER_20
:
5151 case RTL_GIGA_MAC_VER_21
:
5152 case RTL_GIGA_MAC_VER_22
:
5153 case RTL_GIGA_MAC_VER_23
:
5154 case RTL_GIGA_MAC_VER_24
:
5155 case RTL_GIGA_MAC_VER_25
:
5156 case RTL_GIGA_MAC_VER_26
:
5157 case RTL_GIGA_MAC_VER_27
:
5158 case RTL_GIGA_MAC_VER_28
:
5159 case RTL_GIGA_MAC_VER_31
:
5160 case RTL_GIGA_MAC_VER_32
:
5161 case RTL_GIGA_MAC_VER_33
:
5162 case RTL_GIGA_MAC_VER_34
:
5163 case RTL_GIGA_MAC_VER_35
:
5164 case RTL_GIGA_MAC_VER_36
:
5165 case RTL_GIGA_MAC_VER_38
:
5166 case RTL_GIGA_MAC_VER_40
:
5167 case RTL_GIGA_MAC_VER_41
:
5168 case RTL_GIGA_MAC_VER_42
:
5169 case RTL_GIGA_MAC_VER_44
:
5170 case RTL_GIGA_MAC_VER_45
:
5171 case RTL_GIGA_MAC_VER_46
:
5172 case RTL_GIGA_MAC_VER_49
:
5173 case RTL_GIGA_MAC_VER_50
:
5174 case RTL_GIGA_MAC_VER_51
:
5175 ops
->down
= r8168_pll_power_down
;
5176 ops
->up
= r8168_pll_power_up
;
5186 static void rtl_init_rxcfg(struct rtl8169_private
*tp
)
5188 void __iomem
*ioaddr
= tp
->mmio_addr
;
5190 switch (tp
->mac_version
) {
5191 case RTL_GIGA_MAC_VER_01
:
5192 case RTL_GIGA_MAC_VER_02
:
5193 case RTL_GIGA_MAC_VER_03
:
5194 case RTL_GIGA_MAC_VER_04
:
5195 case RTL_GIGA_MAC_VER_05
:
5196 case RTL_GIGA_MAC_VER_06
:
5197 case RTL_GIGA_MAC_VER_10
:
5198 case RTL_GIGA_MAC_VER_11
:
5199 case RTL_GIGA_MAC_VER_12
:
5200 case RTL_GIGA_MAC_VER_13
:
5201 case RTL_GIGA_MAC_VER_14
:
5202 case RTL_GIGA_MAC_VER_15
:
5203 case RTL_GIGA_MAC_VER_16
:
5204 case RTL_GIGA_MAC_VER_17
:
5205 RTL_W32(RxConfig
, RX_FIFO_THRESH
| RX_DMA_BURST
);
5207 case RTL_GIGA_MAC_VER_18
:
5208 case RTL_GIGA_MAC_VER_19
:
5209 case RTL_GIGA_MAC_VER_20
:
5210 case RTL_GIGA_MAC_VER_21
:
5211 case RTL_GIGA_MAC_VER_22
:
5212 case RTL_GIGA_MAC_VER_23
:
5213 case RTL_GIGA_MAC_VER_24
:
5214 case RTL_GIGA_MAC_VER_34
:
5215 case RTL_GIGA_MAC_VER_35
:
5216 RTL_W32(RxConfig
, RX128_INT_EN
| RX_MULTI_EN
| RX_DMA_BURST
);
5218 case RTL_GIGA_MAC_VER_40
:
5219 case RTL_GIGA_MAC_VER_41
:
5220 case RTL_GIGA_MAC_VER_42
:
5221 case RTL_GIGA_MAC_VER_43
:
5222 case RTL_GIGA_MAC_VER_44
:
5223 case RTL_GIGA_MAC_VER_45
:
5224 case RTL_GIGA_MAC_VER_46
:
5225 case RTL_GIGA_MAC_VER_47
:
5226 case RTL_GIGA_MAC_VER_48
:
5227 case RTL_GIGA_MAC_VER_49
:
5228 case RTL_GIGA_MAC_VER_50
:
5229 case RTL_GIGA_MAC_VER_51
:
5230 RTL_W32(RxConfig
, RX128_INT_EN
| RX_MULTI_EN
| RX_DMA_BURST
| RX_EARLY_OFF
);
5233 RTL_W32(RxConfig
, RX128_INT_EN
| RX_DMA_BURST
);
5238 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
5240 tp
->dirty_tx
= tp
->cur_tx
= tp
->cur_rx
= 0;
5243 static void rtl_hw_jumbo_enable(struct rtl8169_private
*tp
)
5245 void __iomem
*ioaddr
= tp
->mmio_addr
;
5247 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
5248 rtl_generic_op(tp
, tp
->jumbo_ops
.enable
);
5249 RTL_W8(Cfg9346
, Cfg9346_Lock
);
5252 static void rtl_hw_jumbo_disable(struct rtl8169_private
*tp
)
5254 void __iomem
*ioaddr
= tp
->mmio_addr
;
5256 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
5257 rtl_generic_op(tp
, tp
->jumbo_ops
.disable
);
5258 RTL_W8(Cfg9346
, Cfg9346_Lock
);
5261 static void r8168c_hw_jumbo_enable(struct rtl8169_private
*tp
)
5263 void __iomem
*ioaddr
= tp
->mmio_addr
;
5265 RTL_W8(Config3
, RTL_R8(Config3
) | Jumbo_En0
);
5266 RTL_W8(Config4
, RTL_R8(Config4
) | Jumbo_En1
);
5267 rtl_tx_performance_tweak(tp
->pci_dev
, PCI_EXP_DEVCTL_READRQ_512B
);
5270 static void r8168c_hw_jumbo_disable(struct rtl8169_private
*tp
)
5272 void __iomem
*ioaddr
= tp
->mmio_addr
;
5274 RTL_W8(Config3
, RTL_R8(Config3
) & ~Jumbo_En0
);
5275 RTL_W8(Config4
, RTL_R8(Config4
) & ~Jumbo_En1
);
5276 rtl_tx_performance_tweak(tp
->pci_dev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5279 static void r8168dp_hw_jumbo_enable(struct rtl8169_private
*tp
)
5281 void __iomem
*ioaddr
= tp
->mmio_addr
;
5283 RTL_W8(Config3
, RTL_R8(Config3
) | Jumbo_En0
);
5286 static void r8168dp_hw_jumbo_disable(struct rtl8169_private
*tp
)
5288 void __iomem
*ioaddr
= tp
->mmio_addr
;
5290 RTL_W8(Config3
, RTL_R8(Config3
) & ~Jumbo_En0
);
5293 static void r8168e_hw_jumbo_enable(struct rtl8169_private
*tp
)
5295 void __iomem
*ioaddr
= tp
->mmio_addr
;
5297 RTL_W8(MaxTxPacketSize
, 0x3f);
5298 RTL_W8(Config3
, RTL_R8(Config3
) | Jumbo_En0
);
5299 RTL_W8(Config4
, RTL_R8(Config4
) | 0x01);
5300 rtl_tx_performance_tweak(tp
->pci_dev
, PCI_EXP_DEVCTL_READRQ_512B
);
5303 static void r8168e_hw_jumbo_disable(struct rtl8169_private
*tp
)
5305 void __iomem
*ioaddr
= tp
->mmio_addr
;
5307 RTL_W8(MaxTxPacketSize
, 0x0c);
5308 RTL_W8(Config3
, RTL_R8(Config3
) & ~Jumbo_En0
);
5309 RTL_W8(Config4
, RTL_R8(Config4
) & ~0x01);
5310 rtl_tx_performance_tweak(tp
->pci_dev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5313 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private
*tp
)
5315 rtl_tx_performance_tweak(tp
->pci_dev
,
5316 PCI_EXP_DEVCTL_READRQ_512B
| PCI_EXP_DEVCTL_NOSNOOP_EN
);
5319 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private
*tp
)
5321 rtl_tx_performance_tweak(tp
->pci_dev
,
5322 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
5325 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private
*tp
)
5327 void __iomem
*ioaddr
= tp
->mmio_addr
;
5329 r8168b_0_hw_jumbo_enable(tp
);
5331 RTL_W8(Config4
, RTL_R8(Config4
) | (1 << 0));
5334 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private
*tp
)
5336 void __iomem
*ioaddr
= tp
->mmio_addr
;
5338 r8168b_0_hw_jumbo_disable(tp
);
5340 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
5343 static void rtl_init_jumbo_ops(struct rtl8169_private
*tp
)
5345 struct jumbo_ops
*ops
= &tp
->jumbo_ops
;
5347 switch (tp
->mac_version
) {
5348 case RTL_GIGA_MAC_VER_11
:
5349 ops
->disable
= r8168b_0_hw_jumbo_disable
;
5350 ops
->enable
= r8168b_0_hw_jumbo_enable
;
5352 case RTL_GIGA_MAC_VER_12
:
5353 case RTL_GIGA_MAC_VER_17
:
5354 ops
->disable
= r8168b_1_hw_jumbo_disable
;
5355 ops
->enable
= r8168b_1_hw_jumbo_enable
;
5357 case RTL_GIGA_MAC_VER_18
: /* Wild guess. Needs info from Realtek. */
5358 case RTL_GIGA_MAC_VER_19
:
5359 case RTL_GIGA_MAC_VER_20
:
5360 case RTL_GIGA_MAC_VER_21
: /* Wild guess. Needs info from Realtek. */
5361 case RTL_GIGA_MAC_VER_22
:
5362 case RTL_GIGA_MAC_VER_23
:
5363 case RTL_GIGA_MAC_VER_24
:
5364 case RTL_GIGA_MAC_VER_25
:
5365 case RTL_GIGA_MAC_VER_26
:
5366 ops
->disable
= r8168c_hw_jumbo_disable
;
5367 ops
->enable
= r8168c_hw_jumbo_enable
;
5369 case RTL_GIGA_MAC_VER_27
:
5370 case RTL_GIGA_MAC_VER_28
:
5371 ops
->disable
= r8168dp_hw_jumbo_disable
;
5372 ops
->enable
= r8168dp_hw_jumbo_enable
;
5374 case RTL_GIGA_MAC_VER_31
: /* Wild guess. Needs info from Realtek. */
5375 case RTL_GIGA_MAC_VER_32
:
5376 case RTL_GIGA_MAC_VER_33
:
5377 case RTL_GIGA_MAC_VER_34
:
5378 ops
->disable
= r8168e_hw_jumbo_disable
;
5379 ops
->enable
= r8168e_hw_jumbo_enable
;
5383 * No action needed for jumbo frames with 8169.
5384 * No jumbo for 810x at all.
5386 case RTL_GIGA_MAC_VER_40
:
5387 case RTL_GIGA_MAC_VER_41
:
5388 case RTL_GIGA_MAC_VER_42
:
5389 case RTL_GIGA_MAC_VER_43
:
5390 case RTL_GIGA_MAC_VER_44
:
5391 case RTL_GIGA_MAC_VER_45
:
5392 case RTL_GIGA_MAC_VER_46
:
5393 case RTL_GIGA_MAC_VER_47
:
5394 case RTL_GIGA_MAC_VER_48
:
5395 case RTL_GIGA_MAC_VER_49
:
5396 case RTL_GIGA_MAC_VER_50
:
5397 case RTL_GIGA_MAC_VER_51
:
5399 ops
->disable
= NULL
;
5405 DECLARE_RTL_COND(rtl_chipcmd_cond
)
5407 void __iomem
*ioaddr
= tp
->mmio_addr
;
5409 return RTL_R8(ChipCmd
) & CmdReset
;
5412 static void rtl_hw_reset(struct rtl8169_private
*tp
)
5414 void __iomem
*ioaddr
= tp
->mmio_addr
;
5416 RTL_W8(ChipCmd
, CmdReset
);
5418 rtl_udelay_loop_wait_low(tp
, &rtl_chipcmd_cond
, 100, 100);
5421 static void rtl_request_uncached_firmware(struct rtl8169_private
*tp
)
5423 struct rtl_fw
*rtl_fw
;
5427 name
= rtl_lookup_firmware_name(tp
);
5429 goto out_no_firmware
;
5431 rtl_fw
= kzalloc(sizeof(*rtl_fw
), GFP_KERNEL
);
5435 rc
= request_firmware(&rtl_fw
->fw
, name
, &tp
->pci_dev
->dev
);
5439 rc
= rtl_check_firmware(tp
, rtl_fw
);
5441 goto err_release_firmware
;
5443 tp
->rtl_fw
= rtl_fw
;
5447 err_release_firmware
:
5448 release_firmware(rtl_fw
->fw
);
5452 netif_warn(tp
, ifup
, tp
->dev
, "unable to load firmware patch %s (%d)\n",
5459 static void rtl_request_firmware(struct rtl8169_private
*tp
)
5461 if (IS_ERR(tp
->rtl_fw
))
5462 rtl_request_uncached_firmware(tp
);
5465 static void rtl_rx_close(struct rtl8169_private
*tp
)
5467 void __iomem
*ioaddr
= tp
->mmio_addr
;
5469 RTL_W32(RxConfig
, RTL_R32(RxConfig
) & ~RX_CONFIG_ACCEPT_MASK
);
5472 DECLARE_RTL_COND(rtl_npq_cond
)
5474 void __iomem
*ioaddr
= tp
->mmio_addr
;
5476 return RTL_R8(TxPoll
) & NPQ
;
5479 DECLARE_RTL_COND(rtl_txcfg_empty_cond
)
5481 void __iomem
*ioaddr
= tp
->mmio_addr
;
5483 return RTL_R32(TxConfig
) & TXCFG_EMPTY
;
5486 static void rtl8169_hw_reset(struct rtl8169_private
*tp
)
5488 void __iomem
*ioaddr
= tp
->mmio_addr
;
5490 /* Disable interrupts */
5491 rtl8169_irq_mask_and_ack(tp
);
5495 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
5496 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
5497 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
5498 rtl_udelay_loop_wait_low(tp
, &rtl_npq_cond
, 20, 42*42);
5499 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
||
5500 tp
->mac_version
== RTL_GIGA_MAC_VER_35
||
5501 tp
->mac_version
== RTL_GIGA_MAC_VER_36
||
5502 tp
->mac_version
== RTL_GIGA_MAC_VER_37
||
5503 tp
->mac_version
== RTL_GIGA_MAC_VER_38
||
5504 tp
->mac_version
== RTL_GIGA_MAC_VER_40
||
5505 tp
->mac_version
== RTL_GIGA_MAC_VER_41
||
5506 tp
->mac_version
== RTL_GIGA_MAC_VER_42
||
5507 tp
->mac_version
== RTL_GIGA_MAC_VER_43
||
5508 tp
->mac_version
== RTL_GIGA_MAC_VER_44
||
5509 tp
->mac_version
== RTL_GIGA_MAC_VER_45
||
5510 tp
->mac_version
== RTL_GIGA_MAC_VER_46
||
5511 tp
->mac_version
== RTL_GIGA_MAC_VER_47
||
5512 tp
->mac_version
== RTL_GIGA_MAC_VER_48
||
5513 tp
->mac_version
== RTL_GIGA_MAC_VER_49
||
5514 tp
->mac_version
== RTL_GIGA_MAC_VER_50
||
5515 tp
->mac_version
== RTL_GIGA_MAC_VER_51
) {
5516 RTL_W8(ChipCmd
, RTL_R8(ChipCmd
) | StopReq
);
5517 rtl_udelay_loop_wait_high(tp
, &rtl_txcfg_empty_cond
, 100, 666);
5519 RTL_W8(ChipCmd
, RTL_R8(ChipCmd
) | StopReq
);
5526 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
5528 void __iomem
*ioaddr
= tp
->mmio_addr
;
5530 /* Set DMA burst size and Interframe Gap Time */
5531 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
5532 (InterFrameGap
<< TxInterFrameGapShift
));
5535 static void rtl_hw_start(struct net_device
*dev
)
5537 struct rtl8169_private
*tp
= netdev_priv(dev
);
5541 rtl_irq_enable_all(tp
);
5544 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
5545 void __iomem
*ioaddr
)
5548 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5549 * register to be written before TxDescAddrLow to work.
5550 * Switching from MMIO to I/O access fixes the issue as well.
5552 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
5553 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_BIT_MASK(32));
5554 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
5555 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_BIT_MASK(32));
5558 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
5562 cmd
= RTL_R16(CPlusCmd
);
5563 RTL_W16(CPlusCmd
, cmd
);
5567 static void rtl_set_rx_max_size(void __iomem
*ioaddr
, unsigned int rx_buf_sz
)
5569 /* Low hurts. Let's disable the filtering. */
5570 RTL_W16(RxMaxSize
, rx_buf_sz
+ 1);
5573 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
5575 static const struct rtl_cfg2_info
{
5580 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
5581 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
5582 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
5583 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
5585 const struct rtl_cfg2_info
*p
= cfg2_info
;
5589 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
5590 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
5591 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
5592 RTL_W32(0x7c, p
->val
);
5598 static void rtl_set_rx_mode(struct net_device
*dev
)
5600 struct rtl8169_private
*tp
= netdev_priv(dev
);
5601 void __iomem
*ioaddr
= tp
->mmio_addr
;
5602 u32 mc_filter
[2]; /* Multicast hash filter */
5606 if (dev
->flags
& IFF_PROMISC
) {
5607 /* Unconditionally log net taps. */
5608 netif_notice(tp
, link
, dev
, "Promiscuous mode enabled\n");
5610 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
5612 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
5613 } else if ((netdev_mc_count(dev
) > multicast_filter_limit
) ||
5614 (dev
->flags
& IFF_ALLMULTI
)) {
5615 /* Too many to filter perfectly -- accept all multicasts. */
5616 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
5617 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
5619 struct netdev_hw_addr
*ha
;
5621 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
5622 mc_filter
[1] = mc_filter
[0] = 0;
5623 netdev_for_each_mc_addr(ha
, dev
) {
5624 int bit_nr
= ether_crc(ETH_ALEN
, ha
->addr
) >> 26;
5625 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
5626 rx_mode
|= AcceptMulticast
;
5630 if (dev
->features
& NETIF_F_RXALL
)
5631 rx_mode
|= (AcceptErr
| AcceptRunt
);
5633 tmp
= (RTL_R32(RxConfig
) & ~RX_CONFIG_ACCEPT_MASK
) | rx_mode
;
5635 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
5636 u32 data
= mc_filter
[0];
5638 mc_filter
[0] = swab32(mc_filter
[1]);
5639 mc_filter
[1] = swab32(data
);
5642 if (tp
->mac_version
== RTL_GIGA_MAC_VER_35
)
5643 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
5645 RTL_W32(MAR0
+ 4, mc_filter
[1]);
5646 RTL_W32(MAR0
+ 0, mc_filter
[0]);
5648 RTL_W32(RxConfig
, tmp
);
5651 static void rtl_hw_start_8169(struct net_device
*dev
)
5653 struct rtl8169_private
*tp
= netdev_priv(dev
);
5654 void __iomem
*ioaddr
= tp
->mmio_addr
;
5655 struct pci_dev
*pdev
= tp
->pci_dev
;
5657 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
5658 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
5659 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
5662 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
5663 if (tp
->mac_version
== RTL_GIGA_MAC_VER_01
||
5664 tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
5665 tp
->mac_version
== RTL_GIGA_MAC_VER_03
||
5666 tp
->mac_version
== RTL_GIGA_MAC_VER_04
)
5667 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
5671 RTL_W8(EarlyTxThres
, NoEarlyTx
);
5673 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
5675 if (tp
->mac_version
== RTL_GIGA_MAC_VER_01
||
5676 tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
5677 tp
->mac_version
== RTL_GIGA_MAC_VER_03
||
5678 tp
->mac_version
== RTL_GIGA_MAC_VER_04
)
5679 rtl_set_rx_tx_config_registers(tp
);
5681 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
5683 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
5684 tp
->mac_version
== RTL_GIGA_MAC_VER_03
) {
5685 dprintk("Set MAC Reg C+CR Offset 0xe0. "
5686 "Bit-3 and bit-14 MUST be 1\n");
5687 tp
->cp_cmd
|= (1 << 14);
5690 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
5692 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
5695 * Undocumented corner. Supposedly:
5696 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5698 RTL_W16(IntrMitigate
, 0x0000);
5700 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
5702 if (tp
->mac_version
!= RTL_GIGA_MAC_VER_01
&&
5703 tp
->mac_version
!= RTL_GIGA_MAC_VER_02
&&
5704 tp
->mac_version
!= RTL_GIGA_MAC_VER_03
&&
5705 tp
->mac_version
!= RTL_GIGA_MAC_VER_04
) {
5706 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
5707 rtl_set_rx_tx_config_registers(tp
);
5710 RTL_W8(Cfg9346
, Cfg9346_Lock
);
5712 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5715 RTL_W32(RxMissed
, 0);
5717 rtl_set_rx_mode(dev
);
5719 /* no early-rx interrupts */
5720 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
5723 static void rtl_csi_write(struct rtl8169_private
*tp
, int addr
, int value
)
5725 if (tp
->csi_ops
.write
)
5726 tp
->csi_ops
.write(tp
, addr
, value
);
5729 static u32
rtl_csi_read(struct rtl8169_private
*tp
, int addr
)
5731 return tp
->csi_ops
.read
? tp
->csi_ops
.read(tp
, addr
) : ~0;
5734 static void rtl_csi_access_enable(struct rtl8169_private
*tp
, u32 bits
)
5738 csi
= rtl_csi_read(tp
, 0x070c) & 0x00ffffff;
5739 rtl_csi_write(tp
, 0x070c, csi
| bits
);
5742 static void rtl_csi_access_enable_1(struct rtl8169_private
*tp
)
5744 rtl_csi_access_enable(tp
, 0x17000000);
5747 static void rtl_csi_access_enable_2(struct rtl8169_private
*tp
)
5749 rtl_csi_access_enable(tp
, 0x27000000);
5752 DECLARE_RTL_COND(rtl_csiar_cond
)
5754 void __iomem
*ioaddr
= tp
->mmio_addr
;
5756 return RTL_R32(CSIAR
) & CSIAR_FLAG
;
5759 static void r8169_csi_write(struct rtl8169_private
*tp
, int addr
, int value
)
5761 void __iomem
*ioaddr
= tp
->mmio_addr
;
5763 RTL_W32(CSIDR
, value
);
5764 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
5765 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
5767 rtl_udelay_loop_wait_low(tp
, &rtl_csiar_cond
, 10, 100);
5770 static u32
r8169_csi_read(struct rtl8169_private
*tp
, int addr
)
5772 void __iomem
*ioaddr
= tp
->mmio_addr
;
5774 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) |
5775 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
5777 return rtl_udelay_loop_wait_high(tp
, &rtl_csiar_cond
, 10, 100) ?
5778 RTL_R32(CSIDR
) : ~0;
5781 static void r8402_csi_write(struct rtl8169_private
*tp
, int addr
, int value
)
5783 void __iomem
*ioaddr
= tp
->mmio_addr
;
5785 RTL_W32(CSIDR
, value
);
5786 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
5787 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
|
5790 rtl_udelay_loop_wait_low(tp
, &rtl_csiar_cond
, 10, 100);
5793 static u32
r8402_csi_read(struct rtl8169_private
*tp
, int addr
)
5795 void __iomem
*ioaddr
= tp
->mmio_addr
;
5797 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) | CSIAR_FUNC_NIC
|
5798 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
5800 return rtl_udelay_loop_wait_high(tp
, &rtl_csiar_cond
, 10, 100) ?
5801 RTL_R32(CSIDR
) : ~0;
5804 static void r8411_csi_write(struct rtl8169_private
*tp
, int addr
, int value
)
5806 void __iomem
*ioaddr
= tp
->mmio_addr
;
5808 RTL_W32(CSIDR
, value
);
5809 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
5810 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
|
5813 rtl_udelay_loop_wait_low(tp
, &rtl_csiar_cond
, 10, 100);
5816 static u32
r8411_csi_read(struct rtl8169_private
*tp
, int addr
)
5818 void __iomem
*ioaddr
= tp
->mmio_addr
;
5820 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) | CSIAR_FUNC_NIC2
|
5821 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
5823 return rtl_udelay_loop_wait_high(tp
, &rtl_csiar_cond
, 10, 100) ?
5824 RTL_R32(CSIDR
) : ~0;
5827 static void rtl_init_csi_ops(struct rtl8169_private
*tp
)
5829 struct csi_ops
*ops
= &tp
->csi_ops
;
5831 switch (tp
->mac_version
) {
5832 case RTL_GIGA_MAC_VER_01
:
5833 case RTL_GIGA_MAC_VER_02
:
5834 case RTL_GIGA_MAC_VER_03
:
5835 case RTL_GIGA_MAC_VER_04
:
5836 case RTL_GIGA_MAC_VER_05
:
5837 case RTL_GIGA_MAC_VER_06
:
5838 case RTL_GIGA_MAC_VER_10
:
5839 case RTL_GIGA_MAC_VER_11
:
5840 case RTL_GIGA_MAC_VER_12
:
5841 case RTL_GIGA_MAC_VER_13
:
5842 case RTL_GIGA_MAC_VER_14
:
5843 case RTL_GIGA_MAC_VER_15
:
5844 case RTL_GIGA_MAC_VER_16
:
5845 case RTL_GIGA_MAC_VER_17
:
5850 case RTL_GIGA_MAC_VER_37
:
5851 case RTL_GIGA_MAC_VER_38
:
5852 ops
->write
= r8402_csi_write
;
5853 ops
->read
= r8402_csi_read
;
5856 case RTL_GIGA_MAC_VER_44
:
5857 ops
->write
= r8411_csi_write
;
5858 ops
->read
= r8411_csi_read
;
5862 ops
->write
= r8169_csi_write
;
5863 ops
->read
= r8169_csi_read
;
5869 unsigned int offset
;
5874 static void rtl_ephy_init(struct rtl8169_private
*tp
, const struct ephy_info
*e
,
5880 w
= (rtl_ephy_read(tp
, e
->offset
) & ~e
->mask
) | e
->bits
;
5881 rtl_ephy_write(tp
, e
->offset
, w
);
5886 static void rtl_disable_clock_request(struct pci_dev
*pdev
)
5888 pcie_capability_clear_word(pdev
, PCI_EXP_LNKCTL
,
5889 PCI_EXP_LNKCTL_CLKREQ_EN
);
5892 static void rtl_enable_clock_request(struct pci_dev
*pdev
)
5894 pcie_capability_set_word(pdev
, PCI_EXP_LNKCTL
,
5895 PCI_EXP_LNKCTL_CLKREQ_EN
);
5898 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private
*tp
, bool enable
)
5900 void __iomem
*ioaddr
= tp
->mmio_addr
;
5903 data
= RTL_R8(Config3
);
5908 data
&= ~Rdy_to_L23
;
5910 RTL_W8(Config3
, data
);
5913 #define R8168_CPCMD_QUIRK_MASK (\
5924 static void rtl_hw_start_8168bb(struct rtl8169_private
*tp
)
5926 void __iomem
*ioaddr
= tp
->mmio_addr
;
5927 struct pci_dev
*pdev
= tp
->pci_dev
;
5929 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
5931 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
5933 if (tp
->dev
->mtu
<= ETH_DATA_LEN
) {
5934 rtl_tx_performance_tweak(pdev
, (0x5 << MAX_READ_REQUEST_SHIFT
) |
5935 PCI_EXP_DEVCTL_NOSNOOP_EN
);
5939 static void rtl_hw_start_8168bef(struct rtl8169_private
*tp
)
5941 void __iomem
*ioaddr
= tp
->mmio_addr
;
5943 rtl_hw_start_8168bb(tp
);
5945 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
5947 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
5950 static void __rtl_hw_start_8168cp(struct rtl8169_private
*tp
)
5952 void __iomem
*ioaddr
= tp
->mmio_addr
;
5953 struct pci_dev
*pdev
= tp
->pci_dev
;
5955 RTL_W8(Config1
, RTL_R8(Config1
) | Speed_down
);
5957 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
5959 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
5960 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5962 rtl_disable_clock_request(pdev
);
5964 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
5967 static void rtl_hw_start_8168cp_1(struct rtl8169_private
*tp
)
5969 static const struct ephy_info e_info_8168cp
[] = {
5970 { 0x01, 0, 0x0001 },
5971 { 0x02, 0x0800, 0x1000 },
5972 { 0x03, 0, 0x0042 },
5973 { 0x06, 0x0080, 0x0000 },
5977 rtl_csi_access_enable_2(tp
);
5979 rtl_ephy_init(tp
, e_info_8168cp
, ARRAY_SIZE(e_info_8168cp
));
5981 __rtl_hw_start_8168cp(tp
);
5984 static void rtl_hw_start_8168cp_2(struct rtl8169_private
*tp
)
5986 void __iomem
*ioaddr
= tp
->mmio_addr
;
5987 struct pci_dev
*pdev
= tp
->pci_dev
;
5989 rtl_csi_access_enable_2(tp
);
5991 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
5993 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
5994 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5996 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
5999 static void rtl_hw_start_8168cp_3(struct rtl8169_private
*tp
)
6001 void __iomem
*ioaddr
= tp
->mmio_addr
;
6002 struct pci_dev
*pdev
= tp
->pci_dev
;
6004 rtl_csi_access_enable_2(tp
);
6006 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
6009 RTL_W8(DBG_REG
, 0x20);
6011 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
6013 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
6014 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
6016 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
6019 static void rtl_hw_start_8168c_1(struct rtl8169_private
*tp
)
6021 void __iomem
*ioaddr
= tp
->mmio_addr
;
6022 static const struct ephy_info e_info_8168c_1
[] = {
6023 { 0x02, 0x0800, 0x1000 },
6024 { 0x03, 0, 0x0002 },
6025 { 0x06, 0x0080, 0x0000 }
6028 rtl_csi_access_enable_2(tp
);
6030 RTL_W8(DBG_REG
, 0x06 | FIX_NAK_1
| FIX_NAK_2
);
6032 rtl_ephy_init(tp
, e_info_8168c_1
, ARRAY_SIZE(e_info_8168c_1
));
6034 __rtl_hw_start_8168cp(tp
);
6037 static void rtl_hw_start_8168c_2(struct rtl8169_private
*tp
)
6039 static const struct ephy_info e_info_8168c_2
[] = {
6040 { 0x01, 0, 0x0001 },
6041 { 0x03, 0x0400, 0x0220 }
6044 rtl_csi_access_enable_2(tp
);
6046 rtl_ephy_init(tp
, e_info_8168c_2
, ARRAY_SIZE(e_info_8168c_2
));
6048 __rtl_hw_start_8168cp(tp
);
6051 static void rtl_hw_start_8168c_3(struct rtl8169_private
*tp
)
6053 rtl_hw_start_8168c_2(tp
);
6056 static void rtl_hw_start_8168c_4(struct rtl8169_private
*tp
)
6058 rtl_csi_access_enable_2(tp
);
6060 __rtl_hw_start_8168cp(tp
);
6063 static void rtl_hw_start_8168d(struct rtl8169_private
*tp
)
6065 void __iomem
*ioaddr
= tp
->mmio_addr
;
6066 struct pci_dev
*pdev
= tp
->pci_dev
;
6068 rtl_csi_access_enable_2(tp
);
6070 rtl_disable_clock_request(pdev
);
6072 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
6074 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
6075 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
6077 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
6080 static void rtl_hw_start_8168dp(struct rtl8169_private
*tp
)
6082 void __iomem
*ioaddr
= tp
->mmio_addr
;
6083 struct pci_dev
*pdev
= tp
->pci_dev
;
6085 rtl_csi_access_enable_1(tp
);
6087 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
6088 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
6090 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
6092 rtl_disable_clock_request(pdev
);
6095 static void rtl_hw_start_8168d_4(struct rtl8169_private
*tp
)
6097 void __iomem
*ioaddr
= tp
->mmio_addr
;
6098 struct pci_dev
*pdev
= tp
->pci_dev
;
6099 static const struct ephy_info e_info_8168d_4
[] = {
6100 { 0x0b, 0x0000, 0x0048 },
6101 { 0x19, 0x0020, 0x0050 },
6102 { 0x0c, 0x0100, 0x0020 }
6105 rtl_csi_access_enable_1(tp
);
6107 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
6109 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
6111 rtl_ephy_init(tp
, e_info_8168d_4
, ARRAY_SIZE(e_info_8168d_4
));
6113 rtl_enable_clock_request(pdev
);
6116 static void rtl_hw_start_8168e_1(struct rtl8169_private
*tp
)
6118 void __iomem
*ioaddr
= tp
->mmio_addr
;
6119 struct pci_dev
*pdev
= tp
->pci_dev
;
6120 static const struct ephy_info e_info_8168e_1
[] = {
6121 { 0x00, 0x0200, 0x0100 },
6122 { 0x00, 0x0000, 0x0004 },
6123 { 0x06, 0x0002, 0x0001 },
6124 { 0x06, 0x0000, 0x0030 },
6125 { 0x07, 0x0000, 0x2000 },
6126 { 0x00, 0x0000, 0x0020 },
6127 { 0x03, 0x5800, 0x2000 },
6128 { 0x03, 0x0000, 0x0001 },
6129 { 0x01, 0x0800, 0x1000 },
6130 { 0x07, 0x0000, 0x4000 },
6131 { 0x1e, 0x0000, 0x2000 },
6132 { 0x19, 0xffff, 0xfe6c },
6133 { 0x0a, 0x0000, 0x0040 }
6136 rtl_csi_access_enable_2(tp
);
6138 rtl_ephy_init(tp
, e_info_8168e_1
, ARRAY_SIZE(e_info_8168e_1
));
6140 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
6141 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
6143 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
6145 rtl_disable_clock_request(pdev
);
6147 /* Reset tx FIFO pointer */
6148 RTL_W32(MISC
, RTL_R32(MISC
) | TXPLA_RST
);
6149 RTL_W32(MISC
, RTL_R32(MISC
) & ~TXPLA_RST
);
6151 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
6154 static void rtl_hw_start_8168e_2(struct rtl8169_private
*tp
)
6156 void __iomem
*ioaddr
= tp
->mmio_addr
;
6157 struct pci_dev
*pdev
= tp
->pci_dev
;
6158 static const struct ephy_info e_info_8168e_2
[] = {
6159 { 0x09, 0x0000, 0x0080 },
6160 { 0x19, 0x0000, 0x0224 }
6163 rtl_csi_access_enable_1(tp
);
6165 rtl_ephy_init(tp
, e_info_8168e_2
, ARRAY_SIZE(e_info_8168e_2
));
6167 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
6168 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
6170 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
6171 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
6172 rtl_eri_write(tp
, 0xc8, ERIAR_MASK_1111
, 0x00100002, ERIAR_EXGMAC
);
6173 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
6174 rtl_eri_write(tp
, 0xcc, ERIAR_MASK_1111
, 0x00000050, ERIAR_EXGMAC
);
6175 rtl_eri_write(tp
, 0xd0, ERIAR_MASK_1111
, 0x07ff0060, ERIAR_EXGMAC
);
6176 rtl_w0w1_eri(tp
, 0x1b0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
6177 rtl_w0w1_eri(tp
, 0x0d4, ERIAR_MASK_0011
, 0x0c00, 0xff00, ERIAR_EXGMAC
);
6179 RTL_W8(MaxTxPacketSize
, EarlySize
);
6181 rtl_disable_clock_request(pdev
);
6183 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
6184 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
6186 /* Adjust EEE LED frequency */
6187 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
6189 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
6190 RTL_W32(MISC
, RTL_R32(MISC
) | PWM_EN
);
6191 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
6194 static void rtl_hw_start_8168f(struct rtl8169_private
*tp
)
6196 void __iomem
*ioaddr
= tp
->mmio_addr
;
6197 struct pci_dev
*pdev
= tp
->pci_dev
;
6199 rtl_csi_access_enable_2(tp
);
6201 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
6203 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
6204 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
6205 rtl_eri_write(tp
, 0xc8, ERIAR_MASK_1111
, 0x00100002, ERIAR_EXGMAC
);
6206 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
6207 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01, ERIAR_EXGMAC
);
6208 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00, ERIAR_EXGMAC
);
6209 rtl_w0w1_eri(tp
, 0x1b0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
6210 rtl_w0w1_eri(tp
, 0x1d0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
6211 rtl_eri_write(tp
, 0xcc, ERIAR_MASK_1111
, 0x00000050, ERIAR_EXGMAC
);
6212 rtl_eri_write(tp
, 0xd0, ERIAR_MASK_1111
, 0x00000060, ERIAR_EXGMAC
);
6214 RTL_W8(MaxTxPacketSize
, EarlySize
);
6216 rtl_disable_clock_request(pdev
);
6218 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
6219 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
6220 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
6221 RTL_W32(MISC
, RTL_R32(MISC
) | PWM_EN
);
6222 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
6225 static void rtl_hw_start_8168f_1(struct rtl8169_private
*tp
)
6227 void __iomem
*ioaddr
= tp
->mmio_addr
;
6228 static const struct ephy_info e_info_8168f_1
[] = {
6229 { 0x06, 0x00c0, 0x0020 },
6230 { 0x08, 0x0001, 0x0002 },
6231 { 0x09, 0x0000, 0x0080 },
6232 { 0x19, 0x0000, 0x0224 }
6235 rtl_hw_start_8168f(tp
);
6237 rtl_ephy_init(tp
, e_info_8168f_1
, ARRAY_SIZE(e_info_8168f_1
));
6239 rtl_w0w1_eri(tp
, 0x0d4, ERIAR_MASK_0011
, 0x0c00, 0xff00, ERIAR_EXGMAC
);
6241 /* Adjust EEE LED frequency */
6242 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
6245 static void rtl_hw_start_8411(struct rtl8169_private
*tp
)
6247 static const struct ephy_info e_info_8168f_1
[] = {
6248 { 0x06, 0x00c0, 0x0020 },
6249 { 0x0f, 0xffff, 0x5200 },
6250 { 0x1e, 0x0000, 0x4000 },
6251 { 0x19, 0x0000, 0x0224 }
6254 rtl_hw_start_8168f(tp
);
6255 rtl_pcie_state_l2l3_enable(tp
, false);
6257 rtl_ephy_init(tp
, e_info_8168f_1
, ARRAY_SIZE(e_info_8168f_1
));
6259 rtl_w0w1_eri(tp
, 0x0d4, ERIAR_MASK_0011
, 0x0c00, 0x0000, ERIAR_EXGMAC
);
6262 static void rtl_hw_start_8168g(struct rtl8169_private
*tp
)
6264 void __iomem
*ioaddr
= tp
->mmio_addr
;
6265 struct pci_dev
*pdev
= tp
->pci_dev
;
6267 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
6269 rtl_eri_write(tp
, 0xc8, ERIAR_MASK_0101
, 0x080002, ERIAR_EXGMAC
);
6270 rtl_eri_write(tp
, 0xcc, ERIAR_MASK_0001
, 0x38, ERIAR_EXGMAC
);
6271 rtl_eri_write(tp
, 0xd0, ERIAR_MASK_0001
, 0x48, ERIAR_EXGMAC
);
6272 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
6274 rtl_csi_access_enable_1(tp
);
6276 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
6278 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01, ERIAR_EXGMAC
);
6279 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00, ERIAR_EXGMAC
);
6280 rtl_eri_write(tp
, 0x2f8, ERIAR_MASK_0011
, 0x1d8f, ERIAR_EXGMAC
);
6282 RTL_W32(MISC
, RTL_R32(MISC
) & ~RXDV_GATED_EN
);
6283 RTL_W8(MaxTxPacketSize
, EarlySize
);
6285 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
6286 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
6288 /* Adjust EEE LED frequency */
6289 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
6291 rtl_w0w1_eri(tp
, 0x2fc, ERIAR_MASK_0001
, 0x01, 0x06, ERIAR_EXGMAC
);
6292 rtl_w0w1_eri(tp
, 0x1b0, ERIAR_MASK_0011
, 0x0000, 0x1000, ERIAR_EXGMAC
);
6294 rtl_pcie_state_l2l3_enable(tp
, false);
6297 static void rtl_hw_start_8168g_1(struct rtl8169_private
*tp
)
6299 void __iomem
*ioaddr
= tp
->mmio_addr
;
6300 static const struct ephy_info e_info_8168g_1
[] = {
6301 { 0x00, 0x0000, 0x0008 },
6302 { 0x0c, 0x37d0, 0x0820 },
6303 { 0x1e, 0x0000, 0x0001 },
6304 { 0x19, 0x8000, 0x0000 }
6307 rtl_hw_start_8168g(tp
);
6309 /* disable aspm and clock request before access ephy */
6310 RTL_W8(Config2
, RTL_R8(Config2
) & ~ClkReqEn
);
6311 RTL_W8(Config5
, RTL_R8(Config5
) & ~ASPM_en
);
6312 rtl_ephy_init(tp
, e_info_8168g_1
, ARRAY_SIZE(e_info_8168g_1
));
6315 static void rtl_hw_start_8168g_2(struct rtl8169_private
*tp
)
6317 void __iomem
*ioaddr
= tp
->mmio_addr
;
6318 static const struct ephy_info e_info_8168g_2
[] = {
6319 { 0x00, 0x0000, 0x0008 },
6320 { 0x0c, 0x3df0, 0x0200 },
6321 { 0x19, 0xffff, 0xfc00 },
6322 { 0x1e, 0xffff, 0x20eb }
6325 rtl_hw_start_8168g(tp
);
6327 /* disable aspm and clock request before access ephy */
6328 RTL_W8(Config2
, RTL_R8(Config2
) & ~ClkReqEn
);
6329 RTL_W8(Config5
, RTL_R8(Config5
) & ~ASPM_en
);
6330 rtl_ephy_init(tp
, e_info_8168g_2
, ARRAY_SIZE(e_info_8168g_2
));
6333 static void rtl_hw_start_8411_2(struct rtl8169_private
*tp
)
6335 void __iomem
*ioaddr
= tp
->mmio_addr
;
6336 static const struct ephy_info e_info_8411_2
[] = {
6337 { 0x00, 0x0000, 0x0008 },
6338 { 0x0c, 0x3df0, 0x0200 },
6339 { 0x0f, 0xffff, 0x5200 },
6340 { 0x19, 0x0020, 0x0000 },
6341 { 0x1e, 0x0000, 0x2000 }
6344 rtl_hw_start_8168g(tp
);
6346 /* disable aspm and clock request before access ephy */
6347 RTL_W8(Config2
, RTL_R8(Config2
) & ~ClkReqEn
);
6348 RTL_W8(Config5
, RTL_R8(Config5
) & ~ASPM_en
);
6349 rtl_ephy_init(tp
, e_info_8411_2
, ARRAY_SIZE(e_info_8411_2
));
6352 static void rtl_hw_start_8168h_1(struct rtl8169_private
*tp
)
6354 void __iomem
*ioaddr
= tp
->mmio_addr
;
6355 struct pci_dev
*pdev
= tp
->pci_dev
;
6358 static const struct ephy_info e_info_8168h_1
[] = {
6359 { 0x1e, 0x0800, 0x0001 },
6360 { 0x1d, 0x0000, 0x0800 },
6361 { 0x05, 0xffff, 0x2089 },
6362 { 0x06, 0xffff, 0x5881 },
6363 { 0x04, 0xffff, 0x154a },
6364 { 0x01, 0xffff, 0x068b }
6367 /* disable aspm and clock request before access ephy */
6368 RTL_W8(Config2
, RTL_R8(Config2
) & ~ClkReqEn
);
6369 RTL_W8(Config5
, RTL_R8(Config5
) & ~ASPM_en
);
6370 rtl_ephy_init(tp
, e_info_8168h_1
, ARRAY_SIZE(e_info_8168h_1
));
6372 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
6374 rtl_eri_write(tp
, 0xc8, ERIAR_MASK_0101
, 0x00080002, ERIAR_EXGMAC
);
6375 rtl_eri_write(tp
, 0xcc, ERIAR_MASK_0001
, 0x38, ERIAR_EXGMAC
);
6376 rtl_eri_write(tp
, 0xd0, ERIAR_MASK_0001
, 0x48, ERIAR_EXGMAC
);
6377 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
6379 rtl_csi_access_enable_1(tp
);
6381 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
6383 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01, ERIAR_EXGMAC
);
6384 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00, ERIAR_EXGMAC
);
6386 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_1111
, 0x0010, 0x00, ERIAR_EXGMAC
);
6388 rtl_w0w1_eri(tp
, 0xd4, ERIAR_MASK_1111
, 0x1f00, 0x00, ERIAR_EXGMAC
);
6390 rtl_eri_write(tp
, 0x5f0, ERIAR_MASK_0011
, 0x4f87, ERIAR_EXGMAC
);
6392 RTL_W32(MISC
, RTL_R32(MISC
) & ~RXDV_GATED_EN
);
6393 RTL_W8(MaxTxPacketSize
, EarlySize
);
6395 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
6396 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
6398 /* Adjust EEE LED frequency */
6399 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
6401 RTL_W8(DLLPR
, RTL_R8(DLLPR
) & ~PFM_EN
);
6402 RTL_W8(MISC_1
, RTL_R8(MISC_1
) & ~PFM_D3COLD_EN
);
6404 RTL_W8(DLLPR
, RTL_R8(DLLPR
) & ~TX_10M_PS_EN
);
6406 rtl_w0w1_eri(tp
, 0x1b0, ERIAR_MASK_0011
, 0x0000, 0x1000, ERIAR_EXGMAC
);
6408 rtl_pcie_state_l2l3_enable(tp
, false);
6410 rtl_writephy(tp
, 0x1f, 0x0c42);
6411 rg_saw_cnt
= (rtl_readphy(tp
, 0x13) & 0x3fff);
6412 rtl_writephy(tp
, 0x1f, 0x0000);
6413 if (rg_saw_cnt
> 0) {
6416 sw_cnt_1ms_ini
= 16000000/rg_saw_cnt
;
6417 sw_cnt_1ms_ini
&= 0x0fff;
6418 data
= r8168_mac_ocp_read(tp
, 0xd412);
6420 data
|= sw_cnt_1ms_ini
;
6421 r8168_mac_ocp_write(tp
, 0xd412, data
);
6424 data
= r8168_mac_ocp_read(tp
, 0xe056);
6427 r8168_mac_ocp_write(tp
, 0xe056, data
);
6429 data
= r8168_mac_ocp_read(tp
, 0xe052);
6432 r8168_mac_ocp_write(tp
, 0xe052, data
);
6434 data
= r8168_mac_ocp_read(tp
, 0xe0d6);
6437 r8168_mac_ocp_write(tp
, 0xe0d6, data
);
6439 data
= r8168_mac_ocp_read(tp
, 0xd420);
6442 r8168_mac_ocp_write(tp
, 0xd420, data
);
6444 r8168_mac_ocp_write(tp
, 0xe63e, 0x0001);
6445 r8168_mac_ocp_write(tp
, 0xe63e, 0x0000);
6446 r8168_mac_ocp_write(tp
, 0xc094, 0x0000);
6447 r8168_mac_ocp_write(tp
, 0xc09e, 0x0000);
6450 static void rtl_hw_start_8168ep(struct rtl8169_private
*tp
)
6452 void __iomem
*ioaddr
= tp
->mmio_addr
;
6453 struct pci_dev
*pdev
= tp
->pci_dev
;
6455 rtl8168ep_stop_cmac(tp
);
6457 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
6459 rtl_eri_write(tp
, 0xc8, ERIAR_MASK_0101
, 0x00080002, ERIAR_EXGMAC
);
6460 rtl_eri_write(tp
, 0xcc, ERIAR_MASK_0001
, 0x2f, ERIAR_EXGMAC
);
6461 rtl_eri_write(tp
, 0xd0, ERIAR_MASK_0001
, 0x5f, ERIAR_EXGMAC
);
6462 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
6464 rtl_csi_access_enable_1(tp
);
6466 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
6468 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01, ERIAR_EXGMAC
);
6469 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00, ERIAR_EXGMAC
);
6471 rtl_w0w1_eri(tp
, 0xd4, ERIAR_MASK_1111
, 0x1f80, 0x00, ERIAR_EXGMAC
);
6473 rtl_eri_write(tp
, 0x5f0, ERIAR_MASK_0011
, 0x4f87, ERIAR_EXGMAC
);
6475 RTL_W32(MISC
, RTL_R32(MISC
) & ~RXDV_GATED_EN
);
6476 RTL_W8(MaxTxPacketSize
, EarlySize
);
6478 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
6479 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
6481 /* Adjust EEE LED frequency */
6482 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
6484 rtl_w0w1_eri(tp
, 0x2fc, ERIAR_MASK_0001
, 0x01, 0x06, ERIAR_EXGMAC
);
6486 RTL_W8(DLLPR
, RTL_R8(DLLPR
) & ~TX_10M_PS_EN
);
6488 rtl_pcie_state_l2l3_enable(tp
, false);
6491 static void rtl_hw_start_8168ep_1(struct rtl8169_private
*tp
)
6493 void __iomem
*ioaddr
= tp
->mmio_addr
;
6494 static const struct ephy_info e_info_8168ep_1
[] = {
6495 { 0x00, 0xffff, 0x10ab },
6496 { 0x06, 0xffff, 0xf030 },
6497 { 0x08, 0xffff, 0x2006 },
6498 { 0x0d, 0xffff, 0x1666 },
6499 { 0x0c, 0x3ff0, 0x0000 }
6502 /* disable aspm and clock request before access ephy */
6503 RTL_W8(Config2
, RTL_R8(Config2
) & ~ClkReqEn
);
6504 RTL_W8(Config5
, RTL_R8(Config5
) & ~ASPM_en
);
6505 rtl_ephy_init(tp
, e_info_8168ep_1
, ARRAY_SIZE(e_info_8168ep_1
));
6507 rtl_hw_start_8168ep(tp
);
6510 static void rtl_hw_start_8168ep_2(struct rtl8169_private
*tp
)
6512 void __iomem
*ioaddr
= tp
->mmio_addr
;
6513 static const struct ephy_info e_info_8168ep_2
[] = {
6514 { 0x00, 0xffff, 0x10a3 },
6515 { 0x19, 0xffff, 0xfc00 },
6516 { 0x1e, 0xffff, 0x20ea }
6519 /* disable aspm and clock request before access ephy */
6520 RTL_W8(Config2
, RTL_R8(Config2
) & ~ClkReqEn
);
6521 RTL_W8(Config5
, RTL_R8(Config5
) & ~ASPM_en
);
6522 rtl_ephy_init(tp
, e_info_8168ep_2
, ARRAY_SIZE(e_info_8168ep_2
));
6524 rtl_hw_start_8168ep(tp
);
6526 RTL_W8(DLLPR
, RTL_R8(DLLPR
) & ~PFM_EN
);
6527 RTL_W8(MISC_1
, RTL_R8(MISC_1
) & ~PFM_D3COLD_EN
);
6530 static void rtl_hw_start_8168ep_3(struct rtl8169_private
*tp
)
6532 void __iomem
*ioaddr
= tp
->mmio_addr
;
6534 static const struct ephy_info e_info_8168ep_3
[] = {
6535 { 0x00, 0xffff, 0x10a3 },
6536 { 0x19, 0xffff, 0x7c00 },
6537 { 0x1e, 0xffff, 0x20eb },
6538 { 0x0d, 0xffff, 0x1666 }
6541 /* disable aspm and clock request before access ephy */
6542 RTL_W8(Config2
, RTL_R8(Config2
) & ~ClkReqEn
);
6543 RTL_W8(Config5
, RTL_R8(Config5
) & ~ASPM_en
);
6544 rtl_ephy_init(tp
, e_info_8168ep_3
, ARRAY_SIZE(e_info_8168ep_3
));
6546 rtl_hw_start_8168ep(tp
);
6548 RTL_W8(DLLPR
, RTL_R8(DLLPR
) & ~PFM_EN
);
6549 RTL_W8(MISC_1
, RTL_R8(MISC_1
) & ~PFM_D3COLD_EN
);
6551 data
= r8168_mac_ocp_read(tp
, 0xd3e2);
6554 r8168_mac_ocp_write(tp
, 0xd3e2, data
);
6556 data
= r8168_mac_ocp_read(tp
, 0xd3e4);
6558 r8168_mac_ocp_write(tp
, 0xd3e4, data
);
6560 data
= r8168_mac_ocp_read(tp
, 0xe860);
6562 r8168_mac_ocp_write(tp
, 0xe860, data
);
6565 static void rtl_hw_start_8168(struct net_device
*dev
)
6567 struct rtl8169_private
*tp
= netdev_priv(dev
);
6568 void __iomem
*ioaddr
= tp
->mmio_addr
;
6570 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
6572 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
6574 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
6576 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
6578 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
6580 RTL_W16(IntrMitigate
, 0x5151);
6582 /* Work around for RxFIFO overflow. */
6583 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
) {
6584 tp
->event_slow
|= RxFIFOOver
| PCSTimeout
;
6585 tp
->event_slow
&= ~RxOverflow
;
6588 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
6590 rtl_set_rx_tx_config_registers(tp
);
6594 switch (tp
->mac_version
) {
6595 case RTL_GIGA_MAC_VER_11
:
6596 rtl_hw_start_8168bb(tp
);
6599 case RTL_GIGA_MAC_VER_12
:
6600 case RTL_GIGA_MAC_VER_17
:
6601 rtl_hw_start_8168bef(tp
);
6604 case RTL_GIGA_MAC_VER_18
:
6605 rtl_hw_start_8168cp_1(tp
);
6608 case RTL_GIGA_MAC_VER_19
:
6609 rtl_hw_start_8168c_1(tp
);
6612 case RTL_GIGA_MAC_VER_20
:
6613 rtl_hw_start_8168c_2(tp
);
6616 case RTL_GIGA_MAC_VER_21
:
6617 rtl_hw_start_8168c_3(tp
);
6620 case RTL_GIGA_MAC_VER_22
:
6621 rtl_hw_start_8168c_4(tp
);
6624 case RTL_GIGA_MAC_VER_23
:
6625 rtl_hw_start_8168cp_2(tp
);
6628 case RTL_GIGA_MAC_VER_24
:
6629 rtl_hw_start_8168cp_3(tp
);
6632 case RTL_GIGA_MAC_VER_25
:
6633 case RTL_GIGA_MAC_VER_26
:
6634 case RTL_GIGA_MAC_VER_27
:
6635 rtl_hw_start_8168d(tp
);
6638 case RTL_GIGA_MAC_VER_28
:
6639 rtl_hw_start_8168d_4(tp
);
6642 case RTL_GIGA_MAC_VER_31
:
6643 rtl_hw_start_8168dp(tp
);
6646 case RTL_GIGA_MAC_VER_32
:
6647 case RTL_GIGA_MAC_VER_33
:
6648 rtl_hw_start_8168e_1(tp
);
6650 case RTL_GIGA_MAC_VER_34
:
6651 rtl_hw_start_8168e_2(tp
);
6654 case RTL_GIGA_MAC_VER_35
:
6655 case RTL_GIGA_MAC_VER_36
:
6656 rtl_hw_start_8168f_1(tp
);
6659 case RTL_GIGA_MAC_VER_38
:
6660 rtl_hw_start_8411(tp
);
6663 case RTL_GIGA_MAC_VER_40
:
6664 case RTL_GIGA_MAC_VER_41
:
6665 rtl_hw_start_8168g_1(tp
);
6667 case RTL_GIGA_MAC_VER_42
:
6668 rtl_hw_start_8168g_2(tp
);
6671 case RTL_GIGA_MAC_VER_44
:
6672 rtl_hw_start_8411_2(tp
);
6675 case RTL_GIGA_MAC_VER_45
:
6676 case RTL_GIGA_MAC_VER_46
:
6677 rtl_hw_start_8168h_1(tp
);
6680 case RTL_GIGA_MAC_VER_49
:
6681 rtl_hw_start_8168ep_1(tp
);
6684 case RTL_GIGA_MAC_VER_50
:
6685 rtl_hw_start_8168ep_2(tp
);
6688 case RTL_GIGA_MAC_VER_51
:
6689 rtl_hw_start_8168ep_3(tp
);
6693 printk(KERN_ERR PFX
"%s: unknown chipset (mac_version = %d).\n",
6694 dev
->name
, tp
->mac_version
);
6698 RTL_W8(Cfg9346
, Cfg9346_Lock
);
6700 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
6702 rtl_set_rx_mode(dev
);
6704 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
6707 #define R810X_CPCMD_QUIRK_MASK (\
6718 static void rtl_hw_start_8102e_1(struct rtl8169_private
*tp
)
6720 void __iomem
*ioaddr
= tp
->mmio_addr
;
6721 struct pci_dev
*pdev
= tp
->pci_dev
;
6722 static const struct ephy_info e_info_8102e_1
[] = {
6723 { 0x01, 0, 0x6e65 },
6724 { 0x02, 0, 0x091f },
6725 { 0x03, 0, 0xc2f9 },
6726 { 0x06, 0, 0xafb5 },
6727 { 0x07, 0, 0x0e00 },
6728 { 0x19, 0, 0xec80 },
6729 { 0x01, 0, 0x2e65 },
6734 rtl_csi_access_enable_2(tp
);
6736 RTL_W8(DBG_REG
, FIX_NAK_1
);
6738 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
6741 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
6742 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
6744 cfg1
= RTL_R8(Config1
);
6745 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
6746 RTL_W8(Config1
, cfg1
& ~LEDS0
);
6748 rtl_ephy_init(tp
, e_info_8102e_1
, ARRAY_SIZE(e_info_8102e_1
));
6751 static void rtl_hw_start_8102e_2(struct rtl8169_private
*tp
)
6753 void __iomem
*ioaddr
= tp
->mmio_addr
;
6754 struct pci_dev
*pdev
= tp
->pci_dev
;
6756 rtl_csi_access_enable_2(tp
);
6758 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
6760 RTL_W8(Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
6761 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
6764 static void rtl_hw_start_8102e_3(struct rtl8169_private
*tp
)
6766 rtl_hw_start_8102e_2(tp
);
6768 rtl_ephy_write(tp
, 0x03, 0xc2f9);
6771 static void rtl_hw_start_8105e_1(struct rtl8169_private
*tp
)
6773 void __iomem
*ioaddr
= tp
->mmio_addr
;
6774 static const struct ephy_info e_info_8105e_1
[] = {
6775 { 0x07, 0, 0x4000 },
6776 { 0x19, 0, 0x0200 },
6777 { 0x19, 0, 0x0020 },
6778 { 0x1e, 0, 0x2000 },
6779 { 0x03, 0, 0x0001 },
6780 { 0x19, 0, 0x0100 },
6781 { 0x19, 0, 0x0004 },
6785 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6786 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) | 0x002800);
6788 /* Disable Early Tally Counter */
6789 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) & ~0x010000);
6791 RTL_W8(MCU
, RTL_R8(MCU
) | EN_NDP
| EN_OOB_RESET
);
6792 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
6794 rtl_ephy_init(tp
, e_info_8105e_1
, ARRAY_SIZE(e_info_8105e_1
));
6796 rtl_pcie_state_l2l3_enable(tp
, false);
6799 static void rtl_hw_start_8105e_2(struct rtl8169_private
*tp
)
6801 rtl_hw_start_8105e_1(tp
);
6802 rtl_ephy_write(tp
, 0x1e, rtl_ephy_read(tp
, 0x1e) | 0x8000);
6805 static void rtl_hw_start_8402(struct rtl8169_private
*tp
)
6807 void __iomem
*ioaddr
= tp
->mmio_addr
;
6808 static const struct ephy_info e_info_8402
[] = {
6809 { 0x19, 0xffff, 0xff64 },
6813 rtl_csi_access_enable_2(tp
);
6815 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6816 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) | 0x002800);
6818 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
6819 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
6821 rtl_ephy_init(tp
, e_info_8402
, ARRAY_SIZE(e_info_8402
));
6823 rtl_tx_performance_tweak(tp
->pci_dev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
6825 rtl_eri_write(tp
, 0xc8, ERIAR_MASK_1111
, 0x00000002, ERIAR_EXGMAC
);
6826 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_1111
, 0x00000006, ERIAR_EXGMAC
);
6827 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01, ERIAR_EXGMAC
);
6828 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00, ERIAR_EXGMAC
);
6829 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
6830 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
6831 rtl_w0w1_eri(tp
, 0x0d4, ERIAR_MASK_0011
, 0x0e00, 0xff00, ERIAR_EXGMAC
);
6833 rtl_pcie_state_l2l3_enable(tp
, false);
6836 static void rtl_hw_start_8106(struct rtl8169_private
*tp
)
6838 void __iomem
*ioaddr
= tp
->mmio_addr
;
6840 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6841 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) | 0x002800);
6843 RTL_W32(MISC
, (RTL_R32(MISC
) | DISABLE_LAN_EN
) & ~EARLY_TALLY_EN
);
6844 RTL_W8(MCU
, RTL_R8(MCU
) | EN_NDP
| EN_OOB_RESET
);
6845 RTL_W8(DLLPR
, RTL_R8(DLLPR
) & ~PFM_EN
);
6847 rtl_pcie_state_l2l3_enable(tp
, false);
6850 static void rtl_hw_start_8101(struct net_device
*dev
)
6852 struct rtl8169_private
*tp
= netdev_priv(dev
);
6853 void __iomem
*ioaddr
= tp
->mmio_addr
;
6854 struct pci_dev
*pdev
= tp
->pci_dev
;
6856 if (tp
->mac_version
>= RTL_GIGA_MAC_VER_30
)
6857 tp
->event_slow
&= ~RxFIFOOver
;
6859 if (tp
->mac_version
== RTL_GIGA_MAC_VER_13
||
6860 tp
->mac_version
== RTL_GIGA_MAC_VER_16
)
6861 pcie_capability_set_word(pdev
, PCI_EXP_DEVCTL
,
6862 PCI_EXP_DEVCTL_NOSNOOP_EN
);
6864 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
6866 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
6868 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
6870 tp
->cp_cmd
&= ~R810X_CPCMD_QUIRK_MASK
;
6871 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
6873 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
6875 rtl_set_rx_tx_config_registers(tp
);
6877 switch (tp
->mac_version
) {
6878 case RTL_GIGA_MAC_VER_07
:
6879 rtl_hw_start_8102e_1(tp
);
6882 case RTL_GIGA_MAC_VER_08
:
6883 rtl_hw_start_8102e_3(tp
);
6886 case RTL_GIGA_MAC_VER_09
:
6887 rtl_hw_start_8102e_2(tp
);
6890 case RTL_GIGA_MAC_VER_29
:
6891 rtl_hw_start_8105e_1(tp
);
6893 case RTL_GIGA_MAC_VER_30
:
6894 rtl_hw_start_8105e_2(tp
);
6897 case RTL_GIGA_MAC_VER_37
:
6898 rtl_hw_start_8402(tp
);
6901 case RTL_GIGA_MAC_VER_39
:
6902 rtl_hw_start_8106(tp
);
6904 case RTL_GIGA_MAC_VER_43
:
6905 rtl_hw_start_8168g_2(tp
);
6907 case RTL_GIGA_MAC_VER_47
:
6908 case RTL_GIGA_MAC_VER_48
:
6909 rtl_hw_start_8168h_1(tp
);
6913 RTL_W8(Cfg9346
, Cfg9346_Lock
);
6915 RTL_W16(IntrMitigate
, 0x0000);
6917 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
6919 rtl_set_rx_mode(dev
);
6923 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
6926 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
6928 struct rtl8169_private
*tp
= netdev_priv(dev
);
6930 if (new_mtu
> ETH_DATA_LEN
)
6931 rtl_hw_jumbo_enable(tp
);
6933 rtl_hw_jumbo_disable(tp
);
6936 netdev_update_features(dev
);
6941 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
6943 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
6944 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
6947 static void rtl8169_free_rx_databuff(struct rtl8169_private
*tp
,
6948 void **data_buff
, struct RxDesc
*desc
)
6950 dma_unmap_single(&tp
->pci_dev
->dev
, le64_to_cpu(desc
->addr
), rx_buf_sz
,
6955 rtl8169_make_unusable_by_asic(desc
);
6958 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
6960 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
6962 /* Force memory writes to complete before releasing descriptor */
6965 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
6968 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
6971 desc
->addr
= cpu_to_le64(mapping
);
6972 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
6975 static inline void *rtl8169_align(void *data
)
6977 return (void *)ALIGN((long)data
, 16);
6980 static struct sk_buff
*rtl8169_alloc_rx_data(struct rtl8169_private
*tp
,
6981 struct RxDesc
*desc
)
6985 struct device
*d
= &tp
->pci_dev
->dev
;
6986 struct net_device
*dev
= tp
->dev
;
6987 int node
= dev
->dev
.parent
? dev_to_node(dev
->dev
.parent
) : -1;
6989 data
= kmalloc_node(rx_buf_sz
, GFP_KERNEL
, node
);
6993 if (rtl8169_align(data
) != data
) {
6995 data
= kmalloc_node(rx_buf_sz
+ 15, GFP_KERNEL
, node
);
7000 mapping
= dma_map_single(d
, rtl8169_align(data
), rx_buf_sz
,
7002 if (unlikely(dma_mapping_error(d
, mapping
))) {
7003 if (net_ratelimit())
7004 netif_err(tp
, drv
, tp
->dev
, "Failed to map RX DMA!\n");
7008 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
7016 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
7020 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
7021 if (tp
->Rx_databuff
[i
]) {
7022 rtl8169_free_rx_databuff(tp
, tp
->Rx_databuff
+ i
,
7023 tp
->RxDescArray
+ i
);
7028 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
7030 desc
->opts1
|= cpu_to_le32(RingEnd
);
7033 static int rtl8169_rx_fill(struct rtl8169_private
*tp
)
7037 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
7040 if (tp
->Rx_databuff
[i
])
7043 data
= rtl8169_alloc_rx_data(tp
, tp
->RxDescArray
+ i
);
7045 rtl8169_make_unusable_by_asic(tp
->RxDescArray
+ i
);
7048 tp
->Rx_databuff
[i
] = data
;
7051 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
7055 rtl8169_rx_clear(tp
);
7059 static int rtl8169_init_ring(struct net_device
*dev
)
7061 struct rtl8169_private
*tp
= netdev_priv(dev
);
7063 rtl8169_init_ring_indexes(tp
);
7065 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
7066 memset(tp
->Rx_databuff
, 0x0, NUM_RX_DESC
* sizeof(void *));
7068 return rtl8169_rx_fill(tp
);
7071 static void rtl8169_unmap_tx_skb(struct device
*d
, struct ring_info
*tx_skb
,
7072 struct TxDesc
*desc
)
7074 unsigned int len
= tx_skb
->len
;
7076 dma_unmap_single(d
, le64_to_cpu(desc
->addr
), len
, DMA_TO_DEVICE
);
7084 static void rtl8169_tx_clear_range(struct rtl8169_private
*tp
, u32 start
,
7089 for (i
= 0; i
< n
; i
++) {
7090 unsigned int entry
= (start
+ i
) % NUM_TX_DESC
;
7091 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
7092 unsigned int len
= tx_skb
->len
;
7095 struct sk_buff
*skb
= tx_skb
->skb
;
7097 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
7098 tp
->TxDescArray
+ entry
);
7100 dev_consume_skb_any(skb
);
7107 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
7109 rtl8169_tx_clear_range(tp
, tp
->dirty_tx
, NUM_TX_DESC
);
7110 tp
->cur_tx
= tp
->dirty_tx
= 0;
7113 static void rtl_reset_work(struct rtl8169_private
*tp
)
7115 struct net_device
*dev
= tp
->dev
;
7118 napi_disable(&tp
->napi
);
7119 netif_stop_queue(dev
);
7120 synchronize_sched();
7122 rtl8169_hw_reset(tp
);
7124 for (i
= 0; i
< NUM_RX_DESC
; i
++)
7125 rtl8169_mark_to_asic(tp
->RxDescArray
+ i
, rx_buf_sz
);
7127 rtl8169_tx_clear(tp
);
7128 rtl8169_init_ring_indexes(tp
);
7130 napi_enable(&tp
->napi
);
7132 netif_wake_queue(dev
);
7133 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
7136 static void rtl8169_tx_timeout(struct net_device
*dev
)
7138 struct rtl8169_private
*tp
= netdev_priv(dev
);
7140 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
7143 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
7146 struct skb_shared_info
*info
= skb_shinfo(skb
);
7147 unsigned int cur_frag
, entry
;
7148 struct TxDesc
*uninitialized_var(txd
);
7149 struct device
*d
= &tp
->pci_dev
->dev
;
7152 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
7153 const skb_frag_t
*frag
= info
->frags
+ cur_frag
;
7158 entry
= (entry
+ 1) % NUM_TX_DESC
;
7160 txd
= tp
->TxDescArray
+ entry
;
7161 len
= skb_frag_size(frag
);
7162 addr
= skb_frag_address(frag
);
7163 mapping
= dma_map_single(d
, addr
, len
, DMA_TO_DEVICE
);
7164 if (unlikely(dma_mapping_error(d
, mapping
))) {
7165 if (net_ratelimit())
7166 netif_err(tp
, drv
, tp
->dev
,
7167 "Failed to map TX fragments DMA!\n");
7171 /* Anti gcc 2.95.3 bugware (sic) */
7172 status
= opts
[0] | len
|
7173 (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
7175 txd
->opts1
= cpu_to_le32(status
);
7176 txd
->opts2
= cpu_to_le32(opts
[1]);
7177 txd
->addr
= cpu_to_le64(mapping
);
7179 tp
->tx_skb
[entry
].len
= len
;
7183 tp
->tx_skb
[entry
].skb
= skb
;
7184 txd
->opts1
|= cpu_to_le32(LastFrag
);
7190 rtl8169_tx_clear_range(tp
, tp
->cur_tx
+ 1, cur_frag
);
7194 static bool rtl_test_hw_pad_bug(struct rtl8169_private
*tp
, struct sk_buff
*skb
)
7196 return skb
->len
< ETH_ZLEN
&& tp
->mac_version
== RTL_GIGA_MAC_VER_34
;
7199 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
7200 struct net_device
*dev
);
7201 /* r8169_csum_workaround()
7202 * The hw limites the value the transport offset. When the offset is out of the
7203 * range, calculate the checksum by sw.
7205 static void r8169_csum_workaround(struct rtl8169_private
*tp
,
7206 struct sk_buff
*skb
)
7208 if (skb_shinfo(skb
)->gso_size
) {
7209 netdev_features_t features
= tp
->dev
->features
;
7210 struct sk_buff
*segs
, *nskb
;
7212 features
&= ~(NETIF_F_SG
| NETIF_F_IPV6_CSUM
| NETIF_F_TSO6
);
7213 segs
= skb_gso_segment(skb
, features
);
7214 if (IS_ERR(segs
) || !segs
)
7221 rtl8169_start_xmit(nskb
, tp
->dev
);
7224 dev_consume_skb_any(skb
);
7225 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
7226 if (skb_checksum_help(skb
) < 0)
7229 rtl8169_start_xmit(skb
, tp
->dev
);
7231 struct net_device_stats
*stats
;
7234 stats
= &tp
->dev
->stats
;
7235 stats
->tx_dropped
++;
7236 dev_kfree_skb_any(skb
);
7240 /* msdn_giant_send_check()
7241 * According to the document of microsoft, the TCP Pseudo Header excludes the
7242 * packet length for IPv6 TCP large packets.
7244 static int msdn_giant_send_check(struct sk_buff
*skb
)
7246 const struct ipv6hdr
*ipv6h
;
7250 ret
= skb_cow_head(skb
, 0);
7254 ipv6h
= ipv6_hdr(skb
);
7258 th
->check
= ~tcp_v6_check(0, &ipv6h
->saddr
, &ipv6h
->daddr
, 0);
7263 static inline __be16
get_protocol(struct sk_buff
*skb
)
7267 if (skb
->protocol
== htons(ETH_P_8021Q
))
7268 protocol
= vlan_eth_hdr(skb
)->h_vlan_encapsulated_proto
;
7270 protocol
= skb
->protocol
;
7275 static bool rtl8169_tso_csum_v1(struct rtl8169_private
*tp
,
7276 struct sk_buff
*skb
, u32
*opts
)
7278 u32 mss
= skb_shinfo(skb
)->gso_size
;
7282 opts
[0] |= min(mss
, TD_MSS_MAX
) << TD0_MSS_SHIFT
;
7283 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
7284 const struct iphdr
*ip
= ip_hdr(skb
);
7286 if (ip
->protocol
== IPPROTO_TCP
)
7287 opts
[0] |= TD0_IP_CS
| TD0_TCP_CS
;
7288 else if (ip
->protocol
== IPPROTO_UDP
)
7289 opts
[0] |= TD0_IP_CS
| TD0_UDP_CS
;
7297 static bool rtl8169_tso_csum_v2(struct rtl8169_private
*tp
,
7298 struct sk_buff
*skb
, u32
*opts
)
7300 u32 transport_offset
= (u32
)skb_transport_offset(skb
);
7301 u32 mss
= skb_shinfo(skb
)->gso_size
;
7304 if (transport_offset
> GTTCPHO_MAX
) {
7305 netif_warn(tp
, tx_err
, tp
->dev
,
7306 "Invalid transport offset 0x%x for TSO\n",
7311 switch (get_protocol(skb
)) {
7312 case htons(ETH_P_IP
):
7313 opts
[0] |= TD1_GTSENV4
;
7316 case htons(ETH_P_IPV6
):
7317 if (msdn_giant_send_check(skb
))
7320 opts
[0] |= TD1_GTSENV6
;
7328 opts
[0] |= transport_offset
<< GTTCPHO_SHIFT
;
7329 opts
[1] |= min(mss
, TD_MSS_MAX
) << TD1_MSS_SHIFT
;
7330 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
7333 if (unlikely(rtl_test_hw_pad_bug(tp
, skb
)))
7334 return !(skb_checksum_help(skb
) || eth_skb_pad(skb
));
7336 if (transport_offset
> TCPHO_MAX
) {
7337 netif_warn(tp
, tx_err
, tp
->dev
,
7338 "Invalid transport offset 0x%x\n",
7343 switch (get_protocol(skb
)) {
7344 case htons(ETH_P_IP
):
7345 opts
[1] |= TD1_IPv4_CS
;
7346 ip_protocol
= ip_hdr(skb
)->protocol
;
7349 case htons(ETH_P_IPV6
):
7350 opts
[1] |= TD1_IPv6_CS
;
7351 ip_protocol
= ipv6_hdr(skb
)->nexthdr
;
7355 ip_protocol
= IPPROTO_RAW
;
7359 if (ip_protocol
== IPPROTO_TCP
)
7360 opts
[1] |= TD1_TCP_CS
;
7361 else if (ip_protocol
== IPPROTO_UDP
)
7362 opts
[1] |= TD1_UDP_CS
;
7366 opts
[1] |= transport_offset
<< TCPHO_SHIFT
;
7368 if (unlikely(rtl_test_hw_pad_bug(tp
, skb
)))
7369 return !eth_skb_pad(skb
);
7375 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
7376 struct net_device
*dev
)
7378 struct rtl8169_private
*tp
= netdev_priv(dev
);
7379 unsigned int entry
= tp
->cur_tx
% NUM_TX_DESC
;
7380 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
7381 void __iomem
*ioaddr
= tp
->mmio_addr
;
7382 struct device
*d
= &tp
->pci_dev
->dev
;
7388 if (unlikely(!TX_FRAGS_READY_FOR(tp
, skb_shinfo(skb
)->nr_frags
))) {
7389 netif_err(tp
, drv
, dev
, "BUG! Tx Ring full when queue awake!\n");
7393 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
7396 opts
[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb
));
7399 if (!tp
->tso_csum(tp
, skb
, opts
)) {
7400 r8169_csum_workaround(tp
, skb
);
7401 return NETDEV_TX_OK
;
7404 len
= skb_headlen(skb
);
7405 mapping
= dma_map_single(d
, skb
->data
, len
, DMA_TO_DEVICE
);
7406 if (unlikely(dma_mapping_error(d
, mapping
))) {
7407 if (net_ratelimit())
7408 netif_err(tp
, drv
, dev
, "Failed to map TX DMA!\n");
7412 tp
->tx_skb
[entry
].len
= len
;
7413 txd
->addr
= cpu_to_le64(mapping
);
7415 frags
= rtl8169_xmit_frags(tp
, skb
, opts
);
7419 opts
[0] |= FirstFrag
;
7421 opts
[0] |= FirstFrag
| LastFrag
;
7422 tp
->tx_skb
[entry
].skb
= skb
;
7425 txd
->opts2
= cpu_to_le32(opts
[1]);
7427 skb_tx_timestamp(skb
);
7429 /* Force memory writes to complete before releasing descriptor */
7432 /* Anti gcc 2.95.3 bugware (sic) */
7433 status
= opts
[0] | len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
7434 txd
->opts1
= cpu_to_le32(status
);
7436 /* Force all memory writes to complete before notifying device */
7439 tp
->cur_tx
+= frags
+ 1;
7441 RTL_W8(TxPoll
, NPQ
);
7445 if (!TX_FRAGS_READY_FOR(tp
, MAX_SKB_FRAGS
)) {
7446 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7447 * not miss a ring update when it notices a stopped queue.
7450 netif_stop_queue(dev
);
7451 /* Sync with rtl_tx:
7452 * - publish queue status and cur_tx ring index (write barrier)
7453 * - refresh dirty_tx ring index (read barrier).
7454 * May the current thread have a pessimistic view of the ring
7455 * status and forget to wake up queue, a racing rtl_tx thread
7459 if (TX_FRAGS_READY_FOR(tp
, MAX_SKB_FRAGS
))
7460 netif_wake_queue(dev
);
7463 return NETDEV_TX_OK
;
7466 rtl8169_unmap_tx_skb(d
, tp
->tx_skb
+ entry
, txd
);
7468 dev_kfree_skb_any(skb
);
7469 dev
->stats
.tx_dropped
++;
7470 return NETDEV_TX_OK
;
7473 netif_stop_queue(dev
);
7474 dev
->stats
.tx_dropped
++;
7475 return NETDEV_TX_BUSY
;
7478 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
7480 struct rtl8169_private
*tp
= netdev_priv(dev
);
7481 struct pci_dev
*pdev
= tp
->pci_dev
;
7482 u16 pci_status
, pci_cmd
;
7484 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
7485 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
7487 netif_err(tp
, intr
, dev
, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7488 pci_cmd
, pci_status
);
7491 * The recovery sequence below admits a very elaborated explanation:
7492 * - it seems to work;
7493 * - I did not see what else could be done;
7494 * - it makes iop3xx happy.
7496 * Feel free to adjust to your needs.
7498 if (pdev
->broken_parity_status
)
7499 pci_cmd
&= ~PCI_COMMAND_PARITY
;
7501 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
7503 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
7505 pci_write_config_word(pdev
, PCI_STATUS
,
7506 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
7507 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
7508 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
7510 /* The infamous DAC f*ckup only happens at boot time */
7511 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->cur_rx
) {
7512 void __iomem
*ioaddr
= tp
->mmio_addr
;
7514 netif_info(tp
, intr
, dev
, "disabling PCI DAC\n");
7515 tp
->cp_cmd
&= ~PCIDAC
;
7516 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
7517 dev
->features
&= ~NETIF_F_HIGHDMA
;
7520 rtl8169_hw_reset(tp
);
7522 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
7525 static void rtl_tx(struct net_device
*dev
, struct rtl8169_private
*tp
)
7527 unsigned int dirty_tx
, tx_left
;
7529 dirty_tx
= tp
->dirty_tx
;
7531 tx_left
= tp
->cur_tx
- dirty_tx
;
7533 while (tx_left
> 0) {
7534 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
7535 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
7538 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
7539 if (status
& DescOwn
)
7542 /* This barrier is needed to keep us from reading
7543 * any other fields out of the Tx descriptor until
7544 * we know the status of DescOwn
7548 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
7549 tp
->TxDescArray
+ entry
);
7550 if (status
& LastFrag
) {
7551 u64_stats_update_begin(&tp
->tx_stats
.syncp
);
7552 tp
->tx_stats
.packets
++;
7553 tp
->tx_stats
.bytes
+= tx_skb
->skb
->len
;
7554 u64_stats_update_end(&tp
->tx_stats
.syncp
);
7555 dev_consume_skb_any(tx_skb
->skb
);
7562 if (tp
->dirty_tx
!= dirty_tx
) {
7563 tp
->dirty_tx
= dirty_tx
;
7564 /* Sync with rtl8169_start_xmit:
7565 * - publish dirty_tx ring index (write barrier)
7566 * - refresh cur_tx ring index and queue status (read barrier)
7567 * May the current thread miss the stopped queue condition,
7568 * a racing xmit thread can only have a right view of the
7572 if (netif_queue_stopped(dev
) &&
7573 TX_FRAGS_READY_FOR(tp
, MAX_SKB_FRAGS
)) {
7574 netif_wake_queue(dev
);
7577 * 8168 hack: TxPoll requests are lost when the Tx packets are
7578 * too close. Let's kick an extra TxPoll request when a burst
7579 * of start_xmit activity is detected (if it is not detected,
7580 * it is slow enough). -- FR
7582 if (tp
->cur_tx
!= dirty_tx
) {
7583 void __iomem
*ioaddr
= tp
->mmio_addr
;
7585 RTL_W8(TxPoll
, NPQ
);
7590 static inline int rtl8169_fragmented_frame(u32 status
)
7592 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
7595 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, u32 opts1
)
7597 u32 status
= opts1
& RxProtoMask
;
7599 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
7600 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)))
7601 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
7603 skb_checksum_none_assert(skb
);
7606 static struct sk_buff
*rtl8169_try_rx_copy(void *data
,
7607 struct rtl8169_private
*tp
,
7611 struct sk_buff
*skb
;
7612 struct device
*d
= &tp
->pci_dev
->dev
;
7614 data
= rtl8169_align(data
);
7615 dma_sync_single_for_cpu(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
7617 skb
= napi_alloc_skb(&tp
->napi
, pkt_size
);
7619 memcpy(skb
->data
, data
, pkt_size
);
7620 dma_sync_single_for_device(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
7625 static int rtl_rx(struct net_device
*dev
, struct rtl8169_private
*tp
, u32 budget
)
7627 unsigned int cur_rx
, rx_left
;
7630 cur_rx
= tp
->cur_rx
;
7632 for (rx_left
= min(budget
, NUM_RX_DESC
); rx_left
> 0; rx_left
--, cur_rx
++) {
7633 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
7634 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
7637 status
= le32_to_cpu(desc
->opts1
) & tp
->opts1_mask
;
7638 if (status
& DescOwn
)
7641 /* This barrier is needed to keep us from reading
7642 * any other fields out of the Rx descriptor until
7643 * we know the status of DescOwn
7647 if (unlikely(status
& RxRES
)) {
7648 netif_info(tp
, rx_err
, dev
, "Rx ERROR. status = %08x\n",
7650 dev
->stats
.rx_errors
++;
7651 if (status
& (RxRWT
| RxRUNT
))
7652 dev
->stats
.rx_length_errors
++;
7654 dev
->stats
.rx_crc_errors
++;
7655 if (status
& RxFOVF
) {
7656 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
7657 dev
->stats
.rx_fifo_errors
++;
7659 if ((status
& (RxRUNT
| RxCRC
)) &&
7660 !(status
& (RxRWT
| RxFOVF
)) &&
7661 (dev
->features
& NETIF_F_RXALL
))
7664 struct sk_buff
*skb
;
7669 addr
= le64_to_cpu(desc
->addr
);
7670 if (likely(!(dev
->features
& NETIF_F_RXFCS
)))
7671 pkt_size
= (status
& 0x00003fff) - 4;
7673 pkt_size
= status
& 0x00003fff;
7676 * The driver does not support incoming fragmented
7677 * frames. They are seen as a symptom of over-mtu
7680 if (unlikely(rtl8169_fragmented_frame(status
))) {
7681 dev
->stats
.rx_dropped
++;
7682 dev
->stats
.rx_length_errors
++;
7683 goto release_descriptor
;
7686 skb
= rtl8169_try_rx_copy(tp
->Rx_databuff
[entry
],
7687 tp
, pkt_size
, addr
);
7689 dev
->stats
.rx_dropped
++;
7690 goto release_descriptor
;
7693 rtl8169_rx_csum(skb
, status
);
7694 skb_put(skb
, pkt_size
);
7695 skb
->protocol
= eth_type_trans(skb
, dev
);
7697 rtl8169_rx_vlan_tag(desc
, skb
);
7699 if (skb
->pkt_type
== PACKET_MULTICAST
)
7700 dev
->stats
.multicast
++;
7702 napi_gro_receive(&tp
->napi
, skb
);
7704 u64_stats_update_begin(&tp
->rx_stats
.syncp
);
7705 tp
->rx_stats
.packets
++;
7706 tp
->rx_stats
.bytes
+= pkt_size
;
7707 u64_stats_update_end(&tp
->rx_stats
.syncp
);
7711 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
7714 count
= cur_rx
- tp
->cur_rx
;
7715 tp
->cur_rx
= cur_rx
;
7720 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
7722 struct net_device
*dev
= dev_instance
;
7723 struct rtl8169_private
*tp
= netdev_priv(dev
);
7727 status
= rtl_get_events(tp
);
7728 if (status
&& status
!= 0xffff) {
7729 status
&= RTL_EVENT_NAPI
| tp
->event_slow
;
7733 rtl_irq_disable(tp
);
7734 napi_schedule(&tp
->napi
);
7737 return IRQ_RETVAL(handled
);
7741 * Workqueue context.
7743 static void rtl_slow_event_work(struct rtl8169_private
*tp
)
7745 struct net_device
*dev
= tp
->dev
;
7748 status
= rtl_get_events(tp
) & tp
->event_slow
;
7749 rtl_ack_events(tp
, status
);
7751 if (unlikely(status
& RxFIFOOver
)) {
7752 switch (tp
->mac_version
) {
7753 /* Work around for rx fifo overflow */
7754 case RTL_GIGA_MAC_VER_11
:
7755 netif_stop_queue(dev
);
7756 /* XXX - Hack alert. See rtl_task(). */
7757 set_bit(RTL_FLAG_TASK_RESET_PENDING
, tp
->wk
.flags
);
7763 if (unlikely(status
& SYSErr
))
7764 rtl8169_pcierr_interrupt(dev
);
7766 if (status
& LinkChg
)
7767 __rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
, true);
7769 rtl_irq_enable_all(tp
);
7772 static void rtl_task(struct work_struct
*work
)
7774 static const struct {
7776 void (*action
)(struct rtl8169_private
*);
7778 /* XXX - keep rtl_slow_event_work() as first element. */
7779 { RTL_FLAG_TASK_SLOW_PENDING
, rtl_slow_event_work
},
7780 { RTL_FLAG_TASK_RESET_PENDING
, rtl_reset_work
},
7781 { RTL_FLAG_TASK_PHY_PENDING
, rtl_phy_work
}
7783 struct rtl8169_private
*tp
=
7784 container_of(work
, struct rtl8169_private
, wk
.work
);
7785 struct net_device
*dev
= tp
->dev
;
7790 if (!netif_running(dev
) ||
7791 !test_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
))
7794 for (i
= 0; i
< ARRAY_SIZE(rtl_work
); i
++) {
7797 pending
= test_and_clear_bit(rtl_work
[i
].bitnr
, tp
->wk
.flags
);
7799 rtl_work
[i
].action(tp
);
7803 rtl_unlock_work(tp
);
7806 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
7808 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
7809 struct net_device
*dev
= tp
->dev
;
7810 u16 enable_mask
= RTL_EVENT_NAPI
| tp
->event_slow
;
7814 status
= rtl_get_events(tp
);
7815 rtl_ack_events(tp
, status
& ~tp
->event_slow
);
7817 if (status
& RTL_EVENT_NAPI_RX
)
7818 work_done
= rtl_rx(dev
, tp
, (u32
) budget
);
7820 if (status
& RTL_EVENT_NAPI_TX
)
7823 if (status
& tp
->event_slow
) {
7824 enable_mask
&= ~tp
->event_slow
;
7826 rtl_schedule_task(tp
, RTL_FLAG_TASK_SLOW_PENDING
);
7829 if (work_done
< budget
) {
7830 napi_complete_done(napi
, work_done
);
7832 rtl_irq_enable(tp
, enable_mask
);
7839 static void rtl8169_rx_missed(struct net_device
*dev
, void __iomem
*ioaddr
)
7841 struct rtl8169_private
*tp
= netdev_priv(dev
);
7843 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
7846 dev
->stats
.rx_missed_errors
+= (RTL_R32(RxMissed
) & 0xffffff);
7847 RTL_W32(RxMissed
, 0);
7850 static void rtl8169_down(struct net_device
*dev
)
7852 struct rtl8169_private
*tp
= netdev_priv(dev
);
7853 void __iomem
*ioaddr
= tp
->mmio_addr
;
7855 del_timer_sync(&tp
->timer
);
7857 napi_disable(&tp
->napi
);
7858 netif_stop_queue(dev
);
7860 rtl8169_hw_reset(tp
);
7862 * At this point device interrupts can not be enabled in any function,
7863 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7864 * and napi is disabled (rtl8169_poll).
7866 rtl8169_rx_missed(dev
, ioaddr
);
7868 /* Give a racing hard_start_xmit a few cycles to complete. */
7869 synchronize_sched();
7871 rtl8169_tx_clear(tp
);
7873 rtl8169_rx_clear(tp
);
7875 rtl_pll_power_down(tp
);
7878 static int rtl8169_close(struct net_device
*dev
)
7880 struct rtl8169_private
*tp
= netdev_priv(dev
);
7881 struct pci_dev
*pdev
= tp
->pci_dev
;
7883 pm_runtime_get_sync(&pdev
->dev
);
7885 /* Update counters before going down */
7886 rtl8169_update_counters(dev
);
7889 clear_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
7892 rtl_unlock_work(tp
);
7894 cancel_work_sync(&tp
->wk
.work
);
7896 free_irq(pdev
->irq
, dev
);
7898 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
7900 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
7902 tp
->TxDescArray
= NULL
;
7903 tp
->RxDescArray
= NULL
;
7905 pm_runtime_put_sync(&pdev
->dev
);
7910 #ifdef CONFIG_NET_POLL_CONTROLLER
7911 static void rtl8169_netpoll(struct net_device
*dev
)
7913 struct rtl8169_private
*tp
= netdev_priv(dev
);
7915 rtl8169_interrupt(tp
->pci_dev
->irq
, dev
);
7919 static int rtl_open(struct net_device
*dev
)
7921 struct rtl8169_private
*tp
= netdev_priv(dev
);
7922 void __iomem
*ioaddr
= tp
->mmio_addr
;
7923 struct pci_dev
*pdev
= tp
->pci_dev
;
7924 int retval
= -ENOMEM
;
7926 pm_runtime_get_sync(&pdev
->dev
);
7929 * Rx and Tx descriptors needs 256 bytes alignment.
7930 * dma_alloc_coherent provides more.
7932 tp
->TxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
,
7933 &tp
->TxPhyAddr
, GFP_KERNEL
);
7934 if (!tp
->TxDescArray
)
7935 goto err_pm_runtime_put
;
7937 tp
->RxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
,
7938 &tp
->RxPhyAddr
, GFP_KERNEL
);
7939 if (!tp
->RxDescArray
)
7942 retval
= rtl8169_init_ring(dev
);
7946 INIT_WORK(&tp
->wk
.work
, rtl_task
);
7950 rtl_request_firmware(tp
);
7952 retval
= request_irq(pdev
->irq
, rtl8169_interrupt
,
7953 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
7956 goto err_release_fw_2
;
7960 set_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
7962 napi_enable(&tp
->napi
);
7964 rtl8169_init_phy(dev
, tp
);
7966 __rtl8169_set_features(dev
, dev
->features
);
7968 rtl_pll_power_up(tp
);
7972 if (!rtl8169_init_counter_offsets(dev
))
7973 netif_warn(tp
, hw
, dev
, "counter reset/update failed\n");
7975 netif_start_queue(dev
);
7977 rtl_unlock_work(tp
);
7979 tp
->saved_wolopts
= 0;
7980 pm_runtime_put_noidle(&pdev
->dev
);
7982 rtl8169_check_link_status(dev
, tp
, ioaddr
);
7987 rtl_release_firmware(tp
);
7988 rtl8169_rx_clear(tp
);
7990 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
7992 tp
->RxDescArray
= NULL
;
7994 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
7996 tp
->TxDescArray
= NULL
;
7998 pm_runtime_put_noidle(&pdev
->dev
);
8003 rtl8169_get_stats64(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
8005 struct rtl8169_private
*tp
= netdev_priv(dev
);
8006 void __iomem
*ioaddr
= tp
->mmio_addr
;
8007 struct pci_dev
*pdev
= tp
->pci_dev
;
8008 struct rtl8169_counters
*counters
= tp
->counters
;
8011 pm_runtime_get_noresume(&pdev
->dev
);
8013 if (netif_running(dev
) && pm_runtime_active(&pdev
->dev
))
8014 rtl8169_rx_missed(dev
, ioaddr
);
8017 start
= u64_stats_fetch_begin_irq(&tp
->rx_stats
.syncp
);
8018 stats
->rx_packets
= tp
->rx_stats
.packets
;
8019 stats
->rx_bytes
= tp
->rx_stats
.bytes
;
8020 } while (u64_stats_fetch_retry_irq(&tp
->rx_stats
.syncp
, start
));
8023 start
= u64_stats_fetch_begin_irq(&tp
->tx_stats
.syncp
);
8024 stats
->tx_packets
= tp
->tx_stats
.packets
;
8025 stats
->tx_bytes
= tp
->tx_stats
.bytes
;
8026 } while (u64_stats_fetch_retry_irq(&tp
->tx_stats
.syncp
, start
));
8028 stats
->rx_dropped
= dev
->stats
.rx_dropped
;
8029 stats
->tx_dropped
= dev
->stats
.tx_dropped
;
8030 stats
->rx_length_errors
= dev
->stats
.rx_length_errors
;
8031 stats
->rx_errors
= dev
->stats
.rx_errors
;
8032 stats
->rx_crc_errors
= dev
->stats
.rx_crc_errors
;
8033 stats
->rx_fifo_errors
= dev
->stats
.rx_fifo_errors
;
8034 stats
->rx_missed_errors
= dev
->stats
.rx_missed_errors
;
8035 stats
->multicast
= dev
->stats
.multicast
;
8038 * Fetch additonal counter values missing in stats collected by driver
8039 * from tally counters.
8041 if (pm_runtime_active(&pdev
->dev
))
8042 rtl8169_update_counters(dev
);
8045 * Subtract values fetched during initalization.
8046 * See rtl8169_init_counter_offsets for a description why we do that.
8048 stats
->tx_errors
= le64_to_cpu(counters
->tx_errors
) -
8049 le64_to_cpu(tp
->tc_offset
.tx_errors
);
8050 stats
->collisions
= le32_to_cpu(counters
->tx_multi_collision
) -
8051 le32_to_cpu(tp
->tc_offset
.tx_multi_collision
);
8052 stats
->tx_aborted_errors
= le16_to_cpu(counters
->tx_aborted
) -
8053 le16_to_cpu(tp
->tc_offset
.tx_aborted
);
8055 pm_runtime_put_noidle(&pdev
->dev
);
8058 static void rtl8169_net_suspend(struct net_device
*dev
)
8060 struct rtl8169_private
*tp
= netdev_priv(dev
);
8062 if (!netif_running(dev
))
8065 netif_device_detach(dev
);
8066 netif_stop_queue(dev
);
8069 napi_disable(&tp
->napi
);
8070 clear_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
8071 rtl_unlock_work(tp
);
8073 rtl_pll_power_down(tp
);
8078 static int rtl8169_suspend(struct device
*device
)
8080 struct pci_dev
*pdev
= to_pci_dev(device
);
8081 struct net_device
*dev
= pci_get_drvdata(pdev
);
8083 rtl8169_net_suspend(dev
);
8088 static void __rtl8169_resume(struct net_device
*dev
)
8090 struct rtl8169_private
*tp
= netdev_priv(dev
);
8092 netif_device_attach(dev
);
8094 rtl_pll_power_up(tp
);
8097 napi_enable(&tp
->napi
);
8098 set_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
8099 rtl_unlock_work(tp
);
8101 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
8104 static int rtl8169_resume(struct device
*device
)
8106 struct pci_dev
*pdev
= to_pci_dev(device
);
8107 struct net_device
*dev
= pci_get_drvdata(pdev
);
8108 struct rtl8169_private
*tp
= netdev_priv(dev
);
8110 rtl8169_init_phy(dev
, tp
);
8112 if (netif_running(dev
))
8113 __rtl8169_resume(dev
);
8118 static int rtl8169_runtime_suspend(struct device
*device
)
8120 struct pci_dev
*pdev
= to_pci_dev(device
);
8121 struct net_device
*dev
= pci_get_drvdata(pdev
);
8122 struct rtl8169_private
*tp
= netdev_priv(dev
);
8124 if (!tp
->TxDescArray
)
8128 tp
->saved_wolopts
= __rtl8169_get_wol(tp
);
8129 __rtl8169_set_wol(tp
, WAKE_ANY
);
8130 rtl_unlock_work(tp
);
8132 rtl8169_net_suspend(dev
);
8134 /* Update counters before going runtime suspend */
8135 rtl8169_rx_missed(dev
, tp
->mmio_addr
);
8136 rtl8169_update_counters(dev
);
8141 static int rtl8169_runtime_resume(struct device
*device
)
8143 struct pci_dev
*pdev
= to_pci_dev(device
);
8144 struct net_device
*dev
= pci_get_drvdata(pdev
);
8145 struct rtl8169_private
*tp
= netdev_priv(dev
);
8146 rtl_rar_set(tp
, dev
->dev_addr
);
8148 if (!tp
->TxDescArray
)
8152 __rtl8169_set_wol(tp
, tp
->saved_wolopts
);
8153 tp
->saved_wolopts
= 0;
8154 rtl_unlock_work(tp
);
8156 rtl8169_init_phy(dev
, tp
);
8158 __rtl8169_resume(dev
);
8163 static int rtl8169_runtime_idle(struct device
*device
)
8165 struct pci_dev
*pdev
= to_pci_dev(device
);
8166 struct net_device
*dev
= pci_get_drvdata(pdev
);
8167 struct rtl8169_private
*tp
= netdev_priv(dev
);
8169 return tp
->TxDescArray
? -EBUSY
: 0;
8172 static const struct dev_pm_ops rtl8169_pm_ops
= {
8173 .suspend
= rtl8169_suspend
,
8174 .resume
= rtl8169_resume
,
8175 .freeze
= rtl8169_suspend
,
8176 .thaw
= rtl8169_resume
,
8177 .poweroff
= rtl8169_suspend
,
8178 .restore
= rtl8169_resume
,
8179 .runtime_suspend
= rtl8169_runtime_suspend
,
8180 .runtime_resume
= rtl8169_runtime_resume
,
8181 .runtime_idle
= rtl8169_runtime_idle
,
8184 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
8186 #else /* !CONFIG_PM */
8188 #define RTL8169_PM_OPS NULL
8190 #endif /* !CONFIG_PM */
8192 static void rtl_wol_shutdown_quirk(struct rtl8169_private
*tp
)
8194 void __iomem
*ioaddr
= tp
->mmio_addr
;
8196 /* WoL fails with 8168b when the receiver is disabled. */
8197 switch (tp
->mac_version
) {
8198 case RTL_GIGA_MAC_VER_11
:
8199 case RTL_GIGA_MAC_VER_12
:
8200 case RTL_GIGA_MAC_VER_17
:
8201 pci_clear_master(tp
->pci_dev
);
8203 RTL_W8(ChipCmd
, CmdRxEnb
);
8212 static void rtl_shutdown(struct pci_dev
*pdev
)
8214 struct net_device
*dev
= pci_get_drvdata(pdev
);
8215 struct rtl8169_private
*tp
= netdev_priv(dev
);
8216 struct device
*d
= &pdev
->dev
;
8218 pm_runtime_get_sync(d
);
8220 rtl8169_net_suspend(dev
);
8222 /* Restore original MAC address */
8223 rtl_rar_set(tp
, dev
->perm_addr
);
8225 rtl8169_hw_reset(tp
);
8227 if (system_state
== SYSTEM_POWER_OFF
) {
8228 if (__rtl8169_get_wol(tp
) & WAKE_ANY
) {
8229 rtl_wol_suspend_quirk(tp
);
8230 rtl_wol_shutdown_quirk(tp
);
8233 pci_wake_from_d3(pdev
, true);
8234 pci_set_power_state(pdev
, PCI_D3hot
);
8237 pm_runtime_put_noidle(d
);
8240 static void rtl_remove_one(struct pci_dev
*pdev
)
8242 struct net_device
*dev
= pci_get_drvdata(pdev
);
8243 struct rtl8169_private
*tp
= netdev_priv(dev
);
8245 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
8246 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
8247 tp
->mac_version
== RTL_GIGA_MAC_VER_31
||
8248 tp
->mac_version
== RTL_GIGA_MAC_VER_49
||
8249 tp
->mac_version
== RTL_GIGA_MAC_VER_50
||
8250 tp
->mac_version
== RTL_GIGA_MAC_VER_51
) &&
8251 r8168_check_dash(tp
)) {
8252 rtl8168_driver_stop(tp
);
8255 netif_napi_del(&tp
->napi
);
8257 unregister_netdev(dev
);
8259 dma_free_coherent(&tp
->pci_dev
->dev
, sizeof(*tp
->counters
),
8260 tp
->counters
, tp
->counters_phys_addr
);
8262 rtl_release_firmware(tp
);
8264 if (pci_dev_run_wake(pdev
))
8265 pm_runtime_get_noresume(&pdev
->dev
);
8267 /* restore original MAC address */
8268 rtl_rar_set(tp
, dev
->perm_addr
);
8270 rtl_disable_msi(pdev
, tp
);
8271 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
8274 static const struct net_device_ops rtl_netdev_ops
= {
8275 .ndo_open
= rtl_open
,
8276 .ndo_stop
= rtl8169_close
,
8277 .ndo_get_stats64
= rtl8169_get_stats64
,
8278 .ndo_start_xmit
= rtl8169_start_xmit
,
8279 .ndo_tx_timeout
= rtl8169_tx_timeout
,
8280 .ndo_validate_addr
= eth_validate_addr
,
8281 .ndo_change_mtu
= rtl8169_change_mtu
,
8282 .ndo_fix_features
= rtl8169_fix_features
,
8283 .ndo_set_features
= rtl8169_set_features
,
8284 .ndo_set_mac_address
= rtl_set_mac_address
,
8285 .ndo_do_ioctl
= rtl8169_ioctl
,
8286 .ndo_set_rx_mode
= rtl_set_rx_mode
,
8287 #ifdef CONFIG_NET_POLL_CONTROLLER
8288 .ndo_poll_controller
= rtl8169_netpoll
,
8293 static const struct rtl_cfg_info
{
8294 void (*hw_start
)(struct net_device
*);
8295 unsigned int region
;
8299 const struct rtl_coalesce_info
*coalesce_info
;
8301 } rtl_cfg_infos
[] = {
8303 .hw_start
= rtl_hw_start_8169
,
8306 .event_slow
= SYSErr
| LinkChg
| RxOverflow
| RxFIFOOver
,
8307 .features
= RTL_FEATURE_GMII
,
8308 .coalesce_info
= rtl_coalesce_info_8169
,
8309 .default_ver
= RTL_GIGA_MAC_VER_01
,
8312 .hw_start
= rtl_hw_start_8168
,
8315 .event_slow
= SYSErr
| LinkChg
| RxOverflow
,
8316 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
,
8317 .coalesce_info
= rtl_coalesce_info_8168_8136
,
8318 .default_ver
= RTL_GIGA_MAC_VER_11
,
8321 .hw_start
= rtl_hw_start_8101
,
8324 .event_slow
= SYSErr
| LinkChg
| RxOverflow
| RxFIFOOver
|
8326 .features
= RTL_FEATURE_MSI
,
8327 .coalesce_info
= rtl_coalesce_info_8168_8136
,
8328 .default_ver
= RTL_GIGA_MAC_VER_13
,
8332 /* Cfg9346_Unlock assumed. */
8333 static unsigned rtl_try_msi(struct rtl8169_private
*tp
,
8334 const struct rtl_cfg_info
*cfg
)
8336 void __iomem
*ioaddr
= tp
->mmio_addr
;
8340 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
8341 if (cfg
->features
& RTL_FEATURE_MSI
) {
8342 if (pci_enable_msi(tp
->pci_dev
)) {
8343 netif_info(tp
, hw
, tp
->dev
, "no MSI. Back to INTx.\n");
8346 msi
= RTL_FEATURE_MSI
;
8349 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
8350 RTL_W8(Config2
, cfg2
);
8354 DECLARE_RTL_COND(rtl_link_list_ready_cond
)
8356 void __iomem
*ioaddr
= tp
->mmio_addr
;
8358 return RTL_R8(MCU
) & LINK_LIST_RDY
;
8361 DECLARE_RTL_COND(rtl_rxtx_empty_cond
)
8363 void __iomem
*ioaddr
= tp
->mmio_addr
;
8365 return (RTL_R8(MCU
) & RXTX_EMPTY
) == RXTX_EMPTY
;
8368 static void rtl_hw_init_8168g(struct rtl8169_private
*tp
)
8370 void __iomem
*ioaddr
= tp
->mmio_addr
;
8373 tp
->ocp_base
= OCP_STD_PHY_BASE
;
8375 RTL_W32(MISC
, RTL_R32(MISC
) | RXDV_GATED_EN
);
8377 if (!rtl_udelay_loop_wait_high(tp
, &rtl_txcfg_empty_cond
, 100, 42))
8380 if (!rtl_udelay_loop_wait_high(tp
, &rtl_rxtx_empty_cond
, 100, 42))
8383 RTL_W8(ChipCmd
, RTL_R8(ChipCmd
) & ~(CmdTxEnb
| CmdRxEnb
));
8385 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
8387 data
= r8168_mac_ocp_read(tp
, 0xe8de);
8389 r8168_mac_ocp_write(tp
, 0xe8de, data
);
8391 if (!rtl_udelay_loop_wait_high(tp
, &rtl_link_list_ready_cond
, 100, 42))
8394 data
= r8168_mac_ocp_read(tp
, 0xe8de);
8396 r8168_mac_ocp_write(tp
, 0xe8de, data
);
8398 if (!rtl_udelay_loop_wait_high(tp
, &rtl_link_list_ready_cond
, 100, 42))
8402 static void rtl_hw_init_8168ep(struct rtl8169_private
*tp
)
8404 rtl8168ep_stop_cmac(tp
);
8405 rtl_hw_init_8168g(tp
);
8408 static void rtl_hw_initialize(struct rtl8169_private
*tp
)
8410 switch (tp
->mac_version
) {
8411 case RTL_GIGA_MAC_VER_40
:
8412 case RTL_GIGA_MAC_VER_41
:
8413 case RTL_GIGA_MAC_VER_42
:
8414 case RTL_GIGA_MAC_VER_43
:
8415 case RTL_GIGA_MAC_VER_44
:
8416 case RTL_GIGA_MAC_VER_45
:
8417 case RTL_GIGA_MAC_VER_46
:
8418 case RTL_GIGA_MAC_VER_47
:
8419 case RTL_GIGA_MAC_VER_48
:
8420 rtl_hw_init_8168g(tp
);
8422 case RTL_GIGA_MAC_VER_49
:
8423 case RTL_GIGA_MAC_VER_50
:
8424 case RTL_GIGA_MAC_VER_51
:
8425 rtl_hw_init_8168ep(tp
);
8432 static int rtl_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
8434 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
8435 const unsigned int region
= cfg
->region
;
8436 struct rtl8169_private
*tp
;
8437 struct mii_if_info
*mii
;
8438 struct net_device
*dev
;
8439 void __iomem
*ioaddr
;
8443 if (netif_msg_drv(&debug
)) {
8444 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
8445 MODULENAME
, RTL8169_VERSION
);
8448 dev
= alloc_etherdev(sizeof (*tp
));
8454 SET_NETDEV_DEV(dev
, &pdev
->dev
);
8455 dev
->netdev_ops
= &rtl_netdev_ops
;
8456 tp
= netdev_priv(dev
);
8459 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
8463 mii
->mdio_read
= rtl_mdio_read
;
8464 mii
->mdio_write
= rtl_mdio_write
;
8465 mii
->phy_id_mask
= 0x1f;
8466 mii
->reg_num_mask
= 0x1f;
8467 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
8469 /* disable ASPM completely as that cause random device stop working
8470 * problems as well as full system hangs for some PCIe devices users */
8471 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
| PCIE_LINK_STATE_L1
|
8472 PCIE_LINK_STATE_CLKPM
);
8474 /* enable device (incl. PCI PM wakeup and hotplug setup) */
8475 rc
= pci_enable_device(pdev
);
8477 netif_err(tp
, probe
, dev
, "enable failure\n");
8478 goto err_out_free_dev_1
;
8481 if (pci_set_mwi(pdev
) < 0)
8482 netif_info(tp
, probe
, dev
, "Mem-Wr-Inval unavailable\n");
8484 /* make sure PCI base addr 1 is MMIO */
8485 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
8486 netif_err(tp
, probe
, dev
,
8487 "region #%d not an MMIO resource, aborting\n",
8493 /* check for weird/broken PCI region reporting */
8494 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
8495 netif_err(tp
, probe
, dev
,
8496 "Invalid PCI region size(s), aborting\n");
8501 rc
= pci_request_regions(pdev
, MODULENAME
);
8503 netif_err(tp
, probe
, dev
, "could not request regions\n");
8507 /* ioremap MMIO region */
8508 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
8510 netif_err(tp
, probe
, dev
, "cannot remap MMIO, aborting\n");
8512 goto err_out_free_res_3
;
8514 tp
->mmio_addr
= ioaddr
;
8516 if (!pci_is_pcie(pdev
))
8517 netif_info(tp
, probe
, dev
, "not PCI Express\n");
8519 /* Identify chip attached to board */
8520 rtl8169_get_mac_version(tp
, dev
, cfg
->default_ver
);
8524 if ((sizeof(dma_addr_t
) > 4) &&
8525 (use_dac
== 1 || (use_dac
== -1 && pci_is_pcie(pdev
) &&
8526 tp
->mac_version
>= RTL_GIGA_MAC_VER_18
)) &&
8527 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) &&
8528 !pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64))) {
8530 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
8531 if (!pci_is_pcie(pdev
))
8532 tp
->cp_cmd
|= PCIDAC
;
8533 dev
->features
|= NETIF_F_HIGHDMA
;
8535 rc
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
8537 netif_err(tp
, probe
, dev
, "DMA configuration failed\n");
8538 goto err_out_unmap_4
;
8544 rtl_irq_disable(tp
);
8546 rtl_hw_initialize(tp
);
8550 rtl_ack_events(tp
, 0xffff);
8552 pci_set_master(pdev
);
8554 rtl_init_mdio_ops(tp
);
8555 rtl_init_pll_power_ops(tp
);
8556 rtl_init_jumbo_ops(tp
);
8557 rtl_init_csi_ops(tp
);
8559 rtl8169_print_mac_version(tp
);
8561 chipset
= tp
->mac_version
;
8562 tp
->txd_version
= rtl_chip_infos
[chipset
].txd_version
;
8564 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
8565 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
8566 RTL_W8(Config5
, RTL_R8(Config5
) & (BWF
| MWF
| UWF
| LanWake
| PMEStatus
));
8567 switch (tp
->mac_version
) {
8568 case RTL_GIGA_MAC_VER_34
:
8569 case RTL_GIGA_MAC_VER_35
:
8570 case RTL_GIGA_MAC_VER_36
:
8571 case RTL_GIGA_MAC_VER_37
:
8572 case RTL_GIGA_MAC_VER_38
:
8573 case RTL_GIGA_MAC_VER_40
:
8574 case RTL_GIGA_MAC_VER_41
:
8575 case RTL_GIGA_MAC_VER_42
:
8576 case RTL_GIGA_MAC_VER_43
:
8577 case RTL_GIGA_MAC_VER_44
:
8578 case RTL_GIGA_MAC_VER_45
:
8579 case RTL_GIGA_MAC_VER_46
:
8580 case RTL_GIGA_MAC_VER_47
:
8581 case RTL_GIGA_MAC_VER_48
:
8582 case RTL_GIGA_MAC_VER_49
:
8583 case RTL_GIGA_MAC_VER_50
:
8584 case RTL_GIGA_MAC_VER_51
:
8585 if (rtl_eri_read(tp
, 0xdc, ERIAR_EXGMAC
) & MagicPacket_v2
)
8586 tp
->features
|= RTL_FEATURE_WOL
;
8587 if ((RTL_R8(Config3
) & LinkUp
) != 0)
8588 tp
->features
|= RTL_FEATURE_WOL
;
8591 if ((RTL_R8(Config3
) & (LinkUp
| MagicPacket
)) != 0)
8592 tp
->features
|= RTL_FEATURE_WOL
;
8595 if ((RTL_R8(Config5
) & (UWF
| BWF
| MWF
)) != 0)
8596 tp
->features
|= RTL_FEATURE_WOL
;
8597 tp
->features
|= rtl_try_msi(tp
, cfg
);
8598 RTL_W8(Cfg9346
, Cfg9346_Lock
);
8600 if (rtl_tbi_enabled(tp
)) {
8601 tp
->set_speed
= rtl8169_set_speed_tbi
;
8602 tp
->get_link_ksettings
= rtl8169_get_link_ksettings_tbi
;
8603 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
8604 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
8605 tp
->link_ok
= rtl8169_tbi_link_ok
;
8606 tp
->do_ioctl
= rtl_tbi_ioctl
;
8608 tp
->set_speed
= rtl8169_set_speed_xmii
;
8609 tp
->get_link_ksettings
= rtl8169_get_link_ksettings_xmii
;
8610 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
8611 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
8612 tp
->link_ok
= rtl8169_xmii_link_ok
;
8613 tp
->do_ioctl
= rtl_xmii_ioctl
;
8616 mutex_init(&tp
->wk
.mutex
);
8617 u64_stats_init(&tp
->rx_stats
.syncp
);
8618 u64_stats_init(&tp
->tx_stats
.syncp
);
8620 /* Get MAC address */
8621 if (tp
->mac_version
== RTL_GIGA_MAC_VER_35
||
8622 tp
->mac_version
== RTL_GIGA_MAC_VER_36
||
8623 tp
->mac_version
== RTL_GIGA_MAC_VER_37
||
8624 tp
->mac_version
== RTL_GIGA_MAC_VER_38
||
8625 tp
->mac_version
== RTL_GIGA_MAC_VER_40
||
8626 tp
->mac_version
== RTL_GIGA_MAC_VER_41
||
8627 tp
->mac_version
== RTL_GIGA_MAC_VER_42
||
8628 tp
->mac_version
== RTL_GIGA_MAC_VER_43
||
8629 tp
->mac_version
== RTL_GIGA_MAC_VER_44
||
8630 tp
->mac_version
== RTL_GIGA_MAC_VER_45
||
8631 tp
->mac_version
== RTL_GIGA_MAC_VER_46
||
8632 tp
->mac_version
== RTL_GIGA_MAC_VER_47
||
8633 tp
->mac_version
== RTL_GIGA_MAC_VER_48
||
8634 tp
->mac_version
== RTL_GIGA_MAC_VER_49
||
8635 tp
->mac_version
== RTL_GIGA_MAC_VER_50
||
8636 tp
->mac_version
== RTL_GIGA_MAC_VER_51
) {
8639 *(u32
*)&mac_addr
[0] = rtl_eri_read(tp
, 0xe0, ERIAR_EXGMAC
);
8640 *(u16
*)&mac_addr
[2] = rtl_eri_read(tp
, 0xe4, ERIAR_EXGMAC
);
8642 if (is_valid_ether_addr((u8
*)mac_addr
))
8643 rtl_rar_set(tp
, (u8
*)mac_addr
);
8645 for (i
= 0; i
< ETH_ALEN
; i
++)
8646 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
8648 dev
->ethtool_ops
= &rtl8169_ethtool_ops
;
8649 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
8651 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, R8169_NAPI_WEIGHT
);
8653 /* don't enable SG, IP_CSUM and TSO by default - it might not work
8654 * properly for all devices */
8655 dev
->features
|= NETIF_F_RXCSUM
|
8656 NETIF_F_HW_VLAN_CTAG_TX
| NETIF_F_HW_VLAN_CTAG_RX
;
8658 dev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
8659 NETIF_F_RXCSUM
| NETIF_F_HW_VLAN_CTAG_TX
|
8660 NETIF_F_HW_VLAN_CTAG_RX
;
8661 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
8664 tp
->cp_cmd
|= RxChkSum
| RxVlan
;
8667 * Pretend we are using VLANs; This bypasses a nasty bug where
8668 * Interrupts stop flowing on high load on 8110SCd controllers.
8670 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
8671 /* Disallow toggling */
8672 dev
->hw_features
&= ~NETIF_F_HW_VLAN_CTAG_RX
;
8674 if (tp
->txd_version
== RTL_TD_0
)
8675 tp
->tso_csum
= rtl8169_tso_csum_v1
;
8676 else if (tp
->txd_version
== RTL_TD_1
) {
8677 tp
->tso_csum
= rtl8169_tso_csum_v2
;
8678 dev
->hw_features
|= NETIF_F_IPV6_CSUM
| NETIF_F_TSO6
;
8682 dev
->hw_features
|= NETIF_F_RXALL
;
8683 dev
->hw_features
|= NETIF_F_RXFCS
;
8685 /* MTU range: 60 - hw-specific max */
8686 dev
->min_mtu
= ETH_ZLEN
;
8687 dev
->max_mtu
= rtl_chip_infos
[chipset
].jumbo_max
;
8689 tp
->hw_start
= cfg
->hw_start
;
8690 tp
->event_slow
= cfg
->event_slow
;
8691 tp
->coalesce_info
= cfg
->coalesce_info
;
8693 tp
->opts1_mask
= (tp
->mac_version
!= RTL_GIGA_MAC_VER_01
) ?
8694 ~(RxBOVF
| RxFOVF
) : ~0;
8696 timer_setup(&tp
->timer
, rtl8169_phy_timer
, 0);
8698 tp
->rtl_fw
= RTL_FIRMWARE_UNKNOWN
;
8700 tp
->counters
= dma_alloc_coherent (&pdev
->dev
, sizeof(*tp
->counters
),
8701 &tp
->counters_phys_addr
, GFP_KERNEL
);
8702 if (!tp
->counters
) {
8707 rc
= register_netdev(dev
);
8711 pci_set_drvdata(pdev
, dev
);
8713 netif_info(tp
, probe
, dev
, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
8714 rtl_chip_infos
[chipset
].name
, ioaddr
, dev
->dev_addr
,
8715 (u32
)(RTL_R32(TxConfig
) & 0x9cf0f8ff), pdev
->irq
);
8716 if (rtl_chip_infos
[chipset
].jumbo_max
!= JUMBO_1K
) {
8717 netif_info(tp
, probe
, dev
, "jumbo features [frames: %d bytes, "
8718 "tx checksumming: %s]\n",
8719 rtl_chip_infos
[chipset
].jumbo_max
,
8720 rtl_chip_infos
[chipset
].jumbo_tx_csum
? "ok" : "ko");
8723 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
8724 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
8725 tp
->mac_version
== RTL_GIGA_MAC_VER_31
||
8726 tp
->mac_version
== RTL_GIGA_MAC_VER_49
||
8727 tp
->mac_version
== RTL_GIGA_MAC_VER_50
||
8728 tp
->mac_version
== RTL_GIGA_MAC_VER_51
) &&
8729 r8168_check_dash(tp
)) {
8730 rtl8168_driver_start(tp
);
8733 if (pci_dev_run_wake(pdev
))
8734 pm_runtime_put_noidle(&pdev
->dev
);
8736 netif_carrier_off(dev
);
8742 dma_free_coherent(&pdev
->dev
, sizeof(*tp
->counters
), tp
->counters
,
8743 tp
->counters_phys_addr
);
8745 netif_napi_del(&tp
->napi
);
8746 rtl_disable_msi(pdev
, tp
);
8750 pci_release_regions(pdev
);
8752 pci_clear_mwi(pdev
);
8753 pci_disable_device(pdev
);
8759 static struct pci_driver rtl8169_pci_driver
= {
8761 .id_table
= rtl8169_pci_tbl
,
8762 .probe
= rtl_init_one
,
8763 .remove
= rtl_remove_one
,
8764 .shutdown
= rtl_shutdown
,
8765 .driver
.pm
= RTL8169_PM_OPS
,
8768 module_pci_driver(rtl8169_pci_driver
);