2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28 #include <linux/pci-aspm.h>
29 #include <linux/prefetch.h>
30 #include <linux/ipv6.h>
31 #include <net/ip6_checksum.h>
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
45 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
47 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
48 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
49 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
50 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
51 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
52 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
53 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
54 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
55 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
56 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
57 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
58 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
61 #define assert(expr) \
63 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
64 #expr,__FILE__,__func__,__LINE__); \
66 #define dprintk(fmt, args...) \
67 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
69 #define assert(expr) do {} while (0)
70 #define dprintk(fmt, args...) do {} while (0)
71 #endif /* RTL8169_DEBUG */
73 #define R8169_MSG_DEFAULT \
74 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
76 #define TX_SLOTS_AVAIL(tp) \
77 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
79 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
80 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
81 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
83 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
84 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
85 static const int multicast_filter_limit
= 32;
87 #define MAX_READ_REQUEST_SHIFT 12
88 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
89 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
91 #define R8169_REGS_SIZE 256
92 #define R8169_NAPI_WEIGHT 64
93 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
94 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
95 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
96 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
98 #define RTL8169_TX_TIMEOUT (6*HZ)
99 #define RTL8169_PHY_TIMEOUT (10*HZ)
101 /* write/read MMIO register */
102 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
103 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
104 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
105 #define RTL_R8(reg) readb (ioaddr + (reg))
106 #define RTL_R16(reg) readw (ioaddr + (reg))
107 #define RTL_R32(reg) readl (ioaddr + (reg))
110 RTL_GIGA_MAC_VER_01
= 0,
161 RTL_GIGA_MAC_NONE
= 0xff,
164 enum rtl_tx_desc_version
{
169 #define JUMBO_1K ETH_DATA_LEN
170 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
171 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
172 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
173 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
175 #define _R(NAME,TD,FW,SZ,B) { \
183 static const struct {
185 enum rtl_tx_desc_version txd_version
;
189 } rtl_chip_infos
[] = {
191 [RTL_GIGA_MAC_VER_01
] =
192 _R("RTL8169", RTL_TD_0
, NULL
, JUMBO_7K
, true),
193 [RTL_GIGA_MAC_VER_02
] =
194 _R("RTL8169s", RTL_TD_0
, NULL
, JUMBO_7K
, true),
195 [RTL_GIGA_MAC_VER_03
] =
196 _R("RTL8110s", RTL_TD_0
, NULL
, JUMBO_7K
, true),
197 [RTL_GIGA_MAC_VER_04
] =
198 _R("RTL8169sb/8110sb", RTL_TD_0
, NULL
, JUMBO_7K
, true),
199 [RTL_GIGA_MAC_VER_05
] =
200 _R("RTL8169sc/8110sc", RTL_TD_0
, NULL
, JUMBO_7K
, true),
201 [RTL_GIGA_MAC_VER_06
] =
202 _R("RTL8169sc/8110sc", RTL_TD_0
, NULL
, JUMBO_7K
, true),
204 [RTL_GIGA_MAC_VER_07
] =
205 _R("RTL8102e", RTL_TD_1
, NULL
, JUMBO_1K
, true),
206 [RTL_GIGA_MAC_VER_08
] =
207 _R("RTL8102e", RTL_TD_1
, NULL
, JUMBO_1K
, true),
208 [RTL_GIGA_MAC_VER_09
] =
209 _R("RTL8102e", RTL_TD_1
, NULL
, JUMBO_1K
, true),
210 [RTL_GIGA_MAC_VER_10
] =
211 _R("RTL8101e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
212 [RTL_GIGA_MAC_VER_11
] =
213 _R("RTL8168b/8111b", RTL_TD_0
, NULL
, JUMBO_4K
, false),
214 [RTL_GIGA_MAC_VER_12
] =
215 _R("RTL8168b/8111b", RTL_TD_0
, NULL
, JUMBO_4K
, false),
216 [RTL_GIGA_MAC_VER_13
] =
217 _R("RTL8101e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
218 [RTL_GIGA_MAC_VER_14
] =
219 _R("RTL8100e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
220 [RTL_GIGA_MAC_VER_15
] =
221 _R("RTL8100e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
222 [RTL_GIGA_MAC_VER_16
] =
223 _R("RTL8101e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
224 [RTL_GIGA_MAC_VER_17
] =
225 _R("RTL8168b/8111b", RTL_TD_0
, NULL
, JUMBO_4K
, false),
226 [RTL_GIGA_MAC_VER_18
] =
227 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
, JUMBO_6K
, false),
228 [RTL_GIGA_MAC_VER_19
] =
229 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
230 [RTL_GIGA_MAC_VER_20
] =
231 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
232 [RTL_GIGA_MAC_VER_21
] =
233 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
234 [RTL_GIGA_MAC_VER_22
] =
235 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
236 [RTL_GIGA_MAC_VER_23
] =
237 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
, JUMBO_6K
, false),
238 [RTL_GIGA_MAC_VER_24
] =
239 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
, JUMBO_6K
, false),
240 [RTL_GIGA_MAC_VER_25
] =
241 _R("RTL8168d/8111d", RTL_TD_1
, FIRMWARE_8168D_1
,
243 [RTL_GIGA_MAC_VER_26
] =
244 _R("RTL8168d/8111d", RTL_TD_1
, FIRMWARE_8168D_2
,
246 [RTL_GIGA_MAC_VER_27
] =
247 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
, JUMBO_9K
, false),
248 [RTL_GIGA_MAC_VER_28
] =
249 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
, JUMBO_9K
, false),
250 [RTL_GIGA_MAC_VER_29
] =
251 _R("RTL8105e", RTL_TD_1
, FIRMWARE_8105E_1
,
253 [RTL_GIGA_MAC_VER_30
] =
254 _R("RTL8105e", RTL_TD_1
, FIRMWARE_8105E_1
,
256 [RTL_GIGA_MAC_VER_31
] =
257 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
, JUMBO_9K
, false),
258 [RTL_GIGA_MAC_VER_32
] =
259 _R("RTL8168e/8111e", RTL_TD_1
, FIRMWARE_8168E_1
,
261 [RTL_GIGA_MAC_VER_33
] =
262 _R("RTL8168e/8111e", RTL_TD_1
, FIRMWARE_8168E_2
,
264 [RTL_GIGA_MAC_VER_34
] =
265 _R("RTL8168evl/8111evl",RTL_TD_1
, FIRMWARE_8168E_3
,
267 [RTL_GIGA_MAC_VER_35
] =
268 _R("RTL8168f/8111f", RTL_TD_1
, FIRMWARE_8168F_1
,
270 [RTL_GIGA_MAC_VER_36
] =
271 _R("RTL8168f/8111f", RTL_TD_1
, FIRMWARE_8168F_2
,
273 [RTL_GIGA_MAC_VER_37
] =
274 _R("RTL8402", RTL_TD_1
, FIRMWARE_8402_1
,
276 [RTL_GIGA_MAC_VER_38
] =
277 _R("RTL8411", RTL_TD_1
, FIRMWARE_8411_1
,
279 [RTL_GIGA_MAC_VER_39
] =
280 _R("RTL8106e", RTL_TD_1
, FIRMWARE_8106E_1
,
282 [RTL_GIGA_MAC_VER_40
] =
283 _R("RTL8168g/8111g", RTL_TD_1
, FIRMWARE_8168G_2
,
285 [RTL_GIGA_MAC_VER_41
] =
286 _R("RTL8168g/8111g", RTL_TD_1
, NULL
, JUMBO_9K
, false),
287 [RTL_GIGA_MAC_VER_42
] =
288 _R("RTL8168g/8111g", RTL_TD_1
, FIRMWARE_8168G_3
,
290 [RTL_GIGA_MAC_VER_43
] =
291 _R("RTL8106e", RTL_TD_1
, FIRMWARE_8106E_2
,
293 [RTL_GIGA_MAC_VER_44
] =
294 _R("RTL8411", RTL_TD_1
, FIRMWARE_8411_2
,
296 [RTL_GIGA_MAC_VER_45
] =
297 _R("RTL8168h/8111h", RTL_TD_1
, FIRMWARE_8168H_1
,
299 [RTL_GIGA_MAC_VER_46
] =
300 _R("RTL8168h/8111h", RTL_TD_1
, FIRMWARE_8168H_2
,
302 [RTL_GIGA_MAC_VER_47
] =
303 _R("RTL8107e", RTL_TD_1
, FIRMWARE_8107E_1
,
305 [RTL_GIGA_MAC_VER_48
] =
306 _R("RTL8107e", RTL_TD_1
, FIRMWARE_8107E_2
,
308 [RTL_GIGA_MAC_VER_49
] =
309 _R("RTL8168ep/8111ep", RTL_TD_1
, NULL
,
311 [RTL_GIGA_MAC_VER_50
] =
312 _R("RTL8168ep/8111ep", RTL_TD_1
, NULL
,
314 [RTL_GIGA_MAC_VER_51
] =
315 _R("RTL8168ep/8111ep", RTL_TD_1
, NULL
,
326 static const struct pci_device_id rtl8169_pci_tbl
[] = {
327 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
328 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
329 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8161), 0, 0, RTL_CFG_1
},
330 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
331 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
332 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
333 { PCI_VENDOR_ID_DLINK
, 0x4300,
334 PCI_VENDOR_ID_DLINK
, 0x4b10, 0, 0, RTL_CFG_1
},
335 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
336 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4302), 0, 0, RTL_CFG_0
},
337 { PCI_DEVICE(PCI_VENDOR_ID_AT
, 0xc107), 0, 0, RTL_CFG_0
},
338 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
339 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
340 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
342 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
346 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
348 static int rx_buf_sz
= 16383;
349 static int use_dac
= -1;
355 MAC0
= 0, /* Ethernet hardware address. */
357 MAR0
= 8, /* Multicast filter. */
358 CounterAddrLow
= 0x10,
359 CounterAddrHigh
= 0x14,
360 TxDescStartAddrLow
= 0x20,
361 TxDescStartAddrHigh
= 0x24,
362 TxHDescStartAddrLow
= 0x28,
363 TxHDescStartAddrHigh
= 0x2c,
372 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
373 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
376 #define RX128_INT_EN (1 << 15) /* 8111c and later */
377 #define RX_MULTI_EN (1 << 14) /* 8111c only */
378 #define RXCFG_FIFO_SHIFT 13
379 /* No threshold before first PCI xfer */
380 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
381 #define RX_EARLY_OFF (1 << 11)
382 #define RXCFG_DMA_SHIFT 8
383 /* Unlimited maximum PCI burst. */
384 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
391 #define PME_SIGNAL (1 << 5) /* 8168c and later */
402 RxDescAddrLow
= 0xe4,
403 RxDescAddrHigh
= 0xe8,
404 EarlyTxThres
= 0xec, /* 8169. Unit of 32 bytes. */
406 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
408 MaxTxPacketSize
= 0xec, /* 8101/8168. Unit of 128 bytes. */
410 #define TxPacketMax (8064 >> 7)
411 #define EarlySize 0x27
414 FuncEventMask
= 0xf4,
415 FuncPresetState
= 0xf8,
420 FuncForceEvent
= 0xfc,
423 enum rtl8110_registers
{
429 enum rtl8168_8101_registers
{
432 #define CSIAR_FLAG 0x80000000
433 #define CSIAR_WRITE_CMD 0x80000000
434 #define CSIAR_BYTE_ENABLE 0x0f
435 #define CSIAR_BYTE_ENABLE_SHIFT 12
436 #define CSIAR_ADDR_MASK 0x0fff
437 #define CSIAR_FUNC_CARD 0x00000000
438 #define CSIAR_FUNC_SDIO 0x00010000
439 #define CSIAR_FUNC_NIC 0x00020000
440 #define CSIAR_FUNC_NIC2 0x00010000
443 #define EPHYAR_FLAG 0x80000000
444 #define EPHYAR_WRITE_CMD 0x80000000
445 #define EPHYAR_REG_MASK 0x1f
446 #define EPHYAR_REG_SHIFT 16
447 #define EPHYAR_DATA_MASK 0xffff
449 #define PFM_EN (1 << 6)
450 #define TX_10M_PS_EN (1 << 7)
452 #define FIX_NAK_1 (1 << 4)
453 #define FIX_NAK_2 (1 << 3)
456 #define NOW_IS_OOB (1 << 7)
457 #define TX_EMPTY (1 << 5)
458 #define RX_EMPTY (1 << 4)
459 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
460 #define EN_NDP (1 << 3)
461 #define EN_OOB_RESET (1 << 2)
462 #define LINK_LIST_RDY (1 << 1)
464 #define EFUSEAR_FLAG 0x80000000
465 #define EFUSEAR_WRITE_CMD 0x80000000
466 #define EFUSEAR_READ_CMD 0x00000000
467 #define EFUSEAR_REG_MASK 0x03ff
468 #define EFUSEAR_REG_SHIFT 8
469 #define EFUSEAR_DATA_MASK 0xff
471 #define PFM_D3COLD_EN (1 << 6)
474 enum rtl8168_registers
{
479 #define ERIAR_FLAG 0x80000000
480 #define ERIAR_WRITE_CMD 0x80000000
481 #define ERIAR_READ_CMD 0x00000000
482 #define ERIAR_ADDR_BYTE_ALIGN 4
483 #define ERIAR_TYPE_SHIFT 16
484 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
485 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
486 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
487 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
488 #define ERIAR_MASK_SHIFT 12
489 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
490 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
491 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
492 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
493 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
494 EPHY_RXER_NUM
= 0x7c,
495 OCPDR
= 0xb0, /* OCP GPHY access */
496 #define OCPDR_WRITE_CMD 0x80000000
497 #define OCPDR_READ_CMD 0x00000000
498 #define OCPDR_REG_MASK 0x7f
499 #define OCPDR_GPHY_REG_SHIFT 16
500 #define OCPDR_DATA_MASK 0xffff
502 #define OCPAR_FLAG 0x80000000
503 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
504 #define OCPAR_GPHY_READ_CMD 0x0000f060
506 RDSAR1
= 0xd0, /* 8168c only. Undocumented on 8168dp */
507 MISC
= 0xf0, /* 8168e only. */
508 #define TXPLA_RST (1 << 29)
509 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
510 #define PWM_EN (1 << 22)
511 #define RXDV_GATED_EN (1 << 19)
512 #define EARLY_TALLY_EN (1 << 16)
515 enum rtl_register_content
{
516 /* InterruptStatusBits */
520 TxDescUnavail
= 0x0080,
544 /* TXPoll register p.5 */
545 HPQ
= 0x80, /* Poll cmd on the high prio queue */
546 NPQ
= 0x40, /* Poll cmd on the low prio queue */
547 FSWInt
= 0x01, /* Forced software interrupt */
551 Cfg9346_Unlock
= 0xc0,
556 AcceptBroadcast
= 0x08,
557 AcceptMulticast
= 0x04,
559 AcceptAllPhys
= 0x01,
560 #define RX_CONFIG_ACCEPT_MASK 0x3f
563 TxInterFrameGapShift
= 24,
564 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
566 /* Config1 register p.24 */
569 Speed_down
= (1 << 4),
573 PMEnable
= (1 << 0), /* Power Management Enable */
575 /* Config2 register p. 25 */
576 ClkReqEn
= (1 << 7), /* Clock Request Enable */
577 MSIEnable
= (1 << 5), /* 8169 only. Reserved in the 8168. */
578 PCI_Clock_66MHz
= 0x01,
579 PCI_Clock_33MHz
= 0x00,
581 /* Config3 register p.25 */
582 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
583 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
584 Jumbo_En0
= (1 << 2), /* 8168 only. Reserved in the 8168b */
585 Rdy_to_L23
= (1 << 1), /* L23 Enable */
586 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
588 /* Config4 register */
589 Jumbo_En1
= (1 << 1), /* 8168 only. Reserved in the 8168b */
591 /* Config5 register p.27 */
592 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
593 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
594 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
596 LanWake
= (1 << 1), /* LanWake enable/disable */
597 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
598 ASPM_en
= (1 << 0), /* ASPM enable */
601 TBIReset
= 0x80000000,
602 TBILoopback
= 0x40000000,
603 TBINwEnable
= 0x20000000,
604 TBINwRestart
= 0x10000000,
605 TBILinkOk
= 0x02000000,
606 TBINwComplete
= 0x01000000,
609 EnableBist
= (1 << 15), // 8168 8101
610 Mac_dbgo_oe
= (1 << 14), // 8168 8101
611 Normal_mode
= (1 << 13), // unused
612 Force_half_dup
= (1 << 12), // 8168 8101
613 Force_rxflow_en
= (1 << 11), // 8168 8101
614 Force_txflow_en
= (1 << 10), // 8168 8101
615 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
616 ASF
= (1 << 8), // 8168 8101
617 PktCntrDisable
= (1 << 7), // 8168 8101
618 Mac_dbgo_sel
= 0x001c, // 8168
623 INTT_0
= 0x0000, // 8168
624 INTT_1
= 0x0001, // 8168
625 INTT_2
= 0x0002, // 8168
626 INTT_3
= 0x0003, // 8168
628 /* rtl8169_PHYstatus */
639 TBILinkOK
= 0x02000000,
641 /* ResetCounterCommand */
644 /* DumpCounterCommand */
647 /* magic enable v2 */
648 MagicPacket_v2
= (1 << 16), /* Wake up when receives a Magic Packet */
652 /* First doubleword. */
653 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
654 RingEnd
= (1 << 30), /* End of descriptor ring */
655 FirstFrag
= (1 << 29), /* First segment of a packet */
656 LastFrag
= (1 << 28), /* Final segment of a packet */
660 enum rtl_tx_desc_bit
{
661 /* First doubleword. */
662 TD_LSO
= (1 << 27), /* Large Send Offload */
663 #define TD_MSS_MAX 0x07ffu /* MSS value */
665 /* Second doubleword. */
666 TxVlanTag
= (1 << 17), /* Add VLAN tag */
669 /* 8169, 8168b and 810x except 8102e. */
670 enum rtl_tx_desc_bit_0
{
671 /* First doubleword. */
672 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
673 TD0_TCP_CS
= (1 << 16), /* Calculate TCP/IP checksum */
674 TD0_UDP_CS
= (1 << 17), /* Calculate UDP/IP checksum */
675 TD0_IP_CS
= (1 << 18), /* Calculate IP checksum */
678 /* 8102e, 8168c and beyond. */
679 enum rtl_tx_desc_bit_1
{
680 /* First doubleword. */
681 TD1_GTSENV4
= (1 << 26), /* Giant Send for IPv4 */
682 TD1_GTSENV6
= (1 << 25), /* Giant Send for IPv6 */
683 #define GTTCPHO_SHIFT 18
684 #define GTTCPHO_MAX 0x7fU
686 /* Second doubleword. */
687 #define TCPHO_SHIFT 18
688 #define TCPHO_MAX 0x3ffU
689 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
690 TD1_IPv6_CS
= (1 << 28), /* Calculate IPv6 checksum */
691 TD1_IPv4_CS
= (1 << 29), /* Calculate IPv4 checksum */
692 TD1_TCP_CS
= (1 << 30), /* Calculate TCP/IP checksum */
693 TD1_UDP_CS
= (1 << 31), /* Calculate UDP/IP checksum */
696 enum rtl_rx_desc_bit
{
698 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
699 PID0
= (1 << 17), /* Protocol ID bit 0/2 */
701 #define RxProtoUDP (PID1)
702 #define RxProtoTCP (PID0)
703 #define RxProtoIP (PID1 | PID0)
704 #define RxProtoMask RxProtoIP
706 IPFail
= (1 << 16), /* IP checksum failed */
707 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
708 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
709 RxVlanTag
= (1 << 16), /* VLAN tag available */
712 #define RsvdMask 0x3fffc000
729 u8 __pad
[sizeof(void *) - sizeof(u32
)];
733 RTL_FEATURE_WOL
= (1 << 0),
734 RTL_FEATURE_MSI
= (1 << 1),
735 RTL_FEATURE_GMII
= (1 << 2),
738 struct rtl8169_counters
{
745 __le32 tx_one_collision
;
746 __le32 tx_multi_collision
;
754 struct rtl8169_tc_offsets
{
757 __le32 tx_multi_collision
;
762 RTL_FLAG_TASK_ENABLED
,
763 RTL_FLAG_TASK_SLOW_PENDING
,
764 RTL_FLAG_TASK_RESET_PENDING
,
765 RTL_FLAG_TASK_PHY_PENDING
,
769 struct rtl8169_stats
{
772 struct u64_stats_sync syncp
;
775 struct rtl8169_private
{
776 void __iomem
*mmio_addr
; /* memory map physical address */
777 struct pci_dev
*pci_dev
;
778 struct net_device
*dev
;
779 struct napi_struct napi
;
783 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
784 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
786 struct rtl8169_stats rx_stats
;
787 struct rtl8169_stats tx_stats
;
788 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
789 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
790 dma_addr_t TxPhyAddr
;
791 dma_addr_t RxPhyAddr
;
792 void *Rx_databuff
[NUM_RX_DESC
]; /* Rx data buffers */
793 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
794 struct timer_list timer
;
800 void (*write
)(struct rtl8169_private
*, int, int);
801 int (*read
)(struct rtl8169_private
*, int);
804 struct pll_power_ops
{
805 void (*down
)(struct rtl8169_private
*);
806 void (*up
)(struct rtl8169_private
*);
810 void (*enable
)(struct rtl8169_private
*);
811 void (*disable
)(struct rtl8169_private
*);
815 void (*write
)(struct rtl8169_private
*, int, int);
816 u32 (*read
)(struct rtl8169_private
*, int);
819 int (*set_speed
)(struct net_device
*, u8 aneg
, u16 sp
, u8 dpx
, u32 adv
);
820 int (*get_link_ksettings
)(struct net_device
*,
821 struct ethtool_link_ksettings
*);
822 void (*phy_reset_enable
)(struct rtl8169_private
*tp
);
823 void (*hw_start
)(struct net_device
*);
824 unsigned int (*phy_reset_pending
)(struct rtl8169_private
*tp
);
825 unsigned int (*link_ok
)(void __iomem
*);
826 int (*do_ioctl
)(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
);
827 bool (*tso_csum
)(struct rtl8169_private
*, struct sk_buff
*, u32
*);
830 DECLARE_BITMAP(flags
, RTL_FLAG_MAX
);
832 struct work_struct work
;
837 struct mii_if_info mii
;
838 dma_addr_t counters_phys_addr
;
839 struct rtl8169_counters
*counters
;
840 struct rtl8169_tc_offsets tc_offset
;
845 const struct firmware
*fw
;
847 #define RTL_VER_SIZE 32
849 char version
[RTL_VER_SIZE
];
851 struct rtl_fw_phy_action
{
856 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
861 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
862 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
863 module_param(use_dac
, int, 0);
864 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
865 module_param_named(debug
, debug
.msg_enable
, int, 0);
866 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
867 MODULE_LICENSE("GPL");
868 MODULE_VERSION(RTL8169_VERSION
);
869 MODULE_FIRMWARE(FIRMWARE_8168D_1
);
870 MODULE_FIRMWARE(FIRMWARE_8168D_2
);
871 MODULE_FIRMWARE(FIRMWARE_8168E_1
);
872 MODULE_FIRMWARE(FIRMWARE_8168E_2
);
873 MODULE_FIRMWARE(FIRMWARE_8168E_3
);
874 MODULE_FIRMWARE(FIRMWARE_8105E_1
);
875 MODULE_FIRMWARE(FIRMWARE_8168F_1
);
876 MODULE_FIRMWARE(FIRMWARE_8168F_2
);
877 MODULE_FIRMWARE(FIRMWARE_8402_1
);
878 MODULE_FIRMWARE(FIRMWARE_8411_1
);
879 MODULE_FIRMWARE(FIRMWARE_8411_2
);
880 MODULE_FIRMWARE(FIRMWARE_8106E_1
);
881 MODULE_FIRMWARE(FIRMWARE_8106E_2
);
882 MODULE_FIRMWARE(FIRMWARE_8168G_2
);
883 MODULE_FIRMWARE(FIRMWARE_8168G_3
);
884 MODULE_FIRMWARE(FIRMWARE_8168H_1
);
885 MODULE_FIRMWARE(FIRMWARE_8168H_2
);
886 MODULE_FIRMWARE(FIRMWARE_8107E_1
);
887 MODULE_FIRMWARE(FIRMWARE_8107E_2
);
889 static void rtl_lock_work(struct rtl8169_private
*tp
)
891 mutex_lock(&tp
->wk
.mutex
);
894 static void rtl_unlock_work(struct rtl8169_private
*tp
)
896 mutex_unlock(&tp
->wk
.mutex
);
899 static void rtl_tx_performance_tweak(struct pci_dev
*pdev
, u16 force
)
901 pcie_capability_clear_and_set_word(pdev
, PCI_EXP_DEVCTL
,
902 PCI_EXP_DEVCTL_READRQ
, force
);
906 bool (*check
)(struct rtl8169_private
*);
910 static void rtl_udelay(unsigned int d
)
915 static bool rtl_loop_wait(struct rtl8169_private
*tp
, const struct rtl_cond
*c
,
916 void (*delay
)(unsigned int), unsigned int d
, int n
,
921 for (i
= 0; i
< n
; i
++) {
923 if (c
->check(tp
) == high
)
926 netif_err(tp
, drv
, tp
->dev
, "%s == %d (loop: %d, delay: %d).\n",
927 c
->msg
, !high
, n
, d
);
931 static bool rtl_udelay_loop_wait_high(struct rtl8169_private
*tp
,
932 const struct rtl_cond
*c
,
933 unsigned int d
, int n
)
935 return rtl_loop_wait(tp
, c
, rtl_udelay
, d
, n
, true);
938 static bool rtl_udelay_loop_wait_low(struct rtl8169_private
*tp
,
939 const struct rtl_cond
*c
,
940 unsigned int d
, int n
)
942 return rtl_loop_wait(tp
, c
, rtl_udelay
, d
, n
, false);
945 static bool rtl_msleep_loop_wait_high(struct rtl8169_private
*tp
,
946 const struct rtl_cond
*c
,
947 unsigned int d
, int n
)
949 return rtl_loop_wait(tp
, c
, msleep
, d
, n
, true);
952 static bool rtl_msleep_loop_wait_low(struct rtl8169_private
*tp
,
953 const struct rtl_cond
*c
,
954 unsigned int d
, int n
)
956 return rtl_loop_wait(tp
, c
, msleep
, d
, n
, false);
959 #define DECLARE_RTL_COND(name) \
960 static bool name ## _check(struct rtl8169_private *); \
962 static const struct rtl_cond name = { \
963 .check = name ## _check, \
967 static bool name ## _check(struct rtl8169_private *tp)
969 static bool rtl_ocp_reg_failure(struct rtl8169_private
*tp
, u32 reg
)
971 if (reg
& 0xffff0001) {
972 netif_err(tp
, drv
, tp
->dev
, "Invalid ocp reg %x!\n", reg
);
978 DECLARE_RTL_COND(rtl_ocp_gphy_cond
)
980 void __iomem
*ioaddr
= tp
->mmio_addr
;
982 return RTL_R32(GPHY_OCP
) & OCPAR_FLAG
;
985 static void r8168_phy_ocp_write(struct rtl8169_private
*tp
, u32 reg
, u32 data
)
987 void __iomem
*ioaddr
= tp
->mmio_addr
;
989 if (rtl_ocp_reg_failure(tp
, reg
))
992 RTL_W32(GPHY_OCP
, OCPAR_FLAG
| (reg
<< 15) | data
);
994 rtl_udelay_loop_wait_low(tp
, &rtl_ocp_gphy_cond
, 25, 10);
997 static u16
r8168_phy_ocp_read(struct rtl8169_private
*tp
, u32 reg
)
999 void __iomem
*ioaddr
= tp
->mmio_addr
;
1001 if (rtl_ocp_reg_failure(tp
, reg
))
1004 RTL_W32(GPHY_OCP
, reg
<< 15);
1006 return rtl_udelay_loop_wait_high(tp
, &rtl_ocp_gphy_cond
, 25, 10) ?
1007 (RTL_R32(GPHY_OCP
) & 0xffff) : ~0;
1010 static void r8168_mac_ocp_write(struct rtl8169_private
*tp
, u32 reg
, u32 data
)
1012 void __iomem
*ioaddr
= tp
->mmio_addr
;
1014 if (rtl_ocp_reg_failure(tp
, reg
))
1017 RTL_W32(OCPDR
, OCPAR_FLAG
| (reg
<< 15) | data
);
1020 static u16
r8168_mac_ocp_read(struct rtl8169_private
*tp
, u32 reg
)
1022 void __iomem
*ioaddr
= tp
->mmio_addr
;
1024 if (rtl_ocp_reg_failure(tp
, reg
))
1027 RTL_W32(OCPDR
, reg
<< 15);
1029 return RTL_R32(OCPDR
);
1032 #define OCP_STD_PHY_BASE 0xa400
1034 static void r8168g_mdio_write(struct rtl8169_private
*tp
, int reg
, int value
)
1037 tp
->ocp_base
= value
? value
<< 4 : OCP_STD_PHY_BASE
;
1041 if (tp
->ocp_base
!= OCP_STD_PHY_BASE
)
1044 r8168_phy_ocp_write(tp
, tp
->ocp_base
+ reg
* 2, value
);
1047 static int r8168g_mdio_read(struct rtl8169_private
*tp
, int reg
)
1049 if (tp
->ocp_base
!= OCP_STD_PHY_BASE
)
1052 return r8168_phy_ocp_read(tp
, tp
->ocp_base
+ reg
* 2);
1055 static void mac_mcu_write(struct rtl8169_private
*tp
, int reg
, int value
)
1058 tp
->ocp_base
= value
<< 4;
1062 r8168_mac_ocp_write(tp
, tp
->ocp_base
+ reg
, value
);
1065 static int mac_mcu_read(struct rtl8169_private
*tp
, int reg
)
1067 return r8168_mac_ocp_read(tp
, tp
->ocp_base
+ reg
);
1070 DECLARE_RTL_COND(rtl_phyar_cond
)
1072 void __iomem
*ioaddr
= tp
->mmio_addr
;
1074 return RTL_R32(PHYAR
) & 0x80000000;
1077 static void r8169_mdio_write(struct rtl8169_private
*tp
, int reg
, int value
)
1079 void __iomem
*ioaddr
= tp
->mmio_addr
;
1081 RTL_W32(PHYAR
, 0x80000000 | (reg
& 0x1f) << 16 | (value
& 0xffff));
1083 rtl_udelay_loop_wait_low(tp
, &rtl_phyar_cond
, 25, 20);
1085 * According to hardware specs a 20us delay is required after write
1086 * complete indication, but before sending next command.
1091 static int r8169_mdio_read(struct rtl8169_private
*tp
, int reg
)
1093 void __iomem
*ioaddr
= tp
->mmio_addr
;
1096 RTL_W32(PHYAR
, 0x0 | (reg
& 0x1f) << 16);
1098 value
= rtl_udelay_loop_wait_high(tp
, &rtl_phyar_cond
, 25, 20) ?
1099 RTL_R32(PHYAR
) & 0xffff : ~0;
1102 * According to hardware specs a 20us delay is required after read
1103 * complete indication, but before sending next command.
1110 DECLARE_RTL_COND(rtl_ocpar_cond
)
1112 void __iomem
*ioaddr
= tp
->mmio_addr
;
1114 return RTL_R32(OCPAR
) & OCPAR_FLAG
;
1117 static void r8168dp_1_mdio_access(struct rtl8169_private
*tp
, int reg
, u32 data
)
1119 void __iomem
*ioaddr
= tp
->mmio_addr
;
1121 RTL_W32(OCPDR
, data
| ((reg
& OCPDR_REG_MASK
) << OCPDR_GPHY_REG_SHIFT
));
1122 RTL_W32(OCPAR
, OCPAR_GPHY_WRITE_CMD
);
1123 RTL_W32(EPHY_RXER_NUM
, 0);
1125 rtl_udelay_loop_wait_low(tp
, &rtl_ocpar_cond
, 1000, 100);
1128 static void r8168dp_1_mdio_write(struct rtl8169_private
*tp
, int reg
, int value
)
1130 r8168dp_1_mdio_access(tp
, reg
,
1131 OCPDR_WRITE_CMD
| (value
& OCPDR_DATA_MASK
));
1134 static int r8168dp_1_mdio_read(struct rtl8169_private
*tp
, int reg
)
1136 void __iomem
*ioaddr
= tp
->mmio_addr
;
1138 r8168dp_1_mdio_access(tp
, reg
, OCPDR_READ_CMD
);
1141 RTL_W32(OCPAR
, OCPAR_GPHY_READ_CMD
);
1142 RTL_W32(EPHY_RXER_NUM
, 0);
1144 return rtl_udelay_loop_wait_high(tp
, &rtl_ocpar_cond
, 1000, 100) ?
1145 RTL_R32(OCPDR
) & OCPDR_DATA_MASK
: ~0;
1148 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1150 static void r8168dp_2_mdio_start(void __iomem
*ioaddr
)
1152 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT
);
1155 static void r8168dp_2_mdio_stop(void __iomem
*ioaddr
)
1157 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT
);
1160 static void r8168dp_2_mdio_write(struct rtl8169_private
*tp
, int reg
, int value
)
1162 void __iomem
*ioaddr
= tp
->mmio_addr
;
1164 r8168dp_2_mdio_start(ioaddr
);
1166 r8169_mdio_write(tp
, reg
, value
);
1168 r8168dp_2_mdio_stop(ioaddr
);
1171 static int r8168dp_2_mdio_read(struct rtl8169_private
*tp
, int reg
)
1173 void __iomem
*ioaddr
= tp
->mmio_addr
;
1176 r8168dp_2_mdio_start(ioaddr
);
1178 value
= r8169_mdio_read(tp
, reg
);
1180 r8168dp_2_mdio_stop(ioaddr
);
1185 static void rtl_writephy(struct rtl8169_private
*tp
, int location
, u32 val
)
1187 tp
->mdio_ops
.write(tp
, location
, val
);
1190 static int rtl_readphy(struct rtl8169_private
*tp
, int location
)
1192 return tp
->mdio_ops
.read(tp
, location
);
1195 static void rtl_patchphy(struct rtl8169_private
*tp
, int reg_addr
, int value
)
1197 rtl_writephy(tp
, reg_addr
, rtl_readphy(tp
, reg_addr
) | value
);
1200 static void rtl_w0w1_phy(struct rtl8169_private
*tp
, int reg_addr
, int p
, int m
)
1204 val
= rtl_readphy(tp
, reg_addr
);
1205 rtl_writephy(tp
, reg_addr
, (val
& ~m
) | p
);
1208 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
1211 struct rtl8169_private
*tp
= netdev_priv(dev
);
1213 rtl_writephy(tp
, location
, val
);
1216 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
1218 struct rtl8169_private
*tp
= netdev_priv(dev
);
1220 return rtl_readphy(tp
, location
);
1223 DECLARE_RTL_COND(rtl_ephyar_cond
)
1225 void __iomem
*ioaddr
= tp
->mmio_addr
;
1227 return RTL_R32(EPHYAR
) & EPHYAR_FLAG
;
1230 static void rtl_ephy_write(struct rtl8169_private
*tp
, int reg_addr
, int value
)
1232 void __iomem
*ioaddr
= tp
->mmio_addr
;
1234 RTL_W32(EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
1235 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
1237 rtl_udelay_loop_wait_low(tp
, &rtl_ephyar_cond
, 10, 100);
1242 static u16
rtl_ephy_read(struct rtl8169_private
*tp
, int reg_addr
)
1244 void __iomem
*ioaddr
= tp
->mmio_addr
;
1246 RTL_W32(EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
1248 return rtl_udelay_loop_wait_high(tp
, &rtl_ephyar_cond
, 10, 100) ?
1249 RTL_R32(EPHYAR
) & EPHYAR_DATA_MASK
: ~0;
1252 DECLARE_RTL_COND(rtl_eriar_cond
)
1254 void __iomem
*ioaddr
= tp
->mmio_addr
;
1256 return RTL_R32(ERIAR
) & ERIAR_FLAG
;
1259 static void rtl_eri_write(struct rtl8169_private
*tp
, int addr
, u32 mask
,
1262 void __iomem
*ioaddr
= tp
->mmio_addr
;
1264 BUG_ON((addr
& 3) || (mask
== 0));
1265 RTL_W32(ERIDR
, val
);
1266 RTL_W32(ERIAR
, ERIAR_WRITE_CMD
| type
| mask
| addr
);
1268 rtl_udelay_loop_wait_low(tp
, &rtl_eriar_cond
, 100, 100);
1271 static u32
rtl_eri_read(struct rtl8169_private
*tp
, int addr
, int type
)
1273 void __iomem
*ioaddr
= tp
->mmio_addr
;
1275 RTL_W32(ERIAR
, ERIAR_READ_CMD
| type
| ERIAR_MASK_1111
| addr
);
1277 return rtl_udelay_loop_wait_high(tp
, &rtl_eriar_cond
, 100, 100) ?
1278 RTL_R32(ERIDR
) : ~0;
1281 static void rtl_w0w1_eri(struct rtl8169_private
*tp
, int addr
, u32 mask
, u32 p
,
1286 val
= rtl_eri_read(tp
, addr
, type
);
1287 rtl_eri_write(tp
, addr
, mask
, (val
& ~m
) | p
, type
);
1290 static u32
r8168dp_ocp_read(struct rtl8169_private
*tp
, u8 mask
, u16 reg
)
1292 void __iomem
*ioaddr
= tp
->mmio_addr
;
1294 RTL_W32(OCPAR
, ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
1295 return rtl_udelay_loop_wait_high(tp
, &rtl_ocpar_cond
, 100, 20) ?
1296 RTL_R32(OCPDR
) : ~0;
1299 static u32
r8168ep_ocp_read(struct rtl8169_private
*tp
, u8 mask
, u16 reg
)
1301 return rtl_eri_read(tp
, reg
, ERIAR_OOB
);
1304 static u32
ocp_read(struct rtl8169_private
*tp
, u8 mask
, u16 reg
)
1306 switch (tp
->mac_version
) {
1307 case RTL_GIGA_MAC_VER_27
:
1308 case RTL_GIGA_MAC_VER_28
:
1309 case RTL_GIGA_MAC_VER_31
:
1310 return r8168dp_ocp_read(tp
, mask
, reg
);
1311 case RTL_GIGA_MAC_VER_49
:
1312 case RTL_GIGA_MAC_VER_50
:
1313 case RTL_GIGA_MAC_VER_51
:
1314 return r8168ep_ocp_read(tp
, mask
, reg
);
1321 static void r8168dp_ocp_write(struct rtl8169_private
*tp
, u8 mask
, u16 reg
,
1324 void __iomem
*ioaddr
= tp
->mmio_addr
;
1326 RTL_W32(OCPDR
, data
);
1327 RTL_W32(OCPAR
, OCPAR_FLAG
| ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
1328 rtl_udelay_loop_wait_low(tp
, &rtl_ocpar_cond
, 100, 20);
1331 static void r8168ep_ocp_write(struct rtl8169_private
*tp
, u8 mask
, u16 reg
,
1334 rtl_eri_write(tp
, reg
, ((u32
)mask
& 0x0f) << ERIAR_MASK_SHIFT
,
1338 static void ocp_write(struct rtl8169_private
*tp
, u8 mask
, u16 reg
, u32 data
)
1340 switch (tp
->mac_version
) {
1341 case RTL_GIGA_MAC_VER_27
:
1342 case RTL_GIGA_MAC_VER_28
:
1343 case RTL_GIGA_MAC_VER_31
:
1344 r8168dp_ocp_write(tp
, mask
, reg
, data
);
1346 case RTL_GIGA_MAC_VER_49
:
1347 case RTL_GIGA_MAC_VER_50
:
1348 case RTL_GIGA_MAC_VER_51
:
1349 r8168ep_ocp_write(tp
, mask
, reg
, data
);
1357 static void rtl8168_oob_notify(struct rtl8169_private
*tp
, u8 cmd
)
1359 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_0001
, cmd
, ERIAR_EXGMAC
);
1361 ocp_write(tp
, 0x1, 0x30, 0x00000001);
1364 #define OOB_CMD_RESET 0x00
1365 #define OOB_CMD_DRIVER_START 0x05
1366 #define OOB_CMD_DRIVER_STOP 0x06
1368 static u16
rtl8168_get_ocp_reg(struct rtl8169_private
*tp
)
1370 return (tp
->mac_version
== RTL_GIGA_MAC_VER_31
) ? 0xb8 : 0x10;
1373 DECLARE_RTL_COND(rtl_ocp_read_cond
)
1377 reg
= rtl8168_get_ocp_reg(tp
);
1379 return ocp_read(tp
, 0x0f, reg
) & 0x00000800;
1382 DECLARE_RTL_COND(rtl_ep_ocp_read_cond
)
1384 return ocp_read(tp
, 0x0f, 0x124) & 0x00000001;
1387 DECLARE_RTL_COND(rtl_ocp_tx_cond
)
1389 void __iomem
*ioaddr
= tp
->mmio_addr
;
1391 return RTL_R8(IBISR0
) & 0x02;
1394 static void rtl8168ep_stop_cmac(struct rtl8169_private
*tp
)
1396 void __iomem
*ioaddr
= tp
->mmio_addr
;
1398 RTL_W8(IBCR2
, RTL_R8(IBCR2
) & ~0x01);
1399 rtl_msleep_loop_wait_low(tp
, &rtl_ocp_tx_cond
, 50, 2000);
1400 RTL_W8(IBISR0
, RTL_R8(IBISR0
) | 0x20);
1401 RTL_W8(IBCR0
, RTL_R8(IBCR0
) & ~0x01);
1404 static void rtl8168dp_driver_start(struct rtl8169_private
*tp
)
1406 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_START
);
1407 rtl_msleep_loop_wait_high(tp
, &rtl_ocp_read_cond
, 10, 10);
1410 static void rtl8168ep_driver_start(struct rtl8169_private
*tp
)
1412 ocp_write(tp
, 0x01, 0x180, OOB_CMD_DRIVER_START
);
1413 ocp_write(tp
, 0x01, 0x30, ocp_read(tp
, 0x01, 0x30) | 0x01);
1414 rtl_msleep_loop_wait_high(tp
, &rtl_ep_ocp_read_cond
, 10, 10);
1417 static void rtl8168_driver_start(struct rtl8169_private
*tp
)
1419 switch (tp
->mac_version
) {
1420 case RTL_GIGA_MAC_VER_27
:
1421 case RTL_GIGA_MAC_VER_28
:
1422 case RTL_GIGA_MAC_VER_31
:
1423 rtl8168dp_driver_start(tp
);
1425 case RTL_GIGA_MAC_VER_49
:
1426 case RTL_GIGA_MAC_VER_50
:
1427 case RTL_GIGA_MAC_VER_51
:
1428 rtl8168ep_driver_start(tp
);
1436 static void rtl8168dp_driver_stop(struct rtl8169_private
*tp
)
1438 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_STOP
);
1439 rtl_msleep_loop_wait_low(tp
, &rtl_ocp_read_cond
, 10, 10);
1442 static void rtl8168ep_driver_stop(struct rtl8169_private
*tp
)
1444 rtl8168ep_stop_cmac(tp
);
1445 ocp_write(tp
, 0x01, 0x180, OOB_CMD_DRIVER_STOP
);
1446 ocp_write(tp
, 0x01, 0x30, ocp_read(tp
, 0x01, 0x30) | 0x01);
1447 rtl_msleep_loop_wait_low(tp
, &rtl_ep_ocp_read_cond
, 10, 10);
1450 static void rtl8168_driver_stop(struct rtl8169_private
*tp
)
1452 switch (tp
->mac_version
) {
1453 case RTL_GIGA_MAC_VER_27
:
1454 case RTL_GIGA_MAC_VER_28
:
1455 case RTL_GIGA_MAC_VER_31
:
1456 rtl8168dp_driver_stop(tp
);
1458 case RTL_GIGA_MAC_VER_49
:
1459 case RTL_GIGA_MAC_VER_50
:
1460 case RTL_GIGA_MAC_VER_51
:
1461 rtl8168ep_driver_stop(tp
);
1469 static int r8168dp_check_dash(struct rtl8169_private
*tp
)
1471 u16 reg
= rtl8168_get_ocp_reg(tp
);
1473 return (ocp_read(tp
, 0x0f, reg
) & 0x00008000) ? 1 : 0;
1476 static int r8168ep_check_dash(struct rtl8169_private
*tp
)
1478 return (ocp_read(tp
, 0x0f, 0x128) & 0x00000001) ? 1 : 0;
1481 static int r8168_check_dash(struct rtl8169_private
*tp
)
1483 switch (tp
->mac_version
) {
1484 case RTL_GIGA_MAC_VER_27
:
1485 case RTL_GIGA_MAC_VER_28
:
1486 case RTL_GIGA_MAC_VER_31
:
1487 return r8168dp_check_dash(tp
);
1488 case RTL_GIGA_MAC_VER_49
:
1489 case RTL_GIGA_MAC_VER_50
:
1490 case RTL_GIGA_MAC_VER_51
:
1491 return r8168ep_check_dash(tp
);
1503 static void rtl_write_exgmac_batch(struct rtl8169_private
*tp
,
1504 const struct exgmac_reg
*r
, int len
)
1507 rtl_eri_write(tp
, r
->addr
, r
->mask
, r
->val
, ERIAR_EXGMAC
);
1512 DECLARE_RTL_COND(rtl_efusear_cond
)
1514 void __iomem
*ioaddr
= tp
->mmio_addr
;
1516 return RTL_R32(EFUSEAR
) & EFUSEAR_FLAG
;
1519 static u8
rtl8168d_efuse_read(struct rtl8169_private
*tp
, int reg_addr
)
1521 void __iomem
*ioaddr
= tp
->mmio_addr
;
1523 RTL_W32(EFUSEAR
, (reg_addr
& EFUSEAR_REG_MASK
) << EFUSEAR_REG_SHIFT
);
1525 return rtl_udelay_loop_wait_high(tp
, &rtl_efusear_cond
, 100, 300) ?
1526 RTL_R32(EFUSEAR
) & EFUSEAR_DATA_MASK
: ~0;
1529 static u16
rtl_get_events(struct rtl8169_private
*tp
)
1531 void __iomem
*ioaddr
= tp
->mmio_addr
;
1533 return RTL_R16(IntrStatus
);
1536 static void rtl_ack_events(struct rtl8169_private
*tp
, u16 bits
)
1538 void __iomem
*ioaddr
= tp
->mmio_addr
;
1540 RTL_W16(IntrStatus
, bits
);
1544 static void rtl_irq_disable(struct rtl8169_private
*tp
)
1546 void __iomem
*ioaddr
= tp
->mmio_addr
;
1548 RTL_W16(IntrMask
, 0);
1552 static void rtl_irq_enable(struct rtl8169_private
*tp
, u16 bits
)
1554 void __iomem
*ioaddr
= tp
->mmio_addr
;
1556 RTL_W16(IntrMask
, bits
);
1559 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1560 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1561 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1563 static void rtl_irq_enable_all(struct rtl8169_private
*tp
)
1565 rtl_irq_enable(tp
, RTL_EVENT_NAPI
| tp
->event_slow
);
1568 static void rtl8169_irq_mask_and_ack(struct rtl8169_private
*tp
)
1570 void __iomem
*ioaddr
= tp
->mmio_addr
;
1572 rtl_irq_disable(tp
);
1573 rtl_ack_events(tp
, RTL_EVENT_NAPI
| tp
->event_slow
);
1577 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private
*tp
)
1579 void __iomem
*ioaddr
= tp
->mmio_addr
;
1581 return RTL_R32(TBICSR
) & TBIReset
;
1584 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private
*tp
)
1586 return rtl_readphy(tp
, MII_BMCR
) & BMCR_RESET
;
1589 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
1591 return RTL_R32(TBICSR
) & TBILinkOk
;
1594 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
1596 return RTL_R8(PHYstatus
) & LinkStatus
;
1599 static void rtl8169_tbi_reset_enable(struct rtl8169_private
*tp
)
1601 void __iomem
*ioaddr
= tp
->mmio_addr
;
1603 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
1606 static void rtl8169_xmii_reset_enable(struct rtl8169_private
*tp
)
1610 val
= rtl_readphy(tp
, MII_BMCR
) | BMCR_RESET
;
1611 rtl_writephy(tp
, MII_BMCR
, val
& 0xffff);
1614 static void rtl_link_chg_patch(struct rtl8169_private
*tp
)
1616 void __iomem
*ioaddr
= tp
->mmio_addr
;
1617 struct net_device
*dev
= tp
->dev
;
1619 if (!netif_running(dev
))
1622 if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
||
1623 tp
->mac_version
== RTL_GIGA_MAC_VER_38
) {
1624 if (RTL_R8(PHYstatus
) & _1000bpsF
) {
1625 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x00000011,
1627 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x00000005,
1629 } else if (RTL_R8(PHYstatus
) & _100bps
) {
1630 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x0000001f,
1632 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x00000005,
1635 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x0000001f,
1637 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x0000003f,
1640 /* Reset packet filter */
1641 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01,
1643 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00,
1645 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_35
||
1646 tp
->mac_version
== RTL_GIGA_MAC_VER_36
) {
1647 if (RTL_R8(PHYstatus
) & _1000bpsF
) {
1648 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x00000011,
1650 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x00000005,
1653 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x0000001f,
1655 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x0000003f,
1658 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_37
) {
1659 if (RTL_R8(PHYstatus
) & _10bps
) {
1660 rtl_eri_write(tp
, 0x1d0, ERIAR_MASK_0011
, 0x4d02,
1662 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_0011
, 0x0060,
1665 rtl_eri_write(tp
, 0x1d0, ERIAR_MASK_0011
, 0x0000,
1671 static void __rtl8169_check_link_status(struct net_device
*dev
,
1672 struct rtl8169_private
*tp
,
1673 void __iomem
*ioaddr
, bool pm
)
1675 if (tp
->link_ok(ioaddr
)) {
1676 rtl_link_chg_patch(tp
);
1677 /* This is to cancel a scheduled suspend if there's one. */
1679 pm_request_resume(&tp
->pci_dev
->dev
);
1680 netif_carrier_on(dev
);
1681 if (net_ratelimit())
1682 netif_info(tp
, ifup
, dev
, "link up\n");
1684 netif_carrier_off(dev
);
1685 netif_info(tp
, ifdown
, dev
, "link down\n");
1687 pm_schedule_suspend(&tp
->pci_dev
->dev
, 5000);
1691 static void rtl8169_check_link_status(struct net_device
*dev
,
1692 struct rtl8169_private
*tp
,
1693 void __iomem
*ioaddr
)
1695 __rtl8169_check_link_status(dev
, tp
, ioaddr
, false);
1698 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1700 static u32
__rtl8169_get_wol(struct rtl8169_private
*tp
)
1702 void __iomem
*ioaddr
= tp
->mmio_addr
;
1706 options
= RTL_R8(Config1
);
1707 if (!(options
& PMEnable
))
1710 options
= RTL_R8(Config3
);
1711 if (options
& LinkUp
)
1712 wolopts
|= WAKE_PHY
;
1713 switch (tp
->mac_version
) {
1714 case RTL_GIGA_MAC_VER_34
:
1715 case RTL_GIGA_MAC_VER_35
:
1716 case RTL_GIGA_MAC_VER_36
:
1717 case RTL_GIGA_MAC_VER_37
:
1718 case RTL_GIGA_MAC_VER_38
:
1719 case RTL_GIGA_MAC_VER_40
:
1720 case RTL_GIGA_MAC_VER_41
:
1721 case RTL_GIGA_MAC_VER_42
:
1722 case RTL_GIGA_MAC_VER_43
:
1723 case RTL_GIGA_MAC_VER_44
:
1724 case RTL_GIGA_MAC_VER_45
:
1725 case RTL_GIGA_MAC_VER_46
:
1726 case RTL_GIGA_MAC_VER_47
:
1727 case RTL_GIGA_MAC_VER_48
:
1728 case RTL_GIGA_MAC_VER_49
:
1729 case RTL_GIGA_MAC_VER_50
:
1730 case RTL_GIGA_MAC_VER_51
:
1731 if (rtl_eri_read(tp
, 0xdc, ERIAR_EXGMAC
) & MagicPacket_v2
)
1732 wolopts
|= WAKE_MAGIC
;
1735 if (options
& MagicPacket
)
1736 wolopts
|= WAKE_MAGIC
;
1740 options
= RTL_R8(Config5
);
1742 wolopts
|= WAKE_UCAST
;
1744 wolopts
|= WAKE_BCAST
;
1746 wolopts
|= WAKE_MCAST
;
1751 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1753 struct rtl8169_private
*tp
= netdev_priv(dev
);
1754 struct device
*d
= &tp
->pci_dev
->dev
;
1756 pm_runtime_get_noresume(d
);
1760 wol
->supported
= WAKE_ANY
;
1761 if (pm_runtime_active(d
))
1762 wol
->wolopts
= __rtl8169_get_wol(tp
);
1764 wol
->wolopts
= tp
->saved_wolopts
;
1766 rtl_unlock_work(tp
);
1768 pm_runtime_put_noidle(d
);
1771 static void __rtl8169_set_wol(struct rtl8169_private
*tp
, u32 wolopts
)
1773 void __iomem
*ioaddr
= tp
->mmio_addr
;
1774 unsigned int i
, tmp
;
1775 static const struct {
1780 { WAKE_PHY
, Config3
, LinkUp
},
1781 { WAKE_UCAST
, Config5
, UWF
},
1782 { WAKE_BCAST
, Config5
, BWF
},
1783 { WAKE_MCAST
, Config5
, MWF
},
1784 { WAKE_ANY
, Config5
, LanWake
},
1785 { WAKE_MAGIC
, Config3
, MagicPacket
}
1789 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1791 switch (tp
->mac_version
) {
1792 case RTL_GIGA_MAC_VER_34
:
1793 case RTL_GIGA_MAC_VER_35
:
1794 case RTL_GIGA_MAC_VER_36
:
1795 case RTL_GIGA_MAC_VER_37
:
1796 case RTL_GIGA_MAC_VER_38
:
1797 case RTL_GIGA_MAC_VER_40
:
1798 case RTL_GIGA_MAC_VER_41
:
1799 case RTL_GIGA_MAC_VER_42
:
1800 case RTL_GIGA_MAC_VER_43
:
1801 case RTL_GIGA_MAC_VER_44
:
1802 case RTL_GIGA_MAC_VER_45
:
1803 case RTL_GIGA_MAC_VER_46
:
1804 case RTL_GIGA_MAC_VER_47
:
1805 case RTL_GIGA_MAC_VER_48
:
1806 case RTL_GIGA_MAC_VER_49
:
1807 case RTL_GIGA_MAC_VER_50
:
1808 case RTL_GIGA_MAC_VER_51
:
1809 tmp
= ARRAY_SIZE(cfg
) - 1;
1810 if (wolopts
& WAKE_MAGIC
)
1826 tmp
= ARRAY_SIZE(cfg
);
1830 for (i
= 0; i
< tmp
; i
++) {
1831 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
1832 if (wolopts
& cfg
[i
].opt
)
1833 options
|= cfg
[i
].mask
;
1834 RTL_W8(cfg
[i
].reg
, options
);
1837 switch (tp
->mac_version
) {
1838 case RTL_GIGA_MAC_VER_01
... RTL_GIGA_MAC_VER_17
:
1839 options
= RTL_R8(Config1
) & ~PMEnable
;
1841 options
|= PMEnable
;
1842 RTL_W8(Config1
, options
);
1845 options
= RTL_R8(Config2
) & ~PME_SIGNAL
;
1847 options
|= PME_SIGNAL
;
1848 RTL_W8(Config2
, options
);
1852 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1855 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1857 struct rtl8169_private
*tp
= netdev_priv(dev
);
1858 struct device
*d
= &tp
->pci_dev
->dev
;
1860 pm_runtime_get_noresume(d
);
1865 tp
->features
|= RTL_FEATURE_WOL
;
1867 tp
->features
&= ~RTL_FEATURE_WOL
;
1868 if (pm_runtime_active(d
))
1869 __rtl8169_set_wol(tp
, wol
->wolopts
);
1871 tp
->saved_wolopts
= wol
->wolopts
;
1873 rtl_unlock_work(tp
);
1875 device_set_wakeup_enable(&tp
->pci_dev
->dev
, wol
->wolopts
);
1877 pm_runtime_put_noidle(d
);
1882 static const char *rtl_lookup_firmware_name(struct rtl8169_private
*tp
)
1884 return rtl_chip_infos
[tp
->mac_version
].fw_name
;
1887 static void rtl8169_get_drvinfo(struct net_device
*dev
,
1888 struct ethtool_drvinfo
*info
)
1890 struct rtl8169_private
*tp
= netdev_priv(dev
);
1891 struct rtl_fw
*rtl_fw
= tp
->rtl_fw
;
1893 strlcpy(info
->driver
, MODULENAME
, sizeof(info
->driver
));
1894 strlcpy(info
->version
, RTL8169_VERSION
, sizeof(info
->version
));
1895 strlcpy(info
->bus_info
, pci_name(tp
->pci_dev
), sizeof(info
->bus_info
));
1896 BUILD_BUG_ON(sizeof(info
->fw_version
) < sizeof(rtl_fw
->version
));
1897 if (!IS_ERR_OR_NULL(rtl_fw
))
1898 strlcpy(info
->fw_version
, rtl_fw
->version
,
1899 sizeof(info
->fw_version
));
1902 static int rtl8169_get_regs_len(struct net_device
*dev
)
1904 return R8169_REGS_SIZE
;
1907 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
1908 u8 autoneg
, u16 speed
, u8 duplex
, u32 ignored
)
1910 struct rtl8169_private
*tp
= netdev_priv(dev
);
1911 void __iomem
*ioaddr
= tp
->mmio_addr
;
1915 reg
= RTL_R32(TBICSR
);
1916 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
1917 (duplex
== DUPLEX_FULL
)) {
1918 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
1919 } else if (autoneg
== AUTONEG_ENABLE
)
1920 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
1922 netif_warn(tp
, link
, dev
,
1923 "incorrect speed setting refused in TBI mode\n");
1930 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
1931 u8 autoneg
, u16 speed
, u8 duplex
, u32 adv
)
1933 struct rtl8169_private
*tp
= netdev_priv(dev
);
1934 int giga_ctrl
, bmcr
;
1937 rtl_writephy(tp
, 0x1f, 0x0000);
1939 if (autoneg
== AUTONEG_ENABLE
) {
1942 auto_nego
= rtl_readphy(tp
, MII_ADVERTISE
);
1943 auto_nego
&= ~(ADVERTISE_10HALF
| ADVERTISE_10FULL
|
1944 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
1946 if (adv
& ADVERTISED_10baseT_Half
)
1947 auto_nego
|= ADVERTISE_10HALF
;
1948 if (adv
& ADVERTISED_10baseT_Full
)
1949 auto_nego
|= ADVERTISE_10FULL
;
1950 if (adv
& ADVERTISED_100baseT_Half
)
1951 auto_nego
|= ADVERTISE_100HALF
;
1952 if (adv
& ADVERTISED_100baseT_Full
)
1953 auto_nego
|= ADVERTISE_100FULL
;
1955 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
1957 giga_ctrl
= rtl_readphy(tp
, MII_CTRL1000
);
1958 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
1960 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1961 if (tp
->mii
.supports_gmii
) {
1962 if (adv
& ADVERTISED_1000baseT_Half
)
1963 giga_ctrl
|= ADVERTISE_1000HALF
;
1964 if (adv
& ADVERTISED_1000baseT_Full
)
1965 giga_ctrl
|= ADVERTISE_1000FULL
;
1966 } else if (adv
& (ADVERTISED_1000baseT_Half
|
1967 ADVERTISED_1000baseT_Full
)) {
1968 netif_info(tp
, link
, dev
,
1969 "PHY does not support 1000Mbps\n");
1973 bmcr
= BMCR_ANENABLE
| BMCR_ANRESTART
;
1975 rtl_writephy(tp
, MII_ADVERTISE
, auto_nego
);
1976 rtl_writephy(tp
, MII_CTRL1000
, giga_ctrl
);
1980 if (speed
== SPEED_10
)
1982 else if (speed
== SPEED_100
)
1983 bmcr
= BMCR_SPEED100
;
1987 if (duplex
== DUPLEX_FULL
)
1988 bmcr
|= BMCR_FULLDPLX
;
1991 rtl_writephy(tp
, MII_BMCR
, bmcr
);
1993 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
1994 tp
->mac_version
== RTL_GIGA_MAC_VER_03
) {
1995 if ((speed
== SPEED_100
) && (autoneg
!= AUTONEG_ENABLE
)) {
1996 rtl_writephy(tp
, 0x17, 0x2138);
1997 rtl_writephy(tp
, 0x0e, 0x0260);
1999 rtl_writephy(tp
, 0x17, 0x2108);
2000 rtl_writephy(tp
, 0x0e, 0x0000);
2009 static int rtl8169_set_speed(struct net_device
*dev
,
2010 u8 autoneg
, u16 speed
, u8 duplex
, u32 advertising
)
2012 struct rtl8169_private
*tp
= netdev_priv(dev
);
2015 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
, advertising
);
2019 if (netif_running(dev
) && (autoneg
== AUTONEG_ENABLE
) &&
2020 (advertising
& ADVERTISED_1000baseT_Full
) &&
2021 !pci_is_pcie(tp
->pci_dev
)) {
2022 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
2028 static int rtl8169_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
2030 struct rtl8169_private
*tp
= netdev_priv(dev
);
2033 del_timer_sync(&tp
->timer
);
2036 ret
= rtl8169_set_speed(dev
, cmd
->autoneg
, ethtool_cmd_speed(cmd
),
2037 cmd
->duplex
, cmd
->advertising
);
2038 rtl_unlock_work(tp
);
2043 static netdev_features_t
rtl8169_fix_features(struct net_device
*dev
,
2044 netdev_features_t features
)
2046 struct rtl8169_private
*tp
= netdev_priv(dev
);
2048 if (dev
->mtu
> TD_MSS_MAX
)
2049 features
&= ~NETIF_F_ALL_TSO
;
2051 if (dev
->mtu
> JUMBO_1K
&&
2052 !rtl_chip_infos
[tp
->mac_version
].jumbo_tx_csum
)
2053 features
&= ~NETIF_F_IP_CSUM
;
2058 static void __rtl8169_set_features(struct net_device
*dev
,
2059 netdev_features_t features
)
2061 struct rtl8169_private
*tp
= netdev_priv(dev
);
2062 void __iomem
*ioaddr
= tp
->mmio_addr
;
2065 rx_config
= RTL_R32(RxConfig
);
2066 if (features
& NETIF_F_RXALL
)
2067 rx_config
|= (AcceptErr
| AcceptRunt
);
2069 rx_config
&= ~(AcceptErr
| AcceptRunt
);
2071 RTL_W32(RxConfig
, rx_config
);
2073 if (features
& NETIF_F_RXCSUM
)
2074 tp
->cp_cmd
|= RxChkSum
;
2076 tp
->cp_cmd
&= ~RxChkSum
;
2078 if (features
& NETIF_F_HW_VLAN_CTAG_RX
)
2079 tp
->cp_cmd
|= RxVlan
;
2081 tp
->cp_cmd
&= ~RxVlan
;
2083 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) & ~(RxVlan
| RxChkSum
);
2085 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2089 static int rtl8169_set_features(struct net_device
*dev
,
2090 netdev_features_t features
)
2092 struct rtl8169_private
*tp
= netdev_priv(dev
);
2094 features
&= NETIF_F_RXALL
| NETIF_F_RXCSUM
| NETIF_F_HW_VLAN_CTAG_RX
;
2097 if (features
^ dev
->features
)
2098 __rtl8169_set_features(dev
, features
);
2099 rtl_unlock_work(tp
);
2105 static inline u32
rtl8169_tx_vlan_tag(struct sk_buff
*skb
)
2107 return (skb_vlan_tag_present(skb
)) ?
2108 TxVlanTag
| swab16(skb_vlan_tag_get(skb
)) : 0x00;
2111 static void rtl8169_rx_vlan_tag(struct RxDesc
*desc
, struct sk_buff
*skb
)
2113 u32 opts2
= le32_to_cpu(desc
->opts2
);
2115 if (opts2
& RxVlanTag
)
2116 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
), swab16(opts2
& 0xffff));
2119 static int rtl8169_get_link_ksettings_tbi(struct net_device
*dev
,
2120 struct ethtool_link_ksettings
*cmd
)
2122 struct rtl8169_private
*tp
= netdev_priv(dev
);
2123 void __iomem
*ioaddr
= tp
->mmio_addr
;
2125 u32 supported
, advertising
;
2128 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
2129 cmd
->base
.port
= PORT_FIBRE
;
2131 status
= RTL_R32(TBICSR
);
2132 advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
2133 cmd
->base
.autoneg
= !!(status
& TBINwEnable
);
2135 cmd
->base
.speed
= SPEED_1000
;
2136 cmd
->base
.duplex
= DUPLEX_FULL
; /* Always set */
2138 ethtool_convert_legacy_u32_to_link_mode(cmd
->link_modes
.supported
,
2140 ethtool_convert_legacy_u32_to_link_mode(cmd
->link_modes
.advertising
,
2146 static int rtl8169_get_link_ksettings_xmii(struct net_device
*dev
,
2147 struct ethtool_link_ksettings
*cmd
)
2149 struct rtl8169_private
*tp
= netdev_priv(dev
);
2151 mii_ethtool_get_link_ksettings(&tp
->mii
, cmd
);
2156 static int rtl8169_get_link_ksettings(struct net_device
*dev
,
2157 struct ethtool_link_ksettings
*cmd
)
2159 struct rtl8169_private
*tp
= netdev_priv(dev
);
2163 rc
= tp
->get_link_ksettings(dev
, cmd
);
2164 rtl_unlock_work(tp
);
2169 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
2172 struct rtl8169_private
*tp
= netdev_priv(dev
);
2173 u32 __iomem
*data
= tp
->mmio_addr
;
2178 for (i
= 0; i
< R8169_REGS_SIZE
; i
+= 4)
2179 memcpy_fromio(dw
++, data
++, 4);
2180 rtl_unlock_work(tp
);
2183 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
2185 struct rtl8169_private
*tp
= netdev_priv(dev
);
2187 return tp
->msg_enable
;
2190 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
2192 struct rtl8169_private
*tp
= netdev_priv(dev
);
2194 tp
->msg_enable
= value
;
2197 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
2204 "tx_single_collisions",
2205 "tx_multi_collisions",
2213 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
2217 return ARRAY_SIZE(rtl8169_gstrings
);
2223 DECLARE_RTL_COND(rtl_counters_cond
)
2225 void __iomem
*ioaddr
= tp
->mmio_addr
;
2227 return RTL_R32(CounterAddrLow
) & (CounterReset
| CounterDump
);
2230 static bool rtl8169_do_counters(struct net_device
*dev
, u32 counter_cmd
)
2232 struct rtl8169_private
*tp
= netdev_priv(dev
);
2233 void __iomem
*ioaddr
= tp
->mmio_addr
;
2234 dma_addr_t paddr
= tp
->counters_phys_addr
;
2238 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
2239 cmd
= (u64
)paddr
& DMA_BIT_MASK(32);
2240 RTL_W32(CounterAddrLow
, cmd
);
2241 RTL_W32(CounterAddrLow
, cmd
| counter_cmd
);
2243 ret
= rtl_udelay_loop_wait_low(tp
, &rtl_counters_cond
, 10, 1000);
2245 RTL_W32(CounterAddrLow
, 0);
2246 RTL_W32(CounterAddrHigh
, 0);
2251 static bool rtl8169_reset_counters(struct net_device
*dev
)
2253 struct rtl8169_private
*tp
= netdev_priv(dev
);
2256 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
2259 if (tp
->mac_version
< RTL_GIGA_MAC_VER_19
)
2262 return rtl8169_do_counters(dev
, CounterReset
);
2265 static bool rtl8169_update_counters(struct net_device
*dev
)
2267 struct rtl8169_private
*tp
= netdev_priv(dev
);
2268 void __iomem
*ioaddr
= tp
->mmio_addr
;
2271 * Some chips are unable to dump tally counters when the receiver
2274 if ((RTL_R8(ChipCmd
) & CmdRxEnb
) == 0)
2277 return rtl8169_do_counters(dev
, CounterDump
);
2280 static bool rtl8169_init_counter_offsets(struct net_device
*dev
)
2282 struct rtl8169_private
*tp
= netdev_priv(dev
);
2283 struct rtl8169_counters
*counters
= tp
->counters
;
2287 * rtl8169_init_counter_offsets is called from rtl_open. On chip
2288 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
2289 * reset by a power cycle, while the counter values collected by the
2290 * driver are reset at every driver unload/load cycle.
2292 * To make sure the HW values returned by @get_stats64 match the SW
2293 * values, we collect the initial values at first open(*) and use them
2294 * as offsets to normalize the values returned by @get_stats64.
2296 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
2297 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
2298 * set at open time by rtl_hw_start.
2301 if (tp
->tc_offset
.inited
)
2304 /* If both, reset and update fail, propagate to caller. */
2305 if (rtl8169_reset_counters(dev
))
2308 if (rtl8169_update_counters(dev
))
2311 tp
->tc_offset
.tx_errors
= counters
->tx_errors
;
2312 tp
->tc_offset
.tx_multi_collision
= counters
->tx_multi_collision
;
2313 tp
->tc_offset
.tx_aborted
= counters
->tx_aborted
;
2314 tp
->tc_offset
.inited
= true;
2319 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
2320 struct ethtool_stats
*stats
, u64
*data
)
2322 struct rtl8169_private
*tp
= netdev_priv(dev
);
2323 struct device
*d
= &tp
->pci_dev
->dev
;
2324 struct rtl8169_counters
*counters
= tp
->counters
;
2328 pm_runtime_get_noresume(d
);
2330 if (pm_runtime_active(d
))
2331 rtl8169_update_counters(dev
);
2333 pm_runtime_put_noidle(d
);
2335 data
[0] = le64_to_cpu(counters
->tx_packets
);
2336 data
[1] = le64_to_cpu(counters
->rx_packets
);
2337 data
[2] = le64_to_cpu(counters
->tx_errors
);
2338 data
[3] = le32_to_cpu(counters
->rx_errors
);
2339 data
[4] = le16_to_cpu(counters
->rx_missed
);
2340 data
[5] = le16_to_cpu(counters
->align_errors
);
2341 data
[6] = le32_to_cpu(counters
->tx_one_collision
);
2342 data
[7] = le32_to_cpu(counters
->tx_multi_collision
);
2343 data
[8] = le64_to_cpu(counters
->rx_unicast
);
2344 data
[9] = le64_to_cpu(counters
->rx_broadcast
);
2345 data
[10] = le32_to_cpu(counters
->rx_multicast
);
2346 data
[11] = le16_to_cpu(counters
->tx_aborted
);
2347 data
[12] = le16_to_cpu(counters
->tx_underun
);
2350 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
2354 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
2359 static int rtl8169_nway_reset(struct net_device
*dev
)
2361 struct rtl8169_private
*tp
= netdev_priv(dev
);
2363 return mii_nway_restart(&tp
->mii
);
2366 static const struct ethtool_ops rtl8169_ethtool_ops
= {
2367 .get_drvinfo
= rtl8169_get_drvinfo
,
2368 .get_regs_len
= rtl8169_get_regs_len
,
2369 .get_link
= ethtool_op_get_link
,
2370 .set_settings
= rtl8169_set_settings
,
2371 .get_msglevel
= rtl8169_get_msglevel
,
2372 .set_msglevel
= rtl8169_set_msglevel
,
2373 .get_regs
= rtl8169_get_regs
,
2374 .get_wol
= rtl8169_get_wol
,
2375 .set_wol
= rtl8169_set_wol
,
2376 .get_strings
= rtl8169_get_strings
,
2377 .get_sset_count
= rtl8169_get_sset_count
,
2378 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
2379 .get_ts_info
= ethtool_op_get_ts_info
,
2380 .nway_reset
= rtl8169_nway_reset
,
2381 .get_link_ksettings
= rtl8169_get_link_ksettings
,
2384 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
,
2385 struct net_device
*dev
, u8 default_version
)
2387 void __iomem
*ioaddr
= tp
->mmio_addr
;
2389 * The driver currently handles the 8168Bf and the 8168Be identically
2390 * but they can be identified more specifically through the test below
2393 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2395 * Same thing for the 8101Eb and the 8101Ec:
2397 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2399 static const struct rtl_mac_info
{
2404 /* 8168EP family. */
2405 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51
},
2406 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50
},
2407 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49
},
2410 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46
},
2411 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45
},
2414 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44
},
2415 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42
},
2416 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41
},
2417 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40
},
2420 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38
},
2421 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36
},
2422 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35
},
2425 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34
},
2426 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33
},
2427 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32
},
2428 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33
},
2431 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26
},
2432 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25
},
2433 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26
},
2435 /* 8168DP family. */
2436 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27
},
2437 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28
},
2438 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31
},
2441 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24
},
2442 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23
},
2443 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
2444 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24
},
2445 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
2446 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
2447 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21
},
2448 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22
},
2449 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22
},
2452 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
2453 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
2454 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
2455 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
2458 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39
},
2459 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39
},
2460 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37
},
2461 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30
},
2462 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30
},
2463 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29
},
2464 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30
},
2465 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09
},
2466 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09
},
2467 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08
},
2468 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08
},
2469 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07
},
2470 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07
},
2471 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
2472 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10
},
2473 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
2474 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09
},
2475 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09
},
2476 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
2477 /* FIXME: where did these entries come from ? -- FR */
2478 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
2479 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
2482 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
2483 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
2484 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
2485 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
2486 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
2487 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
2490 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE
}
2492 const struct rtl_mac_info
*p
= mac_info
;
2495 reg
= RTL_R32(TxConfig
);
2496 while ((reg
& p
->mask
) != p
->val
)
2498 tp
->mac_version
= p
->mac_version
;
2500 if (tp
->mac_version
== RTL_GIGA_MAC_NONE
) {
2501 netif_notice(tp
, probe
, dev
,
2502 "unknown MAC, using family default\n");
2503 tp
->mac_version
= default_version
;
2504 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_42
) {
2505 tp
->mac_version
= tp
->mii
.supports_gmii
?
2506 RTL_GIGA_MAC_VER_42
:
2507 RTL_GIGA_MAC_VER_43
;
2508 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_45
) {
2509 tp
->mac_version
= tp
->mii
.supports_gmii
?
2510 RTL_GIGA_MAC_VER_45
:
2511 RTL_GIGA_MAC_VER_47
;
2512 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_46
) {
2513 tp
->mac_version
= tp
->mii
.supports_gmii
?
2514 RTL_GIGA_MAC_VER_46
:
2515 RTL_GIGA_MAC_VER_48
;
2519 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
2521 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
2529 static void rtl_writephy_batch(struct rtl8169_private
*tp
,
2530 const struct phy_reg
*regs
, int len
)
2533 rtl_writephy(tp
, regs
->reg
, regs
->val
);
2538 #define PHY_READ 0x00000000
2539 #define PHY_DATA_OR 0x10000000
2540 #define PHY_DATA_AND 0x20000000
2541 #define PHY_BJMPN 0x30000000
2542 #define PHY_MDIO_CHG 0x40000000
2543 #define PHY_CLEAR_READCOUNT 0x70000000
2544 #define PHY_WRITE 0x80000000
2545 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2546 #define PHY_COMP_EQ_SKIPN 0xa0000000
2547 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2548 #define PHY_WRITE_PREVIOUS 0xc0000000
2549 #define PHY_SKIPN 0xd0000000
2550 #define PHY_DELAY_MS 0xe0000000
2554 char version
[RTL_VER_SIZE
];
2560 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2562 static bool rtl_fw_format_ok(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
2564 const struct firmware
*fw
= rtl_fw
->fw
;
2565 struct fw_info
*fw_info
= (struct fw_info
*)fw
->data
;
2566 struct rtl_fw_phy_action
*pa
= &rtl_fw
->phy_action
;
2567 char *version
= rtl_fw
->version
;
2570 if (fw
->size
< FW_OPCODE_SIZE
)
2573 if (!fw_info
->magic
) {
2574 size_t i
, size
, start
;
2577 if (fw
->size
< sizeof(*fw_info
))
2580 for (i
= 0; i
< fw
->size
; i
++)
2581 checksum
+= fw
->data
[i
];
2585 start
= le32_to_cpu(fw_info
->fw_start
);
2586 if (start
> fw
->size
)
2589 size
= le32_to_cpu(fw_info
->fw_len
);
2590 if (size
> (fw
->size
- start
) / FW_OPCODE_SIZE
)
2593 memcpy(version
, fw_info
->version
, RTL_VER_SIZE
);
2595 pa
->code
= (__le32
*)(fw
->data
+ start
);
2598 if (fw
->size
% FW_OPCODE_SIZE
)
2601 strlcpy(version
, rtl_lookup_firmware_name(tp
), RTL_VER_SIZE
);
2603 pa
->code
= (__le32
*)fw
->data
;
2604 pa
->size
= fw
->size
/ FW_OPCODE_SIZE
;
2606 version
[RTL_VER_SIZE
- 1] = 0;
2613 static bool rtl_fw_data_ok(struct rtl8169_private
*tp
, struct net_device
*dev
,
2614 struct rtl_fw_phy_action
*pa
)
2619 for (index
= 0; index
< pa
->size
; index
++) {
2620 u32 action
= le32_to_cpu(pa
->code
[index
]);
2621 u32 regno
= (action
& 0x0fff0000) >> 16;
2623 switch(action
& 0xf0000000) {
2628 case PHY_CLEAR_READCOUNT
:
2630 case PHY_WRITE_PREVIOUS
:
2635 if (regno
> index
) {
2636 netif_err(tp
, ifup
, tp
->dev
,
2637 "Out of range of firmware\n");
2641 case PHY_READCOUNT_EQ_SKIP
:
2642 if (index
+ 2 >= pa
->size
) {
2643 netif_err(tp
, ifup
, tp
->dev
,
2644 "Out of range of firmware\n");
2648 case PHY_COMP_EQ_SKIPN
:
2649 case PHY_COMP_NEQ_SKIPN
:
2651 if (index
+ 1 + regno
>= pa
->size
) {
2652 netif_err(tp
, ifup
, tp
->dev
,
2653 "Out of range of firmware\n");
2659 netif_err(tp
, ifup
, tp
->dev
,
2660 "Invalid action 0x%08x\n", action
);
2669 static int rtl_check_firmware(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
2671 struct net_device
*dev
= tp
->dev
;
2674 if (!rtl_fw_format_ok(tp
, rtl_fw
)) {
2675 netif_err(tp
, ifup
, dev
, "invalid firmware\n");
2679 if (rtl_fw_data_ok(tp
, dev
, &rtl_fw
->phy_action
))
2685 static void rtl_phy_write_fw(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
2687 struct rtl_fw_phy_action
*pa
= &rtl_fw
->phy_action
;
2688 struct mdio_ops org
, *ops
= &tp
->mdio_ops
;
2692 predata
= count
= 0;
2693 org
.write
= ops
->write
;
2694 org
.read
= ops
->read
;
2696 for (index
= 0; index
< pa
->size
; ) {
2697 u32 action
= le32_to_cpu(pa
->code
[index
]);
2698 u32 data
= action
& 0x0000ffff;
2699 u32 regno
= (action
& 0x0fff0000) >> 16;
2704 switch(action
& 0xf0000000) {
2706 predata
= rtl_readphy(tp
, regno
);
2723 ops
->write
= org
.write
;
2724 ops
->read
= org
.read
;
2725 } else if (data
== 1) {
2726 ops
->write
= mac_mcu_write
;
2727 ops
->read
= mac_mcu_read
;
2732 case PHY_CLEAR_READCOUNT
:
2737 rtl_writephy(tp
, regno
, data
);
2740 case PHY_READCOUNT_EQ_SKIP
:
2741 index
+= (count
== data
) ? 2 : 1;
2743 case PHY_COMP_EQ_SKIPN
:
2744 if (predata
== data
)
2748 case PHY_COMP_NEQ_SKIPN
:
2749 if (predata
!= data
)
2753 case PHY_WRITE_PREVIOUS
:
2754 rtl_writephy(tp
, regno
, predata
);
2770 ops
->write
= org
.write
;
2771 ops
->read
= org
.read
;
2774 static void rtl_release_firmware(struct rtl8169_private
*tp
)
2776 if (!IS_ERR_OR_NULL(tp
->rtl_fw
)) {
2777 release_firmware(tp
->rtl_fw
->fw
);
2780 tp
->rtl_fw
= RTL_FIRMWARE_UNKNOWN
;
2783 static void rtl_apply_firmware(struct rtl8169_private
*tp
)
2785 struct rtl_fw
*rtl_fw
= tp
->rtl_fw
;
2787 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2788 if (!IS_ERR_OR_NULL(rtl_fw
))
2789 rtl_phy_write_fw(tp
, rtl_fw
);
2792 static void rtl_apply_firmware_cond(struct rtl8169_private
*tp
, u8 reg
, u16 val
)
2794 if (rtl_readphy(tp
, reg
) != val
)
2795 netif_warn(tp
, hw
, tp
->dev
, "chipset not ready for firmware\n");
2797 rtl_apply_firmware(tp
);
2800 static void rtl8169s_hw_phy_config(struct rtl8169_private
*tp
)
2802 static const struct phy_reg phy_reg_init
[] = {
2864 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2867 static void rtl8169sb_hw_phy_config(struct rtl8169_private
*tp
)
2869 static const struct phy_reg phy_reg_init
[] = {
2875 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2878 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private
*tp
)
2880 struct pci_dev
*pdev
= tp
->pci_dev
;
2882 if ((pdev
->subsystem_vendor
!= PCI_VENDOR_ID_GIGABYTE
) ||
2883 (pdev
->subsystem_device
!= 0xe000))
2886 rtl_writephy(tp
, 0x1f, 0x0001);
2887 rtl_writephy(tp
, 0x10, 0xf01b);
2888 rtl_writephy(tp
, 0x1f, 0x0000);
2891 static void rtl8169scd_hw_phy_config(struct rtl8169_private
*tp
)
2893 static const struct phy_reg phy_reg_init
[] = {
2933 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2935 rtl8169scd_hw_phy_config_quirk(tp
);
2938 static void rtl8169sce_hw_phy_config(struct rtl8169_private
*tp
)
2940 static const struct phy_reg phy_reg_init
[] = {
2988 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2991 static void rtl8168bb_hw_phy_config(struct rtl8169_private
*tp
)
2993 static const struct phy_reg phy_reg_init
[] = {
2998 rtl_writephy(tp
, 0x1f, 0x0001);
2999 rtl_patchphy(tp
, 0x16, 1 << 0);
3001 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3004 static void rtl8168bef_hw_phy_config(struct rtl8169_private
*tp
)
3006 static const struct phy_reg phy_reg_init
[] = {
3012 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3015 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private
*tp
)
3017 static const struct phy_reg phy_reg_init
[] = {
3025 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3028 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private
*tp
)
3030 static const struct phy_reg phy_reg_init
[] = {
3036 rtl_writephy(tp
, 0x1f, 0x0000);
3037 rtl_patchphy(tp
, 0x14, 1 << 5);
3038 rtl_patchphy(tp
, 0x0d, 1 << 5);
3040 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3043 static void rtl8168c_1_hw_phy_config(struct rtl8169_private
*tp
)
3045 static const struct phy_reg phy_reg_init
[] = {
3065 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3067 rtl_patchphy(tp
, 0x14, 1 << 5);
3068 rtl_patchphy(tp
, 0x0d, 1 << 5);
3069 rtl_writephy(tp
, 0x1f, 0x0000);
3072 static void rtl8168c_2_hw_phy_config(struct rtl8169_private
*tp
)
3074 static const struct phy_reg phy_reg_init
[] = {
3092 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3094 rtl_patchphy(tp
, 0x16, 1 << 0);
3095 rtl_patchphy(tp
, 0x14, 1 << 5);
3096 rtl_patchphy(tp
, 0x0d, 1 << 5);
3097 rtl_writephy(tp
, 0x1f, 0x0000);
3100 static void rtl8168c_3_hw_phy_config(struct rtl8169_private
*tp
)
3102 static const struct phy_reg phy_reg_init
[] = {
3114 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3116 rtl_patchphy(tp
, 0x16, 1 << 0);
3117 rtl_patchphy(tp
, 0x14, 1 << 5);
3118 rtl_patchphy(tp
, 0x0d, 1 << 5);
3119 rtl_writephy(tp
, 0x1f, 0x0000);
3122 static void rtl8168c_4_hw_phy_config(struct rtl8169_private
*tp
)
3124 rtl8168c_3_hw_phy_config(tp
);
3127 static void rtl8168d_1_hw_phy_config(struct rtl8169_private
*tp
)
3129 static const struct phy_reg phy_reg_init_0
[] = {
3130 /* Channel Estimation */
3151 * Enhance line driver power
3160 * Can not link to 1Gbps with bad cable
3161 * Decrease SNR threshold form 21.07dB to 19.04dB
3170 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
3174 * Fine Tune Switching regulator parameter
3176 rtl_writephy(tp
, 0x1f, 0x0002);
3177 rtl_w0w1_phy(tp
, 0x0b, 0x0010, 0x00ef);
3178 rtl_w0w1_phy(tp
, 0x0c, 0xa200, 0x5d00);
3180 if (rtl8168d_efuse_read(tp
, 0x01) == 0xb1) {
3181 static const struct phy_reg phy_reg_init
[] = {
3191 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3193 val
= rtl_readphy(tp
, 0x0d);
3195 if ((val
& 0x00ff) != 0x006c) {
3196 static const u32 set
[] = {
3197 0x0065, 0x0066, 0x0067, 0x0068,
3198 0x0069, 0x006a, 0x006b, 0x006c
3202 rtl_writephy(tp
, 0x1f, 0x0002);
3205 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
3206 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
3209 static const struct phy_reg phy_reg_init
[] = {
3217 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3220 /* RSET couple improve */
3221 rtl_writephy(tp
, 0x1f, 0x0002);
3222 rtl_patchphy(tp
, 0x0d, 0x0300);
3223 rtl_patchphy(tp
, 0x0f, 0x0010);
3225 /* Fine tune PLL performance */
3226 rtl_writephy(tp
, 0x1f, 0x0002);
3227 rtl_w0w1_phy(tp
, 0x02, 0x0100, 0x0600);
3228 rtl_w0w1_phy(tp
, 0x03, 0x0000, 0xe000);
3230 rtl_writephy(tp
, 0x1f, 0x0005);
3231 rtl_writephy(tp
, 0x05, 0x001b);
3233 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xbf00);
3235 rtl_writephy(tp
, 0x1f, 0x0000);
3238 static void rtl8168d_2_hw_phy_config(struct rtl8169_private
*tp
)
3240 static const struct phy_reg phy_reg_init_0
[] = {
3241 /* Channel Estimation */
3262 * Enhance line driver power
3271 * Can not link to 1Gbps with bad cable
3272 * Decrease SNR threshold form 21.07dB to 19.04dB
3281 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
3283 if (rtl8168d_efuse_read(tp
, 0x01) == 0xb1) {
3284 static const struct phy_reg phy_reg_init
[] = {
3295 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3297 val
= rtl_readphy(tp
, 0x0d);
3298 if ((val
& 0x00ff) != 0x006c) {
3299 static const u32 set
[] = {
3300 0x0065, 0x0066, 0x0067, 0x0068,
3301 0x0069, 0x006a, 0x006b, 0x006c
3305 rtl_writephy(tp
, 0x1f, 0x0002);
3308 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
3309 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
3312 static const struct phy_reg phy_reg_init
[] = {
3320 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3323 /* Fine tune PLL performance */
3324 rtl_writephy(tp
, 0x1f, 0x0002);
3325 rtl_w0w1_phy(tp
, 0x02, 0x0100, 0x0600);
3326 rtl_w0w1_phy(tp
, 0x03, 0x0000, 0xe000);
3328 /* Switching regulator Slew rate */
3329 rtl_writephy(tp
, 0x1f, 0x0002);
3330 rtl_patchphy(tp
, 0x0f, 0x0017);
3332 rtl_writephy(tp
, 0x1f, 0x0005);
3333 rtl_writephy(tp
, 0x05, 0x001b);
3335 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xb300);
3337 rtl_writephy(tp
, 0x1f, 0x0000);
3340 static void rtl8168d_3_hw_phy_config(struct rtl8169_private
*tp
)
3342 static const struct phy_reg phy_reg_init
[] = {
3398 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3401 static void rtl8168d_4_hw_phy_config(struct rtl8169_private
*tp
)
3403 static const struct phy_reg phy_reg_init
[] = {
3413 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3414 rtl_patchphy(tp
, 0x0d, 1 << 5);
3417 static void rtl8168e_1_hw_phy_config(struct rtl8169_private
*tp
)
3419 static const struct phy_reg phy_reg_init
[] = {
3420 /* Enable Delay cap */
3426 /* Channel estimation fine tune */
3435 /* Update PFM & 10M TX idle timer */
3447 rtl_apply_firmware(tp
);
3449 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3451 /* DCO enable for 10M IDLE Power */
3452 rtl_writephy(tp
, 0x1f, 0x0007);
3453 rtl_writephy(tp
, 0x1e, 0x0023);
3454 rtl_w0w1_phy(tp
, 0x17, 0x0006, 0x0000);
3455 rtl_writephy(tp
, 0x1f, 0x0000);
3457 /* For impedance matching */
3458 rtl_writephy(tp
, 0x1f, 0x0002);
3459 rtl_w0w1_phy(tp
, 0x08, 0x8000, 0x7f00);
3460 rtl_writephy(tp
, 0x1f, 0x0000);
3462 /* PHY auto speed down */
3463 rtl_writephy(tp
, 0x1f, 0x0007);
3464 rtl_writephy(tp
, 0x1e, 0x002d);
3465 rtl_w0w1_phy(tp
, 0x18, 0x0050, 0x0000);
3466 rtl_writephy(tp
, 0x1f, 0x0000);
3467 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
3469 rtl_writephy(tp
, 0x1f, 0x0005);
3470 rtl_writephy(tp
, 0x05, 0x8b86);
3471 rtl_w0w1_phy(tp
, 0x06, 0x0001, 0x0000);
3472 rtl_writephy(tp
, 0x1f, 0x0000);
3474 rtl_writephy(tp
, 0x1f, 0x0005);
3475 rtl_writephy(tp
, 0x05, 0x8b85);
3476 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x2000);
3477 rtl_writephy(tp
, 0x1f, 0x0007);
3478 rtl_writephy(tp
, 0x1e, 0x0020);
3479 rtl_w0w1_phy(tp
, 0x15, 0x0000, 0x1100);
3480 rtl_writephy(tp
, 0x1f, 0x0006);
3481 rtl_writephy(tp
, 0x00, 0x5a00);
3482 rtl_writephy(tp
, 0x1f, 0x0000);
3483 rtl_writephy(tp
, 0x0d, 0x0007);
3484 rtl_writephy(tp
, 0x0e, 0x003c);
3485 rtl_writephy(tp
, 0x0d, 0x4007);
3486 rtl_writephy(tp
, 0x0e, 0x0000);
3487 rtl_writephy(tp
, 0x0d, 0x0000);
3490 static void rtl_rar_exgmac_set(struct rtl8169_private
*tp
, u8
*addr
)
3493 addr
[0] | (addr
[1] << 8),
3494 addr
[2] | (addr
[3] << 8),
3495 addr
[4] | (addr
[5] << 8)
3497 const struct exgmac_reg e
[] = {
3498 { .addr
= 0xe0, ERIAR_MASK_1111
, .val
= w
[0] | (w
[1] << 16) },
3499 { .addr
= 0xe4, ERIAR_MASK_1111
, .val
= w
[2] },
3500 { .addr
= 0xf0, ERIAR_MASK_1111
, .val
= w
[0] << 16 },
3501 { .addr
= 0xf4, ERIAR_MASK_1111
, .val
= w
[1] | (w
[2] << 16) }
3504 rtl_write_exgmac_batch(tp
, e
, ARRAY_SIZE(e
));
3507 static void rtl8168e_2_hw_phy_config(struct rtl8169_private
*tp
)
3509 static const struct phy_reg phy_reg_init
[] = {
3510 /* Enable Delay cap */
3519 /* Channel estimation fine tune */
3536 rtl_apply_firmware(tp
);
3538 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3540 /* For 4-corner performance improve */
3541 rtl_writephy(tp
, 0x1f, 0x0005);
3542 rtl_writephy(tp
, 0x05, 0x8b80);
3543 rtl_w0w1_phy(tp
, 0x17, 0x0006, 0x0000);
3544 rtl_writephy(tp
, 0x1f, 0x0000);
3546 /* PHY auto speed down */
3547 rtl_writephy(tp
, 0x1f, 0x0004);
3548 rtl_writephy(tp
, 0x1f, 0x0007);
3549 rtl_writephy(tp
, 0x1e, 0x002d);
3550 rtl_w0w1_phy(tp
, 0x18, 0x0010, 0x0000);
3551 rtl_writephy(tp
, 0x1f, 0x0002);
3552 rtl_writephy(tp
, 0x1f, 0x0000);
3553 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
3555 /* improve 10M EEE waveform */
3556 rtl_writephy(tp
, 0x1f, 0x0005);
3557 rtl_writephy(tp
, 0x05, 0x8b86);
3558 rtl_w0w1_phy(tp
, 0x06, 0x0001, 0x0000);
3559 rtl_writephy(tp
, 0x1f, 0x0000);
3561 /* Improve 2-pair detection performance */
3562 rtl_writephy(tp
, 0x1f, 0x0005);
3563 rtl_writephy(tp
, 0x05, 0x8b85);
3564 rtl_w0w1_phy(tp
, 0x06, 0x4000, 0x0000);
3565 rtl_writephy(tp
, 0x1f, 0x0000);
3568 rtl_w0w1_eri(tp
, 0x1b0, ERIAR_MASK_1111
, 0x0000, 0x0003, ERIAR_EXGMAC
);
3569 rtl_writephy(tp
, 0x1f, 0x0005);
3570 rtl_writephy(tp
, 0x05, 0x8b85);
3571 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x2000);
3572 rtl_writephy(tp
, 0x1f, 0x0004);
3573 rtl_writephy(tp
, 0x1f, 0x0007);
3574 rtl_writephy(tp
, 0x1e, 0x0020);
3575 rtl_w0w1_phy(tp
, 0x15, 0x0000, 0x0100);
3576 rtl_writephy(tp
, 0x1f, 0x0002);
3577 rtl_writephy(tp
, 0x1f, 0x0000);
3578 rtl_writephy(tp
, 0x0d, 0x0007);
3579 rtl_writephy(tp
, 0x0e, 0x003c);
3580 rtl_writephy(tp
, 0x0d, 0x4007);
3581 rtl_writephy(tp
, 0x0e, 0x0000);
3582 rtl_writephy(tp
, 0x0d, 0x0000);
3585 rtl_writephy(tp
, 0x1f, 0x0003);
3586 rtl_w0w1_phy(tp
, 0x19, 0x0000, 0x0001);
3587 rtl_w0w1_phy(tp
, 0x10, 0x0000, 0x0400);
3588 rtl_writephy(tp
, 0x1f, 0x0000);
3590 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3591 rtl_rar_exgmac_set(tp
, tp
->dev
->dev_addr
);
3594 static void rtl8168f_hw_phy_config(struct rtl8169_private
*tp
)
3596 /* For 4-corner performance improve */
3597 rtl_writephy(tp
, 0x1f, 0x0005);
3598 rtl_writephy(tp
, 0x05, 0x8b80);
3599 rtl_w0w1_phy(tp
, 0x06, 0x0006, 0x0000);
3600 rtl_writephy(tp
, 0x1f, 0x0000);
3602 /* PHY auto speed down */
3603 rtl_writephy(tp
, 0x1f, 0x0007);
3604 rtl_writephy(tp
, 0x1e, 0x002d);
3605 rtl_w0w1_phy(tp
, 0x18, 0x0010, 0x0000);
3606 rtl_writephy(tp
, 0x1f, 0x0000);
3607 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
3609 /* Improve 10M EEE waveform */
3610 rtl_writephy(tp
, 0x1f, 0x0005);
3611 rtl_writephy(tp
, 0x05, 0x8b86);
3612 rtl_w0w1_phy(tp
, 0x06, 0x0001, 0x0000);
3613 rtl_writephy(tp
, 0x1f, 0x0000);
3616 static void rtl8168f_1_hw_phy_config(struct rtl8169_private
*tp
)
3618 static const struct phy_reg phy_reg_init
[] = {
3619 /* Channel estimation fine tune */
3624 /* Modify green table for giga & fnet */
3641 /* Modify green table for 10M */
3647 /* Disable hiimpedance detection (RTCT) */
3653 rtl_apply_firmware(tp
);
3655 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3657 rtl8168f_hw_phy_config(tp
);
3659 /* Improve 2-pair detection performance */
3660 rtl_writephy(tp
, 0x1f, 0x0005);
3661 rtl_writephy(tp
, 0x05, 0x8b85);
3662 rtl_w0w1_phy(tp
, 0x06, 0x4000, 0x0000);
3663 rtl_writephy(tp
, 0x1f, 0x0000);
3666 static void rtl8168f_2_hw_phy_config(struct rtl8169_private
*tp
)
3668 rtl_apply_firmware(tp
);
3670 rtl8168f_hw_phy_config(tp
);
3673 static void rtl8411_hw_phy_config(struct rtl8169_private
*tp
)
3675 static const struct phy_reg phy_reg_init
[] = {
3676 /* Channel estimation fine tune */
3681 /* Modify green table for giga & fnet */
3698 /* Modify green table for 10M */
3704 /* Disable hiimpedance detection (RTCT) */
3711 rtl_apply_firmware(tp
);
3713 rtl8168f_hw_phy_config(tp
);
3715 /* Improve 2-pair detection performance */
3716 rtl_writephy(tp
, 0x1f, 0x0005);
3717 rtl_writephy(tp
, 0x05, 0x8b85);
3718 rtl_w0w1_phy(tp
, 0x06, 0x4000, 0x0000);
3719 rtl_writephy(tp
, 0x1f, 0x0000);
3721 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3723 /* Modify green table for giga */
3724 rtl_writephy(tp
, 0x1f, 0x0005);
3725 rtl_writephy(tp
, 0x05, 0x8b54);
3726 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0800);
3727 rtl_writephy(tp
, 0x05, 0x8b5d);
3728 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0800);
3729 rtl_writephy(tp
, 0x05, 0x8a7c);
3730 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0100);
3731 rtl_writephy(tp
, 0x05, 0x8a7f);
3732 rtl_w0w1_phy(tp
, 0x06, 0x0100, 0x0000);
3733 rtl_writephy(tp
, 0x05, 0x8a82);
3734 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0100);
3735 rtl_writephy(tp
, 0x05, 0x8a85);
3736 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0100);
3737 rtl_writephy(tp
, 0x05, 0x8a88);
3738 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0100);
3739 rtl_writephy(tp
, 0x1f, 0x0000);
3741 /* uc same-seed solution */
3742 rtl_writephy(tp
, 0x1f, 0x0005);
3743 rtl_writephy(tp
, 0x05, 0x8b85);
3744 rtl_w0w1_phy(tp
, 0x06, 0x8000, 0x0000);
3745 rtl_writephy(tp
, 0x1f, 0x0000);
3748 rtl_w0w1_eri(tp
, 0x1b0, ERIAR_MASK_0001
, 0x00, 0x03, ERIAR_EXGMAC
);
3749 rtl_writephy(tp
, 0x1f, 0x0005);
3750 rtl_writephy(tp
, 0x05, 0x8b85);
3751 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x2000);
3752 rtl_writephy(tp
, 0x1f, 0x0004);
3753 rtl_writephy(tp
, 0x1f, 0x0007);
3754 rtl_writephy(tp
, 0x1e, 0x0020);
3755 rtl_w0w1_phy(tp
, 0x15, 0x0000, 0x0100);
3756 rtl_writephy(tp
, 0x1f, 0x0000);
3757 rtl_writephy(tp
, 0x0d, 0x0007);
3758 rtl_writephy(tp
, 0x0e, 0x003c);
3759 rtl_writephy(tp
, 0x0d, 0x4007);
3760 rtl_writephy(tp
, 0x0e, 0x0000);
3761 rtl_writephy(tp
, 0x0d, 0x0000);
3764 rtl_writephy(tp
, 0x1f, 0x0003);
3765 rtl_w0w1_phy(tp
, 0x19, 0x0000, 0x0001);
3766 rtl_w0w1_phy(tp
, 0x10, 0x0000, 0x0400);
3767 rtl_writephy(tp
, 0x1f, 0x0000);
3770 static void rtl8168g_1_hw_phy_config(struct rtl8169_private
*tp
)
3772 rtl_apply_firmware(tp
);
3774 rtl_writephy(tp
, 0x1f, 0x0a46);
3775 if (rtl_readphy(tp
, 0x10) & 0x0100) {
3776 rtl_writephy(tp
, 0x1f, 0x0bcc);
3777 rtl_w0w1_phy(tp
, 0x12, 0x0000, 0x8000);
3779 rtl_writephy(tp
, 0x1f, 0x0bcc);
3780 rtl_w0w1_phy(tp
, 0x12, 0x8000, 0x0000);
3783 rtl_writephy(tp
, 0x1f, 0x0a46);
3784 if (rtl_readphy(tp
, 0x13) & 0x0100) {
3785 rtl_writephy(tp
, 0x1f, 0x0c41);
3786 rtl_w0w1_phy(tp
, 0x15, 0x0002, 0x0000);
3788 rtl_writephy(tp
, 0x1f, 0x0c41);
3789 rtl_w0w1_phy(tp
, 0x15, 0x0000, 0x0002);
3792 /* Enable PHY auto speed down */
3793 rtl_writephy(tp
, 0x1f, 0x0a44);
3794 rtl_w0w1_phy(tp
, 0x11, 0x000c, 0x0000);
3796 rtl_writephy(tp
, 0x1f, 0x0bcc);
3797 rtl_w0w1_phy(tp
, 0x14, 0x0100, 0x0000);
3798 rtl_writephy(tp
, 0x1f, 0x0a44);
3799 rtl_w0w1_phy(tp
, 0x11, 0x00c0, 0x0000);
3800 rtl_writephy(tp
, 0x1f, 0x0a43);
3801 rtl_writephy(tp
, 0x13, 0x8084);
3802 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x6000);
3803 rtl_w0w1_phy(tp
, 0x10, 0x1003, 0x0000);
3805 /* EEE auto-fallback function */
3806 rtl_writephy(tp
, 0x1f, 0x0a4b);
3807 rtl_w0w1_phy(tp
, 0x11, 0x0004, 0x0000);
3809 /* Enable UC LPF tune function */
3810 rtl_writephy(tp
, 0x1f, 0x0a43);
3811 rtl_writephy(tp
, 0x13, 0x8012);
3812 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
3814 rtl_writephy(tp
, 0x1f, 0x0c42);
3815 rtl_w0w1_phy(tp
, 0x11, 0x4000, 0x2000);
3817 /* Improve SWR Efficiency */
3818 rtl_writephy(tp
, 0x1f, 0x0bcd);
3819 rtl_writephy(tp
, 0x14, 0x5065);
3820 rtl_writephy(tp
, 0x14, 0xd065);
3821 rtl_writephy(tp
, 0x1f, 0x0bc8);
3822 rtl_writephy(tp
, 0x11, 0x5655);
3823 rtl_writephy(tp
, 0x1f, 0x0bcd);
3824 rtl_writephy(tp
, 0x14, 0x1065);
3825 rtl_writephy(tp
, 0x14, 0x9065);
3826 rtl_writephy(tp
, 0x14, 0x1065);
3828 /* Check ALDPS bit, disable it if enabled */
3829 rtl_writephy(tp
, 0x1f, 0x0a43);
3830 if (rtl_readphy(tp
, 0x10) & 0x0004)
3831 rtl_w0w1_phy(tp
, 0x10, 0x0000, 0x0004);
3833 rtl_writephy(tp
, 0x1f, 0x0000);
3836 static void rtl8168g_2_hw_phy_config(struct rtl8169_private
*tp
)
3838 rtl_apply_firmware(tp
);
3841 static void rtl8168h_1_hw_phy_config(struct rtl8169_private
*tp
)
3846 rtl_apply_firmware(tp
);
3848 /* CHN EST parameters adjust - giga master */
3849 rtl_writephy(tp
, 0x1f, 0x0a43);
3850 rtl_writephy(tp
, 0x13, 0x809b);
3851 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0xf800);
3852 rtl_writephy(tp
, 0x13, 0x80a2);
3853 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0xff00);
3854 rtl_writephy(tp
, 0x13, 0x80a4);
3855 rtl_w0w1_phy(tp
, 0x14, 0x8500, 0xff00);
3856 rtl_writephy(tp
, 0x13, 0x809c);
3857 rtl_w0w1_phy(tp
, 0x14, 0xbd00, 0xff00);
3858 rtl_writephy(tp
, 0x1f, 0x0000);
3860 /* CHN EST parameters adjust - giga slave */
3861 rtl_writephy(tp
, 0x1f, 0x0a43);
3862 rtl_writephy(tp
, 0x13, 0x80ad);
3863 rtl_w0w1_phy(tp
, 0x14, 0x7000, 0xf800);
3864 rtl_writephy(tp
, 0x13, 0x80b4);
3865 rtl_w0w1_phy(tp
, 0x14, 0x5000, 0xff00);
3866 rtl_writephy(tp
, 0x13, 0x80ac);
3867 rtl_w0w1_phy(tp
, 0x14, 0x4000, 0xff00);
3868 rtl_writephy(tp
, 0x1f, 0x0000);
3870 /* CHN EST parameters adjust - fnet */
3871 rtl_writephy(tp
, 0x1f, 0x0a43);
3872 rtl_writephy(tp
, 0x13, 0x808e);
3873 rtl_w0w1_phy(tp
, 0x14, 0x1200, 0xff00);
3874 rtl_writephy(tp
, 0x13, 0x8090);
3875 rtl_w0w1_phy(tp
, 0x14, 0xe500, 0xff00);
3876 rtl_writephy(tp
, 0x13, 0x8092);
3877 rtl_w0w1_phy(tp
, 0x14, 0x9f00, 0xff00);
3878 rtl_writephy(tp
, 0x1f, 0x0000);
3880 /* enable R-tune & PGA-retune function */
3882 rtl_writephy(tp
, 0x1f, 0x0a46);
3883 data
= rtl_readphy(tp
, 0x13);
3886 dout_tapbin
|= data
;
3887 data
= rtl_readphy(tp
, 0x12);
3890 dout_tapbin
|= data
;
3891 dout_tapbin
= ~(dout_tapbin
^0x08);
3893 dout_tapbin
&= 0xf000;
3894 rtl_writephy(tp
, 0x1f, 0x0a43);
3895 rtl_writephy(tp
, 0x13, 0x827a);
3896 rtl_w0w1_phy(tp
, 0x14, dout_tapbin
, 0xf000);
3897 rtl_writephy(tp
, 0x13, 0x827b);
3898 rtl_w0w1_phy(tp
, 0x14, dout_tapbin
, 0xf000);
3899 rtl_writephy(tp
, 0x13, 0x827c);
3900 rtl_w0w1_phy(tp
, 0x14, dout_tapbin
, 0xf000);
3901 rtl_writephy(tp
, 0x13, 0x827d);
3902 rtl_w0w1_phy(tp
, 0x14, dout_tapbin
, 0xf000);
3904 rtl_writephy(tp
, 0x1f, 0x0a43);
3905 rtl_writephy(tp
, 0x13, 0x0811);
3906 rtl_w0w1_phy(tp
, 0x14, 0x0800, 0x0000);
3907 rtl_writephy(tp
, 0x1f, 0x0a42);
3908 rtl_w0w1_phy(tp
, 0x16, 0x0002, 0x0000);
3909 rtl_writephy(tp
, 0x1f, 0x0000);
3911 /* enable GPHY 10M */
3912 rtl_writephy(tp
, 0x1f, 0x0a44);
3913 rtl_w0w1_phy(tp
, 0x11, 0x0800, 0x0000);
3914 rtl_writephy(tp
, 0x1f, 0x0000);
3916 /* SAR ADC performance */
3917 rtl_writephy(tp
, 0x1f, 0x0bca);
3918 rtl_w0w1_phy(tp
, 0x17, 0x4000, 0x3000);
3919 rtl_writephy(tp
, 0x1f, 0x0000);
3921 rtl_writephy(tp
, 0x1f, 0x0a43);
3922 rtl_writephy(tp
, 0x13, 0x803f);
3923 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3924 rtl_writephy(tp
, 0x13, 0x8047);
3925 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3926 rtl_writephy(tp
, 0x13, 0x804f);
3927 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3928 rtl_writephy(tp
, 0x13, 0x8057);
3929 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3930 rtl_writephy(tp
, 0x13, 0x805f);
3931 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3932 rtl_writephy(tp
, 0x13, 0x8067);
3933 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3934 rtl_writephy(tp
, 0x13, 0x806f);
3935 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3936 rtl_writephy(tp
, 0x1f, 0x0000);
3938 /* disable phy pfm mode */
3939 rtl_writephy(tp
, 0x1f, 0x0a44);
3940 rtl_w0w1_phy(tp
, 0x11, 0x0000, 0x0080);
3941 rtl_writephy(tp
, 0x1f, 0x0000);
3943 /* Check ALDPS bit, disable it if enabled */
3944 rtl_writephy(tp
, 0x1f, 0x0a43);
3945 if (rtl_readphy(tp
, 0x10) & 0x0004)
3946 rtl_w0w1_phy(tp
, 0x10, 0x0000, 0x0004);
3948 rtl_writephy(tp
, 0x1f, 0x0000);
3951 static void rtl8168h_2_hw_phy_config(struct rtl8169_private
*tp
)
3953 u16 ioffset_p3
, ioffset_p2
, ioffset_p1
, ioffset_p0
;
3957 rtl_apply_firmware(tp
);
3959 /* CHIN EST parameter update */
3960 rtl_writephy(tp
, 0x1f, 0x0a43);
3961 rtl_writephy(tp
, 0x13, 0x808a);
3962 rtl_w0w1_phy(tp
, 0x14, 0x000a, 0x003f);
3963 rtl_writephy(tp
, 0x1f, 0x0000);
3965 /* enable R-tune & PGA-retune function */
3966 rtl_writephy(tp
, 0x1f, 0x0a43);
3967 rtl_writephy(tp
, 0x13, 0x0811);
3968 rtl_w0w1_phy(tp
, 0x14, 0x0800, 0x0000);
3969 rtl_writephy(tp
, 0x1f, 0x0a42);
3970 rtl_w0w1_phy(tp
, 0x16, 0x0002, 0x0000);
3971 rtl_writephy(tp
, 0x1f, 0x0000);
3973 /* enable GPHY 10M */
3974 rtl_writephy(tp
, 0x1f, 0x0a44);
3975 rtl_w0w1_phy(tp
, 0x11, 0x0800, 0x0000);
3976 rtl_writephy(tp
, 0x1f, 0x0000);
3978 r8168_mac_ocp_write(tp
, 0xdd02, 0x807d);
3979 data
= r8168_mac_ocp_read(tp
, 0xdd02);
3980 ioffset_p3
= ((data
& 0x80)>>7);
3983 data
= r8168_mac_ocp_read(tp
, 0xdd00);
3984 ioffset_p3
|= ((data
& (0xe000))>>13);
3985 ioffset_p2
= ((data
& (0x1e00))>>9);
3986 ioffset_p1
= ((data
& (0x01e0))>>5);
3987 ioffset_p0
= ((data
& 0x0010)>>4);
3989 ioffset_p0
|= (data
& (0x07));
3990 data
= (ioffset_p3
<<12)|(ioffset_p2
<<8)|(ioffset_p1
<<4)|(ioffset_p0
);
3992 if ((ioffset_p3
!= 0x0f) || (ioffset_p2
!= 0x0f) ||
3993 (ioffset_p1
!= 0x0f) || (ioffset_p0
!= 0x0f)) {
3994 rtl_writephy(tp
, 0x1f, 0x0bcf);
3995 rtl_writephy(tp
, 0x16, data
);
3996 rtl_writephy(tp
, 0x1f, 0x0000);
3999 /* Modify rlen (TX LPF corner frequency) level */
4000 rtl_writephy(tp
, 0x1f, 0x0bcd);
4001 data
= rtl_readphy(tp
, 0x16);
4006 data
= rlen
| (rlen
<<4) | (rlen
<<8) | (rlen
<<12);
4007 rtl_writephy(tp
, 0x17, data
);
4008 rtl_writephy(tp
, 0x1f, 0x0bcd);
4009 rtl_writephy(tp
, 0x1f, 0x0000);
4011 /* disable phy pfm mode */
4012 rtl_writephy(tp
, 0x1f, 0x0a44);
4013 rtl_w0w1_phy(tp
, 0x11, 0x0000, 0x0080);
4014 rtl_writephy(tp
, 0x1f, 0x0000);
4016 /* Check ALDPS bit, disable it if enabled */
4017 rtl_writephy(tp
, 0x1f, 0x0a43);
4018 if (rtl_readphy(tp
, 0x10) & 0x0004)
4019 rtl_w0w1_phy(tp
, 0x10, 0x0000, 0x0004);
4021 rtl_writephy(tp
, 0x1f, 0x0000);
4024 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private
*tp
)
4026 /* Enable PHY auto speed down */
4027 rtl_writephy(tp
, 0x1f, 0x0a44);
4028 rtl_w0w1_phy(tp
, 0x11, 0x000c, 0x0000);
4029 rtl_writephy(tp
, 0x1f, 0x0000);
4031 /* patch 10M & ALDPS */
4032 rtl_writephy(tp
, 0x1f, 0x0bcc);
4033 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x0100);
4034 rtl_writephy(tp
, 0x1f, 0x0a44);
4035 rtl_w0w1_phy(tp
, 0x11, 0x00c0, 0x0000);
4036 rtl_writephy(tp
, 0x1f, 0x0a43);
4037 rtl_writephy(tp
, 0x13, 0x8084);
4038 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x6000);
4039 rtl_w0w1_phy(tp
, 0x10, 0x1003, 0x0000);
4040 rtl_writephy(tp
, 0x1f, 0x0000);
4042 /* Enable EEE auto-fallback function */
4043 rtl_writephy(tp
, 0x1f, 0x0a4b);
4044 rtl_w0w1_phy(tp
, 0x11, 0x0004, 0x0000);
4045 rtl_writephy(tp
, 0x1f, 0x0000);
4047 /* Enable UC LPF tune function */
4048 rtl_writephy(tp
, 0x1f, 0x0a43);
4049 rtl_writephy(tp
, 0x13, 0x8012);
4050 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
4051 rtl_writephy(tp
, 0x1f, 0x0000);
4053 /* set rg_sel_sdm_rate */
4054 rtl_writephy(tp
, 0x1f, 0x0c42);
4055 rtl_w0w1_phy(tp
, 0x11, 0x4000, 0x2000);
4056 rtl_writephy(tp
, 0x1f, 0x0000);
4058 /* Check ALDPS bit, disable it if enabled */
4059 rtl_writephy(tp
, 0x1f, 0x0a43);
4060 if (rtl_readphy(tp
, 0x10) & 0x0004)
4061 rtl_w0w1_phy(tp
, 0x10, 0x0000, 0x0004);
4063 rtl_writephy(tp
, 0x1f, 0x0000);
4066 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private
*tp
)
4068 /* patch 10M & ALDPS */
4069 rtl_writephy(tp
, 0x1f, 0x0bcc);
4070 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x0100);
4071 rtl_writephy(tp
, 0x1f, 0x0a44);
4072 rtl_w0w1_phy(tp
, 0x11, 0x00c0, 0x0000);
4073 rtl_writephy(tp
, 0x1f, 0x0a43);
4074 rtl_writephy(tp
, 0x13, 0x8084);
4075 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x6000);
4076 rtl_w0w1_phy(tp
, 0x10, 0x1003, 0x0000);
4077 rtl_writephy(tp
, 0x1f, 0x0000);
4079 /* Enable UC LPF tune function */
4080 rtl_writephy(tp
, 0x1f, 0x0a43);
4081 rtl_writephy(tp
, 0x13, 0x8012);
4082 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
4083 rtl_writephy(tp
, 0x1f, 0x0000);
4085 /* Set rg_sel_sdm_rate */
4086 rtl_writephy(tp
, 0x1f, 0x0c42);
4087 rtl_w0w1_phy(tp
, 0x11, 0x4000, 0x2000);
4088 rtl_writephy(tp
, 0x1f, 0x0000);
4090 /* Channel estimation parameters */
4091 rtl_writephy(tp
, 0x1f, 0x0a43);
4092 rtl_writephy(tp
, 0x13, 0x80f3);
4093 rtl_w0w1_phy(tp
, 0x14, 0x8b00, ~0x8bff);
4094 rtl_writephy(tp
, 0x13, 0x80f0);
4095 rtl_w0w1_phy(tp
, 0x14, 0x3a00, ~0x3aff);
4096 rtl_writephy(tp
, 0x13, 0x80ef);
4097 rtl_w0w1_phy(tp
, 0x14, 0x0500, ~0x05ff);
4098 rtl_writephy(tp
, 0x13, 0x80f6);
4099 rtl_w0w1_phy(tp
, 0x14, 0x6e00, ~0x6eff);
4100 rtl_writephy(tp
, 0x13, 0x80ec);
4101 rtl_w0w1_phy(tp
, 0x14, 0x6800, ~0x68ff);
4102 rtl_writephy(tp
, 0x13, 0x80ed);
4103 rtl_w0w1_phy(tp
, 0x14, 0x7c00, ~0x7cff);
4104 rtl_writephy(tp
, 0x13, 0x80f2);
4105 rtl_w0w1_phy(tp
, 0x14, 0xf400, ~0xf4ff);
4106 rtl_writephy(tp
, 0x13, 0x80f4);
4107 rtl_w0w1_phy(tp
, 0x14, 0x8500, ~0x85ff);
4108 rtl_writephy(tp
, 0x1f, 0x0a43);
4109 rtl_writephy(tp
, 0x13, 0x8110);
4110 rtl_w0w1_phy(tp
, 0x14, 0xa800, ~0xa8ff);
4111 rtl_writephy(tp
, 0x13, 0x810f);
4112 rtl_w0w1_phy(tp
, 0x14, 0x1d00, ~0x1dff);
4113 rtl_writephy(tp
, 0x13, 0x8111);
4114 rtl_w0w1_phy(tp
, 0x14, 0xf500, ~0xf5ff);
4115 rtl_writephy(tp
, 0x13, 0x8113);
4116 rtl_w0w1_phy(tp
, 0x14, 0x6100, ~0x61ff);
4117 rtl_writephy(tp
, 0x13, 0x8115);
4118 rtl_w0w1_phy(tp
, 0x14, 0x9200, ~0x92ff);
4119 rtl_writephy(tp
, 0x13, 0x810e);
4120 rtl_w0w1_phy(tp
, 0x14, 0x0400, ~0x04ff);
4121 rtl_writephy(tp
, 0x13, 0x810c);
4122 rtl_w0w1_phy(tp
, 0x14, 0x7c00, ~0x7cff);
4123 rtl_writephy(tp
, 0x13, 0x810b);
4124 rtl_w0w1_phy(tp
, 0x14, 0x5a00, ~0x5aff);
4125 rtl_writephy(tp
, 0x1f, 0x0a43);
4126 rtl_writephy(tp
, 0x13, 0x80d1);
4127 rtl_w0w1_phy(tp
, 0x14, 0xff00, ~0xffff);
4128 rtl_writephy(tp
, 0x13, 0x80cd);
4129 rtl_w0w1_phy(tp
, 0x14, 0x9e00, ~0x9eff);
4130 rtl_writephy(tp
, 0x13, 0x80d3);
4131 rtl_w0w1_phy(tp
, 0x14, 0x0e00, ~0x0eff);
4132 rtl_writephy(tp
, 0x13, 0x80d5);
4133 rtl_w0w1_phy(tp
, 0x14, 0xca00, ~0xcaff);
4134 rtl_writephy(tp
, 0x13, 0x80d7);
4135 rtl_w0w1_phy(tp
, 0x14, 0x8400, ~0x84ff);
4137 /* Force PWM-mode */
4138 rtl_writephy(tp
, 0x1f, 0x0bcd);
4139 rtl_writephy(tp
, 0x14, 0x5065);
4140 rtl_writephy(tp
, 0x14, 0xd065);
4141 rtl_writephy(tp
, 0x1f, 0x0bc8);
4142 rtl_writephy(tp
, 0x12, 0x00ed);
4143 rtl_writephy(tp
, 0x1f, 0x0bcd);
4144 rtl_writephy(tp
, 0x14, 0x1065);
4145 rtl_writephy(tp
, 0x14, 0x9065);
4146 rtl_writephy(tp
, 0x14, 0x1065);
4147 rtl_writephy(tp
, 0x1f, 0x0000);
4149 /* Check ALDPS bit, disable it if enabled */
4150 rtl_writephy(tp
, 0x1f, 0x0a43);
4151 if (rtl_readphy(tp
, 0x10) & 0x0004)
4152 rtl_w0w1_phy(tp
, 0x10, 0x0000, 0x0004);
4154 rtl_writephy(tp
, 0x1f, 0x0000);
4157 static void rtl8102e_hw_phy_config(struct rtl8169_private
*tp
)
4159 static const struct phy_reg phy_reg_init
[] = {
4166 rtl_writephy(tp
, 0x1f, 0x0000);
4167 rtl_patchphy(tp
, 0x11, 1 << 12);
4168 rtl_patchphy(tp
, 0x19, 1 << 13);
4169 rtl_patchphy(tp
, 0x10, 1 << 15);
4171 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
4174 static void rtl8105e_hw_phy_config(struct rtl8169_private
*tp
)
4176 static const struct phy_reg phy_reg_init
[] = {
4190 /* Disable ALDPS before ram code */
4191 rtl_writephy(tp
, 0x1f, 0x0000);
4192 rtl_writephy(tp
, 0x18, 0x0310);
4195 rtl_apply_firmware(tp
);
4197 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
4200 static void rtl8402_hw_phy_config(struct rtl8169_private
*tp
)
4202 /* Disable ALDPS before setting firmware */
4203 rtl_writephy(tp
, 0x1f, 0x0000);
4204 rtl_writephy(tp
, 0x18, 0x0310);
4207 rtl_apply_firmware(tp
);
4210 rtl_eri_write(tp
, 0x1b0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4211 rtl_writephy(tp
, 0x1f, 0x0004);
4212 rtl_writephy(tp
, 0x10, 0x401f);
4213 rtl_writephy(tp
, 0x19, 0x7030);
4214 rtl_writephy(tp
, 0x1f, 0x0000);
4217 static void rtl8106e_hw_phy_config(struct rtl8169_private
*tp
)
4219 static const struct phy_reg phy_reg_init
[] = {
4226 /* Disable ALDPS before ram code */
4227 rtl_writephy(tp
, 0x1f, 0x0000);
4228 rtl_writephy(tp
, 0x18, 0x0310);
4231 rtl_apply_firmware(tp
);
4233 rtl_eri_write(tp
, 0x1b0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4234 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
4236 rtl_eri_write(tp
, 0x1d0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4239 static void rtl_hw_phy_config(struct net_device
*dev
)
4241 struct rtl8169_private
*tp
= netdev_priv(dev
);
4243 rtl8169_print_mac_version(tp
);
4245 switch (tp
->mac_version
) {
4246 case RTL_GIGA_MAC_VER_01
:
4248 case RTL_GIGA_MAC_VER_02
:
4249 case RTL_GIGA_MAC_VER_03
:
4250 rtl8169s_hw_phy_config(tp
);
4252 case RTL_GIGA_MAC_VER_04
:
4253 rtl8169sb_hw_phy_config(tp
);
4255 case RTL_GIGA_MAC_VER_05
:
4256 rtl8169scd_hw_phy_config(tp
);
4258 case RTL_GIGA_MAC_VER_06
:
4259 rtl8169sce_hw_phy_config(tp
);
4261 case RTL_GIGA_MAC_VER_07
:
4262 case RTL_GIGA_MAC_VER_08
:
4263 case RTL_GIGA_MAC_VER_09
:
4264 rtl8102e_hw_phy_config(tp
);
4266 case RTL_GIGA_MAC_VER_11
:
4267 rtl8168bb_hw_phy_config(tp
);
4269 case RTL_GIGA_MAC_VER_12
:
4270 rtl8168bef_hw_phy_config(tp
);
4272 case RTL_GIGA_MAC_VER_17
:
4273 rtl8168bef_hw_phy_config(tp
);
4275 case RTL_GIGA_MAC_VER_18
:
4276 rtl8168cp_1_hw_phy_config(tp
);
4278 case RTL_GIGA_MAC_VER_19
:
4279 rtl8168c_1_hw_phy_config(tp
);
4281 case RTL_GIGA_MAC_VER_20
:
4282 rtl8168c_2_hw_phy_config(tp
);
4284 case RTL_GIGA_MAC_VER_21
:
4285 rtl8168c_3_hw_phy_config(tp
);
4287 case RTL_GIGA_MAC_VER_22
:
4288 rtl8168c_4_hw_phy_config(tp
);
4290 case RTL_GIGA_MAC_VER_23
:
4291 case RTL_GIGA_MAC_VER_24
:
4292 rtl8168cp_2_hw_phy_config(tp
);
4294 case RTL_GIGA_MAC_VER_25
:
4295 rtl8168d_1_hw_phy_config(tp
);
4297 case RTL_GIGA_MAC_VER_26
:
4298 rtl8168d_2_hw_phy_config(tp
);
4300 case RTL_GIGA_MAC_VER_27
:
4301 rtl8168d_3_hw_phy_config(tp
);
4303 case RTL_GIGA_MAC_VER_28
:
4304 rtl8168d_4_hw_phy_config(tp
);
4306 case RTL_GIGA_MAC_VER_29
:
4307 case RTL_GIGA_MAC_VER_30
:
4308 rtl8105e_hw_phy_config(tp
);
4310 case RTL_GIGA_MAC_VER_31
:
4313 case RTL_GIGA_MAC_VER_32
:
4314 case RTL_GIGA_MAC_VER_33
:
4315 rtl8168e_1_hw_phy_config(tp
);
4317 case RTL_GIGA_MAC_VER_34
:
4318 rtl8168e_2_hw_phy_config(tp
);
4320 case RTL_GIGA_MAC_VER_35
:
4321 rtl8168f_1_hw_phy_config(tp
);
4323 case RTL_GIGA_MAC_VER_36
:
4324 rtl8168f_2_hw_phy_config(tp
);
4327 case RTL_GIGA_MAC_VER_37
:
4328 rtl8402_hw_phy_config(tp
);
4331 case RTL_GIGA_MAC_VER_38
:
4332 rtl8411_hw_phy_config(tp
);
4335 case RTL_GIGA_MAC_VER_39
:
4336 rtl8106e_hw_phy_config(tp
);
4339 case RTL_GIGA_MAC_VER_40
:
4340 rtl8168g_1_hw_phy_config(tp
);
4342 case RTL_GIGA_MAC_VER_42
:
4343 case RTL_GIGA_MAC_VER_43
:
4344 case RTL_GIGA_MAC_VER_44
:
4345 rtl8168g_2_hw_phy_config(tp
);
4347 case RTL_GIGA_MAC_VER_45
:
4348 case RTL_GIGA_MAC_VER_47
:
4349 rtl8168h_1_hw_phy_config(tp
);
4351 case RTL_GIGA_MAC_VER_46
:
4352 case RTL_GIGA_MAC_VER_48
:
4353 rtl8168h_2_hw_phy_config(tp
);
4356 case RTL_GIGA_MAC_VER_49
:
4357 rtl8168ep_1_hw_phy_config(tp
);
4359 case RTL_GIGA_MAC_VER_50
:
4360 case RTL_GIGA_MAC_VER_51
:
4361 rtl8168ep_2_hw_phy_config(tp
);
4364 case RTL_GIGA_MAC_VER_41
:
4370 static void rtl_phy_work(struct rtl8169_private
*tp
)
4372 struct timer_list
*timer
= &tp
->timer
;
4373 void __iomem
*ioaddr
= tp
->mmio_addr
;
4374 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
4376 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
4378 if (tp
->phy_reset_pending(tp
)) {
4380 * A busy loop could burn quite a few cycles on nowadays CPU.
4381 * Let's delay the execution of the timer for a few ticks.
4387 if (tp
->link_ok(ioaddr
))
4390 netif_dbg(tp
, link
, tp
->dev
, "PHY reset until link up\n");
4392 tp
->phy_reset_enable(tp
);
4395 mod_timer(timer
, jiffies
+ timeout
);
4398 static void rtl_schedule_task(struct rtl8169_private
*tp
, enum rtl_flag flag
)
4400 if (!test_and_set_bit(flag
, tp
->wk
.flags
))
4401 schedule_work(&tp
->wk
.work
);
4404 static void rtl8169_phy_timer(unsigned long __opaque
)
4406 struct net_device
*dev
= (struct net_device
*)__opaque
;
4407 struct rtl8169_private
*tp
= netdev_priv(dev
);
4409 rtl_schedule_task(tp
, RTL_FLAG_TASK_PHY_PENDING
);
4412 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
4413 void __iomem
*ioaddr
)
4416 pci_release_regions(pdev
);
4417 pci_clear_mwi(pdev
);
4418 pci_disable_device(pdev
);
4422 DECLARE_RTL_COND(rtl_phy_reset_cond
)
4424 return tp
->phy_reset_pending(tp
);
4427 static void rtl8169_phy_reset(struct net_device
*dev
,
4428 struct rtl8169_private
*tp
)
4430 tp
->phy_reset_enable(tp
);
4431 rtl_msleep_loop_wait_low(tp
, &rtl_phy_reset_cond
, 1, 100);
4434 static bool rtl_tbi_enabled(struct rtl8169_private
*tp
)
4436 void __iomem
*ioaddr
= tp
->mmio_addr
;
4438 return (tp
->mac_version
== RTL_GIGA_MAC_VER_01
) &&
4439 (RTL_R8(PHYstatus
) & TBI_Enable
);
4442 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
4444 void __iomem
*ioaddr
= tp
->mmio_addr
;
4446 rtl_hw_phy_config(dev
);
4448 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
4449 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4453 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
4455 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
4456 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
4458 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
4459 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4461 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4462 rtl_writephy(tp
, 0x0b, 0x0000); //w 0x0b 15 0 0
4465 rtl8169_phy_reset(dev
, tp
);
4467 rtl8169_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
,
4468 ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
4469 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
4470 (tp
->mii
.supports_gmii
?
4471 ADVERTISED_1000baseT_Half
|
4472 ADVERTISED_1000baseT_Full
: 0));
4474 if (rtl_tbi_enabled(tp
))
4475 netif_info(tp
, link
, dev
, "TBI auto-negotiating\n");
4478 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
4480 void __iomem
*ioaddr
= tp
->mmio_addr
;
4484 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4486 RTL_W32(MAC4
, addr
[4] | addr
[5] << 8);
4489 RTL_W32(MAC0
, addr
[0] | addr
[1] << 8 | addr
[2] << 16 | addr
[3] << 24);
4492 if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
)
4493 rtl_rar_exgmac_set(tp
, addr
);
4495 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4497 rtl_unlock_work(tp
);
4500 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
4502 struct rtl8169_private
*tp
= netdev_priv(dev
);
4503 struct device
*d
= &tp
->pci_dev
->dev
;
4504 struct sockaddr
*addr
= p
;
4506 if (!is_valid_ether_addr(addr
->sa_data
))
4507 return -EADDRNOTAVAIL
;
4509 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
4511 pm_runtime_get_noresume(d
);
4513 if (pm_runtime_active(d
))
4514 rtl_rar_set(tp
, dev
->dev_addr
);
4516 pm_runtime_put_noidle(d
);
4521 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
4523 struct rtl8169_private
*tp
= netdev_priv(dev
);
4524 struct mii_ioctl_data
*data
= if_mii(ifr
);
4526 return netif_running(dev
) ? tp
->do_ioctl(tp
, data
, cmd
) : -ENODEV
;
4529 static int rtl_xmii_ioctl(struct rtl8169_private
*tp
,
4530 struct mii_ioctl_data
*data
, int cmd
)
4534 data
->phy_id
= 32; /* Internal PHY */
4538 data
->val_out
= rtl_readphy(tp
, data
->reg_num
& 0x1f);
4542 rtl_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
4548 static int rtl_tbi_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
4553 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8169_private
*tp
)
4555 if (tp
->features
& RTL_FEATURE_MSI
) {
4556 pci_disable_msi(pdev
);
4557 tp
->features
&= ~RTL_FEATURE_MSI
;
4561 static void rtl_init_mdio_ops(struct rtl8169_private
*tp
)
4563 struct mdio_ops
*ops
= &tp
->mdio_ops
;
4565 switch (tp
->mac_version
) {
4566 case RTL_GIGA_MAC_VER_27
:
4567 ops
->write
= r8168dp_1_mdio_write
;
4568 ops
->read
= r8168dp_1_mdio_read
;
4570 case RTL_GIGA_MAC_VER_28
:
4571 case RTL_GIGA_MAC_VER_31
:
4572 ops
->write
= r8168dp_2_mdio_write
;
4573 ops
->read
= r8168dp_2_mdio_read
;
4575 case RTL_GIGA_MAC_VER_40
:
4576 case RTL_GIGA_MAC_VER_41
:
4577 case RTL_GIGA_MAC_VER_42
:
4578 case RTL_GIGA_MAC_VER_43
:
4579 case RTL_GIGA_MAC_VER_44
:
4580 case RTL_GIGA_MAC_VER_45
:
4581 case RTL_GIGA_MAC_VER_46
:
4582 case RTL_GIGA_MAC_VER_47
:
4583 case RTL_GIGA_MAC_VER_48
:
4584 case RTL_GIGA_MAC_VER_49
:
4585 case RTL_GIGA_MAC_VER_50
:
4586 case RTL_GIGA_MAC_VER_51
:
4587 ops
->write
= r8168g_mdio_write
;
4588 ops
->read
= r8168g_mdio_read
;
4591 ops
->write
= r8169_mdio_write
;
4592 ops
->read
= r8169_mdio_read
;
4597 static void rtl_speed_down(struct rtl8169_private
*tp
)
4602 rtl_writephy(tp
, 0x1f, 0x0000);
4603 lpa
= rtl_readphy(tp
, MII_LPA
);
4605 if (lpa
& (LPA_10HALF
| LPA_10FULL
))
4606 adv
= ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
;
4607 else if (lpa
& (LPA_100HALF
| LPA_100FULL
))
4608 adv
= ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
4609 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
;
4611 adv
= ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
4612 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
4613 (tp
->mii
.supports_gmii
?
4614 ADVERTISED_1000baseT_Half
|
4615 ADVERTISED_1000baseT_Full
: 0);
4617 rtl8169_set_speed(tp
->dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
,
4621 static void rtl_wol_suspend_quirk(struct rtl8169_private
*tp
)
4623 void __iomem
*ioaddr
= tp
->mmio_addr
;
4625 switch (tp
->mac_version
) {
4626 case RTL_GIGA_MAC_VER_25
:
4627 case RTL_GIGA_MAC_VER_26
:
4628 case RTL_GIGA_MAC_VER_29
:
4629 case RTL_GIGA_MAC_VER_30
:
4630 case RTL_GIGA_MAC_VER_32
:
4631 case RTL_GIGA_MAC_VER_33
:
4632 case RTL_GIGA_MAC_VER_34
:
4633 case RTL_GIGA_MAC_VER_37
:
4634 case RTL_GIGA_MAC_VER_38
:
4635 case RTL_GIGA_MAC_VER_39
:
4636 case RTL_GIGA_MAC_VER_40
:
4637 case RTL_GIGA_MAC_VER_41
:
4638 case RTL_GIGA_MAC_VER_42
:
4639 case RTL_GIGA_MAC_VER_43
:
4640 case RTL_GIGA_MAC_VER_44
:
4641 case RTL_GIGA_MAC_VER_45
:
4642 case RTL_GIGA_MAC_VER_46
:
4643 case RTL_GIGA_MAC_VER_47
:
4644 case RTL_GIGA_MAC_VER_48
:
4645 case RTL_GIGA_MAC_VER_49
:
4646 case RTL_GIGA_MAC_VER_50
:
4647 case RTL_GIGA_MAC_VER_51
:
4648 RTL_W32(RxConfig
, RTL_R32(RxConfig
) |
4649 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
);
4656 static bool rtl_wol_pll_power_down(struct rtl8169_private
*tp
)
4658 if (!(__rtl8169_get_wol(tp
) & WAKE_ANY
))
4662 rtl_wol_suspend_quirk(tp
);
4667 static void r810x_phy_power_down(struct rtl8169_private
*tp
)
4669 rtl_writephy(tp
, 0x1f, 0x0000);
4670 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
4673 static void r810x_phy_power_up(struct rtl8169_private
*tp
)
4675 rtl_writephy(tp
, 0x1f, 0x0000);
4676 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
4679 static void r810x_pll_power_down(struct rtl8169_private
*tp
)
4681 void __iomem
*ioaddr
= tp
->mmio_addr
;
4683 if (rtl_wol_pll_power_down(tp
))
4686 r810x_phy_power_down(tp
);
4688 switch (tp
->mac_version
) {
4689 case RTL_GIGA_MAC_VER_07
:
4690 case RTL_GIGA_MAC_VER_08
:
4691 case RTL_GIGA_MAC_VER_09
:
4692 case RTL_GIGA_MAC_VER_10
:
4693 case RTL_GIGA_MAC_VER_13
:
4694 case RTL_GIGA_MAC_VER_16
:
4697 RTL_W8(PMCH
, RTL_R8(PMCH
) & ~0x80);
4702 static void r810x_pll_power_up(struct rtl8169_private
*tp
)
4704 void __iomem
*ioaddr
= tp
->mmio_addr
;
4706 r810x_phy_power_up(tp
);
4708 switch (tp
->mac_version
) {
4709 case RTL_GIGA_MAC_VER_07
:
4710 case RTL_GIGA_MAC_VER_08
:
4711 case RTL_GIGA_MAC_VER_09
:
4712 case RTL_GIGA_MAC_VER_10
:
4713 case RTL_GIGA_MAC_VER_13
:
4714 case RTL_GIGA_MAC_VER_16
:
4716 case RTL_GIGA_MAC_VER_47
:
4717 case RTL_GIGA_MAC_VER_48
:
4718 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0xc0);
4721 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0x80);
4726 static void r8168_phy_power_up(struct rtl8169_private
*tp
)
4728 rtl_writephy(tp
, 0x1f, 0x0000);
4729 switch (tp
->mac_version
) {
4730 case RTL_GIGA_MAC_VER_11
:
4731 case RTL_GIGA_MAC_VER_12
:
4732 case RTL_GIGA_MAC_VER_17
:
4733 case RTL_GIGA_MAC_VER_18
:
4734 case RTL_GIGA_MAC_VER_19
:
4735 case RTL_GIGA_MAC_VER_20
:
4736 case RTL_GIGA_MAC_VER_21
:
4737 case RTL_GIGA_MAC_VER_22
:
4738 case RTL_GIGA_MAC_VER_23
:
4739 case RTL_GIGA_MAC_VER_24
:
4740 case RTL_GIGA_MAC_VER_25
:
4741 case RTL_GIGA_MAC_VER_26
:
4742 case RTL_GIGA_MAC_VER_27
:
4743 case RTL_GIGA_MAC_VER_28
:
4744 case RTL_GIGA_MAC_VER_31
:
4745 rtl_writephy(tp
, 0x0e, 0x0000);
4750 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
4753 static void r8168_phy_power_down(struct rtl8169_private
*tp
)
4755 rtl_writephy(tp
, 0x1f, 0x0000);
4756 switch (tp
->mac_version
) {
4757 case RTL_GIGA_MAC_VER_32
:
4758 case RTL_GIGA_MAC_VER_33
:
4759 case RTL_GIGA_MAC_VER_40
:
4760 case RTL_GIGA_MAC_VER_41
:
4761 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
| BMCR_PDOWN
);
4764 case RTL_GIGA_MAC_VER_11
:
4765 case RTL_GIGA_MAC_VER_12
:
4766 case RTL_GIGA_MAC_VER_17
:
4767 case RTL_GIGA_MAC_VER_18
:
4768 case RTL_GIGA_MAC_VER_19
:
4769 case RTL_GIGA_MAC_VER_20
:
4770 case RTL_GIGA_MAC_VER_21
:
4771 case RTL_GIGA_MAC_VER_22
:
4772 case RTL_GIGA_MAC_VER_23
:
4773 case RTL_GIGA_MAC_VER_24
:
4774 case RTL_GIGA_MAC_VER_25
:
4775 case RTL_GIGA_MAC_VER_26
:
4776 case RTL_GIGA_MAC_VER_27
:
4777 case RTL_GIGA_MAC_VER_28
:
4778 case RTL_GIGA_MAC_VER_31
:
4779 rtl_writephy(tp
, 0x0e, 0x0200);
4781 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
4786 static void r8168_pll_power_down(struct rtl8169_private
*tp
)
4788 void __iomem
*ioaddr
= tp
->mmio_addr
;
4790 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
4791 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
4792 tp
->mac_version
== RTL_GIGA_MAC_VER_31
||
4793 tp
->mac_version
== RTL_GIGA_MAC_VER_49
||
4794 tp
->mac_version
== RTL_GIGA_MAC_VER_50
||
4795 tp
->mac_version
== RTL_GIGA_MAC_VER_51
) &&
4796 r8168_check_dash(tp
)) {
4800 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_23
||
4801 tp
->mac_version
== RTL_GIGA_MAC_VER_24
) &&
4802 (RTL_R16(CPlusCmd
) & ASF
)) {
4806 if (tp
->mac_version
== RTL_GIGA_MAC_VER_32
||
4807 tp
->mac_version
== RTL_GIGA_MAC_VER_33
)
4808 rtl_ephy_write(tp
, 0x19, 0xff64);
4810 if (rtl_wol_pll_power_down(tp
))
4813 r8168_phy_power_down(tp
);
4815 switch (tp
->mac_version
) {
4816 case RTL_GIGA_MAC_VER_25
:
4817 case RTL_GIGA_MAC_VER_26
:
4818 case RTL_GIGA_MAC_VER_27
:
4819 case RTL_GIGA_MAC_VER_28
:
4820 case RTL_GIGA_MAC_VER_31
:
4821 case RTL_GIGA_MAC_VER_32
:
4822 case RTL_GIGA_MAC_VER_33
:
4823 case RTL_GIGA_MAC_VER_44
:
4824 case RTL_GIGA_MAC_VER_45
:
4825 case RTL_GIGA_MAC_VER_46
:
4826 case RTL_GIGA_MAC_VER_50
:
4827 case RTL_GIGA_MAC_VER_51
:
4828 RTL_W8(PMCH
, RTL_R8(PMCH
) & ~0x80);
4830 case RTL_GIGA_MAC_VER_40
:
4831 case RTL_GIGA_MAC_VER_41
:
4832 case RTL_GIGA_MAC_VER_49
:
4833 rtl_w0w1_eri(tp
, 0x1a8, ERIAR_MASK_1111
, 0x00000000,
4834 0xfc000000, ERIAR_EXGMAC
);
4835 RTL_W8(PMCH
, RTL_R8(PMCH
) & ~0x80);
4840 static void r8168_pll_power_up(struct rtl8169_private
*tp
)
4842 void __iomem
*ioaddr
= tp
->mmio_addr
;
4844 switch (tp
->mac_version
) {
4845 case RTL_GIGA_MAC_VER_25
:
4846 case RTL_GIGA_MAC_VER_26
:
4847 case RTL_GIGA_MAC_VER_27
:
4848 case RTL_GIGA_MAC_VER_28
:
4849 case RTL_GIGA_MAC_VER_31
:
4850 case RTL_GIGA_MAC_VER_32
:
4851 case RTL_GIGA_MAC_VER_33
:
4852 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0x80);
4854 case RTL_GIGA_MAC_VER_44
:
4855 case RTL_GIGA_MAC_VER_45
:
4856 case RTL_GIGA_MAC_VER_46
:
4857 case RTL_GIGA_MAC_VER_50
:
4858 case RTL_GIGA_MAC_VER_51
:
4859 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0xc0);
4861 case RTL_GIGA_MAC_VER_40
:
4862 case RTL_GIGA_MAC_VER_41
:
4863 case RTL_GIGA_MAC_VER_49
:
4864 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0xc0);
4865 rtl_w0w1_eri(tp
, 0x1a8, ERIAR_MASK_1111
, 0xfc000000,
4866 0x00000000, ERIAR_EXGMAC
);
4870 r8168_phy_power_up(tp
);
4873 static void rtl_generic_op(struct rtl8169_private
*tp
,
4874 void (*op
)(struct rtl8169_private
*))
4880 static void rtl_pll_power_down(struct rtl8169_private
*tp
)
4882 rtl_generic_op(tp
, tp
->pll_power_ops
.down
);
4885 static void rtl_pll_power_up(struct rtl8169_private
*tp
)
4887 rtl_generic_op(tp
, tp
->pll_power_ops
.up
);
4890 static void rtl_init_pll_power_ops(struct rtl8169_private
*tp
)
4892 struct pll_power_ops
*ops
= &tp
->pll_power_ops
;
4894 switch (tp
->mac_version
) {
4895 case RTL_GIGA_MAC_VER_07
:
4896 case RTL_GIGA_MAC_VER_08
:
4897 case RTL_GIGA_MAC_VER_09
:
4898 case RTL_GIGA_MAC_VER_10
:
4899 case RTL_GIGA_MAC_VER_16
:
4900 case RTL_GIGA_MAC_VER_29
:
4901 case RTL_GIGA_MAC_VER_30
:
4902 case RTL_GIGA_MAC_VER_37
:
4903 case RTL_GIGA_MAC_VER_39
:
4904 case RTL_GIGA_MAC_VER_43
:
4905 case RTL_GIGA_MAC_VER_47
:
4906 case RTL_GIGA_MAC_VER_48
:
4907 ops
->down
= r810x_pll_power_down
;
4908 ops
->up
= r810x_pll_power_up
;
4911 case RTL_GIGA_MAC_VER_11
:
4912 case RTL_GIGA_MAC_VER_12
:
4913 case RTL_GIGA_MAC_VER_17
:
4914 case RTL_GIGA_MAC_VER_18
:
4915 case RTL_GIGA_MAC_VER_19
:
4916 case RTL_GIGA_MAC_VER_20
:
4917 case RTL_GIGA_MAC_VER_21
:
4918 case RTL_GIGA_MAC_VER_22
:
4919 case RTL_GIGA_MAC_VER_23
:
4920 case RTL_GIGA_MAC_VER_24
:
4921 case RTL_GIGA_MAC_VER_25
:
4922 case RTL_GIGA_MAC_VER_26
:
4923 case RTL_GIGA_MAC_VER_27
:
4924 case RTL_GIGA_MAC_VER_28
:
4925 case RTL_GIGA_MAC_VER_31
:
4926 case RTL_GIGA_MAC_VER_32
:
4927 case RTL_GIGA_MAC_VER_33
:
4928 case RTL_GIGA_MAC_VER_34
:
4929 case RTL_GIGA_MAC_VER_35
:
4930 case RTL_GIGA_MAC_VER_36
:
4931 case RTL_GIGA_MAC_VER_38
:
4932 case RTL_GIGA_MAC_VER_40
:
4933 case RTL_GIGA_MAC_VER_41
:
4934 case RTL_GIGA_MAC_VER_42
:
4935 case RTL_GIGA_MAC_VER_44
:
4936 case RTL_GIGA_MAC_VER_45
:
4937 case RTL_GIGA_MAC_VER_46
:
4938 case RTL_GIGA_MAC_VER_49
:
4939 case RTL_GIGA_MAC_VER_50
:
4940 case RTL_GIGA_MAC_VER_51
:
4941 ops
->down
= r8168_pll_power_down
;
4942 ops
->up
= r8168_pll_power_up
;
4952 static void rtl_init_rxcfg(struct rtl8169_private
*tp
)
4954 void __iomem
*ioaddr
= tp
->mmio_addr
;
4956 switch (tp
->mac_version
) {
4957 case RTL_GIGA_MAC_VER_01
:
4958 case RTL_GIGA_MAC_VER_02
:
4959 case RTL_GIGA_MAC_VER_03
:
4960 case RTL_GIGA_MAC_VER_04
:
4961 case RTL_GIGA_MAC_VER_05
:
4962 case RTL_GIGA_MAC_VER_06
:
4963 case RTL_GIGA_MAC_VER_10
:
4964 case RTL_GIGA_MAC_VER_11
:
4965 case RTL_GIGA_MAC_VER_12
:
4966 case RTL_GIGA_MAC_VER_13
:
4967 case RTL_GIGA_MAC_VER_14
:
4968 case RTL_GIGA_MAC_VER_15
:
4969 case RTL_GIGA_MAC_VER_16
:
4970 case RTL_GIGA_MAC_VER_17
:
4971 RTL_W32(RxConfig
, RX_FIFO_THRESH
| RX_DMA_BURST
);
4973 case RTL_GIGA_MAC_VER_18
:
4974 case RTL_GIGA_MAC_VER_19
:
4975 case RTL_GIGA_MAC_VER_20
:
4976 case RTL_GIGA_MAC_VER_21
:
4977 case RTL_GIGA_MAC_VER_22
:
4978 case RTL_GIGA_MAC_VER_23
:
4979 case RTL_GIGA_MAC_VER_24
:
4980 case RTL_GIGA_MAC_VER_34
:
4981 case RTL_GIGA_MAC_VER_35
:
4982 RTL_W32(RxConfig
, RX128_INT_EN
| RX_MULTI_EN
| RX_DMA_BURST
);
4984 case RTL_GIGA_MAC_VER_40
:
4985 case RTL_GIGA_MAC_VER_41
:
4986 case RTL_GIGA_MAC_VER_42
:
4987 case RTL_GIGA_MAC_VER_43
:
4988 case RTL_GIGA_MAC_VER_44
:
4989 case RTL_GIGA_MAC_VER_45
:
4990 case RTL_GIGA_MAC_VER_46
:
4991 case RTL_GIGA_MAC_VER_47
:
4992 case RTL_GIGA_MAC_VER_48
:
4993 case RTL_GIGA_MAC_VER_49
:
4994 case RTL_GIGA_MAC_VER_50
:
4995 case RTL_GIGA_MAC_VER_51
:
4996 RTL_W32(RxConfig
, RX128_INT_EN
| RX_MULTI_EN
| RX_DMA_BURST
| RX_EARLY_OFF
);
4999 RTL_W32(RxConfig
, RX128_INT_EN
| RX_DMA_BURST
);
5004 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
5006 tp
->dirty_tx
= tp
->cur_tx
= tp
->cur_rx
= 0;
5009 static void rtl_hw_jumbo_enable(struct rtl8169_private
*tp
)
5011 void __iomem
*ioaddr
= tp
->mmio_addr
;
5013 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
5014 rtl_generic_op(tp
, tp
->jumbo_ops
.enable
);
5015 RTL_W8(Cfg9346
, Cfg9346_Lock
);
5018 static void rtl_hw_jumbo_disable(struct rtl8169_private
*tp
)
5020 void __iomem
*ioaddr
= tp
->mmio_addr
;
5022 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
5023 rtl_generic_op(tp
, tp
->jumbo_ops
.disable
);
5024 RTL_W8(Cfg9346
, Cfg9346_Lock
);
5027 static void r8168c_hw_jumbo_enable(struct rtl8169_private
*tp
)
5029 void __iomem
*ioaddr
= tp
->mmio_addr
;
5031 RTL_W8(Config3
, RTL_R8(Config3
) | Jumbo_En0
);
5032 RTL_W8(Config4
, RTL_R8(Config4
) | Jumbo_En1
);
5033 rtl_tx_performance_tweak(tp
->pci_dev
, PCI_EXP_DEVCTL_READRQ_512B
);
5036 static void r8168c_hw_jumbo_disable(struct rtl8169_private
*tp
)
5038 void __iomem
*ioaddr
= tp
->mmio_addr
;
5040 RTL_W8(Config3
, RTL_R8(Config3
) & ~Jumbo_En0
);
5041 RTL_W8(Config4
, RTL_R8(Config4
) & ~Jumbo_En1
);
5042 rtl_tx_performance_tweak(tp
->pci_dev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5045 static void r8168dp_hw_jumbo_enable(struct rtl8169_private
*tp
)
5047 void __iomem
*ioaddr
= tp
->mmio_addr
;
5049 RTL_W8(Config3
, RTL_R8(Config3
) | Jumbo_En0
);
5052 static void r8168dp_hw_jumbo_disable(struct rtl8169_private
*tp
)
5054 void __iomem
*ioaddr
= tp
->mmio_addr
;
5056 RTL_W8(Config3
, RTL_R8(Config3
) & ~Jumbo_En0
);
5059 static void r8168e_hw_jumbo_enable(struct rtl8169_private
*tp
)
5061 void __iomem
*ioaddr
= tp
->mmio_addr
;
5063 RTL_W8(MaxTxPacketSize
, 0x3f);
5064 RTL_W8(Config3
, RTL_R8(Config3
) | Jumbo_En0
);
5065 RTL_W8(Config4
, RTL_R8(Config4
) | 0x01);
5066 rtl_tx_performance_tweak(tp
->pci_dev
, PCI_EXP_DEVCTL_READRQ_512B
);
5069 static void r8168e_hw_jumbo_disable(struct rtl8169_private
*tp
)
5071 void __iomem
*ioaddr
= tp
->mmio_addr
;
5073 RTL_W8(MaxTxPacketSize
, 0x0c);
5074 RTL_W8(Config3
, RTL_R8(Config3
) & ~Jumbo_En0
);
5075 RTL_W8(Config4
, RTL_R8(Config4
) & ~0x01);
5076 rtl_tx_performance_tweak(tp
->pci_dev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5079 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private
*tp
)
5081 rtl_tx_performance_tweak(tp
->pci_dev
,
5082 PCI_EXP_DEVCTL_READRQ_512B
| PCI_EXP_DEVCTL_NOSNOOP_EN
);
5085 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private
*tp
)
5087 rtl_tx_performance_tweak(tp
->pci_dev
,
5088 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
5091 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private
*tp
)
5093 void __iomem
*ioaddr
= tp
->mmio_addr
;
5095 r8168b_0_hw_jumbo_enable(tp
);
5097 RTL_W8(Config4
, RTL_R8(Config4
) | (1 << 0));
5100 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private
*tp
)
5102 void __iomem
*ioaddr
= tp
->mmio_addr
;
5104 r8168b_0_hw_jumbo_disable(tp
);
5106 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
5109 static void rtl_init_jumbo_ops(struct rtl8169_private
*tp
)
5111 struct jumbo_ops
*ops
= &tp
->jumbo_ops
;
5113 switch (tp
->mac_version
) {
5114 case RTL_GIGA_MAC_VER_11
:
5115 ops
->disable
= r8168b_0_hw_jumbo_disable
;
5116 ops
->enable
= r8168b_0_hw_jumbo_enable
;
5118 case RTL_GIGA_MAC_VER_12
:
5119 case RTL_GIGA_MAC_VER_17
:
5120 ops
->disable
= r8168b_1_hw_jumbo_disable
;
5121 ops
->enable
= r8168b_1_hw_jumbo_enable
;
5123 case RTL_GIGA_MAC_VER_18
: /* Wild guess. Needs info from Realtek. */
5124 case RTL_GIGA_MAC_VER_19
:
5125 case RTL_GIGA_MAC_VER_20
:
5126 case RTL_GIGA_MAC_VER_21
: /* Wild guess. Needs info from Realtek. */
5127 case RTL_GIGA_MAC_VER_22
:
5128 case RTL_GIGA_MAC_VER_23
:
5129 case RTL_GIGA_MAC_VER_24
:
5130 case RTL_GIGA_MAC_VER_25
:
5131 case RTL_GIGA_MAC_VER_26
:
5132 ops
->disable
= r8168c_hw_jumbo_disable
;
5133 ops
->enable
= r8168c_hw_jumbo_enable
;
5135 case RTL_GIGA_MAC_VER_27
:
5136 case RTL_GIGA_MAC_VER_28
:
5137 ops
->disable
= r8168dp_hw_jumbo_disable
;
5138 ops
->enable
= r8168dp_hw_jumbo_enable
;
5140 case RTL_GIGA_MAC_VER_31
: /* Wild guess. Needs info from Realtek. */
5141 case RTL_GIGA_MAC_VER_32
:
5142 case RTL_GIGA_MAC_VER_33
:
5143 case RTL_GIGA_MAC_VER_34
:
5144 ops
->disable
= r8168e_hw_jumbo_disable
;
5145 ops
->enable
= r8168e_hw_jumbo_enable
;
5149 * No action needed for jumbo frames with 8169.
5150 * No jumbo for 810x at all.
5152 case RTL_GIGA_MAC_VER_40
:
5153 case RTL_GIGA_MAC_VER_41
:
5154 case RTL_GIGA_MAC_VER_42
:
5155 case RTL_GIGA_MAC_VER_43
:
5156 case RTL_GIGA_MAC_VER_44
:
5157 case RTL_GIGA_MAC_VER_45
:
5158 case RTL_GIGA_MAC_VER_46
:
5159 case RTL_GIGA_MAC_VER_47
:
5160 case RTL_GIGA_MAC_VER_48
:
5161 case RTL_GIGA_MAC_VER_49
:
5162 case RTL_GIGA_MAC_VER_50
:
5163 case RTL_GIGA_MAC_VER_51
:
5165 ops
->disable
= NULL
;
5171 DECLARE_RTL_COND(rtl_chipcmd_cond
)
5173 void __iomem
*ioaddr
= tp
->mmio_addr
;
5175 return RTL_R8(ChipCmd
) & CmdReset
;
5178 static void rtl_hw_reset(struct rtl8169_private
*tp
)
5180 void __iomem
*ioaddr
= tp
->mmio_addr
;
5182 RTL_W8(ChipCmd
, CmdReset
);
5184 rtl_udelay_loop_wait_low(tp
, &rtl_chipcmd_cond
, 100, 100);
5187 static void rtl_request_uncached_firmware(struct rtl8169_private
*tp
)
5189 struct rtl_fw
*rtl_fw
;
5193 name
= rtl_lookup_firmware_name(tp
);
5195 goto out_no_firmware
;
5197 rtl_fw
= kzalloc(sizeof(*rtl_fw
), GFP_KERNEL
);
5201 rc
= request_firmware(&rtl_fw
->fw
, name
, &tp
->pci_dev
->dev
);
5205 rc
= rtl_check_firmware(tp
, rtl_fw
);
5207 goto err_release_firmware
;
5209 tp
->rtl_fw
= rtl_fw
;
5213 err_release_firmware
:
5214 release_firmware(rtl_fw
->fw
);
5218 netif_warn(tp
, ifup
, tp
->dev
, "unable to load firmware patch %s (%d)\n",
5225 static void rtl_request_firmware(struct rtl8169_private
*tp
)
5227 if (IS_ERR(tp
->rtl_fw
))
5228 rtl_request_uncached_firmware(tp
);
5231 static void rtl_rx_close(struct rtl8169_private
*tp
)
5233 void __iomem
*ioaddr
= tp
->mmio_addr
;
5235 RTL_W32(RxConfig
, RTL_R32(RxConfig
) & ~RX_CONFIG_ACCEPT_MASK
);
5238 DECLARE_RTL_COND(rtl_npq_cond
)
5240 void __iomem
*ioaddr
= tp
->mmio_addr
;
5242 return RTL_R8(TxPoll
) & NPQ
;
5245 DECLARE_RTL_COND(rtl_txcfg_empty_cond
)
5247 void __iomem
*ioaddr
= tp
->mmio_addr
;
5249 return RTL_R32(TxConfig
) & TXCFG_EMPTY
;
5252 static void rtl8169_hw_reset(struct rtl8169_private
*tp
)
5254 void __iomem
*ioaddr
= tp
->mmio_addr
;
5256 /* Disable interrupts */
5257 rtl8169_irq_mask_and_ack(tp
);
5261 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
5262 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
5263 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
5264 rtl_udelay_loop_wait_low(tp
, &rtl_npq_cond
, 20, 42*42);
5265 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
||
5266 tp
->mac_version
== RTL_GIGA_MAC_VER_35
||
5267 tp
->mac_version
== RTL_GIGA_MAC_VER_36
||
5268 tp
->mac_version
== RTL_GIGA_MAC_VER_37
||
5269 tp
->mac_version
== RTL_GIGA_MAC_VER_38
||
5270 tp
->mac_version
== RTL_GIGA_MAC_VER_40
||
5271 tp
->mac_version
== RTL_GIGA_MAC_VER_41
||
5272 tp
->mac_version
== RTL_GIGA_MAC_VER_42
||
5273 tp
->mac_version
== RTL_GIGA_MAC_VER_43
||
5274 tp
->mac_version
== RTL_GIGA_MAC_VER_44
||
5275 tp
->mac_version
== RTL_GIGA_MAC_VER_45
||
5276 tp
->mac_version
== RTL_GIGA_MAC_VER_46
||
5277 tp
->mac_version
== RTL_GIGA_MAC_VER_47
||
5278 tp
->mac_version
== RTL_GIGA_MAC_VER_48
||
5279 tp
->mac_version
== RTL_GIGA_MAC_VER_49
||
5280 tp
->mac_version
== RTL_GIGA_MAC_VER_50
||
5281 tp
->mac_version
== RTL_GIGA_MAC_VER_51
) {
5282 RTL_W8(ChipCmd
, RTL_R8(ChipCmd
) | StopReq
);
5283 rtl_udelay_loop_wait_high(tp
, &rtl_txcfg_empty_cond
, 100, 666);
5285 RTL_W8(ChipCmd
, RTL_R8(ChipCmd
) | StopReq
);
5292 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
5294 void __iomem
*ioaddr
= tp
->mmio_addr
;
5296 /* Set DMA burst size and Interframe Gap Time */
5297 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
5298 (InterFrameGap
<< TxInterFrameGapShift
));
5301 static void rtl_hw_start(struct net_device
*dev
)
5303 struct rtl8169_private
*tp
= netdev_priv(dev
);
5307 rtl_irq_enable_all(tp
);
5310 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
5311 void __iomem
*ioaddr
)
5314 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5315 * register to be written before TxDescAddrLow to work.
5316 * Switching from MMIO to I/O access fixes the issue as well.
5318 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
5319 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_BIT_MASK(32));
5320 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
5321 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_BIT_MASK(32));
5324 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
5328 cmd
= RTL_R16(CPlusCmd
);
5329 RTL_W16(CPlusCmd
, cmd
);
5333 static void rtl_set_rx_max_size(void __iomem
*ioaddr
, unsigned int rx_buf_sz
)
5335 /* Low hurts. Let's disable the filtering. */
5336 RTL_W16(RxMaxSize
, rx_buf_sz
+ 1);
5339 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
5341 static const struct rtl_cfg2_info
{
5346 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
5347 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
5348 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
5349 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
5351 const struct rtl_cfg2_info
*p
= cfg2_info
;
5355 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
5356 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
5357 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
5358 RTL_W32(0x7c, p
->val
);
5364 static void rtl_set_rx_mode(struct net_device
*dev
)
5366 struct rtl8169_private
*tp
= netdev_priv(dev
);
5367 void __iomem
*ioaddr
= tp
->mmio_addr
;
5368 u32 mc_filter
[2]; /* Multicast hash filter */
5372 if (dev
->flags
& IFF_PROMISC
) {
5373 /* Unconditionally log net taps. */
5374 netif_notice(tp
, link
, dev
, "Promiscuous mode enabled\n");
5376 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
5378 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
5379 } else if ((netdev_mc_count(dev
) > multicast_filter_limit
) ||
5380 (dev
->flags
& IFF_ALLMULTI
)) {
5381 /* Too many to filter perfectly -- accept all multicasts. */
5382 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
5383 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
5385 struct netdev_hw_addr
*ha
;
5387 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
5388 mc_filter
[1] = mc_filter
[0] = 0;
5389 netdev_for_each_mc_addr(ha
, dev
) {
5390 int bit_nr
= ether_crc(ETH_ALEN
, ha
->addr
) >> 26;
5391 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
5392 rx_mode
|= AcceptMulticast
;
5396 if (dev
->features
& NETIF_F_RXALL
)
5397 rx_mode
|= (AcceptErr
| AcceptRunt
);
5399 tmp
= (RTL_R32(RxConfig
) & ~RX_CONFIG_ACCEPT_MASK
) | rx_mode
;
5401 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
5402 u32 data
= mc_filter
[0];
5404 mc_filter
[0] = swab32(mc_filter
[1]);
5405 mc_filter
[1] = swab32(data
);
5408 if (tp
->mac_version
== RTL_GIGA_MAC_VER_35
)
5409 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
5411 RTL_W32(MAR0
+ 4, mc_filter
[1]);
5412 RTL_W32(MAR0
+ 0, mc_filter
[0]);
5414 RTL_W32(RxConfig
, tmp
);
5417 static void rtl_hw_start_8169(struct net_device
*dev
)
5419 struct rtl8169_private
*tp
= netdev_priv(dev
);
5420 void __iomem
*ioaddr
= tp
->mmio_addr
;
5421 struct pci_dev
*pdev
= tp
->pci_dev
;
5423 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
5424 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
5425 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
5428 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
5429 if (tp
->mac_version
== RTL_GIGA_MAC_VER_01
||
5430 tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
5431 tp
->mac_version
== RTL_GIGA_MAC_VER_03
||
5432 tp
->mac_version
== RTL_GIGA_MAC_VER_04
)
5433 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
5437 RTL_W8(EarlyTxThres
, NoEarlyTx
);
5439 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
5441 if (tp
->mac_version
== RTL_GIGA_MAC_VER_01
||
5442 tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
5443 tp
->mac_version
== RTL_GIGA_MAC_VER_03
||
5444 tp
->mac_version
== RTL_GIGA_MAC_VER_04
)
5445 rtl_set_rx_tx_config_registers(tp
);
5447 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
5449 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
5450 tp
->mac_version
== RTL_GIGA_MAC_VER_03
) {
5451 dprintk("Set MAC Reg C+CR Offset 0xe0. "
5452 "Bit-3 and bit-14 MUST be 1\n");
5453 tp
->cp_cmd
|= (1 << 14);
5456 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
5458 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
5461 * Undocumented corner. Supposedly:
5462 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5464 RTL_W16(IntrMitigate
, 0x0000);
5466 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
5468 if (tp
->mac_version
!= RTL_GIGA_MAC_VER_01
&&
5469 tp
->mac_version
!= RTL_GIGA_MAC_VER_02
&&
5470 tp
->mac_version
!= RTL_GIGA_MAC_VER_03
&&
5471 tp
->mac_version
!= RTL_GIGA_MAC_VER_04
) {
5472 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
5473 rtl_set_rx_tx_config_registers(tp
);
5476 RTL_W8(Cfg9346
, Cfg9346_Lock
);
5478 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5481 RTL_W32(RxMissed
, 0);
5483 rtl_set_rx_mode(dev
);
5485 /* no early-rx interrupts */
5486 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
5489 static void rtl_csi_write(struct rtl8169_private
*tp
, int addr
, int value
)
5491 if (tp
->csi_ops
.write
)
5492 tp
->csi_ops
.write(tp
, addr
, value
);
5495 static u32
rtl_csi_read(struct rtl8169_private
*tp
, int addr
)
5497 return tp
->csi_ops
.read
? tp
->csi_ops
.read(tp
, addr
) : ~0;
5500 static void rtl_csi_access_enable(struct rtl8169_private
*tp
, u32 bits
)
5504 csi
= rtl_csi_read(tp
, 0x070c) & 0x00ffffff;
5505 rtl_csi_write(tp
, 0x070c, csi
| bits
);
5508 static void rtl_csi_access_enable_1(struct rtl8169_private
*tp
)
5510 rtl_csi_access_enable(tp
, 0x17000000);
5513 static void rtl_csi_access_enable_2(struct rtl8169_private
*tp
)
5515 rtl_csi_access_enable(tp
, 0x27000000);
5518 DECLARE_RTL_COND(rtl_csiar_cond
)
5520 void __iomem
*ioaddr
= tp
->mmio_addr
;
5522 return RTL_R32(CSIAR
) & CSIAR_FLAG
;
5525 static void r8169_csi_write(struct rtl8169_private
*tp
, int addr
, int value
)
5527 void __iomem
*ioaddr
= tp
->mmio_addr
;
5529 RTL_W32(CSIDR
, value
);
5530 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
5531 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
5533 rtl_udelay_loop_wait_low(tp
, &rtl_csiar_cond
, 10, 100);
5536 static u32
r8169_csi_read(struct rtl8169_private
*tp
, int addr
)
5538 void __iomem
*ioaddr
= tp
->mmio_addr
;
5540 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) |
5541 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
5543 return rtl_udelay_loop_wait_high(tp
, &rtl_csiar_cond
, 10, 100) ?
5544 RTL_R32(CSIDR
) : ~0;
5547 static void r8402_csi_write(struct rtl8169_private
*tp
, int addr
, int value
)
5549 void __iomem
*ioaddr
= tp
->mmio_addr
;
5551 RTL_W32(CSIDR
, value
);
5552 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
5553 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
|
5556 rtl_udelay_loop_wait_low(tp
, &rtl_csiar_cond
, 10, 100);
5559 static u32
r8402_csi_read(struct rtl8169_private
*tp
, int addr
)
5561 void __iomem
*ioaddr
= tp
->mmio_addr
;
5563 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) | CSIAR_FUNC_NIC
|
5564 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
5566 return rtl_udelay_loop_wait_high(tp
, &rtl_csiar_cond
, 10, 100) ?
5567 RTL_R32(CSIDR
) : ~0;
5570 static void r8411_csi_write(struct rtl8169_private
*tp
, int addr
, int value
)
5572 void __iomem
*ioaddr
= tp
->mmio_addr
;
5574 RTL_W32(CSIDR
, value
);
5575 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
5576 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
|
5579 rtl_udelay_loop_wait_low(tp
, &rtl_csiar_cond
, 10, 100);
5582 static u32
r8411_csi_read(struct rtl8169_private
*tp
, int addr
)
5584 void __iomem
*ioaddr
= tp
->mmio_addr
;
5586 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) | CSIAR_FUNC_NIC2
|
5587 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
5589 return rtl_udelay_loop_wait_high(tp
, &rtl_csiar_cond
, 10, 100) ?
5590 RTL_R32(CSIDR
) : ~0;
5593 static void rtl_init_csi_ops(struct rtl8169_private
*tp
)
5595 struct csi_ops
*ops
= &tp
->csi_ops
;
5597 switch (tp
->mac_version
) {
5598 case RTL_GIGA_MAC_VER_01
:
5599 case RTL_GIGA_MAC_VER_02
:
5600 case RTL_GIGA_MAC_VER_03
:
5601 case RTL_GIGA_MAC_VER_04
:
5602 case RTL_GIGA_MAC_VER_05
:
5603 case RTL_GIGA_MAC_VER_06
:
5604 case RTL_GIGA_MAC_VER_10
:
5605 case RTL_GIGA_MAC_VER_11
:
5606 case RTL_GIGA_MAC_VER_12
:
5607 case RTL_GIGA_MAC_VER_13
:
5608 case RTL_GIGA_MAC_VER_14
:
5609 case RTL_GIGA_MAC_VER_15
:
5610 case RTL_GIGA_MAC_VER_16
:
5611 case RTL_GIGA_MAC_VER_17
:
5616 case RTL_GIGA_MAC_VER_37
:
5617 case RTL_GIGA_MAC_VER_38
:
5618 ops
->write
= r8402_csi_write
;
5619 ops
->read
= r8402_csi_read
;
5622 case RTL_GIGA_MAC_VER_44
:
5623 ops
->write
= r8411_csi_write
;
5624 ops
->read
= r8411_csi_read
;
5628 ops
->write
= r8169_csi_write
;
5629 ops
->read
= r8169_csi_read
;
5635 unsigned int offset
;
5640 static void rtl_ephy_init(struct rtl8169_private
*tp
, const struct ephy_info
*e
,
5646 w
= (rtl_ephy_read(tp
, e
->offset
) & ~e
->mask
) | e
->bits
;
5647 rtl_ephy_write(tp
, e
->offset
, w
);
5652 static void rtl_disable_clock_request(struct pci_dev
*pdev
)
5654 pcie_capability_clear_word(pdev
, PCI_EXP_LNKCTL
,
5655 PCI_EXP_LNKCTL_CLKREQ_EN
);
5658 static void rtl_enable_clock_request(struct pci_dev
*pdev
)
5660 pcie_capability_set_word(pdev
, PCI_EXP_LNKCTL
,
5661 PCI_EXP_LNKCTL_CLKREQ_EN
);
5664 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private
*tp
, bool enable
)
5666 void __iomem
*ioaddr
= tp
->mmio_addr
;
5669 data
= RTL_R8(Config3
);
5674 data
&= ~Rdy_to_L23
;
5676 RTL_W8(Config3
, data
);
5679 #define R8168_CPCMD_QUIRK_MASK (\
5690 static void rtl_hw_start_8168bb(struct rtl8169_private
*tp
)
5692 void __iomem
*ioaddr
= tp
->mmio_addr
;
5693 struct pci_dev
*pdev
= tp
->pci_dev
;
5695 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
5697 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
5699 if (tp
->dev
->mtu
<= ETH_DATA_LEN
) {
5700 rtl_tx_performance_tweak(pdev
, (0x5 << MAX_READ_REQUEST_SHIFT
) |
5701 PCI_EXP_DEVCTL_NOSNOOP_EN
);
5705 static void rtl_hw_start_8168bef(struct rtl8169_private
*tp
)
5707 void __iomem
*ioaddr
= tp
->mmio_addr
;
5709 rtl_hw_start_8168bb(tp
);
5711 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
5713 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
5716 static void __rtl_hw_start_8168cp(struct rtl8169_private
*tp
)
5718 void __iomem
*ioaddr
= tp
->mmio_addr
;
5719 struct pci_dev
*pdev
= tp
->pci_dev
;
5721 RTL_W8(Config1
, RTL_R8(Config1
) | Speed_down
);
5723 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
5725 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
5726 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5728 rtl_disable_clock_request(pdev
);
5730 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
5733 static void rtl_hw_start_8168cp_1(struct rtl8169_private
*tp
)
5735 static const struct ephy_info e_info_8168cp
[] = {
5736 { 0x01, 0, 0x0001 },
5737 { 0x02, 0x0800, 0x1000 },
5738 { 0x03, 0, 0x0042 },
5739 { 0x06, 0x0080, 0x0000 },
5743 rtl_csi_access_enable_2(tp
);
5745 rtl_ephy_init(tp
, e_info_8168cp
, ARRAY_SIZE(e_info_8168cp
));
5747 __rtl_hw_start_8168cp(tp
);
5750 static void rtl_hw_start_8168cp_2(struct rtl8169_private
*tp
)
5752 void __iomem
*ioaddr
= tp
->mmio_addr
;
5753 struct pci_dev
*pdev
= tp
->pci_dev
;
5755 rtl_csi_access_enable_2(tp
);
5757 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
5759 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
5760 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5762 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
5765 static void rtl_hw_start_8168cp_3(struct rtl8169_private
*tp
)
5767 void __iomem
*ioaddr
= tp
->mmio_addr
;
5768 struct pci_dev
*pdev
= tp
->pci_dev
;
5770 rtl_csi_access_enable_2(tp
);
5772 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
5775 RTL_W8(DBG_REG
, 0x20);
5777 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
5779 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
5780 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5782 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
5785 static void rtl_hw_start_8168c_1(struct rtl8169_private
*tp
)
5787 void __iomem
*ioaddr
= tp
->mmio_addr
;
5788 static const struct ephy_info e_info_8168c_1
[] = {
5789 { 0x02, 0x0800, 0x1000 },
5790 { 0x03, 0, 0x0002 },
5791 { 0x06, 0x0080, 0x0000 }
5794 rtl_csi_access_enable_2(tp
);
5796 RTL_W8(DBG_REG
, 0x06 | FIX_NAK_1
| FIX_NAK_2
);
5798 rtl_ephy_init(tp
, e_info_8168c_1
, ARRAY_SIZE(e_info_8168c_1
));
5800 __rtl_hw_start_8168cp(tp
);
5803 static void rtl_hw_start_8168c_2(struct rtl8169_private
*tp
)
5805 static const struct ephy_info e_info_8168c_2
[] = {
5806 { 0x01, 0, 0x0001 },
5807 { 0x03, 0x0400, 0x0220 }
5810 rtl_csi_access_enable_2(tp
);
5812 rtl_ephy_init(tp
, e_info_8168c_2
, ARRAY_SIZE(e_info_8168c_2
));
5814 __rtl_hw_start_8168cp(tp
);
5817 static void rtl_hw_start_8168c_3(struct rtl8169_private
*tp
)
5819 rtl_hw_start_8168c_2(tp
);
5822 static void rtl_hw_start_8168c_4(struct rtl8169_private
*tp
)
5824 rtl_csi_access_enable_2(tp
);
5826 __rtl_hw_start_8168cp(tp
);
5829 static void rtl_hw_start_8168d(struct rtl8169_private
*tp
)
5831 void __iomem
*ioaddr
= tp
->mmio_addr
;
5832 struct pci_dev
*pdev
= tp
->pci_dev
;
5834 rtl_csi_access_enable_2(tp
);
5836 rtl_disable_clock_request(pdev
);
5838 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
5840 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
5841 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5843 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
5846 static void rtl_hw_start_8168dp(struct rtl8169_private
*tp
)
5848 void __iomem
*ioaddr
= tp
->mmio_addr
;
5849 struct pci_dev
*pdev
= tp
->pci_dev
;
5851 rtl_csi_access_enable_1(tp
);
5853 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
5854 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5856 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
5858 rtl_disable_clock_request(pdev
);
5861 static void rtl_hw_start_8168d_4(struct rtl8169_private
*tp
)
5863 void __iomem
*ioaddr
= tp
->mmio_addr
;
5864 struct pci_dev
*pdev
= tp
->pci_dev
;
5865 static const struct ephy_info e_info_8168d_4
[] = {
5866 { 0x0b, 0x0000, 0x0048 },
5867 { 0x19, 0x0020, 0x0050 },
5868 { 0x0c, 0x0100, 0x0020 }
5871 rtl_csi_access_enable_1(tp
);
5873 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5875 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
5877 rtl_ephy_init(tp
, e_info_8168d_4
, ARRAY_SIZE(e_info_8168d_4
));
5879 rtl_enable_clock_request(pdev
);
5882 static void rtl_hw_start_8168e_1(struct rtl8169_private
*tp
)
5884 void __iomem
*ioaddr
= tp
->mmio_addr
;
5885 struct pci_dev
*pdev
= tp
->pci_dev
;
5886 static const struct ephy_info e_info_8168e_1
[] = {
5887 { 0x00, 0x0200, 0x0100 },
5888 { 0x00, 0x0000, 0x0004 },
5889 { 0x06, 0x0002, 0x0001 },
5890 { 0x06, 0x0000, 0x0030 },
5891 { 0x07, 0x0000, 0x2000 },
5892 { 0x00, 0x0000, 0x0020 },
5893 { 0x03, 0x5800, 0x2000 },
5894 { 0x03, 0x0000, 0x0001 },
5895 { 0x01, 0x0800, 0x1000 },
5896 { 0x07, 0x0000, 0x4000 },
5897 { 0x1e, 0x0000, 0x2000 },
5898 { 0x19, 0xffff, 0xfe6c },
5899 { 0x0a, 0x0000, 0x0040 }
5902 rtl_csi_access_enable_2(tp
);
5904 rtl_ephy_init(tp
, e_info_8168e_1
, ARRAY_SIZE(e_info_8168e_1
));
5906 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
5907 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5909 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
5911 rtl_disable_clock_request(pdev
);
5913 /* Reset tx FIFO pointer */
5914 RTL_W32(MISC
, RTL_R32(MISC
) | TXPLA_RST
);
5915 RTL_W32(MISC
, RTL_R32(MISC
) & ~TXPLA_RST
);
5917 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
5920 static void rtl_hw_start_8168e_2(struct rtl8169_private
*tp
)
5922 void __iomem
*ioaddr
= tp
->mmio_addr
;
5923 struct pci_dev
*pdev
= tp
->pci_dev
;
5924 static const struct ephy_info e_info_8168e_2
[] = {
5925 { 0x09, 0x0000, 0x0080 },
5926 { 0x19, 0x0000, 0x0224 }
5929 rtl_csi_access_enable_1(tp
);
5931 rtl_ephy_init(tp
, e_info_8168e_2
, ARRAY_SIZE(e_info_8168e_2
));
5933 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
5934 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5936 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
5937 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
5938 rtl_eri_write(tp
, 0xc8, ERIAR_MASK_1111
, 0x00100002, ERIAR_EXGMAC
);
5939 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
5940 rtl_eri_write(tp
, 0xcc, ERIAR_MASK_1111
, 0x00000050, ERIAR_EXGMAC
);
5941 rtl_eri_write(tp
, 0xd0, ERIAR_MASK_1111
, 0x07ff0060, ERIAR_EXGMAC
);
5942 rtl_w0w1_eri(tp
, 0x1b0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
5943 rtl_w0w1_eri(tp
, 0x0d4, ERIAR_MASK_0011
, 0x0c00, 0xff00, ERIAR_EXGMAC
);
5945 RTL_W8(MaxTxPacketSize
, EarlySize
);
5947 rtl_disable_clock_request(pdev
);
5949 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
5950 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
5952 /* Adjust EEE LED frequency */
5953 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
5955 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
5956 RTL_W32(MISC
, RTL_R32(MISC
) | PWM_EN
);
5957 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
5960 static void rtl_hw_start_8168f(struct rtl8169_private
*tp
)
5962 void __iomem
*ioaddr
= tp
->mmio_addr
;
5963 struct pci_dev
*pdev
= tp
->pci_dev
;
5965 rtl_csi_access_enable_2(tp
);
5967 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5969 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
5970 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
5971 rtl_eri_write(tp
, 0xc8, ERIAR_MASK_1111
, 0x00100002, ERIAR_EXGMAC
);
5972 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
5973 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01, ERIAR_EXGMAC
);
5974 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00, ERIAR_EXGMAC
);
5975 rtl_w0w1_eri(tp
, 0x1b0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
5976 rtl_w0w1_eri(tp
, 0x1d0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
5977 rtl_eri_write(tp
, 0xcc, ERIAR_MASK_1111
, 0x00000050, ERIAR_EXGMAC
);
5978 rtl_eri_write(tp
, 0xd0, ERIAR_MASK_1111
, 0x00000060, ERIAR_EXGMAC
);
5980 RTL_W8(MaxTxPacketSize
, EarlySize
);
5982 rtl_disable_clock_request(pdev
);
5984 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
5985 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
5986 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
5987 RTL_W32(MISC
, RTL_R32(MISC
) | PWM_EN
);
5988 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
5991 static void rtl_hw_start_8168f_1(struct rtl8169_private
*tp
)
5993 void __iomem
*ioaddr
= tp
->mmio_addr
;
5994 static const struct ephy_info e_info_8168f_1
[] = {
5995 { 0x06, 0x00c0, 0x0020 },
5996 { 0x08, 0x0001, 0x0002 },
5997 { 0x09, 0x0000, 0x0080 },
5998 { 0x19, 0x0000, 0x0224 }
6001 rtl_hw_start_8168f(tp
);
6003 rtl_ephy_init(tp
, e_info_8168f_1
, ARRAY_SIZE(e_info_8168f_1
));
6005 rtl_w0w1_eri(tp
, 0x0d4, ERIAR_MASK_0011
, 0x0c00, 0xff00, ERIAR_EXGMAC
);
6007 /* Adjust EEE LED frequency */
6008 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
6011 static void rtl_hw_start_8411(struct rtl8169_private
*tp
)
6013 static const struct ephy_info e_info_8168f_1
[] = {
6014 { 0x06, 0x00c0, 0x0020 },
6015 { 0x0f, 0xffff, 0x5200 },
6016 { 0x1e, 0x0000, 0x4000 },
6017 { 0x19, 0x0000, 0x0224 }
6020 rtl_hw_start_8168f(tp
);
6021 rtl_pcie_state_l2l3_enable(tp
, false);
6023 rtl_ephy_init(tp
, e_info_8168f_1
, ARRAY_SIZE(e_info_8168f_1
));
6025 rtl_w0w1_eri(tp
, 0x0d4, ERIAR_MASK_0011
, 0x0c00, 0x0000, ERIAR_EXGMAC
);
6028 static void rtl_hw_start_8168g(struct rtl8169_private
*tp
)
6030 void __iomem
*ioaddr
= tp
->mmio_addr
;
6031 struct pci_dev
*pdev
= tp
->pci_dev
;
6033 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
6035 rtl_eri_write(tp
, 0xc8, ERIAR_MASK_0101
, 0x080002, ERIAR_EXGMAC
);
6036 rtl_eri_write(tp
, 0xcc, ERIAR_MASK_0001
, 0x38, ERIAR_EXGMAC
);
6037 rtl_eri_write(tp
, 0xd0, ERIAR_MASK_0001
, 0x48, ERIAR_EXGMAC
);
6038 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
6040 rtl_csi_access_enable_1(tp
);
6042 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
6044 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01, ERIAR_EXGMAC
);
6045 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00, ERIAR_EXGMAC
);
6046 rtl_eri_write(tp
, 0x2f8, ERIAR_MASK_0011
, 0x1d8f, ERIAR_EXGMAC
);
6048 RTL_W32(MISC
, RTL_R32(MISC
) & ~RXDV_GATED_EN
);
6049 RTL_W8(MaxTxPacketSize
, EarlySize
);
6051 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
6052 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
6054 /* Adjust EEE LED frequency */
6055 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
6057 rtl_w0w1_eri(tp
, 0x2fc, ERIAR_MASK_0001
, 0x01, 0x06, ERIAR_EXGMAC
);
6058 rtl_w0w1_eri(tp
, 0x1b0, ERIAR_MASK_0011
, 0x0000, 0x1000, ERIAR_EXGMAC
);
6060 rtl_pcie_state_l2l3_enable(tp
, false);
6063 static void rtl_hw_start_8168g_1(struct rtl8169_private
*tp
)
6065 void __iomem
*ioaddr
= tp
->mmio_addr
;
6066 static const struct ephy_info e_info_8168g_1
[] = {
6067 { 0x00, 0x0000, 0x0008 },
6068 { 0x0c, 0x37d0, 0x0820 },
6069 { 0x1e, 0x0000, 0x0001 },
6070 { 0x19, 0x8000, 0x0000 }
6073 rtl_hw_start_8168g(tp
);
6075 /* disable aspm and clock request before access ephy */
6076 RTL_W8(Config2
, RTL_R8(Config2
) & ~ClkReqEn
);
6077 RTL_W8(Config5
, RTL_R8(Config5
) & ~ASPM_en
);
6078 rtl_ephy_init(tp
, e_info_8168g_1
, ARRAY_SIZE(e_info_8168g_1
));
6081 static void rtl_hw_start_8168g_2(struct rtl8169_private
*tp
)
6083 void __iomem
*ioaddr
= tp
->mmio_addr
;
6084 static const struct ephy_info e_info_8168g_2
[] = {
6085 { 0x00, 0x0000, 0x0008 },
6086 { 0x0c, 0x3df0, 0x0200 },
6087 { 0x19, 0xffff, 0xfc00 },
6088 { 0x1e, 0xffff, 0x20eb }
6091 rtl_hw_start_8168g(tp
);
6093 /* disable aspm and clock request before access ephy */
6094 RTL_W8(Config2
, RTL_R8(Config2
) & ~ClkReqEn
);
6095 RTL_W8(Config5
, RTL_R8(Config5
) & ~ASPM_en
);
6096 rtl_ephy_init(tp
, e_info_8168g_2
, ARRAY_SIZE(e_info_8168g_2
));
6099 static void rtl_hw_start_8411_2(struct rtl8169_private
*tp
)
6101 void __iomem
*ioaddr
= tp
->mmio_addr
;
6102 static const struct ephy_info e_info_8411_2
[] = {
6103 { 0x00, 0x0000, 0x0008 },
6104 { 0x0c, 0x3df0, 0x0200 },
6105 { 0x0f, 0xffff, 0x5200 },
6106 { 0x19, 0x0020, 0x0000 },
6107 { 0x1e, 0x0000, 0x2000 }
6110 rtl_hw_start_8168g(tp
);
6112 /* disable aspm and clock request before access ephy */
6113 RTL_W8(Config2
, RTL_R8(Config2
) & ~ClkReqEn
);
6114 RTL_W8(Config5
, RTL_R8(Config5
) & ~ASPM_en
);
6115 rtl_ephy_init(tp
, e_info_8411_2
, ARRAY_SIZE(e_info_8411_2
));
6118 static void rtl_hw_start_8168h_1(struct rtl8169_private
*tp
)
6120 void __iomem
*ioaddr
= tp
->mmio_addr
;
6121 struct pci_dev
*pdev
= tp
->pci_dev
;
6124 static const struct ephy_info e_info_8168h_1
[] = {
6125 { 0x1e, 0x0800, 0x0001 },
6126 { 0x1d, 0x0000, 0x0800 },
6127 { 0x05, 0xffff, 0x2089 },
6128 { 0x06, 0xffff, 0x5881 },
6129 { 0x04, 0xffff, 0x154a },
6130 { 0x01, 0xffff, 0x068b }
6133 /* disable aspm and clock request before access ephy */
6134 RTL_W8(Config2
, RTL_R8(Config2
) & ~ClkReqEn
);
6135 RTL_W8(Config5
, RTL_R8(Config5
) & ~ASPM_en
);
6136 rtl_ephy_init(tp
, e_info_8168h_1
, ARRAY_SIZE(e_info_8168h_1
));
6138 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
6140 rtl_eri_write(tp
, 0xc8, ERIAR_MASK_0101
, 0x00080002, ERIAR_EXGMAC
);
6141 rtl_eri_write(tp
, 0xcc, ERIAR_MASK_0001
, 0x38, ERIAR_EXGMAC
);
6142 rtl_eri_write(tp
, 0xd0, ERIAR_MASK_0001
, 0x48, ERIAR_EXGMAC
);
6143 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
6145 rtl_csi_access_enable_1(tp
);
6147 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
6149 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01, ERIAR_EXGMAC
);
6150 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00, ERIAR_EXGMAC
);
6152 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_1111
, 0x0010, 0x00, ERIAR_EXGMAC
);
6154 rtl_w0w1_eri(tp
, 0xd4, ERIAR_MASK_1111
, 0x1f00, 0x00, ERIAR_EXGMAC
);
6156 rtl_eri_write(tp
, 0x5f0, ERIAR_MASK_0011
, 0x4f87, ERIAR_EXGMAC
);
6158 RTL_W32(MISC
, RTL_R32(MISC
) & ~RXDV_GATED_EN
);
6159 RTL_W8(MaxTxPacketSize
, EarlySize
);
6161 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
6162 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
6164 /* Adjust EEE LED frequency */
6165 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
6167 RTL_W8(DLLPR
, RTL_R8(DLLPR
) & ~PFM_EN
);
6168 RTL_W8(MISC_1
, RTL_R8(MISC_1
) & ~PFM_D3COLD_EN
);
6170 RTL_W8(DLLPR
, RTL_R8(DLLPR
) & ~TX_10M_PS_EN
);
6172 rtl_w0w1_eri(tp
, 0x1b0, ERIAR_MASK_0011
, 0x0000, 0x1000, ERIAR_EXGMAC
);
6174 rtl_pcie_state_l2l3_enable(tp
, false);
6176 rtl_writephy(tp
, 0x1f, 0x0c42);
6177 rg_saw_cnt
= (rtl_readphy(tp
, 0x13) & 0x3fff);
6178 rtl_writephy(tp
, 0x1f, 0x0000);
6179 if (rg_saw_cnt
> 0) {
6182 sw_cnt_1ms_ini
= 16000000/rg_saw_cnt
;
6183 sw_cnt_1ms_ini
&= 0x0fff;
6184 data
= r8168_mac_ocp_read(tp
, 0xd412);
6186 data
|= sw_cnt_1ms_ini
;
6187 r8168_mac_ocp_write(tp
, 0xd412, data
);
6190 data
= r8168_mac_ocp_read(tp
, 0xe056);
6193 r8168_mac_ocp_write(tp
, 0xe056, data
);
6195 data
= r8168_mac_ocp_read(tp
, 0xe052);
6198 r8168_mac_ocp_write(tp
, 0xe052, data
);
6200 data
= r8168_mac_ocp_read(tp
, 0xe0d6);
6203 r8168_mac_ocp_write(tp
, 0xe0d6, data
);
6205 data
= r8168_mac_ocp_read(tp
, 0xd420);
6208 r8168_mac_ocp_write(tp
, 0xd420, data
);
6210 r8168_mac_ocp_write(tp
, 0xe63e, 0x0001);
6211 r8168_mac_ocp_write(tp
, 0xe63e, 0x0000);
6212 r8168_mac_ocp_write(tp
, 0xc094, 0x0000);
6213 r8168_mac_ocp_write(tp
, 0xc09e, 0x0000);
6216 static void rtl_hw_start_8168ep(struct rtl8169_private
*tp
)
6218 void __iomem
*ioaddr
= tp
->mmio_addr
;
6219 struct pci_dev
*pdev
= tp
->pci_dev
;
6221 rtl8168ep_stop_cmac(tp
);
6223 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
6225 rtl_eri_write(tp
, 0xc8, ERIAR_MASK_0101
, 0x00080002, ERIAR_EXGMAC
);
6226 rtl_eri_write(tp
, 0xcc, ERIAR_MASK_0001
, 0x2f, ERIAR_EXGMAC
);
6227 rtl_eri_write(tp
, 0xd0, ERIAR_MASK_0001
, 0x5f, ERIAR_EXGMAC
);
6228 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
6230 rtl_csi_access_enable_1(tp
);
6232 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
6234 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01, ERIAR_EXGMAC
);
6235 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00, ERIAR_EXGMAC
);
6237 rtl_w0w1_eri(tp
, 0xd4, ERIAR_MASK_1111
, 0x1f80, 0x00, ERIAR_EXGMAC
);
6239 rtl_eri_write(tp
, 0x5f0, ERIAR_MASK_0011
, 0x4f87, ERIAR_EXGMAC
);
6241 RTL_W32(MISC
, RTL_R32(MISC
) & ~RXDV_GATED_EN
);
6242 RTL_W8(MaxTxPacketSize
, EarlySize
);
6244 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
6245 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
6247 /* Adjust EEE LED frequency */
6248 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
6250 rtl_w0w1_eri(tp
, 0x2fc, ERIAR_MASK_0001
, 0x01, 0x06, ERIAR_EXGMAC
);
6252 RTL_W8(DLLPR
, RTL_R8(DLLPR
) & ~TX_10M_PS_EN
);
6254 rtl_pcie_state_l2l3_enable(tp
, false);
6257 static void rtl_hw_start_8168ep_1(struct rtl8169_private
*tp
)
6259 void __iomem
*ioaddr
= tp
->mmio_addr
;
6260 static const struct ephy_info e_info_8168ep_1
[] = {
6261 { 0x00, 0xffff, 0x10ab },
6262 { 0x06, 0xffff, 0xf030 },
6263 { 0x08, 0xffff, 0x2006 },
6264 { 0x0d, 0xffff, 0x1666 },
6265 { 0x0c, 0x3ff0, 0x0000 }
6268 /* disable aspm and clock request before access ephy */
6269 RTL_W8(Config2
, RTL_R8(Config2
) & ~ClkReqEn
);
6270 RTL_W8(Config5
, RTL_R8(Config5
) & ~ASPM_en
);
6271 rtl_ephy_init(tp
, e_info_8168ep_1
, ARRAY_SIZE(e_info_8168ep_1
));
6273 rtl_hw_start_8168ep(tp
);
6276 static void rtl_hw_start_8168ep_2(struct rtl8169_private
*tp
)
6278 void __iomem
*ioaddr
= tp
->mmio_addr
;
6279 static const struct ephy_info e_info_8168ep_2
[] = {
6280 { 0x00, 0xffff, 0x10a3 },
6281 { 0x19, 0xffff, 0xfc00 },
6282 { 0x1e, 0xffff, 0x20ea }
6285 /* disable aspm and clock request before access ephy */
6286 RTL_W8(Config2
, RTL_R8(Config2
) & ~ClkReqEn
);
6287 RTL_W8(Config5
, RTL_R8(Config5
) & ~ASPM_en
);
6288 rtl_ephy_init(tp
, e_info_8168ep_2
, ARRAY_SIZE(e_info_8168ep_2
));
6290 rtl_hw_start_8168ep(tp
);
6292 RTL_W8(DLLPR
, RTL_R8(DLLPR
) & ~PFM_EN
);
6293 RTL_W8(MISC_1
, RTL_R8(MISC_1
) & ~PFM_D3COLD_EN
);
6296 static void rtl_hw_start_8168ep_3(struct rtl8169_private
*tp
)
6298 void __iomem
*ioaddr
= tp
->mmio_addr
;
6300 static const struct ephy_info e_info_8168ep_3
[] = {
6301 { 0x00, 0xffff, 0x10a3 },
6302 { 0x19, 0xffff, 0x7c00 },
6303 { 0x1e, 0xffff, 0x20eb },
6304 { 0x0d, 0xffff, 0x1666 }
6307 /* disable aspm and clock request before access ephy */
6308 RTL_W8(Config2
, RTL_R8(Config2
) & ~ClkReqEn
);
6309 RTL_W8(Config5
, RTL_R8(Config5
) & ~ASPM_en
);
6310 rtl_ephy_init(tp
, e_info_8168ep_3
, ARRAY_SIZE(e_info_8168ep_3
));
6312 rtl_hw_start_8168ep(tp
);
6314 RTL_W8(DLLPR
, RTL_R8(DLLPR
) & ~PFM_EN
);
6315 RTL_W8(MISC_1
, RTL_R8(MISC_1
) & ~PFM_D3COLD_EN
);
6317 data
= r8168_mac_ocp_read(tp
, 0xd3e2);
6320 r8168_mac_ocp_write(tp
, 0xd3e2, data
);
6322 data
= r8168_mac_ocp_read(tp
, 0xd3e4);
6324 r8168_mac_ocp_write(tp
, 0xd3e4, data
);
6326 data
= r8168_mac_ocp_read(tp
, 0xe860);
6328 r8168_mac_ocp_write(tp
, 0xe860, data
);
6331 static void rtl_hw_start_8168(struct net_device
*dev
)
6333 struct rtl8169_private
*tp
= netdev_priv(dev
);
6334 void __iomem
*ioaddr
= tp
->mmio_addr
;
6336 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
6338 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
6340 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
6342 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
6344 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
6346 RTL_W16(IntrMitigate
, 0x5151);
6348 /* Work around for RxFIFO overflow. */
6349 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
) {
6350 tp
->event_slow
|= RxFIFOOver
| PCSTimeout
;
6351 tp
->event_slow
&= ~RxOverflow
;
6354 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
6356 rtl_set_rx_tx_config_registers(tp
);
6360 switch (tp
->mac_version
) {
6361 case RTL_GIGA_MAC_VER_11
:
6362 rtl_hw_start_8168bb(tp
);
6365 case RTL_GIGA_MAC_VER_12
:
6366 case RTL_GIGA_MAC_VER_17
:
6367 rtl_hw_start_8168bef(tp
);
6370 case RTL_GIGA_MAC_VER_18
:
6371 rtl_hw_start_8168cp_1(tp
);
6374 case RTL_GIGA_MAC_VER_19
:
6375 rtl_hw_start_8168c_1(tp
);
6378 case RTL_GIGA_MAC_VER_20
:
6379 rtl_hw_start_8168c_2(tp
);
6382 case RTL_GIGA_MAC_VER_21
:
6383 rtl_hw_start_8168c_3(tp
);
6386 case RTL_GIGA_MAC_VER_22
:
6387 rtl_hw_start_8168c_4(tp
);
6390 case RTL_GIGA_MAC_VER_23
:
6391 rtl_hw_start_8168cp_2(tp
);
6394 case RTL_GIGA_MAC_VER_24
:
6395 rtl_hw_start_8168cp_3(tp
);
6398 case RTL_GIGA_MAC_VER_25
:
6399 case RTL_GIGA_MAC_VER_26
:
6400 case RTL_GIGA_MAC_VER_27
:
6401 rtl_hw_start_8168d(tp
);
6404 case RTL_GIGA_MAC_VER_28
:
6405 rtl_hw_start_8168d_4(tp
);
6408 case RTL_GIGA_MAC_VER_31
:
6409 rtl_hw_start_8168dp(tp
);
6412 case RTL_GIGA_MAC_VER_32
:
6413 case RTL_GIGA_MAC_VER_33
:
6414 rtl_hw_start_8168e_1(tp
);
6416 case RTL_GIGA_MAC_VER_34
:
6417 rtl_hw_start_8168e_2(tp
);
6420 case RTL_GIGA_MAC_VER_35
:
6421 case RTL_GIGA_MAC_VER_36
:
6422 rtl_hw_start_8168f_1(tp
);
6425 case RTL_GIGA_MAC_VER_38
:
6426 rtl_hw_start_8411(tp
);
6429 case RTL_GIGA_MAC_VER_40
:
6430 case RTL_GIGA_MAC_VER_41
:
6431 rtl_hw_start_8168g_1(tp
);
6433 case RTL_GIGA_MAC_VER_42
:
6434 rtl_hw_start_8168g_2(tp
);
6437 case RTL_GIGA_MAC_VER_44
:
6438 rtl_hw_start_8411_2(tp
);
6441 case RTL_GIGA_MAC_VER_45
:
6442 case RTL_GIGA_MAC_VER_46
:
6443 rtl_hw_start_8168h_1(tp
);
6446 case RTL_GIGA_MAC_VER_49
:
6447 rtl_hw_start_8168ep_1(tp
);
6450 case RTL_GIGA_MAC_VER_50
:
6451 rtl_hw_start_8168ep_2(tp
);
6454 case RTL_GIGA_MAC_VER_51
:
6455 rtl_hw_start_8168ep_3(tp
);
6459 printk(KERN_ERR PFX
"%s: unknown chipset (mac_version = %d).\n",
6460 dev
->name
, tp
->mac_version
);
6464 RTL_W8(Cfg9346
, Cfg9346_Lock
);
6466 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
6468 rtl_set_rx_mode(dev
);
6470 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
6473 #define R810X_CPCMD_QUIRK_MASK (\
6484 static void rtl_hw_start_8102e_1(struct rtl8169_private
*tp
)
6486 void __iomem
*ioaddr
= tp
->mmio_addr
;
6487 struct pci_dev
*pdev
= tp
->pci_dev
;
6488 static const struct ephy_info e_info_8102e_1
[] = {
6489 { 0x01, 0, 0x6e65 },
6490 { 0x02, 0, 0x091f },
6491 { 0x03, 0, 0xc2f9 },
6492 { 0x06, 0, 0xafb5 },
6493 { 0x07, 0, 0x0e00 },
6494 { 0x19, 0, 0xec80 },
6495 { 0x01, 0, 0x2e65 },
6500 rtl_csi_access_enable_2(tp
);
6502 RTL_W8(DBG_REG
, FIX_NAK_1
);
6504 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
6507 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
6508 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
6510 cfg1
= RTL_R8(Config1
);
6511 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
6512 RTL_W8(Config1
, cfg1
& ~LEDS0
);
6514 rtl_ephy_init(tp
, e_info_8102e_1
, ARRAY_SIZE(e_info_8102e_1
));
6517 static void rtl_hw_start_8102e_2(struct rtl8169_private
*tp
)
6519 void __iomem
*ioaddr
= tp
->mmio_addr
;
6520 struct pci_dev
*pdev
= tp
->pci_dev
;
6522 rtl_csi_access_enable_2(tp
);
6524 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
6526 RTL_W8(Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
6527 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
6530 static void rtl_hw_start_8102e_3(struct rtl8169_private
*tp
)
6532 rtl_hw_start_8102e_2(tp
);
6534 rtl_ephy_write(tp
, 0x03, 0xc2f9);
6537 static void rtl_hw_start_8105e_1(struct rtl8169_private
*tp
)
6539 void __iomem
*ioaddr
= tp
->mmio_addr
;
6540 static const struct ephy_info e_info_8105e_1
[] = {
6541 { 0x07, 0, 0x4000 },
6542 { 0x19, 0, 0x0200 },
6543 { 0x19, 0, 0x0020 },
6544 { 0x1e, 0, 0x2000 },
6545 { 0x03, 0, 0x0001 },
6546 { 0x19, 0, 0x0100 },
6547 { 0x19, 0, 0x0004 },
6551 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6552 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) | 0x002800);
6554 /* Disable Early Tally Counter */
6555 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) & ~0x010000);
6557 RTL_W8(MCU
, RTL_R8(MCU
) | EN_NDP
| EN_OOB_RESET
);
6558 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
6560 rtl_ephy_init(tp
, e_info_8105e_1
, ARRAY_SIZE(e_info_8105e_1
));
6562 rtl_pcie_state_l2l3_enable(tp
, false);
6565 static void rtl_hw_start_8105e_2(struct rtl8169_private
*tp
)
6567 rtl_hw_start_8105e_1(tp
);
6568 rtl_ephy_write(tp
, 0x1e, rtl_ephy_read(tp
, 0x1e) | 0x8000);
6571 static void rtl_hw_start_8402(struct rtl8169_private
*tp
)
6573 void __iomem
*ioaddr
= tp
->mmio_addr
;
6574 static const struct ephy_info e_info_8402
[] = {
6575 { 0x19, 0xffff, 0xff64 },
6579 rtl_csi_access_enable_2(tp
);
6581 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6582 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) | 0x002800);
6584 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
6585 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
6587 rtl_ephy_init(tp
, e_info_8402
, ARRAY_SIZE(e_info_8402
));
6589 rtl_tx_performance_tweak(tp
->pci_dev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
6591 rtl_eri_write(tp
, 0xc8, ERIAR_MASK_1111
, 0x00000002, ERIAR_EXGMAC
);
6592 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_1111
, 0x00000006, ERIAR_EXGMAC
);
6593 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01, ERIAR_EXGMAC
);
6594 rtl_w0w1_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00, ERIAR_EXGMAC
);
6595 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
6596 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
6597 rtl_w0w1_eri(tp
, 0x0d4, ERIAR_MASK_0011
, 0x0e00, 0xff00, ERIAR_EXGMAC
);
6599 rtl_pcie_state_l2l3_enable(tp
, false);
6602 static void rtl_hw_start_8106(struct rtl8169_private
*tp
)
6604 void __iomem
*ioaddr
= tp
->mmio_addr
;
6606 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6607 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) | 0x002800);
6609 RTL_W32(MISC
, (RTL_R32(MISC
) | DISABLE_LAN_EN
) & ~EARLY_TALLY_EN
);
6610 RTL_W8(MCU
, RTL_R8(MCU
) | EN_NDP
| EN_OOB_RESET
);
6611 RTL_W8(DLLPR
, RTL_R8(DLLPR
) & ~PFM_EN
);
6613 rtl_pcie_state_l2l3_enable(tp
, false);
6616 static void rtl_hw_start_8101(struct net_device
*dev
)
6618 struct rtl8169_private
*tp
= netdev_priv(dev
);
6619 void __iomem
*ioaddr
= tp
->mmio_addr
;
6620 struct pci_dev
*pdev
= tp
->pci_dev
;
6622 if (tp
->mac_version
>= RTL_GIGA_MAC_VER_30
)
6623 tp
->event_slow
&= ~RxFIFOOver
;
6625 if (tp
->mac_version
== RTL_GIGA_MAC_VER_13
||
6626 tp
->mac_version
== RTL_GIGA_MAC_VER_16
)
6627 pcie_capability_set_word(pdev
, PCI_EXP_DEVCTL
,
6628 PCI_EXP_DEVCTL_NOSNOOP_EN
);
6630 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
6632 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
6634 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
6636 tp
->cp_cmd
&= ~R810X_CPCMD_QUIRK_MASK
;
6637 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
6639 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
6641 rtl_set_rx_tx_config_registers(tp
);
6643 switch (tp
->mac_version
) {
6644 case RTL_GIGA_MAC_VER_07
:
6645 rtl_hw_start_8102e_1(tp
);
6648 case RTL_GIGA_MAC_VER_08
:
6649 rtl_hw_start_8102e_3(tp
);
6652 case RTL_GIGA_MAC_VER_09
:
6653 rtl_hw_start_8102e_2(tp
);
6656 case RTL_GIGA_MAC_VER_29
:
6657 rtl_hw_start_8105e_1(tp
);
6659 case RTL_GIGA_MAC_VER_30
:
6660 rtl_hw_start_8105e_2(tp
);
6663 case RTL_GIGA_MAC_VER_37
:
6664 rtl_hw_start_8402(tp
);
6667 case RTL_GIGA_MAC_VER_39
:
6668 rtl_hw_start_8106(tp
);
6670 case RTL_GIGA_MAC_VER_43
:
6671 rtl_hw_start_8168g_2(tp
);
6673 case RTL_GIGA_MAC_VER_47
:
6674 case RTL_GIGA_MAC_VER_48
:
6675 rtl_hw_start_8168h_1(tp
);
6679 RTL_W8(Cfg9346
, Cfg9346_Lock
);
6681 RTL_W16(IntrMitigate
, 0x0000);
6683 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
6685 rtl_set_rx_mode(dev
);
6689 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
6692 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
6694 struct rtl8169_private
*tp
= netdev_priv(dev
);
6696 if (new_mtu
> ETH_DATA_LEN
)
6697 rtl_hw_jumbo_enable(tp
);
6699 rtl_hw_jumbo_disable(tp
);
6702 netdev_update_features(dev
);
6707 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
6709 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
6710 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
6713 static void rtl8169_free_rx_databuff(struct rtl8169_private
*tp
,
6714 void **data_buff
, struct RxDesc
*desc
)
6716 dma_unmap_single(&tp
->pci_dev
->dev
, le64_to_cpu(desc
->addr
), rx_buf_sz
,
6721 rtl8169_make_unusable_by_asic(desc
);
6724 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
6726 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
6728 /* Force memory writes to complete before releasing descriptor */
6731 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
6734 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
6737 desc
->addr
= cpu_to_le64(mapping
);
6738 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
6741 static inline void *rtl8169_align(void *data
)
6743 return (void *)ALIGN((long)data
, 16);
6746 static struct sk_buff
*rtl8169_alloc_rx_data(struct rtl8169_private
*tp
,
6747 struct RxDesc
*desc
)
6751 struct device
*d
= &tp
->pci_dev
->dev
;
6752 struct net_device
*dev
= tp
->dev
;
6753 int node
= dev
->dev
.parent
? dev_to_node(dev
->dev
.parent
) : -1;
6755 data
= kmalloc_node(rx_buf_sz
, GFP_KERNEL
, node
);
6759 if (rtl8169_align(data
) != data
) {
6761 data
= kmalloc_node(rx_buf_sz
+ 15, GFP_KERNEL
, node
);
6766 mapping
= dma_map_single(d
, rtl8169_align(data
), rx_buf_sz
,
6768 if (unlikely(dma_mapping_error(d
, mapping
))) {
6769 if (net_ratelimit())
6770 netif_err(tp
, drv
, tp
->dev
, "Failed to map RX DMA!\n");
6774 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
6782 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
6786 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
6787 if (tp
->Rx_databuff
[i
]) {
6788 rtl8169_free_rx_databuff(tp
, tp
->Rx_databuff
+ i
,
6789 tp
->RxDescArray
+ i
);
6794 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
6796 desc
->opts1
|= cpu_to_le32(RingEnd
);
6799 static int rtl8169_rx_fill(struct rtl8169_private
*tp
)
6803 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
6806 if (tp
->Rx_databuff
[i
])
6809 data
= rtl8169_alloc_rx_data(tp
, tp
->RxDescArray
+ i
);
6811 rtl8169_make_unusable_by_asic(tp
->RxDescArray
+ i
);
6814 tp
->Rx_databuff
[i
] = data
;
6817 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
6821 rtl8169_rx_clear(tp
);
6825 static int rtl8169_init_ring(struct net_device
*dev
)
6827 struct rtl8169_private
*tp
= netdev_priv(dev
);
6829 rtl8169_init_ring_indexes(tp
);
6831 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
6832 memset(tp
->Rx_databuff
, 0x0, NUM_RX_DESC
* sizeof(void *));
6834 return rtl8169_rx_fill(tp
);
6837 static void rtl8169_unmap_tx_skb(struct device
*d
, struct ring_info
*tx_skb
,
6838 struct TxDesc
*desc
)
6840 unsigned int len
= tx_skb
->len
;
6842 dma_unmap_single(d
, le64_to_cpu(desc
->addr
), len
, DMA_TO_DEVICE
);
6850 static void rtl8169_tx_clear_range(struct rtl8169_private
*tp
, u32 start
,
6855 for (i
= 0; i
< n
; i
++) {
6856 unsigned int entry
= (start
+ i
) % NUM_TX_DESC
;
6857 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
6858 unsigned int len
= tx_skb
->len
;
6861 struct sk_buff
*skb
= tx_skb
->skb
;
6863 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
6864 tp
->TxDescArray
+ entry
);
6866 tp
->dev
->stats
.tx_dropped
++;
6867 dev_kfree_skb_any(skb
);
6874 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
6876 rtl8169_tx_clear_range(tp
, tp
->dirty_tx
, NUM_TX_DESC
);
6877 tp
->cur_tx
= tp
->dirty_tx
= 0;
6880 static void rtl_reset_work(struct rtl8169_private
*tp
)
6882 struct net_device
*dev
= tp
->dev
;
6885 napi_disable(&tp
->napi
);
6886 netif_stop_queue(dev
);
6887 synchronize_sched();
6889 rtl8169_hw_reset(tp
);
6891 for (i
= 0; i
< NUM_RX_DESC
; i
++)
6892 rtl8169_mark_to_asic(tp
->RxDescArray
+ i
, rx_buf_sz
);
6894 rtl8169_tx_clear(tp
);
6895 rtl8169_init_ring_indexes(tp
);
6897 napi_enable(&tp
->napi
);
6899 netif_wake_queue(dev
);
6900 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
6903 static void rtl8169_tx_timeout(struct net_device
*dev
)
6905 struct rtl8169_private
*tp
= netdev_priv(dev
);
6907 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
6910 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
6913 struct skb_shared_info
*info
= skb_shinfo(skb
);
6914 unsigned int cur_frag
, entry
;
6915 struct TxDesc
*uninitialized_var(txd
);
6916 struct device
*d
= &tp
->pci_dev
->dev
;
6919 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
6920 const skb_frag_t
*frag
= info
->frags
+ cur_frag
;
6925 entry
= (entry
+ 1) % NUM_TX_DESC
;
6927 txd
= tp
->TxDescArray
+ entry
;
6928 len
= skb_frag_size(frag
);
6929 addr
= skb_frag_address(frag
);
6930 mapping
= dma_map_single(d
, addr
, len
, DMA_TO_DEVICE
);
6931 if (unlikely(dma_mapping_error(d
, mapping
))) {
6932 if (net_ratelimit())
6933 netif_err(tp
, drv
, tp
->dev
,
6934 "Failed to map TX fragments DMA!\n");
6938 /* Anti gcc 2.95.3 bugware (sic) */
6939 status
= opts
[0] | len
|
6940 (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
6942 txd
->opts1
= cpu_to_le32(status
);
6943 txd
->opts2
= cpu_to_le32(opts
[1]);
6944 txd
->addr
= cpu_to_le64(mapping
);
6946 tp
->tx_skb
[entry
].len
= len
;
6950 tp
->tx_skb
[entry
].skb
= skb
;
6951 txd
->opts1
|= cpu_to_le32(LastFrag
);
6957 rtl8169_tx_clear_range(tp
, tp
->cur_tx
+ 1, cur_frag
);
6961 static bool rtl_test_hw_pad_bug(struct rtl8169_private
*tp
, struct sk_buff
*skb
)
6963 return skb
->len
< ETH_ZLEN
&& tp
->mac_version
== RTL_GIGA_MAC_VER_34
;
6966 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
6967 struct net_device
*dev
);
6968 /* r8169_csum_workaround()
6969 * The hw limites the value the transport offset. When the offset is out of the
6970 * range, calculate the checksum by sw.
6972 static void r8169_csum_workaround(struct rtl8169_private
*tp
,
6973 struct sk_buff
*skb
)
6975 if (skb_shinfo(skb
)->gso_size
) {
6976 netdev_features_t features
= tp
->dev
->features
;
6977 struct sk_buff
*segs
, *nskb
;
6979 features
&= ~(NETIF_F_SG
| NETIF_F_IPV6_CSUM
| NETIF_F_TSO6
);
6980 segs
= skb_gso_segment(skb
, features
);
6981 if (IS_ERR(segs
) || !segs
)
6988 rtl8169_start_xmit(nskb
, tp
->dev
);
6991 dev_consume_skb_any(skb
);
6992 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
6993 if (skb_checksum_help(skb
) < 0)
6996 rtl8169_start_xmit(skb
, tp
->dev
);
6998 struct net_device_stats
*stats
;
7001 stats
= &tp
->dev
->stats
;
7002 stats
->tx_dropped
++;
7003 dev_kfree_skb_any(skb
);
7007 /* msdn_giant_send_check()
7008 * According to the document of microsoft, the TCP Pseudo Header excludes the
7009 * packet length for IPv6 TCP large packets.
7011 static int msdn_giant_send_check(struct sk_buff
*skb
)
7013 const struct ipv6hdr
*ipv6h
;
7017 ret
= skb_cow_head(skb
, 0);
7021 ipv6h
= ipv6_hdr(skb
);
7025 th
->check
= ~tcp_v6_check(0, &ipv6h
->saddr
, &ipv6h
->daddr
, 0);
7030 static inline __be16
get_protocol(struct sk_buff
*skb
)
7034 if (skb
->protocol
== htons(ETH_P_8021Q
))
7035 protocol
= vlan_eth_hdr(skb
)->h_vlan_encapsulated_proto
;
7037 protocol
= skb
->protocol
;
7042 static bool rtl8169_tso_csum_v1(struct rtl8169_private
*tp
,
7043 struct sk_buff
*skb
, u32
*opts
)
7045 u32 mss
= skb_shinfo(skb
)->gso_size
;
7049 opts
[0] |= min(mss
, TD_MSS_MAX
) << TD0_MSS_SHIFT
;
7050 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
7051 const struct iphdr
*ip
= ip_hdr(skb
);
7053 if (ip
->protocol
== IPPROTO_TCP
)
7054 opts
[0] |= TD0_IP_CS
| TD0_TCP_CS
;
7055 else if (ip
->protocol
== IPPROTO_UDP
)
7056 opts
[0] |= TD0_IP_CS
| TD0_UDP_CS
;
7064 static bool rtl8169_tso_csum_v2(struct rtl8169_private
*tp
,
7065 struct sk_buff
*skb
, u32
*opts
)
7067 u32 transport_offset
= (u32
)skb_transport_offset(skb
);
7068 u32 mss
= skb_shinfo(skb
)->gso_size
;
7071 if (transport_offset
> GTTCPHO_MAX
) {
7072 netif_warn(tp
, tx_err
, tp
->dev
,
7073 "Invalid transport offset 0x%x for TSO\n",
7078 switch (get_protocol(skb
)) {
7079 case htons(ETH_P_IP
):
7080 opts
[0] |= TD1_GTSENV4
;
7083 case htons(ETH_P_IPV6
):
7084 if (msdn_giant_send_check(skb
))
7087 opts
[0] |= TD1_GTSENV6
;
7095 opts
[0] |= transport_offset
<< GTTCPHO_SHIFT
;
7096 opts
[1] |= min(mss
, TD_MSS_MAX
) << TD1_MSS_SHIFT
;
7097 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
7100 if (unlikely(rtl_test_hw_pad_bug(tp
, skb
)))
7101 return !(skb_checksum_help(skb
) || eth_skb_pad(skb
));
7103 if (transport_offset
> TCPHO_MAX
) {
7104 netif_warn(tp
, tx_err
, tp
->dev
,
7105 "Invalid transport offset 0x%x\n",
7110 switch (get_protocol(skb
)) {
7111 case htons(ETH_P_IP
):
7112 opts
[1] |= TD1_IPv4_CS
;
7113 ip_protocol
= ip_hdr(skb
)->protocol
;
7116 case htons(ETH_P_IPV6
):
7117 opts
[1] |= TD1_IPv6_CS
;
7118 ip_protocol
= ipv6_hdr(skb
)->nexthdr
;
7122 ip_protocol
= IPPROTO_RAW
;
7126 if (ip_protocol
== IPPROTO_TCP
)
7127 opts
[1] |= TD1_TCP_CS
;
7128 else if (ip_protocol
== IPPROTO_UDP
)
7129 opts
[1] |= TD1_UDP_CS
;
7133 opts
[1] |= transport_offset
<< TCPHO_SHIFT
;
7135 if (unlikely(rtl_test_hw_pad_bug(tp
, skb
)))
7136 return !eth_skb_pad(skb
);
7142 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
7143 struct net_device
*dev
)
7145 struct rtl8169_private
*tp
= netdev_priv(dev
);
7146 unsigned int entry
= tp
->cur_tx
% NUM_TX_DESC
;
7147 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
7148 void __iomem
*ioaddr
= tp
->mmio_addr
;
7149 struct device
*d
= &tp
->pci_dev
->dev
;
7155 if (unlikely(!TX_FRAGS_READY_FOR(tp
, skb_shinfo(skb
)->nr_frags
))) {
7156 netif_err(tp
, drv
, dev
, "BUG! Tx Ring full when queue awake!\n");
7160 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
7163 opts
[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb
));
7166 if (!tp
->tso_csum(tp
, skb
, opts
)) {
7167 r8169_csum_workaround(tp
, skb
);
7168 return NETDEV_TX_OK
;
7171 len
= skb_headlen(skb
);
7172 mapping
= dma_map_single(d
, skb
->data
, len
, DMA_TO_DEVICE
);
7173 if (unlikely(dma_mapping_error(d
, mapping
))) {
7174 if (net_ratelimit())
7175 netif_err(tp
, drv
, dev
, "Failed to map TX DMA!\n");
7179 tp
->tx_skb
[entry
].len
= len
;
7180 txd
->addr
= cpu_to_le64(mapping
);
7182 frags
= rtl8169_xmit_frags(tp
, skb
, opts
);
7186 opts
[0] |= FirstFrag
;
7188 opts
[0] |= FirstFrag
| LastFrag
;
7189 tp
->tx_skb
[entry
].skb
= skb
;
7192 txd
->opts2
= cpu_to_le32(opts
[1]);
7194 skb_tx_timestamp(skb
);
7196 /* Force memory writes to complete before releasing descriptor */
7199 /* Anti gcc 2.95.3 bugware (sic) */
7200 status
= opts
[0] | len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
7201 txd
->opts1
= cpu_to_le32(status
);
7203 /* Force all memory writes to complete before notifying device */
7206 tp
->cur_tx
+= frags
+ 1;
7208 RTL_W8(TxPoll
, NPQ
);
7212 if (!TX_FRAGS_READY_FOR(tp
, MAX_SKB_FRAGS
)) {
7213 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7214 * not miss a ring update when it notices a stopped queue.
7217 netif_stop_queue(dev
);
7218 /* Sync with rtl_tx:
7219 * - publish queue status and cur_tx ring index (write barrier)
7220 * - refresh dirty_tx ring index (read barrier).
7221 * May the current thread have a pessimistic view of the ring
7222 * status and forget to wake up queue, a racing rtl_tx thread
7226 if (TX_FRAGS_READY_FOR(tp
, MAX_SKB_FRAGS
))
7227 netif_wake_queue(dev
);
7230 return NETDEV_TX_OK
;
7233 rtl8169_unmap_tx_skb(d
, tp
->tx_skb
+ entry
, txd
);
7235 dev_kfree_skb_any(skb
);
7236 dev
->stats
.tx_dropped
++;
7237 return NETDEV_TX_OK
;
7240 netif_stop_queue(dev
);
7241 dev
->stats
.tx_dropped
++;
7242 return NETDEV_TX_BUSY
;
7245 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
7247 struct rtl8169_private
*tp
= netdev_priv(dev
);
7248 struct pci_dev
*pdev
= tp
->pci_dev
;
7249 u16 pci_status
, pci_cmd
;
7251 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
7252 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
7254 netif_err(tp
, intr
, dev
, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7255 pci_cmd
, pci_status
);
7258 * The recovery sequence below admits a very elaborated explanation:
7259 * - it seems to work;
7260 * - I did not see what else could be done;
7261 * - it makes iop3xx happy.
7263 * Feel free to adjust to your needs.
7265 if (pdev
->broken_parity_status
)
7266 pci_cmd
&= ~PCI_COMMAND_PARITY
;
7268 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
7270 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
7272 pci_write_config_word(pdev
, PCI_STATUS
,
7273 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
7274 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
7275 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
7277 /* The infamous DAC f*ckup only happens at boot time */
7278 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->cur_rx
) {
7279 void __iomem
*ioaddr
= tp
->mmio_addr
;
7281 netif_info(tp
, intr
, dev
, "disabling PCI DAC\n");
7282 tp
->cp_cmd
&= ~PCIDAC
;
7283 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
7284 dev
->features
&= ~NETIF_F_HIGHDMA
;
7287 rtl8169_hw_reset(tp
);
7289 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
7292 static void rtl_tx(struct net_device
*dev
, struct rtl8169_private
*tp
)
7294 unsigned int dirty_tx
, tx_left
;
7296 dirty_tx
= tp
->dirty_tx
;
7298 tx_left
= tp
->cur_tx
- dirty_tx
;
7300 while (tx_left
> 0) {
7301 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
7302 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
7305 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
7306 if (status
& DescOwn
)
7309 /* This barrier is needed to keep us from reading
7310 * any other fields out of the Tx descriptor until
7311 * we know the status of DescOwn
7315 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
7316 tp
->TxDescArray
+ entry
);
7317 if (status
& LastFrag
) {
7318 u64_stats_update_begin(&tp
->tx_stats
.syncp
);
7319 tp
->tx_stats
.packets
++;
7320 tp
->tx_stats
.bytes
+= tx_skb
->skb
->len
;
7321 u64_stats_update_end(&tp
->tx_stats
.syncp
);
7322 dev_kfree_skb_any(tx_skb
->skb
);
7329 if (tp
->dirty_tx
!= dirty_tx
) {
7330 tp
->dirty_tx
= dirty_tx
;
7331 /* Sync with rtl8169_start_xmit:
7332 * - publish dirty_tx ring index (write barrier)
7333 * - refresh cur_tx ring index and queue status (read barrier)
7334 * May the current thread miss the stopped queue condition,
7335 * a racing xmit thread can only have a right view of the
7339 if (netif_queue_stopped(dev
) &&
7340 TX_FRAGS_READY_FOR(tp
, MAX_SKB_FRAGS
)) {
7341 netif_wake_queue(dev
);
7344 * 8168 hack: TxPoll requests are lost when the Tx packets are
7345 * too close. Let's kick an extra TxPoll request when a burst
7346 * of start_xmit activity is detected (if it is not detected,
7347 * it is slow enough). -- FR
7349 if (tp
->cur_tx
!= dirty_tx
) {
7350 void __iomem
*ioaddr
= tp
->mmio_addr
;
7352 RTL_W8(TxPoll
, NPQ
);
7357 static inline int rtl8169_fragmented_frame(u32 status
)
7359 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
7362 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, u32 opts1
)
7364 u32 status
= opts1
& RxProtoMask
;
7366 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
7367 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)))
7368 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
7370 skb_checksum_none_assert(skb
);
7373 static struct sk_buff
*rtl8169_try_rx_copy(void *data
,
7374 struct rtl8169_private
*tp
,
7378 struct sk_buff
*skb
;
7379 struct device
*d
= &tp
->pci_dev
->dev
;
7381 data
= rtl8169_align(data
);
7382 dma_sync_single_for_cpu(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
7384 skb
= napi_alloc_skb(&tp
->napi
, pkt_size
);
7386 memcpy(skb
->data
, data
, pkt_size
);
7387 dma_sync_single_for_device(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
7392 static int rtl_rx(struct net_device
*dev
, struct rtl8169_private
*tp
, u32 budget
)
7394 unsigned int cur_rx
, rx_left
;
7397 cur_rx
= tp
->cur_rx
;
7399 for (rx_left
= min(budget
, NUM_RX_DESC
); rx_left
> 0; rx_left
--, cur_rx
++) {
7400 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
7401 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
7404 status
= le32_to_cpu(desc
->opts1
) & tp
->opts1_mask
;
7405 if (status
& DescOwn
)
7408 /* This barrier is needed to keep us from reading
7409 * any other fields out of the Rx descriptor until
7410 * we know the status of DescOwn
7414 if (unlikely(status
& RxRES
)) {
7415 netif_info(tp
, rx_err
, dev
, "Rx ERROR. status = %08x\n",
7417 dev
->stats
.rx_errors
++;
7418 if (status
& (RxRWT
| RxRUNT
))
7419 dev
->stats
.rx_length_errors
++;
7421 dev
->stats
.rx_crc_errors
++;
7422 if (status
& RxFOVF
) {
7423 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
7424 dev
->stats
.rx_fifo_errors
++;
7426 if ((status
& (RxRUNT
| RxCRC
)) &&
7427 !(status
& (RxRWT
| RxFOVF
)) &&
7428 (dev
->features
& NETIF_F_RXALL
))
7431 struct sk_buff
*skb
;
7436 addr
= le64_to_cpu(desc
->addr
);
7437 if (likely(!(dev
->features
& NETIF_F_RXFCS
)))
7438 pkt_size
= (status
& 0x00003fff) - 4;
7440 pkt_size
= status
& 0x00003fff;
7443 * The driver does not support incoming fragmented
7444 * frames. They are seen as a symptom of over-mtu
7447 if (unlikely(rtl8169_fragmented_frame(status
))) {
7448 dev
->stats
.rx_dropped
++;
7449 dev
->stats
.rx_length_errors
++;
7450 goto release_descriptor
;
7453 skb
= rtl8169_try_rx_copy(tp
->Rx_databuff
[entry
],
7454 tp
, pkt_size
, addr
);
7456 dev
->stats
.rx_dropped
++;
7457 goto release_descriptor
;
7460 rtl8169_rx_csum(skb
, status
);
7461 skb_put(skb
, pkt_size
);
7462 skb
->protocol
= eth_type_trans(skb
, dev
);
7464 rtl8169_rx_vlan_tag(desc
, skb
);
7466 if (skb
->pkt_type
== PACKET_MULTICAST
)
7467 dev
->stats
.multicast
++;
7469 napi_gro_receive(&tp
->napi
, skb
);
7471 u64_stats_update_begin(&tp
->rx_stats
.syncp
);
7472 tp
->rx_stats
.packets
++;
7473 tp
->rx_stats
.bytes
+= pkt_size
;
7474 u64_stats_update_end(&tp
->rx_stats
.syncp
);
7478 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
7481 count
= cur_rx
- tp
->cur_rx
;
7482 tp
->cur_rx
= cur_rx
;
7487 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
7489 struct net_device
*dev
= dev_instance
;
7490 struct rtl8169_private
*tp
= netdev_priv(dev
);
7494 status
= rtl_get_events(tp
);
7495 if (status
&& status
!= 0xffff) {
7496 status
&= RTL_EVENT_NAPI
| tp
->event_slow
;
7500 rtl_irq_disable(tp
);
7501 napi_schedule(&tp
->napi
);
7504 return IRQ_RETVAL(handled
);
7508 * Workqueue context.
7510 static void rtl_slow_event_work(struct rtl8169_private
*tp
)
7512 struct net_device
*dev
= tp
->dev
;
7515 status
= rtl_get_events(tp
) & tp
->event_slow
;
7516 rtl_ack_events(tp
, status
);
7518 if (unlikely(status
& RxFIFOOver
)) {
7519 switch (tp
->mac_version
) {
7520 /* Work around for rx fifo overflow */
7521 case RTL_GIGA_MAC_VER_11
:
7522 netif_stop_queue(dev
);
7523 /* XXX - Hack alert. See rtl_task(). */
7524 set_bit(RTL_FLAG_TASK_RESET_PENDING
, tp
->wk
.flags
);
7530 if (unlikely(status
& SYSErr
))
7531 rtl8169_pcierr_interrupt(dev
);
7533 if (status
& LinkChg
)
7534 __rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
, true);
7536 rtl_irq_enable_all(tp
);
7539 static void rtl_task(struct work_struct
*work
)
7541 static const struct {
7543 void (*action
)(struct rtl8169_private
*);
7545 /* XXX - keep rtl_slow_event_work() as first element. */
7546 { RTL_FLAG_TASK_SLOW_PENDING
, rtl_slow_event_work
},
7547 { RTL_FLAG_TASK_RESET_PENDING
, rtl_reset_work
},
7548 { RTL_FLAG_TASK_PHY_PENDING
, rtl_phy_work
}
7550 struct rtl8169_private
*tp
=
7551 container_of(work
, struct rtl8169_private
, wk
.work
);
7552 struct net_device
*dev
= tp
->dev
;
7557 if (!netif_running(dev
) ||
7558 !test_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
))
7561 for (i
= 0; i
< ARRAY_SIZE(rtl_work
); i
++) {
7564 pending
= test_and_clear_bit(rtl_work
[i
].bitnr
, tp
->wk
.flags
);
7566 rtl_work
[i
].action(tp
);
7570 rtl_unlock_work(tp
);
7573 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
7575 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
7576 struct net_device
*dev
= tp
->dev
;
7577 u16 enable_mask
= RTL_EVENT_NAPI
| tp
->event_slow
;
7581 status
= rtl_get_events(tp
);
7582 rtl_ack_events(tp
, status
& ~tp
->event_slow
);
7584 if (status
& RTL_EVENT_NAPI_RX
)
7585 work_done
= rtl_rx(dev
, tp
, (u32
) budget
);
7587 if (status
& RTL_EVENT_NAPI_TX
)
7590 if (status
& tp
->event_slow
) {
7591 enable_mask
&= ~tp
->event_slow
;
7593 rtl_schedule_task(tp
, RTL_FLAG_TASK_SLOW_PENDING
);
7596 if (work_done
< budget
) {
7597 napi_complete_done(napi
, work_done
);
7599 rtl_irq_enable(tp
, enable_mask
);
7606 static void rtl8169_rx_missed(struct net_device
*dev
, void __iomem
*ioaddr
)
7608 struct rtl8169_private
*tp
= netdev_priv(dev
);
7610 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
7613 dev
->stats
.rx_missed_errors
+= (RTL_R32(RxMissed
) & 0xffffff);
7614 RTL_W32(RxMissed
, 0);
7617 static void rtl8169_down(struct net_device
*dev
)
7619 struct rtl8169_private
*tp
= netdev_priv(dev
);
7620 void __iomem
*ioaddr
= tp
->mmio_addr
;
7622 del_timer_sync(&tp
->timer
);
7624 napi_disable(&tp
->napi
);
7625 netif_stop_queue(dev
);
7627 rtl8169_hw_reset(tp
);
7629 * At this point device interrupts can not be enabled in any function,
7630 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7631 * and napi is disabled (rtl8169_poll).
7633 rtl8169_rx_missed(dev
, ioaddr
);
7635 /* Give a racing hard_start_xmit a few cycles to complete. */
7636 synchronize_sched();
7638 rtl8169_tx_clear(tp
);
7640 rtl8169_rx_clear(tp
);
7642 rtl_pll_power_down(tp
);
7645 static int rtl8169_close(struct net_device
*dev
)
7647 struct rtl8169_private
*tp
= netdev_priv(dev
);
7648 struct pci_dev
*pdev
= tp
->pci_dev
;
7650 pm_runtime_get_sync(&pdev
->dev
);
7652 /* Update counters before going down */
7653 rtl8169_update_counters(dev
);
7656 clear_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
7659 rtl_unlock_work(tp
);
7661 cancel_work_sync(&tp
->wk
.work
);
7663 free_irq(pdev
->irq
, dev
);
7665 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
7667 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
7669 tp
->TxDescArray
= NULL
;
7670 tp
->RxDescArray
= NULL
;
7672 pm_runtime_put_sync(&pdev
->dev
);
7677 #ifdef CONFIG_NET_POLL_CONTROLLER
7678 static void rtl8169_netpoll(struct net_device
*dev
)
7680 struct rtl8169_private
*tp
= netdev_priv(dev
);
7682 rtl8169_interrupt(tp
->pci_dev
->irq
, dev
);
7686 static int rtl_open(struct net_device
*dev
)
7688 struct rtl8169_private
*tp
= netdev_priv(dev
);
7689 void __iomem
*ioaddr
= tp
->mmio_addr
;
7690 struct pci_dev
*pdev
= tp
->pci_dev
;
7691 int retval
= -ENOMEM
;
7693 pm_runtime_get_sync(&pdev
->dev
);
7696 * Rx and Tx descriptors needs 256 bytes alignment.
7697 * dma_alloc_coherent provides more.
7699 tp
->TxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
,
7700 &tp
->TxPhyAddr
, GFP_KERNEL
);
7701 if (!tp
->TxDescArray
)
7702 goto err_pm_runtime_put
;
7704 tp
->RxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
,
7705 &tp
->RxPhyAddr
, GFP_KERNEL
);
7706 if (!tp
->RxDescArray
)
7709 retval
= rtl8169_init_ring(dev
);
7713 INIT_WORK(&tp
->wk
.work
, rtl_task
);
7717 rtl_request_firmware(tp
);
7719 retval
= request_irq(pdev
->irq
, rtl8169_interrupt
,
7720 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
7723 goto err_release_fw_2
;
7727 set_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
7729 napi_enable(&tp
->napi
);
7731 rtl8169_init_phy(dev
, tp
);
7733 __rtl8169_set_features(dev
, dev
->features
);
7735 rtl_pll_power_up(tp
);
7739 if (!rtl8169_init_counter_offsets(dev
))
7740 netif_warn(tp
, hw
, dev
, "counter reset/update failed\n");
7742 netif_start_queue(dev
);
7744 rtl_unlock_work(tp
);
7746 tp
->saved_wolopts
= 0;
7747 pm_runtime_put_noidle(&pdev
->dev
);
7749 rtl8169_check_link_status(dev
, tp
, ioaddr
);
7754 rtl_release_firmware(tp
);
7755 rtl8169_rx_clear(tp
);
7757 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
7759 tp
->RxDescArray
= NULL
;
7761 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
7763 tp
->TxDescArray
= NULL
;
7765 pm_runtime_put_noidle(&pdev
->dev
);
7770 rtl8169_get_stats64(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
7772 struct rtl8169_private
*tp
= netdev_priv(dev
);
7773 void __iomem
*ioaddr
= tp
->mmio_addr
;
7774 struct pci_dev
*pdev
= tp
->pci_dev
;
7775 struct rtl8169_counters
*counters
= tp
->counters
;
7778 pm_runtime_get_noresume(&pdev
->dev
);
7780 if (netif_running(dev
) && pm_runtime_active(&pdev
->dev
))
7781 rtl8169_rx_missed(dev
, ioaddr
);
7784 start
= u64_stats_fetch_begin_irq(&tp
->rx_stats
.syncp
);
7785 stats
->rx_packets
= tp
->rx_stats
.packets
;
7786 stats
->rx_bytes
= tp
->rx_stats
.bytes
;
7787 } while (u64_stats_fetch_retry_irq(&tp
->rx_stats
.syncp
, start
));
7790 start
= u64_stats_fetch_begin_irq(&tp
->tx_stats
.syncp
);
7791 stats
->tx_packets
= tp
->tx_stats
.packets
;
7792 stats
->tx_bytes
= tp
->tx_stats
.bytes
;
7793 } while (u64_stats_fetch_retry_irq(&tp
->tx_stats
.syncp
, start
));
7795 stats
->rx_dropped
= dev
->stats
.rx_dropped
;
7796 stats
->tx_dropped
= dev
->stats
.tx_dropped
;
7797 stats
->rx_length_errors
= dev
->stats
.rx_length_errors
;
7798 stats
->rx_errors
= dev
->stats
.rx_errors
;
7799 stats
->rx_crc_errors
= dev
->stats
.rx_crc_errors
;
7800 stats
->rx_fifo_errors
= dev
->stats
.rx_fifo_errors
;
7801 stats
->rx_missed_errors
= dev
->stats
.rx_missed_errors
;
7802 stats
->multicast
= dev
->stats
.multicast
;
7805 * Fetch additonal counter values missing in stats collected by driver
7806 * from tally counters.
7808 if (pm_runtime_active(&pdev
->dev
))
7809 rtl8169_update_counters(dev
);
7812 * Subtract values fetched during initalization.
7813 * See rtl8169_init_counter_offsets for a description why we do that.
7815 stats
->tx_errors
= le64_to_cpu(counters
->tx_errors
) -
7816 le64_to_cpu(tp
->tc_offset
.tx_errors
);
7817 stats
->collisions
= le32_to_cpu(counters
->tx_multi_collision
) -
7818 le32_to_cpu(tp
->tc_offset
.tx_multi_collision
);
7819 stats
->tx_aborted_errors
= le16_to_cpu(counters
->tx_aborted
) -
7820 le16_to_cpu(tp
->tc_offset
.tx_aborted
);
7822 pm_runtime_put_noidle(&pdev
->dev
);
7825 static void rtl8169_net_suspend(struct net_device
*dev
)
7827 struct rtl8169_private
*tp
= netdev_priv(dev
);
7829 if (!netif_running(dev
))
7832 netif_device_detach(dev
);
7833 netif_stop_queue(dev
);
7836 napi_disable(&tp
->napi
);
7837 clear_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
7838 rtl_unlock_work(tp
);
7840 rtl_pll_power_down(tp
);
7845 static int rtl8169_suspend(struct device
*device
)
7847 struct pci_dev
*pdev
= to_pci_dev(device
);
7848 struct net_device
*dev
= pci_get_drvdata(pdev
);
7850 rtl8169_net_suspend(dev
);
7855 static void __rtl8169_resume(struct net_device
*dev
)
7857 struct rtl8169_private
*tp
= netdev_priv(dev
);
7859 netif_device_attach(dev
);
7861 rtl_pll_power_up(tp
);
7864 napi_enable(&tp
->napi
);
7865 set_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
7866 rtl_unlock_work(tp
);
7868 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
7871 static int rtl8169_resume(struct device
*device
)
7873 struct pci_dev
*pdev
= to_pci_dev(device
);
7874 struct net_device
*dev
= pci_get_drvdata(pdev
);
7875 struct rtl8169_private
*tp
= netdev_priv(dev
);
7877 rtl8169_init_phy(dev
, tp
);
7879 if (netif_running(dev
))
7880 __rtl8169_resume(dev
);
7885 static int rtl8169_runtime_suspend(struct device
*device
)
7887 struct pci_dev
*pdev
= to_pci_dev(device
);
7888 struct net_device
*dev
= pci_get_drvdata(pdev
);
7889 struct rtl8169_private
*tp
= netdev_priv(dev
);
7891 if (!tp
->TxDescArray
)
7895 tp
->saved_wolopts
= __rtl8169_get_wol(tp
);
7896 __rtl8169_set_wol(tp
, WAKE_ANY
);
7897 rtl_unlock_work(tp
);
7899 rtl8169_net_suspend(dev
);
7901 /* Update counters before going runtime suspend */
7902 rtl8169_rx_missed(dev
, tp
->mmio_addr
);
7903 rtl8169_update_counters(dev
);
7908 static int rtl8169_runtime_resume(struct device
*device
)
7910 struct pci_dev
*pdev
= to_pci_dev(device
);
7911 struct net_device
*dev
= pci_get_drvdata(pdev
);
7912 struct rtl8169_private
*tp
= netdev_priv(dev
);
7913 rtl_rar_set(tp
, dev
->dev_addr
);
7915 if (!tp
->TxDescArray
)
7919 __rtl8169_set_wol(tp
, tp
->saved_wolopts
);
7920 tp
->saved_wolopts
= 0;
7921 rtl_unlock_work(tp
);
7923 rtl8169_init_phy(dev
, tp
);
7925 __rtl8169_resume(dev
);
7930 static int rtl8169_runtime_idle(struct device
*device
)
7932 struct pci_dev
*pdev
= to_pci_dev(device
);
7933 struct net_device
*dev
= pci_get_drvdata(pdev
);
7934 struct rtl8169_private
*tp
= netdev_priv(dev
);
7936 return tp
->TxDescArray
? -EBUSY
: 0;
7939 static const struct dev_pm_ops rtl8169_pm_ops
= {
7940 .suspend
= rtl8169_suspend
,
7941 .resume
= rtl8169_resume
,
7942 .freeze
= rtl8169_suspend
,
7943 .thaw
= rtl8169_resume
,
7944 .poweroff
= rtl8169_suspend
,
7945 .restore
= rtl8169_resume
,
7946 .runtime_suspend
= rtl8169_runtime_suspend
,
7947 .runtime_resume
= rtl8169_runtime_resume
,
7948 .runtime_idle
= rtl8169_runtime_idle
,
7951 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
7953 #else /* !CONFIG_PM */
7955 #define RTL8169_PM_OPS NULL
7957 #endif /* !CONFIG_PM */
7959 static void rtl_wol_shutdown_quirk(struct rtl8169_private
*tp
)
7961 void __iomem
*ioaddr
= tp
->mmio_addr
;
7963 /* WoL fails with 8168b when the receiver is disabled. */
7964 switch (tp
->mac_version
) {
7965 case RTL_GIGA_MAC_VER_11
:
7966 case RTL_GIGA_MAC_VER_12
:
7967 case RTL_GIGA_MAC_VER_17
:
7968 pci_clear_master(tp
->pci_dev
);
7970 RTL_W8(ChipCmd
, CmdRxEnb
);
7979 static void rtl_shutdown(struct pci_dev
*pdev
)
7981 struct net_device
*dev
= pci_get_drvdata(pdev
);
7982 struct rtl8169_private
*tp
= netdev_priv(dev
);
7983 struct device
*d
= &pdev
->dev
;
7985 pm_runtime_get_sync(d
);
7987 rtl8169_net_suspend(dev
);
7989 /* Restore original MAC address */
7990 rtl_rar_set(tp
, dev
->perm_addr
);
7992 rtl8169_hw_reset(tp
);
7994 if (system_state
== SYSTEM_POWER_OFF
) {
7995 if (__rtl8169_get_wol(tp
) & WAKE_ANY
) {
7996 rtl_wol_suspend_quirk(tp
);
7997 rtl_wol_shutdown_quirk(tp
);
8000 pci_wake_from_d3(pdev
, true);
8001 pci_set_power_state(pdev
, PCI_D3hot
);
8004 pm_runtime_put_noidle(d
);
8007 static void rtl_remove_one(struct pci_dev
*pdev
)
8009 struct net_device
*dev
= pci_get_drvdata(pdev
);
8010 struct rtl8169_private
*tp
= netdev_priv(dev
);
8012 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
8013 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
8014 tp
->mac_version
== RTL_GIGA_MAC_VER_31
||
8015 tp
->mac_version
== RTL_GIGA_MAC_VER_49
||
8016 tp
->mac_version
== RTL_GIGA_MAC_VER_50
||
8017 tp
->mac_version
== RTL_GIGA_MAC_VER_51
) &&
8018 r8168_check_dash(tp
)) {
8019 rtl8168_driver_stop(tp
);
8022 netif_napi_del(&tp
->napi
);
8024 unregister_netdev(dev
);
8026 dma_free_coherent(&tp
->pci_dev
->dev
, sizeof(*tp
->counters
),
8027 tp
->counters
, tp
->counters_phys_addr
);
8029 rtl_release_firmware(tp
);
8031 if (pci_dev_run_wake(pdev
))
8032 pm_runtime_get_noresume(&pdev
->dev
);
8034 /* restore original MAC address */
8035 rtl_rar_set(tp
, dev
->perm_addr
);
8037 rtl_disable_msi(pdev
, tp
);
8038 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
8041 static const struct net_device_ops rtl_netdev_ops
= {
8042 .ndo_open
= rtl_open
,
8043 .ndo_stop
= rtl8169_close
,
8044 .ndo_get_stats64
= rtl8169_get_stats64
,
8045 .ndo_start_xmit
= rtl8169_start_xmit
,
8046 .ndo_tx_timeout
= rtl8169_tx_timeout
,
8047 .ndo_validate_addr
= eth_validate_addr
,
8048 .ndo_change_mtu
= rtl8169_change_mtu
,
8049 .ndo_fix_features
= rtl8169_fix_features
,
8050 .ndo_set_features
= rtl8169_set_features
,
8051 .ndo_set_mac_address
= rtl_set_mac_address
,
8052 .ndo_do_ioctl
= rtl8169_ioctl
,
8053 .ndo_set_rx_mode
= rtl_set_rx_mode
,
8054 #ifdef CONFIG_NET_POLL_CONTROLLER
8055 .ndo_poll_controller
= rtl8169_netpoll
,
8060 static const struct rtl_cfg_info
{
8061 void (*hw_start
)(struct net_device
*);
8062 unsigned int region
;
8067 } rtl_cfg_infos
[] = {
8069 .hw_start
= rtl_hw_start_8169
,
8072 .event_slow
= SYSErr
| LinkChg
| RxOverflow
| RxFIFOOver
,
8073 .features
= RTL_FEATURE_GMII
,
8074 .default_ver
= RTL_GIGA_MAC_VER_01
,
8077 .hw_start
= rtl_hw_start_8168
,
8080 .event_slow
= SYSErr
| LinkChg
| RxOverflow
,
8081 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
,
8082 .default_ver
= RTL_GIGA_MAC_VER_11
,
8085 .hw_start
= rtl_hw_start_8101
,
8088 .event_slow
= SYSErr
| LinkChg
| RxOverflow
| RxFIFOOver
|
8090 .features
= RTL_FEATURE_MSI
,
8091 .default_ver
= RTL_GIGA_MAC_VER_13
,
8095 /* Cfg9346_Unlock assumed. */
8096 static unsigned rtl_try_msi(struct rtl8169_private
*tp
,
8097 const struct rtl_cfg_info
*cfg
)
8099 void __iomem
*ioaddr
= tp
->mmio_addr
;
8103 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
8104 if (cfg
->features
& RTL_FEATURE_MSI
) {
8105 if (pci_enable_msi(tp
->pci_dev
)) {
8106 netif_info(tp
, hw
, tp
->dev
, "no MSI. Back to INTx.\n");
8109 msi
= RTL_FEATURE_MSI
;
8112 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
8113 RTL_W8(Config2
, cfg2
);
8117 DECLARE_RTL_COND(rtl_link_list_ready_cond
)
8119 void __iomem
*ioaddr
= tp
->mmio_addr
;
8121 return RTL_R8(MCU
) & LINK_LIST_RDY
;
8124 DECLARE_RTL_COND(rtl_rxtx_empty_cond
)
8126 void __iomem
*ioaddr
= tp
->mmio_addr
;
8128 return (RTL_R8(MCU
) & RXTX_EMPTY
) == RXTX_EMPTY
;
8131 static void rtl_hw_init_8168g(struct rtl8169_private
*tp
)
8133 void __iomem
*ioaddr
= tp
->mmio_addr
;
8136 tp
->ocp_base
= OCP_STD_PHY_BASE
;
8138 RTL_W32(MISC
, RTL_R32(MISC
) | RXDV_GATED_EN
);
8140 if (!rtl_udelay_loop_wait_high(tp
, &rtl_txcfg_empty_cond
, 100, 42))
8143 if (!rtl_udelay_loop_wait_high(tp
, &rtl_rxtx_empty_cond
, 100, 42))
8146 RTL_W8(ChipCmd
, RTL_R8(ChipCmd
) & ~(CmdTxEnb
| CmdRxEnb
));
8148 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
8150 data
= r8168_mac_ocp_read(tp
, 0xe8de);
8152 r8168_mac_ocp_write(tp
, 0xe8de, data
);
8154 if (!rtl_udelay_loop_wait_high(tp
, &rtl_link_list_ready_cond
, 100, 42))
8157 data
= r8168_mac_ocp_read(tp
, 0xe8de);
8159 r8168_mac_ocp_write(tp
, 0xe8de, data
);
8161 if (!rtl_udelay_loop_wait_high(tp
, &rtl_link_list_ready_cond
, 100, 42))
8165 static void rtl_hw_init_8168ep(struct rtl8169_private
*tp
)
8167 rtl8168ep_stop_cmac(tp
);
8168 rtl_hw_init_8168g(tp
);
8171 static void rtl_hw_initialize(struct rtl8169_private
*tp
)
8173 switch (tp
->mac_version
) {
8174 case RTL_GIGA_MAC_VER_40
:
8175 case RTL_GIGA_MAC_VER_41
:
8176 case RTL_GIGA_MAC_VER_42
:
8177 case RTL_GIGA_MAC_VER_43
:
8178 case RTL_GIGA_MAC_VER_44
:
8179 case RTL_GIGA_MAC_VER_45
:
8180 case RTL_GIGA_MAC_VER_46
:
8181 case RTL_GIGA_MAC_VER_47
:
8182 case RTL_GIGA_MAC_VER_48
:
8183 rtl_hw_init_8168g(tp
);
8185 case RTL_GIGA_MAC_VER_49
:
8186 case RTL_GIGA_MAC_VER_50
:
8187 case RTL_GIGA_MAC_VER_51
:
8188 rtl_hw_init_8168ep(tp
);
8195 static int rtl_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
8197 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
8198 const unsigned int region
= cfg
->region
;
8199 struct rtl8169_private
*tp
;
8200 struct mii_if_info
*mii
;
8201 struct net_device
*dev
;
8202 void __iomem
*ioaddr
;
8206 if (netif_msg_drv(&debug
)) {
8207 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
8208 MODULENAME
, RTL8169_VERSION
);
8211 dev
= alloc_etherdev(sizeof (*tp
));
8217 SET_NETDEV_DEV(dev
, &pdev
->dev
);
8218 dev
->netdev_ops
= &rtl_netdev_ops
;
8219 tp
= netdev_priv(dev
);
8222 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
8226 mii
->mdio_read
= rtl_mdio_read
;
8227 mii
->mdio_write
= rtl_mdio_write
;
8228 mii
->phy_id_mask
= 0x1f;
8229 mii
->reg_num_mask
= 0x1f;
8230 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
8232 /* disable ASPM completely as that cause random device stop working
8233 * problems as well as full system hangs for some PCIe devices users */
8234 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
| PCIE_LINK_STATE_L1
|
8235 PCIE_LINK_STATE_CLKPM
);
8237 /* enable device (incl. PCI PM wakeup and hotplug setup) */
8238 rc
= pci_enable_device(pdev
);
8240 netif_err(tp
, probe
, dev
, "enable failure\n");
8241 goto err_out_free_dev_1
;
8244 if (pci_set_mwi(pdev
) < 0)
8245 netif_info(tp
, probe
, dev
, "Mem-Wr-Inval unavailable\n");
8247 /* make sure PCI base addr 1 is MMIO */
8248 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
8249 netif_err(tp
, probe
, dev
,
8250 "region #%d not an MMIO resource, aborting\n",
8256 /* check for weird/broken PCI region reporting */
8257 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
8258 netif_err(tp
, probe
, dev
,
8259 "Invalid PCI region size(s), aborting\n");
8264 rc
= pci_request_regions(pdev
, MODULENAME
);
8266 netif_err(tp
, probe
, dev
, "could not request regions\n");
8270 /* ioremap MMIO region */
8271 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
8273 netif_err(tp
, probe
, dev
, "cannot remap MMIO, aborting\n");
8275 goto err_out_free_res_3
;
8277 tp
->mmio_addr
= ioaddr
;
8279 if (!pci_is_pcie(pdev
))
8280 netif_info(tp
, probe
, dev
, "not PCI Express\n");
8282 /* Identify chip attached to board */
8283 rtl8169_get_mac_version(tp
, dev
, cfg
->default_ver
);
8287 if ((sizeof(dma_addr_t
) > 4) &&
8288 (use_dac
== 1 || (use_dac
== -1 && pci_is_pcie(pdev
) &&
8289 tp
->mac_version
>= RTL_GIGA_MAC_VER_18
)) &&
8290 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) &&
8291 !pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64))) {
8293 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
8294 if (!pci_is_pcie(pdev
))
8295 tp
->cp_cmd
|= PCIDAC
;
8296 dev
->features
|= NETIF_F_HIGHDMA
;
8298 rc
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
8300 netif_err(tp
, probe
, dev
, "DMA configuration failed\n");
8301 goto err_out_unmap_4
;
8307 rtl_irq_disable(tp
);
8309 rtl_hw_initialize(tp
);
8313 rtl_ack_events(tp
, 0xffff);
8315 pci_set_master(pdev
);
8317 rtl_init_mdio_ops(tp
);
8318 rtl_init_pll_power_ops(tp
);
8319 rtl_init_jumbo_ops(tp
);
8320 rtl_init_csi_ops(tp
);
8322 rtl8169_print_mac_version(tp
);
8324 chipset
= tp
->mac_version
;
8325 tp
->txd_version
= rtl_chip_infos
[chipset
].txd_version
;
8327 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
8328 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
8329 RTL_W8(Config5
, RTL_R8(Config5
) & (BWF
| MWF
| UWF
| LanWake
| PMEStatus
));
8330 switch (tp
->mac_version
) {
8331 case RTL_GIGA_MAC_VER_34
:
8332 case RTL_GIGA_MAC_VER_35
:
8333 case RTL_GIGA_MAC_VER_36
:
8334 case RTL_GIGA_MAC_VER_37
:
8335 case RTL_GIGA_MAC_VER_38
:
8336 case RTL_GIGA_MAC_VER_40
:
8337 case RTL_GIGA_MAC_VER_41
:
8338 case RTL_GIGA_MAC_VER_42
:
8339 case RTL_GIGA_MAC_VER_43
:
8340 case RTL_GIGA_MAC_VER_44
:
8341 case RTL_GIGA_MAC_VER_45
:
8342 case RTL_GIGA_MAC_VER_46
:
8343 case RTL_GIGA_MAC_VER_47
:
8344 case RTL_GIGA_MAC_VER_48
:
8345 case RTL_GIGA_MAC_VER_49
:
8346 case RTL_GIGA_MAC_VER_50
:
8347 case RTL_GIGA_MAC_VER_51
:
8348 if (rtl_eri_read(tp
, 0xdc, ERIAR_EXGMAC
) & MagicPacket_v2
)
8349 tp
->features
|= RTL_FEATURE_WOL
;
8350 if ((RTL_R8(Config3
) & LinkUp
) != 0)
8351 tp
->features
|= RTL_FEATURE_WOL
;
8354 if ((RTL_R8(Config3
) & (LinkUp
| MagicPacket
)) != 0)
8355 tp
->features
|= RTL_FEATURE_WOL
;
8358 if ((RTL_R8(Config5
) & (UWF
| BWF
| MWF
)) != 0)
8359 tp
->features
|= RTL_FEATURE_WOL
;
8360 tp
->features
|= rtl_try_msi(tp
, cfg
);
8361 RTL_W8(Cfg9346
, Cfg9346_Lock
);
8363 if (rtl_tbi_enabled(tp
)) {
8364 tp
->set_speed
= rtl8169_set_speed_tbi
;
8365 tp
->get_link_ksettings
= rtl8169_get_link_ksettings_tbi
;
8366 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
8367 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
8368 tp
->link_ok
= rtl8169_tbi_link_ok
;
8369 tp
->do_ioctl
= rtl_tbi_ioctl
;
8371 tp
->set_speed
= rtl8169_set_speed_xmii
;
8372 tp
->get_link_ksettings
= rtl8169_get_link_ksettings_xmii
;
8373 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
8374 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
8375 tp
->link_ok
= rtl8169_xmii_link_ok
;
8376 tp
->do_ioctl
= rtl_xmii_ioctl
;
8379 mutex_init(&tp
->wk
.mutex
);
8380 u64_stats_init(&tp
->rx_stats
.syncp
);
8381 u64_stats_init(&tp
->tx_stats
.syncp
);
8383 /* Get MAC address */
8384 if (tp
->mac_version
== RTL_GIGA_MAC_VER_35
||
8385 tp
->mac_version
== RTL_GIGA_MAC_VER_36
||
8386 tp
->mac_version
== RTL_GIGA_MAC_VER_37
||
8387 tp
->mac_version
== RTL_GIGA_MAC_VER_38
||
8388 tp
->mac_version
== RTL_GIGA_MAC_VER_40
||
8389 tp
->mac_version
== RTL_GIGA_MAC_VER_41
||
8390 tp
->mac_version
== RTL_GIGA_MAC_VER_42
||
8391 tp
->mac_version
== RTL_GIGA_MAC_VER_43
||
8392 tp
->mac_version
== RTL_GIGA_MAC_VER_44
||
8393 tp
->mac_version
== RTL_GIGA_MAC_VER_45
||
8394 tp
->mac_version
== RTL_GIGA_MAC_VER_46
||
8395 tp
->mac_version
== RTL_GIGA_MAC_VER_47
||
8396 tp
->mac_version
== RTL_GIGA_MAC_VER_48
||
8397 tp
->mac_version
== RTL_GIGA_MAC_VER_49
||
8398 tp
->mac_version
== RTL_GIGA_MAC_VER_50
||
8399 tp
->mac_version
== RTL_GIGA_MAC_VER_51
) {
8402 *(u32
*)&mac_addr
[0] = rtl_eri_read(tp
, 0xe0, ERIAR_EXGMAC
);
8403 *(u16
*)&mac_addr
[2] = rtl_eri_read(tp
, 0xe4, ERIAR_EXGMAC
);
8405 if (is_valid_ether_addr((u8
*)mac_addr
))
8406 rtl_rar_set(tp
, (u8
*)mac_addr
);
8408 for (i
= 0; i
< ETH_ALEN
; i
++)
8409 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
8411 dev
->ethtool_ops
= &rtl8169_ethtool_ops
;
8412 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
8414 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, R8169_NAPI_WEIGHT
);
8416 /* don't enable SG, IP_CSUM and TSO by default - it might not work
8417 * properly for all devices */
8418 dev
->features
|= NETIF_F_RXCSUM
|
8419 NETIF_F_HW_VLAN_CTAG_TX
| NETIF_F_HW_VLAN_CTAG_RX
;
8421 dev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
8422 NETIF_F_RXCSUM
| NETIF_F_HW_VLAN_CTAG_TX
|
8423 NETIF_F_HW_VLAN_CTAG_RX
;
8424 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
8427 tp
->cp_cmd
|= RxChkSum
| RxVlan
;
8430 * Pretend we are using VLANs; This bypasses a nasty bug where
8431 * Interrupts stop flowing on high load on 8110SCd controllers.
8433 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
8434 /* Disallow toggling */
8435 dev
->hw_features
&= ~NETIF_F_HW_VLAN_CTAG_RX
;
8437 if (tp
->txd_version
== RTL_TD_0
)
8438 tp
->tso_csum
= rtl8169_tso_csum_v1
;
8439 else if (tp
->txd_version
== RTL_TD_1
) {
8440 tp
->tso_csum
= rtl8169_tso_csum_v2
;
8441 dev
->hw_features
|= NETIF_F_IPV6_CSUM
| NETIF_F_TSO6
;
8445 dev
->hw_features
|= NETIF_F_RXALL
;
8446 dev
->hw_features
|= NETIF_F_RXFCS
;
8448 /* MTU range: 60 - hw-specific max */
8449 dev
->min_mtu
= ETH_ZLEN
;
8450 dev
->max_mtu
= rtl_chip_infos
[chipset
].jumbo_max
;
8452 tp
->hw_start
= cfg
->hw_start
;
8453 tp
->event_slow
= cfg
->event_slow
;
8455 tp
->opts1_mask
= (tp
->mac_version
!= RTL_GIGA_MAC_VER_01
) ?
8456 ~(RxBOVF
| RxFOVF
) : ~0;
8458 setup_timer(&tp
->timer
, rtl8169_phy_timer
, (unsigned long)dev
);
8460 tp
->rtl_fw
= RTL_FIRMWARE_UNKNOWN
;
8462 tp
->counters
= dma_alloc_coherent (&pdev
->dev
, sizeof(*tp
->counters
),
8463 &tp
->counters_phys_addr
, GFP_KERNEL
);
8464 if (!tp
->counters
) {
8469 rc
= register_netdev(dev
);
8473 pci_set_drvdata(pdev
, dev
);
8475 netif_info(tp
, probe
, dev
, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
8476 rtl_chip_infos
[chipset
].name
, ioaddr
, dev
->dev_addr
,
8477 (u32
)(RTL_R32(TxConfig
) & 0x9cf0f8ff), pdev
->irq
);
8478 if (rtl_chip_infos
[chipset
].jumbo_max
!= JUMBO_1K
) {
8479 netif_info(tp
, probe
, dev
, "jumbo features [frames: %d bytes, "
8480 "tx checksumming: %s]\n",
8481 rtl_chip_infos
[chipset
].jumbo_max
,
8482 rtl_chip_infos
[chipset
].jumbo_tx_csum
? "ok" : "ko");
8485 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
8486 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
8487 tp
->mac_version
== RTL_GIGA_MAC_VER_31
||
8488 tp
->mac_version
== RTL_GIGA_MAC_VER_49
||
8489 tp
->mac_version
== RTL_GIGA_MAC_VER_50
||
8490 tp
->mac_version
== RTL_GIGA_MAC_VER_51
) &&
8491 r8168_check_dash(tp
)) {
8492 rtl8168_driver_start(tp
);
8495 device_set_wakeup_enable(&pdev
->dev
, tp
->features
& RTL_FEATURE_WOL
);
8497 if (pci_dev_run_wake(pdev
))
8498 pm_runtime_put_noidle(&pdev
->dev
);
8500 netif_carrier_off(dev
);
8506 dma_free_coherent(&pdev
->dev
, sizeof(*tp
->counters
), tp
->counters
,
8507 tp
->counters_phys_addr
);
8509 netif_napi_del(&tp
->napi
);
8510 rtl_disable_msi(pdev
, tp
);
8514 pci_release_regions(pdev
);
8516 pci_clear_mwi(pdev
);
8517 pci_disable_device(pdev
);
8523 static struct pci_driver rtl8169_pci_driver
= {
8525 .id_table
= rtl8169_pci_tbl
,
8526 .probe
= rtl_init_one
,
8527 .remove
= rtl_remove_one
,
8528 .shutdown
= rtl_shutdown
,
8529 .driver
.pm
= RTL8169_PM_OPS
,
8532 module_pci_driver(rtl8169_pci_driver
);