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Merge tag 'rtc-4.14' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / realtek / r8169.c
1 /*
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28 #include <linux/pci-aspm.h>
29 #include <linux/prefetch.h>
30 #include <linux/ipv6.h>
31 #include <net/ip6_checksum.h>
32
33 #include <asm/io.h>
34 #include <asm/irq.h>
35
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
39
40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
45 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
47 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
48 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
49 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
50 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
51 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
52 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
53 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
54 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
55 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
56 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
57 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
58 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
59
60 #ifdef RTL8169_DEBUG
61 #define assert(expr) \
62 if (!(expr)) { \
63 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
64 #expr,__FILE__,__func__,__LINE__); \
65 }
66 #define dprintk(fmt, args...) \
67 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
68 #else
69 #define assert(expr) do {} while (0)
70 #define dprintk(fmt, args...) do {} while (0)
71 #endif /* RTL8169_DEBUG */
72
73 #define R8169_MSG_DEFAULT \
74 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
75
76 #define TX_SLOTS_AVAIL(tp) \
77 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
78
79 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
80 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
81 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
82
83 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
84 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
85 static const int multicast_filter_limit = 32;
86
87 #define MAX_READ_REQUEST_SHIFT 12
88 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
89 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
90
91 #define R8169_REGS_SIZE 256
92 #define R8169_NAPI_WEIGHT 64
93 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
94 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
95 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
96 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
97
98 #define RTL8169_TX_TIMEOUT (6*HZ)
99 #define RTL8169_PHY_TIMEOUT (10*HZ)
100
101 /* write/read MMIO register */
102 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
103 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
104 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
105 #define RTL_R8(reg) readb (ioaddr + (reg))
106 #define RTL_R16(reg) readw (ioaddr + (reg))
107 #define RTL_R32(reg) readl (ioaddr + (reg))
108
109 enum mac_version {
110 RTL_GIGA_MAC_VER_01 = 0,
111 RTL_GIGA_MAC_VER_02,
112 RTL_GIGA_MAC_VER_03,
113 RTL_GIGA_MAC_VER_04,
114 RTL_GIGA_MAC_VER_05,
115 RTL_GIGA_MAC_VER_06,
116 RTL_GIGA_MAC_VER_07,
117 RTL_GIGA_MAC_VER_08,
118 RTL_GIGA_MAC_VER_09,
119 RTL_GIGA_MAC_VER_10,
120 RTL_GIGA_MAC_VER_11,
121 RTL_GIGA_MAC_VER_12,
122 RTL_GIGA_MAC_VER_13,
123 RTL_GIGA_MAC_VER_14,
124 RTL_GIGA_MAC_VER_15,
125 RTL_GIGA_MAC_VER_16,
126 RTL_GIGA_MAC_VER_17,
127 RTL_GIGA_MAC_VER_18,
128 RTL_GIGA_MAC_VER_19,
129 RTL_GIGA_MAC_VER_20,
130 RTL_GIGA_MAC_VER_21,
131 RTL_GIGA_MAC_VER_22,
132 RTL_GIGA_MAC_VER_23,
133 RTL_GIGA_MAC_VER_24,
134 RTL_GIGA_MAC_VER_25,
135 RTL_GIGA_MAC_VER_26,
136 RTL_GIGA_MAC_VER_27,
137 RTL_GIGA_MAC_VER_28,
138 RTL_GIGA_MAC_VER_29,
139 RTL_GIGA_MAC_VER_30,
140 RTL_GIGA_MAC_VER_31,
141 RTL_GIGA_MAC_VER_32,
142 RTL_GIGA_MAC_VER_33,
143 RTL_GIGA_MAC_VER_34,
144 RTL_GIGA_MAC_VER_35,
145 RTL_GIGA_MAC_VER_36,
146 RTL_GIGA_MAC_VER_37,
147 RTL_GIGA_MAC_VER_38,
148 RTL_GIGA_MAC_VER_39,
149 RTL_GIGA_MAC_VER_40,
150 RTL_GIGA_MAC_VER_41,
151 RTL_GIGA_MAC_VER_42,
152 RTL_GIGA_MAC_VER_43,
153 RTL_GIGA_MAC_VER_44,
154 RTL_GIGA_MAC_VER_45,
155 RTL_GIGA_MAC_VER_46,
156 RTL_GIGA_MAC_VER_47,
157 RTL_GIGA_MAC_VER_48,
158 RTL_GIGA_MAC_VER_49,
159 RTL_GIGA_MAC_VER_50,
160 RTL_GIGA_MAC_VER_51,
161 RTL_GIGA_MAC_NONE = 0xff,
162 };
163
164 enum rtl_tx_desc_version {
165 RTL_TD_0 = 0,
166 RTL_TD_1 = 1,
167 };
168
169 #define JUMBO_1K ETH_DATA_LEN
170 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
171 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
172 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
173 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
174
175 #define _R(NAME,TD,FW,SZ,B) { \
176 .name = NAME, \
177 .txd_version = TD, \
178 .fw_name = FW, \
179 .jumbo_max = SZ, \
180 .jumbo_tx_csum = B \
181 }
182
183 static const struct {
184 const char *name;
185 enum rtl_tx_desc_version txd_version;
186 const char *fw_name;
187 u16 jumbo_max;
188 bool jumbo_tx_csum;
189 } rtl_chip_infos[] = {
190 /* PCI devices. */
191 [RTL_GIGA_MAC_VER_01] =
192 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
193 [RTL_GIGA_MAC_VER_02] =
194 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
195 [RTL_GIGA_MAC_VER_03] =
196 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
197 [RTL_GIGA_MAC_VER_04] =
198 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
199 [RTL_GIGA_MAC_VER_05] =
200 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
201 [RTL_GIGA_MAC_VER_06] =
202 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
203 /* PCI-E devices. */
204 [RTL_GIGA_MAC_VER_07] =
205 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
206 [RTL_GIGA_MAC_VER_08] =
207 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
208 [RTL_GIGA_MAC_VER_09] =
209 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
210 [RTL_GIGA_MAC_VER_10] =
211 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
212 [RTL_GIGA_MAC_VER_11] =
213 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
214 [RTL_GIGA_MAC_VER_12] =
215 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
216 [RTL_GIGA_MAC_VER_13] =
217 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
218 [RTL_GIGA_MAC_VER_14] =
219 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
220 [RTL_GIGA_MAC_VER_15] =
221 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
222 [RTL_GIGA_MAC_VER_16] =
223 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
224 [RTL_GIGA_MAC_VER_17] =
225 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
226 [RTL_GIGA_MAC_VER_18] =
227 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
228 [RTL_GIGA_MAC_VER_19] =
229 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
230 [RTL_GIGA_MAC_VER_20] =
231 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
232 [RTL_GIGA_MAC_VER_21] =
233 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
234 [RTL_GIGA_MAC_VER_22] =
235 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
236 [RTL_GIGA_MAC_VER_23] =
237 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
238 [RTL_GIGA_MAC_VER_24] =
239 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
240 [RTL_GIGA_MAC_VER_25] =
241 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
242 JUMBO_9K, false),
243 [RTL_GIGA_MAC_VER_26] =
244 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
245 JUMBO_9K, false),
246 [RTL_GIGA_MAC_VER_27] =
247 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
248 [RTL_GIGA_MAC_VER_28] =
249 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
250 [RTL_GIGA_MAC_VER_29] =
251 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
252 JUMBO_1K, true),
253 [RTL_GIGA_MAC_VER_30] =
254 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
255 JUMBO_1K, true),
256 [RTL_GIGA_MAC_VER_31] =
257 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
258 [RTL_GIGA_MAC_VER_32] =
259 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
260 JUMBO_9K, false),
261 [RTL_GIGA_MAC_VER_33] =
262 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
263 JUMBO_9K, false),
264 [RTL_GIGA_MAC_VER_34] =
265 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
266 JUMBO_9K, false),
267 [RTL_GIGA_MAC_VER_35] =
268 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
269 JUMBO_9K, false),
270 [RTL_GIGA_MAC_VER_36] =
271 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
272 JUMBO_9K, false),
273 [RTL_GIGA_MAC_VER_37] =
274 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
275 JUMBO_1K, true),
276 [RTL_GIGA_MAC_VER_38] =
277 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
278 JUMBO_9K, false),
279 [RTL_GIGA_MAC_VER_39] =
280 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
281 JUMBO_1K, true),
282 [RTL_GIGA_MAC_VER_40] =
283 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
284 JUMBO_9K, false),
285 [RTL_GIGA_MAC_VER_41] =
286 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
287 [RTL_GIGA_MAC_VER_42] =
288 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
289 JUMBO_9K, false),
290 [RTL_GIGA_MAC_VER_43] =
291 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
292 JUMBO_1K, true),
293 [RTL_GIGA_MAC_VER_44] =
294 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2,
295 JUMBO_9K, false),
296 [RTL_GIGA_MAC_VER_45] =
297 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1,
298 JUMBO_9K, false),
299 [RTL_GIGA_MAC_VER_46] =
300 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2,
301 JUMBO_9K, false),
302 [RTL_GIGA_MAC_VER_47] =
303 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1,
304 JUMBO_1K, false),
305 [RTL_GIGA_MAC_VER_48] =
306 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2,
307 JUMBO_1K, false),
308 [RTL_GIGA_MAC_VER_49] =
309 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
310 JUMBO_9K, false),
311 [RTL_GIGA_MAC_VER_50] =
312 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
313 JUMBO_9K, false),
314 [RTL_GIGA_MAC_VER_51] =
315 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
316 JUMBO_9K, false),
317 };
318 #undef _R
319
320 enum cfg_version {
321 RTL_CFG_0 = 0x00,
322 RTL_CFG_1,
323 RTL_CFG_2
324 };
325
326 static const struct pci_device_id rtl8169_pci_tbl[] = {
327 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
328 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
329 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161), 0, 0, RTL_CFG_1 },
330 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
331 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
332 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
333 { PCI_VENDOR_ID_DLINK, 0x4300,
334 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
335 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
336 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
337 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
338 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
339 { PCI_VENDOR_ID_LINKSYS, 0x1032,
340 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
341 { 0x0001, 0x8168,
342 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
343 {0,},
344 };
345
346 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
347
348 static int rx_buf_sz = 16383;
349 static int use_dac = -1;
350 static struct {
351 u32 msg_enable;
352 } debug = { -1 };
353
354 enum rtl_registers {
355 MAC0 = 0, /* Ethernet hardware address. */
356 MAC4 = 4,
357 MAR0 = 8, /* Multicast filter. */
358 CounterAddrLow = 0x10,
359 CounterAddrHigh = 0x14,
360 TxDescStartAddrLow = 0x20,
361 TxDescStartAddrHigh = 0x24,
362 TxHDescStartAddrLow = 0x28,
363 TxHDescStartAddrHigh = 0x2c,
364 FLASH = 0x30,
365 ERSR = 0x36,
366 ChipCmd = 0x37,
367 TxPoll = 0x38,
368 IntrMask = 0x3c,
369 IntrStatus = 0x3e,
370
371 TxConfig = 0x40,
372 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
373 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
374
375 RxConfig = 0x44,
376 #define RX128_INT_EN (1 << 15) /* 8111c and later */
377 #define RX_MULTI_EN (1 << 14) /* 8111c only */
378 #define RXCFG_FIFO_SHIFT 13
379 /* No threshold before first PCI xfer */
380 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
381 #define RX_EARLY_OFF (1 << 11)
382 #define RXCFG_DMA_SHIFT 8
383 /* Unlimited maximum PCI burst. */
384 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
385
386 RxMissed = 0x4c,
387 Cfg9346 = 0x50,
388 Config0 = 0x51,
389 Config1 = 0x52,
390 Config2 = 0x53,
391 #define PME_SIGNAL (1 << 5) /* 8168c and later */
392
393 Config3 = 0x54,
394 Config4 = 0x55,
395 Config5 = 0x56,
396 MultiIntr = 0x5c,
397 PHYAR = 0x60,
398 PHYstatus = 0x6c,
399 RxMaxSize = 0xda,
400 CPlusCmd = 0xe0,
401 IntrMitigate = 0xe2,
402 RxDescAddrLow = 0xe4,
403 RxDescAddrHigh = 0xe8,
404 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
405
406 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
407
408 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
409
410 #define TxPacketMax (8064 >> 7)
411 #define EarlySize 0x27
412
413 FuncEvent = 0xf0,
414 FuncEventMask = 0xf4,
415 FuncPresetState = 0xf8,
416 IBCR0 = 0xf8,
417 IBCR2 = 0xf9,
418 IBIMR0 = 0xfa,
419 IBISR0 = 0xfb,
420 FuncForceEvent = 0xfc,
421 };
422
423 enum rtl8110_registers {
424 TBICSR = 0x64,
425 TBI_ANAR = 0x68,
426 TBI_LPAR = 0x6a,
427 };
428
429 enum rtl8168_8101_registers {
430 CSIDR = 0x64,
431 CSIAR = 0x68,
432 #define CSIAR_FLAG 0x80000000
433 #define CSIAR_WRITE_CMD 0x80000000
434 #define CSIAR_BYTE_ENABLE 0x0f
435 #define CSIAR_BYTE_ENABLE_SHIFT 12
436 #define CSIAR_ADDR_MASK 0x0fff
437 #define CSIAR_FUNC_CARD 0x00000000
438 #define CSIAR_FUNC_SDIO 0x00010000
439 #define CSIAR_FUNC_NIC 0x00020000
440 #define CSIAR_FUNC_NIC2 0x00010000
441 PMCH = 0x6f,
442 EPHYAR = 0x80,
443 #define EPHYAR_FLAG 0x80000000
444 #define EPHYAR_WRITE_CMD 0x80000000
445 #define EPHYAR_REG_MASK 0x1f
446 #define EPHYAR_REG_SHIFT 16
447 #define EPHYAR_DATA_MASK 0xffff
448 DLLPR = 0xd0,
449 #define PFM_EN (1 << 6)
450 #define TX_10M_PS_EN (1 << 7)
451 DBG_REG = 0xd1,
452 #define FIX_NAK_1 (1 << 4)
453 #define FIX_NAK_2 (1 << 3)
454 TWSI = 0xd2,
455 MCU = 0xd3,
456 #define NOW_IS_OOB (1 << 7)
457 #define TX_EMPTY (1 << 5)
458 #define RX_EMPTY (1 << 4)
459 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
460 #define EN_NDP (1 << 3)
461 #define EN_OOB_RESET (1 << 2)
462 #define LINK_LIST_RDY (1 << 1)
463 EFUSEAR = 0xdc,
464 #define EFUSEAR_FLAG 0x80000000
465 #define EFUSEAR_WRITE_CMD 0x80000000
466 #define EFUSEAR_READ_CMD 0x00000000
467 #define EFUSEAR_REG_MASK 0x03ff
468 #define EFUSEAR_REG_SHIFT 8
469 #define EFUSEAR_DATA_MASK 0xff
470 MISC_1 = 0xf2,
471 #define PFM_D3COLD_EN (1 << 6)
472 };
473
474 enum rtl8168_registers {
475 LED_FREQ = 0x1a,
476 EEE_LED = 0x1b,
477 ERIDR = 0x70,
478 ERIAR = 0x74,
479 #define ERIAR_FLAG 0x80000000
480 #define ERIAR_WRITE_CMD 0x80000000
481 #define ERIAR_READ_CMD 0x00000000
482 #define ERIAR_ADDR_BYTE_ALIGN 4
483 #define ERIAR_TYPE_SHIFT 16
484 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
485 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
486 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
487 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
488 #define ERIAR_MASK_SHIFT 12
489 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
490 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
491 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
492 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
493 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
494 EPHY_RXER_NUM = 0x7c,
495 OCPDR = 0xb0, /* OCP GPHY access */
496 #define OCPDR_WRITE_CMD 0x80000000
497 #define OCPDR_READ_CMD 0x00000000
498 #define OCPDR_REG_MASK 0x7f
499 #define OCPDR_GPHY_REG_SHIFT 16
500 #define OCPDR_DATA_MASK 0xffff
501 OCPAR = 0xb4,
502 #define OCPAR_FLAG 0x80000000
503 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
504 #define OCPAR_GPHY_READ_CMD 0x0000f060
505 GPHY_OCP = 0xb8,
506 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
507 MISC = 0xf0, /* 8168e only. */
508 #define TXPLA_RST (1 << 29)
509 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
510 #define PWM_EN (1 << 22)
511 #define RXDV_GATED_EN (1 << 19)
512 #define EARLY_TALLY_EN (1 << 16)
513 };
514
515 enum rtl_register_content {
516 /* InterruptStatusBits */
517 SYSErr = 0x8000,
518 PCSTimeout = 0x4000,
519 SWInt = 0x0100,
520 TxDescUnavail = 0x0080,
521 RxFIFOOver = 0x0040,
522 LinkChg = 0x0020,
523 RxOverflow = 0x0010,
524 TxErr = 0x0008,
525 TxOK = 0x0004,
526 RxErr = 0x0002,
527 RxOK = 0x0001,
528
529 /* RxStatusDesc */
530 RxBOVF = (1 << 24),
531 RxFOVF = (1 << 23),
532 RxRWT = (1 << 22),
533 RxRES = (1 << 21),
534 RxRUNT = (1 << 20),
535 RxCRC = (1 << 19),
536
537 /* ChipCmdBits */
538 StopReq = 0x80,
539 CmdReset = 0x10,
540 CmdRxEnb = 0x08,
541 CmdTxEnb = 0x04,
542 RxBufEmpty = 0x01,
543
544 /* TXPoll register p.5 */
545 HPQ = 0x80, /* Poll cmd on the high prio queue */
546 NPQ = 0x40, /* Poll cmd on the low prio queue */
547 FSWInt = 0x01, /* Forced software interrupt */
548
549 /* Cfg9346Bits */
550 Cfg9346_Lock = 0x00,
551 Cfg9346_Unlock = 0xc0,
552
553 /* rx_mode_bits */
554 AcceptErr = 0x20,
555 AcceptRunt = 0x10,
556 AcceptBroadcast = 0x08,
557 AcceptMulticast = 0x04,
558 AcceptMyPhys = 0x02,
559 AcceptAllPhys = 0x01,
560 #define RX_CONFIG_ACCEPT_MASK 0x3f
561
562 /* TxConfigBits */
563 TxInterFrameGapShift = 24,
564 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
565
566 /* Config1 register p.24 */
567 LEDS1 = (1 << 7),
568 LEDS0 = (1 << 6),
569 Speed_down = (1 << 4),
570 MEMMAP = (1 << 3),
571 IOMAP = (1 << 2),
572 VPD = (1 << 1),
573 PMEnable = (1 << 0), /* Power Management Enable */
574
575 /* Config2 register p. 25 */
576 ClkReqEn = (1 << 7), /* Clock Request Enable */
577 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
578 PCI_Clock_66MHz = 0x01,
579 PCI_Clock_33MHz = 0x00,
580
581 /* Config3 register p.25 */
582 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
583 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
584 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
585 Rdy_to_L23 = (1 << 1), /* L23 Enable */
586 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
587
588 /* Config4 register */
589 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
590
591 /* Config5 register p.27 */
592 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
593 MWF = (1 << 5), /* Accept Multicast wakeup frame */
594 UWF = (1 << 4), /* Accept Unicast wakeup frame */
595 Spi_en = (1 << 3),
596 LanWake = (1 << 1), /* LanWake enable/disable */
597 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
598 ASPM_en = (1 << 0), /* ASPM enable */
599
600 /* TBICSR p.28 */
601 TBIReset = 0x80000000,
602 TBILoopback = 0x40000000,
603 TBINwEnable = 0x20000000,
604 TBINwRestart = 0x10000000,
605 TBILinkOk = 0x02000000,
606 TBINwComplete = 0x01000000,
607
608 /* CPlusCmd p.31 */
609 EnableBist = (1 << 15), // 8168 8101
610 Mac_dbgo_oe = (1 << 14), // 8168 8101
611 Normal_mode = (1 << 13), // unused
612 Force_half_dup = (1 << 12), // 8168 8101
613 Force_rxflow_en = (1 << 11), // 8168 8101
614 Force_txflow_en = (1 << 10), // 8168 8101
615 Cxpl_dbg_sel = (1 << 9), // 8168 8101
616 ASF = (1 << 8), // 8168 8101
617 PktCntrDisable = (1 << 7), // 8168 8101
618 Mac_dbgo_sel = 0x001c, // 8168
619 RxVlan = (1 << 6),
620 RxChkSum = (1 << 5),
621 PCIDAC = (1 << 4),
622 PCIMulRW = (1 << 3),
623 INTT_0 = 0x0000, // 8168
624 INTT_1 = 0x0001, // 8168
625 INTT_2 = 0x0002, // 8168
626 INTT_3 = 0x0003, // 8168
627
628 /* rtl8169_PHYstatus */
629 TBI_Enable = 0x80,
630 TxFlowCtrl = 0x40,
631 RxFlowCtrl = 0x20,
632 _1000bpsF = 0x10,
633 _100bps = 0x08,
634 _10bps = 0x04,
635 LinkStatus = 0x02,
636 FullDup = 0x01,
637
638 /* _TBICSRBit */
639 TBILinkOK = 0x02000000,
640
641 /* ResetCounterCommand */
642 CounterReset = 0x1,
643
644 /* DumpCounterCommand */
645 CounterDump = 0x8,
646
647 /* magic enable v2 */
648 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
649 };
650
651 enum rtl_desc_bit {
652 /* First doubleword. */
653 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
654 RingEnd = (1 << 30), /* End of descriptor ring */
655 FirstFrag = (1 << 29), /* First segment of a packet */
656 LastFrag = (1 << 28), /* Final segment of a packet */
657 };
658
659 /* Generic case. */
660 enum rtl_tx_desc_bit {
661 /* First doubleword. */
662 TD_LSO = (1 << 27), /* Large Send Offload */
663 #define TD_MSS_MAX 0x07ffu /* MSS value */
664
665 /* Second doubleword. */
666 TxVlanTag = (1 << 17), /* Add VLAN tag */
667 };
668
669 /* 8169, 8168b and 810x except 8102e. */
670 enum rtl_tx_desc_bit_0 {
671 /* First doubleword. */
672 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
673 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
674 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
675 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
676 };
677
678 /* 8102e, 8168c and beyond. */
679 enum rtl_tx_desc_bit_1 {
680 /* First doubleword. */
681 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
682 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
683 #define GTTCPHO_SHIFT 18
684 #define GTTCPHO_MAX 0x7fU
685
686 /* Second doubleword. */
687 #define TCPHO_SHIFT 18
688 #define TCPHO_MAX 0x3ffU
689 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
690 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
691 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
692 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
693 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
694 };
695
696 enum rtl_rx_desc_bit {
697 /* Rx private */
698 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
699 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
700
701 #define RxProtoUDP (PID1)
702 #define RxProtoTCP (PID0)
703 #define RxProtoIP (PID1 | PID0)
704 #define RxProtoMask RxProtoIP
705
706 IPFail = (1 << 16), /* IP checksum failed */
707 UDPFail = (1 << 15), /* UDP/IP checksum failed */
708 TCPFail = (1 << 14), /* TCP/IP checksum failed */
709 RxVlanTag = (1 << 16), /* VLAN tag available */
710 };
711
712 #define RsvdMask 0x3fffc000
713
714 struct TxDesc {
715 __le32 opts1;
716 __le32 opts2;
717 __le64 addr;
718 };
719
720 struct RxDesc {
721 __le32 opts1;
722 __le32 opts2;
723 __le64 addr;
724 };
725
726 struct ring_info {
727 struct sk_buff *skb;
728 u32 len;
729 u8 __pad[sizeof(void *) - sizeof(u32)];
730 };
731
732 enum features {
733 RTL_FEATURE_WOL = (1 << 0),
734 RTL_FEATURE_MSI = (1 << 1),
735 RTL_FEATURE_GMII = (1 << 2),
736 };
737
738 struct rtl8169_counters {
739 __le64 tx_packets;
740 __le64 rx_packets;
741 __le64 tx_errors;
742 __le32 rx_errors;
743 __le16 rx_missed;
744 __le16 align_errors;
745 __le32 tx_one_collision;
746 __le32 tx_multi_collision;
747 __le64 rx_unicast;
748 __le64 rx_broadcast;
749 __le32 rx_multicast;
750 __le16 tx_aborted;
751 __le16 tx_underun;
752 };
753
754 struct rtl8169_tc_offsets {
755 bool inited;
756 __le64 tx_errors;
757 __le32 tx_multi_collision;
758 __le16 tx_aborted;
759 };
760
761 enum rtl_flag {
762 RTL_FLAG_TASK_ENABLED,
763 RTL_FLAG_TASK_SLOW_PENDING,
764 RTL_FLAG_TASK_RESET_PENDING,
765 RTL_FLAG_TASK_PHY_PENDING,
766 RTL_FLAG_MAX
767 };
768
769 struct rtl8169_stats {
770 u64 packets;
771 u64 bytes;
772 struct u64_stats_sync syncp;
773 };
774
775 struct rtl8169_private {
776 void __iomem *mmio_addr; /* memory map physical address */
777 struct pci_dev *pci_dev;
778 struct net_device *dev;
779 struct napi_struct napi;
780 u32 msg_enable;
781 u16 txd_version;
782 u16 mac_version;
783 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
784 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
785 u32 dirty_tx;
786 struct rtl8169_stats rx_stats;
787 struct rtl8169_stats tx_stats;
788 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
789 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
790 dma_addr_t TxPhyAddr;
791 dma_addr_t RxPhyAddr;
792 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
793 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
794 struct timer_list timer;
795 u16 cp_cmd;
796
797 u16 event_slow;
798
799 struct mdio_ops {
800 void (*write)(struct rtl8169_private *, int, int);
801 int (*read)(struct rtl8169_private *, int);
802 } mdio_ops;
803
804 struct pll_power_ops {
805 void (*down)(struct rtl8169_private *);
806 void (*up)(struct rtl8169_private *);
807 } pll_power_ops;
808
809 struct jumbo_ops {
810 void (*enable)(struct rtl8169_private *);
811 void (*disable)(struct rtl8169_private *);
812 } jumbo_ops;
813
814 struct csi_ops {
815 void (*write)(struct rtl8169_private *, int, int);
816 u32 (*read)(struct rtl8169_private *, int);
817 } csi_ops;
818
819 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
820 int (*get_link_ksettings)(struct net_device *,
821 struct ethtool_link_ksettings *);
822 void (*phy_reset_enable)(struct rtl8169_private *tp);
823 void (*hw_start)(struct net_device *);
824 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
825 unsigned int (*link_ok)(void __iomem *);
826 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
827 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
828
829 struct {
830 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
831 struct mutex mutex;
832 struct work_struct work;
833 } wk;
834
835 unsigned features;
836
837 struct mii_if_info mii;
838 dma_addr_t counters_phys_addr;
839 struct rtl8169_counters *counters;
840 struct rtl8169_tc_offsets tc_offset;
841 u32 saved_wolopts;
842 u32 opts1_mask;
843
844 struct rtl_fw {
845 const struct firmware *fw;
846
847 #define RTL_VER_SIZE 32
848
849 char version[RTL_VER_SIZE];
850
851 struct rtl_fw_phy_action {
852 __le32 *code;
853 size_t size;
854 } phy_action;
855 } *rtl_fw;
856 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
857
858 u32 ocp_base;
859 };
860
861 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
862 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
863 module_param(use_dac, int, 0);
864 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
865 module_param_named(debug, debug.msg_enable, int, 0);
866 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
867 MODULE_LICENSE("GPL");
868 MODULE_VERSION(RTL8169_VERSION);
869 MODULE_FIRMWARE(FIRMWARE_8168D_1);
870 MODULE_FIRMWARE(FIRMWARE_8168D_2);
871 MODULE_FIRMWARE(FIRMWARE_8168E_1);
872 MODULE_FIRMWARE(FIRMWARE_8168E_2);
873 MODULE_FIRMWARE(FIRMWARE_8168E_3);
874 MODULE_FIRMWARE(FIRMWARE_8105E_1);
875 MODULE_FIRMWARE(FIRMWARE_8168F_1);
876 MODULE_FIRMWARE(FIRMWARE_8168F_2);
877 MODULE_FIRMWARE(FIRMWARE_8402_1);
878 MODULE_FIRMWARE(FIRMWARE_8411_1);
879 MODULE_FIRMWARE(FIRMWARE_8411_2);
880 MODULE_FIRMWARE(FIRMWARE_8106E_1);
881 MODULE_FIRMWARE(FIRMWARE_8106E_2);
882 MODULE_FIRMWARE(FIRMWARE_8168G_2);
883 MODULE_FIRMWARE(FIRMWARE_8168G_3);
884 MODULE_FIRMWARE(FIRMWARE_8168H_1);
885 MODULE_FIRMWARE(FIRMWARE_8168H_2);
886 MODULE_FIRMWARE(FIRMWARE_8107E_1);
887 MODULE_FIRMWARE(FIRMWARE_8107E_2);
888
889 static void rtl_lock_work(struct rtl8169_private *tp)
890 {
891 mutex_lock(&tp->wk.mutex);
892 }
893
894 static void rtl_unlock_work(struct rtl8169_private *tp)
895 {
896 mutex_unlock(&tp->wk.mutex);
897 }
898
899 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
900 {
901 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
902 PCI_EXP_DEVCTL_READRQ, force);
903 }
904
905 struct rtl_cond {
906 bool (*check)(struct rtl8169_private *);
907 const char *msg;
908 };
909
910 static void rtl_udelay(unsigned int d)
911 {
912 udelay(d);
913 }
914
915 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
916 void (*delay)(unsigned int), unsigned int d, int n,
917 bool high)
918 {
919 int i;
920
921 for (i = 0; i < n; i++) {
922 delay(d);
923 if (c->check(tp) == high)
924 return true;
925 }
926 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
927 c->msg, !high, n, d);
928 return false;
929 }
930
931 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
932 const struct rtl_cond *c,
933 unsigned int d, int n)
934 {
935 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
936 }
937
938 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
939 const struct rtl_cond *c,
940 unsigned int d, int n)
941 {
942 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
943 }
944
945 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
946 const struct rtl_cond *c,
947 unsigned int d, int n)
948 {
949 return rtl_loop_wait(tp, c, msleep, d, n, true);
950 }
951
952 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
953 const struct rtl_cond *c,
954 unsigned int d, int n)
955 {
956 return rtl_loop_wait(tp, c, msleep, d, n, false);
957 }
958
959 #define DECLARE_RTL_COND(name) \
960 static bool name ## _check(struct rtl8169_private *); \
961 \
962 static const struct rtl_cond name = { \
963 .check = name ## _check, \
964 .msg = #name \
965 }; \
966 \
967 static bool name ## _check(struct rtl8169_private *tp)
968
969 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
970 {
971 if (reg & 0xffff0001) {
972 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
973 return true;
974 }
975 return false;
976 }
977
978 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
979 {
980 void __iomem *ioaddr = tp->mmio_addr;
981
982 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
983 }
984
985 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
986 {
987 void __iomem *ioaddr = tp->mmio_addr;
988
989 if (rtl_ocp_reg_failure(tp, reg))
990 return;
991
992 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
993
994 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
995 }
996
997 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
998 {
999 void __iomem *ioaddr = tp->mmio_addr;
1000
1001 if (rtl_ocp_reg_failure(tp, reg))
1002 return 0;
1003
1004 RTL_W32(GPHY_OCP, reg << 15);
1005
1006 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1007 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1008 }
1009
1010 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1011 {
1012 void __iomem *ioaddr = tp->mmio_addr;
1013
1014 if (rtl_ocp_reg_failure(tp, reg))
1015 return;
1016
1017 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1018 }
1019
1020 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1021 {
1022 void __iomem *ioaddr = tp->mmio_addr;
1023
1024 if (rtl_ocp_reg_failure(tp, reg))
1025 return 0;
1026
1027 RTL_W32(OCPDR, reg << 15);
1028
1029 return RTL_R32(OCPDR);
1030 }
1031
1032 #define OCP_STD_PHY_BASE 0xa400
1033
1034 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1035 {
1036 if (reg == 0x1f) {
1037 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1038 return;
1039 }
1040
1041 if (tp->ocp_base != OCP_STD_PHY_BASE)
1042 reg -= 0x10;
1043
1044 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1045 }
1046
1047 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1048 {
1049 if (tp->ocp_base != OCP_STD_PHY_BASE)
1050 reg -= 0x10;
1051
1052 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1053 }
1054
1055 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1056 {
1057 if (reg == 0x1f) {
1058 tp->ocp_base = value << 4;
1059 return;
1060 }
1061
1062 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1063 }
1064
1065 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1066 {
1067 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1068 }
1069
1070 DECLARE_RTL_COND(rtl_phyar_cond)
1071 {
1072 void __iomem *ioaddr = tp->mmio_addr;
1073
1074 return RTL_R32(PHYAR) & 0x80000000;
1075 }
1076
1077 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1078 {
1079 void __iomem *ioaddr = tp->mmio_addr;
1080
1081 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1082
1083 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1084 /*
1085 * According to hardware specs a 20us delay is required after write
1086 * complete indication, but before sending next command.
1087 */
1088 udelay(20);
1089 }
1090
1091 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1092 {
1093 void __iomem *ioaddr = tp->mmio_addr;
1094 int value;
1095
1096 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1097
1098 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1099 RTL_R32(PHYAR) & 0xffff : ~0;
1100
1101 /*
1102 * According to hardware specs a 20us delay is required after read
1103 * complete indication, but before sending next command.
1104 */
1105 udelay(20);
1106
1107 return value;
1108 }
1109
1110 DECLARE_RTL_COND(rtl_ocpar_cond)
1111 {
1112 void __iomem *ioaddr = tp->mmio_addr;
1113
1114 return RTL_R32(OCPAR) & OCPAR_FLAG;
1115 }
1116
1117 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1118 {
1119 void __iomem *ioaddr = tp->mmio_addr;
1120
1121 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1122 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1123 RTL_W32(EPHY_RXER_NUM, 0);
1124
1125 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1126 }
1127
1128 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1129 {
1130 r8168dp_1_mdio_access(tp, reg,
1131 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1132 }
1133
1134 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1135 {
1136 void __iomem *ioaddr = tp->mmio_addr;
1137
1138 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1139
1140 mdelay(1);
1141 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1142 RTL_W32(EPHY_RXER_NUM, 0);
1143
1144 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1145 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1146 }
1147
1148 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1149
1150 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1151 {
1152 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1153 }
1154
1155 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1156 {
1157 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1158 }
1159
1160 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1161 {
1162 void __iomem *ioaddr = tp->mmio_addr;
1163
1164 r8168dp_2_mdio_start(ioaddr);
1165
1166 r8169_mdio_write(tp, reg, value);
1167
1168 r8168dp_2_mdio_stop(ioaddr);
1169 }
1170
1171 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1172 {
1173 void __iomem *ioaddr = tp->mmio_addr;
1174 int value;
1175
1176 r8168dp_2_mdio_start(ioaddr);
1177
1178 value = r8169_mdio_read(tp, reg);
1179
1180 r8168dp_2_mdio_stop(ioaddr);
1181
1182 return value;
1183 }
1184
1185 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1186 {
1187 tp->mdio_ops.write(tp, location, val);
1188 }
1189
1190 static int rtl_readphy(struct rtl8169_private *tp, int location)
1191 {
1192 return tp->mdio_ops.read(tp, location);
1193 }
1194
1195 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1196 {
1197 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1198 }
1199
1200 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1201 {
1202 int val;
1203
1204 val = rtl_readphy(tp, reg_addr);
1205 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1206 }
1207
1208 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1209 int val)
1210 {
1211 struct rtl8169_private *tp = netdev_priv(dev);
1212
1213 rtl_writephy(tp, location, val);
1214 }
1215
1216 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1217 {
1218 struct rtl8169_private *tp = netdev_priv(dev);
1219
1220 return rtl_readphy(tp, location);
1221 }
1222
1223 DECLARE_RTL_COND(rtl_ephyar_cond)
1224 {
1225 void __iomem *ioaddr = tp->mmio_addr;
1226
1227 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1228 }
1229
1230 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1231 {
1232 void __iomem *ioaddr = tp->mmio_addr;
1233
1234 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1235 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1236
1237 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1238
1239 udelay(10);
1240 }
1241
1242 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1243 {
1244 void __iomem *ioaddr = tp->mmio_addr;
1245
1246 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1247
1248 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1249 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1250 }
1251
1252 DECLARE_RTL_COND(rtl_eriar_cond)
1253 {
1254 void __iomem *ioaddr = tp->mmio_addr;
1255
1256 return RTL_R32(ERIAR) & ERIAR_FLAG;
1257 }
1258
1259 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1260 u32 val, int type)
1261 {
1262 void __iomem *ioaddr = tp->mmio_addr;
1263
1264 BUG_ON((addr & 3) || (mask == 0));
1265 RTL_W32(ERIDR, val);
1266 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1267
1268 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1269 }
1270
1271 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1272 {
1273 void __iomem *ioaddr = tp->mmio_addr;
1274
1275 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1276
1277 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1278 RTL_R32(ERIDR) : ~0;
1279 }
1280
1281 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1282 u32 m, int type)
1283 {
1284 u32 val;
1285
1286 val = rtl_eri_read(tp, addr, type);
1287 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1288 }
1289
1290 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1291 {
1292 void __iomem *ioaddr = tp->mmio_addr;
1293
1294 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1295 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1296 RTL_R32(OCPDR) : ~0;
1297 }
1298
1299 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1300 {
1301 return rtl_eri_read(tp, reg, ERIAR_OOB);
1302 }
1303
1304 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1305 {
1306 switch (tp->mac_version) {
1307 case RTL_GIGA_MAC_VER_27:
1308 case RTL_GIGA_MAC_VER_28:
1309 case RTL_GIGA_MAC_VER_31:
1310 return r8168dp_ocp_read(tp, mask, reg);
1311 case RTL_GIGA_MAC_VER_49:
1312 case RTL_GIGA_MAC_VER_50:
1313 case RTL_GIGA_MAC_VER_51:
1314 return r8168ep_ocp_read(tp, mask, reg);
1315 default:
1316 BUG();
1317 return ~0;
1318 }
1319 }
1320
1321 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1322 u32 data)
1323 {
1324 void __iomem *ioaddr = tp->mmio_addr;
1325
1326 RTL_W32(OCPDR, data);
1327 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1328 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1329 }
1330
1331 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1332 u32 data)
1333 {
1334 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1335 data, ERIAR_OOB);
1336 }
1337
1338 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1339 {
1340 switch (tp->mac_version) {
1341 case RTL_GIGA_MAC_VER_27:
1342 case RTL_GIGA_MAC_VER_28:
1343 case RTL_GIGA_MAC_VER_31:
1344 r8168dp_ocp_write(tp, mask, reg, data);
1345 break;
1346 case RTL_GIGA_MAC_VER_49:
1347 case RTL_GIGA_MAC_VER_50:
1348 case RTL_GIGA_MAC_VER_51:
1349 r8168ep_ocp_write(tp, mask, reg, data);
1350 break;
1351 default:
1352 BUG();
1353 break;
1354 }
1355 }
1356
1357 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1358 {
1359 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1360
1361 ocp_write(tp, 0x1, 0x30, 0x00000001);
1362 }
1363
1364 #define OOB_CMD_RESET 0x00
1365 #define OOB_CMD_DRIVER_START 0x05
1366 #define OOB_CMD_DRIVER_STOP 0x06
1367
1368 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1369 {
1370 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1371 }
1372
1373 DECLARE_RTL_COND(rtl_ocp_read_cond)
1374 {
1375 u16 reg;
1376
1377 reg = rtl8168_get_ocp_reg(tp);
1378
1379 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1380 }
1381
1382 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1383 {
1384 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1385 }
1386
1387 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1388 {
1389 void __iomem *ioaddr = tp->mmio_addr;
1390
1391 return RTL_R8(IBISR0) & 0x02;
1392 }
1393
1394 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1395 {
1396 void __iomem *ioaddr = tp->mmio_addr;
1397
1398 RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);
1399 rtl_msleep_loop_wait_low(tp, &rtl_ocp_tx_cond, 50, 2000);
1400 RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);
1401 RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);
1402 }
1403
1404 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1405 {
1406 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1407 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1408 }
1409
1410 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1411 {
1412 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1413 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1414 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1415 }
1416
1417 static void rtl8168_driver_start(struct rtl8169_private *tp)
1418 {
1419 switch (tp->mac_version) {
1420 case RTL_GIGA_MAC_VER_27:
1421 case RTL_GIGA_MAC_VER_28:
1422 case RTL_GIGA_MAC_VER_31:
1423 rtl8168dp_driver_start(tp);
1424 break;
1425 case RTL_GIGA_MAC_VER_49:
1426 case RTL_GIGA_MAC_VER_50:
1427 case RTL_GIGA_MAC_VER_51:
1428 rtl8168ep_driver_start(tp);
1429 break;
1430 default:
1431 BUG();
1432 break;
1433 }
1434 }
1435
1436 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1437 {
1438 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1439 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1440 }
1441
1442 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1443 {
1444 rtl8168ep_stop_cmac(tp);
1445 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1446 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1447 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1448 }
1449
1450 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1451 {
1452 switch (tp->mac_version) {
1453 case RTL_GIGA_MAC_VER_27:
1454 case RTL_GIGA_MAC_VER_28:
1455 case RTL_GIGA_MAC_VER_31:
1456 rtl8168dp_driver_stop(tp);
1457 break;
1458 case RTL_GIGA_MAC_VER_49:
1459 case RTL_GIGA_MAC_VER_50:
1460 case RTL_GIGA_MAC_VER_51:
1461 rtl8168ep_driver_stop(tp);
1462 break;
1463 default:
1464 BUG();
1465 break;
1466 }
1467 }
1468
1469 static int r8168dp_check_dash(struct rtl8169_private *tp)
1470 {
1471 u16 reg = rtl8168_get_ocp_reg(tp);
1472
1473 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1474 }
1475
1476 static int r8168ep_check_dash(struct rtl8169_private *tp)
1477 {
1478 return (ocp_read(tp, 0x0f, 0x128) & 0x00000001) ? 1 : 0;
1479 }
1480
1481 static int r8168_check_dash(struct rtl8169_private *tp)
1482 {
1483 switch (tp->mac_version) {
1484 case RTL_GIGA_MAC_VER_27:
1485 case RTL_GIGA_MAC_VER_28:
1486 case RTL_GIGA_MAC_VER_31:
1487 return r8168dp_check_dash(tp);
1488 case RTL_GIGA_MAC_VER_49:
1489 case RTL_GIGA_MAC_VER_50:
1490 case RTL_GIGA_MAC_VER_51:
1491 return r8168ep_check_dash(tp);
1492 default:
1493 return 0;
1494 }
1495 }
1496
1497 struct exgmac_reg {
1498 u16 addr;
1499 u16 mask;
1500 u32 val;
1501 };
1502
1503 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1504 const struct exgmac_reg *r, int len)
1505 {
1506 while (len-- > 0) {
1507 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1508 r++;
1509 }
1510 }
1511
1512 DECLARE_RTL_COND(rtl_efusear_cond)
1513 {
1514 void __iomem *ioaddr = tp->mmio_addr;
1515
1516 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1517 }
1518
1519 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1520 {
1521 void __iomem *ioaddr = tp->mmio_addr;
1522
1523 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1524
1525 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1526 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1527 }
1528
1529 static u16 rtl_get_events(struct rtl8169_private *tp)
1530 {
1531 void __iomem *ioaddr = tp->mmio_addr;
1532
1533 return RTL_R16(IntrStatus);
1534 }
1535
1536 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1537 {
1538 void __iomem *ioaddr = tp->mmio_addr;
1539
1540 RTL_W16(IntrStatus, bits);
1541 mmiowb();
1542 }
1543
1544 static void rtl_irq_disable(struct rtl8169_private *tp)
1545 {
1546 void __iomem *ioaddr = tp->mmio_addr;
1547
1548 RTL_W16(IntrMask, 0);
1549 mmiowb();
1550 }
1551
1552 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1553 {
1554 void __iomem *ioaddr = tp->mmio_addr;
1555
1556 RTL_W16(IntrMask, bits);
1557 }
1558
1559 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1560 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1561 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1562
1563 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1564 {
1565 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1566 }
1567
1568 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1569 {
1570 void __iomem *ioaddr = tp->mmio_addr;
1571
1572 rtl_irq_disable(tp);
1573 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1574 RTL_R8(ChipCmd);
1575 }
1576
1577 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1578 {
1579 void __iomem *ioaddr = tp->mmio_addr;
1580
1581 return RTL_R32(TBICSR) & TBIReset;
1582 }
1583
1584 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1585 {
1586 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1587 }
1588
1589 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1590 {
1591 return RTL_R32(TBICSR) & TBILinkOk;
1592 }
1593
1594 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1595 {
1596 return RTL_R8(PHYstatus) & LinkStatus;
1597 }
1598
1599 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1600 {
1601 void __iomem *ioaddr = tp->mmio_addr;
1602
1603 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1604 }
1605
1606 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1607 {
1608 unsigned int val;
1609
1610 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1611 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1612 }
1613
1614 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1615 {
1616 void __iomem *ioaddr = tp->mmio_addr;
1617 struct net_device *dev = tp->dev;
1618
1619 if (!netif_running(dev))
1620 return;
1621
1622 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1623 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1624 if (RTL_R8(PHYstatus) & _1000bpsF) {
1625 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1626 ERIAR_EXGMAC);
1627 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1628 ERIAR_EXGMAC);
1629 } else if (RTL_R8(PHYstatus) & _100bps) {
1630 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1631 ERIAR_EXGMAC);
1632 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1633 ERIAR_EXGMAC);
1634 } else {
1635 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1636 ERIAR_EXGMAC);
1637 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1638 ERIAR_EXGMAC);
1639 }
1640 /* Reset packet filter */
1641 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1642 ERIAR_EXGMAC);
1643 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1644 ERIAR_EXGMAC);
1645 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1646 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1647 if (RTL_R8(PHYstatus) & _1000bpsF) {
1648 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1649 ERIAR_EXGMAC);
1650 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1651 ERIAR_EXGMAC);
1652 } else {
1653 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1654 ERIAR_EXGMAC);
1655 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1656 ERIAR_EXGMAC);
1657 }
1658 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1659 if (RTL_R8(PHYstatus) & _10bps) {
1660 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1661 ERIAR_EXGMAC);
1662 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1663 ERIAR_EXGMAC);
1664 } else {
1665 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1666 ERIAR_EXGMAC);
1667 }
1668 }
1669 }
1670
1671 static void __rtl8169_check_link_status(struct net_device *dev,
1672 struct rtl8169_private *tp,
1673 void __iomem *ioaddr, bool pm)
1674 {
1675 if (tp->link_ok(ioaddr)) {
1676 rtl_link_chg_patch(tp);
1677 /* This is to cancel a scheduled suspend if there's one. */
1678 if (pm)
1679 pm_request_resume(&tp->pci_dev->dev);
1680 netif_carrier_on(dev);
1681 if (net_ratelimit())
1682 netif_info(tp, ifup, dev, "link up\n");
1683 } else {
1684 netif_carrier_off(dev);
1685 netif_info(tp, ifdown, dev, "link down\n");
1686 if (pm)
1687 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1688 }
1689 }
1690
1691 static void rtl8169_check_link_status(struct net_device *dev,
1692 struct rtl8169_private *tp,
1693 void __iomem *ioaddr)
1694 {
1695 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1696 }
1697
1698 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1699
1700 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1701 {
1702 void __iomem *ioaddr = tp->mmio_addr;
1703 u8 options;
1704 u32 wolopts = 0;
1705
1706 options = RTL_R8(Config1);
1707 if (!(options & PMEnable))
1708 return 0;
1709
1710 options = RTL_R8(Config3);
1711 if (options & LinkUp)
1712 wolopts |= WAKE_PHY;
1713 switch (tp->mac_version) {
1714 case RTL_GIGA_MAC_VER_34:
1715 case RTL_GIGA_MAC_VER_35:
1716 case RTL_GIGA_MAC_VER_36:
1717 case RTL_GIGA_MAC_VER_37:
1718 case RTL_GIGA_MAC_VER_38:
1719 case RTL_GIGA_MAC_VER_40:
1720 case RTL_GIGA_MAC_VER_41:
1721 case RTL_GIGA_MAC_VER_42:
1722 case RTL_GIGA_MAC_VER_43:
1723 case RTL_GIGA_MAC_VER_44:
1724 case RTL_GIGA_MAC_VER_45:
1725 case RTL_GIGA_MAC_VER_46:
1726 case RTL_GIGA_MAC_VER_47:
1727 case RTL_GIGA_MAC_VER_48:
1728 case RTL_GIGA_MAC_VER_49:
1729 case RTL_GIGA_MAC_VER_50:
1730 case RTL_GIGA_MAC_VER_51:
1731 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1732 wolopts |= WAKE_MAGIC;
1733 break;
1734 default:
1735 if (options & MagicPacket)
1736 wolopts |= WAKE_MAGIC;
1737 break;
1738 }
1739
1740 options = RTL_R8(Config5);
1741 if (options & UWF)
1742 wolopts |= WAKE_UCAST;
1743 if (options & BWF)
1744 wolopts |= WAKE_BCAST;
1745 if (options & MWF)
1746 wolopts |= WAKE_MCAST;
1747
1748 return wolopts;
1749 }
1750
1751 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1752 {
1753 struct rtl8169_private *tp = netdev_priv(dev);
1754 struct device *d = &tp->pci_dev->dev;
1755
1756 pm_runtime_get_noresume(d);
1757
1758 rtl_lock_work(tp);
1759
1760 wol->supported = WAKE_ANY;
1761 if (pm_runtime_active(d))
1762 wol->wolopts = __rtl8169_get_wol(tp);
1763 else
1764 wol->wolopts = tp->saved_wolopts;
1765
1766 rtl_unlock_work(tp);
1767
1768 pm_runtime_put_noidle(d);
1769 }
1770
1771 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1772 {
1773 void __iomem *ioaddr = tp->mmio_addr;
1774 unsigned int i, tmp;
1775 static const struct {
1776 u32 opt;
1777 u16 reg;
1778 u8 mask;
1779 } cfg[] = {
1780 { WAKE_PHY, Config3, LinkUp },
1781 { WAKE_UCAST, Config5, UWF },
1782 { WAKE_BCAST, Config5, BWF },
1783 { WAKE_MCAST, Config5, MWF },
1784 { WAKE_ANY, Config5, LanWake },
1785 { WAKE_MAGIC, Config3, MagicPacket }
1786 };
1787 u8 options;
1788
1789 RTL_W8(Cfg9346, Cfg9346_Unlock);
1790
1791 switch (tp->mac_version) {
1792 case RTL_GIGA_MAC_VER_34:
1793 case RTL_GIGA_MAC_VER_35:
1794 case RTL_GIGA_MAC_VER_36:
1795 case RTL_GIGA_MAC_VER_37:
1796 case RTL_GIGA_MAC_VER_38:
1797 case RTL_GIGA_MAC_VER_40:
1798 case RTL_GIGA_MAC_VER_41:
1799 case RTL_GIGA_MAC_VER_42:
1800 case RTL_GIGA_MAC_VER_43:
1801 case RTL_GIGA_MAC_VER_44:
1802 case RTL_GIGA_MAC_VER_45:
1803 case RTL_GIGA_MAC_VER_46:
1804 case RTL_GIGA_MAC_VER_47:
1805 case RTL_GIGA_MAC_VER_48:
1806 case RTL_GIGA_MAC_VER_49:
1807 case RTL_GIGA_MAC_VER_50:
1808 case RTL_GIGA_MAC_VER_51:
1809 tmp = ARRAY_SIZE(cfg) - 1;
1810 if (wolopts & WAKE_MAGIC)
1811 rtl_w0w1_eri(tp,
1812 0x0dc,
1813 ERIAR_MASK_0100,
1814 MagicPacket_v2,
1815 0x0000,
1816 ERIAR_EXGMAC);
1817 else
1818 rtl_w0w1_eri(tp,
1819 0x0dc,
1820 ERIAR_MASK_0100,
1821 0x0000,
1822 MagicPacket_v2,
1823 ERIAR_EXGMAC);
1824 break;
1825 default:
1826 tmp = ARRAY_SIZE(cfg);
1827 break;
1828 }
1829
1830 for (i = 0; i < tmp; i++) {
1831 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1832 if (wolopts & cfg[i].opt)
1833 options |= cfg[i].mask;
1834 RTL_W8(cfg[i].reg, options);
1835 }
1836
1837 switch (tp->mac_version) {
1838 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1839 options = RTL_R8(Config1) & ~PMEnable;
1840 if (wolopts)
1841 options |= PMEnable;
1842 RTL_W8(Config1, options);
1843 break;
1844 default:
1845 options = RTL_R8(Config2) & ~PME_SIGNAL;
1846 if (wolopts)
1847 options |= PME_SIGNAL;
1848 RTL_W8(Config2, options);
1849 break;
1850 }
1851
1852 RTL_W8(Cfg9346, Cfg9346_Lock);
1853 }
1854
1855 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1856 {
1857 struct rtl8169_private *tp = netdev_priv(dev);
1858 struct device *d = &tp->pci_dev->dev;
1859
1860 pm_runtime_get_noresume(d);
1861
1862 rtl_lock_work(tp);
1863
1864 if (wol->wolopts)
1865 tp->features |= RTL_FEATURE_WOL;
1866 else
1867 tp->features &= ~RTL_FEATURE_WOL;
1868 if (pm_runtime_active(d))
1869 __rtl8169_set_wol(tp, wol->wolopts);
1870 else
1871 tp->saved_wolopts = wol->wolopts;
1872
1873 rtl_unlock_work(tp);
1874
1875 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1876
1877 pm_runtime_put_noidle(d);
1878
1879 return 0;
1880 }
1881
1882 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1883 {
1884 return rtl_chip_infos[tp->mac_version].fw_name;
1885 }
1886
1887 static void rtl8169_get_drvinfo(struct net_device *dev,
1888 struct ethtool_drvinfo *info)
1889 {
1890 struct rtl8169_private *tp = netdev_priv(dev);
1891 struct rtl_fw *rtl_fw = tp->rtl_fw;
1892
1893 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1894 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1895 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1896 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1897 if (!IS_ERR_OR_NULL(rtl_fw))
1898 strlcpy(info->fw_version, rtl_fw->version,
1899 sizeof(info->fw_version));
1900 }
1901
1902 static int rtl8169_get_regs_len(struct net_device *dev)
1903 {
1904 return R8169_REGS_SIZE;
1905 }
1906
1907 static int rtl8169_set_speed_tbi(struct net_device *dev,
1908 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1909 {
1910 struct rtl8169_private *tp = netdev_priv(dev);
1911 void __iomem *ioaddr = tp->mmio_addr;
1912 int ret = 0;
1913 u32 reg;
1914
1915 reg = RTL_R32(TBICSR);
1916 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1917 (duplex == DUPLEX_FULL)) {
1918 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1919 } else if (autoneg == AUTONEG_ENABLE)
1920 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1921 else {
1922 netif_warn(tp, link, dev,
1923 "incorrect speed setting refused in TBI mode\n");
1924 ret = -EOPNOTSUPP;
1925 }
1926
1927 return ret;
1928 }
1929
1930 static int rtl8169_set_speed_xmii(struct net_device *dev,
1931 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1932 {
1933 struct rtl8169_private *tp = netdev_priv(dev);
1934 int giga_ctrl, bmcr;
1935 int rc = -EINVAL;
1936
1937 rtl_writephy(tp, 0x1f, 0x0000);
1938
1939 if (autoneg == AUTONEG_ENABLE) {
1940 int auto_nego;
1941
1942 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1943 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1944 ADVERTISE_100HALF | ADVERTISE_100FULL);
1945
1946 if (adv & ADVERTISED_10baseT_Half)
1947 auto_nego |= ADVERTISE_10HALF;
1948 if (adv & ADVERTISED_10baseT_Full)
1949 auto_nego |= ADVERTISE_10FULL;
1950 if (adv & ADVERTISED_100baseT_Half)
1951 auto_nego |= ADVERTISE_100HALF;
1952 if (adv & ADVERTISED_100baseT_Full)
1953 auto_nego |= ADVERTISE_100FULL;
1954
1955 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1956
1957 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1958 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1959
1960 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1961 if (tp->mii.supports_gmii) {
1962 if (adv & ADVERTISED_1000baseT_Half)
1963 giga_ctrl |= ADVERTISE_1000HALF;
1964 if (adv & ADVERTISED_1000baseT_Full)
1965 giga_ctrl |= ADVERTISE_1000FULL;
1966 } else if (adv & (ADVERTISED_1000baseT_Half |
1967 ADVERTISED_1000baseT_Full)) {
1968 netif_info(tp, link, dev,
1969 "PHY does not support 1000Mbps\n");
1970 goto out;
1971 }
1972
1973 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1974
1975 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1976 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1977 } else {
1978 giga_ctrl = 0;
1979
1980 if (speed == SPEED_10)
1981 bmcr = 0;
1982 else if (speed == SPEED_100)
1983 bmcr = BMCR_SPEED100;
1984 else
1985 goto out;
1986
1987 if (duplex == DUPLEX_FULL)
1988 bmcr |= BMCR_FULLDPLX;
1989 }
1990
1991 rtl_writephy(tp, MII_BMCR, bmcr);
1992
1993 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1994 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1995 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1996 rtl_writephy(tp, 0x17, 0x2138);
1997 rtl_writephy(tp, 0x0e, 0x0260);
1998 } else {
1999 rtl_writephy(tp, 0x17, 0x2108);
2000 rtl_writephy(tp, 0x0e, 0x0000);
2001 }
2002 }
2003
2004 rc = 0;
2005 out:
2006 return rc;
2007 }
2008
2009 static int rtl8169_set_speed(struct net_device *dev,
2010 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
2011 {
2012 struct rtl8169_private *tp = netdev_priv(dev);
2013 int ret;
2014
2015 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
2016 if (ret < 0)
2017 goto out;
2018
2019 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
2020 (advertising & ADVERTISED_1000baseT_Full) &&
2021 !pci_is_pcie(tp->pci_dev)) {
2022 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
2023 }
2024 out:
2025 return ret;
2026 }
2027
2028 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2029 {
2030 struct rtl8169_private *tp = netdev_priv(dev);
2031 int ret;
2032
2033 del_timer_sync(&tp->timer);
2034
2035 rtl_lock_work(tp);
2036 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
2037 cmd->duplex, cmd->advertising);
2038 rtl_unlock_work(tp);
2039
2040 return ret;
2041 }
2042
2043 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
2044 netdev_features_t features)
2045 {
2046 struct rtl8169_private *tp = netdev_priv(dev);
2047
2048 if (dev->mtu > TD_MSS_MAX)
2049 features &= ~NETIF_F_ALL_TSO;
2050
2051 if (dev->mtu > JUMBO_1K &&
2052 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
2053 features &= ~NETIF_F_IP_CSUM;
2054
2055 return features;
2056 }
2057
2058 static void __rtl8169_set_features(struct net_device *dev,
2059 netdev_features_t features)
2060 {
2061 struct rtl8169_private *tp = netdev_priv(dev);
2062 void __iomem *ioaddr = tp->mmio_addr;
2063 u32 rx_config;
2064
2065 rx_config = RTL_R32(RxConfig);
2066 if (features & NETIF_F_RXALL)
2067 rx_config |= (AcceptErr | AcceptRunt);
2068 else
2069 rx_config &= ~(AcceptErr | AcceptRunt);
2070
2071 RTL_W32(RxConfig, rx_config);
2072
2073 if (features & NETIF_F_RXCSUM)
2074 tp->cp_cmd |= RxChkSum;
2075 else
2076 tp->cp_cmd &= ~RxChkSum;
2077
2078 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2079 tp->cp_cmd |= RxVlan;
2080 else
2081 tp->cp_cmd &= ~RxVlan;
2082
2083 tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
2084
2085 RTL_W16(CPlusCmd, tp->cp_cmd);
2086 RTL_R16(CPlusCmd);
2087 }
2088
2089 static int rtl8169_set_features(struct net_device *dev,
2090 netdev_features_t features)
2091 {
2092 struct rtl8169_private *tp = netdev_priv(dev);
2093
2094 features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
2095
2096 rtl_lock_work(tp);
2097 if (features ^ dev->features)
2098 __rtl8169_set_features(dev, features);
2099 rtl_unlock_work(tp);
2100
2101 return 0;
2102 }
2103
2104
2105 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
2106 {
2107 return (skb_vlan_tag_present(skb)) ?
2108 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
2109 }
2110
2111 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
2112 {
2113 u32 opts2 = le32_to_cpu(desc->opts2);
2114
2115 if (opts2 & RxVlanTag)
2116 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
2117 }
2118
2119 static int rtl8169_get_link_ksettings_tbi(struct net_device *dev,
2120 struct ethtool_link_ksettings *cmd)
2121 {
2122 struct rtl8169_private *tp = netdev_priv(dev);
2123 void __iomem *ioaddr = tp->mmio_addr;
2124 u32 status;
2125 u32 supported, advertising;
2126
2127 supported =
2128 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
2129 cmd->base.port = PORT_FIBRE;
2130
2131 status = RTL_R32(TBICSR);
2132 advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
2133 cmd->base.autoneg = !!(status & TBINwEnable);
2134
2135 cmd->base.speed = SPEED_1000;
2136 cmd->base.duplex = DUPLEX_FULL; /* Always set */
2137
2138 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
2139 supported);
2140 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
2141 advertising);
2142
2143 return 0;
2144 }
2145
2146 static int rtl8169_get_link_ksettings_xmii(struct net_device *dev,
2147 struct ethtool_link_ksettings *cmd)
2148 {
2149 struct rtl8169_private *tp = netdev_priv(dev);
2150
2151 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
2152
2153 return 0;
2154 }
2155
2156 static int rtl8169_get_link_ksettings(struct net_device *dev,
2157 struct ethtool_link_ksettings *cmd)
2158 {
2159 struct rtl8169_private *tp = netdev_priv(dev);
2160 int rc;
2161
2162 rtl_lock_work(tp);
2163 rc = tp->get_link_ksettings(dev, cmd);
2164 rtl_unlock_work(tp);
2165
2166 return rc;
2167 }
2168
2169 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2170 void *p)
2171 {
2172 struct rtl8169_private *tp = netdev_priv(dev);
2173 u32 __iomem *data = tp->mmio_addr;
2174 u32 *dw = p;
2175 int i;
2176
2177 rtl_lock_work(tp);
2178 for (i = 0; i < R8169_REGS_SIZE; i += 4)
2179 memcpy_fromio(dw++, data++, 4);
2180 rtl_unlock_work(tp);
2181 }
2182
2183 static u32 rtl8169_get_msglevel(struct net_device *dev)
2184 {
2185 struct rtl8169_private *tp = netdev_priv(dev);
2186
2187 return tp->msg_enable;
2188 }
2189
2190 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2191 {
2192 struct rtl8169_private *tp = netdev_priv(dev);
2193
2194 tp->msg_enable = value;
2195 }
2196
2197 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2198 "tx_packets",
2199 "rx_packets",
2200 "tx_errors",
2201 "rx_errors",
2202 "rx_missed",
2203 "align_errors",
2204 "tx_single_collisions",
2205 "tx_multi_collisions",
2206 "unicast",
2207 "broadcast",
2208 "multicast",
2209 "tx_aborted",
2210 "tx_underrun",
2211 };
2212
2213 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
2214 {
2215 switch (sset) {
2216 case ETH_SS_STATS:
2217 return ARRAY_SIZE(rtl8169_gstrings);
2218 default:
2219 return -EOPNOTSUPP;
2220 }
2221 }
2222
2223 DECLARE_RTL_COND(rtl_counters_cond)
2224 {
2225 void __iomem *ioaddr = tp->mmio_addr;
2226
2227 return RTL_R32(CounterAddrLow) & (CounterReset | CounterDump);
2228 }
2229
2230 static bool rtl8169_do_counters(struct net_device *dev, u32 counter_cmd)
2231 {
2232 struct rtl8169_private *tp = netdev_priv(dev);
2233 void __iomem *ioaddr = tp->mmio_addr;
2234 dma_addr_t paddr = tp->counters_phys_addr;
2235 u32 cmd;
2236 bool ret;
2237
2238 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
2239 cmd = (u64)paddr & DMA_BIT_MASK(32);
2240 RTL_W32(CounterAddrLow, cmd);
2241 RTL_W32(CounterAddrLow, cmd | counter_cmd);
2242
2243 ret = rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
2244
2245 RTL_W32(CounterAddrLow, 0);
2246 RTL_W32(CounterAddrHigh, 0);
2247
2248 return ret;
2249 }
2250
2251 static bool rtl8169_reset_counters(struct net_device *dev)
2252 {
2253 struct rtl8169_private *tp = netdev_priv(dev);
2254
2255 /*
2256 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
2257 * tally counters.
2258 */
2259 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
2260 return true;
2261
2262 return rtl8169_do_counters(dev, CounterReset);
2263 }
2264
2265 static bool rtl8169_update_counters(struct net_device *dev)
2266 {
2267 struct rtl8169_private *tp = netdev_priv(dev);
2268 void __iomem *ioaddr = tp->mmio_addr;
2269
2270 /*
2271 * Some chips are unable to dump tally counters when the receiver
2272 * is disabled.
2273 */
2274 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
2275 return true;
2276
2277 return rtl8169_do_counters(dev, CounterDump);
2278 }
2279
2280 static bool rtl8169_init_counter_offsets(struct net_device *dev)
2281 {
2282 struct rtl8169_private *tp = netdev_priv(dev);
2283 struct rtl8169_counters *counters = tp->counters;
2284 bool ret = false;
2285
2286 /*
2287 * rtl8169_init_counter_offsets is called from rtl_open. On chip
2288 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
2289 * reset by a power cycle, while the counter values collected by the
2290 * driver are reset at every driver unload/load cycle.
2291 *
2292 * To make sure the HW values returned by @get_stats64 match the SW
2293 * values, we collect the initial values at first open(*) and use them
2294 * as offsets to normalize the values returned by @get_stats64.
2295 *
2296 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
2297 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
2298 * set at open time by rtl_hw_start.
2299 */
2300
2301 if (tp->tc_offset.inited)
2302 return true;
2303
2304 /* If both, reset and update fail, propagate to caller. */
2305 if (rtl8169_reset_counters(dev))
2306 ret = true;
2307
2308 if (rtl8169_update_counters(dev))
2309 ret = true;
2310
2311 tp->tc_offset.tx_errors = counters->tx_errors;
2312 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
2313 tp->tc_offset.tx_aborted = counters->tx_aborted;
2314 tp->tc_offset.inited = true;
2315
2316 return ret;
2317 }
2318
2319 static void rtl8169_get_ethtool_stats(struct net_device *dev,
2320 struct ethtool_stats *stats, u64 *data)
2321 {
2322 struct rtl8169_private *tp = netdev_priv(dev);
2323 struct device *d = &tp->pci_dev->dev;
2324 struct rtl8169_counters *counters = tp->counters;
2325
2326 ASSERT_RTNL();
2327
2328 pm_runtime_get_noresume(d);
2329
2330 if (pm_runtime_active(d))
2331 rtl8169_update_counters(dev);
2332
2333 pm_runtime_put_noidle(d);
2334
2335 data[0] = le64_to_cpu(counters->tx_packets);
2336 data[1] = le64_to_cpu(counters->rx_packets);
2337 data[2] = le64_to_cpu(counters->tx_errors);
2338 data[3] = le32_to_cpu(counters->rx_errors);
2339 data[4] = le16_to_cpu(counters->rx_missed);
2340 data[5] = le16_to_cpu(counters->align_errors);
2341 data[6] = le32_to_cpu(counters->tx_one_collision);
2342 data[7] = le32_to_cpu(counters->tx_multi_collision);
2343 data[8] = le64_to_cpu(counters->rx_unicast);
2344 data[9] = le64_to_cpu(counters->rx_broadcast);
2345 data[10] = le32_to_cpu(counters->rx_multicast);
2346 data[11] = le16_to_cpu(counters->tx_aborted);
2347 data[12] = le16_to_cpu(counters->tx_underun);
2348 }
2349
2350 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2351 {
2352 switch(stringset) {
2353 case ETH_SS_STATS:
2354 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2355 break;
2356 }
2357 }
2358
2359 static int rtl8169_nway_reset(struct net_device *dev)
2360 {
2361 struct rtl8169_private *tp = netdev_priv(dev);
2362
2363 return mii_nway_restart(&tp->mii);
2364 }
2365
2366 static const struct ethtool_ops rtl8169_ethtool_ops = {
2367 .get_drvinfo = rtl8169_get_drvinfo,
2368 .get_regs_len = rtl8169_get_regs_len,
2369 .get_link = ethtool_op_get_link,
2370 .set_settings = rtl8169_set_settings,
2371 .get_msglevel = rtl8169_get_msglevel,
2372 .set_msglevel = rtl8169_set_msglevel,
2373 .get_regs = rtl8169_get_regs,
2374 .get_wol = rtl8169_get_wol,
2375 .set_wol = rtl8169_set_wol,
2376 .get_strings = rtl8169_get_strings,
2377 .get_sset_count = rtl8169_get_sset_count,
2378 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2379 .get_ts_info = ethtool_op_get_ts_info,
2380 .nway_reset = rtl8169_nway_reset,
2381 .get_link_ksettings = rtl8169_get_link_ksettings,
2382 };
2383
2384 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2385 struct net_device *dev, u8 default_version)
2386 {
2387 void __iomem *ioaddr = tp->mmio_addr;
2388 /*
2389 * The driver currently handles the 8168Bf and the 8168Be identically
2390 * but they can be identified more specifically through the test below
2391 * if needed:
2392 *
2393 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2394 *
2395 * Same thing for the 8101Eb and the 8101Ec:
2396 *
2397 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2398 */
2399 static const struct rtl_mac_info {
2400 u32 mask;
2401 u32 val;
2402 int mac_version;
2403 } mac_info[] = {
2404 /* 8168EP family. */
2405 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2406 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2407 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2408
2409 /* 8168H family. */
2410 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2411 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2412
2413 /* 8168G family. */
2414 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
2415 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
2416 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2417 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2418
2419 /* 8168F family. */
2420 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
2421 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2422 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2423
2424 /* 8168E family. */
2425 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
2426 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2427 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2428 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2429
2430 /* 8168D family. */
2431 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2432 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
2433 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
2434
2435 /* 8168DP family. */
2436 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2437 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
2438 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
2439
2440 /* 8168C family. */
2441 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
2442 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
2443 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
2444 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
2445 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2446 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
2447 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
2448 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
2449 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
2450
2451 /* 8168B family. */
2452 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2453 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2454 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2455 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2456
2457 /* 8101 family. */
2458 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2459 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
2460 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
2461 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
2462 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2463 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2464 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2465 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2466 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2467 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2468 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2469 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2470 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
2471 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2472 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
2473 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2474 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2475 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
2476 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2477 /* FIXME: where did these entries come from ? -- FR */
2478 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2479 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2480
2481 /* 8110 family. */
2482 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2483 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2484 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2485 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2486 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2487 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2488
2489 /* Catch-all */
2490 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
2491 };
2492 const struct rtl_mac_info *p = mac_info;
2493 u32 reg;
2494
2495 reg = RTL_R32(TxConfig);
2496 while ((reg & p->mask) != p->val)
2497 p++;
2498 tp->mac_version = p->mac_version;
2499
2500 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2501 netif_notice(tp, probe, dev,
2502 "unknown MAC, using family default\n");
2503 tp->mac_version = default_version;
2504 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2505 tp->mac_version = tp->mii.supports_gmii ?
2506 RTL_GIGA_MAC_VER_42 :
2507 RTL_GIGA_MAC_VER_43;
2508 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2509 tp->mac_version = tp->mii.supports_gmii ?
2510 RTL_GIGA_MAC_VER_45 :
2511 RTL_GIGA_MAC_VER_47;
2512 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2513 tp->mac_version = tp->mii.supports_gmii ?
2514 RTL_GIGA_MAC_VER_46 :
2515 RTL_GIGA_MAC_VER_48;
2516 }
2517 }
2518
2519 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2520 {
2521 dprintk("mac_version = 0x%02x\n", tp->mac_version);
2522 }
2523
2524 struct phy_reg {
2525 u16 reg;
2526 u16 val;
2527 };
2528
2529 static void rtl_writephy_batch(struct rtl8169_private *tp,
2530 const struct phy_reg *regs, int len)
2531 {
2532 while (len-- > 0) {
2533 rtl_writephy(tp, regs->reg, regs->val);
2534 regs++;
2535 }
2536 }
2537
2538 #define PHY_READ 0x00000000
2539 #define PHY_DATA_OR 0x10000000
2540 #define PHY_DATA_AND 0x20000000
2541 #define PHY_BJMPN 0x30000000
2542 #define PHY_MDIO_CHG 0x40000000
2543 #define PHY_CLEAR_READCOUNT 0x70000000
2544 #define PHY_WRITE 0x80000000
2545 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2546 #define PHY_COMP_EQ_SKIPN 0xa0000000
2547 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2548 #define PHY_WRITE_PREVIOUS 0xc0000000
2549 #define PHY_SKIPN 0xd0000000
2550 #define PHY_DELAY_MS 0xe0000000
2551
2552 struct fw_info {
2553 u32 magic;
2554 char version[RTL_VER_SIZE];
2555 __le32 fw_start;
2556 __le32 fw_len;
2557 u8 chksum;
2558 } __packed;
2559
2560 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2561
2562 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2563 {
2564 const struct firmware *fw = rtl_fw->fw;
2565 struct fw_info *fw_info = (struct fw_info *)fw->data;
2566 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2567 char *version = rtl_fw->version;
2568 bool rc = false;
2569
2570 if (fw->size < FW_OPCODE_SIZE)
2571 goto out;
2572
2573 if (!fw_info->magic) {
2574 size_t i, size, start;
2575 u8 checksum = 0;
2576
2577 if (fw->size < sizeof(*fw_info))
2578 goto out;
2579
2580 for (i = 0; i < fw->size; i++)
2581 checksum += fw->data[i];
2582 if (checksum != 0)
2583 goto out;
2584
2585 start = le32_to_cpu(fw_info->fw_start);
2586 if (start > fw->size)
2587 goto out;
2588
2589 size = le32_to_cpu(fw_info->fw_len);
2590 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2591 goto out;
2592
2593 memcpy(version, fw_info->version, RTL_VER_SIZE);
2594
2595 pa->code = (__le32 *)(fw->data + start);
2596 pa->size = size;
2597 } else {
2598 if (fw->size % FW_OPCODE_SIZE)
2599 goto out;
2600
2601 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2602
2603 pa->code = (__le32 *)fw->data;
2604 pa->size = fw->size / FW_OPCODE_SIZE;
2605 }
2606 version[RTL_VER_SIZE - 1] = 0;
2607
2608 rc = true;
2609 out:
2610 return rc;
2611 }
2612
2613 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2614 struct rtl_fw_phy_action *pa)
2615 {
2616 bool rc = false;
2617 size_t index;
2618
2619 for (index = 0; index < pa->size; index++) {
2620 u32 action = le32_to_cpu(pa->code[index]);
2621 u32 regno = (action & 0x0fff0000) >> 16;
2622
2623 switch(action & 0xf0000000) {
2624 case PHY_READ:
2625 case PHY_DATA_OR:
2626 case PHY_DATA_AND:
2627 case PHY_MDIO_CHG:
2628 case PHY_CLEAR_READCOUNT:
2629 case PHY_WRITE:
2630 case PHY_WRITE_PREVIOUS:
2631 case PHY_DELAY_MS:
2632 break;
2633
2634 case PHY_BJMPN:
2635 if (regno > index) {
2636 netif_err(tp, ifup, tp->dev,
2637 "Out of range of firmware\n");
2638 goto out;
2639 }
2640 break;
2641 case PHY_READCOUNT_EQ_SKIP:
2642 if (index + 2 >= pa->size) {
2643 netif_err(tp, ifup, tp->dev,
2644 "Out of range of firmware\n");
2645 goto out;
2646 }
2647 break;
2648 case PHY_COMP_EQ_SKIPN:
2649 case PHY_COMP_NEQ_SKIPN:
2650 case PHY_SKIPN:
2651 if (index + 1 + regno >= pa->size) {
2652 netif_err(tp, ifup, tp->dev,
2653 "Out of range of firmware\n");
2654 goto out;
2655 }
2656 break;
2657
2658 default:
2659 netif_err(tp, ifup, tp->dev,
2660 "Invalid action 0x%08x\n", action);
2661 goto out;
2662 }
2663 }
2664 rc = true;
2665 out:
2666 return rc;
2667 }
2668
2669 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2670 {
2671 struct net_device *dev = tp->dev;
2672 int rc = -EINVAL;
2673
2674 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2675 netif_err(tp, ifup, dev, "invalid firmware\n");
2676 goto out;
2677 }
2678
2679 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2680 rc = 0;
2681 out:
2682 return rc;
2683 }
2684
2685 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2686 {
2687 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2688 struct mdio_ops org, *ops = &tp->mdio_ops;
2689 u32 predata, count;
2690 size_t index;
2691
2692 predata = count = 0;
2693 org.write = ops->write;
2694 org.read = ops->read;
2695
2696 for (index = 0; index < pa->size; ) {
2697 u32 action = le32_to_cpu(pa->code[index]);
2698 u32 data = action & 0x0000ffff;
2699 u32 regno = (action & 0x0fff0000) >> 16;
2700
2701 if (!action)
2702 break;
2703
2704 switch(action & 0xf0000000) {
2705 case PHY_READ:
2706 predata = rtl_readphy(tp, regno);
2707 count++;
2708 index++;
2709 break;
2710 case PHY_DATA_OR:
2711 predata |= data;
2712 index++;
2713 break;
2714 case PHY_DATA_AND:
2715 predata &= data;
2716 index++;
2717 break;
2718 case PHY_BJMPN:
2719 index -= regno;
2720 break;
2721 case PHY_MDIO_CHG:
2722 if (data == 0) {
2723 ops->write = org.write;
2724 ops->read = org.read;
2725 } else if (data == 1) {
2726 ops->write = mac_mcu_write;
2727 ops->read = mac_mcu_read;
2728 }
2729
2730 index++;
2731 break;
2732 case PHY_CLEAR_READCOUNT:
2733 count = 0;
2734 index++;
2735 break;
2736 case PHY_WRITE:
2737 rtl_writephy(tp, regno, data);
2738 index++;
2739 break;
2740 case PHY_READCOUNT_EQ_SKIP:
2741 index += (count == data) ? 2 : 1;
2742 break;
2743 case PHY_COMP_EQ_SKIPN:
2744 if (predata == data)
2745 index += regno;
2746 index++;
2747 break;
2748 case PHY_COMP_NEQ_SKIPN:
2749 if (predata != data)
2750 index += regno;
2751 index++;
2752 break;
2753 case PHY_WRITE_PREVIOUS:
2754 rtl_writephy(tp, regno, predata);
2755 index++;
2756 break;
2757 case PHY_SKIPN:
2758 index += regno + 1;
2759 break;
2760 case PHY_DELAY_MS:
2761 mdelay(data);
2762 index++;
2763 break;
2764
2765 default:
2766 BUG();
2767 }
2768 }
2769
2770 ops->write = org.write;
2771 ops->read = org.read;
2772 }
2773
2774 static void rtl_release_firmware(struct rtl8169_private *tp)
2775 {
2776 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2777 release_firmware(tp->rtl_fw->fw);
2778 kfree(tp->rtl_fw);
2779 }
2780 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2781 }
2782
2783 static void rtl_apply_firmware(struct rtl8169_private *tp)
2784 {
2785 struct rtl_fw *rtl_fw = tp->rtl_fw;
2786
2787 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2788 if (!IS_ERR_OR_NULL(rtl_fw))
2789 rtl_phy_write_fw(tp, rtl_fw);
2790 }
2791
2792 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2793 {
2794 if (rtl_readphy(tp, reg) != val)
2795 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2796 else
2797 rtl_apply_firmware(tp);
2798 }
2799
2800 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2801 {
2802 static const struct phy_reg phy_reg_init[] = {
2803 { 0x1f, 0x0001 },
2804 { 0x06, 0x006e },
2805 { 0x08, 0x0708 },
2806 { 0x15, 0x4000 },
2807 { 0x18, 0x65c7 },
2808
2809 { 0x1f, 0x0001 },
2810 { 0x03, 0x00a1 },
2811 { 0x02, 0x0008 },
2812 { 0x01, 0x0120 },
2813 { 0x00, 0x1000 },
2814 { 0x04, 0x0800 },
2815 { 0x04, 0x0000 },
2816
2817 { 0x03, 0xff41 },
2818 { 0x02, 0xdf60 },
2819 { 0x01, 0x0140 },
2820 { 0x00, 0x0077 },
2821 { 0x04, 0x7800 },
2822 { 0x04, 0x7000 },
2823
2824 { 0x03, 0x802f },
2825 { 0x02, 0x4f02 },
2826 { 0x01, 0x0409 },
2827 { 0x00, 0xf0f9 },
2828 { 0x04, 0x9800 },
2829 { 0x04, 0x9000 },
2830
2831 { 0x03, 0xdf01 },
2832 { 0x02, 0xdf20 },
2833 { 0x01, 0xff95 },
2834 { 0x00, 0xba00 },
2835 { 0x04, 0xa800 },
2836 { 0x04, 0xa000 },
2837
2838 { 0x03, 0xff41 },
2839 { 0x02, 0xdf20 },
2840 { 0x01, 0x0140 },
2841 { 0x00, 0x00bb },
2842 { 0x04, 0xb800 },
2843 { 0x04, 0xb000 },
2844
2845 { 0x03, 0xdf41 },
2846 { 0x02, 0xdc60 },
2847 { 0x01, 0x6340 },
2848 { 0x00, 0x007d },
2849 { 0x04, 0xd800 },
2850 { 0x04, 0xd000 },
2851
2852 { 0x03, 0xdf01 },
2853 { 0x02, 0xdf20 },
2854 { 0x01, 0x100a },
2855 { 0x00, 0xa0ff },
2856 { 0x04, 0xf800 },
2857 { 0x04, 0xf000 },
2858
2859 { 0x1f, 0x0000 },
2860 { 0x0b, 0x0000 },
2861 { 0x00, 0x9200 }
2862 };
2863
2864 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2865 }
2866
2867 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2868 {
2869 static const struct phy_reg phy_reg_init[] = {
2870 { 0x1f, 0x0002 },
2871 { 0x01, 0x90d0 },
2872 { 0x1f, 0x0000 }
2873 };
2874
2875 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2876 }
2877
2878 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2879 {
2880 struct pci_dev *pdev = tp->pci_dev;
2881
2882 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2883 (pdev->subsystem_device != 0xe000))
2884 return;
2885
2886 rtl_writephy(tp, 0x1f, 0x0001);
2887 rtl_writephy(tp, 0x10, 0xf01b);
2888 rtl_writephy(tp, 0x1f, 0x0000);
2889 }
2890
2891 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2892 {
2893 static const struct phy_reg phy_reg_init[] = {
2894 { 0x1f, 0x0001 },
2895 { 0x04, 0x0000 },
2896 { 0x03, 0x00a1 },
2897 { 0x02, 0x0008 },
2898 { 0x01, 0x0120 },
2899 { 0x00, 0x1000 },
2900 { 0x04, 0x0800 },
2901 { 0x04, 0x9000 },
2902 { 0x03, 0x802f },
2903 { 0x02, 0x4f02 },
2904 { 0x01, 0x0409 },
2905 { 0x00, 0xf099 },
2906 { 0x04, 0x9800 },
2907 { 0x04, 0xa000 },
2908 { 0x03, 0xdf01 },
2909 { 0x02, 0xdf20 },
2910 { 0x01, 0xff95 },
2911 { 0x00, 0xba00 },
2912 { 0x04, 0xa800 },
2913 { 0x04, 0xf000 },
2914 { 0x03, 0xdf01 },
2915 { 0x02, 0xdf20 },
2916 { 0x01, 0x101a },
2917 { 0x00, 0xa0ff },
2918 { 0x04, 0xf800 },
2919 { 0x04, 0x0000 },
2920 { 0x1f, 0x0000 },
2921
2922 { 0x1f, 0x0001 },
2923 { 0x10, 0xf41b },
2924 { 0x14, 0xfb54 },
2925 { 0x18, 0xf5c7 },
2926 { 0x1f, 0x0000 },
2927
2928 { 0x1f, 0x0001 },
2929 { 0x17, 0x0cc0 },
2930 { 0x1f, 0x0000 }
2931 };
2932
2933 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2934
2935 rtl8169scd_hw_phy_config_quirk(tp);
2936 }
2937
2938 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2939 {
2940 static const struct phy_reg phy_reg_init[] = {
2941 { 0x1f, 0x0001 },
2942 { 0x04, 0x0000 },
2943 { 0x03, 0x00a1 },
2944 { 0x02, 0x0008 },
2945 { 0x01, 0x0120 },
2946 { 0x00, 0x1000 },
2947 { 0x04, 0x0800 },
2948 { 0x04, 0x9000 },
2949 { 0x03, 0x802f },
2950 { 0x02, 0x4f02 },
2951 { 0x01, 0x0409 },
2952 { 0x00, 0xf099 },
2953 { 0x04, 0x9800 },
2954 { 0x04, 0xa000 },
2955 { 0x03, 0xdf01 },
2956 { 0x02, 0xdf20 },
2957 { 0x01, 0xff95 },
2958 { 0x00, 0xba00 },
2959 { 0x04, 0xa800 },
2960 { 0x04, 0xf000 },
2961 { 0x03, 0xdf01 },
2962 { 0x02, 0xdf20 },
2963 { 0x01, 0x101a },
2964 { 0x00, 0xa0ff },
2965 { 0x04, 0xf800 },
2966 { 0x04, 0x0000 },
2967 { 0x1f, 0x0000 },
2968
2969 { 0x1f, 0x0001 },
2970 { 0x0b, 0x8480 },
2971 { 0x1f, 0x0000 },
2972
2973 { 0x1f, 0x0001 },
2974 { 0x18, 0x67c7 },
2975 { 0x04, 0x2000 },
2976 { 0x03, 0x002f },
2977 { 0x02, 0x4360 },
2978 { 0x01, 0x0109 },
2979 { 0x00, 0x3022 },
2980 { 0x04, 0x2800 },
2981 { 0x1f, 0x0000 },
2982
2983 { 0x1f, 0x0001 },
2984 { 0x17, 0x0cc0 },
2985 { 0x1f, 0x0000 }
2986 };
2987
2988 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2989 }
2990
2991 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2992 {
2993 static const struct phy_reg phy_reg_init[] = {
2994 { 0x10, 0xf41b },
2995 { 0x1f, 0x0000 }
2996 };
2997
2998 rtl_writephy(tp, 0x1f, 0x0001);
2999 rtl_patchphy(tp, 0x16, 1 << 0);
3000
3001 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3002 }
3003
3004 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
3005 {
3006 static const struct phy_reg phy_reg_init[] = {
3007 { 0x1f, 0x0001 },
3008 { 0x10, 0xf41b },
3009 { 0x1f, 0x0000 }
3010 };
3011
3012 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3013 }
3014
3015 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
3016 {
3017 static const struct phy_reg phy_reg_init[] = {
3018 { 0x1f, 0x0000 },
3019 { 0x1d, 0x0f00 },
3020 { 0x1f, 0x0002 },
3021 { 0x0c, 0x1ec8 },
3022 { 0x1f, 0x0000 }
3023 };
3024
3025 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3026 }
3027
3028 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
3029 {
3030 static const struct phy_reg phy_reg_init[] = {
3031 { 0x1f, 0x0001 },
3032 { 0x1d, 0x3d98 },
3033 { 0x1f, 0x0000 }
3034 };
3035
3036 rtl_writephy(tp, 0x1f, 0x0000);
3037 rtl_patchphy(tp, 0x14, 1 << 5);
3038 rtl_patchphy(tp, 0x0d, 1 << 5);
3039
3040 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3041 }
3042
3043 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
3044 {
3045 static const struct phy_reg phy_reg_init[] = {
3046 { 0x1f, 0x0001 },
3047 { 0x12, 0x2300 },
3048 { 0x1f, 0x0002 },
3049 { 0x00, 0x88d4 },
3050 { 0x01, 0x82b1 },
3051 { 0x03, 0x7002 },
3052 { 0x08, 0x9e30 },
3053 { 0x09, 0x01f0 },
3054 { 0x0a, 0x5500 },
3055 { 0x0c, 0x00c8 },
3056 { 0x1f, 0x0003 },
3057 { 0x12, 0xc096 },
3058 { 0x16, 0x000a },
3059 { 0x1f, 0x0000 },
3060 { 0x1f, 0x0000 },
3061 { 0x09, 0x2000 },
3062 { 0x09, 0x0000 }
3063 };
3064
3065 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3066
3067 rtl_patchphy(tp, 0x14, 1 << 5);
3068 rtl_patchphy(tp, 0x0d, 1 << 5);
3069 rtl_writephy(tp, 0x1f, 0x0000);
3070 }
3071
3072 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
3073 {
3074 static const struct phy_reg phy_reg_init[] = {
3075 { 0x1f, 0x0001 },
3076 { 0x12, 0x2300 },
3077 { 0x03, 0x802f },
3078 { 0x02, 0x4f02 },
3079 { 0x01, 0x0409 },
3080 { 0x00, 0xf099 },
3081 { 0x04, 0x9800 },
3082 { 0x04, 0x9000 },
3083 { 0x1d, 0x3d98 },
3084 { 0x1f, 0x0002 },
3085 { 0x0c, 0x7eb8 },
3086 { 0x06, 0x0761 },
3087 { 0x1f, 0x0003 },
3088 { 0x16, 0x0f0a },
3089 { 0x1f, 0x0000 }
3090 };
3091
3092 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3093
3094 rtl_patchphy(tp, 0x16, 1 << 0);
3095 rtl_patchphy(tp, 0x14, 1 << 5);
3096 rtl_patchphy(tp, 0x0d, 1 << 5);
3097 rtl_writephy(tp, 0x1f, 0x0000);
3098 }
3099
3100 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
3101 {
3102 static const struct phy_reg phy_reg_init[] = {
3103 { 0x1f, 0x0001 },
3104 { 0x12, 0x2300 },
3105 { 0x1d, 0x3d98 },
3106 { 0x1f, 0x0002 },
3107 { 0x0c, 0x7eb8 },
3108 { 0x06, 0x5461 },
3109 { 0x1f, 0x0003 },
3110 { 0x16, 0x0f0a },
3111 { 0x1f, 0x0000 }
3112 };
3113
3114 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3115
3116 rtl_patchphy(tp, 0x16, 1 << 0);
3117 rtl_patchphy(tp, 0x14, 1 << 5);
3118 rtl_patchphy(tp, 0x0d, 1 << 5);
3119 rtl_writephy(tp, 0x1f, 0x0000);
3120 }
3121
3122 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
3123 {
3124 rtl8168c_3_hw_phy_config(tp);
3125 }
3126
3127 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
3128 {
3129 static const struct phy_reg phy_reg_init_0[] = {
3130 /* Channel Estimation */
3131 { 0x1f, 0x0001 },
3132 { 0x06, 0x4064 },
3133 { 0x07, 0x2863 },
3134 { 0x08, 0x059c },
3135 { 0x09, 0x26b4 },
3136 { 0x0a, 0x6a19 },
3137 { 0x0b, 0xdcc8 },
3138 { 0x10, 0xf06d },
3139 { 0x14, 0x7f68 },
3140 { 0x18, 0x7fd9 },
3141 { 0x1c, 0xf0ff },
3142 { 0x1d, 0x3d9c },
3143 { 0x1f, 0x0003 },
3144 { 0x12, 0xf49f },
3145 { 0x13, 0x070b },
3146 { 0x1a, 0x05ad },
3147 { 0x14, 0x94c0 },
3148
3149 /*
3150 * Tx Error Issue
3151 * Enhance line driver power
3152 */
3153 { 0x1f, 0x0002 },
3154 { 0x06, 0x5561 },
3155 { 0x1f, 0x0005 },
3156 { 0x05, 0x8332 },
3157 { 0x06, 0x5561 },
3158
3159 /*
3160 * Can not link to 1Gbps with bad cable
3161 * Decrease SNR threshold form 21.07dB to 19.04dB
3162 */
3163 { 0x1f, 0x0001 },
3164 { 0x17, 0x0cc0 },
3165
3166 { 0x1f, 0x0000 },
3167 { 0x0d, 0xf880 }
3168 };
3169
3170 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3171
3172 /*
3173 * Rx Error Issue
3174 * Fine Tune Switching regulator parameter
3175 */
3176 rtl_writephy(tp, 0x1f, 0x0002);
3177 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3178 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
3179
3180 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3181 static const struct phy_reg phy_reg_init[] = {
3182 { 0x1f, 0x0002 },
3183 { 0x05, 0x669a },
3184 { 0x1f, 0x0005 },
3185 { 0x05, 0x8330 },
3186 { 0x06, 0x669a },
3187 { 0x1f, 0x0002 }
3188 };
3189 int val;
3190
3191 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3192
3193 val = rtl_readphy(tp, 0x0d);
3194
3195 if ((val & 0x00ff) != 0x006c) {
3196 static const u32 set[] = {
3197 0x0065, 0x0066, 0x0067, 0x0068,
3198 0x0069, 0x006a, 0x006b, 0x006c
3199 };
3200 int i;
3201
3202 rtl_writephy(tp, 0x1f, 0x0002);
3203
3204 val &= 0xff00;
3205 for (i = 0; i < ARRAY_SIZE(set); i++)
3206 rtl_writephy(tp, 0x0d, val | set[i]);
3207 }
3208 } else {
3209 static const struct phy_reg phy_reg_init[] = {
3210 { 0x1f, 0x0002 },
3211 { 0x05, 0x6662 },
3212 { 0x1f, 0x0005 },
3213 { 0x05, 0x8330 },
3214 { 0x06, 0x6662 }
3215 };
3216
3217 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3218 }
3219
3220 /* RSET couple improve */
3221 rtl_writephy(tp, 0x1f, 0x0002);
3222 rtl_patchphy(tp, 0x0d, 0x0300);
3223 rtl_patchphy(tp, 0x0f, 0x0010);
3224
3225 /* Fine tune PLL performance */
3226 rtl_writephy(tp, 0x1f, 0x0002);
3227 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3228 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3229
3230 rtl_writephy(tp, 0x1f, 0x0005);
3231 rtl_writephy(tp, 0x05, 0x001b);
3232
3233 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3234
3235 rtl_writephy(tp, 0x1f, 0x0000);
3236 }
3237
3238 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3239 {
3240 static const struct phy_reg phy_reg_init_0[] = {
3241 /* Channel Estimation */
3242 { 0x1f, 0x0001 },
3243 { 0x06, 0x4064 },
3244 { 0x07, 0x2863 },
3245 { 0x08, 0x059c },
3246 { 0x09, 0x26b4 },
3247 { 0x0a, 0x6a19 },
3248 { 0x0b, 0xdcc8 },
3249 { 0x10, 0xf06d },
3250 { 0x14, 0x7f68 },
3251 { 0x18, 0x7fd9 },
3252 { 0x1c, 0xf0ff },
3253 { 0x1d, 0x3d9c },
3254 { 0x1f, 0x0003 },
3255 { 0x12, 0xf49f },
3256 { 0x13, 0x070b },
3257 { 0x1a, 0x05ad },
3258 { 0x14, 0x94c0 },
3259
3260 /*
3261 * Tx Error Issue
3262 * Enhance line driver power
3263 */
3264 { 0x1f, 0x0002 },
3265 { 0x06, 0x5561 },
3266 { 0x1f, 0x0005 },
3267 { 0x05, 0x8332 },
3268 { 0x06, 0x5561 },
3269
3270 /*
3271 * Can not link to 1Gbps with bad cable
3272 * Decrease SNR threshold form 21.07dB to 19.04dB
3273 */
3274 { 0x1f, 0x0001 },
3275 { 0x17, 0x0cc0 },
3276
3277 { 0x1f, 0x0000 },
3278 { 0x0d, 0xf880 }
3279 };
3280
3281 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3282
3283 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3284 static const struct phy_reg phy_reg_init[] = {
3285 { 0x1f, 0x0002 },
3286 { 0x05, 0x669a },
3287 { 0x1f, 0x0005 },
3288 { 0x05, 0x8330 },
3289 { 0x06, 0x669a },
3290
3291 { 0x1f, 0x0002 }
3292 };
3293 int val;
3294
3295 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3296
3297 val = rtl_readphy(tp, 0x0d);
3298 if ((val & 0x00ff) != 0x006c) {
3299 static const u32 set[] = {
3300 0x0065, 0x0066, 0x0067, 0x0068,
3301 0x0069, 0x006a, 0x006b, 0x006c
3302 };
3303 int i;
3304
3305 rtl_writephy(tp, 0x1f, 0x0002);
3306
3307 val &= 0xff00;
3308 for (i = 0; i < ARRAY_SIZE(set); i++)
3309 rtl_writephy(tp, 0x0d, val | set[i]);
3310 }
3311 } else {
3312 static const struct phy_reg phy_reg_init[] = {
3313 { 0x1f, 0x0002 },
3314 { 0x05, 0x2642 },
3315 { 0x1f, 0x0005 },
3316 { 0x05, 0x8330 },
3317 { 0x06, 0x2642 }
3318 };
3319
3320 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3321 }
3322
3323 /* Fine tune PLL performance */
3324 rtl_writephy(tp, 0x1f, 0x0002);
3325 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3326 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3327
3328 /* Switching regulator Slew rate */
3329 rtl_writephy(tp, 0x1f, 0x0002);
3330 rtl_patchphy(tp, 0x0f, 0x0017);
3331
3332 rtl_writephy(tp, 0x1f, 0x0005);
3333 rtl_writephy(tp, 0x05, 0x001b);
3334
3335 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3336
3337 rtl_writephy(tp, 0x1f, 0x0000);
3338 }
3339
3340 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3341 {
3342 static const struct phy_reg phy_reg_init[] = {
3343 { 0x1f, 0x0002 },
3344 { 0x10, 0x0008 },
3345 { 0x0d, 0x006c },
3346
3347 { 0x1f, 0x0000 },
3348 { 0x0d, 0xf880 },
3349
3350 { 0x1f, 0x0001 },
3351 { 0x17, 0x0cc0 },
3352
3353 { 0x1f, 0x0001 },
3354 { 0x0b, 0xa4d8 },
3355 { 0x09, 0x281c },
3356 { 0x07, 0x2883 },
3357 { 0x0a, 0x6b35 },
3358 { 0x1d, 0x3da4 },
3359 { 0x1c, 0xeffd },
3360 { 0x14, 0x7f52 },
3361 { 0x18, 0x7fc6 },
3362 { 0x08, 0x0601 },
3363 { 0x06, 0x4063 },
3364 { 0x10, 0xf074 },
3365 { 0x1f, 0x0003 },
3366 { 0x13, 0x0789 },
3367 { 0x12, 0xf4bd },
3368 { 0x1a, 0x04fd },
3369 { 0x14, 0x84b0 },
3370 { 0x1f, 0x0000 },
3371 { 0x00, 0x9200 },
3372
3373 { 0x1f, 0x0005 },
3374 { 0x01, 0x0340 },
3375 { 0x1f, 0x0001 },
3376 { 0x04, 0x4000 },
3377 { 0x03, 0x1d21 },
3378 { 0x02, 0x0c32 },
3379 { 0x01, 0x0200 },
3380 { 0x00, 0x5554 },
3381 { 0x04, 0x4800 },
3382 { 0x04, 0x4000 },
3383 { 0x04, 0xf000 },
3384 { 0x03, 0xdf01 },
3385 { 0x02, 0xdf20 },
3386 { 0x01, 0x101a },
3387 { 0x00, 0xa0ff },
3388 { 0x04, 0xf800 },
3389 { 0x04, 0xf000 },
3390 { 0x1f, 0x0000 },
3391
3392 { 0x1f, 0x0007 },
3393 { 0x1e, 0x0023 },
3394 { 0x16, 0x0000 },
3395 { 0x1f, 0x0000 }
3396 };
3397
3398 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3399 }
3400
3401 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3402 {
3403 static const struct phy_reg phy_reg_init[] = {
3404 { 0x1f, 0x0001 },
3405 { 0x17, 0x0cc0 },
3406
3407 { 0x1f, 0x0007 },
3408 { 0x1e, 0x002d },
3409 { 0x18, 0x0040 },
3410 { 0x1f, 0x0000 }
3411 };
3412
3413 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3414 rtl_patchphy(tp, 0x0d, 1 << 5);
3415 }
3416
3417 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3418 {
3419 static const struct phy_reg phy_reg_init[] = {
3420 /* Enable Delay cap */
3421 { 0x1f, 0x0005 },
3422 { 0x05, 0x8b80 },
3423 { 0x06, 0xc896 },
3424 { 0x1f, 0x0000 },
3425
3426 /* Channel estimation fine tune */
3427 { 0x1f, 0x0001 },
3428 { 0x0b, 0x6c20 },
3429 { 0x07, 0x2872 },
3430 { 0x1c, 0xefff },
3431 { 0x1f, 0x0003 },
3432 { 0x14, 0x6420 },
3433 { 0x1f, 0x0000 },
3434
3435 /* Update PFM & 10M TX idle timer */
3436 { 0x1f, 0x0007 },
3437 { 0x1e, 0x002f },
3438 { 0x15, 0x1919 },
3439 { 0x1f, 0x0000 },
3440
3441 { 0x1f, 0x0007 },
3442 { 0x1e, 0x00ac },
3443 { 0x18, 0x0006 },
3444 { 0x1f, 0x0000 }
3445 };
3446
3447 rtl_apply_firmware(tp);
3448
3449 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3450
3451 /* DCO enable for 10M IDLE Power */
3452 rtl_writephy(tp, 0x1f, 0x0007);
3453 rtl_writephy(tp, 0x1e, 0x0023);
3454 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3455 rtl_writephy(tp, 0x1f, 0x0000);
3456
3457 /* For impedance matching */
3458 rtl_writephy(tp, 0x1f, 0x0002);
3459 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3460 rtl_writephy(tp, 0x1f, 0x0000);
3461
3462 /* PHY auto speed down */
3463 rtl_writephy(tp, 0x1f, 0x0007);
3464 rtl_writephy(tp, 0x1e, 0x002d);
3465 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3466 rtl_writephy(tp, 0x1f, 0x0000);
3467 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3468
3469 rtl_writephy(tp, 0x1f, 0x0005);
3470 rtl_writephy(tp, 0x05, 0x8b86);
3471 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3472 rtl_writephy(tp, 0x1f, 0x0000);
3473
3474 rtl_writephy(tp, 0x1f, 0x0005);
3475 rtl_writephy(tp, 0x05, 0x8b85);
3476 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3477 rtl_writephy(tp, 0x1f, 0x0007);
3478 rtl_writephy(tp, 0x1e, 0x0020);
3479 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3480 rtl_writephy(tp, 0x1f, 0x0006);
3481 rtl_writephy(tp, 0x00, 0x5a00);
3482 rtl_writephy(tp, 0x1f, 0x0000);
3483 rtl_writephy(tp, 0x0d, 0x0007);
3484 rtl_writephy(tp, 0x0e, 0x003c);
3485 rtl_writephy(tp, 0x0d, 0x4007);
3486 rtl_writephy(tp, 0x0e, 0x0000);
3487 rtl_writephy(tp, 0x0d, 0x0000);
3488 }
3489
3490 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3491 {
3492 const u16 w[] = {
3493 addr[0] | (addr[1] << 8),
3494 addr[2] | (addr[3] << 8),
3495 addr[4] | (addr[5] << 8)
3496 };
3497 const struct exgmac_reg e[] = {
3498 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3499 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3500 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3501 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3502 };
3503
3504 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3505 }
3506
3507 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3508 {
3509 static const struct phy_reg phy_reg_init[] = {
3510 /* Enable Delay cap */
3511 { 0x1f, 0x0004 },
3512 { 0x1f, 0x0007 },
3513 { 0x1e, 0x00ac },
3514 { 0x18, 0x0006 },
3515 { 0x1f, 0x0002 },
3516 { 0x1f, 0x0000 },
3517 { 0x1f, 0x0000 },
3518
3519 /* Channel estimation fine tune */
3520 { 0x1f, 0x0003 },
3521 { 0x09, 0xa20f },
3522 { 0x1f, 0x0000 },
3523 { 0x1f, 0x0000 },
3524
3525 /* Green Setting */
3526 { 0x1f, 0x0005 },
3527 { 0x05, 0x8b5b },
3528 { 0x06, 0x9222 },
3529 { 0x05, 0x8b6d },
3530 { 0x06, 0x8000 },
3531 { 0x05, 0x8b76 },
3532 { 0x06, 0x8000 },
3533 { 0x1f, 0x0000 }
3534 };
3535
3536 rtl_apply_firmware(tp);
3537
3538 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3539
3540 /* For 4-corner performance improve */
3541 rtl_writephy(tp, 0x1f, 0x0005);
3542 rtl_writephy(tp, 0x05, 0x8b80);
3543 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3544 rtl_writephy(tp, 0x1f, 0x0000);
3545
3546 /* PHY auto speed down */
3547 rtl_writephy(tp, 0x1f, 0x0004);
3548 rtl_writephy(tp, 0x1f, 0x0007);
3549 rtl_writephy(tp, 0x1e, 0x002d);
3550 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3551 rtl_writephy(tp, 0x1f, 0x0002);
3552 rtl_writephy(tp, 0x1f, 0x0000);
3553 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3554
3555 /* improve 10M EEE waveform */
3556 rtl_writephy(tp, 0x1f, 0x0005);
3557 rtl_writephy(tp, 0x05, 0x8b86);
3558 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3559 rtl_writephy(tp, 0x1f, 0x0000);
3560
3561 /* Improve 2-pair detection performance */
3562 rtl_writephy(tp, 0x1f, 0x0005);
3563 rtl_writephy(tp, 0x05, 0x8b85);
3564 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3565 rtl_writephy(tp, 0x1f, 0x0000);
3566
3567 /* EEE setting */
3568 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3569 rtl_writephy(tp, 0x1f, 0x0005);
3570 rtl_writephy(tp, 0x05, 0x8b85);
3571 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3572 rtl_writephy(tp, 0x1f, 0x0004);
3573 rtl_writephy(tp, 0x1f, 0x0007);
3574 rtl_writephy(tp, 0x1e, 0x0020);
3575 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3576 rtl_writephy(tp, 0x1f, 0x0002);
3577 rtl_writephy(tp, 0x1f, 0x0000);
3578 rtl_writephy(tp, 0x0d, 0x0007);
3579 rtl_writephy(tp, 0x0e, 0x003c);
3580 rtl_writephy(tp, 0x0d, 0x4007);
3581 rtl_writephy(tp, 0x0e, 0x0000);
3582 rtl_writephy(tp, 0x0d, 0x0000);
3583
3584 /* Green feature */
3585 rtl_writephy(tp, 0x1f, 0x0003);
3586 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3587 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3588 rtl_writephy(tp, 0x1f, 0x0000);
3589
3590 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3591 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3592 }
3593
3594 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3595 {
3596 /* For 4-corner performance improve */
3597 rtl_writephy(tp, 0x1f, 0x0005);
3598 rtl_writephy(tp, 0x05, 0x8b80);
3599 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3600 rtl_writephy(tp, 0x1f, 0x0000);
3601
3602 /* PHY auto speed down */
3603 rtl_writephy(tp, 0x1f, 0x0007);
3604 rtl_writephy(tp, 0x1e, 0x002d);
3605 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3606 rtl_writephy(tp, 0x1f, 0x0000);
3607 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3608
3609 /* Improve 10M EEE waveform */
3610 rtl_writephy(tp, 0x1f, 0x0005);
3611 rtl_writephy(tp, 0x05, 0x8b86);
3612 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3613 rtl_writephy(tp, 0x1f, 0x0000);
3614 }
3615
3616 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3617 {
3618 static const struct phy_reg phy_reg_init[] = {
3619 /* Channel estimation fine tune */
3620 { 0x1f, 0x0003 },
3621 { 0x09, 0xa20f },
3622 { 0x1f, 0x0000 },
3623
3624 /* Modify green table for giga & fnet */
3625 { 0x1f, 0x0005 },
3626 { 0x05, 0x8b55 },
3627 { 0x06, 0x0000 },
3628 { 0x05, 0x8b5e },
3629 { 0x06, 0x0000 },
3630 { 0x05, 0x8b67 },
3631 { 0x06, 0x0000 },
3632 { 0x05, 0x8b70 },
3633 { 0x06, 0x0000 },
3634 { 0x1f, 0x0000 },
3635 { 0x1f, 0x0007 },
3636 { 0x1e, 0x0078 },
3637 { 0x17, 0x0000 },
3638 { 0x19, 0x00fb },
3639 { 0x1f, 0x0000 },
3640
3641 /* Modify green table for 10M */
3642 { 0x1f, 0x0005 },
3643 { 0x05, 0x8b79 },
3644 { 0x06, 0xaa00 },
3645 { 0x1f, 0x0000 },
3646
3647 /* Disable hiimpedance detection (RTCT) */
3648 { 0x1f, 0x0003 },
3649 { 0x01, 0x328a },
3650 { 0x1f, 0x0000 }
3651 };
3652
3653 rtl_apply_firmware(tp);
3654
3655 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3656
3657 rtl8168f_hw_phy_config(tp);
3658
3659 /* Improve 2-pair detection performance */
3660 rtl_writephy(tp, 0x1f, 0x0005);
3661 rtl_writephy(tp, 0x05, 0x8b85);
3662 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3663 rtl_writephy(tp, 0x1f, 0x0000);
3664 }
3665
3666 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3667 {
3668 rtl_apply_firmware(tp);
3669
3670 rtl8168f_hw_phy_config(tp);
3671 }
3672
3673 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3674 {
3675 static const struct phy_reg phy_reg_init[] = {
3676 /* Channel estimation fine tune */
3677 { 0x1f, 0x0003 },
3678 { 0x09, 0xa20f },
3679 { 0x1f, 0x0000 },
3680
3681 /* Modify green table for giga & fnet */
3682 { 0x1f, 0x0005 },
3683 { 0x05, 0x8b55 },
3684 { 0x06, 0x0000 },
3685 { 0x05, 0x8b5e },
3686 { 0x06, 0x0000 },
3687 { 0x05, 0x8b67 },
3688 { 0x06, 0x0000 },
3689 { 0x05, 0x8b70 },
3690 { 0x06, 0x0000 },
3691 { 0x1f, 0x0000 },
3692 { 0x1f, 0x0007 },
3693 { 0x1e, 0x0078 },
3694 { 0x17, 0x0000 },
3695 { 0x19, 0x00aa },
3696 { 0x1f, 0x0000 },
3697
3698 /* Modify green table for 10M */
3699 { 0x1f, 0x0005 },
3700 { 0x05, 0x8b79 },
3701 { 0x06, 0xaa00 },
3702 { 0x1f, 0x0000 },
3703
3704 /* Disable hiimpedance detection (RTCT) */
3705 { 0x1f, 0x0003 },
3706 { 0x01, 0x328a },
3707 { 0x1f, 0x0000 }
3708 };
3709
3710
3711 rtl_apply_firmware(tp);
3712
3713 rtl8168f_hw_phy_config(tp);
3714
3715 /* Improve 2-pair detection performance */
3716 rtl_writephy(tp, 0x1f, 0x0005);
3717 rtl_writephy(tp, 0x05, 0x8b85);
3718 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3719 rtl_writephy(tp, 0x1f, 0x0000);
3720
3721 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3722
3723 /* Modify green table for giga */
3724 rtl_writephy(tp, 0x1f, 0x0005);
3725 rtl_writephy(tp, 0x05, 0x8b54);
3726 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3727 rtl_writephy(tp, 0x05, 0x8b5d);
3728 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3729 rtl_writephy(tp, 0x05, 0x8a7c);
3730 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3731 rtl_writephy(tp, 0x05, 0x8a7f);
3732 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3733 rtl_writephy(tp, 0x05, 0x8a82);
3734 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3735 rtl_writephy(tp, 0x05, 0x8a85);
3736 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3737 rtl_writephy(tp, 0x05, 0x8a88);
3738 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3739 rtl_writephy(tp, 0x1f, 0x0000);
3740
3741 /* uc same-seed solution */
3742 rtl_writephy(tp, 0x1f, 0x0005);
3743 rtl_writephy(tp, 0x05, 0x8b85);
3744 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3745 rtl_writephy(tp, 0x1f, 0x0000);
3746
3747 /* eee setting */
3748 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3749 rtl_writephy(tp, 0x1f, 0x0005);
3750 rtl_writephy(tp, 0x05, 0x8b85);
3751 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3752 rtl_writephy(tp, 0x1f, 0x0004);
3753 rtl_writephy(tp, 0x1f, 0x0007);
3754 rtl_writephy(tp, 0x1e, 0x0020);
3755 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3756 rtl_writephy(tp, 0x1f, 0x0000);
3757 rtl_writephy(tp, 0x0d, 0x0007);
3758 rtl_writephy(tp, 0x0e, 0x003c);
3759 rtl_writephy(tp, 0x0d, 0x4007);
3760 rtl_writephy(tp, 0x0e, 0x0000);
3761 rtl_writephy(tp, 0x0d, 0x0000);
3762
3763 /* Green feature */
3764 rtl_writephy(tp, 0x1f, 0x0003);
3765 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3766 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3767 rtl_writephy(tp, 0x1f, 0x0000);
3768 }
3769
3770 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3771 {
3772 rtl_apply_firmware(tp);
3773
3774 rtl_writephy(tp, 0x1f, 0x0a46);
3775 if (rtl_readphy(tp, 0x10) & 0x0100) {
3776 rtl_writephy(tp, 0x1f, 0x0bcc);
3777 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3778 } else {
3779 rtl_writephy(tp, 0x1f, 0x0bcc);
3780 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3781 }
3782
3783 rtl_writephy(tp, 0x1f, 0x0a46);
3784 if (rtl_readphy(tp, 0x13) & 0x0100) {
3785 rtl_writephy(tp, 0x1f, 0x0c41);
3786 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3787 } else {
3788 rtl_writephy(tp, 0x1f, 0x0c41);
3789 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3790 }
3791
3792 /* Enable PHY auto speed down */
3793 rtl_writephy(tp, 0x1f, 0x0a44);
3794 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3795
3796 rtl_writephy(tp, 0x1f, 0x0bcc);
3797 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3798 rtl_writephy(tp, 0x1f, 0x0a44);
3799 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3800 rtl_writephy(tp, 0x1f, 0x0a43);
3801 rtl_writephy(tp, 0x13, 0x8084);
3802 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3803 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3804
3805 /* EEE auto-fallback function */
3806 rtl_writephy(tp, 0x1f, 0x0a4b);
3807 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3808
3809 /* Enable UC LPF tune function */
3810 rtl_writephy(tp, 0x1f, 0x0a43);
3811 rtl_writephy(tp, 0x13, 0x8012);
3812 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3813
3814 rtl_writephy(tp, 0x1f, 0x0c42);
3815 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3816
3817 /* Improve SWR Efficiency */
3818 rtl_writephy(tp, 0x1f, 0x0bcd);
3819 rtl_writephy(tp, 0x14, 0x5065);
3820 rtl_writephy(tp, 0x14, 0xd065);
3821 rtl_writephy(tp, 0x1f, 0x0bc8);
3822 rtl_writephy(tp, 0x11, 0x5655);
3823 rtl_writephy(tp, 0x1f, 0x0bcd);
3824 rtl_writephy(tp, 0x14, 0x1065);
3825 rtl_writephy(tp, 0x14, 0x9065);
3826 rtl_writephy(tp, 0x14, 0x1065);
3827
3828 /* Check ALDPS bit, disable it if enabled */
3829 rtl_writephy(tp, 0x1f, 0x0a43);
3830 if (rtl_readphy(tp, 0x10) & 0x0004)
3831 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3832
3833 rtl_writephy(tp, 0x1f, 0x0000);
3834 }
3835
3836 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3837 {
3838 rtl_apply_firmware(tp);
3839 }
3840
3841 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3842 {
3843 u16 dout_tapbin;
3844 u32 data;
3845
3846 rtl_apply_firmware(tp);
3847
3848 /* CHN EST parameters adjust - giga master */
3849 rtl_writephy(tp, 0x1f, 0x0a43);
3850 rtl_writephy(tp, 0x13, 0x809b);
3851 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3852 rtl_writephy(tp, 0x13, 0x80a2);
3853 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3854 rtl_writephy(tp, 0x13, 0x80a4);
3855 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3856 rtl_writephy(tp, 0x13, 0x809c);
3857 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3858 rtl_writephy(tp, 0x1f, 0x0000);
3859
3860 /* CHN EST parameters adjust - giga slave */
3861 rtl_writephy(tp, 0x1f, 0x0a43);
3862 rtl_writephy(tp, 0x13, 0x80ad);
3863 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3864 rtl_writephy(tp, 0x13, 0x80b4);
3865 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3866 rtl_writephy(tp, 0x13, 0x80ac);
3867 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3868 rtl_writephy(tp, 0x1f, 0x0000);
3869
3870 /* CHN EST parameters adjust - fnet */
3871 rtl_writephy(tp, 0x1f, 0x0a43);
3872 rtl_writephy(tp, 0x13, 0x808e);
3873 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3874 rtl_writephy(tp, 0x13, 0x8090);
3875 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3876 rtl_writephy(tp, 0x13, 0x8092);
3877 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3878 rtl_writephy(tp, 0x1f, 0x0000);
3879
3880 /* enable R-tune & PGA-retune function */
3881 dout_tapbin = 0;
3882 rtl_writephy(tp, 0x1f, 0x0a46);
3883 data = rtl_readphy(tp, 0x13);
3884 data &= 3;
3885 data <<= 2;
3886 dout_tapbin |= data;
3887 data = rtl_readphy(tp, 0x12);
3888 data &= 0xc000;
3889 data >>= 14;
3890 dout_tapbin |= data;
3891 dout_tapbin = ~(dout_tapbin^0x08);
3892 dout_tapbin <<= 12;
3893 dout_tapbin &= 0xf000;
3894 rtl_writephy(tp, 0x1f, 0x0a43);
3895 rtl_writephy(tp, 0x13, 0x827a);
3896 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3897 rtl_writephy(tp, 0x13, 0x827b);
3898 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3899 rtl_writephy(tp, 0x13, 0x827c);
3900 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3901 rtl_writephy(tp, 0x13, 0x827d);
3902 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3903
3904 rtl_writephy(tp, 0x1f, 0x0a43);
3905 rtl_writephy(tp, 0x13, 0x0811);
3906 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3907 rtl_writephy(tp, 0x1f, 0x0a42);
3908 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3909 rtl_writephy(tp, 0x1f, 0x0000);
3910
3911 /* enable GPHY 10M */
3912 rtl_writephy(tp, 0x1f, 0x0a44);
3913 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3914 rtl_writephy(tp, 0x1f, 0x0000);
3915
3916 /* SAR ADC performance */
3917 rtl_writephy(tp, 0x1f, 0x0bca);
3918 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3919 rtl_writephy(tp, 0x1f, 0x0000);
3920
3921 rtl_writephy(tp, 0x1f, 0x0a43);
3922 rtl_writephy(tp, 0x13, 0x803f);
3923 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3924 rtl_writephy(tp, 0x13, 0x8047);
3925 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3926 rtl_writephy(tp, 0x13, 0x804f);
3927 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3928 rtl_writephy(tp, 0x13, 0x8057);
3929 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3930 rtl_writephy(tp, 0x13, 0x805f);
3931 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3932 rtl_writephy(tp, 0x13, 0x8067);
3933 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3934 rtl_writephy(tp, 0x13, 0x806f);
3935 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3936 rtl_writephy(tp, 0x1f, 0x0000);
3937
3938 /* disable phy pfm mode */
3939 rtl_writephy(tp, 0x1f, 0x0a44);
3940 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3941 rtl_writephy(tp, 0x1f, 0x0000);
3942
3943 /* Check ALDPS bit, disable it if enabled */
3944 rtl_writephy(tp, 0x1f, 0x0a43);
3945 if (rtl_readphy(tp, 0x10) & 0x0004)
3946 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3947
3948 rtl_writephy(tp, 0x1f, 0x0000);
3949 }
3950
3951 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3952 {
3953 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3954 u16 rlen;
3955 u32 data;
3956
3957 rtl_apply_firmware(tp);
3958
3959 /* CHIN EST parameter update */
3960 rtl_writephy(tp, 0x1f, 0x0a43);
3961 rtl_writephy(tp, 0x13, 0x808a);
3962 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3963 rtl_writephy(tp, 0x1f, 0x0000);
3964
3965 /* enable R-tune & PGA-retune function */
3966 rtl_writephy(tp, 0x1f, 0x0a43);
3967 rtl_writephy(tp, 0x13, 0x0811);
3968 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3969 rtl_writephy(tp, 0x1f, 0x0a42);
3970 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3971 rtl_writephy(tp, 0x1f, 0x0000);
3972
3973 /* enable GPHY 10M */
3974 rtl_writephy(tp, 0x1f, 0x0a44);
3975 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3976 rtl_writephy(tp, 0x1f, 0x0000);
3977
3978 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3979 data = r8168_mac_ocp_read(tp, 0xdd02);
3980 ioffset_p3 = ((data & 0x80)>>7);
3981 ioffset_p3 <<= 3;
3982
3983 data = r8168_mac_ocp_read(tp, 0xdd00);
3984 ioffset_p3 |= ((data & (0xe000))>>13);
3985 ioffset_p2 = ((data & (0x1e00))>>9);
3986 ioffset_p1 = ((data & (0x01e0))>>5);
3987 ioffset_p0 = ((data & 0x0010)>>4);
3988 ioffset_p0 <<= 3;
3989 ioffset_p0 |= (data & (0x07));
3990 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3991
3992 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3993 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3994 rtl_writephy(tp, 0x1f, 0x0bcf);
3995 rtl_writephy(tp, 0x16, data);
3996 rtl_writephy(tp, 0x1f, 0x0000);
3997 }
3998
3999 /* Modify rlen (TX LPF corner frequency) level */
4000 rtl_writephy(tp, 0x1f, 0x0bcd);
4001 data = rtl_readphy(tp, 0x16);
4002 data &= 0x000f;
4003 rlen = 0;
4004 if (data > 3)
4005 rlen = data - 3;
4006 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
4007 rtl_writephy(tp, 0x17, data);
4008 rtl_writephy(tp, 0x1f, 0x0bcd);
4009 rtl_writephy(tp, 0x1f, 0x0000);
4010
4011 /* disable phy pfm mode */
4012 rtl_writephy(tp, 0x1f, 0x0a44);
4013 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
4014 rtl_writephy(tp, 0x1f, 0x0000);
4015
4016 /* Check ALDPS bit, disable it if enabled */
4017 rtl_writephy(tp, 0x1f, 0x0a43);
4018 if (rtl_readphy(tp, 0x10) & 0x0004)
4019 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4020
4021 rtl_writephy(tp, 0x1f, 0x0000);
4022 }
4023
4024 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
4025 {
4026 /* Enable PHY auto speed down */
4027 rtl_writephy(tp, 0x1f, 0x0a44);
4028 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
4029 rtl_writephy(tp, 0x1f, 0x0000);
4030
4031 /* patch 10M & ALDPS */
4032 rtl_writephy(tp, 0x1f, 0x0bcc);
4033 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4034 rtl_writephy(tp, 0x1f, 0x0a44);
4035 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4036 rtl_writephy(tp, 0x1f, 0x0a43);
4037 rtl_writephy(tp, 0x13, 0x8084);
4038 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4039 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4040 rtl_writephy(tp, 0x1f, 0x0000);
4041
4042 /* Enable EEE auto-fallback function */
4043 rtl_writephy(tp, 0x1f, 0x0a4b);
4044 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
4045 rtl_writephy(tp, 0x1f, 0x0000);
4046
4047 /* Enable UC LPF tune function */
4048 rtl_writephy(tp, 0x1f, 0x0a43);
4049 rtl_writephy(tp, 0x13, 0x8012);
4050 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4051 rtl_writephy(tp, 0x1f, 0x0000);
4052
4053 /* set rg_sel_sdm_rate */
4054 rtl_writephy(tp, 0x1f, 0x0c42);
4055 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4056 rtl_writephy(tp, 0x1f, 0x0000);
4057
4058 /* Check ALDPS bit, disable it if enabled */
4059 rtl_writephy(tp, 0x1f, 0x0a43);
4060 if (rtl_readphy(tp, 0x10) & 0x0004)
4061 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4062
4063 rtl_writephy(tp, 0x1f, 0x0000);
4064 }
4065
4066 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
4067 {
4068 /* patch 10M & ALDPS */
4069 rtl_writephy(tp, 0x1f, 0x0bcc);
4070 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4071 rtl_writephy(tp, 0x1f, 0x0a44);
4072 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4073 rtl_writephy(tp, 0x1f, 0x0a43);
4074 rtl_writephy(tp, 0x13, 0x8084);
4075 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4076 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4077 rtl_writephy(tp, 0x1f, 0x0000);
4078
4079 /* Enable UC LPF tune function */
4080 rtl_writephy(tp, 0x1f, 0x0a43);
4081 rtl_writephy(tp, 0x13, 0x8012);
4082 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4083 rtl_writephy(tp, 0x1f, 0x0000);
4084
4085 /* Set rg_sel_sdm_rate */
4086 rtl_writephy(tp, 0x1f, 0x0c42);
4087 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4088 rtl_writephy(tp, 0x1f, 0x0000);
4089
4090 /* Channel estimation parameters */
4091 rtl_writephy(tp, 0x1f, 0x0a43);
4092 rtl_writephy(tp, 0x13, 0x80f3);
4093 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
4094 rtl_writephy(tp, 0x13, 0x80f0);
4095 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
4096 rtl_writephy(tp, 0x13, 0x80ef);
4097 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
4098 rtl_writephy(tp, 0x13, 0x80f6);
4099 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
4100 rtl_writephy(tp, 0x13, 0x80ec);
4101 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
4102 rtl_writephy(tp, 0x13, 0x80ed);
4103 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4104 rtl_writephy(tp, 0x13, 0x80f2);
4105 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
4106 rtl_writephy(tp, 0x13, 0x80f4);
4107 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
4108 rtl_writephy(tp, 0x1f, 0x0a43);
4109 rtl_writephy(tp, 0x13, 0x8110);
4110 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
4111 rtl_writephy(tp, 0x13, 0x810f);
4112 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
4113 rtl_writephy(tp, 0x13, 0x8111);
4114 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
4115 rtl_writephy(tp, 0x13, 0x8113);
4116 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4117 rtl_writephy(tp, 0x13, 0x8115);
4118 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4119 rtl_writephy(tp, 0x13, 0x810e);
4120 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4121 rtl_writephy(tp, 0x13, 0x810c);
4122 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4123 rtl_writephy(tp, 0x13, 0x810b);
4124 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4125 rtl_writephy(tp, 0x1f, 0x0a43);
4126 rtl_writephy(tp, 0x13, 0x80d1);
4127 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4128 rtl_writephy(tp, 0x13, 0x80cd);
4129 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4130 rtl_writephy(tp, 0x13, 0x80d3);
4131 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4132 rtl_writephy(tp, 0x13, 0x80d5);
4133 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4134 rtl_writephy(tp, 0x13, 0x80d7);
4135 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4136
4137 /* Force PWM-mode */
4138 rtl_writephy(tp, 0x1f, 0x0bcd);
4139 rtl_writephy(tp, 0x14, 0x5065);
4140 rtl_writephy(tp, 0x14, 0xd065);
4141 rtl_writephy(tp, 0x1f, 0x0bc8);
4142 rtl_writephy(tp, 0x12, 0x00ed);
4143 rtl_writephy(tp, 0x1f, 0x0bcd);
4144 rtl_writephy(tp, 0x14, 0x1065);
4145 rtl_writephy(tp, 0x14, 0x9065);
4146 rtl_writephy(tp, 0x14, 0x1065);
4147 rtl_writephy(tp, 0x1f, 0x0000);
4148
4149 /* Check ALDPS bit, disable it if enabled */
4150 rtl_writephy(tp, 0x1f, 0x0a43);
4151 if (rtl_readphy(tp, 0x10) & 0x0004)
4152 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4153
4154 rtl_writephy(tp, 0x1f, 0x0000);
4155 }
4156
4157 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
4158 {
4159 static const struct phy_reg phy_reg_init[] = {
4160 { 0x1f, 0x0003 },
4161 { 0x08, 0x441d },
4162 { 0x01, 0x9100 },
4163 { 0x1f, 0x0000 }
4164 };
4165
4166 rtl_writephy(tp, 0x1f, 0x0000);
4167 rtl_patchphy(tp, 0x11, 1 << 12);
4168 rtl_patchphy(tp, 0x19, 1 << 13);
4169 rtl_patchphy(tp, 0x10, 1 << 15);
4170
4171 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4172 }
4173
4174 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4175 {
4176 static const struct phy_reg phy_reg_init[] = {
4177 { 0x1f, 0x0005 },
4178 { 0x1a, 0x0000 },
4179 { 0x1f, 0x0000 },
4180
4181 { 0x1f, 0x0004 },
4182 { 0x1c, 0x0000 },
4183 { 0x1f, 0x0000 },
4184
4185 { 0x1f, 0x0001 },
4186 { 0x15, 0x7701 },
4187 { 0x1f, 0x0000 }
4188 };
4189
4190 /* Disable ALDPS before ram code */
4191 rtl_writephy(tp, 0x1f, 0x0000);
4192 rtl_writephy(tp, 0x18, 0x0310);
4193 msleep(100);
4194
4195 rtl_apply_firmware(tp);
4196
4197 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4198 }
4199
4200 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4201 {
4202 /* Disable ALDPS before setting firmware */
4203 rtl_writephy(tp, 0x1f, 0x0000);
4204 rtl_writephy(tp, 0x18, 0x0310);
4205 msleep(20);
4206
4207 rtl_apply_firmware(tp);
4208
4209 /* EEE setting */
4210 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4211 rtl_writephy(tp, 0x1f, 0x0004);
4212 rtl_writephy(tp, 0x10, 0x401f);
4213 rtl_writephy(tp, 0x19, 0x7030);
4214 rtl_writephy(tp, 0x1f, 0x0000);
4215 }
4216
4217 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4218 {
4219 static const struct phy_reg phy_reg_init[] = {
4220 { 0x1f, 0x0004 },
4221 { 0x10, 0xc07f },
4222 { 0x19, 0x7030 },
4223 { 0x1f, 0x0000 }
4224 };
4225
4226 /* Disable ALDPS before ram code */
4227 rtl_writephy(tp, 0x1f, 0x0000);
4228 rtl_writephy(tp, 0x18, 0x0310);
4229 msleep(100);
4230
4231 rtl_apply_firmware(tp);
4232
4233 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4234 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4235
4236 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4237 }
4238
4239 static void rtl_hw_phy_config(struct net_device *dev)
4240 {
4241 struct rtl8169_private *tp = netdev_priv(dev);
4242
4243 rtl8169_print_mac_version(tp);
4244
4245 switch (tp->mac_version) {
4246 case RTL_GIGA_MAC_VER_01:
4247 break;
4248 case RTL_GIGA_MAC_VER_02:
4249 case RTL_GIGA_MAC_VER_03:
4250 rtl8169s_hw_phy_config(tp);
4251 break;
4252 case RTL_GIGA_MAC_VER_04:
4253 rtl8169sb_hw_phy_config(tp);
4254 break;
4255 case RTL_GIGA_MAC_VER_05:
4256 rtl8169scd_hw_phy_config(tp);
4257 break;
4258 case RTL_GIGA_MAC_VER_06:
4259 rtl8169sce_hw_phy_config(tp);
4260 break;
4261 case RTL_GIGA_MAC_VER_07:
4262 case RTL_GIGA_MAC_VER_08:
4263 case RTL_GIGA_MAC_VER_09:
4264 rtl8102e_hw_phy_config(tp);
4265 break;
4266 case RTL_GIGA_MAC_VER_11:
4267 rtl8168bb_hw_phy_config(tp);
4268 break;
4269 case RTL_GIGA_MAC_VER_12:
4270 rtl8168bef_hw_phy_config(tp);
4271 break;
4272 case RTL_GIGA_MAC_VER_17:
4273 rtl8168bef_hw_phy_config(tp);
4274 break;
4275 case RTL_GIGA_MAC_VER_18:
4276 rtl8168cp_1_hw_phy_config(tp);
4277 break;
4278 case RTL_GIGA_MAC_VER_19:
4279 rtl8168c_1_hw_phy_config(tp);
4280 break;
4281 case RTL_GIGA_MAC_VER_20:
4282 rtl8168c_2_hw_phy_config(tp);
4283 break;
4284 case RTL_GIGA_MAC_VER_21:
4285 rtl8168c_3_hw_phy_config(tp);
4286 break;
4287 case RTL_GIGA_MAC_VER_22:
4288 rtl8168c_4_hw_phy_config(tp);
4289 break;
4290 case RTL_GIGA_MAC_VER_23:
4291 case RTL_GIGA_MAC_VER_24:
4292 rtl8168cp_2_hw_phy_config(tp);
4293 break;
4294 case RTL_GIGA_MAC_VER_25:
4295 rtl8168d_1_hw_phy_config(tp);
4296 break;
4297 case RTL_GIGA_MAC_VER_26:
4298 rtl8168d_2_hw_phy_config(tp);
4299 break;
4300 case RTL_GIGA_MAC_VER_27:
4301 rtl8168d_3_hw_phy_config(tp);
4302 break;
4303 case RTL_GIGA_MAC_VER_28:
4304 rtl8168d_4_hw_phy_config(tp);
4305 break;
4306 case RTL_GIGA_MAC_VER_29:
4307 case RTL_GIGA_MAC_VER_30:
4308 rtl8105e_hw_phy_config(tp);
4309 break;
4310 case RTL_GIGA_MAC_VER_31:
4311 /* None. */
4312 break;
4313 case RTL_GIGA_MAC_VER_32:
4314 case RTL_GIGA_MAC_VER_33:
4315 rtl8168e_1_hw_phy_config(tp);
4316 break;
4317 case RTL_GIGA_MAC_VER_34:
4318 rtl8168e_2_hw_phy_config(tp);
4319 break;
4320 case RTL_GIGA_MAC_VER_35:
4321 rtl8168f_1_hw_phy_config(tp);
4322 break;
4323 case RTL_GIGA_MAC_VER_36:
4324 rtl8168f_2_hw_phy_config(tp);
4325 break;
4326
4327 case RTL_GIGA_MAC_VER_37:
4328 rtl8402_hw_phy_config(tp);
4329 break;
4330
4331 case RTL_GIGA_MAC_VER_38:
4332 rtl8411_hw_phy_config(tp);
4333 break;
4334
4335 case RTL_GIGA_MAC_VER_39:
4336 rtl8106e_hw_phy_config(tp);
4337 break;
4338
4339 case RTL_GIGA_MAC_VER_40:
4340 rtl8168g_1_hw_phy_config(tp);
4341 break;
4342 case RTL_GIGA_MAC_VER_42:
4343 case RTL_GIGA_MAC_VER_43:
4344 case RTL_GIGA_MAC_VER_44:
4345 rtl8168g_2_hw_phy_config(tp);
4346 break;
4347 case RTL_GIGA_MAC_VER_45:
4348 case RTL_GIGA_MAC_VER_47:
4349 rtl8168h_1_hw_phy_config(tp);
4350 break;
4351 case RTL_GIGA_MAC_VER_46:
4352 case RTL_GIGA_MAC_VER_48:
4353 rtl8168h_2_hw_phy_config(tp);
4354 break;
4355
4356 case RTL_GIGA_MAC_VER_49:
4357 rtl8168ep_1_hw_phy_config(tp);
4358 break;
4359 case RTL_GIGA_MAC_VER_50:
4360 case RTL_GIGA_MAC_VER_51:
4361 rtl8168ep_2_hw_phy_config(tp);
4362 break;
4363
4364 case RTL_GIGA_MAC_VER_41:
4365 default:
4366 break;
4367 }
4368 }
4369
4370 static void rtl_phy_work(struct rtl8169_private *tp)
4371 {
4372 struct timer_list *timer = &tp->timer;
4373 void __iomem *ioaddr = tp->mmio_addr;
4374 unsigned long timeout = RTL8169_PHY_TIMEOUT;
4375
4376 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
4377
4378 if (tp->phy_reset_pending(tp)) {
4379 /*
4380 * A busy loop could burn quite a few cycles on nowadays CPU.
4381 * Let's delay the execution of the timer for a few ticks.
4382 */
4383 timeout = HZ/10;
4384 goto out_mod_timer;
4385 }
4386
4387 if (tp->link_ok(ioaddr))
4388 return;
4389
4390 netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
4391
4392 tp->phy_reset_enable(tp);
4393
4394 out_mod_timer:
4395 mod_timer(timer, jiffies + timeout);
4396 }
4397
4398 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4399 {
4400 if (!test_and_set_bit(flag, tp->wk.flags))
4401 schedule_work(&tp->wk.work);
4402 }
4403
4404 static void rtl8169_phy_timer(unsigned long __opaque)
4405 {
4406 struct net_device *dev = (struct net_device *)__opaque;
4407 struct rtl8169_private *tp = netdev_priv(dev);
4408
4409 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
4410 }
4411
4412 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
4413 void __iomem *ioaddr)
4414 {
4415 iounmap(ioaddr);
4416 pci_release_regions(pdev);
4417 pci_clear_mwi(pdev);
4418 pci_disable_device(pdev);
4419 free_netdev(dev);
4420 }
4421
4422 DECLARE_RTL_COND(rtl_phy_reset_cond)
4423 {
4424 return tp->phy_reset_pending(tp);
4425 }
4426
4427 static void rtl8169_phy_reset(struct net_device *dev,
4428 struct rtl8169_private *tp)
4429 {
4430 tp->phy_reset_enable(tp);
4431 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
4432 }
4433
4434 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4435 {
4436 void __iomem *ioaddr = tp->mmio_addr;
4437
4438 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4439 (RTL_R8(PHYstatus) & TBI_Enable);
4440 }
4441
4442 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4443 {
4444 void __iomem *ioaddr = tp->mmio_addr;
4445
4446 rtl_hw_phy_config(dev);
4447
4448 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4449 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4450 RTL_W8(0x82, 0x01);
4451 }
4452
4453 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4454
4455 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4456 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4457
4458 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4459 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4460 RTL_W8(0x82, 0x01);
4461 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4462 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4463 }
4464
4465 rtl8169_phy_reset(dev, tp);
4466
4467 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4468 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4469 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4470 (tp->mii.supports_gmii ?
4471 ADVERTISED_1000baseT_Half |
4472 ADVERTISED_1000baseT_Full : 0));
4473
4474 if (rtl_tbi_enabled(tp))
4475 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4476 }
4477
4478 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4479 {
4480 void __iomem *ioaddr = tp->mmio_addr;
4481
4482 rtl_lock_work(tp);
4483
4484 RTL_W8(Cfg9346, Cfg9346_Unlock);
4485
4486 RTL_W32(MAC4, addr[4] | addr[5] << 8);
4487 RTL_R32(MAC4);
4488
4489 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4490 RTL_R32(MAC0);
4491
4492 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4493 rtl_rar_exgmac_set(tp, addr);
4494
4495 RTL_W8(Cfg9346, Cfg9346_Lock);
4496
4497 rtl_unlock_work(tp);
4498 }
4499
4500 static int rtl_set_mac_address(struct net_device *dev, void *p)
4501 {
4502 struct rtl8169_private *tp = netdev_priv(dev);
4503 struct device *d = &tp->pci_dev->dev;
4504 struct sockaddr *addr = p;
4505
4506 if (!is_valid_ether_addr(addr->sa_data))
4507 return -EADDRNOTAVAIL;
4508
4509 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4510
4511 pm_runtime_get_noresume(d);
4512
4513 if (pm_runtime_active(d))
4514 rtl_rar_set(tp, dev->dev_addr);
4515
4516 pm_runtime_put_noidle(d);
4517
4518 return 0;
4519 }
4520
4521 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4522 {
4523 struct rtl8169_private *tp = netdev_priv(dev);
4524 struct mii_ioctl_data *data = if_mii(ifr);
4525
4526 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4527 }
4528
4529 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4530 struct mii_ioctl_data *data, int cmd)
4531 {
4532 switch (cmd) {
4533 case SIOCGMIIPHY:
4534 data->phy_id = 32; /* Internal PHY */
4535 return 0;
4536
4537 case SIOCGMIIREG:
4538 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
4539 return 0;
4540
4541 case SIOCSMIIREG:
4542 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
4543 return 0;
4544 }
4545 return -EOPNOTSUPP;
4546 }
4547
4548 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4549 {
4550 return -EOPNOTSUPP;
4551 }
4552
4553 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
4554 {
4555 if (tp->features & RTL_FEATURE_MSI) {
4556 pci_disable_msi(pdev);
4557 tp->features &= ~RTL_FEATURE_MSI;
4558 }
4559 }
4560
4561 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4562 {
4563 struct mdio_ops *ops = &tp->mdio_ops;
4564
4565 switch (tp->mac_version) {
4566 case RTL_GIGA_MAC_VER_27:
4567 ops->write = r8168dp_1_mdio_write;
4568 ops->read = r8168dp_1_mdio_read;
4569 break;
4570 case RTL_GIGA_MAC_VER_28:
4571 case RTL_GIGA_MAC_VER_31:
4572 ops->write = r8168dp_2_mdio_write;
4573 ops->read = r8168dp_2_mdio_read;
4574 break;
4575 case RTL_GIGA_MAC_VER_40:
4576 case RTL_GIGA_MAC_VER_41:
4577 case RTL_GIGA_MAC_VER_42:
4578 case RTL_GIGA_MAC_VER_43:
4579 case RTL_GIGA_MAC_VER_44:
4580 case RTL_GIGA_MAC_VER_45:
4581 case RTL_GIGA_MAC_VER_46:
4582 case RTL_GIGA_MAC_VER_47:
4583 case RTL_GIGA_MAC_VER_48:
4584 case RTL_GIGA_MAC_VER_49:
4585 case RTL_GIGA_MAC_VER_50:
4586 case RTL_GIGA_MAC_VER_51:
4587 ops->write = r8168g_mdio_write;
4588 ops->read = r8168g_mdio_read;
4589 break;
4590 default:
4591 ops->write = r8169_mdio_write;
4592 ops->read = r8169_mdio_read;
4593 break;
4594 }
4595 }
4596
4597 static void rtl_speed_down(struct rtl8169_private *tp)
4598 {
4599 u32 adv;
4600 int lpa;
4601
4602 rtl_writephy(tp, 0x1f, 0x0000);
4603 lpa = rtl_readphy(tp, MII_LPA);
4604
4605 if (lpa & (LPA_10HALF | LPA_10FULL))
4606 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4607 else if (lpa & (LPA_100HALF | LPA_100FULL))
4608 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4609 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4610 else
4611 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4612 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4613 (tp->mii.supports_gmii ?
4614 ADVERTISED_1000baseT_Half |
4615 ADVERTISED_1000baseT_Full : 0);
4616
4617 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4618 adv);
4619 }
4620
4621 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4622 {
4623 void __iomem *ioaddr = tp->mmio_addr;
4624
4625 switch (tp->mac_version) {
4626 case RTL_GIGA_MAC_VER_25:
4627 case RTL_GIGA_MAC_VER_26:
4628 case RTL_GIGA_MAC_VER_29:
4629 case RTL_GIGA_MAC_VER_30:
4630 case RTL_GIGA_MAC_VER_32:
4631 case RTL_GIGA_MAC_VER_33:
4632 case RTL_GIGA_MAC_VER_34:
4633 case RTL_GIGA_MAC_VER_37:
4634 case RTL_GIGA_MAC_VER_38:
4635 case RTL_GIGA_MAC_VER_39:
4636 case RTL_GIGA_MAC_VER_40:
4637 case RTL_GIGA_MAC_VER_41:
4638 case RTL_GIGA_MAC_VER_42:
4639 case RTL_GIGA_MAC_VER_43:
4640 case RTL_GIGA_MAC_VER_44:
4641 case RTL_GIGA_MAC_VER_45:
4642 case RTL_GIGA_MAC_VER_46:
4643 case RTL_GIGA_MAC_VER_47:
4644 case RTL_GIGA_MAC_VER_48:
4645 case RTL_GIGA_MAC_VER_49:
4646 case RTL_GIGA_MAC_VER_50:
4647 case RTL_GIGA_MAC_VER_51:
4648 RTL_W32(RxConfig, RTL_R32(RxConfig) |
4649 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4650 break;
4651 default:
4652 break;
4653 }
4654 }
4655
4656 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4657 {
4658 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4659 return false;
4660
4661 rtl_speed_down(tp);
4662 rtl_wol_suspend_quirk(tp);
4663
4664 return true;
4665 }
4666
4667 static void r810x_phy_power_down(struct rtl8169_private *tp)
4668 {
4669 rtl_writephy(tp, 0x1f, 0x0000);
4670 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4671 }
4672
4673 static void r810x_phy_power_up(struct rtl8169_private *tp)
4674 {
4675 rtl_writephy(tp, 0x1f, 0x0000);
4676 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4677 }
4678
4679 static void r810x_pll_power_down(struct rtl8169_private *tp)
4680 {
4681 void __iomem *ioaddr = tp->mmio_addr;
4682
4683 if (rtl_wol_pll_power_down(tp))
4684 return;
4685
4686 r810x_phy_power_down(tp);
4687
4688 switch (tp->mac_version) {
4689 case RTL_GIGA_MAC_VER_07:
4690 case RTL_GIGA_MAC_VER_08:
4691 case RTL_GIGA_MAC_VER_09:
4692 case RTL_GIGA_MAC_VER_10:
4693 case RTL_GIGA_MAC_VER_13:
4694 case RTL_GIGA_MAC_VER_16:
4695 break;
4696 default:
4697 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4698 break;
4699 }
4700 }
4701
4702 static void r810x_pll_power_up(struct rtl8169_private *tp)
4703 {
4704 void __iomem *ioaddr = tp->mmio_addr;
4705
4706 r810x_phy_power_up(tp);
4707
4708 switch (tp->mac_version) {
4709 case RTL_GIGA_MAC_VER_07:
4710 case RTL_GIGA_MAC_VER_08:
4711 case RTL_GIGA_MAC_VER_09:
4712 case RTL_GIGA_MAC_VER_10:
4713 case RTL_GIGA_MAC_VER_13:
4714 case RTL_GIGA_MAC_VER_16:
4715 break;
4716 case RTL_GIGA_MAC_VER_47:
4717 case RTL_GIGA_MAC_VER_48:
4718 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4719 break;
4720 default:
4721 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4722 break;
4723 }
4724 }
4725
4726 static void r8168_phy_power_up(struct rtl8169_private *tp)
4727 {
4728 rtl_writephy(tp, 0x1f, 0x0000);
4729 switch (tp->mac_version) {
4730 case RTL_GIGA_MAC_VER_11:
4731 case RTL_GIGA_MAC_VER_12:
4732 case RTL_GIGA_MAC_VER_17:
4733 case RTL_GIGA_MAC_VER_18:
4734 case RTL_GIGA_MAC_VER_19:
4735 case RTL_GIGA_MAC_VER_20:
4736 case RTL_GIGA_MAC_VER_21:
4737 case RTL_GIGA_MAC_VER_22:
4738 case RTL_GIGA_MAC_VER_23:
4739 case RTL_GIGA_MAC_VER_24:
4740 case RTL_GIGA_MAC_VER_25:
4741 case RTL_GIGA_MAC_VER_26:
4742 case RTL_GIGA_MAC_VER_27:
4743 case RTL_GIGA_MAC_VER_28:
4744 case RTL_GIGA_MAC_VER_31:
4745 rtl_writephy(tp, 0x0e, 0x0000);
4746 break;
4747 default:
4748 break;
4749 }
4750 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4751 }
4752
4753 static void r8168_phy_power_down(struct rtl8169_private *tp)
4754 {
4755 rtl_writephy(tp, 0x1f, 0x0000);
4756 switch (tp->mac_version) {
4757 case RTL_GIGA_MAC_VER_32:
4758 case RTL_GIGA_MAC_VER_33:
4759 case RTL_GIGA_MAC_VER_40:
4760 case RTL_GIGA_MAC_VER_41:
4761 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4762 break;
4763
4764 case RTL_GIGA_MAC_VER_11:
4765 case RTL_GIGA_MAC_VER_12:
4766 case RTL_GIGA_MAC_VER_17:
4767 case RTL_GIGA_MAC_VER_18:
4768 case RTL_GIGA_MAC_VER_19:
4769 case RTL_GIGA_MAC_VER_20:
4770 case RTL_GIGA_MAC_VER_21:
4771 case RTL_GIGA_MAC_VER_22:
4772 case RTL_GIGA_MAC_VER_23:
4773 case RTL_GIGA_MAC_VER_24:
4774 case RTL_GIGA_MAC_VER_25:
4775 case RTL_GIGA_MAC_VER_26:
4776 case RTL_GIGA_MAC_VER_27:
4777 case RTL_GIGA_MAC_VER_28:
4778 case RTL_GIGA_MAC_VER_31:
4779 rtl_writephy(tp, 0x0e, 0x0200);
4780 default:
4781 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4782 break;
4783 }
4784 }
4785
4786 static void r8168_pll_power_down(struct rtl8169_private *tp)
4787 {
4788 void __iomem *ioaddr = tp->mmio_addr;
4789
4790 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4791 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4792 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
4793 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
4794 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
4795 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
4796 r8168_check_dash(tp)) {
4797 return;
4798 }
4799
4800 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4801 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
4802 (RTL_R16(CPlusCmd) & ASF)) {
4803 return;
4804 }
4805
4806 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4807 tp->mac_version == RTL_GIGA_MAC_VER_33)
4808 rtl_ephy_write(tp, 0x19, 0xff64);
4809
4810 if (rtl_wol_pll_power_down(tp))
4811 return;
4812
4813 r8168_phy_power_down(tp);
4814
4815 switch (tp->mac_version) {
4816 case RTL_GIGA_MAC_VER_25:
4817 case RTL_GIGA_MAC_VER_26:
4818 case RTL_GIGA_MAC_VER_27:
4819 case RTL_GIGA_MAC_VER_28:
4820 case RTL_GIGA_MAC_VER_31:
4821 case RTL_GIGA_MAC_VER_32:
4822 case RTL_GIGA_MAC_VER_33:
4823 case RTL_GIGA_MAC_VER_44:
4824 case RTL_GIGA_MAC_VER_45:
4825 case RTL_GIGA_MAC_VER_46:
4826 case RTL_GIGA_MAC_VER_50:
4827 case RTL_GIGA_MAC_VER_51:
4828 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4829 break;
4830 case RTL_GIGA_MAC_VER_40:
4831 case RTL_GIGA_MAC_VER_41:
4832 case RTL_GIGA_MAC_VER_49:
4833 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4834 0xfc000000, ERIAR_EXGMAC);
4835 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4836 break;
4837 }
4838 }
4839
4840 static void r8168_pll_power_up(struct rtl8169_private *tp)
4841 {
4842 void __iomem *ioaddr = tp->mmio_addr;
4843
4844 switch (tp->mac_version) {
4845 case RTL_GIGA_MAC_VER_25:
4846 case RTL_GIGA_MAC_VER_26:
4847 case RTL_GIGA_MAC_VER_27:
4848 case RTL_GIGA_MAC_VER_28:
4849 case RTL_GIGA_MAC_VER_31:
4850 case RTL_GIGA_MAC_VER_32:
4851 case RTL_GIGA_MAC_VER_33:
4852 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4853 break;
4854 case RTL_GIGA_MAC_VER_44:
4855 case RTL_GIGA_MAC_VER_45:
4856 case RTL_GIGA_MAC_VER_46:
4857 case RTL_GIGA_MAC_VER_50:
4858 case RTL_GIGA_MAC_VER_51:
4859 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4860 break;
4861 case RTL_GIGA_MAC_VER_40:
4862 case RTL_GIGA_MAC_VER_41:
4863 case RTL_GIGA_MAC_VER_49:
4864 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4865 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4866 0x00000000, ERIAR_EXGMAC);
4867 break;
4868 }
4869
4870 r8168_phy_power_up(tp);
4871 }
4872
4873 static void rtl_generic_op(struct rtl8169_private *tp,
4874 void (*op)(struct rtl8169_private *))
4875 {
4876 if (op)
4877 op(tp);
4878 }
4879
4880 static void rtl_pll_power_down(struct rtl8169_private *tp)
4881 {
4882 rtl_generic_op(tp, tp->pll_power_ops.down);
4883 }
4884
4885 static void rtl_pll_power_up(struct rtl8169_private *tp)
4886 {
4887 rtl_generic_op(tp, tp->pll_power_ops.up);
4888 }
4889
4890 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4891 {
4892 struct pll_power_ops *ops = &tp->pll_power_ops;
4893
4894 switch (tp->mac_version) {
4895 case RTL_GIGA_MAC_VER_07:
4896 case RTL_GIGA_MAC_VER_08:
4897 case RTL_GIGA_MAC_VER_09:
4898 case RTL_GIGA_MAC_VER_10:
4899 case RTL_GIGA_MAC_VER_16:
4900 case RTL_GIGA_MAC_VER_29:
4901 case RTL_GIGA_MAC_VER_30:
4902 case RTL_GIGA_MAC_VER_37:
4903 case RTL_GIGA_MAC_VER_39:
4904 case RTL_GIGA_MAC_VER_43:
4905 case RTL_GIGA_MAC_VER_47:
4906 case RTL_GIGA_MAC_VER_48:
4907 ops->down = r810x_pll_power_down;
4908 ops->up = r810x_pll_power_up;
4909 break;
4910
4911 case RTL_GIGA_MAC_VER_11:
4912 case RTL_GIGA_MAC_VER_12:
4913 case RTL_GIGA_MAC_VER_17:
4914 case RTL_GIGA_MAC_VER_18:
4915 case RTL_GIGA_MAC_VER_19:
4916 case RTL_GIGA_MAC_VER_20:
4917 case RTL_GIGA_MAC_VER_21:
4918 case RTL_GIGA_MAC_VER_22:
4919 case RTL_GIGA_MAC_VER_23:
4920 case RTL_GIGA_MAC_VER_24:
4921 case RTL_GIGA_MAC_VER_25:
4922 case RTL_GIGA_MAC_VER_26:
4923 case RTL_GIGA_MAC_VER_27:
4924 case RTL_GIGA_MAC_VER_28:
4925 case RTL_GIGA_MAC_VER_31:
4926 case RTL_GIGA_MAC_VER_32:
4927 case RTL_GIGA_MAC_VER_33:
4928 case RTL_GIGA_MAC_VER_34:
4929 case RTL_GIGA_MAC_VER_35:
4930 case RTL_GIGA_MAC_VER_36:
4931 case RTL_GIGA_MAC_VER_38:
4932 case RTL_GIGA_MAC_VER_40:
4933 case RTL_GIGA_MAC_VER_41:
4934 case RTL_GIGA_MAC_VER_42:
4935 case RTL_GIGA_MAC_VER_44:
4936 case RTL_GIGA_MAC_VER_45:
4937 case RTL_GIGA_MAC_VER_46:
4938 case RTL_GIGA_MAC_VER_49:
4939 case RTL_GIGA_MAC_VER_50:
4940 case RTL_GIGA_MAC_VER_51:
4941 ops->down = r8168_pll_power_down;
4942 ops->up = r8168_pll_power_up;
4943 break;
4944
4945 default:
4946 ops->down = NULL;
4947 ops->up = NULL;
4948 break;
4949 }
4950 }
4951
4952 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4953 {
4954 void __iomem *ioaddr = tp->mmio_addr;
4955
4956 switch (tp->mac_version) {
4957 case RTL_GIGA_MAC_VER_01:
4958 case RTL_GIGA_MAC_VER_02:
4959 case RTL_GIGA_MAC_VER_03:
4960 case RTL_GIGA_MAC_VER_04:
4961 case RTL_GIGA_MAC_VER_05:
4962 case RTL_GIGA_MAC_VER_06:
4963 case RTL_GIGA_MAC_VER_10:
4964 case RTL_GIGA_MAC_VER_11:
4965 case RTL_GIGA_MAC_VER_12:
4966 case RTL_GIGA_MAC_VER_13:
4967 case RTL_GIGA_MAC_VER_14:
4968 case RTL_GIGA_MAC_VER_15:
4969 case RTL_GIGA_MAC_VER_16:
4970 case RTL_GIGA_MAC_VER_17:
4971 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4972 break;
4973 case RTL_GIGA_MAC_VER_18:
4974 case RTL_GIGA_MAC_VER_19:
4975 case RTL_GIGA_MAC_VER_20:
4976 case RTL_GIGA_MAC_VER_21:
4977 case RTL_GIGA_MAC_VER_22:
4978 case RTL_GIGA_MAC_VER_23:
4979 case RTL_GIGA_MAC_VER_24:
4980 case RTL_GIGA_MAC_VER_34:
4981 case RTL_GIGA_MAC_VER_35:
4982 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4983 break;
4984 case RTL_GIGA_MAC_VER_40:
4985 case RTL_GIGA_MAC_VER_41:
4986 case RTL_GIGA_MAC_VER_42:
4987 case RTL_GIGA_MAC_VER_43:
4988 case RTL_GIGA_MAC_VER_44:
4989 case RTL_GIGA_MAC_VER_45:
4990 case RTL_GIGA_MAC_VER_46:
4991 case RTL_GIGA_MAC_VER_47:
4992 case RTL_GIGA_MAC_VER_48:
4993 case RTL_GIGA_MAC_VER_49:
4994 case RTL_GIGA_MAC_VER_50:
4995 case RTL_GIGA_MAC_VER_51:
4996 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4997 break;
4998 default:
4999 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
5000 break;
5001 }
5002 }
5003
5004 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
5005 {
5006 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
5007 }
5008
5009 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
5010 {
5011 void __iomem *ioaddr = tp->mmio_addr;
5012
5013 RTL_W8(Cfg9346, Cfg9346_Unlock);
5014 rtl_generic_op(tp, tp->jumbo_ops.enable);
5015 RTL_W8(Cfg9346, Cfg9346_Lock);
5016 }
5017
5018 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
5019 {
5020 void __iomem *ioaddr = tp->mmio_addr;
5021
5022 RTL_W8(Cfg9346, Cfg9346_Unlock);
5023 rtl_generic_op(tp, tp->jumbo_ops.disable);
5024 RTL_W8(Cfg9346, Cfg9346_Lock);
5025 }
5026
5027 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
5028 {
5029 void __iomem *ioaddr = tp->mmio_addr;
5030
5031 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5032 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
5033 rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
5034 }
5035
5036 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
5037 {
5038 void __iomem *ioaddr = tp->mmio_addr;
5039
5040 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5041 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
5042 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5043 }
5044
5045 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
5046 {
5047 void __iomem *ioaddr = tp->mmio_addr;
5048
5049 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5050 }
5051
5052 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
5053 {
5054 void __iomem *ioaddr = tp->mmio_addr;
5055
5056 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5057 }
5058
5059 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
5060 {
5061 void __iomem *ioaddr = tp->mmio_addr;
5062
5063 RTL_W8(MaxTxPacketSize, 0x3f);
5064 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5065 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
5066 rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
5067 }
5068
5069 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
5070 {
5071 void __iomem *ioaddr = tp->mmio_addr;
5072
5073 RTL_W8(MaxTxPacketSize, 0x0c);
5074 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5075 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
5076 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5077 }
5078
5079 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
5080 {
5081 rtl_tx_performance_tweak(tp->pci_dev,
5082 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
5083 }
5084
5085 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
5086 {
5087 rtl_tx_performance_tweak(tp->pci_dev,
5088 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
5089 }
5090
5091 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
5092 {
5093 void __iomem *ioaddr = tp->mmio_addr;
5094
5095 r8168b_0_hw_jumbo_enable(tp);
5096
5097 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
5098 }
5099
5100 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
5101 {
5102 void __iomem *ioaddr = tp->mmio_addr;
5103
5104 r8168b_0_hw_jumbo_disable(tp);
5105
5106 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5107 }
5108
5109 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
5110 {
5111 struct jumbo_ops *ops = &tp->jumbo_ops;
5112
5113 switch (tp->mac_version) {
5114 case RTL_GIGA_MAC_VER_11:
5115 ops->disable = r8168b_0_hw_jumbo_disable;
5116 ops->enable = r8168b_0_hw_jumbo_enable;
5117 break;
5118 case RTL_GIGA_MAC_VER_12:
5119 case RTL_GIGA_MAC_VER_17:
5120 ops->disable = r8168b_1_hw_jumbo_disable;
5121 ops->enable = r8168b_1_hw_jumbo_enable;
5122 break;
5123 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
5124 case RTL_GIGA_MAC_VER_19:
5125 case RTL_GIGA_MAC_VER_20:
5126 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
5127 case RTL_GIGA_MAC_VER_22:
5128 case RTL_GIGA_MAC_VER_23:
5129 case RTL_GIGA_MAC_VER_24:
5130 case RTL_GIGA_MAC_VER_25:
5131 case RTL_GIGA_MAC_VER_26:
5132 ops->disable = r8168c_hw_jumbo_disable;
5133 ops->enable = r8168c_hw_jumbo_enable;
5134 break;
5135 case RTL_GIGA_MAC_VER_27:
5136 case RTL_GIGA_MAC_VER_28:
5137 ops->disable = r8168dp_hw_jumbo_disable;
5138 ops->enable = r8168dp_hw_jumbo_enable;
5139 break;
5140 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
5141 case RTL_GIGA_MAC_VER_32:
5142 case RTL_GIGA_MAC_VER_33:
5143 case RTL_GIGA_MAC_VER_34:
5144 ops->disable = r8168e_hw_jumbo_disable;
5145 ops->enable = r8168e_hw_jumbo_enable;
5146 break;
5147
5148 /*
5149 * No action needed for jumbo frames with 8169.
5150 * No jumbo for 810x at all.
5151 */
5152 case RTL_GIGA_MAC_VER_40:
5153 case RTL_GIGA_MAC_VER_41:
5154 case RTL_GIGA_MAC_VER_42:
5155 case RTL_GIGA_MAC_VER_43:
5156 case RTL_GIGA_MAC_VER_44:
5157 case RTL_GIGA_MAC_VER_45:
5158 case RTL_GIGA_MAC_VER_46:
5159 case RTL_GIGA_MAC_VER_47:
5160 case RTL_GIGA_MAC_VER_48:
5161 case RTL_GIGA_MAC_VER_49:
5162 case RTL_GIGA_MAC_VER_50:
5163 case RTL_GIGA_MAC_VER_51:
5164 default:
5165 ops->disable = NULL;
5166 ops->enable = NULL;
5167 break;
5168 }
5169 }
5170
5171 DECLARE_RTL_COND(rtl_chipcmd_cond)
5172 {
5173 void __iomem *ioaddr = tp->mmio_addr;
5174
5175 return RTL_R8(ChipCmd) & CmdReset;
5176 }
5177
5178 static void rtl_hw_reset(struct rtl8169_private *tp)
5179 {
5180 void __iomem *ioaddr = tp->mmio_addr;
5181
5182 RTL_W8(ChipCmd, CmdReset);
5183
5184 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
5185 }
5186
5187 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
5188 {
5189 struct rtl_fw *rtl_fw;
5190 const char *name;
5191 int rc = -ENOMEM;
5192
5193 name = rtl_lookup_firmware_name(tp);
5194 if (!name)
5195 goto out_no_firmware;
5196
5197 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
5198 if (!rtl_fw)
5199 goto err_warn;
5200
5201 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
5202 if (rc < 0)
5203 goto err_free;
5204
5205 rc = rtl_check_firmware(tp, rtl_fw);
5206 if (rc < 0)
5207 goto err_release_firmware;
5208
5209 tp->rtl_fw = rtl_fw;
5210 out:
5211 return;
5212
5213 err_release_firmware:
5214 release_firmware(rtl_fw->fw);
5215 err_free:
5216 kfree(rtl_fw);
5217 err_warn:
5218 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
5219 name, rc);
5220 out_no_firmware:
5221 tp->rtl_fw = NULL;
5222 goto out;
5223 }
5224
5225 static void rtl_request_firmware(struct rtl8169_private *tp)
5226 {
5227 if (IS_ERR(tp->rtl_fw))
5228 rtl_request_uncached_firmware(tp);
5229 }
5230
5231 static void rtl_rx_close(struct rtl8169_private *tp)
5232 {
5233 void __iomem *ioaddr = tp->mmio_addr;
5234
5235 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
5236 }
5237
5238 DECLARE_RTL_COND(rtl_npq_cond)
5239 {
5240 void __iomem *ioaddr = tp->mmio_addr;
5241
5242 return RTL_R8(TxPoll) & NPQ;
5243 }
5244
5245 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
5246 {
5247 void __iomem *ioaddr = tp->mmio_addr;
5248
5249 return RTL_R32(TxConfig) & TXCFG_EMPTY;
5250 }
5251
5252 static void rtl8169_hw_reset(struct rtl8169_private *tp)
5253 {
5254 void __iomem *ioaddr = tp->mmio_addr;
5255
5256 /* Disable interrupts */
5257 rtl8169_irq_mask_and_ack(tp);
5258
5259 rtl_rx_close(tp);
5260
5261 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5262 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5263 tp->mac_version == RTL_GIGA_MAC_VER_31) {
5264 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
5265 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
5266 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
5267 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
5268 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
5269 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
5270 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
5271 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
5272 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
5273 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
5274 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
5275 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
5276 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
5277 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
5278 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
5279 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5280 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5281 tp->mac_version == RTL_GIGA_MAC_VER_51) {
5282 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5283 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
5284 } else {
5285 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5286 udelay(100);
5287 }
5288
5289 rtl_hw_reset(tp);
5290 }
5291
5292 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
5293 {
5294 void __iomem *ioaddr = tp->mmio_addr;
5295
5296 /* Set DMA burst size and Interframe Gap Time */
5297 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5298 (InterFrameGap << TxInterFrameGapShift));
5299 }
5300
5301 static void rtl_hw_start(struct net_device *dev)
5302 {
5303 struct rtl8169_private *tp = netdev_priv(dev);
5304
5305 tp->hw_start(dev);
5306
5307 rtl_irq_enable_all(tp);
5308 }
5309
5310 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
5311 void __iomem *ioaddr)
5312 {
5313 /*
5314 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5315 * register to be written before TxDescAddrLow to work.
5316 * Switching from MMIO to I/O access fixes the issue as well.
5317 */
5318 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
5319 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
5320 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
5321 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
5322 }
5323
5324 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
5325 {
5326 u16 cmd;
5327
5328 cmd = RTL_R16(CPlusCmd);
5329 RTL_W16(CPlusCmd, cmd);
5330 return cmd;
5331 }
5332
5333 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
5334 {
5335 /* Low hurts. Let's disable the filtering. */
5336 RTL_W16(RxMaxSize, rx_buf_sz + 1);
5337 }
5338
5339 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
5340 {
5341 static const struct rtl_cfg2_info {
5342 u32 mac_version;
5343 u32 clk;
5344 u32 val;
5345 } cfg2_info [] = {
5346 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5347 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5348 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5349 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
5350 };
5351 const struct rtl_cfg2_info *p = cfg2_info;
5352 unsigned int i;
5353 u32 clk;
5354
5355 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
5356 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
5357 if ((p->mac_version == mac_version) && (p->clk == clk)) {
5358 RTL_W32(0x7c, p->val);
5359 break;
5360 }
5361 }
5362 }
5363
5364 static void rtl_set_rx_mode(struct net_device *dev)
5365 {
5366 struct rtl8169_private *tp = netdev_priv(dev);
5367 void __iomem *ioaddr = tp->mmio_addr;
5368 u32 mc_filter[2]; /* Multicast hash filter */
5369 int rx_mode;
5370 u32 tmp = 0;
5371
5372 if (dev->flags & IFF_PROMISC) {
5373 /* Unconditionally log net taps. */
5374 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5375 rx_mode =
5376 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5377 AcceptAllPhys;
5378 mc_filter[1] = mc_filter[0] = 0xffffffff;
5379 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5380 (dev->flags & IFF_ALLMULTI)) {
5381 /* Too many to filter perfectly -- accept all multicasts. */
5382 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5383 mc_filter[1] = mc_filter[0] = 0xffffffff;
5384 } else {
5385 struct netdev_hw_addr *ha;
5386
5387 rx_mode = AcceptBroadcast | AcceptMyPhys;
5388 mc_filter[1] = mc_filter[0] = 0;
5389 netdev_for_each_mc_addr(ha, dev) {
5390 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5391 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5392 rx_mode |= AcceptMulticast;
5393 }
5394 }
5395
5396 if (dev->features & NETIF_F_RXALL)
5397 rx_mode |= (AcceptErr | AcceptRunt);
5398
5399 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5400
5401 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5402 u32 data = mc_filter[0];
5403
5404 mc_filter[0] = swab32(mc_filter[1]);
5405 mc_filter[1] = swab32(data);
5406 }
5407
5408 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5409 mc_filter[1] = mc_filter[0] = 0xffffffff;
5410
5411 RTL_W32(MAR0 + 4, mc_filter[1]);
5412 RTL_W32(MAR0 + 0, mc_filter[0]);
5413
5414 RTL_W32(RxConfig, tmp);
5415 }
5416
5417 static void rtl_hw_start_8169(struct net_device *dev)
5418 {
5419 struct rtl8169_private *tp = netdev_priv(dev);
5420 void __iomem *ioaddr = tp->mmio_addr;
5421 struct pci_dev *pdev = tp->pci_dev;
5422
5423 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
5424 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
5425 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
5426 }
5427
5428 RTL_W8(Cfg9346, Cfg9346_Unlock);
5429 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5430 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5431 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5432 tp->mac_version == RTL_GIGA_MAC_VER_04)
5433 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5434
5435 rtl_init_rxcfg(tp);
5436
5437 RTL_W8(EarlyTxThres, NoEarlyTx);
5438
5439 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5440
5441 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5442 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5443 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5444 tp->mac_version == RTL_GIGA_MAC_VER_04)
5445 rtl_set_rx_tx_config_registers(tp);
5446
5447 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
5448
5449 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5450 tp->mac_version == RTL_GIGA_MAC_VER_03) {
5451 dprintk("Set MAC Reg C+CR Offset 0xe0. "
5452 "Bit-3 and bit-14 MUST be 1\n");
5453 tp->cp_cmd |= (1 << 14);
5454 }
5455
5456 RTL_W16(CPlusCmd, tp->cp_cmd);
5457
5458 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
5459
5460 /*
5461 * Undocumented corner. Supposedly:
5462 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5463 */
5464 RTL_W16(IntrMitigate, 0x0000);
5465
5466 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5467
5468 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5469 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5470 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5471 tp->mac_version != RTL_GIGA_MAC_VER_04) {
5472 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5473 rtl_set_rx_tx_config_registers(tp);
5474 }
5475
5476 RTL_W8(Cfg9346, Cfg9346_Lock);
5477
5478 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5479 RTL_R8(IntrMask);
5480
5481 RTL_W32(RxMissed, 0);
5482
5483 rtl_set_rx_mode(dev);
5484
5485 /* no early-rx interrupts */
5486 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5487 }
5488
5489 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5490 {
5491 if (tp->csi_ops.write)
5492 tp->csi_ops.write(tp, addr, value);
5493 }
5494
5495 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5496 {
5497 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
5498 }
5499
5500 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
5501 {
5502 u32 csi;
5503
5504 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5505 rtl_csi_write(tp, 0x070c, csi | bits);
5506 }
5507
5508 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5509 {
5510 rtl_csi_access_enable(tp, 0x17000000);
5511 }
5512
5513 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
5514 {
5515 rtl_csi_access_enable(tp, 0x27000000);
5516 }
5517
5518 DECLARE_RTL_COND(rtl_csiar_cond)
5519 {
5520 void __iomem *ioaddr = tp->mmio_addr;
5521
5522 return RTL_R32(CSIAR) & CSIAR_FLAG;
5523 }
5524
5525 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
5526 {
5527 void __iomem *ioaddr = tp->mmio_addr;
5528
5529 RTL_W32(CSIDR, value);
5530 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5531 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5532
5533 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5534 }
5535
5536 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
5537 {
5538 void __iomem *ioaddr = tp->mmio_addr;
5539
5540 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
5541 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5542
5543 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5544 RTL_R32(CSIDR) : ~0;
5545 }
5546
5547 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
5548 {
5549 void __iomem *ioaddr = tp->mmio_addr;
5550
5551 RTL_W32(CSIDR, value);
5552 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5553 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5554 CSIAR_FUNC_NIC);
5555
5556 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5557 }
5558
5559 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
5560 {
5561 void __iomem *ioaddr = tp->mmio_addr;
5562
5563 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5564 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5565
5566 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5567 RTL_R32(CSIDR) : ~0;
5568 }
5569
5570 static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5571 {
5572 void __iomem *ioaddr = tp->mmio_addr;
5573
5574 RTL_W32(CSIDR, value);
5575 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5576 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5577 CSIAR_FUNC_NIC2);
5578
5579 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5580 }
5581
5582 static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5583 {
5584 void __iomem *ioaddr = tp->mmio_addr;
5585
5586 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5587 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5588
5589 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5590 RTL_R32(CSIDR) : ~0;
5591 }
5592
5593 static void rtl_init_csi_ops(struct rtl8169_private *tp)
5594 {
5595 struct csi_ops *ops = &tp->csi_ops;
5596
5597 switch (tp->mac_version) {
5598 case RTL_GIGA_MAC_VER_01:
5599 case RTL_GIGA_MAC_VER_02:
5600 case RTL_GIGA_MAC_VER_03:
5601 case RTL_GIGA_MAC_VER_04:
5602 case RTL_GIGA_MAC_VER_05:
5603 case RTL_GIGA_MAC_VER_06:
5604 case RTL_GIGA_MAC_VER_10:
5605 case RTL_GIGA_MAC_VER_11:
5606 case RTL_GIGA_MAC_VER_12:
5607 case RTL_GIGA_MAC_VER_13:
5608 case RTL_GIGA_MAC_VER_14:
5609 case RTL_GIGA_MAC_VER_15:
5610 case RTL_GIGA_MAC_VER_16:
5611 case RTL_GIGA_MAC_VER_17:
5612 ops->write = NULL;
5613 ops->read = NULL;
5614 break;
5615
5616 case RTL_GIGA_MAC_VER_37:
5617 case RTL_GIGA_MAC_VER_38:
5618 ops->write = r8402_csi_write;
5619 ops->read = r8402_csi_read;
5620 break;
5621
5622 case RTL_GIGA_MAC_VER_44:
5623 ops->write = r8411_csi_write;
5624 ops->read = r8411_csi_read;
5625 break;
5626
5627 default:
5628 ops->write = r8169_csi_write;
5629 ops->read = r8169_csi_read;
5630 break;
5631 }
5632 }
5633
5634 struct ephy_info {
5635 unsigned int offset;
5636 u16 mask;
5637 u16 bits;
5638 };
5639
5640 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5641 int len)
5642 {
5643 u16 w;
5644
5645 while (len-- > 0) {
5646 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5647 rtl_ephy_write(tp, e->offset, w);
5648 e++;
5649 }
5650 }
5651
5652 static void rtl_disable_clock_request(struct pci_dev *pdev)
5653 {
5654 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
5655 PCI_EXP_LNKCTL_CLKREQ_EN);
5656 }
5657
5658 static void rtl_enable_clock_request(struct pci_dev *pdev)
5659 {
5660 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
5661 PCI_EXP_LNKCTL_CLKREQ_EN);
5662 }
5663
5664 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5665 {
5666 void __iomem *ioaddr = tp->mmio_addr;
5667 u8 data;
5668
5669 data = RTL_R8(Config3);
5670
5671 if (enable)
5672 data |= Rdy_to_L23;
5673 else
5674 data &= ~Rdy_to_L23;
5675
5676 RTL_W8(Config3, data);
5677 }
5678
5679 #define R8168_CPCMD_QUIRK_MASK (\
5680 EnableBist | \
5681 Mac_dbgo_oe | \
5682 Force_half_dup | \
5683 Force_rxflow_en | \
5684 Force_txflow_en | \
5685 Cxpl_dbg_sel | \
5686 ASF | \
5687 PktCntrDisable | \
5688 Mac_dbgo_sel)
5689
5690 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
5691 {
5692 void __iomem *ioaddr = tp->mmio_addr;
5693 struct pci_dev *pdev = tp->pci_dev;
5694
5695 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5696
5697 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5698
5699 if (tp->dev->mtu <= ETH_DATA_LEN) {
5700 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
5701 PCI_EXP_DEVCTL_NOSNOOP_EN);
5702 }
5703 }
5704
5705 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
5706 {
5707 void __iomem *ioaddr = tp->mmio_addr;
5708
5709 rtl_hw_start_8168bb(tp);
5710
5711 RTL_W8(MaxTxPacketSize, TxPacketMax);
5712
5713 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5714 }
5715
5716 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
5717 {
5718 void __iomem *ioaddr = tp->mmio_addr;
5719 struct pci_dev *pdev = tp->pci_dev;
5720
5721 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
5722
5723 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5724
5725 if (tp->dev->mtu <= ETH_DATA_LEN)
5726 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5727
5728 rtl_disable_clock_request(pdev);
5729
5730 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5731 }
5732
5733 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
5734 {
5735 static const struct ephy_info e_info_8168cp[] = {
5736 { 0x01, 0, 0x0001 },
5737 { 0x02, 0x0800, 0x1000 },
5738 { 0x03, 0, 0x0042 },
5739 { 0x06, 0x0080, 0x0000 },
5740 { 0x07, 0, 0x2000 }
5741 };
5742
5743 rtl_csi_access_enable_2(tp);
5744
5745 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
5746
5747 __rtl_hw_start_8168cp(tp);
5748 }
5749
5750 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
5751 {
5752 void __iomem *ioaddr = tp->mmio_addr;
5753 struct pci_dev *pdev = tp->pci_dev;
5754
5755 rtl_csi_access_enable_2(tp);
5756
5757 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5758
5759 if (tp->dev->mtu <= ETH_DATA_LEN)
5760 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5761
5762 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5763 }
5764
5765 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
5766 {
5767 void __iomem *ioaddr = tp->mmio_addr;
5768 struct pci_dev *pdev = tp->pci_dev;
5769
5770 rtl_csi_access_enable_2(tp);
5771
5772 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5773
5774 /* Magic. */
5775 RTL_W8(DBG_REG, 0x20);
5776
5777 RTL_W8(MaxTxPacketSize, TxPacketMax);
5778
5779 if (tp->dev->mtu <= ETH_DATA_LEN)
5780 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5781
5782 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5783 }
5784
5785 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
5786 {
5787 void __iomem *ioaddr = tp->mmio_addr;
5788 static const struct ephy_info e_info_8168c_1[] = {
5789 { 0x02, 0x0800, 0x1000 },
5790 { 0x03, 0, 0x0002 },
5791 { 0x06, 0x0080, 0x0000 }
5792 };
5793
5794 rtl_csi_access_enable_2(tp);
5795
5796 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5797
5798 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
5799
5800 __rtl_hw_start_8168cp(tp);
5801 }
5802
5803 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
5804 {
5805 static const struct ephy_info e_info_8168c_2[] = {
5806 { 0x01, 0, 0x0001 },
5807 { 0x03, 0x0400, 0x0220 }
5808 };
5809
5810 rtl_csi_access_enable_2(tp);
5811
5812 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
5813
5814 __rtl_hw_start_8168cp(tp);
5815 }
5816
5817 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
5818 {
5819 rtl_hw_start_8168c_2(tp);
5820 }
5821
5822 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5823 {
5824 rtl_csi_access_enable_2(tp);
5825
5826 __rtl_hw_start_8168cp(tp);
5827 }
5828
5829 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5830 {
5831 void __iomem *ioaddr = tp->mmio_addr;
5832 struct pci_dev *pdev = tp->pci_dev;
5833
5834 rtl_csi_access_enable_2(tp);
5835
5836 rtl_disable_clock_request(pdev);
5837
5838 RTL_W8(MaxTxPacketSize, TxPacketMax);
5839
5840 if (tp->dev->mtu <= ETH_DATA_LEN)
5841 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5842
5843 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5844 }
5845
5846 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5847 {
5848 void __iomem *ioaddr = tp->mmio_addr;
5849 struct pci_dev *pdev = tp->pci_dev;
5850
5851 rtl_csi_access_enable_1(tp);
5852
5853 if (tp->dev->mtu <= ETH_DATA_LEN)
5854 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5855
5856 RTL_W8(MaxTxPacketSize, TxPacketMax);
5857
5858 rtl_disable_clock_request(pdev);
5859 }
5860
5861 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5862 {
5863 void __iomem *ioaddr = tp->mmio_addr;
5864 struct pci_dev *pdev = tp->pci_dev;
5865 static const struct ephy_info e_info_8168d_4[] = {
5866 { 0x0b, 0x0000, 0x0048 },
5867 { 0x19, 0x0020, 0x0050 },
5868 { 0x0c, 0x0100, 0x0020 }
5869 };
5870
5871 rtl_csi_access_enable_1(tp);
5872
5873 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5874
5875 RTL_W8(MaxTxPacketSize, TxPacketMax);
5876
5877 rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
5878
5879 rtl_enable_clock_request(pdev);
5880 }
5881
5882 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5883 {
5884 void __iomem *ioaddr = tp->mmio_addr;
5885 struct pci_dev *pdev = tp->pci_dev;
5886 static const struct ephy_info e_info_8168e_1[] = {
5887 { 0x00, 0x0200, 0x0100 },
5888 { 0x00, 0x0000, 0x0004 },
5889 { 0x06, 0x0002, 0x0001 },
5890 { 0x06, 0x0000, 0x0030 },
5891 { 0x07, 0x0000, 0x2000 },
5892 { 0x00, 0x0000, 0x0020 },
5893 { 0x03, 0x5800, 0x2000 },
5894 { 0x03, 0x0000, 0x0001 },
5895 { 0x01, 0x0800, 0x1000 },
5896 { 0x07, 0x0000, 0x4000 },
5897 { 0x1e, 0x0000, 0x2000 },
5898 { 0x19, 0xffff, 0xfe6c },
5899 { 0x0a, 0x0000, 0x0040 }
5900 };
5901
5902 rtl_csi_access_enable_2(tp);
5903
5904 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5905
5906 if (tp->dev->mtu <= ETH_DATA_LEN)
5907 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5908
5909 RTL_W8(MaxTxPacketSize, TxPacketMax);
5910
5911 rtl_disable_clock_request(pdev);
5912
5913 /* Reset tx FIFO pointer */
5914 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5915 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
5916
5917 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5918 }
5919
5920 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5921 {
5922 void __iomem *ioaddr = tp->mmio_addr;
5923 struct pci_dev *pdev = tp->pci_dev;
5924 static const struct ephy_info e_info_8168e_2[] = {
5925 { 0x09, 0x0000, 0x0080 },
5926 { 0x19, 0x0000, 0x0224 }
5927 };
5928
5929 rtl_csi_access_enable_1(tp);
5930
5931 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5932
5933 if (tp->dev->mtu <= ETH_DATA_LEN)
5934 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5935
5936 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5937 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5938 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5939 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5940 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5941 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5942 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5943 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5944
5945 RTL_W8(MaxTxPacketSize, EarlySize);
5946
5947 rtl_disable_clock_request(pdev);
5948
5949 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5950 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5951
5952 /* Adjust EEE LED frequency */
5953 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5954
5955 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5956 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5957 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5958 }
5959
5960 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5961 {
5962 void __iomem *ioaddr = tp->mmio_addr;
5963 struct pci_dev *pdev = tp->pci_dev;
5964
5965 rtl_csi_access_enable_2(tp);
5966
5967 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5968
5969 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5970 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5971 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5972 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5973 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5974 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5975 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5976 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5977 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5978 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5979
5980 RTL_W8(MaxTxPacketSize, EarlySize);
5981
5982 rtl_disable_clock_request(pdev);
5983
5984 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5985 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5986 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5987 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5988 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5989 }
5990
5991 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5992 {
5993 void __iomem *ioaddr = tp->mmio_addr;
5994 static const struct ephy_info e_info_8168f_1[] = {
5995 { 0x06, 0x00c0, 0x0020 },
5996 { 0x08, 0x0001, 0x0002 },
5997 { 0x09, 0x0000, 0x0080 },
5998 { 0x19, 0x0000, 0x0224 }
5999 };
6000
6001 rtl_hw_start_8168f(tp);
6002
6003 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
6004
6005 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
6006
6007 /* Adjust EEE LED frequency */
6008 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6009 }
6010
6011 static void rtl_hw_start_8411(struct rtl8169_private *tp)
6012 {
6013 static const struct ephy_info e_info_8168f_1[] = {
6014 { 0x06, 0x00c0, 0x0020 },
6015 { 0x0f, 0xffff, 0x5200 },
6016 { 0x1e, 0x0000, 0x4000 },
6017 { 0x19, 0x0000, 0x0224 }
6018 };
6019
6020 rtl_hw_start_8168f(tp);
6021 rtl_pcie_state_l2l3_enable(tp, false);
6022
6023 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
6024
6025 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
6026 }
6027
6028 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
6029 {
6030 void __iomem *ioaddr = tp->mmio_addr;
6031 struct pci_dev *pdev = tp->pci_dev;
6032
6033 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6034
6035 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
6036 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6037 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6038 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6039
6040 rtl_csi_access_enable_1(tp);
6041
6042 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6043
6044 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6045 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6046 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
6047
6048 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6049 RTL_W8(MaxTxPacketSize, EarlySize);
6050
6051 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6052 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6053
6054 /* Adjust EEE LED frequency */
6055 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6056
6057 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6058 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6059
6060 rtl_pcie_state_l2l3_enable(tp, false);
6061 }
6062
6063 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
6064 {
6065 void __iomem *ioaddr = tp->mmio_addr;
6066 static const struct ephy_info e_info_8168g_1[] = {
6067 { 0x00, 0x0000, 0x0008 },
6068 { 0x0c, 0x37d0, 0x0820 },
6069 { 0x1e, 0x0000, 0x0001 },
6070 { 0x19, 0x8000, 0x0000 }
6071 };
6072
6073 rtl_hw_start_8168g(tp);
6074
6075 /* disable aspm and clock request before access ephy */
6076 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6077 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6078 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
6079 }
6080
6081 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
6082 {
6083 void __iomem *ioaddr = tp->mmio_addr;
6084 static const struct ephy_info e_info_8168g_2[] = {
6085 { 0x00, 0x0000, 0x0008 },
6086 { 0x0c, 0x3df0, 0x0200 },
6087 { 0x19, 0xffff, 0xfc00 },
6088 { 0x1e, 0xffff, 0x20eb }
6089 };
6090
6091 rtl_hw_start_8168g(tp);
6092
6093 /* disable aspm and clock request before access ephy */
6094 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6095 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6096 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
6097 }
6098
6099 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
6100 {
6101 void __iomem *ioaddr = tp->mmio_addr;
6102 static const struct ephy_info e_info_8411_2[] = {
6103 { 0x00, 0x0000, 0x0008 },
6104 { 0x0c, 0x3df0, 0x0200 },
6105 { 0x0f, 0xffff, 0x5200 },
6106 { 0x19, 0x0020, 0x0000 },
6107 { 0x1e, 0x0000, 0x2000 }
6108 };
6109
6110 rtl_hw_start_8168g(tp);
6111
6112 /* disable aspm and clock request before access ephy */
6113 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6114 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6115 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
6116 }
6117
6118 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
6119 {
6120 void __iomem *ioaddr = tp->mmio_addr;
6121 struct pci_dev *pdev = tp->pci_dev;
6122 int rg_saw_cnt;
6123 u32 data;
6124 static const struct ephy_info e_info_8168h_1[] = {
6125 { 0x1e, 0x0800, 0x0001 },
6126 { 0x1d, 0x0000, 0x0800 },
6127 { 0x05, 0xffff, 0x2089 },
6128 { 0x06, 0xffff, 0x5881 },
6129 { 0x04, 0xffff, 0x154a },
6130 { 0x01, 0xffff, 0x068b }
6131 };
6132
6133 /* disable aspm and clock request before access ephy */
6134 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6135 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6136 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
6137
6138 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6139
6140 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6141 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6142 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6143 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6144
6145 rtl_csi_access_enable_1(tp);
6146
6147 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6148
6149 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6150 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6151
6152 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6153
6154 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6155
6156 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6157
6158 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6159 RTL_W8(MaxTxPacketSize, EarlySize);
6160
6161 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6162 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6163
6164 /* Adjust EEE LED frequency */
6165 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6166
6167 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6168 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6169
6170 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6171
6172 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6173
6174 rtl_pcie_state_l2l3_enable(tp, false);
6175
6176 rtl_writephy(tp, 0x1f, 0x0c42);
6177 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6178 rtl_writephy(tp, 0x1f, 0x0000);
6179 if (rg_saw_cnt > 0) {
6180 u16 sw_cnt_1ms_ini;
6181
6182 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
6183 sw_cnt_1ms_ini &= 0x0fff;
6184 data = r8168_mac_ocp_read(tp, 0xd412);
6185 data &= ~0x0fff;
6186 data |= sw_cnt_1ms_ini;
6187 r8168_mac_ocp_write(tp, 0xd412, data);
6188 }
6189
6190 data = r8168_mac_ocp_read(tp, 0xe056);
6191 data &= ~0xf0;
6192 data |= 0x70;
6193 r8168_mac_ocp_write(tp, 0xe056, data);
6194
6195 data = r8168_mac_ocp_read(tp, 0xe052);
6196 data &= ~0x6000;
6197 data |= 0x8008;
6198 r8168_mac_ocp_write(tp, 0xe052, data);
6199
6200 data = r8168_mac_ocp_read(tp, 0xe0d6);
6201 data &= ~0x01ff;
6202 data |= 0x017f;
6203 r8168_mac_ocp_write(tp, 0xe0d6, data);
6204
6205 data = r8168_mac_ocp_read(tp, 0xd420);
6206 data &= ~0x0fff;
6207 data |= 0x047f;
6208 r8168_mac_ocp_write(tp, 0xd420, data);
6209
6210 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
6211 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
6212 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
6213 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
6214 }
6215
6216 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
6217 {
6218 void __iomem *ioaddr = tp->mmio_addr;
6219 struct pci_dev *pdev = tp->pci_dev;
6220
6221 rtl8168ep_stop_cmac(tp);
6222
6223 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6224
6225 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6226 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
6227 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
6228 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6229
6230 rtl_csi_access_enable_1(tp);
6231
6232 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6233
6234 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6235 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6236
6237 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
6238
6239 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6240
6241 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6242 RTL_W8(MaxTxPacketSize, EarlySize);
6243
6244 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6245 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6246
6247 /* Adjust EEE LED frequency */
6248 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6249
6250 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6251
6252 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6253
6254 rtl_pcie_state_l2l3_enable(tp, false);
6255 }
6256
6257 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
6258 {
6259 void __iomem *ioaddr = tp->mmio_addr;
6260 static const struct ephy_info e_info_8168ep_1[] = {
6261 { 0x00, 0xffff, 0x10ab },
6262 { 0x06, 0xffff, 0xf030 },
6263 { 0x08, 0xffff, 0x2006 },
6264 { 0x0d, 0xffff, 0x1666 },
6265 { 0x0c, 0x3ff0, 0x0000 }
6266 };
6267
6268 /* disable aspm and clock request before access ephy */
6269 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6270 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6271 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
6272
6273 rtl_hw_start_8168ep(tp);
6274 }
6275
6276 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
6277 {
6278 void __iomem *ioaddr = tp->mmio_addr;
6279 static const struct ephy_info e_info_8168ep_2[] = {
6280 { 0x00, 0xffff, 0x10a3 },
6281 { 0x19, 0xffff, 0xfc00 },
6282 { 0x1e, 0xffff, 0x20ea }
6283 };
6284
6285 /* disable aspm and clock request before access ephy */
6286 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6287 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6288 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
6289
6290 rtl_hw_start_8168ep(tp);
6291
6292 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6293 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6294 }
6295
6296 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
6297 {
6298 void __iomem *ioaddr = tp->mmio_addr;
6299 u32 data;
6300 static const struct ephy_info e_info_8168ep_3[] = {
6301 { 0x00, 0xffff, 0x10a3 },
6302 { 0x19, 0xffff, 0x7c00 },
6303 { 0x1e, 0xffff, 0x20eb },
6304 { 0x0d, 0xffff, 0x1666 }
6305 };
6306
6307 /* disable aspm and clock request before access ephy */
6308 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6309 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6310 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
6311
6312 rtl_hw_start_8168ep(tp);
6313
6314 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6315 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6316
6317 data = r8168_mac_ocp_read(tp, 0xd3e2);
6318 data &= 0xf000;
6319 data |= 0x0271;
6320 r8168_mac_ocp_write(tp, 0xd3e2, data);
6321
6322 data = r8168_mac_ocp_read(tp, 0xd3e4);
6323 data &= 0xff00;
6324 r8168_mac_ocp_write(tp, 0xd3e4, data);
6325
6326 data = r8168_mac_ocp_read(tp, 0xe860);
6327 data |= 0x0080;
6328 r8168_mac_ocp_write(tp, 0xe860, data);
6329 }
6330
6331 static void rtl_hw_start_8168(struct net_device *dev)
6332 {
6333 struct rtl8169_private *tp = netdev_priv(dev);
6334 void __iomem *ioaddr = tp->mmio_addr;
6335
6336 RTL_W8(Cfg9346, Cfg9346_Unlock);
6337
6338 RTL_W8(MaxTxPacketSize, TxPacketMax);
6339
6340 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6341
6342 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
6343
6344 RTL_W16(CPlusCmd, tp->cp_cmd);
6345
6346 RTL_W16(IntrMitigate, 0x5151);
6347
6348 /* Work around for RxFIFO overflow. */
6349 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
6350 tp->event_slow |= RxFIFOOver | PCSTimeout;
6351 tp->event_slow &= ~RxOverflow;
6352 }
6353
6354 rtl_set_rx_tx_desc_registers(tp, ioaddr);
6355
6356 rtl_set_rx_tx_config_registers(tp);
6357
6358 RTL_R8(IntrMask);
6359
6360 switch (tp->mac_version) {
6361 case RTL_GIGA_MAC_VER_11:
6362 rtl_hw_start_8168bb(tp);
6363 break;
6364
6365 case RTL_GIGA_MAC_VER_12:
6366 case RTL_GIGA_MAC_VER_17:
6367 rtl_hw_start_8168bef(tp);
6368 break;
6369
6370 case RTL_GIGA_MAC_VER_18:
6371 rtl_hw_start_8168cp_1(tp);
6372 break;
6373
6374 case RTL_GIGA_MAC_VER_19:
6375 rtl_hw_start_8168c_1(tp);
6376 break;
6377
6378 case RTL_GIGA_MAC_VER_20:
6379 rtl_hw_start_8168c_2(tp);
6380 break;
6381
6382 case RTL_GIGA_MAC_VER_21:
6383 rtl_hw_start_8168c_3(tp);
6384 break;
6385
6386 case RTL_GIGA_MAC_VER_22:
6387 rtl_hw_start_8168c_4(tp);
6388 break;
6389
6390 case RTL_GIGA_MAC_VER_23:
6391 rtl_hw_start_8168cp_2(tp);
6392 break;
6393
6394 case RTL_GIGA_MAC_VER_24:
6395 rtl_hw_start_8168cp_3(tp);
6396 break;
6397
6398 case RTL_GIGA_MAC_VER_25:
6399 case RTL_GIGA_MAC_VER_26:
6400 case RTL_GIGA_MAC_VER_27:
6401 rtl_hw_start_8168d(tp);
6402 break;
6403
6404 case RTL_GIGA_MAC_VER_28:
6405 rtl_hw_start_8168d_4(tp);
6406 break;
6407
6408 case RTL_GIGA_MAC_VER_31:
6409 rtl_hw_start_8168dp(tp);
6410 break;
6411
6412 case RTL_GIGA_MAC_VER_32:
6413 case RTL_GIGA_MAC_VER_33:
6414 rtl_hw_start_8168e_1(tp);
6415 break;
6416 case RTL_GIGA_MAC_VER_34:
6417 rtl_hw_start_8168e_2(tp);
6418 break;
6419
6420 case RTL_GIGA_MAC_VER_35:
6421 case RTL_GIGA_MAC_VER_36:
6422 rtl_hw_start_8168f_1(tp);
6423 break;
6424
6425 case RTL_GIGA_MAC_VER_38:
6426 rtl_hw_start_8411(tp);
6427 break;
6428
6429 case RTL_GIGA_MAC_VER_40:
6430 case RTL_GIGA_MAC_VER_41:
6431 rtl_hw_start_8168g_1(tp);
6432 break;
6433 case RTL_GIGA_MAC_VER_42:
6434 rtl_hw_start_8168g_2(tp);
6435 break;
6436
6437 case RTL_GIGA_MAC_VER_44:
6438 rtl_hw_start_8411_2(tp);
6439 break;
6440
6441 case RTL_GIGA_MAC_VER_45:
6442 case RTL_GIGA_MAC_VER_46:
6443 rtl_hw_start_8168h_1(tp);
6444 break;
6445
6446 case RTL_GIGA_MAC_VER_49:
6447 rtl_hw_start_8168ep_1(tp);
6448 break;
6449
6450 case RTL_GIGA_MAC_VER_50:
6451 rtl_hw_start_8168ep_2(tp);
6452 break;
6453
6454 case RTL_GIGA_MAC_VER_51:
6455 rtl_hw_start_8168ep_3(tp);
6456 break;
6457
6458 default:
6459 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
6460 dev->name, tp->mac_version);
6461 break;
6462 }
6463
6464 RTL_W8(Cfg9346, Cfg9346_Lock);
6465
6466 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6467
6468 rtl_set_rx_mode(dev);
6469
6470 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6471 }
6472
6473 #define R810X_CPCMD_QUIRK_MASK (\
6474 EnableBist | \
6475 Mac_dbgo_oe | \
6476 Force_half_dup | \
6477 Force_rxflow_en | \
6478 Force_txflow_en | \
6479 Cxpl_dbg_sel | \
6480 ASF | \
6481 PktCntrDisable | \
6482 Mac_dbgo_sel)
6483
6484 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
6485 {
6486 void __iomem *ioaddr = tp->mmio_addr;
6487 struct pci_dev *pdev = tp->pci_dev;
6488 static const struct ephy_info e_info_8102e_1[] = {
6489 { 0x01, 0, 0x6e65 },
6490 { 0x02, 0, 0x091f },
6491 { 0x03, 0, 0xc2f9 },
6492 { 0x06, 0, 0xafb5 },
6493 { 0x07, 0, 0x0e00 },
6494 { 0x19, 0, 0xec80 },
6495 { 0x01, 0, 0x2e65 },
6496 { 0x01, 0, 0x6e65 }
6497 };
6498 u8 cfg1;
6499
6500 rtl_csi_access_enable_2(tp);
6501
6502 RTL_W8(DBG_REG, FIX_NAK_1);
6503
6504 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6505
6506 RTL_W8(Config1,
6507 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
6508 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6509
6510 cfg1 = RTL_R8(Config1);
6511 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
6512 RTL_W8(Config1, cfg1 & ~LEDS0);
6513
6514 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
6515 }
6516
6517 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
6518 {
6519 void __iomem *ioaddr = tp->mmio_addr;
6520 struct pci_dev *pdev = tp->pci_dev;
6521
6522 rtl_csi_access_enable_2(tp);
6523
6524 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6525
6526 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
6527 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6528 }
6529
6530 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
6531 {
6532 rtl_hw_start_8102e_2(tp);
6533
6534 rtl_ephy_write(tp, 0x03, 0xc2f9);
6535 }
6536
6537 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
6538 {
6539 void __iomem *ioaddr = tp->mmio_addr;
6540 static const struct ephy_info e_info_8105e_1[] = {
6541 { 0x07, 0, 0x4000 },
6542 { 0x19, 0, 0x0200 },
6543 { 0x19, 0, 0x0020 },
6544 { 0x1e, 0, 0x2000 },
6545 { 0x03, 0, 0x0001 },
6546 { 0x19, 0, 0x0100 },
6547 { 0x19, 0, 0x0004 },
6548 { 0x0a, 0, 0x0020 }
6549 };
6550
6551 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6552 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6553
6554 /* Disable Early Tally Counter */
6555 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
6556
6557 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6558 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
6559
6560 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
6561
6562 rtl_pcie_state_l2l3_enable(tp, false);
6563 }
6564
6565 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
6566 {
6567 rtl_hw_start_8105e_1(tp);
6568 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
6569 }
6570
6571 static void rtl_hw_start_8402(struct rtl8169_private *tp)
6572 {
6573 void __iomem *ioaddr = tp->mmio_addr;
6574 static const struct ephy_info e_info_8402[] = {
6575 { 0x19, 0xffff, 0xff64 },
6576 { 0x1e, 0, 0x4000 }
6577 };
6578
6579 rtl_csi_access_enable_2(tp);
6580
6581 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6582 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6583
6584 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6585 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6586
6587 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
6588
6589 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
6590
6591 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6592 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
6593 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6594 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6595 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6596 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6597 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
6598
6599 rtl_pcie_state_l2l3_enable(tp, false);
6600 }
6601
6602 static void rtl_hw_start_8106(struct rtl8169_private *tp)
6603 {
6604 void __iomem *ioaddr = tp->mmio_addr;
6605
6606 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6607 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6608
6609 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
6610 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6611 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6612
6613 rtl_pcie_state_l2l3_enable(tp, false);
6614 }
6615
6616 static void rtl_hw_start_8101(struct net_device *dev)
6617 {
6618 struct rtl8169_private *tp = netdev_priv(dev);
6619 void __iomem *ioaddr = tp->mmio_addr;
6620 struct pci_dev *pdev = tp->pci_dev;
6621
6622 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6623 tp->event_slow &= ~RxFIFOOver;
6624
6625 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
6626 tp->mac_version == RTL_GIGA_MAC_VER_16)
6627 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6628 PCI_EXP_DEVCTL_NOSNOOP_EN);
6629
6630 RTL_W8(Cfg9346, Cfg9346_Unlock);
6631
6632 RTL_W8(MaxTxPacketSize, TxPacketMax);
6633
6634 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6635
6636 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6637 RTL_W16(CPlusCmd, tp->cp_cmd);
6638
6639 rtl_set_rx_tx_desc_registers(tp, ioaddr);
6640
6641 rtl_set_rx_tx_config_registers(tp);
6642
6643 switch (tp->mac_version) {
6644 case RTL_GIGA_MAC_VER_07:
6645 rtl_hw_start_8102e_1(tp);
6646 break;
6647
6648 case RTL_GIGA_MAC_VER_08:
6649 rtl_hw_start_8102e_3(tp);
6650 break;
6651
6652 case RTL_GIGA_MAC_VER_09:
6653 rtl_hw_start_8102e_2(tp);
6654 break;
6655
6656 case RTL_GIGA_MAC_VER_29:
6657 rtl_hw_start_8105e_1(tp);
6658 break;
6659 case RTL_GIGA_MAC_VER_30:
6660 rtl_hw_start_8105e_2(tp);
6661 break;
6662
6663 case RTL_GIGA_MAC_VER_37:
6664 rtl_hw_start_8402(tp);
6665 break;
6666
6667 case RTL_GIGA_MAC_VER_39:
6668 rtl_hw_start_8106(tp);
6669 break;
6670 case RTL_GIGA_MAC_VER_43:
6671 rtl_hw_start_8168g_2(tp);
6672 break;
6673 case RTL_GIGA_MAC_VER_47:
6674 case RTL_GIGA_MAC_VER_48:
6675 rtl_hw_start_8168h_1(tp);
6676 break;
6677 }
6678
6679 RTL_W8(Cfg9346, Cfg9346_Lock);
6680
6681 RTL_W16(IntrMitigate, 0x0000);
6682
6683 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6684
6685 rtl_set_rx_mode(dev);
6686
6687 RTL_R8(IntrMask);
6688
6689 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6690 }
6691
6692 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6693 {
6694 struct rtl8169_private *tp = netdev_priv(dev);
6695
6696 if (new_mtu > ETH_DATA_LEN)
6697 rtl_hw_jumbo_enable(tp);
6698 else
6699 rtl_hw_jumbo_disable(tp);
6700
6701 dev->mtu = new_mtu;
6702 netdev_update_features(dev);
6703
6704 return 0;
6705 }
6706
6707 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6708 {
6709 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
6710 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6711 }
6712
6713 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6714 void **data_buff, struct RxDesc *desc)
6715 {
6716 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
6717 DMA_FROM_DEVICE);
6718
6719 kfree(*data_buff);
6720 *data_buff = NULL;
6721 rtl8169_make_unusable_by_asic(desc);
6722 }
6723
6724 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
6725 {
6726 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6727
6728 /* Force memory writes to complete before releasing descriptor */
6729 dma_wmb();
6730
6731 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
6732 }
6733
6734 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
6735 u32 rx_buf_sz)
6736 {
6737 desc->addr = cpu_to_le64(mapping);
6738 rtl8169_mark_to_asic(desc, rx_buf_sz);
6739 }
6740
6741 static inline void *rtl8169_align(void *data)
6742 {
6743 return (void *)ALIGN((long)data, 16);
6744 }
6745
6746 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6747 struct RxDesc *desc)
6748 {
6749 void *data;
6750 dma_addr_t mapping;
6751 struct device *d = &tp->pci_dev->dev;
6752 struct net_device *dev = tp->dev;
6753 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
6754
6755 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
6756 if (!data)
6757 return NULL;
6758
6759 if (rtl8169_align(data) != data) {
6760 kfree(data);
6761 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
6762 if (!data)
6763 return NULL;
6764 }
6765
6766 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
6767 DMA_FROM_DEVICE);
6768 if (unlikely(dma_mapping_error(d, mapping))) {
6769 if (net_ratelimit())
6770 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
6771 goto err_out;
6772 }
6773
6774 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6775 return data;
6776
6777 err_out:
6778 kfree(data);
6779 return NULL;
6780 }
6781
6782 static void rtl8169_rx_clear(struct rtl8169_private *tp)
6783 {
6784 unsigned int i;
6785
6786 for (i = 0; i < NUM_RX_DESC; i++) {
6787 if (tp->Rx_databuff[i]) {
6788 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
6789 tp->RxDescArray + i);
6790 }
6791 }
6792 }
6793
6794 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
6795 {
6796 desc->opts1 |= cpu_to_le32(RingEnd);
6797 }
6798
6799 static int rtl8169_rx_fill(struct rtl8169_private *tp)
6800 {
6801 unsigned int i;
6802
6803 for (i = 0; i < NUM_RX_DESC; i++) {
6804 void *data;
6805
6806 if (tp->Rx_databuff[i])
6807 continue;
6808
6809 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6810 if (!data) {
6811 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
6812 goto err_out;
6813 }
6814 tp->Rx_databuff[i] = data;
6815 }
6816
6817 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6818 return 0;
6819
6820 err_out:
6821 rtl8169_rx_clear(tp);
6822 return -ENOMEM;
6823 }
6824
6825 static int rtl8169_init_ring(struct net_device *dev)
6826 {
6827 struct rtl8169_private *tp = netdev_priv(dev);
6828
6829 rtl8169_init_ring_indexes(tp);
6830
6831 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6832 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
6833
6834 return rtl8169_rx_fill(tp);
6835 }
6836
6837 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
6838 struct TxDesc *desc)
6839 {
6840 unsigned int len = tx_skb->len;
6841
6842 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6843
6844 desc->opts1 = 0x00;
6845 desc->opts2 = 0x00;
6846 desc->addr = 0x00;
6847 tx_skb->len = 0;
6848 }
6849
6850 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6851 unsigned int n)
6852 {
6853 unsigned int i;
6854
6855 for (i = 0; i < n; i++) {
6856 unsigned int entry = (start + i) % NUM_TX_DESC;
6857 struct ring_info *tx_skb = tp->tx_skb + entry;
6858 unsigned int len = tx_skb->len;
6859
6860 if (len) {
6861 struct sk_buff *skb = tx_skb->skb;
6862
6863 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6864 tp->TxDescArray + entry);
6865 if (skb) {
6866 dev_consume_skb_any(skb);
6867 tx_skb->skb = NULL;
6868 }
6869 }
6870 }
6871 }
6872
6873 static void rtl8169_tx_clear(struct rtl8169_private *tp)
6874 {
6875 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
6876 tp->cur_tx = tp->dirty_tx = 0;
6877 }
6878
6879 static void rtl_reset_work(struct rtl8169_private *tp)
6880 {
6881 struct net_device *dev = tp->dev;
6882 int i;
6883
6884 napi_disable(&tp->napi);
6885 netif_stop_queue(dev);
6886 synchronize_sched();
6887
6888 rtl8169_hw_reset(tp);
6889
6890 for (i = 0; i < NUM_RX_DESC; i++)
6891 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
6892
6893 rtl8169_tx_clear(tp);
6894 rtl8169_init_ring_indexes(tp);
6895
6896 napi_enable(&tp->napi);
6897 rtl_hw_start(dev);
6898 netif_wake_queue(dev);
6899 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
6900 }
6901
6902 static void rtl8169_tx_timeout(struct net_device *dev)
6903 {
6904 struct rtl8169_private *tp = netdev_priv(dev);
6905
6906 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6907 }
6908
6909 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
6910 u32 *opts)
6911 {
6912 struct skb_shared_info *info = skb_shinfo(skb);
6913 unsigned int cur_frag, entry;
6914 struct TxDesc *uninitialized_var(txd);
6915 struct device *d = &tp->pci_dev->dev;
6916
6917 entry = tp->cur_tx;
6918 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
6919 const skb_frag_t *frag = info->frags + cur_frag;
6920 dma_addr_t mapping;
6921 u32 status, len;
6922 void *addr;
6923
6924 entry = (entry + 1) % NUM_TX_DESC;
6925
6926 txd = tp->TxDescArray + entry;
6927 len = skb_frag_size(frag);
6928 addr = skb_frag_address(frag);
6929 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
6930 if (unlikely(dma_mapping_error(d, mapping))) {
6931 if (net_ratelimit())
6932 netif_err(tp, drv, tp->dev,
6933 "Failed to map TX fragments DMA!\n");
6934 goto err_out;
6935 }
6936
6937 /* Anti gcc 2.95.3 bugware (sic) */
6938 status = opts[0] | len |
6939 (RingEnd * !((entry + 1) % NUM_TX_DESC));
6940
6941 txd->opts1 = cpu_to_le32(status);
6942 txd->opts2 = cpu_to_le32(opts[1]);
6943 txd->addr = cpu_to_le64(mapping);
6944
6945 tp->tx_skb[entry].len = len;
6946 }
6947
6948 if (cur_frag) {
6949 tp->tx_skb[entry].skb = skb;
6950 txd->opts1 |= cpu_to_le32(LastFrag);
6951 }
6952
6953 return cur_frag;
6954
6955 err_out:
6956 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6957 return -EIO;
6958 }
6959
6960 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6961 {
6962 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6963 }
6964
6965 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6966 struct net_device *dev);
6967 /* r8169_csum_workaround()
6968 * The hw limites the value the transport offset. When the offset is out of the
6969 * range, calculate the checksum by sw.
6970 */
6971 static void r8169_csum_workaround(struct rtl8169_private *tp,
6972 struct sk_buff *skb)
6973 {
6974 if (skb_shinfo(skb)->gso_size) {
6975 netdev_features_t features = tp->dev->features;
6976 struct sk_buff *segs, *nskb;
6977
6978 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6979 segs = skb_gso_segment(skb, features);
6980 if (IS_ERR(segs) || !segs)
6981 goto drop;
6982
6983 do {
6984 nskb = segs;
6985 segs = segs->next;
6986 nskb->next = NULL;
6987 rtl8169_start_xmit(nskb, tp->dev);
6988 } while (segs);
6989
6990 dev_consume_skb_any(skb);
6991 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6992 if (skb_checksum_help(skb) < 0)
6993 goto drop;
6994
6995 rtl8169_start_xmit(skb, tp->dev);
6996 } else {
6997 struct net_device_stats *stats;
6998
6999 drop:
7000 stats = &tp->dev->stats;
7001 stats->tx_dropped++;
7002 dev_kfree_skb_any(skb);
7003 }
7004 }
7005
7006 /* msdn_giant_send_check()
7007 * According to the document of microsoft, the TCP Pseudo Header excludes the
7008 * packet length for IPv6 TCP large packets.
7009 */
7010 static int msdn_giant_send_check(struct sk_buff *skb)
7011 {
7012 const struct ipv6hdr *ipv6h;
7013 struct tcphdr *th;
7014 int ret;
7015
7016 ret = skb_cow_head(skb, 0);
7017 if (ret)
7018 return ret;
7019
7020 ipv6h = ipv6_hdr(skb);
7021 th = tcp_hdr(skb);
7022
7023 th->check = 0;
7024 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
7025
7026 return ret;
7027 }
7028
7029 static inline __be16 get_protocol(struct sk_buff *skb)
7030 {
7031 __be16 protocol;
7032
7033 if (skb->protocol == htons(ETH_P_8021Q))
7034 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
7035 else
7036 protocol = skb->protocol;
7037
7038 return protocol;
7039 }
7040
7041 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
7042 struct sk_buff *skb, u32 *opts)
7043 {
7044 u32 mss = skb_shinfo(skb)->gso_size;
7045
7046 if (mss) {
7047 opts[0] |= TD_LSO;
7048 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
7049 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7050 const struct iphdr *ip = ip_hdr(skb);
7051
7052 if (ip->protocol == IPPROTO_TCP)
7053 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
7054 else if (ip->protocol == IPPROTO_UDP)
7055 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
7056 else
7057 WARN_ON_ONCE(1);
7058 }
7059
7060 return true;
7061 }
7062
7063 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
7064 struct sk_buff *skb, u32 *opts)
7065 {
7066 u32 transport_offset = (u32)skb_transport_offset(skb);
7067 u32 mss = skb_shinfo(skb)->gso_size;
7068
7069 if (mss) {
7070 if (transport_offset > GTTCPHO_MAX) {
7071 netif_warn(tp, tx_err, tp->dev,
7072 "Invalid transport offset 0x%x for TSO\n",
7073 transport_offset);
7074 return false;
7075 }
7076
7077 switch (get_protocol(skb)) {
7078 case htons(ETH_P_IP):
7079 opts[0] |= TD1_GTSENV4;
7080 break;
7081
7082 case htons(ETH_P_IPV6):
7083 if (msdn_giant_send_check(skb))
7084 return false;
7085
7086 opts[0] |= TD1_GTSENV6;
7087 break;
7088
7089 default:
7090 WARN_ON_ONCE(1);
7091 break;
7092 }
7093
7094 opts[0] |= transport_offset << GTTCPHO_SHIFT;
7095 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
7096 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7097 u8 ip_protocol;
7098
7099 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7100 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
7101
7102 if (transport_offset > TCPHO_MAX) {
7103 netif_warn(tp, tx_err, tp->dev,
7104 "Invalid transport offset 0x%x\n",
7105 transport_offset);
7106 return false;
7107 }
7108
7109 switch (get_protocol(skb)) {
7110 case htons(ETH_P_IP):
7111 opts[1] |= TD1_IPv4_CS;
7112 ip_protocol = ip_hdr(skb)->protocol;
7113 break;
7114
7115 case htons(ETH_P_IPV6):
7116 opts[1] |= TD1_IPv6_CS;
7117 ip_protocol = ipv6_hdr(skb)->nexthdr;
7118 break;
7119
7120 default:
7121 ip_protocol = IPPROTO_RAW;
7122 break;
7123 }
7124
7125 if (ip_protocol == IPPROTO_TCP)
7126 opts[1] |= TD1_TCP_CS;
7127 else if (ip_protocol == IPPROTO_UDP)
7128 opts[1] |= TD1_UDP_CS;
7129 else
7130 WARN_ON_ONCE(1);
7131
7132 opts[1] |= transport_offset << TCPHO_SHIFT;
7133 } else {
7134 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7135 return !eth_skb_pad(skb);
7136 }
7137
7138 return true;
7139 }
7140
7141 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7142 struct net_device *dev)
7143 {
7144 struct rtl8169_private *tp = netdev_priv(dev);
7145 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
7146 struct TxDesc *txd = tp->TxDescArray + entry;
7147 void __iomem *ioaddr = tp->mmio_addr;
7148 struct device *d = &tp->pci_dev->dev;
7149 dma_addr_t mapping;
7150 u32 status, len;
7151 u32 opts[2];
7152 int frags;
7153
7154 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
7155 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
7156 goto err_stop_0;
7157 }
7158
7159 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
7160 goto err_stop_0;
7161
7162 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
7163 opts[0] = DescOwn;
7164
7165 if (!tp->tso_csum(tp, skb, opts)) {
7166 r8169_csum_workaround(tp, skb);
7167 return NETDEV_TX_OK;
7168 }
7169
7170 len = skb_headlen(skb);
7171 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
7172 if (unlikely(dma_mapping_error(d, mapping))) {
7173 if (net_ratelimit())
7174 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
7175 goto err_dma_0;
7176 }
7177
7178 tp->tx_skb[entry].len = len;
7179 txd->addr = cpu_to_le64(mapping);
7180
7181 frags = rtl8169_xmit_frags(tp, skb, opts);
7182 if (frags < 0)
7183 goto err_dma_1;
7184 else if (frags)
7185 opts[0] |= FirstFrag;
7186 else {
7187 opts[0] |= FirstFrag | LastFrag;
7188 tp->tx_skb[entry].skb = skb;
7189 }
7190
7191 txd->opts2 = cpu_to_le32(opts[1]);
7192
7193 skb_tx_timestamp(skb);
7194
7195 /* Force memory writes to complete before releasing descriptor */
7196 dma_wmb();
7197
7198 /* Anti gcc 2.95.3 bugware (sic) */
7199 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
7200 txd->opts1 = cpu_to_le32(status);
7201
7202 /* Force all memory writes to complete before notifying device */
7203 wmb();
7204
7205 tp->cur_tx += frags + 1;
7206
7207 RTL_W8(TxPoll, NPQ);
7208
7209 mmiowb();
7210
7211 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7212 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7213 * not miss a ring update when it notices a stopped queue.
7214 */
7215 smp_wmb();
7216 netif_stop_queue(dev);
7217 /* Sync with rtl_tx:
7218 * - publish queue status and cur_tx ring index (write barrier)
7219 * - refresh dirty_tx ring index (read barrier).
7220 * May the current thread have a pessimistic view of the ring
7221 * status and forget to wake up queue, a racing rtl_tx thread
7222 * can't.
7223 */
7224 smp_mb();
7225 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
7226 netif_wake_queue(dev);
7227 }
7228
7229 return NETDEV_TX_OK;
7230
7231 err_dma_1:
7232 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
7233 err_dma_0:
7234 dev_kfree_skb_any(skb);
7235 dev->stats.tx_dropped++;
7236 return NETDEV_TX_OK;
7237
7238 err_stop_0:
7239 netif_stop_queue(dev);
7240 dev->stats.tx_dropped++;
7241 return NETDEV_TX_BUSY;
7242 }
7243
7244 static void rtl8169_pcierr_interrupt(struct net_device *dev)
7245 {
7246 struct rtl8169_private *tp = netdev_priv(dev);
7247 struct pci_dev *pdev = tp->pci_dev;
7248 u16 pci_status, pci_cmd;
7249
7250 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
7251 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
7252
7253 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7254 pci_cmd, pci_status);
7255
7256 /*
7257 * The recovery sequence below admits a very elaborated explanation:
7258 * - it seems to work;
7259 * - I did not see what else could be done;
7260 * - it makes iop3xx happy.
7261 *
7262 * Feel free to adjust to your needs.
7263 */
7264 if (pdev->broken_parity_status)
7265 pci_cmd &= ~PCI_COMMAND_PARITY;
7266 else
7267 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
7268
7269 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
7270
7271 pci_write_config_word(pdev, PCI_STATUS,
7272 pci_status & (PCI_STATUS_DETECTED_PARITY |
7273 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
7274 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
7275
7276 /* The infamous DAC f*ckup only happens at boot time */
7277 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
7278 void __iomem *ioaddr = tp->mmio_addr;
7279
7280 netif_info(tp, intr, dev, "disabling PCI DAC\n");
7281 tp->cp_cmd &= ~PCIDAC;
7282 RTL_W16(CPlusCmd, tp->cp_cmd);
7283 dev->features &= ~NETIF_F_HIGHDMA;
7284 }
7285
7286 rtl8169_hw_reset(tp);
7287
7288 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7289 }
7290
7291 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
7292 {
7293 unsigned int dirty_tx, tx_left;
7294
7295 dirty_tx = tp->dirty_tx;
7296 smp_rmb();
7297 tx_left = tp->cur_tx - dirty_tx;
7298
7299 while (tx_left > 0) {
7300 unsigned int entry = dirty_tx % NUM_TX_DESC;
7301 struct ring_info *tx_skb = tp->tx_skb + entry;
7302 u32 status;
7303
7304 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
7305 if (status & DescOwn)
7306 break;
7307
7308 /* This barrier is needed to keep us from reading
7309 * any other fields out of the Tx descriptor until
7310 * we know the status of DescOwn
7311 */
7312 dma_rmb();
7313
7314 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
7315 tp->TxDescArray + entry);
7316 if (status & LastFrag) {
7317 u64_stats_update_begin(&tp->tx_stats.syncp);
7318 tp->tx_stats.packets++;
7319 tp->tx_stats.bytes += tx_skb->skb->len;
7320 u64_stats_update_end(&tp->tx_stats.syncp);
7321 dev_consume_skb_any(tx_skb->skb);
7322 tx_skb->skb = NULL;
7323 }
7324 dirty_tx++;
7325 tx_left--;
7326 }
7327
7328 if (tp->dirty_tx != dirty_tx) {
7329 tp->dirty_tx = dirty_tx;
7330 /* Sync with rtl8169_start_xmit:
7331 * - publish dirty_tx ring index (write barrier)
7332 * - refresh cur_tx ring index and queue status (read barrier)
7333 * May the current thread miss the stopped queue condition,
7334 * a racing xmit thread can only have a right view of the
7335 * ring status.
7336 */
7337 smp_mb();
7338 if (netif_queue_stopped(dev) &&
7339 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7340 netif_wake_queue(dev);
7341 }
7342 /*
7343 * 8168 hack: TxPoll requests are lost when the Tx packets are
7344 * too close. Let's kick an extra TxPoll request when a burst
7345 * of start_xmit activity is detected (if it is not detected,
7346 * it is slow enough). -- FR
7347 */
7348 if (tp->cur_tx != dirty_tx) {
7349 void __iomem *ioaddr = tp->mmio_addr;
7350
7351 RTL_W8(TxPoll, NPQ);
7352 }
7353 }
7354 }
7355
7356 static inline int rtl8169_fragmented_frame(u32 status)
7357 {
7358 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
7359 }
7360
7361 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
7362 {
7363 u32 status = opts1 & RxProtoMask;
7364
7365 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
7366 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
7367 skb->ip_summed = CHECKSUM_UNNECESSARY;
7368 else
7369 skb_checksum_none_assert(skb);
7370 }
7371
7372 static struct sk_buff *rtl8169_try_rx_copy(void *data,
7373 struct rtl8169_private *tp,
7374 int pkt_size,
7375 dma_addr_t addr)
7376 {
7377 struct sk_buff *skb;
7378 struct device *d = &tp->pci_dev->dev;
7379
7380 data = rtl8169_align(data);
7381 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
7382 prefetch(data);
7383 skb = napi_alloc_skb(&tp->napi, pkt_size);
7384 if (skb)
7385 memcpy(skb->data, data, pkt_size);
7386 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
7387
7388 return skb;
7389 }
7390
7391 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
7392 {
7393 unsigned int cur_rx, rx_left;
7394 unsigned int count;
7395
7396 cur_rx = tp->cur_rx;
7397
7398 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
7399 unsigned int entry = cur_rx % NUM_RX_DESC;
7400 struct RxDesc *desc = tp->RxDescArray + entry;
7401 u32 status;
7402
7403 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
7404 if (status & DescOwn)
7405 break;
7406
7407 /* This barrier is needed to keep us from reading
7408 * any other fields out of the Rx descriptor until
7409 * we know the status of DescOwn
7410 */
7411 dma_rmb();
7412
7413 if (unlikely(status & RxRES)) {
7414 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
7415 status);
7416 dev->stats.rx_errors++;
7417 if (status & (RxRWT | RxRUNT))
7418 dev->stats.rx_length_errors++;
7419 if (status & RxCRC)
7420 dev->stats.rx_crc_errors++;
7421 if (status & RxFOVF) {
7422 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7423 dev->stats.rx_fifo_errors++;
7424 }
7425 if ((status & (RxRUNT | RxCRC)) &&
7426 !(status & (RxRWT | RxFOVF)) &&
7427 (dev->features & NETIF_F_RXALL))
7428 goto process_pkt;
7429 } else {
7430 struct sk_buff *skb;
7431 dma_addr_t addr;
7432 int pkt_size;
7433
7434 process_pkt:
7435 addr = le64_to_cpu(desc->addr);
7436 if (likely(!(dev->features & NETIF_F_RXFCS)))
7437 pkt_size = (status & 0x00003fff) - 4;
7438 else
7439 pkt_size = status & 0x00003fff;
7440
7441 /*
7442 * The driver does not support incoming fragmented
7443 * frames. They are seen as a symptom of over-mtu
7444 * sized frames.
7445 */
7446 if (unlikely(rtl8169_fragmented_frame(status))) {
7447 dev->stats.rx_dropped++;
7448 dev->stats.rx_length_errors++;
7449 goto release_descriptor;
7450 }
7451
7452 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
7453 tp, pkt_size, addr);
7454 if (!skb) {
7455 dev->stats.rx_dropped++;
7456 goto release_descriptor;
7457 }
7458
7459 rtl8169_rx_csum(skb, status);
7460 skb_put(skb, pkt_size);
7461 skb->protocol = eth_type_trans(skb, dev);
7462
7463 rtl8169_rx_vlan_tag(desc, skb);
7464
7465 if (skb->pkt_type == PACKET_MULTICAST)
7466 dev->stats.multicast++;
7467
7468 napi_gro_receive(&tp->napi, skb);
7469
7470 u64_stats_update_begin(&tp->rx_stats.syncp);
7471 tp->rx_stats.packets++;
7472 tp->rx_stats.bytes += pkt_size;
7473 u64_stats_update_end(&tp->rx_stats.syncp);
7474 }
7475 release_descriptor:
7476 desc->opts2 = 0;
7477 rtl8169_mark_to_asic(desc, rx_buf_sz);
7478 }
7479
7480 count = cur_rx - tp->cur_rx;
7481 tp->cur_rx = cur_rx;
7482
7483 return count;
7484 }
7485
7486 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
7487 {
7488 struct net_device *dev = dev_instance;
7489 struct rtl8169_private *tp = netdev_priv(dev);
7490 int handled = 0;
7491 u16 status;
7492
7493 status = rtl_get_events(tp);
7494 if (status && status != 0xffff) {
7495 status &= RTL_EVENT_NAPI | tp->event_slow;
7496 if (status) {
7497 handled = 1;
7498
7499 rtl_irq_disable(tp);
7500 napi_schedule(&tp->napi);
7501 }
7502 }
7503 return IRQ_RETVAL(handled);
7504 }
7505
7506 /*
7507 * Workqueue context.
7508 */
7509 static void rtl_slow_event_work(struct rtl8169_private *tp)
7510 {
7511 struct net_device *dev = tp->dev;
7512 u16 status;
7513
7514 status = rtl_get_events(tp) & tp->event_slow;
7515 rtl_ack_events(tp, status);
7516
7517 if (unlikely(status & RxFIFOOver)) {
7518 switch (tp->mac_version) {
7519 /* Work around for rx fifo overflow */
7520 case RTL_GIGA_MAC_VER_11:
7521 netif_stop_queue(dev);
7522 /* XXX - Hack alert. See rtl_task(). */
7523 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
7524 default:
7525 break;
7526 }
7527 }
7528
7529 if (unlikely(status & SYSErr))
7530 rtl8169_pcierr_interrupt(dev);
7531
7532 if (status & LinkChg)
7533 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
7534
7535 rtl_irq_enable_all(tp);
7536 }
7537
7538 static void rtl_task(struct work_struct *work)
7539 {
7540 static const struct {
7541 int bitnr;
7542 void (*action)(struct rtl8169_private *);
7543 } rtl_work[] = {
7544 /* XXX - keep rtl_slow_event_work() as first element. */
7545 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
7546 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
7547 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
7548 };
7549 struct rtl8169_private *tp =
7550 container_of(work, struct rtl8169_private, wk.work);
7551 struct net_device *dev = tp->dev;
7552 int i;
7553
7554 rtl_lock_work(tp);
7555
7556 if (!netif_running(dev) ||
7557 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
7558 goto out_unlock;
7559
7560 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7561 bool pending;
7562
7563 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
7564 if (pending)
7565 rtl_work[i].action(tp);
7566 }
7567
7568 out_unlock:
7569 rtl_unlock_work(tp);
7570 }
7571
7572 static int rtl8169_poll(struct napi_struct *napi, int budget)
7573 {
7574 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7575 struct net_device *dev = tp->dev;
7576 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
7577 int work_done= 0;
7578 u16 status;
7579
7580 status = rtl_get_events(tp);
7581 rtl_ack_events(tp, status & ~tp->event_slow);
7582
7583 if (status & RTL_EVENT_NAPI_RX)
7584 work_done = rtl_rx(dev, tp, (u32) budget);
7585
7586 if (status & RTL_EVENT_NAPI_TX)
7587 rtl_tx(dev, tp);
7588
7589 if (status & tp->event_slow) {
7590 enable_mask &= ~tp->event_slow;
7591
7592 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7593 }
7594
7595 if (work_done < budget) {
7596 napi_complete_done(napi, work_done);
7597
7598 rtl_irq_enable(tp, enable_mask);
7599 mmiowb();
7600 }
7601
7602 return work_done;
7603 }
7604
7605 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
7606 {
7607 struct rtl8169_private *tp = netdev_priv(dev);
7608
7609 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7610 return;
7611
7612 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
7613 RTL_W32(RxMissed, 0);
7614 }
7615
7616 static void rtl8169_down(struct net_device *dev)
7617 {
7618 struct rtl8169_private *tp = netdev_priv(dev);
7619 void __iomem *ioaddr = tp->mmio_addr;
7620
7621 del_timer_sync(&tp->timer);
7622
7623 napi_disable(&tp->napi);
7624 netif_stop_queue(dev);
7625
7626 rtl8169_hw_reset(tp);
7627 /*
7628 * At this point device interrupts can not be enabled in any function,
7629 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7630 * and napi is disabled (rtl8169_poll).
7631 */
7632 rtl8169_rx_missed(dev, ioaddr);
7633
7634 /* Give a racing hard_start_xmit a few cycles to complete. */
7635 synchronize_sched();
7636
7637 rtl8169_tx_clear(tp);
7638
7639 rtl8169_rx_clear(tp);
7640
7641 rtl_pll_power_down(tp);
7642 }
7643
7644 static int rtl8169_close(struct net_device *dev)
7645 {
7646 struct rtl8169_private *tp = netdev_priv(dev);
7647 struct pci_dev *pdev = tp->pci_dev;
7648
7649 pm_runtime_get_sync(&pdev->dev);
7650
7651 /* Update counters before going down */
7652 rtl8169_update_counters(dev);
7653
7654 rtl_lock_work(tp);
7655 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7656
7657 rtl8169_down(dev);
7658 rtl_unlock_work(tp);
7659
7660 cancel_work_sync(&tp->wk.work);
7661
7662 free_irq(pdev->irq, dev);
7663
7664 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7665 tp->RxPhyAddr);
7666 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7667 tp->TxPhyAddr);
7668 tp->TxDescArray = NULL;
7669 tp->RxDescArray = NULL;
7670
7671 pm_runtime_put_sync(&pdev->dev);
7672
7673 return 0;
7674 }
7675
7676 #ifdef CONFIG_NET_POLL_CONTROLLER
7677 static void rtl8169_netpoll(struct net_device *dev)
7678 {
7679 struct rtl8169_private *tp = netdev_priv(dev);
7680
7681 rtl8169_interrupt(tp->pci_dev->irq, dev);
7682 }
7683 #endif
7684
7685 static int rtl_open(struct net_device *dev)
7686 {
7687 struct rtl8169_private *tp = netdev_priv(dev);
7688 void __iomem *ioaddr = tp->mmio_addr;
7689 struct pci_dev *pdev = tp->pci_dev;
7690 int retval = -ENOMEM;
7691
7692 pm_runtime_get_sync(&pdev->dev);
7693
7694 /*
7695 * Rx and Tx descriptors needs 256 bytes alignment.
7696 * dma_alloc_coherent provides more.
7697 */
7698 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7699 &tp->TxPhyAddr, GFP_KERNEL);
7700 if (!tp->TxDescArray)
7701 goto err_pm_runtime_put;
7702
7703 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7704 &tp->RxPhyAddr, GFP_KERNEL);
7705 if (!tp->RxDescArray)
7706 goto err_free_tx_0;
7707
7708 retval = rtl8169_init_ring(dev);
7709 if (retval < 0)
7710 goto err_free_rx_1;
7711
7712 INIT_WORK(&tp->wk.work, rtl_task);
7713
7714 smp_mb();
7715
7716 rtl_request_firmware(tp);
7717
7718 retval = request_irq(pdev->irq, rtl8169_interrupt,
7719 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
7720 dev->name, dev);
7721 if (retval < 0)
7722 goto err_release_fw_2;
7723
7724 rtl_lock_work(tp);
7725
7726 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7727
7728 napi_enable(&tp->napi);
7729
7730 rtl8169_init_phy(dev, tp);
7731
7732 __rtl8169_set_features(dev, dev->features);
7733
7734 rtl_pll_power_up(tp);
7735
7736 rtl_hw_start(dev);
7737
7738 if (!rtl8169_init_counter_offsets(dev))
7739 netif_warn(tp, hw, dev, "counter reset/update failed\n");
7740
7741 netif_start_queue(dev);
7742
7743 rtl_unlock_work(tp);
7744
7745 tp->saved_wolopts = 0;
7746 pm_runtime_put_noidle(&pdev->dev);
7747
7748 rtl8169_check_link_status(dev, tp, ioaddr);
7749 out:
7750 return retval;
7751
7752 err_release_fw_2:
7753 rtl_release_firmware(tp);
7754 rtl8169_rx_clear(tp);
7755 err_free_rx_1:
7756 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7757 tp->RxPhyAddr);
7758 tp->RxDescArray = NULL;
7759 err_free_tx_0:
7760 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7761 tp->TxPhyAddr);
7762 tp->TxDescArray = NULL;
7763 err_pm_runtime_put:
7764 pm_runtime_put_noidle(&pdev->dev);
7765 goto out;
7766 }
7767
7768 static void
7769 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7770 {
7771 struct rtl8169_private *tp = netdev_priv(dev);
7772 void __iomem *ioaddr = tp->mmio_addr;
7773 struct pci_dev *pdev = tp->pci_dev;
7774 struct rtl8169_counters *counters = tp->counters;
7775 unsigned int start;
7776
7777 pm_runtime_get_noresume(&pdev->dev);
7778
7779 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
7780 rtl8169_rx_missed(dev, ioaddr);
7781
7782 do {
7783 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
7784 stats->rx_packets = tp->rx_stats.packets;
7785 stats->rx_bytes = tp->rx_stats.bytes;
7786 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
7787
7788 do {
7789 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
7790 stats->tx_packets = tp->tx_stats.packets;
7791 stats->tx_bytes = tp->tx_stats.bytes;
7792 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
7793
7794 stats->rx_dropped = dev->stats.rx_dropped;
7795 stats->tx_dropped = dev->stats.tx_dropped;
7796 stats->rx_length_errors = dev->stats.rx_length_errors;
7797 stats->rx_errors = dev->stats.rx_errors;
7798 stats->rx_crc_errors = dev->stats.rx_crc_errors;
7799 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
7800 stats->rx_missed_errors = dev->stats.rx_missed_errors;
7801 stats->multicast = dev->stats.multicast;
7802
7803 /*
7804 * Fetch additonal counter values missing in stats collected by driver
7805 * from tally counters.
7806 */
7807 if (pm_runtime_active(&pdev->dev))
7808 rtl8169_update_counters(dev);
7809
7810 /*
7811 * Subtract values fetched during initalization.
7812 * See rtl8169_init_counter_offsets for a description why we do that.
7813 */
7814 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
7815 le64_to_cpu(tp->tc_offset.tx_errors);
7816 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
7817 le32_to_cpu(tp->tc_offset.tx_multi_collision);
7818 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
7819 le16_to_cpu(tp->tc_offset.tx_aborted);
7820
7821 pm_runtime_put_noidle(&pdev->dev);
7822 }
7823
7824 static void rtl8169_net_suspend(struct net_device *dev)
7825 {
7826 struct rtl8169_private *tp = netdev_priv(dev);
7827
7828 if (!netif_running(dev))
7829 return;
7830
7831 netif_device_detach(dev);
7832 netif_stop_queue(dev);
7833
7834 rtl_lock_work(tp);
7835 napi_disable(&tp->napi);
7836 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7837 rtl_unlock_work(tp);
7838
7839 rtl_pll_power_down(tp);
7840 }
7841
7842 #ifdef CONFIG_PM
7843
7844 static int rtl8169_suspend(struct device *device)
7845 {
7846 struct pci_dev *pdev = to_pci_dev(device);
7847 struct net_device *dev = pci_get_drvdata(pdev);
7848
7849 rtl8169_net_suspend(dev);
7850
7851 return 0;
7852 }
7853
7854 static void __rtl8169_resume(struct net_device *dev)
7855 {
7856 struct rtl8169_private *tp = netdev_priv(dev);
7857
7858 netif_device_attach(dev);
7859
7860 rtl_pll_power_up(tp);
7861
7862 rtl_lock_work(tp);
7863 napi_enable(&tp->napi);
7864 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7865 rtl_unlock_work(tp);
7866
7867 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7868 }
7869
7870 static int rtl8169_resume(struct device *device)
7871 {
7872 struct pci_dev *pdev = to_pci_dev(device);
7873 struct net_device *dev = pci_get_drvdata(pdev);
7874 struct rtl8169_private *tp = netdev_priv(dev);
7875
7876 rtl8169_init_phy(dev, tp);
7877
7878 if (netif_running(dev))
7879 __rtl8169_resume(dev);
7880
7881 return 0;
7882 }
7883
7884 static int rtl8169_runtime_suspend(struct device *device)
7885 {
7886 struct pci_dev *pdev = to_pci_dev(device);
7887 struct net_device *dev = pci_get_drvdata(pdev);
7888 struct rtl8169_private *tp = netdev_priv(dev);
7889
7890 if (!tp->TxDescArray)
7891 return 0;
7892
7893 rtl_lock_work(tp);
7894 tp->saved_wolopts = __rtl8169_get_wol(tp);
7895 __rtl8169_set_wol(tp, WAKE_ANY);
7896 rtl_unlock_work(tp);
7897
7898 rtl8169_net_suspend(dev);
7899
7900 /* Update counters before going runtime suspend */
7901 rtl8169_rx_missed(dev, tp->mmio_addr);
7902 rtl8169_update_counters(dev);
7903
7904 return 0;
7905 }
7906
7907 static int rtl8169_runtime_resume(struct device *device)
7908 {
7909 struct pci_dev *pdev = to_pci_dev(device);
7910 struct net_device *dev = pci_get_drvdata(pdev);
7911 struct rtl8169_private *tp = netdev_priv(dev);
7912 rtl_rar_set(tp, dev->dev_addr);
7913
7914 if (!tp->TxDescArray)
7915 return 0;
7916
7917 rtl_lock_work(tp);
7918 __rtl8169_set_wol(tp, tp->saved_wolopts);
7919 tp->saved_wolopts = 0;
7920 rtl_unlock_work(tp);
7921
7922 rtl8169_init_phy(dev, tp);
7923
7924 __rtl8169_resume(dev);
7925
7926 return 0;
7927 }
7928
7929 static int rtl8169_runtime_idle(struct device *device)
7930 {
7931 struct pci_dev *pdev = to_pci_dev(device);
7932 struct net_device *dev = pci_get_drvdata(pdev);
7933 struct rtl8169_private *tp = netdev_priv(dev);
7934
7935 return tp->TxDescArray ? -EBUSY : 0;
7936 }
7937
7938 static const struct dev_pm_ops rtl8169_pm_ops = {
7939 .suspend = rtl8169_suspend,
7940 .resume = rtl8169_resume,
7941 .freeze = rtl8169_suspend,
7942 .thaw = rtl8169_resume,
7943 .poweroff = rtl8169_suspend,
7944 .restore = rtl8169_resume,
7945 .runtime_suspend = rtl8169_runtime_suspend,
7946 .runtime_resume = rtl8169_runtime_resume,
7947 .runtime_idle = rtl8169_runtime_idle,
7948 };
7949
7950 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
7951
7952 #else /* !CONFIG_PM */
7953
7954 #define RTL8169_PM_OPS NULL
7955
7956 #endif /* !CONFIG_PM */
7957
7958 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7959 {
7960 void __iomem *ioaddr = tp->mmio_addr;
7961
7962 /* WoL fails with 8168b when the receiver is disabled. */
7963 switch (tp->mac_version) {
7964 case RTL_GIGA_MAC_VER_11:
7965 case RTL_GIGA_MAC_VER_12:
7966 case RTL_GIGA_MAC_VER_17:
7967 pci_clear_master(tp->pci_dev);
7968
7969 RTL_W8(ChipCmd, CmdRxEnb);
7970 /* PCI commit */
7971 RTL_R8(ChipCmd);
7972 break;
7973 default:
7974 break;
7975 }
7976 }
7977
7978 static void rtl_shutdown(struct pci_dev *pdev)
7979 {
7980 struct net_device *dev = pci_get_drvdata(pdev);
7981 struct rtl8169_private *tp = netdev_priv(dev);
7982 struct device *d = &pdev->dev;
7983
7984 pm_runtime_get_sync(d);
7985
7986 rtl8169_net_suspend(dev);
7987
7988 /* Restore original MAC address */
7989 rtl_rar_set(tp, dev->perm_addr);
7990
7991 rtl8169_hw_reset(tp);
7992
7993 if (system_state == SYSTEM_POWER_OFF) {
7994 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
7995 rtl_wol_suspend_quirk(tp);
7996 rtl_wol_shutdown_quirk(tp);
7997 }
7998
7999 pci_wake_from_d3(pdev, true);
8000 pci_set_power_state(pdev, PCI_D3hot);
8001 }
8002
8003 pm_runtime_put_noidle(d);
8004 }
8005
8006 static void rtl_remove_one(struct pci_dev *pdev)
8007 {
8008 struct net_device *dev = pci_get_drvdata(pdev);
8009 struct rtl8169_private *tp = netdev_priv(dev);
8010
8011 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8012 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
8013 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8014 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8015 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8016 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
8017 r8168_check_dash(tp)) {
8018 rtl8168_driver_stop(tp);
8019 }
8020
8021 netif_napi_del(&tp->napi);
8022
8023 unregister_netdev(dev);
8024
8025 dma_free_coherent(&tp->pci_dev->dev, sizeof(*tp->counters),
8026 tp->counters, tp->counters_phys_addr);
8027
8028 rtl_release_firmware(tp);
8029
8030 if (pci_dev_run_wake(pdev))
8031 pm_runtime_get_noresume(&pdev->dev);
8032
8033 /* restore original MAC address */
8034 rtl_rar_set(tp, dev->perm_addr);
8035
8036 rtl_disable_msi(pdev, tp);
8037 rtl8169_release_board(pdev, dev, tp->mmio_addr);
8038 }
8039
8040 static const struct net_device_ops rtl_netdev_ops = {
8041 .ndo_open = rtl_open,
8042 .ndo_stop = rtl8169_close,
8043 .ndo_get_stats64 = rtl8169_get_stats64,
8044 .ndo_start_xmit = rtl8169_start_xmit,
8045 .ndo_tx_timeout = rtl8169_tx_timeout,
8046 .ndo_validate_addr = eth_validate_addr,
8047 .ndo_change_mtu = rtl8169_change_mtu,
8048 .ndo_fix_features = rtl8169_fix_features,
8049 .ndo_set_features = rtl8169_set_features,
8050 .ndo_set_mac_address = rtl_set_mac_address,
8051 .ndo_do_ioctl = rtl8169_ioctl,
8052 .ndo_set_rx_mode = rtl_set_rx_mode,
8053 #ifdef CONFIG_NET_POLL_CONTROLLER
8054 .ndo_poll_controller = rtl8169_netpoll,
8055 #endif
8056
8057 };
8058
8059 static const struct rtl_cfg_info {
8060 void (*hw_start)(struct net_device *);
8061 unsigned int region;
8062 unsigned int align;
8063 u16 event_slow;
8064 unsigned features;
8065 u8 default_ver;
8066 } rtl_cfg_infos [] = {
8067 [RTL_CFG_0] = {
8068 .hw_start = rtl_hw_start_8169,
8069 .region = 1,
8070 .align = 0,
8071 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
8072 .features = RTL_FEATURE_GMII,
8073 .default_ver = RTL_GIGA_MAC_VER_01,
8074 },
8075 [RTL_CFG_1] = {
8076 .hw_start = rtl_hw_start_8168,
8077 .region = 2,
8078 .align = 8,
8079 .event_slow = SYSErr | LinkChg | RxOverflow,
8080 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
8081 .default_ver = RTL_GIGA_MAC_VER_11,
8082 },
8083 [RTL_CFG_2] = {
8084 .hw_start = rtl_hw_start_8101,
8085 .region = 2,
8086 .align = 8,
8087 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
8088 PCSTimeout,
8089 .features = RTL_FEATURE_MSI,
8090 .default_ver = RTL_GIGA_MAC_VER_13,
8091 }
8092 };
8093
8094 /* Cfg9346_Unlock assumed. */
8095 static unsigned rtl_try_msi(struct rtl8169_private *tp,
8096 const struct rtl_cfg_info *cfg)
8097 {
8098 void __iomem *ioaddr = tp->mmio_addr;
8099 unsigned msi = 0;
8100 u8 cfg2;
8101
8102 cfg2 = RTL_R8(Config2) & ~MSIEnable;
8103 if (cfg->features & RTL_FEATURE_MSI) {
8104 if (pci_enable_msi(tp->pci_dev)) {
8105 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
8106 } else {
8107 cfg2 |= MSIEnable;
8108 msi = RTL_FEATURE_MSI;
8109 }
8110 }
8111 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
8112 RTL_W8(Config2, cfg2);
8113 return msi;
8114 }
8115
8116 DECLARE_RTL_COND(rtl_link_list_ready_cond)
8117 {
8118 void __iomem *ioaddr = tp->mmio_addr;
8119
8120 return RTL_R8(MCU) & LINK_LIST_RDY;
8121 }
8122
8123 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
8124 {
8125 void __iomem *ioaddr = tp->mmio_addr;
8126
8127 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
8128 }
8129
8130 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
8131 {
8132 void __iomem *ioaddr = tp->mmio_addr;
8133 u32 data;
8134
8135 tp->ocp_base = OCP_STD_PHY_BASE;
8136
8137 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
8138
8139 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
8140 return;
8141
8142 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
8143 return;
8144
8145 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
8146 msleep(1);
8147 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
8148
8149 data = r8168_mac_ocp_read(tp, 0xe8de);
8150 data &= ~(1 << 14);
8151 r8168_mac_ocp_write(tp, 0xe8de, data);
8152
8153 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8154 return;
8155
8156 data = r8168_mac_ocp_read(tp, 0xe8de);
8157 data |= (1 << 15);
8158 r8168_mac_ocp_write(tp, 0xe8de, data);
8159
8160 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8161 return;
8162 }
8163
8164 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
8165 {
8166 rtl8168ep_stop_cmac(tp);
8167 rtl_hw_init_8168g(tp);
8168 }
8169
8170 static void rtl_hw_initialize(struct rtl8169_private *tp)
8171 {
8172 switch (tp->mac_version) {
8173 case RTL_GIGA_MAC_VER_40:
8174 case RTL_GIGA_MAC_VER_41:
8175 case RTL_GIGA_MAC_VER_42:
8176 case RTL_GIGA_MAC_VER_43:
8177 case RTL_GIGA_MAC_VER_44:
8178 case RTL_GIGA_MAC_VER_45:
8179 case RTL_GIGA_MAC_VER_46:
8180 case RTL_GIGA_MAC_VER_47:
8181 case RTL_GIGA_MAC_VER_48:
8182 rtl_hw_init_8168g(tp);
8183 break;
8184 case RTL_GIGA_MAC_VER_49:
8185 case RTL_GIGA_MAC_VER_50:
8186 case RTL_GIGA_MAC_VER_51:
8187 rtl_hw_init_8168ep(tp);
8188 break;
8189 default:
8190 break;
8191 }
8192 }
8193
8194 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8195 {
8196 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
8197 const unsigned int region = cfg->region;
8198 struct rtl8169_private *tp;
8199 struct mii_if_info *mii;
8200 struct net_device *dev;
8201 void __iomem *ioaddr;
8202 int chipset, i;
8203 int rc;
8204
8205 if (netif_msg_drv(&debug)) {
8206 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
8207 MODULENAME, RTL8169_VERSION);
8208 }
8209
8210 dev = alloc_etherdev(sizeof (*tp));
8211 if (!dev) {
8212 rc = -ENOMEM;
8213 goto out;
8214 }
8215
8216 SET_NETDEV_DEV(dev, &pdev->dev);
8217 dev->netdev_ops = &rtl_netdev_ops;
8218 tp = netdev_priv(dev);
8219 tp->dev = dev;
8220 tp->pci_dev = pdev;
8221 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
8222
8223 mii = &tp->mii;
8224 mii->dev = dev;
8225 mii->mdio_read = rtl_mdio_read;
8226 mii->mdio_write = rtl_mdio_write;
8227 mii->phy_id_mask = 0x1f;
8228 mii->reg_num_mask = 0x1f;
8229 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
8230
8231 /* disable ASPM completely as that cause random device stop working
8232 * problems as well as full system hangs for some PCIe devices users */
8233 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
8234 PCIE_LINK_STATE_CLKPM);
8235
8236 /* enable device (incl. PCI PM wakeup and hotplug setup) */
8237 rc = pci_enable_device(pdev);
8238 if (rc < 0) {
8239 netif_err(tp, probe, dev, "enable failure\n");
8240 goto err_out_free_dev_1;
8241 }
8242
8243 if (pci_set_mwi(pdev) < 0)
8244 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
8245
8246 /* make sure PCI base addr 1 is MMIO */
8247 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
8248 netif_err(tp, probe, dev,
8249 "region #%d not an MMIO resource, aborting\n",
8250 region);
8251 rc = -ENODEV;
8252 goto err_out_mwi_2;
8253 }
8254
8255 /* check for weird/broken PCI region reporting */
8256 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
8257 netif_err(tp, probe, dev,
8258 "Invalid PCI region size(s), aborting\n");
8259 rc = -ENODEV;
8260 goto err_out_mwi_2;
8261 }
8262
8263 rc = pci_request_regions(pdev, MODULENAME);
8264 if (rc < 0) {
8265 netif_err(tp, probe, dev, "could not request regions\n");
8266 goto err_out_mwi_2;
8267 }
8268
8269 /* ioremap MMIO region */
8270 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
8271 if (!ioaddr) {
8272 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
8273 rc = -EIO;
8274 goto err_out_free_res_3;
8275 }
8276 tp->mmio_addr = ioaddr;
8277
8278 if (!pci_is_pcie(pdev))
8279 netif_info(tp, probe, dev, "not PCI Express\n");
8280
8281 /* Identify chip attached to board */
8282 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
8283
8284 tp->cp_cmd = 0;
8285
8286 if ((sizeof(dma_addr_t) > 4) &&
8287 (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
8288 tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
8289 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
8290 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
8291
8292 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
8293 if (!pci_is_pcie(pdev))
8294 tp->cp_cmd |= PCIDAC;
8295 dev->features |= NETIF_F_HIGHDMA;
8296 } else {
8297 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8298 if (rc < 0) {
8299 netif_err(tp, probe, dev, "DMA configuration failed\n");
8300 goto err_out_unmap_4;
8301 }
8302 }
8303
8304 rtl_init_rxcfg(tp);
8305
8306 rtl_irq_disable(tp);
8307
8308 rtl_hw_initialize(tp);
8309
8310 rtl_hw_reset(tp);
8311
8312 rtl_ack_events(tp, 0xffff);
8313
8314 pci_set_master(pdev);
8315
8316 rtl_init_mdio_ops(tp);
8317 rtl_init_pll_power_ops(tp);
8318 rtl_init_jumbo_ops(tp);
8319 rtl_init_csi_ops(tp);
8320
8321 rtl8169_print_mac_version(tp);
8322
8323 chipset = tp->mac_version;
8324 tp->txd_version = rtl_chip_infos[chipset].txd_version;
8325
8326 RTL_W8(Cfg9346, Cfg9346_Unlock);
8327 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
8328 RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
8329 switch (tp->mac_version) {
8330 case RTL_GIGA_MAC_VER_34:
8331 case RTL_GIGA_MAC_VER_35:
8332 case RTL_GIGA_MAC_VER_36:
8333 case RTL_GIGA_MAC_VER_37:
8334 case RTL_GIGA_MAC_VER_38:
8335 case RTL_GIGA_MAC_VER_40:
8336 case RTL_GIGA_MAC_VER_41:
8337 case RTL_GIGA_MAC_VER_42:
8338 case RTL_GIGA_MAC_VER_43:
8339 case RTL_GIGA_MAC_VER_44:
8340 case RTL_GIGA_MAC_VER_45:
8341 case RTL_GIGA_MAC_VER_46:
8342 case RTL_GIGA_MAC_VER_47:
8343 case RTL_GIGA_MAC_VER_48:
8344 case RTL_GIGA_MAC_VER_49:
8345 case RTL_GIGA_MAC_VER_50:
8346 case RTL_GIGA_MAC_VER_51:
8347 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
8348 tp->features |= RTL_FEATURE_WOL;
8349 if ((RTL_R8(Config3) & LinkUp) != 0)
8350 tp->features |= RTL_FEATURE_WOL;
8351 break;
8352 default:
8353 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
8354 tp->features |= RTL_FEATURE_WOL;
8355 break;
8356 }
8357 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
8358 tp->features |= RTL_FEATURE_WOL;
8359 tp->features |= rtl_try_msi(tp, cfg);
8360 RTL_W8(Cfg9346, Cfg9346_Lock);
8361
8362 if (rtl_tbi_enabled(tp)) {
8363 tp->set_speed = rtl8169_set_speed_tbi;
8364 tp->get_link_ksettings = rtl8169_get_link_ksettings_tbi;
8365 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
8366 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
8367 tp->link_ok = rtl8169_tbi_link_ok;
8368 tp->do_ioctl = rtl_tbi_ioctl;
8369 } else {
8370 tp->set_speed = rtl8169_set_speed_xmii;
8371 tp->get_link_ksettings = rtl8169_get_link_ksettings_xmii;
8372 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
8373 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
8374 tp->link_ok = rtl8169_xmii_link_ok;
8375 tp->do_ioctl = rtl_xmii_ioctl;
8376 }
8377
8378 mutex_init(&tp->wk.mutex);
8379 u64_stats_init(&tp->rx_stats.syncp);
8380 u64_stats_init(&tp->tx_stats.syncp);
8381
8382 /* Get MAC address */
8383 if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
8384 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
8385 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
8386 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
8387 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
8388 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
8389 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
8390 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
8391 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
8392 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
8393 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
8394 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
8395 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
8396 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8397 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8398 tp->mac_version == RTL_GIGA_MAC_VER_51) {
8399 u16 mac_addr[3];
8400
8401 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
8402 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
8403
8404 if (is_valid_ether_addr((u8 *)mac_addr))
8405 rtl_rar_set(tp, (u8 *)mac_addr);
8406 }
8407 for (i = 0; i < ETH_ALEN; i++)
8408 dev->dev_addr[i] = RTL_R8(MAC0 + i);
8409
8410 dev->ethtool_ops = &rtl8169_ethtool_ops;
8411 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
8412
8413 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
8414
8415 /* don't enable SG, IP_CSUM and TSO by default - it might not work
8416 * properly for all devices */
8417 dev->features |= NETIF_F_RXCSUM |
8418 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
8419
8420 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8421 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
8422 NETIF_F_HW_VLAN_CTAG_RX;
8423 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8424 NETIF_F_HIGHDMA;
8425
8426 tp->cp_cmd |= RxChkSum | RxVlan;
8427
8428 /*
8429 * Pretend we are using VLANs; This bypasses a nasty bug where
8430 * Interrupts stop flowing on high load on 8110SCd controllers.
8431 */
8432 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
8433 /* Disallow toggling */
8434 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
8435
8436 if (tp->txd_version == RTL_TD_0)
8437 tp->tso_csum = rtl8169_tso_csum_v1;
8438 else if (tp->txd_version == RTL_TD_1) {
8439 tp->tso_csum = rtl8169_tso_csum_v2;
8440 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8441 } else
8442 WARN_ON_ONCE(1);
8443
8444 dev->hw_features |= NETIF_F_RXALL;
8445 dev->hw_features |= NETIF_F_RXFCS;
8446
8447 /* MTU range: 60 - hw-specific max */
8448 dev->min_mtu = ETH_ZLEN;
8449 dev->max_mtu = rtl_chip_infos[chipset].jumbo_max;
8450
8451 tp->hw_start = cfg->hw_start;
8452 tp->event_slow = cfg->event_slow;
8453
8454 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
8455 ~(RxBOVF | RxFOVF) : ~0;
8456
8457 setup_timer(&tp->timer, rtl8169_phy_timer, (unsigned long)dev);
8458
8459 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
8460
8461 tp->counters = dma_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
8462 &tp->counters_phys_addr, GFP_KERNEL);
8463 if (!tp->counters) {
8464 rc = -ENOMEM;
8465 goto err_out_msi_5;
8466 }
8467
8468 rc = register_netdev(dev);
8469 if (rc < 0)
8470 goto err_out_cnt_6;
8471
8472 pci_set_drvdata(pdev, dev);
8473
8474 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
8475 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
8476 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
8477 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
8478 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
8479 "tx checksumming: %s]\n",
8480 rtl_chip_infos[chipset].jumbo_max,
8481 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
8482 }
8483
8484 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8485 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
8486 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8487 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8488 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8489 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
8490 r8168_check_dash(tp)) {
8491 rtl8168_driver_start(tp);
8492 }
8493
8494 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
8495
8496 if (pci_dev_run_wake(pdev))
8497 pm_runtime_put_noidle(&pdev->dev);
8498
8499 netif_carrier_off(dev);
8500
8501 out:
8502 return rc;
8503
8504 err_out_cnt_6:
8505 dma_free_coherent(&pdev->dev, sizeof(*tp->counters), tp->counters,
8506 tp->counters_phys_addr);
8507 err_out_msi_5:
8508 netif_napi_del(&tp->napi);
8509 rtl_disable_msi(pdev, tp);
8510 err_out_unmap_4:
8511 iounmap(ioaddr);
8512 err_out_free_res_3:
8513 pci_release_regions(pdev);
8514 err_out_mwi_2:
8515 pci_clear_mwi(pdev);
8516 pci_disable_device(pdev);
8517 err_out_free_dev_1:
8518 free_netdev(dev);
8519 goto out;
8520 }
8521
8522 static struct pci_driver rtl8169_pci_driver = {
8523 .name = MODULENAME,
8524 .id_table = rtl8169_pci_tbl,
8525 .probe = rtl_init_one,
8526 .remove = rtl_remove_one,
8527 .shutdown = rtl_shutdown,
8528 .driver.pm = RTL8169_PM_OPS,
8529 };
8530
8531 module_pci_driver(rtl8169_pci_driver);
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