2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/pci-aspm.h>
30 #include <linux/prefetch.h>
32 #include <asm/system.h>
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
45 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
47 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
50 #define assert(expr) \
52 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
53 #expr,__FILE__,__func__,__LINE__); \
55 #define dprintk(fmt, args...) \
56 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
58 #define assert(expr) do {} while (0)
59 #define dprintk(fmt, args...) do {} while (0)
60 #endif /* RTL8169_DEBUG */
62 #define R8169_MSG_DEFAULT \
63 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
65 #define TX_BUFFS_AVAIL(tp) \
66 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
68 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
69 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
70 static const int multicast_filter_limit
= 32;
72 /* MAC address length */
73 #define MAC_ADDR_LEN 6
75 #define MAX_READ_REQUEST_SHIFT 12
76 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
77 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
78 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
80 #define R8169_REGS_SIZE 256
81 #define R8169_NAPI_WEIGHT 64
82 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
83 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
84 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
85 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
86 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
88 #define RTL8169_TX_TIMEOUT (6*HZ)
89 #define RTL8169_PHY_TIMEOUT (10*HZ)
91 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
92 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
93 #define RTL_EEPROM_SIG_ADDR 0x0000
95 /* write/read MMIO register */
96 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
97 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
98 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
99 #define RTL_R8(reg) readb (ioaddr + (reg))
100 #define RTL_R16(reg) readw (ioaddr + (reg))
101 #define RTL_R32(reg) readl (ioaddr + (reg))
104 RTL_GIGA_MAC_VER_01
= 0,
140 RTL_GIGA_MAC_NONE
= 0xff,
143 enum rtl_tx_desc_version
{
148 #define JUMBO_1K ETH_DATA_LEN
149 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
150 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
151 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
152 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
154 #define _R(NAME,TD,FW,SZ,B) { \
162 static const struct {
164 enum rtl_tx_desc_version txd_version
;
168 } rtl_chip_infos
[] = {
170 [RTL_GIGA_MAC_VER_01
] =
171 _R("RTL8169", RTL_TD_0
, NULL
, JUMBO_7K
, true),
172 [RTL_GIGA_MAC_VER_02
] =
173 _R("RTL8169s", RTL_TD_0
, NULL
, JUMBO_7K
, true),
174 [RTL_GIGA_MAC_VER_03
] =
175 _R("RTL8110s", RTL_TD_0
, NULL
, JUMBO_7K
, true),
176 [RTL_GIGA_MAC_VER_04
] =
177 _R("RTL8169sb/8110sb", RTL_TD_0
, NULL
, JUMBO_7K
, true),
178 [RTL_GIGA_MAC_VER_05
] =
179 _R("RTL8169sc/8110sc", RTL_TD_0
, NULL
, JUMBO_7K
, true),
180 [RTL_GIGA_MAC_VER_06
] =
181 _R("RTL8169sc/8110sc", RTL_TD_0
, NULL
, JUMBO_7K
, true),
183 [RTL_GIGA_MAC_VER_07
] =
184 _R("RTL8102e", RTL_TD_1
, NULL
, JUMBO_1K
, true),
185 [RTL_GIGA_MAC_VER_08
] =
186 _R("RTL8102e", RTL_TD_1
, NULL
, JUMBO_1K
, true),
187 [RTL_GIGA_MAC_VER_09
] =
188 _R("RTL8102e", RTL_TD_1
, NULL
, JUMBO_1K
, true),
189 [RTL_GIGA_MAC_VER_10
] =
190 _R("RTL8101e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
191 [RTL_GIGA_MAC_VER_11
] =
192 _R("RTL8168b/8111b", RTL_TD_0
, NULL
, JUMBO_4K
, false),
193 [RTL_GIGA_MAC_VER_12
] =
194 _R("RTL8168b/8111b", RTL_TD_0
, NULL
, JUMBO_4K
, false),
195 [RTL_GIGA_MAC_VER_13
] =
196 _R("RTL8101e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
197 [RTL_GIGA_MAC_VER_14
] =
198 _R("RTL8100e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
199 [RTL_GIGA_MAC_VER_15
] =
200 _R("RTL8100e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
201 [RTL_GIGA_MAC_VER_16
] =
202 _R("RTL8101e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
203 [RTL_GIGA_MAC_VER_17
] =
204 _R("RTL8168b/8111b", RTL_TD_1
, NULL
, JUMBO_4K
, false),
205 [RTL_GIGA_MAC_VER_18
] =
206 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
, JUMBO_6K
, false),
207 [RTL_GIGA_MAC_VER_19
] =
208 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
209 [RTL_GIGA_MAC_VER_20
] =
210 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
211 [RTL_GIGA_MAC_VER_21
] =
212 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
213 [RTL_GIGA_MAC_VER_22
] =
214 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
215 [RTL_GIGA_MAC_VER_23
] =
216 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
, JUMBO_6K
, false),
217 [RTL_GIGA_MAC_VER_24
] =
218 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
, JUMBO_6K
, false),
219 [RTL_GIGA_MAC_VER_25
] =
220 _R("RTL8168d/8111d", RTL_TD_1
, FIRMWARE_8168D_1
,
222 [RTL_GIGA_MAC_VER_26
] =
223 _R("RTL8168d/8111d", RTL_TD_1
, FIRMWARE_8168D_2
,
225 [RTL_GIGA_MAC_VER_27
] =
226 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
, JUMBO_9K
, false),
227 [RTL_GIGA_MAC_VER_28
] =
228 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
, JUMBO_9K
, false),
229 [RTL_GIGA_MAC_VER_29
] =
230 _R("RTL8105e", RTL_TD_1
, FIRMWARE_8105E_1
,
232 [RTL_GIGA_MAC_VER_30
] =
233 _R("RTL8105e", RTL_TD_1
, FIRMWARE_8105E_1
,
235 [RTL_GIGA_MAC_VER_31
] =
236 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
, JUMBO_9K
, false),
237 [RTL_GIGA_MAC_VER_32
] =
238 _R("RTL8168e/8111e", RTL_TD_1
, FIRMWARE_8168E_1
,
240 [RTL_GIGA_MAC_VER_33
] =
241 _R("RTL8168e/8111e", RTL_TD_1
, FIRMWARE_8168E_2
,
243 [RTL_GIGA_MAC_VER_34
] =
244 _R("RTL8168evl/8111evl",RTL_TD_1
, FIRMWARE_8168E_3
,
246 [RTL_GIGA_MAC_VER_35
] =
247 _R("RTL8168f/8111f", RTL_TD_1
, FIRMWARE_8168F_1
,
249 [RTL_GIGA_MAC_VER_36
] =
250 _R("RTL8168f/8111f", RTL_TD_1
, FIRMWARE_8168F_2
,
261 static void rtl_hw_start_8169(struct net_device
*);
262 static void rtl_hw_start_8168(struct net_device
*);
263 static void rtl_hw_start_8101(struct net_device
*);
265 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl
) = {
266 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
267 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
268 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
269 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
270 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
271 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
272 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4302), 0, 0, RTL_CFG_0
},
273 { PCI_DEVICE(PCI_VENDOR_ID_AT
, 0xc107), 0, 0, RTL_CFG_0
},
274 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
275 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
276 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
278 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
282 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
284 static int rx_buf_sz
= 16383;
291 MAC0
= 0, /* Ethernet hardware address. */
293 MAR0
= 8, /* Multicast filter. */
294 CounterAddrLow
= 0x10,
295 CounterAddrHigh
= 0x14,
296 TxDescStartAddrLow
= 0x20,
297 TxDescStartAddrHigh
= 0x24,
298 TxHDescStartAddrLow
= 0x28,
299 TxHDescStartAddrHigh
= 0x2c,
308 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
309 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
312 #define RX128_INT_EN (1 << 15) /* 8111c and later */
313 #define RX_MULTI_EN (1 << 14) /* 8111c only */
314 #define RXCFG_FIFO_SHIFT 13
315 /* No threshold before first PCI xfer */
316 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
317 #define RXCFG_DMA_SHIFT 8
318 /* Unlimited maximum PCI burst. */
319 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
335 RxDescAddrLow
= 0xe4,
336 RxDescAddrHigh
= 0xe8,
337 EarlyTxThres
= 0xec, /* 8169. Unit of 32 bytes. */
339 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
341 MaxTxPacketSize
= 0xec, /* 8101/8168. Unit of 128 bytes. */
343 #define TxPacketMax (8064 >> 7)
344 #define EarlySize 0x27
347 FuncEventMask
= 0xf4,
348 FuncPresetState
= 0xf8,
349 FuncForceEvent
= 0xfc,
352 enum rtl8110_registers
{
358 enum rtl8168_8101_registers
{
361 #define CSIAR_FLAG 0x80000000
362 #define CSIAR_WRITE_CMD 0x80000000
363 #define CSIAR_BYTE_ENABLE 0x0f
364 #define CSIAR_BYTE_ENABLE_SHIFT 12
365 #define CSIAR_ADDR_MASK 0x0fff
368 #define EPHYAR_FLAG 0x80000000
369 #define EPHYAR_WRITE_CMD 0x80000000
370 #define EPHYAR_REG_MASK 0x1f
371 #define EPHYAR_REG_SHIFT 16
372 #define EPHYAR_DATA_MASK 0xffff
374 #define PFM_EN (1 << 6)
376 #define FIX_NAK_1 (1 << 4)
377 #define FIX_NAK_2 (1 << 3)
380 #define NOW_IS_OOB (1 << 7)
381 #define EN_NDP (1 << 3)
382 #define EN_OOB_RESET (1 << 2)
384 #define EFUSEAR_FLAG 0x80000000
385 #define EFUSEAR_WRITE_CMD 0x80000000
386 #define EFUSEAR_READ_CMD 0x00000000
387 #define EFUSEAR_REG_MASK 0x03ff
388 #define EFUSEAR_REG_SHIFT 8
389 #define EFUSEAR_DATA_MASK 0xff
392 enum rtl8168_registers
{
397 #define ERIAR_FLAG 0x80000000
398 #define ERIAR_WRITE_CMD 0x80000000
399 #define ERIAR_READ_CMD 0x00000000
400 #define ERIAR_ADDR_BYTE_ALIGN 4
401 #define ERIAR_TYPE_SHIFT 16
402 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
403 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
404 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
405 #define ERIAR_MASK_SHIFT 12
406 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
407 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
408 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
409 EPHY_RXER_NUM
= 0x7c,
410 OCPDR
= 0xb0, /* OCP GPHY access */
411 #define OCPDR_WRITE_CMD 0x80000000
412 #define OCPDR_READ_CMD 0x00000000
413 #define OCPDR_REG_MASK 0x7f
414 #define OCPDR_GPHY_REG_SHIFT 16
415 #define OCPDR_DATA_MASK 0xffff
417 #define OCPAR_FLAG 0x80000000
418 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
419 #define OCPAR_GPHY_READ_CMD 0x0000f060
420 RDSAR1
= 0xd0, /* 8168c only. Undocumented on 8168dp */
421 MISC
= 0xf0, /* 8168e only. */
422 #define TXPLA_RST (1 << 29)
423 #define PWM_EN (1 << 22)
426 enum rtl_register_content
{
427 /* InterruptStatusBits */
431 TxDescUnavail
= 0x0080,
455 /* TXPoll register p.5 */
456 HPQ
= 0x80, /* Poll cmd on the high prio queue */
457 NPQ
= 0x40, /* Poll cmd on the low prio queue */
458 FSWInt
= 0x01, /* Forced software interrupt */
462 Cfg9346_Unlock
= 0xc0,
467 AcceptBroadcast
= 0x08,
468 AcceptMulticast
= 0x04,
470 AcceptAllPhys
= 0x01,
471 #define RX_CONFIG_ACCEPT_MASK 0x3f
474 TxInterFrameGapShift
= 24,
475 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
477 /* Config1 register p.24 */
480 MSIEnable
= (1 << 5), /* Enable Message Signaled Interrupt */
481 Speed_down
= (1 << 4),
485 PMEnable
= (1 << 0), /* Power Management Enable */
487 /* Config2 register p. 25 */
488 PCI_Clock_66MHz
= 0x01,
489 PCI_Clock_33MHz
= 0x00,
491 /* Config3 register p.25 */
492 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
493 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
494 Jumbo_En0
= (1 << 2), /* 8168 only. Reserved in the 8168b */
495 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
497 /* Config4 register */
498 Jumbo_En1
= (1 << 1), /* 8168 only. Reserved in the 8168b */
500 /* Config5 register p.27 */
501 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
502 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
503 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
505 LanWake
= (1 << 1), /* LanWake enable/disable */
506 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
509 TBIReset
= 0x80000000,
510 TBILoopback
= 0x40000000,
511 TBINwEnable
= 0x20000000,
512 TBINwRestart
= 0x10000000,
513 TBILinkOk
= 0x02000000,
514 TBINwComplete
= 0x01000000,
517 EnableBist
= (1 << 15), // 8168 8101
518 Mac_dbgo_oe
= (1 << 14), // 8168 8101
519 Normal_mode
= (1 << 13), // unused
520 Force_half_dup
= (1 << 12), // 8168 8101
521 Force_rxflow_en
= (1 << 11), // 8168 8101
522 Force_txflow_en
= (1 << 10), // 8168 8101
523 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
524 ASF
= (1 << 8), // 8168 8101
525 PktCntrDisable
= (1 << 7), // 8168 8101
526 Mac_dbgo_sel
= 0x001c, // 8168
531 INTT_0
= 0x0000, // 8168
532 INTT_1
= 0x0001, // 8168
533 INTT_2
= 0x0002, // 8168
534 INTT_3
= 0x0003, // 8168
536 /* rtl8169_PHYstatus */
547 TBILinkOK
= 0x02000000,
549 /* DumpCounterCommand */
554 /* First doubleword. */
555 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
556 RingEnd
= (1 << 30), /* End of descriptor ring */
557 FirstFrag
= (1 << 29), /* First segment of a packet */
558 LastFrag
= (1 << 28), /* Final segment of a packet */
562 enum rtl_tx_desc_bit
{
563 /* First doubleword. */
564 TD_LSO
= (1 << 27), /* Large Send Offload */
565 #define TD_MSS_MAX 0x07ffu /* MSS value */
567 /* Second doubleword. */
568 TxVlanTag
= (1 << 17), /* Add VLAN tag */
571 /* 8169, 8168b and 810x except 8102e. */
572 enum rtl_tx_desc_bit_0
{
573 /* First doubleword. */
574 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
575 TD0_TCP_CS
= (1 << 16), /* Calculate TCP/IP checksum */
576 TD0_UDP_CS
= (1 << 17), /* Calculate UDP/IP checksum */
577 TD0_IP_CS
= (1 << 18), /* Calculate IP checksum */
580 /* 8102e, 8168c and beyond. */
581 enum rtl_tx_desc_bit_1
{
582 /* Second doubleword. */
583 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
584 TD1_IP_CS
= (1 << 29), /* Calculate IP checksum */
585 TD1_TCP_CS
= (1 << 30), /* Calculate TCP/IP checksum */
586 TD1_UDP_CS
= (1 << 31), /* Calculate UDP/IP checksum */
589 static const struct rtl_tx_desc_info
{
596 } tx_desc_info
[] = {
599 .udp
= TD0_IP_CS
| TD0_UDP_CS
,
600 .tcp
= TD0_IP_CS
| TD0_TCP_CS
602 .mss_shift
= TD0_MSS_SHIFT
,
607 .udp
= TD1_IP_CS
| TD1_UDP_CS
,
608 .tcp
= TD1_IP_CS
| TD1_TCP_CS
610 .mss_shift
= TD1_MSS_SHIFT
,
615 enum rtl_rx_desc_bit
{
617 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
618 PID0
= (1 << 17), /* Protocol ID bit 2/2 */
620 #define RxProtoUDP (PID1)
621 #define RxProtoTCP (PID0)
622 #define RxProtoIP (PID1 | PID0)
623 #define RxProtoMask RxProtoIP
625 IPFail
= (1 << 16), /* IP checksum failed */
626 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
627 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
628 RxVlanTag
= (1 << 16), /* VLAN tag available */
631 #define RsvdMask 0x3fffc000
648 u8 __pad
[sizeof(void *) - sizeof(u32
)];
652 RTL_FEATURE_WOL
= (1 << 0),
653 RTL_FEATURE_MSI
= (1 << 1),
654 RTL_FEATURE_GMII
= (1 << 2),
657 struct rtl8169_counters
{
664 __le32 tx_one_collision
;
665 __le32 tx_multi_collision
;
673 struct rtl8169_private
{
674 void __iomem
*mmio_addr
; /* memory map physical address */
675 struct pci_dev
*pci_dev
;
676 struct net_device
*dev
;
677 struct napi_struct napi
;
682 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
683 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
686 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
687 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
688 dma_addr_t TxPhyAddr
;
689 dma_addr_t RxPhyAddr
;
690 void *Rx_databuff
[NUM_RX_DESC
]; /* Rx data buffers */
691 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
692 struct timer_list timer
;
699 void (*write
)(void __iomem
*, int, int);
700 int (*read
)(void __iomem
*, int);
703 struct pll_power_ops
{
704 void (*down
)(struct rtl8169_private
*);
705 void (*up
)(struct rtl8169_private
*);
709 void (*enable
)(struct rtl8169_private
*);
710 void (*disable
)(struct rtl8169_private
*);
713 int (*set_speed
)(struct net_device
*, u8 aneg
, u16 sp
, u8 dpx
, u32 adv
);
714 int (*get_settings
)(struct net_device
*, struct ethtool_cmd
*);
715 void (*phy_reset_enable
)(struct rtl8169_private
*tp
);
716 void (*hw_start
)(struct net_device
*);
717 unsigned int (*phy_reset_pending
)(struct rtl8169_private
*tp
);
718 unsigned int (*link_ok
)(void __iomem
*);
719 int (*do_ioctl
)(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
);
720 struct delayed_work task
;
723 struct mii_if_info mii
;
724 struct rtl8169_counters counters
;
729 const struct firmware
*fw
;
731 #define RTL_VER_SIZE 32
733 char version
[RTL_VER_SIZE
];
735 struct rtl_fw_phy_action
{
740 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
743 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
744 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
745 module_param(use_dac
, int, 0);
746 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
747 module_param_named(debug
, debug
.msg_enable
, int, 0);
748 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
749 MODULE_LICENSE("GPL");
750 MODULE_VERSION(RTL8169_VERSION
);
751 MODULE_FIRMWARE(FIRMWARE_8168D_1
);
752 MODULE_FIRMWARE(FIRMWARE_8168D_2
);
753 MODULE_FIRMWARE(FIRMWARE_8168E_1
);
754 MODULE_FIRMWARE(FIRMWARE_8168E_2
);
755 MODULE_FIRMWARE(FIRMWARE_8168E_3
);
756 MODULE_FIRMWARE(FIRMWARE_8105E_1
);
757 MODULE_FIRMWARE(FIRMWARE_8168F_1
);
758 MODULE_FIRMWARE(FIRMWARE_8168F_2
);
760 static int rtl8169_open(struct net_device
*dev
);
761 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
762 struct net_device
*dev
);
763 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
);
764 static int rtl8169_init_ring(struct net_device
*dev
);
765 static void rtl_hw_start(struct net_device
*dev
);
766 static int rtl8169_close(struct net_device
*dev
);
767 static void rtl_set_rx_mode(struct net_device
*dev
);
768 static void rtl8169_tx_timeout(struct net_device
*dev
);
769 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
);
770 static int rtl8169_rx_interrupt(struct net_device
*, struct rtl8169_private
*,
771 void __iomem
*, u32 budget
);
772 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
);
773 static void rtl8169_down(struct net_device
*dev
);
774 static void rtl8169_rx_clear(struct rtl8169_private
*tp
);
775 static int rtl8169_poll(struct napi_struct
*napi
, int budget
);
777 static void rtl_tx_performance_tweak(struct pci_dev
*pdev
, u16 force
)
779 int cap
= pci_pcie_cap(pdev
);
784 pci_read_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
785 ctl
= (ctl
& ~PCI_EXP_DEVCTL_READRQ
) | force
;
786 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
790 static u32
ocp_read(struct rtl8169_private
*tp
, u8 mask
, u16 reg
)
792 void __iomem
*ioaddr
= tp
->mmio_addr
;
795 RTL_W32(OCPAR
, ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
796 for (i
= 0; i
< 20; i
++) {
798 if (RTL_R32(OCPAR
) & OCPAR_FLAG
)
801 return RTL_R32(OCPDR
);
804 static void ocp_write(struct rtl8169_private
*tp
, u8 mask
, u16 reg
, u32 data
)
806 void __iomem
*ioaddr
= tp
->mmio_addr
;
809 RTL_W32(OCPDR
, data
);
810 RTL_W32(OCPAR
, OCPAR_FLAG
| ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
811 for (i
= 0; i
< 20; i
++) {
813 if ((RTL_R32(OCPAR
) & OCPAR_FLAG
) == 0)
818 static void rtl8168_oob_notify(struct rtl8169_private
*tp
, u8 cmd
)
820 void __iomem
*ioaddr
= tp
->mmio_addr
;
824 RTL_W32(ERIAR
, 0x800010e8);
826 for (i
= 0; i
< 5; i
++) {
828 if (!(RTL_R32(ERIAR
) & ERIAR_FLAG
))
832 ocp_write(tp
, 0x1, 0x30, 0x00000001);
835 #define OOB_CMD_RESET 0x00
836 #define OOB_CMD_DRIVER_START 0x05
837 #define OOB_CMD_DRIVER_STOP 0x06
839 static u16
rtl8168_get_ocp_reg(struct rtl8169_private
*tp
)
841 return (tp
->mac_version
== RTL_GIGA_MAC_VER_31
) ? 0xb8 : 0x10;
844 static void rtl8168_driver_start(struct rtl8169_private
*tp
)
849 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_START
);
851 reg
= rtl8168_get_ocp_reg(tp
);
853 for (i
= 0; i
< 10; i
++) {
855 if (ocp_read(tp
, 0x0f, reg
) & 0x00000800)
860 static void rtl8168_driver_stop(struct rtl8169_private
*tp
)
865 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_STOP
);
867 reg
= rtl8168_get_ocp_reg(tp
);
869 for (i
= 0; i
< 10; i
++) {
871 if ((ocp_read(tp
, 0x0f, reg
) & 0x00000800) == 0)
876 static int r8168dp_check_dash(struct rtl8169_private
*tp
)
878 u16 reg
= rtl8168_get_ocp_reg(tp
);
880 return (ocp_read(tp
, 0x0f, reg
) & 0x00008000) ? 1 : 0;
883 static void r8169_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
887 RTL_W32(PHYAR
, 0x80000000 | (reg_addr
& 0x1f) << 16 | (value
& 0xffff));
889 for (i
= 20; i
> 0; i
--) {
891 * Check if the RTL8169 has completed writing to the specified
894 if (!(RTL_R32(PHYAR
) & 0x80000000))
899 * According to hardware specs a 20us delay is required after write
900 * complete indication, but before sending next command.
905 static int r8169_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
909 RTL_W32(PHYAR
, 0x0 | (reg_addr
& 0x1f) << 16);
911 for (i
= 20; i
> 0; i
--) {
913 * Check if the RTL8169 has completed retrieving data from
914 * the specified MII register.
916 if (RTL_R32(PHYAR
) & 0x80000000) {
917 value
= RTL_R32(PHYAR
) & 0xffff;
923 * According to hardware specs a 20us delay is required after read
924 * complete indication, but before sending next command.
931 static void r8168dp_1_mdio_access(void __iomem
*ioaddr
, int reg_addr
, u32 data
)
935 RTL_W32(OCPDR
, data
|
936 ((reg_addr
& OCPDR_REG_MASK
) << OCPDR_GPHY_REG_SHIFT
));
937 RTL_W32(OCPAR
, OCPAR_GPHY_WRITE_CMD
);
938 RTL_W32(EPHY_RXER_NUM
, 0);
940 for (i
= 0; i
< 100; i
++) {
942 if (!(RTL_R32(OCPAR
) & OCPAR_FLAG
))
947 static void r8168dp_1_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
949 r8168dp_1_mdio_access(ioaddr
, reg_addr
, OCPDR_WRITE_CMD
|
950 (value
& OCPDR_DATA_MASK
));
953 static int r8168dp_1_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
957 r8168dp_1_mdio_access(ioaddr
, reg_addr
, OCPDR_READ_CMD
);
960 RTL_W32(OCPAR
, OCPAR_GPHY_READ_CMD
);
961 RTL_W32(EPHY_RXER_NUM
, 0);
963 for (i
= 0; i
< 100; i
++) {
965 if (RTL_R32(OCPAR
) & OCPAR_FLAG
)
969 return RTL_R32(OCPDR
) & OCPDR_DATA_MASK
;
972 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
974 static void r8168dp_2_mdio_start(void __iomem
*ioaddr
)
976 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT
);
979 static void r8168dp_2_mdio_stop(void __iomem
*ioaddr
)
981 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT
);
984 static void r8168dp_2_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
986 r8168dp_2_mdio_start(ioaddr
);
988 r8169_mdio_write(ioaddr
, reg_addr
, value
);
990 r8168dp_2_mdio_stop(ioaddr
);
993 static int r8168dp_2_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
997 r8168dp_2_mdio_start(ioaddr
);
999 value
= r8169_mdio_read(ioaddr
, reg_addr
);
1001 r8168dp_2_mdio_stop(ioaddr
);
1006 static void rtl_writephy(struct rtl8169_private
*tp
, int location
, u32 val
)
1008 tp
->mdio_ops
.write(tp
->mmio_addr
, location
, val
);
1011 static int rtl_readphy(struct rtl8169_private
*tp
, int location
)
1013 return tp
->mdio_ops
.read(tp
->mmio_addr
, location
);
1016 static void rtl_patchphy(struct rtl8169_private
*tp
, int reg_addr
, int value
)
1018 rtl_writephy(tp
, reg_addr
, rtl_readphy(tp
, reg_addr
) | value
);
1021 static void rtl_w1w0_phy(struct rtl8169_private
*tp
, int reg_addr
, int p
, int m
)
1025 val
= rtl_readphy(tp
, reg_addr
);
1026 rtl_writephy(tp
, reg_addr
, (val
| p
) & ~m
);
1029 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
1032 struct rtl8169_private
*tp
= netdev_priv(dev
);
1034 rtl_writephy(tp
, location
, val
);
1037 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
1039 struct rtl8169_private
*tp
= netdev_priv(dev
);
1041 return rtl_readphy(tp
, location
);
1044 static void rtl_ephy_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
1048 RTL_W32(EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
1049 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
1051 for (i
= 0; i
< 100; i
++) {
1052 if (!(RTL_R32(EPHYAR
) & EPHYAR_FLAG
))
1058 static u16
rtl_ephy_read(void __iomem
*ioaddr
, int reg_addr
)
1063 RTL_W32(EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
1065 for (i
= 0; i
< 100; i
++) {
1066 if (RTL_R32(EPHYAR
) & EPHYAR_FLAG
) {
1067 value
= RTL_R32(EPHYAR
) & EPHYAR_DATA_MASK
;
1076 static void rtl_csi_write(void __iomem
*ioaddr
, int addr
, int value
)
1080 RTL_W32(CSIDR
, value
);
1081 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
1082 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
1084 for (i
= 0; i
< 100; i
++) {
1085 if (!(RTL_R32(CSIAR
) & CSIAR_FLAG
))
1091 static u32
rtl_csi_read(void __iomem
*ioaddr
, int addr
)
1096 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) |
1097 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
1099 for (i
= 0; i
< 100; i
++) {
1100 if (RTL_R32(CSIAR
) & CSIAR_FLAG
) {
1101 value
= RTL_R32(CSIDR
);
1111 void rtl_eri_write(void __iomem
*ioaddr
, int addr
, u32 mask
, u32 val
, int type
)
1115 BUG_ON((addr
& 3) || (mask
== 0));
1116 RTL_W32(ERIDR
, val
);
1117 RTL_W32(ERIAR
, ERIAR_WRITE_CMD
| type
| mask
| addr
);
1119 for (i
= 0; i
< 100; i
++) {
1120 if (!(RTL_R32(ERIAR
) & ERIAR_FLAG
))
1126 static u32
rtl_eri_read(void __iomem
*ioaddr
, int addr
, int type
)
1131 RTL_W32(ERIAR
, ERIAR_READ_CMD
| type
| ERIAR_MASK_1111
| addr
);
1133 for (i
= 0; i
< 100; i
++) {
1134 if (RTL_R32(ERIAR
) & ERIAR_FLAG
) {
1135 value
= RTL_R32(ERIDR
);
1145 rtl_w1w0_eri(void __iomem
*ioaddr
, int addr
, u32 mask
, u32 p
, u32 m
, int type
)
1149 val
= rtl_eri_read(ioaddr
, addr
, type
);
1150 rtl_eri_write(ioaddr
, addr
, mask
, (val
& ~m
) | p
, type
);
1159 static void rtl_write_exgmac_batch(void __iomem
*ioaddr
,
1160 const struct exgmac_reg
*r
, int len
)
1163 rtl_eri_write(ioaddr
, r
->addr
, r
->mask
, r
->val
, ERIAR_EXGMAC
);
1168 static u8
rtl8168d_efuse_read(void __iomem
*ioaddr
, int reg_addr
)
1173 RTL_W32(EFUSEAR
, (reg_addr
& EFUSEAR_REG_MASK
) << EFUSEAR_REG_SHIFT
);
1175 for (i
= 0; i
< 300; i
++) {
1176 if (RTL_R32(EFUSEAR
) & EFUSEAR_FLAG
) {
1177 value
= RTL_R32(EFUSEAR
) & EFUSEAR_DATA_MASK
;
1186 static void rtl8169_irq_mask_and_ack(struct rtl8169_private
*tp
)
1188 void __iomem
*ioaddr
= tp
->mmio_addr
;
1190 RTL_W16(IntrMask
, 0x0000);
1191 RTL_W16(IntrStatus
, tp
->intr_event
);
1195 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private
*tp
)
1197 void __iomem
*ioaddr
= tp
->mmio_addr
;
1199 return RTL_R32(TBICSR
) & TBIReset
;
1202 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private
*tp
)
1204 return rtl_readphy(tp
, MII_BMCR
) & BMCR_RESET
;
1207 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
1209 return RTL_R32(TBICSR
) & TBILinkOk
;
1212 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
1214 return RTL_R8(PHYstatus
) & LinkStatus
;
1217 static void rtl8169_tbi_reset_enable(struct rtl8169_private
*tp
)
1219 void __iomem
*ioaddr
= tp
->mmio_addr
;
1221 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
1224 static void rtl8169_xmii_reset_enable(struct rtl8169_private
*tp
)
1228 val
= rtl_readphy(tp
, MII_BMCR
) | BMCR_RESET
;
1229 rtl_writephy(tp
, MII_BMCR
, val
& 0xffff);
1232 static void rtl_link_chg_patch(struct rtl8169_private
*tp
)
1234 void __iomem
*ioaddr
= tp
->mmio_addr
;
1235 struct net_device
*dev
= tp
->dev
;
1237 if (!netif_running(dev
))
1240 if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
) {
1241 if (RTL_R8(PHYstatus
) & _1000bpsF
) {
1242 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1243 0x00000011, ERIAR_EXGMAC
);
1244 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1245 0x00000005, ERIAR_EXGMAC
);
1246 } else if (RTL_R8(PHYstatus
) & _100bps
) {
1247 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1248 0x0000001f, ERIAR_EXGMAC
);
1249 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1250 0x00000005, ERIAR_EXGMAC
);
1252 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1253 0x0000001f, ERIAR_EXGMAC
);
1254 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1255 0x0000003f, ERIAR_EXGMAC
);
1257 /* Reset packet filter */
1258 rtl_w1w0_eri(ioaddr
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01,
1260 rtl_w1w0_eri(ioaddr
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00,
1262 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_35
||
1263 tp
->mac_version
== RTL_GIGA_MAC_VER_36
) {
1264 if (RTL_R8(PHYstatus
) & _1000bpsF
) {
1265 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1266 0x00000011, ERIAR_EXGMAC
);
1267 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1268 0x00000005, ERIAR_EXGMAC
);
1270 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1271 0x0000001f, ERIAR_EXGMAC
);
1272 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1273 0x0000003f, ERIAR_EXGMAC
);
1278 static void __rtl8169_check_link_status(struct net_device
*dev
,
1279 struct rtl8169_private
*tp
,
1280 void __iomem
*ioaddr
, bool pm
)
1282 unsigned long flags
;
1284 spin_lock_irqsave(&tp
->lock
, flags
);
1285 if (tp
->link_ok(ioaddr
)) {
1286 rtl_link_chg_patch(tp
);
1287 /* This is to cancel a scheduled suspend if there's one. */
1289 pm_request_resume(&tp
->pci_dev
->dev
);
1290 netif_carrier_on(dev
);
1291 if (net_ratelimit())
1292 netif_info(tp
, ifup
, dev
, "link up\n");
1294 netif_carrier_off(dev
);
1295 netif_info(tp
, ifdown
, dev
, "link down\n");
1297 pm_schedule_suspend(&tp
->pci_dev
->dev
, 5000);
1299 spin_unlock_irqrestore(&tp
->lock
, flags
);
1302 static void rtl8169_check_link_status(struct net_device
*dev
,
1303 struct rtl8169_private
*tp
,
1304 void __iomem
*ioaddr
)
1306 __rtl8169_check_link_status(dev
, tp
, ioaddr
, false);
1309 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1311 static u32
__rtl8169_get_wol(struct rtl8169_private
*tp
)
1313 void __iomem
*ioaddr
= tp
->mmio_addr
;
1317 options
= RTL_R8(Config1
);
1318 if (!(options
& PMEnable
))
1321 options
= RTL_R8(Config3
);
1322 if (options
& LinkUp
)
1323 wolopts
|= WAKE_PHY
;
1324 if (options
& MagicPacket
)
1325 wolopts
|= WAKE_MAGIC
;
1327 options
= RTL_R8(Config5
);
1329 wolopts
|= WAKE_UCAST
;
1331 wolopts
|= WAKE_BCAST
;
1333 wolopts
|= WAKE_MCAST
;
1338 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1340 struct rtl8169_private
*tp
= netdev_priv(dev
);
1342 spin_lock_irq(&tp
->lock
);
1344 wol
->supported
= WAKE_ANY
;
1345 wol
->wolopts
= __rtl8169_get_wol(tp
);
1347 spin_unlock_irq(&tp
->lock
);
1350 static void __rtl8169_set_wol(struct rtl8169_private
*tp
, u32 wolopts
)
1352 void __iomem
*ioaddr
= tp
->mmio_addr
;
1354 static const struct {
1359 { WAKE_ANY
, Config1
, PMEnable
},
1360 { WAKE_PHY
, Config3
, LinkUp
},
1361 { WAKE_MAGIC
, Config3
, MagicPacket
},
1362 { WAKE_UCAST
, Config5
, UWF
},
1363 { WAKE_BCAST
, Config5
, BWF
},
1364 { WAKE_MCAST
, Config5
, MWF
},
1365 { WAKE_ANY
, Config5
, LanWake
}
1368 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1370 for (i
= 0; i
< ARRAY_SIZE(cfg
); i
++) {
1371 u8 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
1372 if (wolopts
& cfg
[i
].opt
)
1373 options
|= cfg
[i
].mask
;
1374 RTL_W8(cfg
[i
].reg
, options
);
1377 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1380 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1382 struct rtl8169_private
*tp
= netdev_priv(dev
);
1384 spin_lock_irq(&tp
->lock
);
1387 tp
->features
|= RTL_FEATURE_WOL
;
1389 tp
->features
&= ~RTL_FEATURE_WOL
;
1390 __rtl8169_set_wol(tp
, wol
->wolopts
);
1391 spin_unlock_irq(&tp
->lock
);
1393 device_set_wakeup_enable(&tp
->pci_dev
->dev
, wol
->wolopts
);
1398 static const char *rtl_lookup_firmware_name(struct rtl8169_private
*tp
)
1400 return rtl_chip_infos
[tp
->mac_version
].fw_name
;
1403 static void rtl8169_get_drvinfo(struct net_device
*dev
,
1404 struct ethtool_drvinfo
*info
)
1406 struct rtl8169_private
*tp
= netdev_priv(dev
);
1407 struct rtl_fw
*rtl_fw
= tp
->rtl_fw
;
1409 strcpy(info
->driver
, MODULENAME
);
1410 strcpy(info
->version
, RTL8169_VERSION
);
1411 strcpy(info
->bus_info
, pci_name(tp
->pci_dev
));
1412 BUILD_BUG_ON(sizeof(info
->fw_version
) < sizeof(rtl_fw
->version
));
1413 strcpy(info
->fw_version
, IS_ERR_OR_NULL(rtl_fw
) ? "N/A" :
1417 static int rtl8169_get_regs_len(struct net_device
*dev
)
1419 return R8169_REGS_SIZE
;
1422 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
1423 u8 autoneg
, u16 speed
, u8 duplex
, u32 ignored
)
1425 struct rtl8169_private
*tp
= netdev_priv(dev
);
1426 void __iomem
*ioaddr
= tp
->mmio_addr
;
1430 reg
= RTL_R32(TBICSR
);
1431 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
1432 (duplex
== DUPLEX_FULL
)) {
1433 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
1434 } else if (autoneg
== AUTONEG_ENABLE
)
1435 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
1437 netif_warn(tp
, link
, dev
,
1438 "incorrect speed setting refused in TBI mode\n");
1445 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
1446 u8 autoneg
, u16 speed
, u8 duplex
, u32 adv
)
1448 struct rtl8169_private
*tp
= netdev_priv(dev
);
1449 int giga_ctrl
, bmcr
;
1452 rtl_writephy(tp
, 0x1f, 0x0000);
1454 if (autoneg
== AUTONEG_ENABLE
) {
1457 auto_nego
= rtl_readphy(tp
, MII_ADVERTISE
);
1458 auto_nego
&= ~(ADVERTISE_10HALF
| ADVERTISE_10FULL
|
1459 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
1461 if (adv
& ADVERTISED_10baseT_Half
)
1462 auto_nego
|= ADVERTISE_10HALF
;
1463 if (adv
& ADVERTISED_10baseT_Full
)
1464 auto_nego
|= ADVERTISE_10FULL
;
1465 if (adv
& ADVERTISED_100baseT_Half
)
1466 auto_nego
|= ADVERTISE_100HALF
;
1467 if (adv
& ADVERTISED_100baseT_Full
)
1468 auto_nego
|= ADVERTISE_100FULL
;
1470 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
1472 giga_ctrl
= rtl_readphy(tp
, MII_CTRL1000
);
1473 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
1475 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1476 if (tp
->mii
.supports_gmii
) {
1477 if (adv
& ADVERTISED_1000baseT_Half
)
1478 giga_ctrl
|= ADVERTISE_1000HALF
;
1479 if (adv
& ADVERTISED_1000baseT_Full
)
1480 giga_ctrl
|= ADVERTISE_1000FULL
;
1481 } else if (adv
& (ADVERTISED_1000baseT_Half
|
1482 ADVERTISED_1000baseT_Full
)) {
1483 netif_info(tp
, link
, dev
,
1484 "PHY does not support 1000Mbps\n");
1488 bmcr
= BMCR_ANENABLE
| BMCR_ANRESTART
;
1490 rtl_writephy(tp
, MII_ADVERTISE
, auto_nego
);
1491 rtl_writephy(tp
, MII_CTRL1000
, giga_ctrl
);
1495 if (speed
== SPEED_10
)
1497 else if (speed
== SPEED_100
)
1498 bmcr
= BMCR_SPEED100
;
1502 if (duplex
== DUPLEX_FULL
)
1503 bmcr
|= BMCR_FULLDPLX
;
1506 rtl_writephy(tp
, MII_BMCR
, bmcr
);
1508 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
1509 tp
->mac_version
== RTL_GIGA_MAC_VER_03
) {
1510 if ((speed
== SPEED_100
) && (autoneg
!= AUTONEG_ENABLE
)) {
1511 rtl_writephy(tp
, 0x17, 0x2138);
1512 rtl_writephy(tp
, 0x0e, 0x0260);
1514 rtl_writephy(tp
, 0x17, 0x2108);
1515 rtl_writephy(tp
, 0x0e, 0x0000);
1524 static int rtl8169_set_speed(struct net_device
*dev
,
1525 u8 autoneg
, u16 speed
, u8 duplex
, u32 advertising
)
1527 struct rtl8169_private
*tp
= netdev_priv(dev
);
1530 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
, advertising
);
1534 if (netif_running(dev
) && (autoneg
== AUTONEG_ENABLE
) &&
1535 (advertising
& ADVERTISED_1000baseT_Full
)) {
1536 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
1542 static int rtl8169_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1544 struct rtl8169_private
*tp
= netdev_priv(dev
);
1545 unsigned long flags
;
1548 del_timer_sync(&tp
->timer
);
1550 spin_lock_irqsave(&tp
->lock
, flags
);
1551 ret
= rtl8169_set_speed(dev
, cmd
->autoneg
, ethtool_cmd_speed(cmd
),
1552 cmd
->duplex
, cmd
->advertising
);
1553 spin_unlock_irqrestore(&tp
->lock
, flags
);
1558 static u32
rtl8169_fix_features(struct net_device
*dev
, u32 features
)
1560 struct rtl8169_private
*tp
= netdev_priv(dev
);
1562 if (dev
->mtu
> TD_MSS_MAX
)
1563 features
&= ~NETIF_F_ALL_TSO
;
1565 if (dev
->mtu
> JUMBO_1K
&&
1566 !rtl_chip_infos
[tp
->mac_version
].jumbo_tx_csum
)
1567 features
&= ~NETIF_F_IP_CSUM
;
1572 static int rtl8169_set_features(struct net_device
*dev
, u32 features
)
1574 struct rtl8169_private
*tp
= netdev_priv(dev
);
1575 void __iomem
*ioaddr
= tp
->mmio_addr
;
1576 unsigned long flags
;
1578 spin_lock_irqsave(&tp
->lock
, flags
);
1580 if (features
& NETIF_F_RXCSUM
)
1581 tp
->cp_cmd
|= RxChkSum
;
1583 tp
->cp_cmd
&= ~RxChkSum
;
1585 if (dev
->features
& NETIF_F_HW_VLAN_RX
)
1586 tp
->cp_cmd
|= RxVlan
;
1588 tp
->cp_cmd
&= ~RxVlan
;
1590 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
1593 spin_unlock_irqrestore(&tp
->lock
, flags
);
1598 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
1599 struct sk_buff
*skb
)
1601 return (vlan_tx_tag_present(skb
)) ?
1602 TxVlanTag
| swab16(vlan_tx_tag_get(skb
)) : 0x00;
1605 static void rtl8169_rx_vlan_tag(struct RxDesc
*desc
, struct sk_buff
*skb
)
1607 u32 opts2
= le32_to_cpu(desc
->opts2
);
1609 if (opts2
& RxVlanTag
)
1610 __vlan_hwaccel_put_tag(skb
, swab16(opts2
& 0xffff));
1615 static int rtl8169_gset_tbi(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1617 struct rtl8169_private
*tp
= netdev_priv(dev
);
1618 void __iomem
*ioaddr
= tp
->mmio_addr
;
1622 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
1623 cmd
->port
= PORT_FIBRE
;
1624 cmd
->transceiver
= XCVR_INTERNAL
;
1626 status
= RTL_R32(TBICSR
);
1627 cmd
->advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
1628 cmd
->autoneg
= !!(status
& TBINwEnable
);
1630 ethtool_cmd_speed_set(cmd
, SPEED_1000
);
1631 cmd
->duplex
= DUPLEX_FULL
; /* Always set */
1636 static int rtl8169_gset_xmii(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1638 struct rtl8169_private
*tp
= netdev_priv(dev
);
1640 return mii_ethtool_gset(&tp
->mii
, cmd
);
1643 static int rtl8169_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1645 struct rtl8169_private
*tp
= netdev_priv(dev
);
1646 unsigned long flags
;
1649 spin_lock_irqsave(&tp
->lock
, flags
);
1651 rc
= tp
->get_settings(dev
, cmd
);
1653 spin_unlock_irqrestore(&tp
->lock
, flags
);
1657 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1660 struct rtl8169_private
*tp
= netdev_priv(dev
);
1661 unsigned long flags
;
1663 if (regs
->len
> R8169_REGS_SIZE
)
1664 regs
->len
= R8169_REGS_SIZE
;
1666 spin_lock_irqsave(&tp
->lock
, flags
);
1667 memcpy_fromio(p
, tp
->mmio_addr
, regs
->len
);
1668 spin_unlock_irqrestore(&tp
->lock
, flags
);
1671 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
1673 struct rtl8169_private
*tp
= netdev_priv(dev
);
1675 return tp
->msg_enable
;
1678 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
1680 struct rtl8169_private
*tp
= netdev_priv(dev
);
1682 tp
->msg_enable
= value
;
1685 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
1692 "tx_single_collisions",
1693 "tx_multi_collisions",
1701 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
1705 return ARRAY_SIZE(rtl8169_gstrings
);
1711 static void rtl8169_update_counters(struct net_device
*dev
)
1713 struct rtl8169_private
*tp
= netdev_priv(dev
);
1714 void __iomem
*ioaddr
= tp
->mmio_addr
;
1715 struct device
*d
= &tp
->pci_dev
->dev
;
1716 struct rtl8169_counters
*counters
;
1722 * Some chips are unable to dump tally counters when the receiver
1725 if ((RTL_R8(ChipCmd
) & CmdRxEnb
) == 0)
1728 counters
= dma_alloc_coherent(d
, sizeof(*counters
), &paddr
, GFP_KERNEL
);
1732 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
1733 cmd
= (u64
)paddr
& DMA_BIT_MASK(32);
1734 RTL_W32(CounterAddrLow
, cmd
);
1735 RTL_W32(CounterAddrLow
, cmd
| CounterDump
);
1738 if ((RTL_R32(CounterAddrLow
) & CounterDump
) == 0) {
1739 memcpy(&tp
->counters
, counters
, sizeof(*counters
));
1745 RTL_W32(CounterAddrLow
, 0);
1746 RTL_W32(CounterAddrHigh
, 0);
1748 dma_free_coherent(d
, sizeof(*counters
), counters
, paddr
);
1751 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
1752 struct ethtool_stats
*stats
, u64
*data
)
1754 struct rtl8169_private
*tp
= netdev_priv(dev
);
1758 rtl8169_update_counters(dev
);
1760 data
[0] = le64_to_cpu(tp
->counters
.tx_packets
);
1761 data
[1] = le64_to_cpu(tp
->counters
.rx_packets
);
1762 data
[2] = le64_to_cpu(tp
->counters
.tx_errors
);
1763 data
[3] = le32_to_cpu(tp
->counters
.rx_errors
);
1764 data
[4] = le16_to_cpu(tp
->counters
.rx_missed
);
1765 data
[5] = le16_to_cpu(tp
->counters
.align_errors
);
1766 data
[6] = le32_to_cpu(tp
->counters
.tx_one_collision
);
1767 data
[7] = le32_to_cpu(tp
->counters
.tx_multi_collision
);
1768 data
[8] = le64_to_cpu(tp
->counters
.rx_unicast
);
1769 data
[9] = le64_to_cpu(tp
->counters
.rx_broadcast
);
1770 data
[10] = le32_to_cpu(tp
->counters
.rx_multicast
);
1771 data
[11] = le16_to_cpu(tp
->counters
.tx_aborted
);
1772 data
[12] = le16_to_cpu(tp
->counters
.tx_underun
);
1775 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1779 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
1784 static const struct ethtool_ops rtl8169_ethtool_ops
= {
1785 .get_drvinfo
= rtl8169_get_drvinfo
,
1786 .get_regs_len
= rtl8169_get_regs_len
,
1787 .get_link
= ethtool_op_get_link
,
1788 .get_settings
= rtl8169_get_settings
,
1789 .set_settings
= rtl8169_set_settings
,
1790 .get_msglevel
= rtl8169_get_msglevel
,
1791 .set_msglevel
= rtl8169_set_msglevel
,
1792 .get_regs
= rtl8169_get_regs
,
1793 .get_wol
= rtl8169_get_wol
,
1794 .set_wol
= rtl8169_set_wol
,
1795 .get_strings
= rtl8169_get_strings
,
1796 .get_sset_count
= rtl8169_get_sset_count
,
1797 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
1800 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
,
1801 struct net_device
*dev
, u8 default_version
)
1803 void __iomem
*ioaddr
= tp
->mmio_addr
;
1805 * The driver currently handles the 8168Bf and the 8168Be identically
1806 * but they can be identified more specifically through the test below
1809 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1811 * Same thing for the 8101Eb and the 8101Ec:
1813 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1815 static const struct rtl_mac_info
{
1821 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36
},
1822 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35
},
1825 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34
},
1826 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33
},
1827 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32
},
1828 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33
},
1831 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26
},
1832 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25
},
1833 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26
},
1835 /* 8168DP family. */
1836 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27
},
1837 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28
},
1838 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31
},
1841 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24
},
1842 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23
},
1843 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
1844 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24
},
1845 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
1846 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
1847 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21
},
1848 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22
},
1849 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22
},
1852 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
1853 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
1854 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
1855 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
1858 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30
},
1859 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30
},
1860 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29
},
1861 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30
},
1862 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09
},
1863 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09
},
1864 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08
},
1865 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08
},
1866 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07
},
1867 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07
},
1868 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
1869 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10
},
1870 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
1871 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09
},
1872 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09
},
1873 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
1874 /* FIXME: where did these entries come from ? -- FR */
1875 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
1876 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
1879 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
1880 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
1881 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
1882 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
1883 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
1884 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
1887 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE
}
1889 const struct rtl_mac_info
*p
= mac_info
;
1892 reg
= RTL_R32(TxConfig
);
1893 while ((reg
& p
->mask
) != p
->val
)
1895 tp
->mac_version
= p
->mac_version
;
1897 if (tp
->mac_version
== RTL_GIGA_MAC_NONE
) {
1898 netif_notice(tp
, probe
, dev
,
1899 "unknown MAC, using family default\n");
1900 tp
->mac_version
= default_version
;
1904 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
1906 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
1914 static void rtl_writephy_batch(struct rtl8169_private
*tp
,
1915 const struct phy_reg
*regs
, int len
)
1918 rtl_writephy(tp
, regs
->reg
, regs
->val
);
1923 #define PHY_READ 0x00000000
1924 #define PHY_DATA_OR 0x10000000
1925 #define PHY_DATA_AND 0x20000000
1926 #define PHY_BJMPN 0x30000000
1927 #define PHY_READ_EFUSE 0x40000000
1928 #define PHY_READ_MAC_BYTE 0x50000000
1929 #define PHY_WRITE_MAC_BYTE 0x60000000
1930 #define PHY_CLEAR_READCOUNT 0x70000000
1931 #define PHY_WRITE 0x80000000
1932 #define PHY_READCOUNT_EQ_SKIP 0x90000000
1933 #define PHY_COMP_EQ_SKIPN 0xa0000000
1934 #define PHY_COMP_NEQ_SKIPN 0xb0000000
1935 #define PHY_WRITE_PREVIOUS 0xc0000000
1936 #define PHY_SKIPN 0xd0000000
1937 #define PHY_DELAY_MS 0xe0000000
1938 #define PHY_WRITE_ERI_WORD 0xf0000000
1942 char version
[RTL_VER_SIZE
];
1948 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1950 static bool rtl_fw_format_ok(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
1952 const struct firmware
*fw
= rtl_fw
->fw
;
1953 struct fw_info
*fw_info
= (struct fw_info
*)fw
->data
;
1954 struct rtl_fw_phy_action
*pa
= &rtl_fw
->phy_action
;
1955 char *version
= rtl_fw
->version
;
1958 if (fw
->size
< FW_OPCODE_SIZE
)
1961 if (!fw_info
->magic
) {
1962 size_t i
, size
, start
;
1965 if (fw
->size
< sizeof(*fw_info
))
1968 for (i
= 0; i
< fw
->size
; i
++)
1969 checksum
+= fw
->data
[i
];
1973 start
= le32_to_cpu(fw_info
->fw_start
);
1974 if (start
> fw
->size
)
1977 size
= le32_to_cpu(fw_info
->fw_len
);
1978 if (size
> (fw
->size
- start
) / FW_OPCODE_SIZE
)
1981 memcpy(version
, fw_info
->version
, RTL_VER_SIZE
);
1983 pa
->code
= (__le32
*)(fw
->data
+ start
);
1986 if (fw
->size
% FW_OPCODE_SIZE
)
1989 strlcpy(version
, rtl_lookup_firmware_name(tp
), RTL_VER_SIZE
);
1991 pa
->code
= (__le32
*)fw
->data
;
1992 pa
->size
= fw
->size
/ FW_OPCODE_SIZE
;
1994 version
[RTL_VER_SIZE
- 1] = 0;
2001 static bool rtl_fw_data_ok(struct rtl8169_private
*tp
, struct net_device
*dev
,
2002 struct rtl_fw_phy_action
*pa
)
2007 for (index
= 0; index
< pa
->size
; index
++) {
2008 u32 action
= le32_to_cpu(pa
->code
[index
]);
2009 u32 regno
= (action
& 0x0fff0000) >> 16;
2011 switch(action
& 0xf0000000) {
2015 case PHY_READ_EFUSE
:
2016 case PHY_CLEAR_READCOUNT
:
2018 case PHY_WRITE_PREVIOUS
:
2023 if (regno
> index
) {
2024 netif_err(tp
, ifup
, tp
->dev
,
2025 "Out of range of firmware\n");
2029 case PHY_READCOUNT_EQ_SKIP
:
2030 if (index
+ 2 >= pa
->size
) {
2031 netif_err(tp
, ifup
, tp
->dev
,
2032 "Out of range of firmware\n");
2036 case PHY_COMP_EQ_SKIPN
:
2037 case PHY_COMP_NEQ_SKIPN
:
2039 if (index
+ 1 + regno
>= pa
->size
) {
2040 netif_err(tp
, ifup
, tp
->dev
,
2041 "Out of range of firmware\n");
2046 case PHY_READ_MAC_BYTE
:
2047 case PHY_WRITE_MAC_BYTE
:
2048 case PHY_WRITE_ERI_WORD
:
2050 netif_err(tp
, ifup
, tp
->dev
,
2051 "Invalid action 0x%08x\n", action
);
2060 static int rtl_check_firmware(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
2062 struct net_device
*dev
= tp
->dev
;
2065 if (!rtl_fw_format_ok(tp
, rtl_fw
)) {
2066 netif_err(tp
, ifup
, dev
, "invalid firwmare\n");
2070 if (rtl_fw_data_ok(tp
, dev
, &rtl_fw
->phy_action
))
2076 static void rtl_phy_write_fw(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
2078 struct rtl_fw_phy_action
*pa
= &rtl_fw
->phy_action
;
2082 predata
= count
= 0;
2084 for (index
= 0; index
< pa
->size
; ) {
2085 u32 action
= le32_to_cpu(pa
->code
[index
]);
2086 u32 data
= action
& 0x0000ffff;
2087 u32 regno
= (action
& 0x0fff0000) >> 16;
2092 switch(action
& 0xf0000000) {
2094 predata
= rtl_readphy(tp
, regno
);
2109 case PHY_READ_EFUSE
:
2110 predata
= rtl8168d_efuse_read(tp
->mmio_addr
, regno
);
2113 case PHY_CLEAR_READCOUNT
:
2118 rtl_writephy(tp
, regno
, data
);
2121 case PHY_READCOUNT_EQ_SKIP
:
2122 index
+= (count
== data
) ? 2 : 1;
2124 case PHY_COMP_EQ_SKIPN
:
2125 if (predata
== data
)
2129 case PHY_COMP_NEQ_SKIPN
:
2130 if (predata
!= data
)
2134 case PHY_WRITE_PREVIOUS
:
2135 rtl_writephy(tp
, regno
, predata
);
2146 case PHY_READ_MAC_BYTE
:
2147 case PHY_WRITE_MAC_BYTE
:
2148 case PHY_WRITE_ERI_WORD
:
2155 static void rtl_release_firmware(struct rtl8169_private
*tp
)
2157 if (!IS_ERR_OR_NULL(tp
->rtl_fw
)) {
2158 release_firmware(tp
->rtl_fw
->fw
);
2161 tp
->rtl_fw
= RTL_FIRMWARE_UNKNOWN
;
2164 static void rtl_apply_firmware(struct rtl8169_private
*tp
)
2166 struct rtl_fw
*rtl_fw
= tp
->rtl_fw
;
2168 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2169 if (!IS_ERR_OR_NULL(rtl_fw
))
2170 rtl_phy_write_fw(tp
, rtl_fw
);
2173 static void rtl_apply_firmware_cond(struct rtl8169_private
*tp
, u8 reg
, u16 val
)
2175 if (rtl_readphy(tp
, reg
) != val
)
2176 netif_warn(tp
, hw
, tp
->dev
, "chipset not ready for firmware\n");
2178 rtl_apply_firmware(tp
);
2181 static void rtl8169s_hw_phy_config(struct rtl8169_private
*tp
)
2183 static const struct phy_reg phy_reg_init
[] = {
2245 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2248 static void rtl8169sb_hw_phy_config(struct rtl8169_private
*tp
)
2250 static const struct phy_reg phy_reg_init
[] = {
2256 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2259 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private
*tp
)
2261 struct pci_dev
*pdev
= tp
->pci_dev
;
2263 if ((pdev
->subsystem_vendor
!= PCI_VENDOR_ID_GIGABYTE
) ||
2264 (pdev
->subsystem_device
!= 0xe000))
2267 rtl_writephy(tp
, 0x1f, 0x0001);
2268 rtl_writephy(tp
, 0x10, 0xf01b);
2269 rtl_writephy(tp
, 0x1f, 0x0000);
2272 static void rtl8169scd_hw_phy_config(struct rtl8169_private
*tp
)
2274 static const struct phy_reg phy_reg_init
[] = {
2314 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2316 rtl8169scd_hw_phy_config_quirk(tp
);
2319 static void rtl8169sce_hw_phy_config(struct rtl8169_private
*tp
)
2321 static const struct phy_reg phy_reg_init
[] = {
2369 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2372 static void rtl8168bb_hw_phy_config(struct rtl8169_private
*tp
)
2374 static const struct phy_reg phy_reg_init
[] = {
2379 rtl_writephy(tp
, 0x1f, 0x0001);
2380 rtl_patchphy(tp
, 0x16, 1 << 0);
2382 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2385 static void rtl8168bef_hw_phy_config(struct rtl8169_private
*tp
)
2387 static const struct phy_reg phy_reg_init
[] = {
2393 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2396 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private
*tp
)
2398 static const struct phy_reg phy_reg_init
[] = {
2406 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2409 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private
*tp
)
2411 static const struct phy_reg phy_reg_init
[] = {
2417 rtl_writephy(tp
, 0x1f, 0x0000);
2418 rtl_patchphy(tp
, 0x14, 1 << 5);
2419 rtl_patchphy(tp
, 0x0d, 1 << 5);
2421 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2424 static void rtl8168c_1_hw_phy_config(struct rtl8169_private
*tp
)
2426 static const struct phy_reg phy_reg_init
[] = {
2446 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2448 rtl_patchphy(tp
, 0x14, 1 << 5);
2449 rtl_patchphy(tp
, 0x0d, 1 << 5);
2450 rtl_writephy(tp
, 0x1f, 0x0000);
2453 static void rtl8168c_2_hw_phy_config(struct rtl8169_private
*tp
)
2455 static const struct phy_reg phy_reg_init
[] = {
2473 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2475 rtl_patchphy(tp
, 0x16, 1 << 0);
2476 rtl_patchphy(tp
, 0x14, 1 << 5);
2477 rtl_patchphy(tp
, 0x0d, 1 << 5);
2478 rtl_writephy(tp
, 0x1f, 0x0000);
2481 static void rtl8168c_3_hw_phy_config(struct rtl8169_private
*tp
)
2483 static const struct phy_reg phy_reg_init
[] = {
2495 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2497 rtl_patchphy(tp
, 0x16, 1 << 0);
2498 rtl_patchphy(tp
, 0x14, 1 << 5);
2499 rtl_patchphy(tp
, 0x0d, 1 << 5);
2500 rtl_writephy(tp
, 0x1f, 0x0000);
2503 static void rtl8168c_4_hw_phy_config(struct rtl8169_private
*tp
)
2505 rtl8168c_3_hw_phy_config(tp
);
2508 static void rtl8168d_1_hw_phy_config(struct rtl8169_private
*tp
)
2510 static const struct phy_reg phy_reg_init_0
[] = {
2511 /* Channel Estimation */
2532 * Enhance line driver power
2541 * Can not link to 1Gbps with bad cable
2542 * Decrease SNR threshold form 21.07dB to 19.04dB
2550 void __iomem
*ioaddr
= tp
->mmio_addr
;
2552 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2556 * Fine Tune Switching regulator parameter
2558 rtl_writephy(tp
, 0x1f, 0x0002);
2559 rtl_w1w0_phy(tp
, 0x0b, 0x0010, 0x00ef);
2560 rtl_w1w0_phy(tp
, 0x0c, 0xa200, 0x5d00);
2562 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2563 static const struct phy_reg phy_reg_init
[] = {
2573 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2575 val
= rtl_readphy(tp
, 0x0d);
2577 if ((val
& 0x00ff) != 0x006c) {
2578 static const u32 set
[] = {
2579 0x0065, 0x0066, 0x0067, 0x0068,
2580 0x0069, 0x006a, 0x006b, 0x006c
2584 rtl_writephy(tp
, 0x1f, 0x0002);
2587 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2588 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
2591 static const struct phy_reg phy_reg_init
[] = {
2599 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2602 /* RSET couple improve */
2603 rtl_writephy(tp
, 0x1f, 0x0002);
2604 rtl_patchphy(tp
, 0x0d, 0x0300);
2605 rtl_patchphy(tp
, 0x0f, 0x0010);
2607 /* Fine tune PLL performance */
2608 rtl_writephy(tp
, 0x1f, 0x0002);
2609 rtl_w1w0_phy(tp
, 0x02, 0x0100, 0x0600);
2610 rtl_w1w0_phy(tp
, 0x03, 0x0000, 0xe000);
2612 rtl_writephy(tp
, 0x1f, 0x0005);
2613 rtl_writephy(tp
, 0x05, 0x001b);
2615 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xbf00);
2617 rtl_writephy(tp
, 0x1f, 0x0000);
2620 static void rtl8168d_2_hw_phy_config(struct rtl8169_private
*tp
)
2622 static const struct phy_reg phy_reg_init_0
[] = {
2623 /* Channel Estimation */
2644 * Enhance line driver power
2653 * Can not link to 1Gbps with bad cable
2654 * Decrease SNR threshold form 21.07dB to 19.04dB
2662 void __iomem
*ioaddr
= tp
->mmio_addr
;
2664 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2666 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2667 static const struct phy_reg phy_reg_init
[] = {
2678 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2680 val
= rtl_readphy(tp
, 0x0d);
2681 if ((val
& 0x00ff) != 0x006c) {
2682 static const u32 set
[] = {
2683 0x0065, 0x0066, 0x0067, 0x0068,
2684 0x0069, 0x006a, 0x006b, 0x006c
2688 rtl_writephy(tp
, 0x1f, 0x0002);
2691 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2692 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
2695 static const struct phy_reg phy_reg_init
[] = {
2703 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2706 /* Fine tune PLL performance */
2707 rtl_writephy(tp
, 0x1f, 0x0002);
2708 rtl_w1w0_phy(tp
, 0x02, 0x0100, 0x0600);
2709 rtl_w1w0_phy(tp
, 0x03, 0x0000, 0xe000);
2711 /* Switching regulator Slew rate */
2712 rtl_writephy(tp
, 0x1f, 0x0002);
2713 rtl_patchphy(tp
, 0x0f, 0x0017);
2715 rtl_writephy(tp
, 0x1f, 0x0005);
2716 rtl_writephy(tp
, 0x05, 0x001b);
2718 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xb300);
2720 rtl_writephy(tp
, 0x1f, 0x0000);
2723 static void rtl8168d_3_hw_phy_config(struct rtl8169_private
*tp
)
2725 static const struct phy_reg phy_reg_init
[] = {
2781 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2784 static void rtl8168d_4_hw_phy_config(struct rtl8169_private
*tp
)
2786 static const struct phy_reg phy_reg_init
[] = {
2796 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2797 rtl_patchphy(tp
, 0x0d, 1 << 5);
2800 static void rtl8168e_1_hw_phy_config(struct rtl8169_private
*tp
)
2802 static const struct phy_reg phy_reg_init
[] = {
2803 /* Enable Delay cap */
2809 /* Channel estimation fine tune */
2818 /* Update PFM & 10M TX idle timer */
2830 rtl_apply_firmware(tp
);
2832 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2834 /* DCO enable for 10M IDLE Power */
2835 rtl_writephy(tp
, 0x1f, 0x0007);
2836 rtl_writephy(tp
, 0x1e, 0x0023);
2837 rtl_w1w0_phy(tp
, 0x17, 0x0006, 0x0000);
2838 rtl_writephy(tp
, 0x1f, 0x0000);
2840 /* For impedance matching */
2841 rtl_writephy(tp
, 0x1f, 0x0002);
2842 rtl_w1w0_phy(tp
, 0x08, 0x8000, 0x7f00);
2843 rtl_writephy(tp
, 0x1f, 0x0000);
2845 /* PHY auto speed down */
2846 rtl_writephy(tp
, 0x1f, 0x0007);
2847 rtl_writephy(tp
, 0x1e, 0x002d);
2848 rtl_w1w0_phy(tp
, 0x18, 0x0050, 0x0000);
2849 rtl_writephy(tp
, 0x1f, 0x0000);
2850 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
2852 rtl_writephy(tp
, 0x1f, 0x0005);
2853 rtl_writephy(tp
, 0x05, 0x8b86);
2854 rtl_w1w0_phy(tp
, 0x06, 0x0001, 0x0000);
2855 rtl_writephy(tp
, 0x1f, 0x0000);
2857 rtl_writephy(tp
, 0x1f, 0x0005);
2858 rtl_writephy(tp
, 0x05, 0x8b85);
2859 rtl_w1w0_phy(tp
, 0x06, 0x0000, 0x2000);
2860 rtl_writephy(tp
, 0x1f, 0x0007);
2861 rtl_writephy(tp
, 0x1e, 0x0020);
2862 rtl_w1w0_phy(tp
, 0x15, 0x0000, 0x1100);
2863 rtl_writephy(tp
, 0x1f, 0x0006);
2864 rtl_writephy(tp
, 0x00, 0x5a00);
2865 rtl_writephy(tp
, 0x1f, 0x0000);
2866 rtl_writephy(tp
, 0x0d, 0x0007);
2867 rtl_writephy(tp
, 0x0e, 0x003c);
2868 rtl_writephy(tp
, 0x0d, 0x4007);
2869 rtl_writephy(tp
, 0x0e, 0x0000);
2870 rtl_writephy(tp
, 0x0d, 0x0000);
2873 static void rtl8168e_2_hw_phy_config(struct rtl8169_private
*tp
)
2875 static const struct phy_reg phy_reg_init
[] = {
2876 /* Enable Delay cap */
2885 /* Channel estimation fine tune */
2902 rtl_apply_firmware(tp
);
2904 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2906 /* For 4-corner performance improve */
2907 rtl_writephy(tp
, 0x1f, 0x0005);
2908 rtl_writephy(tp
, 0x05, 0x8b80);
2909 rtl_w1w0_phy(tp
, 0x17, 0x0006, 0x0000);
2910 rtl_writephy(tp
, 0x1f, 0x0000);
2912 /* PHY auto speed down */
2913 rtl_writephy(tp
, 0x1f, 0x0004);
2914 rtl_writephy(tp
, 0x1f, 0x0007);
2915 rtl_writephy(tp
, 0x1e, 0x002d);
2916 rtl_w1w0_phy(tp
, 0x18, 0x0010, 0x0000);
2917 rtl_writephy(tp
, 0x1f, 0x0002);
2918 rtl_writephy(tp
, 0x1f, 0x0000);
2919 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
2921 /* improve 10M EEE waveform */
2922 rtl_writephy(tp
, 0x1f, 0x0005);
2923 rtl_writephy(tp
, 0x05, 0x8b86);
2924 rtl_w1w0_phy(tp
, 0x06, 0x0001, 0x0000);
2925 rtl_writephy(tp
, 0x1f, 0x0000);
2927 /* Improve 2-pair detection performance */
2928 rtl_writephy(tp
, 0x1f, 0x0005);
2929 rtl_writephy(tp
, 0x05, 0x8b85);
2930 rtl_w1w0_phy(tp
, 0x06, 0x4000, 0x0000);
2931 rtl_writephy(tp
, 0x1f, 0x0000);
2934 rtl_w1w0_eri(tp
->mmio_addr
, 0x1b0, ERIAR_MASK_1111
, 0x0000, 0x0003,
2936 rtl_writephy(tp
, 0x1f, 0x0005);
2937 rtl_writephy(tp
, 0x05, 0x8b85);
2938 rtl_w1w0_phy(tp
, 0x06, 0x0000, 0x2000);
2939 rtl_writephy(tp
, 0x1f, 0x0004);
2940 rtl_writephy(tp
, 0x1f, 0x0007);
2941 rtl_writephy(tp
, 0x1e, 0x0020);
2942 rtl_w1w0_phy(tp
, 0x15, 0x0000, 0x0100);
2943 rtl_writephy(tp
, 0x1f, 0x0002);
2944 rtl_writephy(tp
, 0x1f, 0x0000);
2945 rtl_writephy(tp
, 0x0d, 0x0007);
2946 rtl_writephy(tp
, 0x0e, 0x003c);
2947 rtl_writephy(tp
, 0x0d, 0x4007);
2948 rtl_writephy(tp
, 0x0e, 0x0000);
2949 rtl_writephy(tp
, 0x0d, 0x0000);
2952 rtl_writephy(tp
, 0x1f, 0x0003);
2953 rtl_w1w0_phy(tp
, 0x19, 0x0000, 0x0001);
2954 rtl_w1w0_phy(tp
, 0x10, 0x0000, 0x0400);
2955 rtl_writephy(tp
, 0x1f, 0x0000);
2958 static void rtl8168f_1_hw_phy_config(struct rtl8169_private
*tp
)
2960 static const struct phy_reg phy_reg_init
[] = {
2961 /* Channel estimation fine tune */
2966 /* Modify green table for giga & fnet */
2983 /* Modify green table for 10M */
2989 /* Disable hiimpedance detection (RTCT) */
2995 rtl_apply_firmware(tp
);
2997 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2999 /* For 4-corner performance improve */
3000 rtl_writephy(tp
, 0x1f, 0x0005);
3001 rtl_writephy(tp
, 0x05, 0x8b80);
3002 rtl_w1w0_phy(tp
, 0x06, 0x0006, 0x0000);
3003 rtl_writephy(tp
, 0x1f, 0x0000);
3005 /* PHY auto speed down */
3006 rtl_writephy(tp
, 0x1f, 0x0007);
3007 rtl_writephy(tp
, 0x1e, 0x002d);
3008 rtl_w1w0_phy(tp
, 0x18, 0x0010, 0x0000);
3009 rtl_writephy(tp
, 0x1f, 0x0000);
3010 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
3012 /* Improve 10M EEE waveform */
3013 rtl_writephy(tp
, 0x1f, 0x0005);
3014 rtl_writephy(tp
, 0x05, 0x8b86);
3015 rtl_w1w0_phy(tp
, 0x06, 0x0001, 0x0000);
3016 rtl_writephy(tp
, 0x1f, 0x0000);
3018 /* Improve 2-pair detection performance */
3019 rtl_writephy(tp
, 0x1f, 0x0005);
3020 rtl_writephy(tp
, 0x05, 0x8b85);
3021 rtl_w1w0_phy(tp
, 0x06, 0x4000, 0x0000);
3022 rtl_writephy(tp
, 0x1f, 0x0000);
3025 static void rtl8168f_2_hw_phy_config(struct rtl8169_private
*tp
)
3027 rtl_apply_firmware(tp
);
3029 /* For 4-corner performance improve */
3030 rtl_writephy(tp
, 0x1f, 0x0005);
3031 rtl_writephy(tp
, 0x05, 0x8b80);
3032 rtl_w1w0_phy(tp
, 0x06, 0x0006, 0x0000);
3033 rtl_writephy(tp
, 0x1f, 0x0000);
3035 /* PHY auto speed down */
3036 rtl_writephy(tp
, 0x1f, 0x0007);
3037 rtl_writephy(tp
, 0x1e, 0x002d);
3038 rtl_w1w0_phy(tp
, 0x18, 0x0010, 0x0000);
3039 rtl_writephy(tp
, 0x1f, 0x0000);
3040 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
3042 /* Improve 10M EEE waveform */
3043 rtl_writephy(tp
, 0x1f, 0x0005);
3044 rtl_writephy(tp
, 0x05, 0x8b86);
3045 rtl_w1w0_phy(tp
, 0x06, 0x0001, 0x0000);
3046 rtl_writephy(tp
, 0x1f, 0x0000);
3049 static void rtl8102e_hw_phy_config(struct rtl8169_private
*tp
)
3051 static const struct phy_reg phy_reg_init
[] = {
3058 rtl_writephy(tp
, 0x1f, 0x0000);
3059 rtl_patchphy(tp
, 0x11, 1 << 12);
3060 rtl_patchphy(tp
, 0x19, 1 << 13);
3061 rtl_patchphy(tp
, 0x10, 1 << 15);
3063 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3066 static void rtl8105e_hw_phy_config(struct rtl8169_private
*tp
)
3068 static const struct phy_reg phy_reg_init
[] = {
3082 /* Disable ALDPS before ram code */
3083 rtl_writephy(tp
, 0x1f, 0x0000);
3084 rtl_writephy(tp
, 0x18, 0x0310);
3087 rtl_apply_firmware(tp
);
3089 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3092 static void rtl_hw_phy_config(struct net_device
*dev
)
3094 struct rtl8169_private
*tp
= netdev_priv(dev
);
3096 rtl8169_print_mac_version(tp
);
3098 switch (tp
->mac_version
) {
3099 case RTL_GIGA_MAC_VER_01
:
3101 case RTL_GIGA_MAC_VER_02
:
3102 case RTL_GIGA_MAC_VER_03
:
3103 rtl8169s_hw_phy_config(tp
);
3105 case RTL_GIGA_MAC_VER_04
:
3106 rtl8169sb_hw_phy_config(tp
);
3108 case RTL_GIGA_MAC_VER_05
:
3109 rtl8169scd_hw_phy_config(tp
);
3111 case RTL_GIGA_MAC_VER_06
:
3112 rtl8169sce_hw_phy_config(tp
);
3114 case RTL_GIGA_MAC_VER_07
:
3115 case RTL_GIGA_MAC_VER_08
:
3116 case RTL_GIGA_MAC_VER_09
:
3117 rtl8102e_hw_phy_config(tp
);
3119 case RTL_GIGA_MAC_VER_11
:
3120 rtl8168bb_hw_phy_config(tp
);
3122 case RTL_GIGA_MAC_VER_12
:
3123 rtl8168bef_hw_phy_config(tp
);
3125 case RTL_GIGA_MAC_VER_17
:
3126 rtl8168bef_hw_phy_config(tp
);
3128 case RTL_GIGA_MAC_VER_18
:
3129 rtl8168cp_1_hw_phy_config(tp
);
3131 case RTL_GIGA_MAC_VER_19
:
3132 rtl8168c_1_hw_phy_config(tp
);
3134 case RTL_GIGA_MAC_VER_20
:
3135 rtl8168c_2_hw_phy_config(tp
);
3137 case RTL_GIGA_MAC_VER_21
:
3138 rtl8168c_3_hw_phy_config(tp
);
3140 case RTL_GIGA_MAC_VER_22
:
3141 rtl8168c_4_hw_phy_config(tp
);
3143 case RTL_GIGA_MAC_VER_23
:
3144 case RTL_GIGA_MAC_VER_24
:
3145 rtl8168cp_2_hw_phy_config(tp
);
3147 case RTL_GIGA_MAC_VER_25
:
3148 rtl8168d_1_hw_phy_config(tp
);
3150 case RTL_GIGA_MAC_VER_26
:
3151 rtl8168d_2_hw_phy_config(tp
);
3153 case RTL_GIGA_MAC_VER_27
:
3154 rtl8168d_3_hw_phy_config(tp
);
3156 case RTL_GIGA_MAC_VER_28
:
3157 rtl8168d_4_hw_phy_config(tp
);
3159 case RTL_GIGA_MAC_VER_29
:
3160 case RTL_GIGA_MAC_VER_30
:
3161 rtl8105e_hw_phy_config(tp
);
3163 case RTL_GIGA_MAC_VER_31
:
3166 case RTL_GIGA_MAC_VER_32
:
3167 case RTL_GIGA_MAC_VER_33
:
3168 rtl8168e_1_hw_phy_config(tp
);
3170 case RTL_GIGA_MAC_VER_34
:
3171 rtl8168e_2_hw_phy_config(tp
);
3173 case RTL_GIGA_MAC_VER_35
:
3174 rtl8168f_1_hw_phy_config(tp
);
3176 case RTL_GIGA_MAC_VER_36
:
3177 rtl8168f_2_hw_phy_config(tp
);
3185 static void rtl8169_phy_timer(unsigned long __opaque
)
3187 struct net_device
*dev
= (struct net_device
*)__opaque
;
3188 struct rtl8169_private
*tp
= netdev_priv(dev
);
3189 struct timer_list
*timer
= &tp
->timer
;
3190 void __iomem
*ioaddr
= tp
->mmio_addr
;
3191 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
3193 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
3195 spin_lock_irq(&tp
->lock
);
3197 if (tp
->phy_reset_pending(tp
)) {
3199 * A busy loop could burn quite a few cycles on nowadays CPU.
3200 * Let's delay the execution of the timer for a few ticks.
3206 if (tp
->link_ok(ioaddr
))
3209 netif_warn(tp
, link
, dev
, "PHY reset until link up\n");
3211 tp
->phy_reset_enable(tp
);
3214 mod_timer(timer
, jiffies
+ timeout
);
3216 spin_unlock_irq(&tp
->lock
);
3219 #ifdef CONFIG_NET_POLL_CONTROLLER
3221 * Polling 'interrupt' - used by things like netconsole to send skbs
3222 * without having to re-enable interrupts. It's not called while
3223 * the interrupt routine is executing.
3225 static void rtl8169_netpoll(struct net_device
*dev
)
3227 struct rtl8169_private
*tp
= netdev_priv(dev
);
3228 struct pci_dev
*pdev
= tp
->pci_dev
;
3230 disable_irq(pdev
->irq
);
3231 rtl8169_interrupt(pdev
->irq
, dev
);
3232 enable_irq(pdev
->irq
);
3236 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
3237 void __iomem
*ioaddr
)
3240 pci_release_regions(pdev
);
3241 pci_clear_mwi(pdev
);
3242 pci_disable_device(pdev
);
3246 static void rtl8169_phy_reset(struct net_device
*dev
,
3247 struct rtl8169_private
*tp
)
3251 tp
->phy_reset_enable(tp
);
3252 for (i
= 0; i
< 100; i
++) {
3253 if (!tp
->phy_reset_pending(tp
))
3257 netif_err(tp
, link
, dev
, "PHY reset failed\n");
3260 static bool rtl_tbi_enabled(struct rtl8169_private
*tp
)
3262 void __iomem
*ioaddr
= tp
->mmio_addr
;
3264 return (tp
->mac_version
== RTL_GIGA_MAC_VER_01
) &&
3265 (RTL_R8(PHYstatus
) & TBI_Enable
);
3268 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
3270 void __iomem
*ioaddr
= tp
->mmio_addr
;
3272 rtl_hw_phy_config(dev
);
3274 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
3275 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3279 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
3281 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
3282 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
3284 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
3285 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3287 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3288 rtl_writephy(tp
, 0x0b, 0x0000); //w 0x0b 15 0 0
3291 rtl8169_phy_reset(dev
, tp
);
3293 rtl8169_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
,
3294 ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
3295 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
3296 (tp
->mii
.supports_gmii
?
3297 ADVERTISED_1000baseT_Half
|
3298 ADVERTISED_1000baseT_Full
: 0));
3300 if (rtl_tbi_enabled(tp
))
3301 netif_info(tp
, link
, dev
, "TBI auto-negotiating\n");
3304 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
3306 void __iomem
*ioaddr
= tp
->mmio_addr
;
3310 low
= addr
[0] | (addr
[1] << 8) | (addr
[2] << 16) | (addr
[3] << 24);
3311 high
= addr
[4] | (addr
[5] << 8);
3313 spin_lock_irq(&tp
->lock
);
3315 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3317 RTL_W32(MAC4
, high
);
3323 if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
) {
3324 const struct exgmac_reg e
[] = {
3325 { .addr
= 0xe0, ERIAR_MASK_1111
, .val
= low
},
3326 { .addr
= 0xe4, ERIAR_MASK_1111
, .val
= high
},
3327 { .addr
= 0xf0, ERIAR_MASK_1111
, .val
= low
<< 16 },
3328 { .addr
= 0xf4, ERIAR_MASK_1111
, .val
= high
<< 16 |
3332 rtl_write_exgmac_batch(ioaddr
, e
, ARRAY_SIZE(e
));
3335 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3337 spin_unlock_irq(&tp
->lock
);
3340 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
3342 struct rtl8169_private
*tp
= netdev_priv(dev
);
3343 struct sockaddr
*addr
= p
;
3345 if (!is_valid_ether_addr(addr
->sa_data
))
3346 return -EADDRNOTAVAIL
;
3348 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
3350 rtl_rar_set(tp
, dev
->dev_addr
);
3355 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
3357 struct rtl8169_private
*tp
= netdev_priv(dev
);
3358 struct mii_ioctl_data
*data
= if_mii(ifr
);
3360 return netif_running(dev
) ? tp
->do_ioctl(tp
, data
, cmd
) : -ENODEV
;
3363 static int rtl_xmii_ioctl(struct rtl8169_private
*tp
,
3364 struct mii_ioctl_data
*data
, int cmd
)
3368 data
->phy_id
= 32; /* Internal PHY */
3372 data
->val_out
= rtl_readphy(tp
, data
->reg_num
& 0x1f);
3376 rtl_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
3382 static int rtl_tbi_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
3387 static const struct rtl_cfg_info
{
3388 void (*hw_start
)(struct net_device
*);
3389 unsigned int region
;
3395 } rtl_cfg_infos
[] = {
3397 .hw_start
= rtl_hw_start_8169
,
3400 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
3401 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
3402 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
3403 .features
= RTL_FEATURE_GMII
,
3404 .default_ver
= RTL_GIGA_MAC_VER_01
,
3407 .hw_start
= rtl_hw_start_8168
,
3410 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
3411 TxErr
| TxOK
| RxOK
| RxErr
,
3412 .napi_event
= TxErr
| TxOK
| RxOK
| RxOverflow
,
3413 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
,
3414 .default_ver
= RTL_GIGA_MAC_VER_11
,
3417 .hw_start
= rtl_hw_start_8101
,
3420 .intr_event
= SYSErr
| LinkChg
| RxOverflow
| PCSTimeout
|
3421 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
3422 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
3423 .features
= RTL_FEATURE_MSI
,
3424 .default_ver
= RTL_GIGA_MAC_VER_13
,
3428 /* Cfg9346_Unlock assumed. */
3429 static unsigned rtl_try_msi(struct pci_dev
*pdev
, void __iomem
*ioaddr
,
3430 const struct rtl_cfg_info
*cfg
)
3435 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
3436 if (cfg
->features
& RTL_FEATURE_MSI
) {
3437 if (pci_enable_msi(pdev
)) {
3438 dev_info(&pdev
->dev
, "no MSI. Back to INTx.\n");
3441 msi
= RTL_FEATURE_MSI
;
3444 RTL_W8(Config2
, cfg2
);
3448 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8169_private
*tp
)
3450 if (tp
->features
& RTL_FEATURE_MSI
) {
3451 pci_disable_msi(pdev
);
3452 tp
->features
&= ~RTL_FEATURE_MSI
;
3456 static const struct net_device_ops rtl8169_netdev_ops
= {
3457 .ndo_open
= rtl8169_open
,
3458 .ndo_stop
= rtl8169_close
,
3459 .ndo_get_stats
= rtl8169_get_stats
,
3460 .ndo_start_xmit
= rtl8169_start_xmit
,
3461 .ndo_tx_timeout
= rtl8169_tx_timeout
,
3462 .ndo_validate_addr
= eth_validate_addr
,
3463 .ndo_change_mtu
= rtl8169_change_mtu
,
3464 .ndo_fix_features
= rtl8169_fix_features
,
3465 .ndo_set_features
= rtl8169_set_features
,
3466 .ndo_set_mac_address
= rtl_set_mac_address
,
3467 .ndo_do_ioctl
= rtl8169_ioctl
,
3468 .ndo_set_rx_mode
= rtl_set_rx_mode
,
3469 #ifdef CONFIG_NET_POLL_CONTROLLER
3470 .ndo_poll_controller
= rtl8169_netpoll
,
3475 static void __devinit
rtl_init_mdio_ops(struct rtl8169_private
*tp
)
3477 struct mdio_ops
*ops
= &tp
->mdio_ops
;
3479 switch (tp
->mac_version
) {
3480 case RTL_GIGA_MAC_VER_27
:
3481 ops
->write
= r8168dp_1_mdio_write
;
3482 ops
->read
= r8168dp_1_mdio_read
;
3484 case RTL_GIGA_MAC_VER_28
:
3485 case RTL_GIGA_MAC_VER_31
:
3486 ops
->write
= r8168dp_2_mdio_write
;
3487 ops
->read
= r8168dp_2_mdio_read
;
3490 ops
->write
= r8169_mdio_write
;
3491 ops
->read
= r8169_mdio_read
;
3496 static void rtl_wol_suspend_quirk(struct rtl8169_private
*tp
)
3498 void __iomem
*ioaddr
= tp
->mmio_addr
;
3500 switch (tp
->mac_version
) {
3501 case RTL_GIGA_MAC_VER_29
:
3502 case RTL_GIGA_MAC_VER_30
:
3503 case RTL_GIGA_MAC_VER_32
:
3504 case RTL_GIGA_MAC_VER_33
:
3505 case RTL_GIGA_MAC_VER_34
:
3506 RTL_W32(RxConfig
, RTL_R32(RxConfig
) |
3507 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
);
3514 static bool rtl_wol_pll_power_down(struct rtl8169_private
*tp
)
3516 if (!(__rtl8169_get_wol(tp
) & WAKE_ANY
))
3519 rtl_writephy(tp
, 0x1f, 0x0000);
3520 rtl_writephy(tp
, MII_BMCR
, 0x0000);
3522 rtl_wol_suspend_quirk(tp
);
3527 static void r810x_phy_power_down(struct rtl8169_private
*tp
)
3529 rtl_writephy(tp
, 0x1f, 0x0000);
3530 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
3533 static void r810x_phy_power_up(struct rtl8169_private
*tp
)
3535 rtl_writephy(tp
, 0x1f, 0x0000);
3536 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
3539 static void r810x_pll_power_down(struct rtl8169_private
*tp
)
3541 if (rtl_wol_pll_power_down(tp
))
3544 r810x_phy_power_down(tp
);
3547 static void r810x_pll_power_up(struct rtl8169_private
*tp
)
3549 r810x_phy_power_up(tp
);
3552 static void r8168_phy_power_up(struct rtl8169_private
*tp
)
3554 rtl_writephy(tp
, 0x1f, 0x0000);
3555 switch (tp
->mac_version
) {
3556 case RTL_GIGA_MAC_VER_11
:
3557 case RTL_GIGA_MAC_VER_12
:
3558 case RTL_GIGA_MAC_VER_17
:
3559 case RTL_GIGA_MAC_VER_18
:
3560 case RTL_GIGA_MAC_VER_19
:
3561 case RTL_GIGA_MAC_VER_20
:
3562 case RTL_GIGA_MAC_VER_21
:
3563 case RTL_GIGA_MAC_VER_22
:
3564 case RTL_GIGA_MAC_VER_23
:
3565 case RTL_GIGA_MAC_VER_24
:
3566 case RTL_GIGA_MAC_VER_25
:
3567 case RTL_GIGA_MAC_VER_26
:
3568 case RTL_GIGA_MAC_VER_27
:
3569 case RTL_GIGA_MAC_VER_28
:
3570 case RTL_GIGA_MAC_VER_31
:
3571 rtl_writephy(tp
, 0x0e, 0x0000);
3576 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
3579 static void r8168_phy_power_down(struct rtl8169_private
*tp
)
3581 rtl_writephy(tp
, 0x1f, 0x0000);
3582 switch (tp
->mac_version
) {
3583 case RTL_GIGA_MAC_VER_32
:
3584 case RTL_GIGA_MAC_VER_33
:
3585 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
| BMCR_PDOWN
);
3588 case RTL_GIGA_MAC_VER_11
:
3589 case RTL_GIGA_MAC_VER_12
:
3590 case RTL_GIGA_MAC_VER_17
:
3591 case RTL_GIGA_MAC_VER_18
:
3592 case RTL_GIGA_MAC_VER_19
:
3593 case RTL_GIGA_MAC_VER_20
:
3594 case RTL_GIGA_MAC_VER_21
:
3595 case RTL_GIGA_MAC_VER_22
:
3596 case RTL_GIGA_MAC_VER_23
:
3597 case RTL_GIGA_MAC_VER_24
:
3598 case RTL_GIGA_MAC_VER_25
:
3599 case RTL_GIGA_MAC_VER_26
:
3600 case RTL_GIGA_MAC_VER_27
:
3601 case RTL_GIGA_MAC_VER_28
:
3602 case RTL_GIGA_MAC_VER_31
:
3603 rtl_writephy(tp
, 0x0e, 0x0200);
3605 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
3610 static void r8168_pll_power_down(struct rtl8169_private
*tp
)
3612 void __iomem
*ioaddr
= tp
->mmio_addr
;
3614 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3615 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3616 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) &&
3617 r8168dp_check_dash(tp
)) {
3621 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_23
||
3622 tp
->mac_version
== RTL_GIGA_MAC_VER_24
) &&
3623 (RTL_R16(CPlusCmd
) & ASF
)) {
3627 if (tp
->mac_version
== RTL_GIGA_MAC_VER_32
||
3628 tp
->mac_version
== RTL_GIGA_MAC_VER_33
)
3629 rtl_ephy_write(ioaddr
, 0x19, 0xff64);
3631 if (rtl_wol_pll_power_down(tp
))
3634 r8168_phy_power_down(tp
);
3636 switch (tp
->mac_version
) {
3637 case RTL_GIGA_MAC_VER_25
:
3638 case RTL_GIGA_MAC_VER_26
:
3639 case RTL_GIGA_MAC_VER_27
:
3640 case RTL_GIGA_MAC_VER_28
:
3641 case RTL_GIGA_MAC_VER_31
:
3642 case RTL_GIGA_MAC_VER_32
:
3643 case RTL_GIGA_MAC_VER_33
:
3644 RTL_W8(PMCH
, RTL_R8(PMCH
) & ~0x80);
3649 static void r8168_pll_power_up(struct rtl8169_private
*tp
)
3651 void __iomem
*ioaddr
= tp
->mmio_addr
;
3653 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3654 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3655 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) &&
3656 r8168dp_check_dash(tp
)) {
3660 switch (tp
->mac_version
) {
3661 case RTL_GIGA_MAC_VER_25
:
3662 case RTL_GIGA_MAC_VER_26
:
3663 case RTL_GIGA_MAC_VER_27
:
3664 case RTL_GIGA_MAC_VER_28
:
3665 case RTL_GIGA_MAC_VER_31
:
3666 case RTL_GIGA_MAC_VER_32
:
3667 case RTL_GIGA_MAC_VER_33
:
3668 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0x80);
3672 r8168_phy_power_up(tp
);
3675 static void rtl_generic_op(struct rtl8169_private
*tp
,
3676 void (*op
)(struct rtl8169_private
*))
3682 static void rtl_pll_power_down(struct rtl8169_private
*tp
)
3684 rtl_generic_op(tp
, tp
->pll_power_ops
.down
);
3687 static void rtl_pll_power_up(struct rtl8169_private
*tp
)
3689 rtl_generic_op(tp
, tp
->pll_power_ops
.up
);
3692 static void __devinit
rtl_init_pll_power_ops(struct rtl8169_private
*tp
)
3694 struct pll_power_ops
*ops
= &tp
->pll_power_ops
;
3696 switch (tp
->mac_version
) {
3697 case RTL_GIGA_MAC_VER_07
:
3698 case RTL_GIGA_MAC_VER_08
:
3699 case RTL_GIGA_MAC_VER_09
:
3700 case RTL_GIGA_MAC_VER_10
:
3701 case RTL_GIGA_MAC_VER_16
:
3702 case RTL_GIGA_MAC_VER_29
:
3703 case RTL_GIGA_MAC_VER_30
:
3704 ops
->down
= r810x_pll_power_down
;
3705 ops
->up
= r810x_pll_power_up
;
3708 case RTL_GIGA_MAC_VER_11
:
3709 case RTL_GIGA_MAC_VER_12
:
3710 case RTL_GIGA_MAC_VER_17
:
3711 case RTL_GIGA_MAC_VER_18
:
3712 case RTL_GIGA_MAC_VER_19
:
3713 case RTL_GIGA_MAC_VER_20
:
3714 case RTL_GIGA_MAC_VER_21
:
3715 case RTL_GIGA_MAC_VER_22
:
3716 case RTL_GIGA_MAC_VER_23
:
3717 case RTL_GIGA_MAC_VER_24
:
3718 case RTL_GIGA_MAC_VER_25
:
3719 case RTL_GIGA_MAC_VER_26
:
3720 case RTL_GIGA_MAC_VER_27
:
3721 case RTL_GIGA_MAC_VER_28
:
3722 case RTL_GIGA_MAC_VER_31
:
3723 case RTL_GIGA_MAC_VER_32
:
3724 case RTL_GIGA_MAC_VER_33
:
3725 case RTL_GIGA_MAC_VER_34
:
3726 case RTL_GIGA_MAC_VER_35
:
3727 case RTL_GIGA_MAC_VER_36
:
3728 ops
->down
= r8168_pll_power_down
;
3729 ops
->up
= r8168_pll_power_up
;
3739 static void rtl_init_rxcfg(struct rtl8169_private
*tp
)
3741 void __iomem
*ioaddr
= tp
->mmio_addr
;
3743 switch (tp
->mac_version
) {
3744 case RTL_GIGA_MAC_VER_01
:
3745 case RTL_GIGA_MAC_VER_02
:
3746 case RTL_GIGA_MAC_VER_03
:
3747 case RTL_GIGA_MAC_VER_04
:
3748 case RTL_GIGA_MAC_VER_05
:
3749 case RTL_GIGA_MAC_VER_06
:
3750 case RTL_GIGA_MAC_VER_10
:
3751 case RTL_GIGA_MAC_VER_11
:
3752 case RTL_GIGA_MAC_VER_12
:
3753 case RTL_GIGA_MAC_VER_13
:
3754 case RTL_GIGA_MAC_VER_14
:
3755 case RTL_GIGA_MAC_VER_15
:
3756 case RTL_GIGA_MAC_VER_16
:
3757 case RTL_GIGA_MAC_VER_17
:
3758 RTL_W32(RxConfig
, RX_FIFO_THRESH
| RX_DMA_BURST
);
3760 case RTL_GIGA_MAC_VER_18
:
3761 case RTL_GIGA_MAC_VER_19
:
3762 case RTL_GIGA_MAC_VER_20
:
3763 case RTL_GIGA_MAC_VER_21
:
3764 case RTL_GIGA_MAC_VER_22
:
3765 case RTL_GIGA_MAC_VER_23
:
3766 case RTL_GIGA_MAC_VER_24
:
3767 RTL_W32(RxConfig
, RX128_INT_EN
| RX_MULTI_EN
| RX_DMA_BURST
);
3770 RTL_W32(RxConfig
, RX128_INT_EN
| RX_DMA_BURST
);
3775 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
3777 tp
->dirty_tx
= tp
->dirty_rx
= tp
->cur_tx
= tp
->cur_rx
= 0;
3780 static void rtl_hw_jumbo_enable(struct rtl8169_private
*tp
)
3782 rtl_generic_op(tp
, tp
->jumbo_ops
.enable
);
3785 static void rtl_hw_jumbo_disable(struct rtl8169_private
*tp
)
3787 rtl_generic_op(tp
, tp
->jumbo_ops
.disable
);
3790 static void r8168c_hw_jumbo_enable(struct rtl8169_private
*tp
)
3792 void __iomem
*ioaddr
= tp
->mmio_addr
;
3794 RTL_W8(Config3
, RTL_R8(Config3
) | Jumbo_En0
);
3795 RTL_W8(Config4
, RTL_R8(Config4
) | Jumbo_En1
);
3796 rtl_tx_performance_tweak(tp
->pci_dev
, 0x2 << MAX_READ_REQUEST_SHIFT
);
3799 static void r8168c_hw_jumbo_disable(struct rtl8169_private
*tp
)
3801 void __iomem
*ioaddr
= tp
->mmio_addr
;
3803 RTL_W8(Config3
, RTL_R8(Config3
) & ~Jumbo_En0
);
3804 RTL_W8(Config4
, RTL_R8(Config4
) & ~Jumbo_En1
);
3805 rtl_tx_performance_tweak(tp
->pci_dev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3808 static void r8168dp_hw_jumbo_enable(struct rtl8169_private
*tp
)
3810 void __iomem
*ioaddr
= tp
->mmio_addr
;
3812 RTL_W8(Config3
, RTL_R8(Config3
) | Jumbo_En0
);
3815 static void r8168dp_hw_jumbo_disable(struct rtl8169_private
*tp
)
3817 void __iomem
*ioaddr
= tp
->mmio_addr
;
3819 RTL_W8(Config3
, RTL_R8(Config3
) & ~Jumbo_En0
);
3822 static void r8168e_hw_jumbo_enable(struct rtl8169_private
*tp
)
3824 void __iomem
*ioaddr
= tp
->mmio_addr
;
3825 struct pci_dev
*pdev
= tp
->pci_dev
;
3827 RTL_W8(MaxTxPacketSize
, 0x3f);
3828 RTL_W8(Config3
, RTL_R8(Config3
) | Jumbo_En0
);
3829 RTL_W8(Config4
, RTL_R8(Config4
) | 0x01);
3830 pci_write_config_byte(pdev
, 0x79, 0x20);
3833 static void r8168e_hw_jumbo_disable(struct rtl8169_private
*tp
)
3835 void __iomem
*ioaddr
= tp
->mmio_addr
;
3836 struct pci_dev
*pdev
= tp
->pci_dev
;
3838 RTL_W8(MaxTxPacketSize
, 0x0c);
3839 RTL_W8(Config3
, RTL_R8(Config3
) & ~Jumbo_En0
);
3840 RTL_W8(Config4
, RTL_R8(Config4
) & ~0x01);
3841 pci_write_config_byte(pdev
, 0x79, 0x50);
3844 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private
*tp
)
3846 rtl_tx_performance_tweak(tp
->pci_dev
,
3847 (0x2 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
3850 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private
*tp
)
3852 rtl_tx_performance_tweak(tp
->pci_dev
,
3853 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
3856 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private
*tp
)
3858 void __iomem
*ioaddr
= tp
->mmio_addr
;
3860 r8168b_0_hw_jumbo_enable(tp
);
3862 RTL_W8(Config4
, RTL_R8(Config4
) | (1 << 0));
3865 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private
*tp
)
3867 void __iomem
*ioaddr
= tp
->mmio_addr
;
3869 r8168b_0_hw_jumbo_disable(tp
);
3871 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
3874 static void __devinit
rtl_init_jumbo_ops(struct rtl8169_private
*tp
)
3876 struct jumbo_ops
*ops
= &tp
->jumbo_ops
;
3878 switch (tp
->mac_version
) {
3879 case RTL_GIGA_MAC_VER_11
:
3880 ops
->disable
= r8168b_0_hw_jumbo_disable
;
3881 ops
->enable
= r8168b_0_hw_jumbo_enable
;
3883 case RTL_GIGA_MAC_VER_12
:
3884 case RTL_GIGA_MAC_VER_17
:
3885 ops
->disable
= r8168b_1_hw_jumbo_disable
;
3886 ops
->enable
= r8168b_1_hw_jumbo_enable
;
3888 case RTL_GIGA_MAC_VER_18
: /* Wild guess. Needs info from Realtek. */
3889 case RTL_GIGA_MAC_VER_19
:
3890 case RTL_GIGA_MAC_VER_20
:
3891 case RTL_GIGA_MAC_VER_21
: /* Wild guess. Needs info from Realtek. */
3892 case RTL_GIGA_MAC_VER_22
:
3893 case RTL_GIGA_MAC_VER_23
:
3894 case RTL_GIGA_MAC_VER_24
:
3895 case RTL_GIGA_MAC_VER_25
:
3896 case RTL_GIGA_MAC_VER_26
:
3897 ops
->disable
= r8168c_hw_jumbo_disable
;
3898 ops
->enable
= r8168c_hw_jumbo_enable
;
3900 case RTL_GIGA_MAC_VER_27
:
3901 case RTL_GIGA_MAC_VER_28
:
3902 ops
->disable
= r8168dp_hw_jumbo_disable
;
3903 ops
->enable
= r8168dp_hw_jumbo_enable
;
3905 case RTL_GIGA_MAC_VER_31
: /* Wild guess. Needs info from Realtek. */
3906 case RTL_GIGA_MAC_VER_32
:
3907 case RTL_GIGA_MAC_VER_33
:
3908 case RTL_GIGA_MAC_VER_34
:
3909 ops
->disable
= r8168e_hw_jumbo_disable
;
3910 ops
->enable
= r8168e_hw_jumbo_enable
;
3914 * No action needed for jumbo frames with 8169.
3915 * No jumbo for 810x at all.
3918 ops
->disable
= NULL
;
3924 static void rtl_hw_reset(struct rtl8169_private
*tp
)
3926 void __iomem
*ioaddr
= tp
->mmio_addr
;
3929 /* Soft reset the chip. */
3930 RTL_W8(ChipCmd
, CmdReset
);
3932 /* Check that the chip has finished the reset. */
3933 for (i
= 0; i
< 100; i
++) {
3934 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
3940 static int __devinit
3941 rtl8169_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
3943 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
3944 const unsigned int region
= cfg
->region
;
3945 struct rtl8169_private
*tp
;
3946 struct mii_if_info
*mii
;
3947 struct net_device
*dev
;
3948 void __iomem
*ioaddr
;
3952 if (netif_msg_drv(&debug
)) {
3953 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
3954 MODULENAME
, RTL8169_VERSION
);
3957 dev
= alloc_etherdev(sizeof (*tp
));
3959 if (netif_msg_drv(&debug
))
3960 dev_err(&pdev
->dev
, "unable to alloc new ethernet\n");
3965 SET_NETDEV_DEV(dev
, &pdev
->dev
);
3966 dev
->netdev_ops
= &rtl8169_netdev_ops
;
3967 tp
= netdev_priv(dev
);
3970 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
3974 mii
->mdio_read
= rtl_mdio_read
;
3975 mii
->mdio_write
= rtl_mdio_write
;
3976 mii
->phy_id_mask
= 0x1f;
3977 mii
->reg_num_mask
= 0x1f;
3978 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
3980 /* disable ASPM completely as that cause random device stop working
3981 * problems as well as full system hangs for some PCIe devices users */
3982 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
| PCIE_LINK_STATE_L1
|
3983 PCIE_LINK_STATE_CLKPM
);
3985 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3986 rc
= pci_enable_device(pdev
);
3988 netif_err(tp
, probe
, dev
, "enable failure\n");
3989 goto err_out_free_dev_1
;
3992 if (pci_set_mwi(pdev
) < 0)
3993 netif_info(tp
, probe
, dev
, "Mem-Wr-Inval unavailable\n");
3995 /* make sure PCI base addr 1 is MMIO */
3996 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
3997 netif_err(tp
, probe
, dev
,
3998 "region #%d not an MMIO resource, aborting\n",
4004 /* check for weird/broken PCI region reporting */
4005 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
4006 netif_err(tp
, probe
, dev
,
4007 "Invalid PCI region size(s), aborting\n");
4012 rc
= pci_request_regions(pdev
, MODULENAME
);
4014 netif_err(tp
, probe
, dev
, "could not request regions\n");
4018 tp
->cp_cmd
= RxChkSum
;
4020 if ((sizeof(dma_addr_t
) > 4) &&
4021 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) && use_dac
) {
4022 tp
->cp_cmd
|= PCIDAC
;
4023 dev
->features
|= NETIF_F_HIGHDMA
;
4025 rc
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
4027 netif_err(tp
, probe
, dev
, "DMA configuration failed\n");
4028 goto err_out_free_res_3
;
4032 /* ioremap MMIO region */
4033 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
4035 netif_err(tp
, probe
, dev
, "cannot remap MMIO, aborting\n");
4037 goto err_out_free_res_3
;
4039 tp
->mmio_addr
= ioaddr
;
4041 if (!pci_is_pcie(pdev
))
4042 netif_info(tp
, probe
, dev
, "not PCI Express\n");
4044 /* Identify chip attached to board */
4045 rtl8169_get_mac_version(tp
, dev
, cfg
->default_ver
);
4049 RTL_W16(IntrMask
, 0x0000);
4053 RTL_W16(IntrStatus
, 0xffff);
4055 pci_set_master(pdev
);
4058 * Pretend we are using VLANs; This bypasses a nasty bug where
4059 * Interrupts stop flowing on high load on 8110SCd controllers.
4061 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
4062 tp
->cp_cmd
|= RxVlan
;
4064 rtl_init_mdio_ops(tp
);
4065 rtl_init_pll_power_ops(tp
);
4066 rtl_init_jumbo_ops(tp
);
4068 rtl8169_print_mac_version(tp
);
4070 chipset
= tp
->mac_version
;
4071 tp
->txd_version
= rtl_chip_infos
[chipset
].txd_version
;
4073 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4074 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
4075 RTL_W8(Config5
, RTL_R8(Config5
) & PMEStatus
);
4076 if ((RTL_R8(Config3
) & (LinkUp
| MagicPacket
)) != 0)
4077 tp
->features
|= RTL_FEATURE_WOL
;
4078 if ((RTL_R8(Config5
) & (UWF
| BWF
| MWF
)) != 0)
4079 tp
->features
|= RTL_FEATURE_WOL
;
4080 tp
->features
|= rtl_try_msi(pdev
, ioaddr
, cfg
);
4081 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4083 if (rtl_tbi_enabled(tp
)) {
4084 tp
->set_speed
= rtl8169_set_speed_tbi
;
4085 tp
->get_settings
= rtl8169_gset_tbi
;
4086 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
4087 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
4088 tp
->link_ok
= rtl8169_tbi_link_ok
;
4089 tp
->do_ioctl
= rtl_tbi_ioctl
;
4091 tp
->set_speed
= rtl8169_set_speed_xmii
;
4092 tp
->get_settings
= rtl8169_gset_xmii
;
4093 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
4094 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
4095 tp
->link_ok
= rtl8169_xmii_link_ok
;
4096 tp
->do_ioctl
= rtl_xmii_ioctl
;
4099 spin_lock_init(&tp
->lock
);
4101 /* Get MAC address */
4102 for (i
= 0; i
< MAC_ADDR_LEN
; i
++)
4103 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
4104 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
4106 SET_ETHTOOL_OPS(dev
, &rtl8169_ethtool_ops
);
4107 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
4108 dev
->irq
= pdev
->irq
;
4109 dev
->base_addr
= (unsigned long) ioaddr
;
4111 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, R8169_NAPI_WEIGHT
);
4113 /* don't enable SG, IP_CSUM and TSO by default - it might not work
4114 * properly for all devices */
4115 dev
->features
|= NETIF_F_RXCSUM
|
4116 NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
4118 dev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
4119 NETIF_F_RXCSUM
| NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
4120 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
4123 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
4124 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
4125 dev
->hw_features
&= ~NETIF_F_HW_VLAN_RX
;
4127 tp
->intr_mask
= 0xffff;
4128 tp
->hw_start
= cfg
->hw_start
;
4129 tp
->intr_event
= cfg
->intr_event
;
4130 tp
->napi_event
= cfg
->napi_event
;
4132 tp
->opts1_mask
= (tp
->mac_version
!= RTL_GIGA_MAC_VER_01
) ?
4133 ~(RxBOVF
| RxFOVF
) : ~0;
4135 init_timer(&tp
->timer
);
4136 tp
->timer
.data
= (unsigned long) dev
;
4137 tp
->timer
.function
= rtl8169_phy_timer
;
4139 tp
->rtl_fw
= RTL_FIRMWARE_UNKNOWN
;
4141 rc
= register_netdev(dev
);
4145 pci_set_drvdata(pdev
, dev
);
4147 netif_info(tp
, probe
, dev
, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
4148 rtl_chip_infos
[chipset
].name
, dev
->base_addr
, dev
->dev_addr
,
4149 (u32
)(RTL_R32(TxConfig
) & 0x9cf0f8ff), dev
->irq
);
4150 if (rtl_chip_infos
[chipset
].jumbo_max
!= JUMBO_1K
) {
4151 netif_info(tp
, probe
, dev
, "jumbo features [frames: %d bytes, "
4152 "tx checksumming: %s]\n",
4153 rtl_chip_infos
[chipset
].jumbo_max
,
4154 rtl_chip_infos
[chipset
].jumbo_tx_csum
? "ok" : "ko");
4157 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
4158 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
4159 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
4160 rtl8168_driver_start(tp
);
4163 device_set_wakeup_enable(&pdev
->dev
, tp
->features
& RTL_FEATURE_WOL
);
4165 if (pci_dev_run_wake(pdev
))
4166 pm_runtime_put_noidle(&pdev
->dev
);
4168 netif_carrier_off(dev
);
4174 rtl_disable_msi(pdev
, tp
);
4177 pci_release_regions(pdev
);
4179 pci_clear_mwi(pdev
);
4180 pci_disable_device(pdev
);
4186 static void __devexit
rtl8169_remove_one(struct pci_dev
*pdev
)
4188 struct net_device
*dev
= pci_get_drvdata(pdev
);
4189 struct rtl8169_private
*tp
= netdev_priv(dev
);
4191 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
4192 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
4193 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
4194 rtl8168_driver_stop(tp
);
4197 cancel_delayed_work_sync(&tp
->task
);
4199 unregister_netdev(dev
);
4201 rtl_release_firmware(tp
);
4203 if (pci_dev_run_wake(pdev
))
4204 pm_runtime_get_noresume(&pdev
->dev
);
4206 /* restore original MAC address */
4207 rtl_rar_set(tp
, dev
->perm_addr
);
4209 rtl_disable_msi(pdev
, tp
);
4210 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
4211 pci_set_drvdata(pdev
, NULL
);
4214 static void rtl_request_uncached_firmware(struct rtl8169_private
*tp
)
4216 struct rtl_fw
*rtl_fw
;
4220 name
= rtl_lookup_firmware_name(tp
);
4222 goto out_no_firmware
;
4224 rtl_fw
= kzalloc(sizeof(*rtl_fw
), GFP_KERNEL
);
4228 rc
= request_firmware(&rtl_fw
->fw
, name
, &tp
->pci_dev
->dev
);
4232 rc
= rtl_check_firmware(tp
, rtl_fw
);
4234 goto err_release_firmware
;
4236 tp
->rtl_fw
= rtl_fw
;
4240 err_release_firmware
:
4241 release_firmware(rtl_fw
->fw
);
4245 netif_warn(tp
, ifup
, tp
->dev
, "unable to load firmware patch %s (%d)\n",
4252 static void rtl_request_firmware(struct rtl8169_private
*tp
)
4254 if (IS_ERR(tp
->rtl_fw
))
4255 rtl_request_uncached_firmware(tp
);
4258 static int rtl8169_open(struct net_device
*dev
)
4260 struct rtl8169_private
*tp
= netdev_priv(dev
);
4261 void __iomem
*ioaddr
= tp
->mmio_addr
;
4262 struct pci_dev
*pdev
= tp
->pci_dev
;
4263 int retval
= -ENOMEM
;
4265 pm_runtime_get_sync(&pdev
->dev
);
4268 * Rx and Tx desscriptors needs 256 bytes alignment.
4269 * dma_alloc_coherent provides more.
4271 tp
->TxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
,
4272 &tp
->TxPhyAddr
, GFP_KERNEL
);
4273 if (!tp
->TxDescArray
)
4274 goto err_pm_runtime_put
;
4276 tp
->RxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
,
4277 &tp
->RxPhyAddr
, GFP_KERNEL
);
4278 if (!tp
->RxDescArray
)
4281 retval
= rtl8169_init_ring(dev
);
4285 INIT_DELAYED_WORK(&tp
->task
, NULL
);
4289 rtl_request_firmware(tp
);
4291 retval
= request_irq(dev
->irq
, rtl8169_interrupt
,
4292 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
4295 goto err_release_fw_2
;
4297 napi_enable(&tp
->napi
);
4299 rtl8169_init_phy(dev
, tp
);
4301 rtl8169_set_features(dev
, dev
->features
);
4303 rtl_pll_power_up(tp
);
4307 tp
->saved_wolopts
= 0;
4308 pm_runtime_put_noidle(&pdev
->dev
);
4310 rtl8169_check_link_status(dev
, tp
, ioaddr
);
4315 rtl_release_firmware(tp
);
4316 rtl8169_rx_clear(tp
);
4318 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
4320 tp
->RxDescArray
= NULL
;
4322 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
4324 tp
->TxDescArray
= NULL
;
4326 pm_runtime_put_noidle(&pdev
->dev
);
4330 static void rtl_rx_close(struct rtl8169_private
*tp
)
4332 void __iomem
*ioaddr
= tp
->mmio_addr
;
4334 RTL_W32(RxConfig
, RTL_R32(RxConfig
) & ~RX_CONFIG_ACCEPT_MASK
);
4337 static void rtl8169_hw_reset(struct rtl8169_private
*tp
)
4339 void __iomem
*ioaddr
= tp
->mmio_addr
;
4341 /* Disable interrupts */
4342 rtl8169_irq_mask_and_ack(tp
);
4346 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
4347 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
4348 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
4349 while (RTL_R8(TxPoll
) & NPQ
)
4351 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
||
4352 tp
->mac_version
== RTL_GIGA_MAC_VER_35
||
4353 tp
->mac_version
== RTL_GIGA_MAC_VER_36
) {
4354 RTL_W8(ChipCmd
, RTL_R8(ChipCmd
) | StopReq
);
4355 while (!(RTL_R32(TxConfig
) & TXCFG_EMPTY
))
4358 RTL_W8(ChipCmd
, RTL_R8(ChipCmd
) | StopReq
);
4365 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
4367 void __iomem
*ioaddr
= tp
->mmio_addr
;
4369 /* Set DMA burst size and Interframe Gap Time */
4370 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
4371 (InterFrameGap
<< TxInterFrameGapShift
));
4374 static void rtl_hw_start(struct net_device
*dev
)
4376 struct rtl8169_private
*tp
= netdev_priv(dev
);
4380 netif_start_queue(dev
);
4383 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
4384 void __iomem
*ioaddr
)
4387 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4388 * register to be written before TxDescAddrLow to work.
4389 * Switching from MMIO to I/O access fixes the issue as well.
4391 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
4392 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_BIT_MASK(32));
4393 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
4394 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_BIT_MASK(32));
4397 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
4401 cmd
= RTL_R16(CPlusCmd
);
4402 RTL_W16(CPlusCmd
, cmd
);
4406 static void rtl_set_rx_max_size(void __iomem
*ioaddr
, unsigned int rx_buf_sz
)
4408 /* Low hurts. Let's disable the filtering. */
4409 RTL_W16(RxMaxSize
, rx_buf_sz
+ 1);
4412 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
4414 static const struct rtl_cfg2_info
{
4419 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
4420 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
4421 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
4422 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
4424 const struct rtl_cfg2_info
*p
= cfg2_info
;
4428 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
4429 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
4430 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
4431 RTL_W32(0x7c, p
->val
);
4437 static void rtl_hw_start_8169(struct net_device
*dev
)
4439 struct rtl8169_private
*tp
= netdev_priv(dev
);
4440 void __iomem
*ioaddr
= tp
->mmio_addr
;
4441 struct pci_dev
*pdev
= tp
->pci_dev
;
4443 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
4444 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
4445 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
4448 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4449 if (tp
->mac_version
== RTL_GIGA_MAC_VER_01
||
4450 tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
4451 tp
->mac_version
== RTL_GIGA_MAC_VER_03
||
4452 tp
->mac_version
== RTL_GIGA_MAC_VER_04
)
4453 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4457 RTL_W8(EarlyTxThres
, NoEarlyTx
);
4459 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
4461 if (tp
->mac_version
== RTL_GIGA_MAC_VER_01
||
4462 tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
4463 tp
->mac_version
== RTL_GIGA_MAC_VER_03
||
4464 tp
->mac_version
== RTL_GIGA_MAC_VER_04
)
4465 rtl_set_rx_tx_config_registers(tp
);
4467 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
4469 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
4470 tp
->mac_version
== RTL_GIGA_MAC_VER_03
) {
4471 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4472 "Bit-3 and bit-14 MUST be 1\n");
4473 tp
->cp_cmd
|= (1 << 14);
4476 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4478 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
4481 * Undocumented corner. Supposedly:
4482 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4484 RTL_W16(IntrMitigate
, 0x0000);
4486 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
4488 if (tp
->mac_version
!= RTL_GIGA_MAC_VER_01
&&
4489 tp
->mac_version
!= RTL_GIGA_MAC_VER_02
&&
4490 tp
->mac_version
!= RTL_GIGA_MAC_VER_03
&&
4491 tp
->mac_version
!= RTL_GIGA_MAC_VER_04
) {
4492 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4493 rtl_set_rx_tx_config_registers(tp
);
4496 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4498 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4501 RTL_W32(RxMissed
, 0);
4503 rtl_set_rx_mode(dev
);
4505 /* no early-rx interrupts */
4506 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
4508 /* Enable all known interrupts by setting the interrupt mask. */
4509 RTL_W16(IntrMask
, tp
->intr_event
);
4512 static void rtl_csi_access_enable(void __iomem
*ioaddr
, u32 bits
)
4516 csi
= rtl_csi_read(ioaddr
, 0x070c) & 0x00ffffff;
4517 rtl_csi_write(ioaddr
, 0x070c, csi
| bits
);
4520 static void rtl_csi_access_enable_1(void __iomem
*ioaddr
)
4522 rtl_csi_access_enable(ioaddr
, 0x17000000);
4525 static void rtl_csi_access_enable_2(void __iomem
*ioaddr
)
4527 rtl_csi_access_enable(ioaddr
, 0x27000000);
4531 unsigned int offset
;
4536 static void rtl_ephy_init(void __iomem
*ioaddr
, const struct ephy_info
*e
, int len
)
4541 w
= (rtl_ephy_read(ioaddr
, e
->offset
) & ~e
->mask
) | e
->bits
;
4542 rtl_ephy_write(ioaddr
, e
->offset
, w
);
4547 static void rtl_disable_clock_request(struct pci_dev
*pdev
)
4549 int cap
= pci_pcie_cap(pdev
);
4554 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
4555 ctl
&= ~PCI_EXP_LNKCTL_CLKREQ_EN
;
4556 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
4560 static void rtl_enable_clock_request(struct pci_dev
*pdev
)
4562 int cap
= pci_pcie_cap(pdev
);
4567 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
4568 ctl
|= PCI_EXP_LNKCTL_CLKREQ_EN
;
4569 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
4573 #define R8168_CPCMD_QUIRK_MASK (\
4584 static void rtl_hw_start_8168bb(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4586 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4588 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4590 rtl_tx_performance_tweak(pdev
,
4591 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
4594 static void rtl_hw_start_8168bef(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4596 rtl_hw_start_8168bb(ioaddr
, pdev
);
4598 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4600 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
4603 static void __rtl_hw_start_8168cp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4605 RTL_W8(Config1
, RTL_R8(Config1
) | Speed_down
);
4607 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4609 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4611 rtl_disable_clock_request(pdev
);
4613 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4616 static void rtl_hw_start_8168cp_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4618 static const struct ephy_info e_info_8168cp
[] = {
4619 { 0x01, 0, 0x0001 },
4620 { 0x02, 0x0800, 0x1000 },
4621 { 0x03, 0, 0x0042 },
4622 { 0x06, 0x0080, 0x0000 },
4626 rtl_csi_access_enable_2(ioaddr
);
4628 rtl_ephy_init(ioaddr
, e_info_8168cp
, ARRAY_SIZE(e_info_8168cp
));
4630 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4633 static void rtl_hw_start_8168cp_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4635 rtl_csi_access_enable_2(ioaddr
);
4637 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4639 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4641 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4644 static void rtl_hw_start_8168cp_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4646 rtl_csi_access_enable_2(ioaddr
);
4648 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4651 RTL_W8(DBG_REG
, 0x20);
4653 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4655 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4657 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4660 static void rtl_hw_start_8168c_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4662 static const struct ephy_info e_info_8168c_1
[] = {
4663 { 0x02, 0x0800, 0x1000 },
4664 { 0x03, 0, 0x0002 },
4665 { 0x06, 0x0080, 0x0000 }
4668 rtl_csi_access_enable_2(ioaddr
);
4670 RTL_W8(DBG_REG
, 0x06 | FIX_NAK_1
| FIX_NAK_2
);
4672 rtl_ephy_init(ioaddr
, e_info_8168c_1
, ARRAY_SIZE(e_info_8168c_1
));
4674 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4677 static void rtl_hw_start_8168c_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4679 static const struct ephy_info e_info_8168c_2
[] = {
4680 { 0x01, 0, 0x0001 },
4681 { 0x03, 0x0400, 0x0220 }
4684 rtl_csi_access_enable_2(ioaddr
);
4686 rtl_ephy_init(ioaddr
, e_info_8168c_2
, ARRAY_SIZE(e_info_8168c_2
));
4688 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4691 static void rtl_hw_start_8168c_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4693 rtl_hw_start_8168c_2(ioaddr
, pdev
);
4696 static void rtl_hw_start_8168c_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4698 rtl_csi_access_enable_2(ioaddr
);
4700 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4703 static void rtl_hw_start_8168d(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4705 rtl_csi_access_enable_2(ioaddr
);
4707 rtl_disable_clock_request(pdev
);
4709 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4711 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4713 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4716 static void rtl_hw_start_8168dp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4718 rtl_csi_access_enable_1(ioaddr
);
4720 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4722 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4724 rtl_disable_clock_request(pdev
);
4727 static void rtl_hw_start_8168d_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4729 static const struct ephy_info e_info_8168d_4
[] = {
4731 { 0x19, 0x20, 0x50 },
4736 rtl_csi_access_enable_1(ioaddr
);
4738 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4740 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4742 for (i
= 0; i
< ARRAY_SIZE(e_info_8168d_4
); i
++) {
4743 const struct ephy_info
*e
= e_info_8168d_4
+ i
;
4746 w
= rtl_ephy_read(ioaddr
, e
->offset
);
4747 rtl_ephy_write(ioaddr
, 0x03, (w
& e
->mask
) | e
->bits
);
4750 rtl_enable_clock_request(pdev
);
4753 static void rtl_hw_start_8168e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4755 static const struct ephy_info e_info_8168e_1
[] = {
4756 { 0x00, 0x0200, 0x0100 },
4757 { 0x00, 0x0000, 0x0004 },
4758 { 0x06, 0x0002, 0x0001 },
4759 { 0x06, 0x0000, 0x0030 },
4760 { 0x07, 0x0000, 0x2000 },
4761 { 0x00, 0x0000, 0x0020 },
4762 { 0x03, 0x5800, 0x2000 },
4763 { 0x03, 0x0000, 0x0001 },
4764 { 0x01, 0x0800, 0x1000 },
4765 { 0x07, 0x0000, 0x4000 },
4766 { 0x1e, 0x0000, 0x2000 },
4767 { 0x19, 0xffff, 0xfe6c },
4768 { 0x0a, 0x0000, 0x0040 }
4771 rtl_csi_access_enable_2(ioaddr
);
4773 rtl_ephy_init(ioaddr
, e_info_8168e_1
, ARRAY_SIZE(e_info_8168e_1
));
4775 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4777 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4779 rtl_disable_clock_request(pdev
);
4781 /* Reset tx FIFO pointer */
4782 RTL_W32(MISC
, RTL_R32(MISC
) | TXPLA_RST
);
4783 RTL_W32(MISC
, RTL_R32(MISC
) & ~TXPLA_RST
);
4785 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
4788 static void rtl_hw_start_8168e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4790 static const struct ephy_info e_info_8168e_2
[] = {
4791 { 0x09, 0x0000, 0x0080 },
4792 { 0x19, 0x0000, 0x0224 }
4795 rtl_csi_access_enable_1(ioaddr
);
4797 rtl_ephy_init(ioaddr
, e_info_8168e_2
, ARRAY_SIZE(e_info_8168e_2
));
4799 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4801 rtl_eri_write(ioaddr
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4802 rtl_eri_write(ioaddr
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4803 rtl_eri_write(ioaddr
, 0xc8, ERIAR_MASK_1111
, 0x00100002, ERIAR_EXGMAC
);
4804 rtl_eri_write(ioaddr
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
4805 rtl_eri_write(ioaddr
, 0xcc, ERIAR_MASK_1111
, 0x00000050, ERIAR_EXGMAC
);
4806 rtl_eri_write(ioaddr
, 0xd0, ERIAR_MASK_1111
, 0x07ff0060, ERIAR_EXGMAC
);
4807 rtl_w1w0_eri(ioaddr
, 0x1b0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
4808 rtl_w1w0_eri(ioaddr
, 0x0d4, ERIAR_MASK_0011
, 0x0c00, 0xff00,
4811 RTL_W8(MaxTxPacketSize
, EarlySize
);
4813 rtl_disable_clock_request(pdev
);
4815 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
4816 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
4818 /* Adjust EEE LED frequency */
4819 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
4821 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
4822 RTL_W32(MISC
, RTL_R32(MISC
) | PWM_EN
);
4823 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
4826 static void rtl_hw_start_8168f_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4828 static const struct ephy_info e_info_8168f_1
[] = {
4829 { 0x06, 0x00c0, 0x0020 },
4830 { 0x08, 0x0001, 0x0002 },
4831 { 0x09, 0x0000, 0x0080 },
4832 { 0x19, 0x0000, 0x0224 }
4835 rtl_csi_access_enable_1(ioaddr
);
4837 rtl_ephy_init(ioaddr
, e_info_8168f_1
, ARRAY_SIZE(e_info_8168f_1
));
4839 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4841 rtl_eri_write(ioaddr
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4842 rtl_eri_write(ioaddr
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4843 rtl_eri_write(ioaddr
, 0xc8, ERIAR_MASK_1111
, 0x00100002, ERIAR_EXGMAC
);
4844 rtl_eri_write(ioaddr
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
4845 rtl_w1w0_eri(ioaddr
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01, ERIAR_EXGMAC
);
4846 rtl_w1w0_eri(ioaddr
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00, ERIAR_EXGMAC
);
4847 rtl_w1w0_eri(ioaddr
, 0x1b0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
4848 rtl_w1w0_eri(ioaddr
, 0x1d0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
4849 rtl_eri_write(ioaddr
, 0xcc, ERIAR_MASK_1111
, 0x00000050, ERIAR_EXGMAC
);
4850 rtl_eri_write(ioaddr
, 0xd0, ERIAR_MASK_1111
, 0x00000060, ERIAR_EXGMAC
);
4851 rtl_w1w0_eri(ioaddr
, 0x0d4, ERIAR_MASK_0011
, 0x0c00, 0xff00,
4854 RTL_W8(MaxTxPacketSize
, EarlySize
);
4856 rtl_disable_clock_request(pdev
);
4858 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
4859 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
4861 /* Adjust EEE LED frequency */
4862 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
4864 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
4865 RTL_W32(MISC
, RTL_R32(MISC
) | PWM_EN
);
4866 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
4869 static void rtl_hw_start_8168(struct net_device
*dev
)
4871 struct rtl8169_private
*tp
= netdev_priv(dev
);
4872 void __iomem
*ioaddr
= tp
->mmio_addr
;
4873 struct pci_dev
*pdev
= tp
->pci_dev
;
4875 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4877 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4879 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
4881 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
4883 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4885 RTL_W16(IntrMitigate
, 0x5151);
4887 /* Work around for RxFIFO overflow. */
4888 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
) {
4889 tp
->intr_event
|= RxFIFOOver
| PCSTimeout
;
4890 tp
->intr_event
&= ~RxOverflow
;
4893 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
4895 rtl_set_rx_mode(dev
);
4897 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
4898 (InterFrameGap
<< TxInterFrameGapShift
));
4902 switch (tp
->mac_version
) {
4903 case RTL_GIGA_MAC_VER_11
:
4904 rtl_hw_start_8168bb(ioaddr
, pdev
);
4907 case RTL_GIGA_MAC_VER_12
:
4908 case RTL_GIGA_MAC_VER_17
:
4909 rtl_hw_start_8168bef(ioaddr
, pdev
);
4912 case RTL_GIGA_MAC_VER_18
:
4913 rtl_hw_start_8168cp_1(ioaddr
, pdev
);
4916 case RTL_GIGA_MAC_VER_19
:
4917 rtl_hw_start_8168c_1(ioaddr
, pdev
);
4920 case RTL_GIGA_MAC_VER_20
:
4921 rtl_hw_start_8168c_2(ioaddr
, pdev
);
4924 case RTL_GIGA_MAC_VER_21
:
4925 rtl_hw_start_8168c_3(ioaddr
, pdev
);
4928 case RTL_GIGA_MAC_VER_22
:
4929 rtl_hw_start_8168c_4(ioaddr
, pdev
);
4932 case RTL_GIGA_MAC_VER_23
:
4933 rtl_hw_start_8168cp_2(ioaddr
, pdev
);
4936 case RTL_GIGA_MAC_VER_24
:
4937 rtl_hw_start_8168cp_3(ioaddr
, pdev
);
4940 case RTL_GIGA_MAC_VER_25
:
4941 case RTL_GIGA_MAC_VER_26
:
4942 case RTL_GIGA_MAC_VER_27
:
4943 rtl_hw_start_8168d(ioaddr
, pdev
);
4946 case RTL_GIGA_MAC_VER_28
:
4947 rtl_hw_start_8168d_4(ioaddr
, pdev
);
4950 case RTL_GIGA_MAC_VER_31
:
4951 rtl_hw_start_8168dp(ioaddr
, pdev
);
4954 case RTL_GIGA_MAC_VER_32
:
4955 case RTL_GIGA_MAC_VER_33
:
4956 rtl_hw_start_8168e_1(ioaddr
, pdev
);
4958 case RTL_GIGA_MAC_VER_34
:
4959 rtl_hw_start_8168e_2(ioaddr
, pdev
);
4962 case RTL_GIGA_MAC_VER_35
:
4963 case RTL_GIGA_MAC_VER_36
:
4964 rtl_hw_start_8168f_1(ioaddr
, pdev
);
4968 printk(KERN_ERR PFX
"%s: unknown chipset (mac_version = %d).\n",
4969 dev
->name
, tp
->mac_version
);
4973 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4975 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4977 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
4979 RTL_W16(IntrMask
, tp
->intr_event
);
4982 #define R810X_CPCMD_QUIRK_MASK (\
4993 static void rtl_hw_start_8102e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4995 static const struct ephy_info e_info_8102e_1
[] = {
4996 { 0x01, 0, 0x6e65 },
4997 { 0x02, 0, 0x091f },
4998 { 0x03, 0, 0xc2f9 },
4999 { 0x06, 0, 0xafb5 },
5000 { 0x07, 0, 0x0e00 },
5001 { 0x19, 0, 0xec80 },
5002 { 0x01, 0, 0x2e65 },
5007 rtl_csi_access_enable_2(ioaddr
);
5009 RTL_W8(DBG_REG
, FIX_NAK_1
);
5011 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5014 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
5015 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
5017 cfg1
= RTL_R8(Config1
);
5018 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
5019 RTL_W8(Config1
, cfg1
& ~LEDS0
);
5021 rtl_ephy_init(ioaddr
, e_info_8102e_1
, ARRAY_SIZE(e_info_8102e_1
));
5024 static void rtl_hw_start_8102e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
5026 rtl_csi_access_enable_2(ioaddr
);
5028 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5030 RTL_W8(Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
5031 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
5034 static void rtl_hw_start_8102e_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
5036 rtl_hw_start_8102e_2(ioaddr
, pdev
);
5038 rtl_ephy_write(ioaddr
, 0x03, 0xc2f9);
5041 static void rtl_hw_start_8105e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
5043 static const struct ephy_info e_info_8105e_1
[] = {
5044 { 0x07, 0, 0x4000 },
5045 { 0x19, 0, 0x0200 },
5046 { 0x19, 0, 0x0020 },
5047 { 0x1e, 0, 0x2000 },
5048 { 0x03, 0, 0x0001 },
5049 { 0x19, 0, 0x0100 },
5050 { 0x19, 0, 0x0004 },
5054 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5055 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) | 0x002800);
5057 /* Disable Early Tally Counter */
5058 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) & ~0x010000);
5060 RTL_W8(MCU
, RTL_R8(MCU
) | EN_NDP
| EN_OOB_RESET
);
5061 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
5063 rtl_ephy_init(ioaddr
, e_info_8105e_1
, ARRAY_SIZE(e_info_8105e_1
));
5066 static void rtl_hw_start_8105e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
5068 rtl_hw_start_8105e_1(ioaddr
, pdev
);
5069 rtl_ephy_write(ioaddr
, 0x1e, rtl_ephy_read(ioaddr
, 0x1e) | 0x8000);
5072 static void rtl_hw_start_8101(struct net_device
*dev
)
5074 struct rtl8169_private
*tp
= netdev_priv(dev
);
5075 void __iomem
*ioaddr
= tp
->mmio_addr
;
5076 struct pci_dev
*pdev
= tp
->pci_dev
;
5078 if (tp
->mac_version
>= RTL_GIGA_MAC_VER_30
) {
5079 tp
->intr_event
&= ~RxFIFOOver
;
5080 tp
->napi_event
&= ~RxFIFOOver
;
5083 if (tp
->mac_version
== RTL_GIGA_MAC_VER_13
||
5084 tp
->mac_version
== RTL_GIGA_MAC_VER_16
) {
5085 int cap
= pci_pcie_cap(pdev
);
5088 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
,
5089 PCI_EXP_DEVCTL_NOSNOOP_EN
);
5093 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
5095 switch (tp
->mac_version
) {
5096 case RTL_GIGA_MAC_VER_07
:
5097 rtl_hw_start_8102e_1(ioaddr
, pdev
);
5100 case RTL_GIGA_MAC_VER_08
:
5101 rtl_hw_start_8102e_3(ioaddr
, pdev
);
5104 case RTL_GIGA_MAC_VER_09
:
5105 rtl_hw_start_8102e_2(ioaddr
, pdev
);
5108 case RTL_GIGA_MAC_VER_29
:
5109 rtl_hw_start_8105e_1(ioaddr
, pdev
);
5111 case RTL_GIGA_MAC_VER_30
:
5112 rtl_hw_start_8105e_2(ioaddr
, pdev
);
5116 RTL_W8(Cfg9346
, Cfg9346_Lock
);
5118 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
5120 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
5122 tp
->cp_cmd
&= ~R810X_CPCMD_QUIRK_MASK
;
5123 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
5125 RTL_W16(IntrMitigate
, 0x0000);
5127 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
5129 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
5130 rtl_set_rx_tx_config_registers(tp
);
5134 rtl_set_rx_mode(dev
);
5136 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
5138 RTL_W16(IntrMask
, tp
->intr_event
);
5141 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
5143 struct rtl8169_private
*tp
= netdev_priv(dev
);
5145 if (new_mtu
< ETH_ZLEN
||
5146 new_mtu
> rtl_chip_infos
[tp
->mac_version
].jumbo_max
)
5149 if (new_mtu
> ETH_DATA_LEN
)
5150 rtl_hw_jumbo_enable(tp
);
5152 rtl_hw_jumbo_disable(tp
);
5155 netdev_update_features(dev
);
5160 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
5162 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
5163 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
5166 static void rtl8169_free_rx_databuff(struct rtl8169_private
*tp
,
5167 void **data_buff
, struct RxDesc
*desc
)
5169 dma_unmap_single(&tp
->pci_dev
->dev
, le64_to_cpu(desc
->addr
), rx_buf_sz
,
5174 rtl8169_make_unusable_by_asic(desc
);
5177 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
5179 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
5181 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
5184 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
5187 desc
->addr
= cpu_to_le64(mapping
);
5189 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5192 static inline void *rtl8169_align(void *data
)
5194 return (void *)ALIGN((long)data
, 16);
5197 static struct sk_buff
*rtl8169_alloc_rx_data(struct rtl8169_private
*tp
,
5198 struct RxDesc
*desc
)
5202 struct device
*d
= &tp
->pci_dev
->dev
;
5203 struct net_device
*dev
= tp
->dev
;
5204 int node
= dev
->dev
.parent
? dev_to_node(dev
->dev
.parent
) : -1;
5206 data
= kmalloc_node(rx_buf_sz
, GFP_KERNEL
, node
);
5210 if (rtl8169_align(data
) != data
) {
5212 data
= kmalloc_node(rx_buf_sz
+ 15, GFP_KERNEL
, node
);
5217 mapping
= dma_map_single(d
, rtl8169_align(data
), rx_buf_sz
,
5219 if (unlikely(dma_mapping_error(d
, mapping
))) {
5220 if (net_ratelimit())
5221 netif_err(tp
, drv
, tp
->dev
, "Failed to map RX DMA!\n");
5225 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
5233 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
5237 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
5238 if (tp
->Rx_databuff
[i
]) {
5239 rtl8169_free_rx_databuff(tp
, tp
->Rx_databuff
+ i
,
5240 tp
->RxDescArray
+ i
);
5245 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
5247 desc
->opts1
|= cpu_to_le32(RingEnd
);
5250 static int rtl8169_rx_fill(struct rtl8169_private
*tp
)
5254 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
5257 if (tp
->Rx_databuff
[i
])
5260 data
= rtl8169_alloc_rx_data(tp
, tp
->RxDescArray
+ i
);
5262 rtl8169_make_unusable_by_asic(tp
->RxDescArray
+ i
);
5265 tp
->Rx_databuff
[i
] = data
;
5268 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
5272 rtl8169_rx_clear(tp
);
5276 static int rtl8169_init_ring(struct net_device
*dev
)
5278 struct rtl8169_private
*tp
= netdev_priv(dev
);
5280 rtl8169_init_ring_indexes(tp
);
5282 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
5283 memset(tp
->Rx_databuff
, 0x0, NUM_RX_DESC
* sizeof(void *));
5285 return rtl8169_rx_fill(tp
);
5288 static void rtl8169_unmap_tx_skb(struct device
*d
, struct ring_info
*tx_skb
,
5289 struct TxDesc
*desc
)
5291 unsigned int len
= tx_skb
->len
;
5293 dma_unmap_single(d
, le64_to_cpu(desc
->addr
), len
, DMA_TO_DEVICE
);
5301 static void rtl8169_tx_clear_range(struct rtl8169_private
*tp
, u32 start
,
5306 for (i
= 0; i
< n
; i
++) {
5307 unsigned int entry
= (start
+ i
) % NUM_TX_DESC
;
5308 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
5309 unsigned int len
= tx_skb
->len
;
5312 struct sk_buff
*skb
= tx_skb
->skb
;
5314 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
5315 tp
->TxDescArray
+ entry
);
5317 tp
->dev
->stats
.tx_dropped
++;
5325 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
5327 rtl8169_tx_clear_range(tp
, tp
->dirty_tx
, NUM_TX_DESC
);
5328 tp
->cur_tx
= tp
->dirty_tx
= 0;
5331 static void rtl8169_schedule_work(struct net_device
*dev
, work_func_t task
)
5333 struct rtl8169_private
*tp
= netdev_priv(dev
);
5335 PREPARE_DELAYED_WORK(&tp
->task
, task
);
5336 schedule_delayed_work(&tp
->task
, 4);
5339 static void rtl8169_wait_for_quiescence(struct net_device
*dev
)
5341 struct rtl8169_private
*tp
= netdev_priv(dev
);
5342 void __iomem
*ioaddr
= tp
->mmio_addr
;
5344 synchronize_irq(dev
->irq
);
5346 /* Wait for any pending NAPI task to complete */
5347 napi_disable(&tp
->napi
);
5349 rtl8169_irq_mask_and_ack(tp
);
5351 tp
->intr_mask
= 0xffff;
5352 RTL_W16(IntrMask
, tp
->intr_event
);
5353 napi_enable(&tp
->napi
);
5356 static void rtl8169_reinit_task(struct work_struct
*work
)
5358 struct rtl8169_private
*tp
=
5359 container_of(work
, struct rtl8169_private
, task
.work
);
5360 struct net_device
*dev
= tp
->dev
;
5365 if (!netif_running(dev
))
5368 rtl8169_wait_for_quiescence(dev
);
5371 ret
= rtl8169_open(dev
);
5372 if (unlikely(ret
< 0)) {
5373 if (net_ratelimit())
5374 netif_err(tp
, drv
, dev
,
5375 "reinit failure (status = %d). Rescheduling\n",
5377 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
5384 static void rtl8169_reset_task(struct work_struct
*work
)
5386 struct rtl8169_private
*tp
=
5387 container_of(work
, struct rtl8169_private
, task
.work
);
5388 struct net_device
*dev
= tp
->dev
;
5393 if (!netif_running(dev
))
5396 rtl8169_hw_reset(tp
);
5398 rtl8169_wait_for_quiescence(dev
);
5400 for (i
= 0; i
< NUM_RX_DESC
; i
++)
5401 rtl8169_mark_to_asic(tp
->RxDescArray
+ i
, rx_buf_sz
);
5403 rtl8169_tx_clear(tp
);
5404 rtl8169_init_ring_indexes(tp
);
5407 netif_wake_queue(dev
);
5408 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
5414 static void rtl8169_tx_timeout(struct net_device
*dev
)
5416 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
5419 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
5422 struct skb_shared_info
*info
= skb_shinfo(skb
);
5423 unsigned int cur_frag
, entry
;
5424 struct TxDesc
* uninitialized_var(txd
);
5425 struct device
*d
= &tp
->pci_dev
->dev
;
5428 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
5429 const skb_frag_t
*frag
= info
->frags
+ cur_frag
;
5434 entry
= (entry
+ 1) % NUM_TX_DESC
;
5436 txd
= tp
->TxDescArray
+ entry
;
5437 len
= skb_frag_size(frag
);
5438 addr
= skb_frag_address(frag
);
5439 mapping
= dma_map_single(d
, addr
, len
, DMA_TO_DEVICE
);
5440 if (unlikely(dma_mapping_error(d
, mapping
))) {
5441 if (net_ratelimit())
5442 netif_err(tp
, drv
, tp
->dev
,
5443 "Failed to map TX fragments DMA!\n");
5447 /* Anti gcc 2.95.3 bugware (sic) */
5448 status
= opts
[0] | len
|
5449 (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
5451 txd
->opts1
= cpu_to_le32(status
);
5452 txd
->opts2
= cpu_to_le32(opts
[1]);
5453 txd
->addr
= cpu_to_le64(mapping
);
5455 tp
->tx_skb
[entry
].len
= len
;
5459 tp
->tx_skb
[entry
].skb
= skb
;
5460 txd
->opts1
|= cpu_to_le32(LastFrag
);
5466 rtl8169_tx_clear_range(tp
, tp
->cur_tx
+ 1, cur_frag
);
5470 static inline void rtl8169_tso_csum(struct rtl8169_private
*tp
,
5471 struct sk_buff
*skb
, u32
*opts
)
5473 const struct rtl_tx_desc_info
*info
= tx_desc_info
+ tp
->txd_version
;
5474 u32 mss
= skb_shinfo(skb
)->gso_size
;
5475 int offset
= info
->opts_offset
;
5479 opts
[offset
] |= min(mss
, TD_MSS_MAX
) << info
->mss_shift
;
5480 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5481 const struct iphdr
*ip
= ip_hdr(skb
);
5483 if (ip
->protocol
== IPPROTO_TCP
)
5484 opts
[offset
] |= info
->checksum
.tcp
;
5485 else if (ip
->protocol
== IPPROTO_UDP
)
5486 opts
[offset
] |= info
->checksum
.udp
;
5492 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
5493 struct net_device
*dev
)
5495 struct rtl8169_private
*tp
= netdev_priv(dev
);
5496 unsigned int entry
= tp
->cur_tx
% NUM_TX_DESC
;
5497 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
5498 void __iomem
*ioaddr
= tp
->mmio_addr
;
5499 struct device
*d
= &tp
->pci_dev
->dev
;
5505 if (unlikely(TX_BUFFS_AVAIL(tp
) < skb_shinfo(skb
)->nr_frags
)) {
5506 netif_err(tp
, drv
, dev
, "BUG! Tx Ring full when queue awake!\n");
5510 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
5513 len
= skb_headlen(skb
);
5514 mapping
= dma_map_single(d
, skb
->data
, len
, DMA_TO_DEVICE
);
5515 if (unlikely(dma_mapping_error(d
, mapping
))) {
5516 if (net_ratelimit())
5517 netif_err(tp
, drv
, dev
, "Failed to map TX DMA!\n");
5521 tp
->tx_skb
[entry
].len
= len
;
5522 txd
->addr
= cpu_to_le64(mapping
);
5524 opts
[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp
, skb
));
5527 rtl8169_tso_csum(tp
, skb
, opts
);
5529 frags
= rtl8169_xmit_frags(tp
, skb
, opts
);
5533 opts
[0] |= FirstFrag
;
5535 opts
[0] |= FirstFrag
| LastFrag
;
5536 tp
->tx_skb
[entry
].skb
= skb
;
5539 txd
->opts2
= cpu_to_le32(opts
[1]);
5543 /* Anti gcc 2.95.3 bugware (sic) */
5544 status
= opts
[0] | len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
5545 txd
->opts1
= cpu_to_le32(status
);
5547 tp
->cur_tx
+= frags
+ 1;
5551 RTL_W8(TxPoll
, NPQ
);
5553 if (TX_BUFFS_AVAIL(tp
) < MAX_SKB_FRAGS
) {
5554 netif_stop_queue(dev
);
5556 if (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)
5557 netif_wake_queue(dev
);
5560 return NETDEV_TX_OK
;
5563 rtl8169_unmap_tx_skb(d
, tp
->tx_skb
+ entry
, txd
);
5566 dev
->stats
.tx_dropped
++;
5567 return NETDEV_TX_OK
;
5570 netif_stop_queue(dev
);
5571 dev
->stats
.tx_dropped
++;
5572 return NETDEV_TX_BUSY
;
5575 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
5577 struct rtl8169_private
*tp
= netdev_priv(dev
);
5578 struct pci_dev
*pdev
= tp
->pci_dev
;
5579 u16 pci_status
, pci_cmd
;
5581 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
5582 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
5584 netif_err(tp
, intr
, dev
, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5585 pci_cmd
, pci_status
);
5588 * The recovery sequence below admits a very elaborated explanation:
5589 * - it seems to work;
5590 * - I did not see what else could be done;
5591 * - it makes iop3xx happy.
5593 * Feel free to adjust to your needs.
5595 if (pdev
->broken_parity_status
)
5596 pci_cmd
&= ~PCI_COMMAND_PARITY
;
5598 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
5600 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
5602 pci_write_config_word(pdev
, PCI_STATUS
,
5603 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
5604 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
5605 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
5607 /* The infamous DAC f*ckup only happens at boot time */
5608 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->dirty_rx
&& !tp
->cur_rx
) {
5609 void __iomem
*ioaddr
= tp
->mmio_addr
;
5611 netif_info(tp
, intr
, dev
, "disabling PCI DAC\n");
5612 tp
->cp_cmd
&= ~PCIDAC
;
5613 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
5614 dev
->features
&= ~NETIF_F_HIGHDMA
;
5617 rtl8169_hw_reset(tp
);
5619 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
5622 static void rtl8169_tx_interrupt(struct net_device
*dev
,
5623 struct rtl8169_private
*tp
,
5624 void __iomem
*ioaddr
)
5626 unsigned int dirty_tx
, tx_left
;
5628 dirty_tx
= tp
->dirty_tx
;
5630 tx_left
= tp
->cur_tx
- dirty_tx
;
5632 while (tx_left
> 0) {
5633 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
5634 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
5638 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
5639 if (status
& DescOwn
)
5642 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
5643 tp
->TxDescArray
+ entry
);
5644 if (status
& LastFrag
) {
5645 dev
->stats
.tx_packets
++;
5646 dev
->stats
.tx_bytes
+= tx_skb
->skb
->len
;
5647 dev_kfree_skb(tx_skb
->skb
);
5654 if (tp
->dirty_tx
!= dirty_tx
) {
5655 tp
->dirty_tx
= dirty_tx
;
5657 if (netif_queue_stopped(dev
) &&
5658 (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)) {
5659 netif_wake_queue(dev
);
5662 * 8168 hack: TxPoll requests are lost when the Tx packets are
5663 * too close. Let's kick an extra TxPoll request when a burst
5664 * of start_xmit activity is detected (if it is not detected,
5665 * it is slow enough). -- FR
5668 if (tp
->cur_tx
!= dirty_tx
)
5669 RTL_W8(TxPoll
, NPQ
);
5673 static inline int rtl8169_fragmented_frame(u32 status
)
5675 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
5678 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, u32 opts1
)
5680 u32 status
= opts1
& RxProtoMask
;
5682 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
5683 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)))
5684 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
5686 skb_checksum_none_assert(skb
);
5689 static struct sk_buff
*rtl8169_try_rx_copy(void *data
,
5690 struct rtl8169_private
*tp
,
5694 struct sk_buff
*skb
;
5695 struct device
*d
= &tp
->pci_dev
->dev
;
5697 data
= rtl8169_align(data
);
5698 dma_sync_single_for_cpu(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
5700 skb
= netdev_alloc_skb_ip_align(tp
->dev
, pkt_size
);
5702 memcpy(skb
->data
, data
, pkt_size
);
5703 dma_sync_single_for_device(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
5708 static int rtl8169_rx_interrupt(struct net_device
*dev
,
5709 struct rtl8169_private
*tp
,
5710 void __iomem
*ioaddr
, u32 budget
)
5712 unsigned int cur_rx
, rx_left
;
5715 cur_rx
= tp
->cur_rx
;
5716 rx_left
= NUM_RX_DESC
+ tp
->dirty_rx
- cur_rx
;
5717 rx_left
= min(rx_left
, budget
);
5719 for (; rx_left
> 0; rx_left
--, cur_rx
++) {
5720 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
5721 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
5725 status
= le32_to_cpu(desc
->opts1
) & tp
->opts1_mask
;
5727 if (status
& DescOwn
)
5729 if (unlikely(status
& RxRES
)) {
5730 netif_info(tp
, rx_err
, dev
, "Rx ERROR. status = %08x\n",
5732 dev
->stats
.rx_errors
++;
5733 if (status
& (RxRWT
| RxRUNT
))
5734 dev
->stats
.rx_length_errors
++;
5736 dev
->stats
.rx_crc_errors
++;
5737 if (status
& RxFOVF
) {
5738 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
5739 dev
->stats
.rx_fifo_errors
++;
5741 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5743 struct sk_buff
*skb
;
5744 dma_addr_t addr
= le64_to_cpu(desc
->addr
);
5745 int pkt_size
= (status
& 0x00003fff) - 4;
5748 * The driver does not support incoming fragmented
5749 * frames. They are seen as a symptom of over-mtu
5752 if (unlikely(rtl8169_fragmented_frame(status
))) {
5753 dev
->stats
.rx_dropped
++;
5754 dev
->stats
.rx_length_errors
++;
5755 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5759 skb
= rtl8169_try_rx_copy(tp
->Rx_databuff
[entry
],
5760 tp
, pkt_size
, addr
);
5761 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5763 dev
->stats
.rx_dropped
++;
5767 rtl8169_rx_csum(skb
, status
);
5768 skb_put(skb
, pkt_size
);
5769 skb
->protocol
= eth_type_trans(skb
, dev
);
5771 rtl8169_rx_vlan_tag(desc
, skb
);
5773 napi_gro_receive(&tp
->napi
, skb
);
5775 dev
->stats
.rx_bytes
+= pkt_size
;
5776 dev
->stats
.rx_packets
++;
5779 /* Work around for AMD plateform. */
5780 if ((desc
->opts2
& cpu_to_le32(0xfffe000)) &&
5781 (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)) {
5787 count
= cur_rx
- tp
->cur_rx
;
5788 tp
->cur_rx
= cur_rx
;
5790 tp
->dirty_rx
+= count
;
5795 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
5797 struct net_device
*dev
= dev_instance
;
5798 struct rtl8169_private
*tp
= netdev_priv(dev
);
5799 void __iomem
*ioaddr
= tp
->mmio_addr
;
5803 /* loop handling interrupts until we have no new ones or
5804 * we hit a invalid/hotplug case.
5806 status
= RTL_R16(IntrStatus
);
5807 while (status
&& status
!= 0xffff) {
5808 status
&= tp
->intr_event
;
5814 /* Handle all of the error cases first. These will reset
5815 * the chip, so just exit the loop.
5817 if (unlikely(!netif_running(dev
))) {
5818 rtl8169_hw_reset(tp
);
5822 if (unlikely(status
& RxFIFOOver
)) {
5823 switch (tp
->mac_version
) {
5824 /* Work around for rx fifo overflow */
5825 case RTL_GIGA_MAC_VER_11
:
5826 netif_stop_queue(dev
);
5827 rtl8169_tx_timeout(dev
);
5834 if (unlikely(status
& SYSErr
)) {
5835 rtl8169_pcierr_interrupt(dev
);
5839 if (status
& LinkChg
)
5840 __rtl8169_check_link_status(dev
, tp
, ioaddr
, true);
5842 /* We need to see the lastest version of tp->intr_mask to
5843 * avoid ignoring an MSI interrupt and having to wait for
5844 * another event which may never come.
5847 if (status
& tp
->intr_mask
& tp
->napi_event
) {
5848 RTL_W16(IntrMask
, tp
->intr_event
& ~tp
->napi_event
);
5849 tp
->intr_mask
= ~tp
->napi_event
;
5851 if (likely(napi_schedule_prep(&tp
->napi
)))
5852 __napi_schedule(&tp
->napi
);
5854 netif_info(tp
, intr
, dev
,
5855 "interrupt %04x in poll\n", status
);
5858 /* We only get a new MSI interrupt when all active irq
5859 * sources on the chip have been acknowledged. So, ack
5860 * everything we've seen and check if new sources have become
5861 * active to avoid blocking all interrupts from the chip.
5864 (status
& RxFIFOOver
) ? (status
| RxOverflow
) : status
);
5865 status
= RTL_R16(IntrStatus
);
5868 return IRQ_RETVAL(handled
);
5871 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
5873 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
5874 struct net_device
*dev
= tp
->dev
;
5875 void __iomem
*ioaddr
= tp
->mmio_addr
;
5878 work_done
= rtl8169_rx_interrupt(dev
, tp
, ioaddr
, (u32
) budget
);
5879 rtl8169_tx_interrupt(dev
, tp
, ioaddr
);
5881 if (work_done
< budget
) {
5882 napi_complete(napi
);
5884 /* We need for force the visibility of tp->intr_mask
5885 * for other CPUs, as we can loose an MSI interrupt
5886 * and potentially wait for a retransmit timeout if we don't.
5887 * The posted write to IntrMask is safe, as it will
5888 * eventually make it to the chip and we won't loose anything
5891 tp
->intr_mask
= 0xffff;
5893 RTL_W16(IntrMask
, tp
->intr_event
);
5899 static void rtl8169_rx_missed(struct net_device
*dev
, void __iomem
*ioaddr
)
5901 struct rtl8169_private
*tp
= netdev_priv(dev
);
5903 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
5906 dev
->stats
.rx_missed_errors
+= (RTL_R32(RxMissed
) & 0xffffff);
5907 RTL_W32(RxMissed
, 0);
5910 static void rtl8169_down(struct net_device
*dev
)
5912 struct rtl8169_private
*tp
= netdev_priv(dev
);
5913 void __iomem
*ioaddr
= tp
->mmio_addr
;
5915 del_timer_sync(&tp
->timer
);
5917 netif_stop_queue(dev
);
5919 napi_disable(&tp
->napi
);
5921 spin_lock_irq(&tp
->lock
);
5923 rtl8169_hw_reset(tp
);
5925 * At this point device interrupts can not be enabled in any function,
5926 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5927 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5929 rtl8169_rx_missed(dev
, ioaddr
);
5931 spin_unlock_irq(&tp
->lock
);
5933 synchronize_irq(dev
->irq
);
5935 /* Give a racing hard_start_xmit a few cycles to complete. */
5936 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
5938 rtl8169_tx_clear(tp
);
5940 rtl8169_rx_clear(tp
);
5942 rtl_pll_power_down(tp
);
5945 static int rtl8169_close(struct net_device
*dev
)
5947 struct rtl8169_private
*tp
= netdev_priv(dev
);
5948 struct pci_dev
*pdev
= tp
->pci_dev
;
5950 pm_runtime_get_sync(&pdev
->dev
);
5952 /* Update counters before going down */
5953 rtl8169_update_counters(dev
);
5957 free_irq(dev
->irq
, dev
);
5959 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
5961 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
5963 tp
->TxDescArray
= NULL
;
5964 tp
->RxDescArray
= NULL
;
5966 pm_runtime_put_sync(&pdev
->dev
);
5971 static void rtl_set_rx_mode(struct net_device
*dev
)
5973 struct rtl8169_private
*tp
= netdev_priv(dev
);
5974 void __iomem
*ioaddr
= tp
->mmio_addr
;
5975 unsigned long flags
;
5976 u32 mc_filter
[2]; /* Multicast hash filter */
5980 if (dev
->flags
& IFF_PROMISC
) {
5981 /* Unconditionally log net taps. */
5982 netif_notice(tp
, link
, dev
, "Promiscuous mode enabled\n");
5984 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
5986 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
5987 } else if ((netdev_mc_count(dev
) > multicast_filter_limit
) ||
5988 (dev
->flags
& IFF_ALLMULTI
)) {
5989 /* Too many to filter perfectly -- accept all multicasts. */
5990 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
5991 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
5993 struct netdev_hw_addr
*ha
;
5995 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
5996 mc_filter
[1] = mc_filter
[0] = 0;
5997 netdev_for_each_mc_addr(ha
, dev
) {
5998 int bit_nr
= ether_crc(ETH_ALEN
, ha
->addr
) >> 26;
5999 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
6000 rx_mode
|= AcceptMulticast
;
6004 spin_lock_irqsave(&tp
->lock
, flags
);
6006 tmp
= (RTL_R32(RxConfig
) & ~RX_CONFIG_ACCEPT_MASK
) | rx_mode
;
6008 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
6009 u32 data
= mc_filter
[0];
6011 mc_filter
[0] = swab32(mc_filter
[1]);
6012 mc_filter
[1] = swab32(data
);
6015 RTL_W32(MAR0
+ 4, mc_filter
[1]);
6016 RTL_W32(MAR0
+ 0, mc_filter
[0]);
6018 RTL_W32(RxConfig
, tmp
);
6020 spin_unlock_irqrestore(&tp
->lock
, flags
);
6024 * rtl8169_get_stats - Get rtl8169 read/write statistics
6025 * @dev: The Ethernet Device to get statistics for
6027 * Get TX/RX statistics for rtl8169
6029 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
)
6031 struct rtl8169_private
*tp
= netdev_priv(dev
);
6032 void __iomem
*ioaddr
= tp
->mmio_addr
;
6033 unsigned long flags
;
6035 if (netif_running(dev
)) {
6036 spin_lock_irqsave(&tp
->lock
, flags
);
6037 rtl8169_rx_missed(dev
, ioaddr
);
6038 spin_unlock_irqrestore(&tp
->lock
, flags
);
6044 static void rtl8169_net_suspend(struct net_device
*dev
)
6046 struct rtl8169_private
*tp
= netdev_priv(dev
);
6048 if (!netif_running(dev
))
6051 rtl_pll_power_down(tp
);
6053 netif_device_detach(dev
);
6054 netif_stop_queue(dev
);
6059 static int rtl8169_suspend(struct device
*device
)
6061 struct pci_dev
*pdev
= to_pci_dev(device
);
6062 struct net_device
*dev
= pci_get_drvdata(pdev
);
6064 rtl8169_net_suspend(dev
);
6069 static void __rtl8169_resume(struct net_device
*dev
)
6071 struct rtl8169_private
*tp
= netdev_priv(dev
);
6073 netif_device_attach(dev
);
6075 rtl_pll_power_up(tp
);
6077 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
6080 static int rtl8169_resume(struct device
*device
)
6082 struct pci_dev
*pdev
= to_pci_dev(device
);
6083 struct net_device
*dev
= pci_get_drvdata(pdev
);
6084 struct rtl8169_private
*tp
= netdev_priv(dev
);
6086 rtl8169_init_phy(dev
, tp
);
6088 if (netif_running(dev
))
6089 __rtl8169_resume(dev
);
6094 static int rtl8169_runtime_suspend(struct device
*device
)
6096 struct pci_dev
*pdev
= to_pci_dev(device
);
6097 struct net_device
*dev
= pci_get_drvdata(pdev
);
6098 struct rtl8169_private
*tp
= netdev_priv(dev
);
6100 if (!tp
->TxDescArray
)
6103 spin_lock_irq(&tp
->lock
);
6104 tp
->saved_wolopts
= __rtl8169_get_wol(tp
);
6105 __rtl8169_set_wol(tp
, WAKE_ANY
);
6106 spin_unlock_irq(&tp
->lock
);
6108 rtl8169_net_suspend(dev
);
6113 static int rtl8169_runtime_resume(struct device
*device
)
6115 struct pci_dev
*pdev
= to_pci_dev(device
);
6116 struct net_device
*dev
= pci_get_drvdata(pdev
);
6117 struct rtl8169_private
*tp
= netdev_priv(dev
);
6119 if (!tp
->TxDescArray
)
6122 spin_lock_irq(&tp
->lock
);
6123 __rtl8169_set_wol(tp
, tp
->saved_wolopts
);
6124 tp
->saved_wolopts
= 0;
6125 spin_unlock_irq(&tp
->lock
);
6127 rtl8169_init_phy(dev
, tp
);
6129 __rtl8169_resume(dev
);
6134 static int rtl8169_runtime_idle(struct device
*device
)
6136 struct pci_dev
*pdev
= to_pci_dev(device
);
6137 struct net_device
*dev
= pci_get_drvdata(pdev
);
6138 struct rtl8169_private
*tp
= netdev_priv(dev
);
6140 return tp
->TxDescArray
? -EBUSY
: 0;
6143 static const struct dev_pm_ops rtl8169_pm_ops
= {
6144 .suspend
= rtl8169_suspend
,
6145 .resume
= rtl8169_resume
,
6146 .freeze
= rtl8169_suspend
,
6147 .thaw
= rtl8169_resume
,
6148 .poweroff
= rtl8169_suspend
,
6149 .restore
= rtl8169_resume
,
6150 .runtime_suspend
= rtl8169_runtime_suspend
,
6151 .runtime_resume
= rtl8169_runtime_resume
,
6152 .runtime_idle
= rtl8169_runtime_idle
,
6155 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
6157 #else /* !CONFIG_PM */
6159 #define RTL8169_PM_OPS NULL
6161 #endif /* !CONFIG_PM */
6163 static void rtl_wol_shutdown_quirk(struct rtl8169_private
*tp
)
6165 void __iomem
*ioaddr
= tp
->mmio_addr
;
6167 /* WoL fails with 8168b when the receiver is disabled. */
6168 switch (tp
->mac_version
) {
6169 case RTL_GIGA_MAC_VER_11
:
6170 case RTL_GIGA_MAC_VER_12
:
6171 case RTL_GIGA_MAC_VER_17
:
6172 pci_clear_master(tp
->pci_dev
);
6174 RTL_W8(ChipCmd
, CmdRxEnb
);
6183 static void rtl_shutdown(struct pci_dev
*pdev
)
6185 struct net_device
*dev
= pci_get_drvdata(pdev
);
6186 struct rtl8169_private
*tp
= netdev_priv(dev
);
6188 rtl8169_net_suspend(dev
);
6190 /* Restore original MAC address */
6191 rtl_rar_set(tp
, dev
->perm_addr
);
6193 spin_lock_irq(&tp
->lock
);
6195 rtl8169_hw_reset(tp
);
6197 spin_unlock_irq(&tp
->lock
);
6199 if (system_state
== SYSTEM_POWER_OFF
) {
6200 if (__rtl8169_get_wol(tp
) & WAKE_ANY
) {
6201 rtl_wol_suspend_quirk(tp
);
6202 rtl_wol_shutdown_quirk(tp
);
6205 pci_wake_from_d3(pdev
, true);
6206 pci_set_power_state(pdev
, PCI_D3hot
);
6210 static struct pci_driver rtl8169_pci_driver
= {
6212 .id_table
= rtl8169_pci_tbl
,
6213 .probe
= rtl8169_init_one
,
6214 .remove
= __devexit_p(rtl8169_remove_one
),
6215 .shutdown
= rtl_shutdown
,
6216 .driver
.pm
= RTL8169_PM_OPS
,
6219 static int __init
rtl8169_init_module(void)
6221 return pci_register_driver(&rtl8169_pci_driver
);
6224 static void __exit
rtl8169_cleanup_module(void)
6226 pci_unregister_driver(&rtl8169_pci_driver
);
6229 module_init(rtl8169_init_module
);
6230 module_exit(rtl8169_cleanup_module
);