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r8169: fix rtl_hw_jumbo_disable for RTL8168evl
[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / realtek / r8169_main.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 *
5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
7 * Copyright (c) a lot of people too. Please respect their work.
8 *
9 * See MAINTAINERS file for support contact information.
10 */
11
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/pci.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/ethtool.h>
20 #include <linux/phy.h>
21 #include <linux/if_vlan.h>
22 #include <linux/crc32.h>
23 #include <linux/in.h>
24 #include <linux/io.h>
25 #include <linux/ip.h>
26 #include <linux/tcp.h>
27 #include <linux/interrupt.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/prefetch.h>
31 #include <linux/ipv6.h>
32 #include <net/ip6_checksum.h>
33
34 #include "r8169_firmware.h"
35
36 #define MODULENAME "r8169"
37
38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
53 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
54 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
55 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
56 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
57 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw"
58
59 #define R8169_MSG_DEFAULT \
60 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
61
62 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
63 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
64 #define MC_FILTER_LIMIT 32
65
66 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
67 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
68
69 #define R8169_REGS_SIZE 256
70 #define R8169_RX_BUF_SIZE (SZ_16K - 1)
71 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
72 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
73 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
74 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
75
76 #define RTL_CFG_NO_GBIT 1
77
78 /* write/read MMIO register */
79 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
80 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
81 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
82 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
83 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
84 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
85
86 enum mac_version {
87 /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */
88 RTL_GIGA_MAC_VER_02,
89 RTL_GIGA_MAC_VER_03,
90 RTL_GIGA_MAC_VER_04,
91 RTL_GIGA_MAC_VER_05,
92 RTL_GIGA_MAC_VER_06,
93 RTL_GIGA_MAC_VER_07,
94 RTL_GIGA_MAC_VER_08,
95 RTL_GIGA_MAC_VER_09,
96 RTL_GIGA_MAC_VER_10,
97 RTL_GIGA_MAC_VER_11,
98 RTL_GIGA_MAC_VER_12,
99 RTL_GIGA_MAC_VER_13,
100 RTL_GIGA_MAC_VER_14,
101 RTL_GIGA_MAC_VER_15,
102 RTL_GIGA_MAC_VER_16,
103 RTL_GIGA_MAC_VER_17,
104 RTL_GIGA_MAC_VER_18,
105 RTL_GIGA_MAC_VER_19,
106 RTL_GIGA_MAC_VER_20,
107 RTL_GIGA_MAC_VER_21,
108 RTL_GIGA_MAC_VER_22,
109 RTL_GIGA_MAC_VER_23,
110 RTL_GIGA_MAC_VER_24,
111 RTL_GIGA_MAC_VER_25,
112 RTL_GIGA_MAC_VER_26,
113 RTL_GIGA_MAC_VER_27,
114 RTL_GIGA_MAC_VER_28,
115 RTL_GIGA_MAC_VER_29,
116 RTL_GIGA_MAC_VER_30,
117 RTL_GIGA_MAC_VER_31,
118 RTL_GIGA_MAC_VER_32,
119 RTL_GIGA_MAC_VER_33,
120 RTL_GIGA_MAC_VER_34,
121 RTL_GIGA_MAC_VER_35,
122 RTL_GIGA_MAC_VER_36,
123 RTL_GIGA_MAC_VER_37,
124 RTL_GIGA_MAC_VER_38,
125 RTL_GIGA_MAC_VER_39,
126 RTL_GIGA_MAC_VER_40,
127 RTL_GIGA_MAC_VER_41,
128 RTL_GIGA_MAC_VER_42,
129 RTL_GIGA_MAC_VER_43,
130 RTL_GIGA_MAC_VER_44,
131 RTL_GIGA_MAC_VER_45,
132 RTL_GIGA_MAC_VER_46,
133 RTL_GIGA_MAC_VER_47,
134 RTL_GIGA_MAC_VER_48,
135 RTL_GIGA_MAC_VER_49,
136 RTL_GIGA_MAC_VER_50,
137 RTL_GIGA_MAC_VER_51,
138 RTL_GIGA_MAC_VER_60,
139 RTL_GIGA_MAC_VER_61,
140 RTL_GIGA_MAC_NONE
141 };
142
143 #define JUMBO_1K ETH_DATA_LEN
144 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
145 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
146 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
147 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
148
149 static const struct {
150 const char *name;
151 const char *fw_name;
152 } rtl_chip_infos[] = {
153 /* PCI devices. */
154 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
155 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
156 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
157 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
158 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
159 /* PCI-E devices. */
160 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
161 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
162 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" },
163 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
164 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
165 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
166 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" },
167 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" },
168 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" },
169 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
170 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
171 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
172 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
173 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
174 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
175 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
176 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
177 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
178 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
179 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
180 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
181 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
182 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
183 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
184 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
185 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
186 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
187 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
188 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
189 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
190 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
191 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
192 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
193 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
194 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
195 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3},
196 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2},
197 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 },
198 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
199 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
200 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
201 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
202 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
203 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
204 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
205 [RTL_GIGA_MAC_VER_60] = {"RTL8125" },
206 [RTL_GIGA_MAC_VER_61] = {"RTL8125", FIRMWARE_8125A_3},
207 };
208
209 static const struct pci_device_id rtl8169_pci_tbl[] = {
210 { PCI_VDEVICE(REALTEK, 0x2502) },
211 { PCI_VDEVICE(REALTEK, 0x2600) },
212 { PCI_VDEVICE(REALTEK, 0x8129) },
213 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
214 { PCI_VDEVICE(REALTEK, 0x8161) },
215 { PCI_VDEVICE(REALTEK, 0x8167) },
216 { PCI_VDEVICE(REALTEK, 0x8168) },
217 { PCI_VDEVICE(NCUBE, 0x8168) },
218 { PCI_VDEVICE(REALTEK, 0x8169) },
219 { PCI_VENDOR_ID_DLINK, 0x4300,
220 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
221 { PCI_VDEVICE(DLINK, 0x4300) },
222 { PCI_VDEVICE(DLINK, 0x4302) },
223 { PCI_VDEVICE(AT, 0xc107) },
224 { PCI_VDEVICE(USR, 0x0116) },
225 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
226 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
227 { PCI_VDEVICE(REALTEK, 0x8125) },
228 { PCI_VDEVICE(REALTEK, 0x3000) },
229 {}
230 };
231
232 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
233
234 static struct {
235 u32 msg_enable;
236 } debug = { -1 };
237
238 enum rtl_registers {
239 MAC0 = 0, /* Ethernet hardware address. */
240 MAC4 = 4,
241 MAR0 = 8, /* Multicast filter. */
242 CounterAddrLow = 0x10,
243 CounterAddrHigh = 0x14,
244 TxDescStartAddrLow = 0x20,
245 TxDescStartAddrHigh = 0x24,
246 TxHDescStartAddrLow = 0x28,
247 TxHDescStartAddrHigh = 0x2c,
248 FLASH = 0x30,
249 ERSR = 0x36,
250 ChipCmd = 0x37,
251 TxPoll = 0x38,
252 IntrMask = 0x3c,
253 IntrStatus = 0x3e,
254
255 TxConfig = 0x40,
256 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
257 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
258
259 RxConfig = 0x44,
260 #define RX128_INT_EN (1 << 15) /* 8111c and later */
261 #define RX_MULTI_EN (1 << 14) /* 8111c only */
262 #define RXCFG_FIFO_SHIFT 13
263 /* No threshold before first PCI xfer */
264 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
265 #define RX_EARLY_OFF (1 << 11)
266 #define RXCFG_DMA_SHIFT 8
267 /* Unlimited maximum PCI burst. */
268 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
269
270 RxMissed = 0x4c,
271 Cfg9346 = 0x50,
272 Config0 = 0x51,
273 Config1 = 0x52,
274 Config2 = 0x53,
275 #define PME_SIGNAL (1 << 5) /* 8168c and later */
276
277 Config3 = 0x54,
278 Config4 = 0x55,
279 Config5 = 0x56,
280 PHYAR = 0x60,
281 PHYstatus = 0x6c,
282 RxMaxSize = 0xda,
283 CPlusCmd = 0xe0,
284 IntrMitigate = 0xe2,
285
286 #define RTL_COALESCE_MASK 0x0f
287 #define RTL_COALESCE_SHIFT 4
288 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
289 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
290
291 RxDescAddrLow = 0xe4,
292 RxDescAddrHigh = 0xe8,
293 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
294
295 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
296
297 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
298
299 #define TxPacketMax (8064 >> 7)
300 #define EarlySize 0x27
301
302 FuncEvent = 0xf0,
303 FuncEventMask = 0xf4,
304 FuncPresetState = 0xf8,
305 IBCR0 = 0xf8,
306 IBCR2 = 0xf9,
307 IBIMR0 = 0xfa,
308 IBISR0 = 0xfb,
309 FuncForceEvent = 0xfc,
310 };
311
312 enum rtl8168_8101_registers {
313 CSIDR = 0x64,
314 CSIAR = 0x68,
315 #define CSIAR_FLAG 0x80000000
316 #define CSIAR_WRITE_CMD 0x80000000
317 #define CSIAR_BYTE_ENABLE 0x0000f000
318 #define CSIAR_ADDR_MASK 0x00000fff
319 PMCH = 0x6f,
320 EPHYAR = 0x80,
321 #define EPHYAR_FLAG 0x80000000
322 #define EPHYAR_WRITE_CMD 0x80000000
323 #define EPHYAR_REG_MASK 0x1f
324 #define EPHYAR_REG_SHIFT 16
325 #define EPHYAR_DATA_MASK 0xffff
326 DLLPR = 0xd0,
327 #define PFM_EN (1 << 6)
328 #define TX_10M_PS_EN (1 << 7)
329 DBG_REG = 0xd1,
330 #define FIX_NAK_1 (1 << 4)
331 #define FIX_NAK_2 (1 << 3)
332 TWSI = 0xd2,
333 MCU = 0xd3,
334 #define NOW_IS_OOB (1 << 7)
335 #define TX_EMPTY (1 << 5)
336 #define RX_EMPTY (1 << 4)
337 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
338 #define EN_NDP (1 << 3)
339 #define EN_OOB_RESET (1 << 2)
340 #define LINK_LIST_RDY (1 << 1)
341 EFUSEAR = 0xdc,
342 #define EFUSEAR_FLAG 0x80000000
343 #define EFUSEAR_WRITE_CMD 0x80000000
344 #define EFUSEAR_READ_CMD 0x00000000
345 #define EFUSEAR_REG_MASK 0x03ff
346 #define EFUSEAR_REG_SHIFT 8
347 #define EFUSEAR_DATA_MASK 0xff
348 MISC_1 = 0xf2,
349 #define PFM_D3COLD_EN (1 << 6)
350 };
351
352 enum rtl8168_registers {
353 LED_FREQ = 0x1a,
354 EEE_LED = 0x1b,
355 ERIDR = 0x70,
356 ERIAR = 0x74,
357 #define ERIAR_FLAG 0x80000000
358 #define ERIAR_WRITE_CMD 0x80000000
359 #define ERIAR_READ_CMD 0x00000000
360 #define ERIAR_ADDR_BYTE_ALIGN 4
361 #define ERIAR_TYPE_SHIFT 16
362 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
363 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
364 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
365 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
366 #define ERIAR_MASK_SHIFT 12
367 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
368 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
369 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
370 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
371 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
372 EPHY_RXER_NUM = 0x7c,
373 OCPDR = 0xb0, /* OCP GPHY access */
374 #define OCPDR_WRITE_CMD 0x80000000
375 #define OCPDR_READ_CMD 0x00000000
376 #define OCPDR_REG_MASK 0x7f
377 #define OCPDR_GPHY_REG_SHIFT 16
378 #define OCPDR_DATA_MASK 0xffff
379 OCPAR = 0xb4,
380 #define OCPAR_FLAG 0x80000000
381 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
382 #define OCPAR_GPHY_READ_CMD 0x0000f060
383 GPHY_OCP = 0xb8,
384 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
385 MISC = 0xf0, /* 8168e only. */
386 #define TXPLA_RST (1 << 29)
387 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
388 #define PWM_EN (1 << 22)
389 #define RXDV_GATED_EN (1 << 19)
390 #define EARLY_TALLY_EN (1 << 16)
391 };
392
393 enum rtl8125_registers {
394 IntrMask_8125 = 0x38,
395 IntrStatus_8125 = 0x3c,
396 TxPoll_8125 = 0x90,
397 MAC0_BKP = 0x19e0,
398 };
399
400 #define RX_VLAN_INNER_8125 BIT(22)
401 #define RX_VLAN_OUTER_8125 BIT(23)
402 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
403
404 #define RX_FETCH_DFLT_8125 (8 << 27)
405
406 enum rtl_register_content {
407 /* InterruptStatusBits */
408 SYSErr = 0x8000,
409 PCSTimeout = 0x4000,
410 SWInt = 0x0100,
411 TxDescUnavail = 0x0080,
412 RxFIFOOver = 0x0040,
413 LinkChg = 0x0020,
414 RxOverflow = 0x0010,
415 TxErr = 0x0008,
416 TxOK = 0x0004,
417 RxErr = 0x0002,
418 RxOK = 0x0001,
419
420 /* RxStatusDesc */
421 RxRWT = (1 << 22),
422 RxRES = (1 << 21),
423 RxRUNT = (1 << 20),
424 RxCRC = (1 << 19),
425
426 /* ChipCmdBits */
427 StopReq = 0x80,
428 CmdReset = 0x10,
429 CmdRxEnb = 0x08,
430 CmdTxEnb = 0x04,
431 RxBufEmpty = 0x01,
432
433 /* TXPoll register p.5 */
434 HPQ = 0x80, /* Poll cmd on the high prio queue */
435 NPQ = 0x40, /* Poll cmd on the low prio queue */
436 FSWInt = 0x01, /* Forced software interrupt */
437
438 /* Cfg9346Bits */
439 Cfg9346_Lock = 0x00,
440 Cfg9346_Unlock = 0xc0,
441
442 /* rx_mode_bits */
443 AcceptErr = 0x20,
444 AcceptRunt = 0x10,
445 AcceptBroadcast = 0x08,
446 AcceptMulticast = 0x04,
447 AcceptMyPhys = 0x02,
448 AcceptAllPhys = 0x01,
449 #define RX_CONFIG_ACCEPT_MASK 0x3f
450
451 /* TxConfigBits */
452 TxInterFrameGapShift = 24,
453 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
454
455 /* Config1 register p.24 */
456 LEDS1 = (1 << 7),
457 LEDS0 = (1 << 6),
458 Speed_down = (1 << 4),
459 MEMMAP = (1 << 3),
460 IOMAP = (1 << 2),
461 VPD = (1 << 1),
462 PMEnable = (1 << 0), /* Power Management Enable */
463
464 /* Config2 register p. 25 */
465 ClkReqEn = (1 << 7), /* Clock Request Enable */
466 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
467 PCI_Clock_66MHz = 0x01,
468 PCI_Clock_33MHz = 0x00,
469
470 /* Config3 register p.25 */
471 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
472 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
473 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
474 Rdy_to_L23 = (1 << 1), /* L23 Enable */
475 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
476
477 /* Config4 register */
478 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
479
480 /* Config5 register p.27 */
481 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
482 MWF = (1 << 5), /* Accept Multicast wakeup frame */
483 UWF = (1 << 4), /* Accept Unicast wakeup frame */
484 Spi_en = (1 << 3),
485 LanWake = (1 << 1), /* LanWake enable/disable */
486 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
487 ASPM_en = (1 << 0), /* ASPM enable */
488
489 /* CPlusCmd p.31 */
490 EnableBist = (1 << 15), // 8168 8101
491 Mac_dbgo_oe = (1 << 14), // 8168 8101
492 Normal_mode = (1 << 13), // unused
493 Force_half_dup = (1 << 12), // 8168 8101
494 Force_rxflow_en = (1 << 11), // 8168 8101
495 Force_txflow_en = (1 << 10), // 8168 8101
496 Cxpl_dbg_sel = (1 << 9), // 8168 8101
497 ASF = (1 << 8), // 8168 8101
498 PktCntrDisable = (1 << 7), // 8168 8101
499 Mac_dbgo_sel = 0x001c, // 8168
500 RxVlan = (1 << 6),
501 RxChkSum = (1 << 5),
502 PCIDAC = (1 << 4),
503 PCIMulRW = (1 << 3),
504 #define INTT_MASK GENMASK(1, 0)
505 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
506
507 /* rtl8169_PHYstatus */
508 TBI_Enable = 0x80,
509 TxFlowCtrl = 0x40,
510 RxFlowCtrl = 0x20,
511 _1000bpsF = 0x10,
512 _100bps = 0x08,
513 _10bps = 0x04,
514 LinkStatus = 0x02,
515 FullDup = 0x01,
516
517 /* ResetCounterCommand */
518 CounterReset = 0x1,
519
520 /* DumpCounterCommand */
521 CounterDump = 0x8,
522
523 /* magic enable v2 */
524 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
525 };
526
527 enum rtl_desc_bit {
528 /* First doubleword. */
529 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
530 RingEnd = (1 << 30), /* End of descriptor ring */
531 FirstFrag = (1 << 29), /* First segment of a packet */
532 LastFrag = (1 << 28), /* Final segment of a packet */
533 };
534
535 /* Generic case. */
536 enum rtl_tx_desc_bit {
537 /* First doubleword. */
538 TD_LSO = (1 << 27), /* Large Send Offload */
539 #define TD_MSS_MAX 0x07ffu /* MSS value */
540
541 /* Second doubleword. */
542 TxVlanTag = (1 << 17), /* Add VLAN tag */
543 };
544
545 /* 8169, 8168b and 810x except 8102e. */
546 enum rtl_tx_desc_bit_0 {
547 /* First doubleword. */
548 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
549 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
550 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
551 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
552 };
553
554 /* 8102e, 8168c and beyond. */
555 enum rtl_tx_desc_bit_1 {
556 /* First doubleword. */
557 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
558 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
559 #define GTTCPHO_SHIFT 18
560 #define GTTCPHO_MAX 0x7f
561
562 /* Second doubleword. */
563 #define TCPHO_SHIFT 18
564 #define TCPHO_MAX 0x3ff
565 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
566 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
567 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
568 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
569 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
570 };
571
572 enum rtl_rx_desc_bit {
573 /* Rx private */
574 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
575 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
576
577 #define RxProtoUDP (PID1)
578 #define RxProtoTCP (PID0)
579 #define RxProtoIP (PID1 | PID0)
580 #define RxProtoMask RxProtoIP
581
582 IPFail = (1 << 16), /* IP checksum failed */
583 UDPFail = (1 << 15), /* UDP/IP checksum failed */
584 TCPFail = (1 << 14), /* TCP/IP checksum failed */
585 RxVlanTag = (1 << 16), /* VLAN tag available */
586 };
587
588 #define RsvdMask 0x3fffc000
589
590 #define RTL_GSO_MAX_SIZE_V1 32000
591 #define RTL_GSO_MAX_SEGS_V1 24
592 #define RTL_GSO_MAX_SIZE_V2 64000
593 #define RTL_GSO_MAX_SEGS_V2 64
594
595 struct TxDesc {
596 __le32 opts1;
597 __le32 opts2;
598 __le64 addr;
599 };
600
601 struct RxDesc {
602 __le32 opts1;
603 __le32 opts2;
604 __le64 addr;
605 };
606
607 struct ring_info {
608 struct sk_buff *skb;
609 u32 len;
610 };
611
612 struct rtl8169_counters {
613 __le64 tx_packets;
614 __le64 rx_packets;
615 __le64 tx_errors;
616 __le32 rx_errors;
617 __le16 rx_missed;
618 __le16 align_errors;
619 __le32 tx_one_collision;
620 __le32 tx_multi_collision;
621 __le64 rx_unicast;
622 __le64 rx_broadcast;
623 __le32 rx_multicast;
624 __le16 tx_aborted;
625 __le16 tx_underun;
626 };
627
628 struct rtl8169_tc_offsets {
629 bool inited;
630 __le64 tx_errors;
631 __le32 tx_multi_collision;
632 __le16 tx_aborted;
633 };
634
635 enum rtl_flag {
636 RTL_FLAG_TASK_ENABLED = 0,
637 RTL_FLAG_TASK_RESET_PENDING,
638 RTL_FLAG_MAX
639 };
640
641 struct rtl8169_stats {
642 u64 packets;
643 u64 bytes;
644 struct u64_stats_sync syncp;
645 };
646
647 struct rtl8169_private {
648 void __iomem *mmio_addr; /* memory map physical address */
649 struct pci_dev *pci_dev;
650 struct net_device *dev;
651 struct phy_device *phydev;
652 struct napi_struct napi;
653 u32 msg_enable;
654 enum mac_version mac_version;
655 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
656 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
657 u32 dirty_tx;
658 struct rtl8169_stats rx_stats;
659 struct rtl8169_stats tx_stats;
660 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
661 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
662 dma_addr_t TxPhyAddr;
663 dma_addr_t RxPhyAddr;
664 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
665 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
666 u16 cp_cmd;
667 u32 irq_mask;
668 struct clk *clk;
669
670 struct {
671 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
672 struct mutex mutex;
673 struct work_struct work;
674 } wk;
675
676 unsigned irq_enabled:1;
677 unsigned supports_gmii:1;
678 unsigned aspm_manageable:1;
679 dma_addr_t counters_phys_addr;
680 struct rtl8169_counters *counters;
681 struct rtl8169_tc_offsets tc_offset;
682 u32 saved_wolopts;
683
684 const char *fw_name;
685 struct rtl_fw *rtl_fw;
686
687 u32 ocp_base;
688 };
689
690 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
691
692 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
693 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
694 module_param_named(debug, debug.msg_enable, int, 0);
695 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
696 MODULE_SOFTDEP("pre: realtek");
697 MODULE_LICENSE("GPL");
698 MODULE_FIRMWARE(FIRMWARE_8168D_1);
699 MODULE_FIRMWARE(FIRMWARE_8168D_2);
700 MODULE_FIRMWARE(FIRMWARE_8168E_1);
701 MODULE_FIRMWARE(FIRMWARE_8168E_2);
702 MODULE_FIRMWARE(FIRMWARE_8168E_3);
703 MODULE_FIRMWARE(FIRMWARE_8105E_1);
704 MODULE_FIRMWARE(FIRMWARE_8168F_1);
705 MODULE_FIRMWARE(FIRMWARE_8168F_2);
706 MODULE_FIRMWARE(FIRMWARE_8402_1);
707 MODULE_FIRMWARE(FIRMWARE_8411_1);
708 MODULE_FIRMWARE(FIRMWARE_8411_2);
709 MODULE_FIRMWARE(FIRMWARE_8106E_1);
710 MODULE_FIRMWARE(FIRMWARE_8106E_2);
711 MODULE_FIRMWARE(FIRMWARE_8168G_2);
712 MODULE_FIRMWARE(FIRMWARE_8168G_3);
713 MODULE_FIRMWARE(FIRMWARE_8168H_1);
714 MODULE_FIRMWARE(FIRMWARE_8168H_2);
715 MODULE_FIRMWARE(FIRMWARE_8107E_1);
716 MODULE_FIRMWARE(FIRMWARE_8107E_2);
717 MODULE_FIRMWARE(FIRMWARE_8125A_3);
718
719 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
720 {
721 return &tp->pci_dev->dev;
722 }
723
724 static void rtl_lock_work(struct rtl8169_private *tp)
725 {
726 mutex_lock(&tp->wk.mutex);
727 }
728
729 static void rtl_unlock_work(struct rtl8169_private *tp)
730 {
731 mutex_unlock(&tp->wk.mutex);
732 }
733
734 static void rtl_lock_config_regs(struct rtl8169_private *tp)
735 {
736 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
737 }
738
739 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
740 {
741 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
742 }
743
744 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
745 {
746 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
747 PCI_EXP_DEVCTL_READRQ, force);
748 }
749
750 static bool rtl_is_8125(struct rtl8169_private *tp)
751 {
752 return tp->mac_version >= RTL_GIGA_MAC_VER_60;
753 }
754
755 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
756 {
757 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
758 tp->mac_version != RTL_GIGA_MAC_VER_39 &&
759 tp->mac_version <= RTL_GIGA_MAC_VER_51;
760 }
761
762 static bool rtl_supports_eee(struct rtl8169_private *tp)
763 {
764 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
765 tp->mac_version != RTL_GIGA_MAC_VER_37 &&
766 tp->mac_version != RTL_GIGA_MAC_VER_39;
767 }
768
769 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
770 {
771 int i;
772
773 for (i = 0; i < ETH_ALEN; i++)
774 mac[i] = RTL_R8(tp, reg + i);
775 }
776
777 struct rtl_cond {
778 bool (*check)(struct rtl8169_private *);
779 const char *msg;
780 };
781
782 static void rtl_udelay(unsigned int d)
783 {
784 udelay(d);
785 }
786
787 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
788 void (*delay)(unsigned int), unsigned int d, int n,
789 bool high)
790 {
791 int i;
792
793 for (i = 0; i < n; i++) {
794 if (c->check(tp) == high)
795 return true;
796 delay(d);
797 }
798 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
799 c->msg, !high, n, d);
800 return false;
801 }
802
803 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
804 const struct rtl_cond *c,
805 unsigned int d, int n)
806 {
807 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
808 }
809
810 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
811 const struct rtl_cond *c,
812 unsigned int d, int n)
813 {
814 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
815 }
816
817 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
818 const struct rtl_cond *c,
819 unsigned int d, int n)
820 {
821 return rtl_loop_wait(tp, c, msleep, d, n, true);
822 }
823
824 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
825 const struct rtl_cond *c,
826 unsigned int d, int n)
827 {
828 return rtl_loop_wait(tp, c, msleep, d, n, false);
829 }
830
831 #define DECLARE_RTL_COND(name) \
832 static bool name ## _check(struct rtl8169_private *); \
833 \
834 static const struct rtl_cond name = { \
835 .check = name ## _check, \
836 .msg = #name \
837 }; \
838 \
839 static bool name ## _check(struct rtl8169_private *tp)
840
841 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
842 {
843 if (reg & 0xffff0001) {
844 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
845 return true;
846 }
847 return false;
848 }
849
850 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
851 {
852 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
853 }
854
855 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
856 {
857 if (rtl_ocp_reg_failure(tp, reg))
858 return;
859
860 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
861
862 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
863 }
864
865 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
866 {
867 if (rtl_ocp_reg_failure(tp, reg))
868 return 0;
869
870 RTL_W32(tp, GPHY_OCP, reg << 15);
871
872 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
873 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
874 }
875
876 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
877 {
878 if (rtl_ocp_reg_failure(tp, reg))
879 return;
880
881 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
882 }
883
884 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
885 {
886 if (rtl_ocp_reg_failure(tp, reg))
887 return 0;
888
889 RTL_W32(tp, OCPDR, reg << 15);
890
891 return RTL_R32(tp, OCPDR);
892 }
893
894 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
895 u16 set)
896 {
897 u16 data = r8168_mac_ocp_read(tp, reg);
898
899 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
900 }
901
902 #define OCP_STD_PHY_BASE 0xa400
903
904 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
905 {
906 if (reg == 0x1f) {
907 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
908 return;
909 }
910
911 if (tp->ocp_base != OCP_STD_PHY_BASE)
912 reg -= 0x10;
913
914 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
915 }
916
917 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
918 {
919 if (reg == 0x1f)
920 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
921
922 if (tp->ocp_base != OCP_STD_PHY_BASE)
923 reg -= 0x10;
924
925 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
926 }
927
928 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
929 {
930 if (reg == 0x1f) {
931 tp->ocp_base = value << 4;
932 return;
933 }
934
935 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
936 }
937
938 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
939 {
940 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
941 }
942
943 DECLARE_RTL_COND(rtl_phyar_cond)
944 {
945 return RTL_R32(tp, PHYAR) & 0x80000000;
946 }
947
948 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
949 {
950 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
951
952 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
953 /*
954 * According to hardware specs a 20us delay is required after write
955 * complete indication, but before sending next command.
956 */
957 udelay(20);
958 }
959
960 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
961 {
962 int value;
963
964 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
965
966 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
967 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
968
969 /*
970 * According to hardware specs a 20us delay is required after read
971 * complete indication, but before sending next command.
972 */
973 udelay(20);
974
975 return value;
976 }
977
978 DECLARE_RTL_COND(rtl_ocpar_cond)
979 {
980 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
981 }
982
983 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
984 {
985 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
986 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
987 RTL_W32(tp, EPHY_RXER_NUM, 0);
988
989 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
990 }
991
992 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
993 {
994 r8168dp_1_mdio_access(tp, reg,
995 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
996 }
997
998 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
999 {
1000 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1001
1002 mdelay(1);
1003 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
1004 RTL_W32(tp, EPHY_RXER_NUM, 0);
1005
1006 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1007 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
1008 }
1009
1010 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1011
1012 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1013 {
1014 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1015 }
1016
1017 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1018 {
1019 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1020 }
1021
1022 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1023 {
1024 r8168dp_2_mdio_start(tp);
1025
1026 r8169_mdio_write(tp, reg, value);
1027
1028 r8168dp_2_mdio_stop(tp);
1029 }
1030
1031 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1032 {
1033 int value;
1034
1035 /* Work around issue with chip reporting wrong PHY ID */
1036 if (reg == MII_PHYSID2)
1037 return 0xc912;
1038
1039 r8168dp_2_mdio_start(tp);
1040
1041 value = r8169_mdio_read(tp, reg);
1042
1043 r8168dp_2_mdio_stop(tp);
1044
1045 return value;
1046 }
1047
1048 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1049 {
1050 switch (tp->mac_version) {
1051 case RTL_GIGA_MAC_VER_27:
1052 r8168dp_1_mdio_write(tp, location, val);
1053 break;
1054 case RTL_GIGA_MAC_VER_28:
1055 case RTL_GIGA_MAC_VER_31:
1056 r8168dp_2_mdio_write(tp, location, val);
1057 break;
1058 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61:
1059 r8168g_mdio_write(tp, location, val);
1060 break;
1061 default:
1062 r8169_mdio_write(tp, location, val);
1063 break;
1064 }
1065 }
1066
1067 static int rtl_readphy(struct rtl8169_private *tp, int location)
1068 {
1069 switch (tp->mac_version) {
1070 case RTL_GIGA_MAC_VER_27:
1071 return r8168dp_1_mdio_read(tp, location);
1072 case RTL_GIGA_MAC_VER_28:
1073 case RTL_GIGA_MAC_VER_31:
1074 return r8168dp_2_mdio_read(tp, location);
1075 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61:
1076 return r8168g_mdio_read(tp, location);
1077 default:
1078 return r8169_mdio_read(tp, location);
1079 }
1080 }
1081
1082 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1083 {
1084 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1085 }
1086
1087 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1088 {
1089 int val;
1090
1091 val = rtl_readphy(tp, reg_addr);
1092 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1093 }
1094
1095 DECLARE_RTL_COND(rtl_ephyar_cond)
1096 {
1097 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1098 }
1099
1100 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1101 {
1102 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1103 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1104
1105 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1106
1107 udelay(10);
1108 }
1109
1110 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1111 {
1112 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1113
1114 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1115 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1116 }
1117
1118 DECLARE_RTL_COND(rtl_eriar_cond)
1119 {
1120 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1121 }
1122
1123 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1124 u32 val, int type)
1125 {
1126 BUG_ON((addr & 3) || (mask == 0));
1127 RTL_W32(tp, ERIDR, val);
1128 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1129
1130 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1131 }
1132
1133 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1134 u32 val)
1135 {
1136 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1137 }
1138
1139 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1140 {
1141 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1142
1143 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1144 RTL_R32(tp, ERIDR) : ~0;
1145 }
1146
1147 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1148 {
1149 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1150 }
1151
1152 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1153 u32 m)
1154 {
1155 u32 val;
1156
1157 val = rtl_eri_read(tp, addr);
1158 rtl_eri_write(tp, addr, mask, (val & ~m) | p);
1159 }
1160
1161 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,
1162 u32 p)
1163 {
1164 rtl_w0w1_eri(tp, addr, mask, p, 0);
1165 }
1166
1167 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
1168 u32 m)
1169 {
1170 rtl_w0w1_eri(tp, addr, mask, 0, m);
1171 }
1172
1173 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1174 {
1175 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1176 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1177 RTL_R32(tp, OCPDR) : ~0;
1178 }
1179
1180 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1181 {
1182 return _rtl_eri_read(tp, reg, ERIAR_OOB);
1183 }
1184
1185 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1186 u32 data)
1187 {
1188 RTL_W32(tp, OCPDR, data);
1189 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1190 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1191 }
1192
1193 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1194 u32 data)
1195 {
1196 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1197 data, ERIAR_OOB);
1198 }
1199
1200 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1201 {
1202 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1203
1204 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1205 }
1206
1207 #define OOB_CMD_RESET 0x00
1208 #define OOB_CMD_DRIVER_START 0x05
1209 #define OOB_CMD_DRIVER_STOP 0x06
1210
1211 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1212 {
1213 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1214 }
1215
1216 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1217 {
1218 u16 reg;
1219
1220 reg = rtl8168_get_ocp_reg(tp);
1221
1222 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1223 }
1224
1225 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1226 {
1227 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1228 }
1229
1230 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1231 {
1232 return RTL_R8(tp, IBISR0) & 0x20;
1233 }
1234
1235 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1236 {
1237 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1238 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1239 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1240 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1241 }
1242
1243 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1244 {
1245 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1246 rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1247 }
1248
1249 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1250 {
1251 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1252 r8168ep_ocp_write(tp, 0x01, 0x30,
1253 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1254 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1255 }
1256
1257 static void rtl8168_driver_start(struct rtl8169_private *tp)
1258 {
1259 switch (tp->mac_version) {
1260 case RTL_GIGA_MAC_VER_27:
1261 case RTL_GIGA_MAC_VER_28:
1262 case RTL_GIGA_MAC_VER_31:
1263 rtl8168dp_driver_start(tp);
1264 break;
1265 case RTL_GIGA_MAC_VER_49:
1266 case RTL_GIGA_MAC_VER_50:
1267 case RTL_GIGA_MAC_VER_51:
1268 rtl8168ep_driver_start(tp);
1269 break;
1270 default:
1271 BUG();
1272 break;
1273 }
1274 }
1275
1276 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1277 {
1278 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1279 rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1280 }
1281
1282 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1283 {
1284 rtl8168ep_stop_cmac(tp);
1285 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1286 r8168ep_ocp_write(tp, 0x01, 0x30,
1287 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1288 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1289 }
1290
1291 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1292 {
1293 switch (tp->mac_version) {
1294 case RTL_GIGA_MAC_VER_27:
1295 case RTL_GIGA_MAC_VER_28:
1296 case RTL_GIGA_MAC_VER_31:
1297 rtl8168dp_driver_stop(tp);
1298 break;
1299 case RTL_GIGA_MAC_VER_49:
1300 case RTL_GIGA_MAC_VER_50:
1301 case RTL_GIGA_MAC_VER_51:
1302 rtl8168ep_driver_stop(tp);
1303 break;
1304 default:
1305 BUG();
1306 break;
1307 }
1308 }
1309
1310 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1311 {
1312 u16 reg = rtl8168_get_ocp_reg(tp);
1313
1314 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1315 }
1316
1317 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1318 {
1319 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1320 }
1321
1322 static bool r8168_check_dash(struct rtl8169_private *tp)
1323 {
1324 switch (tp->mac_version) {
1325 case RTL_GIGA_MAC_VER_27:
1326 case RTL_GIGA_MAC_VER_28:
1327 case RTL_GIGA_MAC_VER_31:
1328 return r8168dp_check_dash(tp);
1329 case RTL_GIGA_MAC_VER_49:
1330 case RTL_GIGA_MAC_VER_50:
1331 case RTL_GIGA_MAC_VER_51:
1332 return r8168ep_check_dash(tp);
1333 default:
1334 return false;
1335 }
1336 }
1337
1338 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1339 {
1340 rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1341 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1342 }
1343
1344 DECLARE_RTL_COND(rtl_efusear_cond)
1345 {
1346 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1347 }
1348
1349 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1350 {
1351 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1352
1353 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1354 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1355 }
1356
1357 static u32 rtl_get_events(struct rtl8169_private *tp)
1358 {
1359 if (rtl_is_8125(tp))
1360 return RTL_R32(tp, IntrStatus_8125);
1361 else
1362 return RTL_R16(tp, IntrStatus);
1363 }
1364
1365 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1366 {
1367 if (rtl_is_8125(tp))
1368 RTL_W32(tp, IntrStatus_8125, bits);
1369 else
1370 RTL_W16(tp, IntrStatus, bits);
1371 }
1372
1373 static void rtl_irq_disable(struct rtl8169_private *tp)
1374 {
1375 if (rtl_is_8125(tp))
1376 RTL_W32(tp, IntrMask_8125, 0);
1377 else
1378 RTL_W16(tp, IntrMask, 0);
1379 tp->irq_enabled = 0;
1380 }
1381
1382 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1383 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1384 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1385
1386 static void rtl_irq_enable(struct rtl8169_private *tp)
1387 {
1388 tp->irq_enabled = 1;
1389 if (rtl_is_8125(tp))
1390 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1391 else
1392 RTL_W16(tp, IntrMask, tp->irq_mask);
1393 }
1394
1395 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1396 {
1397 rtl_irq_disable(tp);
1398 rtl_ack_events(tp, 0xffffffff);
1399 /* PCI commit */
1400 RTL_R8(tp, ChipCmd);
1401 }
1402
1403 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1404 {
1405 struct net_device *dev = tp->dev;
1406 struct phy_device *phydev = tp->phydev;
1407
1408 if (!netif_running(dev))
1409 return;
1410
1411 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1412 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1413 if (phydev->speed == SPEED_1000) {
1414 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1415 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1416 } else if (phydev->speed == SPEED_100) {
1417 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1418 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1419 } else {
1420 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1421 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1422 }
1423 rtl_reset_packet_filter(tp);
1424 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1425 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1426 if (phydev->speed == SPEED_1000) {
1427 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1428 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1429 } else {
1430 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1431 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1432 }
1433 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1434 if (phydev->speed == SPEED_10) {
1435 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1436 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1437 } else {
1438 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1439 }
1440 }
1441 }
1442
1443 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1444
1445 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1446 {
1447 struct rtl8169_private *tp = netdev_priv(dev);
1448
1449 rtl_lock_work(tp);
1450 wol->supported = WAKE_ANY;
1451 wol->wolopts = tp->saved_wolopts;
1452 rtl_unlock_work(tp);
1453 }
1454
1455 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1456 {
1457 static const struct {
1458 u32 opt;
1459 u16 reg;
1460 u8 mask;
1461 } cfg[] = {
1462 { WAKE_PHY, Config3, LinkUp },
1463 { WAKE_UCAST, Config5, UWF },
1464 { WAKE_BCAST, Config5, BWF },
1465 { WAKE_MCAST, Config5, MWF },
1466 { WAKE_ANY, Config5, LanWake },
1467 { WAKE_MAGIC, Config3, MagicPacket }
1468 };
1469 unsigned int i, tmp = ARRAY_SIZE(cfg);
1470 u8 options;
1471
1472 rtl_unlock_config_regs(tp);
1473
1474 if (rtl_is_8168evl_up(tp)) {
1475 tmp--;
1476 if (wolopts & WAKE_MAGIC)
1477 rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
1478 MagicPacket_v2);
1479 else
1480 rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
1481 MagicPacket_v2);
1482 } else if (rtl_is_8125(tp)) {
1483 tmp--;
1484 if (wolopts & WAKE_MAGIC)
1485 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1486 else
1487 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1488 }
1489
1490 for (i = 0; i < tmp; i++) {
1491 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1492 if (wolopts & cfg[i].opt)
1493 options |= cfg[i].mask;
1494 RTL_W8(tp, cfg[i].reg, options);
1495 }
1496
1497 switch (tp->mac_version) {
1498 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1499 options = RTL_R8(tp, Config1) & ~PMEnable;
1500 if (wolopts)
1501 options |= PMEnable;
1502 RTL_W8(tp, Config1, options);
1503 break;
1504 case RTL_GIGA_MAC_VER_34:
1505 case RTL_GIGA_MAC_VER_37:
1506 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_51:
1507 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1508 if (wolopts)
1509 options |= PME_SIGNAL;
1510 RTL_W8(tp, Config2, options);
1511 break;
1512 default:
1513 break;
1514 }
1515
1516 rtl_lock_config_regs(tp);
1517
1518 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1519 tp->dev->wol_enabled = wolopts ? 1 : 0;
1520 }
1521
1522 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1523 {
1524 struct rtl8169_private *tp = netdev_priv(dev);
1525 struct device *d = tp_to_dev(tp);
1526
1527 if (wol->wolopts & ~WAKE_ANY)
1528 return -EINVAL;
1529
1530 pm_runtime_get_noresume(d);
1531
1532 rtl_lock_work(tp);
1533
1534 tp->saved_wolopts = wol->wolopts;
1535
1536 if (pm_runtime_active(d))
1537 __rtl8169_set_wol(tp, tp->saved_wolopts);
1538
1539 rtl_unlock_work(tp);
1540
1541 pm_runtime_put_noidle(d);
1542
1543 return 0;
1544 }
1545
1546 static void rtl8169_get_drvinfo(struct net_device *dev,
1547 struct ethtool_drvinfo *info)
1548 {
1549 struct rtl8169_private *tp = netdev_priv(dev);
1550 struct rtl_fw *rtl_fw = tp->rtl_fw;
1551
1552 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1553 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1554 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1555 if (rtl_fw)
1556 strlcpy(info->fw_version, rtl_fw->version,
1557 sizeof(info->fw_version));
1558 }
1559
1560 static int rtl8169_get_regs_len(struct net_device *dev)
1561 {
1562 return R8169_REGS_SIZE;
1563 }
1564
1565 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1566 netdev_features_t features)
1567 {
1568 struct rtl8169_private *tp = netdev_priv(dev);
1569
1570 if (dev->mtu > TD_MSS_MAX)
1571 features &= ~NETIF_F_ALL_TSO;
1572
1573 if (dev->mtu > JUMBO_1K &&
1574 tp->mac_version > RTL_GIGA_MAC_VER_06)
1575 features &= ~NETIF_F_IP_CSUM;
1576
1577 return features;
1578 }
1579
1580 static int rtl8169_set_features(struct net_device *dev,
1581 netdev_features_t features)
1582 {
1583 struct rtl8169_private *tp = netdev_priv(dev);
1584 u32 rx_config;
1585
1586 rtl_lock_work(tp);
1587
1588 rx_config = RTL_R32(tp, RxConfig);
1589 if (features & NETIF_F_RXALL)
1590 rx_config |= (AcceptErr | AcceptRunt);
1591 else
1592 rx_config &= ~(AcceptErr | AcceptRunt);
1593
1594 if (rtl_is_8125(tp)) {
1595 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1596 rx_config |= RX_VLAN_8125;
1597 else
1598 rx_config &= ~RX_VLAN_8125;
1599 }
1600
1601 RTL_W32(tp, RxConfig, rx_config);
1602
1603 if (features & NETIF_F_RXCSUM)
1604 tp->cp_cmd |= RxChkSum;
1605 else
1606 tp->cp_cmd &= ~RxChkSum;
1607
1608 if (!rtl_is_8125(tp)) {
1609 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1610 tp->cp_cmd |= RxVlan;
1611 else
1612 tp->cp_cmd &= ~RxVlan;
1613 }
1614
1615 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1616 RTL_R16(tp, CPlusCmd);
1617
1618 rtl_unlock_work(tp);
1619
1620 return 0;
1621 }
1622
1623 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1624 {
1625 return (skb_vlan_tag_present(skb)) ?
1626 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1627 }
1628
1629 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1630 {
1631 u32 opts2 = le32_to_cpu(desc->opts2);
1632
1633 if (opts2 & RxVlanTag)
1634 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1635 }
1636
1637 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1638 void *p)
1639 {
1640 struct rtl8169_private *tp = netdev_priv(dev);
1641 u32 __iomem *data = tp->mmio_addr;
1642 u32 *dw = p;
1643 int i;
1644
1645 rtl_lock_work(tp);
1646 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1647 memcpy_fromio(dw++, data++, 4);
1648 rtl_unlock_work(tp);
1649 }
1650
1651 static u32 rtl8169_get_msglevel(struct net_device *dev)
1652 {
1653 struct rtl8169_private *tp = netdev_priv(dev);
1654
1655 return tp->msg_enable;
1656 }
1657
1658 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1659 {
1660 struct rtl8169_private *tp = netdev_priv(dev);
1661
1662 tp->msg_enable = value;
1663 }
1664
1665 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1666 "tx_packets",
1667 "rx_packets",
1668 "tx_errors",
1669 "rx_errors",
1670 "rx_missed",
1671 "align_errors",
1672 "tx_single_collisions",
1673 "tx_multi_collisions",
1674 "unicast",
1675 "broadcast",
1676 "multicast",
1677 "tx_aborted",
1678 "tx_underrun",
1679 };
1680
1681 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1682 {
1683 switch (sset) {
1684 case ETH_SS_STATS:
1685 return ARRAY_SIZE(rtl8169_gstrings);
1686 default:
1687 return -EOPNOTSUPP;
1688 }
1689 }
1690
1691 DECLARE_RTL_COND(rtl_counters_cond)
1692 {
1693 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1694 }
1695
1696 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1697 {
1698 dma_addr_t paddr = tp->counters_phys_addr;
1699 u32 cmd;
1700
1701 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1702 RTL_R32(tp, CounterAddrHigh);
1703 cmd = (u64)paddr & DMA_BIT_MASK(32);
1704 RTL_W32(tp, CounterAddrLow, cmd);
1705 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1706
1707 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1708 }
1709
1710 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1711 {
1712 /*
1713 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1714 * tally counters.
1715 */
1716 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1717 return true;
1718
1719 return rtl8169_do_counters(tp, CounterReset);
1720 }
1721
1722 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1723 {
1724 u8 val = RTL_R8(tp, ChipCmd);
1725
1726 /*
1727 * Some chips are unable to dump tally counters when the receiver
1728 * is disabled. If 0xff chip may be in a PCI power-save state.
1729 */
1730 if (!(val & CmdRxEnb) || val == 0xff)
1731 return true;
1732
1733 return rtl8169_do_counters(tp, CounterDump);
1734 }
1735
1736 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1737 {
1738 struct rtl8169_counters *counters = tp->counters;
1739 bool ret = false;
1740
1741 /*
1742 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1743 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1744 * reset by a power cycle, while the counter values collected by the
1745 * driver are reset at every driver unload/load cycle.
1746 *
1747 * To make sure the HW values returned by @get_stats64 match the SW
1748 * values, we collect the initial values at first open(*) and use them
1749 * as offsets to normalize the values returned by @get_stats64.
1750 *
1751 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1752 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1753 * set at open time by rtl_hw_start.
1754 */
1755
1756 if (tp->tc_offset.inited)
1757 return true;
1758
1759 /* If both, reset and update fail, propagate to caller. */
1760 if (rtl8169_reset_counters(tp))
1761 ret = true;
1762
1763 if (rtl8169_update_counters(tp))
1764 ret = true;
1765
1766 tp->tc_offset.tx_errors = counters->tx_errors;
1767 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1768 tp->tc_offset.tx_aborted = counters->tx_aborted;
1769 tp->tc_offset.inited = true;
1770
1771 return ret;
1772 }
1773
1774 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1775 struct ethtool_stats *stats, u64 *data)
1776 {
1777 struct rtl8169_private *tp = netdev_priv(dev);
1778 struct device *d = tp_to_dev(tp);
1779 struct rtl8169_counters *counters = tp->counters;
1780
1781 ASSERT_RTNL();
1782
1783 pm_runtime_get_noresume(d);
1784
1785 if (pm_runtime_active(d))
1786 rtl8169_update_counters(tp);
1787
1788 pm_runtime_put_noidle(d);
1789
1790 data[0] = le64_to_cpu(counters->tx_packets);
1791 data[1] = le64_to_cpu(counters->rx_packets);
1792 data[2] = le64_to_cpu(counters->tx_errors);
1793 data[3] = le32_to_cpu(counters->rx_errors);
1794 data[4] = le16_to_cpu(counters->rx_missed);
1795 data[5] = le16_to_cpu(counters->align_errors);
1796 data[6] = le32_to_cpu(counters->tx_one_collision);
1797 data[7] = le32_to_cpu(counters->tx_multi_collision);
1798 data[8] = le64_to_cpu(counters->rx_unicast);
1799 data[9] = le64_to_cpu(counters->rx_broadcast);
1800 data[10] = le32_to_cpu(counters->rx_multicast);
1801 data[11] = le16_to_cpu(counters->tx_aborted);
1802 data[12] = le16_to_cpu(counters->tx_underun);
1803 }
1804
1805 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1806 {
1807 switch(stringset) {
1808 case ETH_SS_STATS:
1809 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1810 break;
1811 }
1812 }
1813
1814 /*
1815 * Interrupt coalescing
1816 *
1817 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1818 * > 8169, 8168 and 810x line of chipsets
1819 *
1820 * 8169, 8168, and 8136(810x) serial chipsets support it.
1821 *
1822 * > 2 - the Tx timer unit at gigabit speed
1823 *
1824 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1825 * (0xe0) bit 1 and bit 0.
1826 *
1827 * For 8169
1828 * bit[1:0] \ speed 1000M 100M 10M
1829 * 0 0 320ns 2.56us 40.96us
1830 * 0 1 2.56us 20.48us 327.7us
1831 * 1 0 5.12us 40.96us 655.4us
1832 * 1 1 10.24us 81.92us 1.31ms
1833 *
1834 * For the other
1835 * bit[1:0] \ speed 1000M 100M 10M
1836 * 0 0 5us 2.56us 40.96us
1837 * 0 1 40us 20.48us 327.7us
1838 * 1 0 80us 40.96us 655.4us
1839 * 1 1 160us 81.92us 1.31ms
1840 */
1841
1842 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1843 struct rtl_coalesce_scale {
1844 /* Rx / Tx */
1845 u32 nsecs[2];
1846 };
1847
1848 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1849 struct rtl_coalesce_info {
1850 u32 speed;
1851 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
1852 };
1853
1854 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1855 #define rxtx_x1822(r, t) { \
1856 {{(r), (t)}}, \
1857 {{(r)*8, (t)*8}}, \
1858 {{(r)*8*2, (t)*8*2}}, \
1859 {{(r)*8*2*2, (t)*8*2*2}}, \
1860 }
1861 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1862 /* speed delays: rx00 tx00 */
1863 { SPEED_10, rxtx_x1822(40960, 40960) },
1864 { SPEED_100, rxtx_x1822( 2560, 2560) },
1865 { SPEED_1000, rxtx_x1822( 320, 320) },
1866 { 0 },
1867 };
1868
1869 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1870 /* speed delays: rx00 tx00 */
1871 { SPEED_10, rxtx_x1822(40960, 40960) },
1872 { SPEED_100, rxtx_x1822( 2560, 2560) },
1873 { SPEED_1000, rxtx_x1822( 5000, 5000) },
1874 { 0 },
1875 };
1876 #undef rxtx_x1822
1877
1878 /* get rx/tx scale vector corresponding to current speed */
1879 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1880 {
1881 struct rtl8169_private *tp = netdev_priv(dev);
1882 const struct rtl_coalesce_info *ci;
1883
1884 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1885 ci = rtl_coalesce_info_8169;
1886 else
1887 ci = rtl_coalesce_info_8168_8136;
1888
1889 for (; ci->speed; ci++) {
1890 if (tp->phydev->speed == ci->speed)
1891 return ci;
1892 }
1893
1894 return ERR_PTR(-ELNRNG);
1895 }
1896
1897 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1898 {
1899 struct rtl8169_private *tp = netdev_priv(dev);
1900 const struct rtl_coalesce_info *ci;
1901 const struct rtl_coalesce_scale *scale;
1902 struct {
1903 u32 *max_frames;
1904 u32 *usecs;
1905 } coal_settings [] = {
1906 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1907 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1908 }, *p = coal_settings;
1909 int i;
1910 u16 w;
1911
1912 if (rtl_is_8125(tp))
1913 return -EOPNOTSUPP;
1914
1915 memset(ec, 0, sizeof(*ec));
1916
1917 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1918 ci = rtl_coalesce_info(dev);
1919 if (IS_ERR(ci))
1920 return PTR_ERR(ci);
1921
1922 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1923
1924 /* read IntrMitigate and adjust according to scale */
1925 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1926 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1927 w >>= RTL_COALESCE_SHIFT;
1928 *p->usecs = w & RTL_COALESCE_MASK;
1929 }
1930
1931 for (i = 0; i < 2; i++) {
1932 p = coal_settings + i;
1933 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1934
1935 /*
1936 * ethtool_coalesce says it is illegal to set both usecs and
1937 * max_frames to 0.
1938 */
1939 if (!*p->usecs && !*p->max_frames)
1940 *p->max_frames = 1;
1941 }
1942
1943 return 0;
1944 }
1945
1946 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1947 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1948 struct net_device *dev, u32 nsec, u16 *cp01)
1949 {
1950 const struct rtl_coalesce_info *ci;
1951 u16 i;
1952
1953 ci = rtl_coalesce_info(dev);
1954 if (IS_ERR(ci))
1955 return ERR_CAST(ci);
1956
1957 for (i = 0; i < 4; i++) {
1958 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1959 ci->scalev[i].nsecs[1]);
1960 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1961 *cp01 = i;
1962 return &ci->scalev[i];
1963 }
1964 }
1965
1966 return ERR_PTR(-EINVAL);
1967 }
1968
1969 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1970 {
1971 struct rtl8169_private *tp = netdev_priv(dev);
1972 const struct rtl_coalesce_scale *scale;
1973 struct {
1974 u32 frames;
1975 u32 usecs;
1976 } coal_settings [] = {
1977 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1978 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1979 }, *p = coal_settings;
1980 u16 w = 0, cp01;
1981 int i;
1982
1983 if (rtl_is_8125(tp))
1984 return -EOPNOTSUPP;
1985
1986 scale = rtl_coalesce_choose_scale(dev,
1987 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1988 if (IS_ERR(scale))
1989 return PTR_ERR(scale);
1990
1991 for (i = 0; i < 2; i++, p++) {
1992 u32 units;
1993
1994 /*
1995 * accept max_frames=1 we returned in rtl_get_coalesce.
1996 * accept it not only when usecs=0 because of e.g. the following scenario:
1997 *
1998 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1999 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2000 * - then user does `ethtool -C eth0 rx-usecs 100`
2001 *
2002 * since ethtool sends to kernel whole ethtool_coalesce
2003 * settings, if we do not handle rx_usecs=!0, rx_frames=1
2004 * we'll reject it below in `frames % 4 != 0`.
2005 */
2006 if (p->frames == 1) {
2007 p->frames = 0;
2008 }
2009
2010 units = p->usecs * 1000 / scale->nsecs[i];
2011 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2012 return -EINVAL;
2013
2014 w <<= RTL_COALESCE_SHIFT;
2015 w |= units;
2016 w <<= RTL_COALESCE_SHIFT;
2017 w |= p->frames >> 2;
2018 }
2019
2020 rtl_lock_work(tp);
2021
2022 RTL_W16(tp, IntrMitigate, swab16(w));
2023
2024 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
2025 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2026 RTL_R16(tp, CPlusCmd);
2027
2028 rtl_unlock_work(tp);
2029
2030 return 0;
2031 }
2032
2033 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
2034 {
2035 struct rtl8169_private *tp = netdev_priv(dev);
2036 struct device *d = tp_to_dev(tp);
2037 int ret;
2038
2039 if (!rtl_supports_eee(tp))
2040 return -EOPNOTSUPP;
2041
2042 pm_runtime_get_noresume(d);
2043
2044 if (!pm_runtime_active(d)) {
2045 ret = -EOPNOTSUPP;
2046 } else {
2047 ret = phy_ethtool_get_eee(tp->phydev, data);
2048 }
2049
2050 pm_runtime_put_noidle(d);
2051
2052 return ret;
2053 }
2054
2055 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
2056 {
2057 struct rtl8169_private *tp = netdev_priv(dev);
2058 struct device *d = tp_to_dev(tp);
2059 int ret;
2060
2061 if (!rtl_supports_eee(tp))
2062 return -EOPNOTSUPP;
2063
2064 pm_runtime_get_noresume(d);
2065
2066 if (!pm_runtime_active(d)) {
2067 ret = -EOPNOTSUPP;
2068 goto out;
2069 }
2070
2071 if (dev->phydev->autoneg == AUTONEG_DISABLE ||
2072 dev->phydev->duplex != DUPLEX_FULL) {
2073 ret = -EPROTONOSUPPORT;
2074 goto out;
2075 }
2076
2077 ret = phy_ethtool_set_eee(tp->phydev, data);
2078 out:
2079 pm_runtime_put_noidle(d);
2080 return ret;
2081 }
2082
2083 static const struct ethtool_ops rtl8169_ethtool_ops = {
2084 .get_drvinfo = rtl8169_get_drvinfo,
2085 .get_regs_len = rtl8169_get_regs_len,
2086 .get_link = ethtool_op_get_link,
2087 .get_coalesce = rtl_get_coalesce,
2088 .set_coalesce = rtl_set_coalesce,
2089 .get_msglevel = rtl8169_get_msglevel,
2090 .set_msglevel = rtl8169_set_msglevel,
2091 .get_regs = rtl8169_get_regs,
2092 .get_wol = rtl8169_get_wol,
2093 .set_wol = rtl8169_set_wol,
2094 .get_strings = rtl8169_get_strings,
2095 .get_sset_count = rtl8169_get_sset_count,
2096 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2097 .get_ts_info = ethtool_op_get_ts_info,
2098 .nway_reset = phy_ethtool_nway_reset,
2099 .get_eee = rtl8169_get_eee,
2100 .set_eee = rtl8169_set_eee,
2101 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2102 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2103 };
2104
2105 static void rtl_enable_eee(struct rtl8169_private *tp)
2106 {
2107 struct phy_device *phydev = tp->phydev;
2108 int supported = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
2109
2110 if (supported > 0)
2111 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, supported);
2112 }
2113
2114 static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2115 {
2116 /*
2117 * The driver currently handles the 8168Bf and the 8168Be identically
2118 * but they can be identified more specifically through the test below
2119 * if needed:
2120 *
2121 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2122 *
2123 * Same thing for the 8101Eb and the 8101Ec:
2124 *
2125 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2126 */
2127 static const struct rtl_mac_info {
2128 u16 mask;
2129 u16 val;
2130 u16 mac_version;
2131 } mac_info[] = {
2132 /* 8125 family. */
2133 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 },
2134 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 },
2135
2136 /* 8168EP family. */
2137 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2138 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2139 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2140
2141 /* 8168H family. */
2142 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2143 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2144
2145 /* 8168G family. */
2146 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2147 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2148 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2149 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2150
2151 /* 8168F family. */
2152 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2153 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2154 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2155
2156 /* 8168E family. */
2157 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2158 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2159 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2160
2161 /* 8168D family. */
2162 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2163 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2164
2165 /* 8168DP family. */
2166 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2167 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2168 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2169
2170 /* 8168C family. */
2171 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2172 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2173 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2174 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2175 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2176 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2177 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2178
2179 /* 8168B family. */
2180 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2181 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2182 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2183
2184 /* 8101 family. */
2185 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2186 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2187 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2188 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2189 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2190 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2191 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2192 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2193 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2194 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2195 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2196 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2197 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2198 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2199 /* FIXME: where did these entries come from ? -- FR */
2200 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2201 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2202
2203 /* 8110 family. */
2204 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2205 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2206 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2207 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2208 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2209
2210 /* Catch-all */
2211 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
2212 };
2213 const struct rtl_mac_info *p = mac_info;
2214 u16 reg = RTL_R32(tp, TxConfig) >> 20;
2215
2216 while ((reg & p->mask) != p->val)
2217 p++;
2218 tp->mac_version = p->mac_version;
2219
2220 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2221 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2222 } else if (!tp->supports_gmii) {
2223 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2224 tp->mac_version = RTL_GIGA_MAC_VER_43;
2225 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2226 tp->mac_version = RTL_GIGA_MAC_VER_47;
2227 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2228 tp->mac_version = RTL_GIGA_MAC_VER_48;
2229 }
2230 }
2231
2232 struct phy_reg {
2233 u16 reg;
2234 u16 val;
2235 };
2236
2237 static void __rtl_writephy_batch(struct rtl8169_private *tp,
2238 const struct phy_reg *regs, int len)
2239 {
2240 while (len-- > 0) {
2241 rtl_writephy(tp, regs->reg, regs->val);
2242 regs++;
2243 }
2244 }
2245
2246 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a))
2247
2248 static void rtl_release_firmware(struct rtl8169_private *tp)
2249 {
2250 if (tp->rtl_fw) {
2251 rtl_fw_release_firmware(tp->rtl_fw);
2252 kfree(tp->rtl_fw);
2253 tp->rtl_fw = NULL;
2254 }
2255 }
2256
2257 static void rtl_apply_firmware(struct rtl8169_private *tp)
2258 {
2259 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2260 if (tp->rtl_fw)
2261 rtl_fw_write_firmware(tp, tp->rtl_fw);
2262 }
2263
2264 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2265 {
2266 if (rtl_readphy(tp, reg) != val)
2267 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2268 else
2269 rtl_apply_firmware(tp);
2270 }
2271
2272 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2273 {
2274 /* Adjust EEE LED frequency */
2275 if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2276 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2277
2278 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);
2279 }
2280
2281 static void rtl8125_config_eee_mac(struct rtl8169_private *tp)
2282 {
2283 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2284 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2285 }
2286
2287 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2288 {
2289 struct phy_device *phydev = tp->phydev;
2290
2291 phy_write(phydev, 0x1f, 0x0007);
2292 phy_write(phydev, 0x1e, 0x0020);
2293 phy_set_bits(phydev, 0x15, BIT(8));
2294
2295 phy_write(phydev, 0x1f, 0x0005);
2296 phy_write(phydev, 0x05, 0x8b85);
2297 phy_set_bits(phydev, 0x06, BIT(13));
2298
2299 phy_write(phydev, 0x1f, 0x0000);
2300 }
2301
2302 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2303 {
2304 phy_modify_paged(tp->phydev, 0x0a43, 0x11, 0, BIT(4));
2305 }
2306
2307 static void rtl8168h_config_eee_phy(struct rtl8169_private *tp)
2308 {
2309 struct phy_device *phydev = tp->phydev;
2310
2311 rtl8168g_config_eee_phy(tp);
2312
2313 phy_modify_paged(phydev, 0xa4a, 0x11, 0x0000, 0x0200);
2314 phy_modify_paged(phydev, 0xa42, 0x14, 0x0000, 0x0080);
2315 }
2316
2317 static void rtl8125_config_eee_phy(struct rtl8169_private *tp)
2318 {
2319 struct phy_device *phydev = tp->phydev;
2320
2321 rtl8168h_config_eee_phy(tp);
2322
2323 phy_modify_paged(phydev, 0xa6d, 0x12, 0x0001, 0x0000);
2324 phy_modify_paged(phydev, 0xa6d, 0x14, 0x0010, 0x0000);
2325 }
2326
2327 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2328 {
2329 static const struct phy_reg phy_reg_init[] = {
2330 { 0x1f, 0x0001 },
2331 { 0x06, 0x006e },
2332 { 0x08, 0x0708 },
2333 { 0x15, 0x4000 },
2334 { 0x18, 0x65c7 },
2335
2336 { 0x1f, 0x0001 },
2337 { 0x03, 0x00a1 },
2338 { 0x02, 0x0008 },
2339 { 0x01, 0x0120 },
2340 { 0x00, 0x1000 },
2341 { 0x04, 0x0800 },
2342 { 0x04, 0x0000 },
2343
2344 { 0x03, 0xff41 },
2345 { 0x02, 0xdf60 },
2346 { 0x01, 0x0140 },
2347 { 0x00, 0x0077 },
2348 { 0x04, 0x7800 },
2349 { 0x04, 0x7000 },
2350
2351 { 0x03, 0x802f },
2352 { 0x02, 0x4f02 },
2353 { 0x01, 0x0409 },
2354 { 0x00, 0xf0f9 },
2355 { 0x04, 0x9800 },
2356 { 0x04, 0x9000 },
2357
2358 { 0x03, 0xdf01 },
2359 { 0x02, 0xdf20 },
2360 { 0x01, 0xff95 },
2361 { 0x00, 0xba00 },
2362 { 0x04, 0xa800 },
2363 { 0x04, 0xa000 },
2364
2365 { 0x03, 0xff41 },
2366 { 0x02, 0xdf20 },
2367 { 0x01, 0x0140 },
2368 { 0x00, 0x00bb },
2369 { 0x04, 0xb800 },
2370 { 0x04, 0xb000 },
2371
2372 { 0x03, 0xdf41 },
2373 { 0x02, 0xdc60 },
2374 { 0x01, 0x6340 },
2375 { 0x00, 0x007d },
2376 { 0x04, 0xd800 },
2377 { 0x04, 0xd000 },
2378
2379 { 0x03, 0xdf01 },
2380 { 0x02, 0xdf20 },
2381 { 0x01, 0x100a },
2382 { 0x00, 0xa0ff },
2383 { 0x04, 0xf800 },
2384 { 0x04, 0xf000 },
2385
2386 { 0x1f, 0x0000 },
2387 { 0x0b, 0x0000 },
2388 { 0x00, 0x9200 }
2389 };
2390
2391 rtl_writephy_batch(tp, phy_reg_init);
2392 }
2393
2394 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2395 {
2396 static const struct phy_reg phy_reg_init[] = {
2397 { 0x1f, 0x0002 },
2398 { 0x01, 0x90d0 },
2399 { 0x1f, 0x0000 }
2400 };
2401
2402 rtl_writephy_batch(tp, phy_reg_init);
2403 }
2404
2405 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2406 {
2407 struct pci_dev *pdev = tp->pci_dev;
2408
2409 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2410 (pdev->subsystem_device != 0xe000))
2411 return;
2412
2413 rtl_writephy(tp, 0x1f, 0x0001);
2414 rtl_writephy(tp, 0x10, 0xf01b);
2415 rtl_writephy(tp, 0x1f, 0x0000);
2416 }
2417
2418 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2419 {
2420 static const struct phy_reg phy_reg_init[] = {
2421 { 0x1f, 0x0001 },
2422 { 0x04, 0x0000 },
2423 { 0x03, 0x00a1 },
2424 { 0x02, 0x0008 },
2425 { 0x01, 0x0120 },
2426 { 0x00, 0x1000 },
2427 { 0x04, 0x0800 },
2428 { 0x04, 0x9000 },
2429 { 0x03, 0x802f },
2430 { 0x02, 0x4f02 },
2431 { 0x01, 0x0409 },
2432 { 0x00, 0xf099 },
2433 { 0x04, 0x9800 },
2434 { 0x04, 0xa000 },
2435 { 0x03, 0xdf01 },
2436 { 0x02, 0xdf20 },
2437 { 0x01, 0xff95 },
2438 { 0x00, 0xba00 },
2439 { 0x04, 0xa800 },
2440 { 0x04, 0xf000 },
2441 { 0x03, 0xdf01 },
2442 { 0x02, 0xdf20 },
2443 { 0x01, 0x101a },
2444 { 0x00, 0xa0ff },
2445 { 0x04, 0xf800 },
2446 { 0x04, 0x0000 },
2447 { 0x1f, 0x0000 },
2448
2449 { 0x1f, 0x0001 },
2450 { 0x10, 0xf41b },
2451 { 0x14, 0xfb54 },
2452 { 0x18, 0xf5c7 },
2453 { 0x1f, 0x0000 },
2454
2455 { 0x1f, 0x0001 },
2456 { 0x17, 0x0cc0 },
2457 { 0x1f, 0x0000 }
2458 };
2459
2460 rtl_writephy_batch(tp, phy_reg_init);
2461
2462 rtl8169scd_hw_phy_config_quirk(tp);
2463 }
2464
2465 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2466 {
2467 static const struct phy_reg phy_reg_init[] = {
2468 { 0x1f, 0x0001 },
2469 { 0x04, 0x0000 },
2470 { 0x03, 0x00a1 },
2471 { 0x02, 0x0008 },
2472 { 0x01, 0x0120 },
2473 { 0x00, 0x1000 },
2474 { 0x04, 0x0800 },
2475 { 0x04, 0x9000 },
2476 { 0x03, 0x802f },
2477 { 0x02, 0x4f02 },
2478 { 0x01, 0x0409 },
2479 { 0x00, 0xf099 },
2480 { 0x04, 0x9800 },
2481 { 0x04, 0xa000 },
2482 { 0x03, 0xdf01 },
2483 { 0x02, 0xdf20 },
2484 { 0x01, 0xff95 },
2485 { 0x00, 0xba00 },
2486 { 0x04, 0xa800 },
2487 { 0x04, 0xf000 },
2488 { 0x03, 0xdf01 },
2489 { 0x02, 0xdf20 },
2490 { 0x01, 0x101a },
2491 { 0x00, 0xa0ff },
2492 { 0x04, 0xf800 },
2493 { 0x04, 0x0000 },
2494 { 0x1f, 0x0000 },
2495
2496 { 0x1f, 0x0001 },
2497 { 0x0b, 0x8480 },
2498 { 0x1f, 0x0000 },
2499
2500 { 0x1f, 0x0001 },
2501 { 0x18, 0x67c7 },
2502 { 0x04, 0x2000 },
2503 { 0x03, 0x002f },
2504 { 0x02, 0x4360 },
2505 { 0x01, 0x0109 },
2506 { 0x00, 0x3022 },
2507 { 0x04, 0x2800 },
2508 { 0x1f, 0x0000 },
2509
2510 { 0x1f, 0x0001 },
2511 { 0x17, 0x0cc0 },
2512 { 0x1f, 0x0000 }
2513 };
2514
2515 rtl_writephy_batch(tp, phy_reg_init);
2516 }
2517
2518 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2519 {
2520 static const struct phy_reg phy_reg_init[] = {
2521 { 0x10, 0xf41b },
2522 { 0x1f, 0x0000 }
2523 };
2524
2525 rtl_writephy(tp, 0x1f, 0x0001);
2526 rtl_patchphy(tp, 0x16, 1 << 0);
2527
2528 rtl_writephy_batch(tp, phy_reg_init);
2529 }
2530
2531 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2532 {
2533 static const struct phy_reg phy_reg_init[] = {
2534 { 0x1f, 0x0001 },
2535 { 0x10, 0xf41b },
2536 { 0x1f, 0x0000 }
2537 };
2538
2539 rtl_writephy_batch(tp, phy_reg_init);
2540 }
2541
2542 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2543 {
2544 static const struct phy_reg phy_reg_init[] = {
2545 { 0x1f, 0x0000 },
2546 { 0x1d, 0x0f00 },
2547 { 0x1f, 0x0002 },
2548 { 0x0c, 0x1ec8 },
2549 { 0x1f, 0x0000 }
2550 };
2551
2552 rtl_writephy_batch(tp, phy_reg_init);
2553 }
2554
2555 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2556 {
2557 static const struct phy_reg phy_reg_init[] = {
2558 { 0x1f, 0x0001 },
2559 { 0x1d, 0x3d98 },
2560 { 0x1f, 0x0000 }
2561 };
2562
2563 rtl_writephy(tp, 0x1f, 0x0000);
2564 rtl_patchphy(tp, 0x14, 1 << 5);
2565 rtl_patchphy(tp, 0x0d, 1 << 5);
2566
2567 rtl_writephy_batch(tp, phy_reg_init);
2568 }
2569
2570 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2571 {
2572 static const struct phy_reg phy_reg_init[] = {
2573 { 0x1f, 0x0001 },
2574 { 0x12, 0x2300 },
2575 { 0x1f, 0x0002 },
2576 { 0x00, 0x88d4 },
2577 { 0x01, 0x82b1 },
2578 { 0x03, 0x7002 },
2579 { 0x08, 0x9e30 },
2580 { 0x09, 0x01f0 },
2581 { 0x0a, 0x5500 },
2582 { 0x0c, 0x00c8 },
2583 { 0x1f, 0x0003 },
2584 { 0x12, 0xc096 },
2585 { 0x16, 0x000a },
2586 { 0x1f, 0x0000 },
2587 { 0x1f, 0x0000 },
2588 { 0x09, 0x2000 },
2589 { 0x09, 0x0000 }
2590 };
2591
2592 rtl_writephy_batch(tp, phy_reg_init);
2593
2594 rtl_patchphy(tp, 0x14, 1 << 5);
2595 rtl_patchphy(tp, 0x0d, 1 << 5);
2596 rtl_writephy(tp, 0x1f, 0x0000);
2597 }
2598
2599 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2600 {
2601 static const struct phy_reg phy_reg_init[] = {
2602 { 0x1f, 0x0001 },
2603 { 0x12, 0x2300 },
2604 { 0x03, 0x802f },
2605 { 0x02, 0x4f02 },
2606 { 0x01, 0x0409 },
2607 { 0x00, 0xf099 },
2608 { 0x04, 0x9800 },
2609 { 0x04, 0x9000 },
2610 { 0x1d, 0x3d98 },
2611 { 0x1f, 0x0002 },
2612 { 0x0c, 0x7eb8 },
2613 { 0x06, 0x0761 },
2614 { 0x1f, 0x0003 },
2615 { 0x16, 0x0f0a },
2616 { 0x1f, 0x0000 }
2617 };
2618
2619 rtl_writephy_batch(tp, phy_reg_init);
2620
2621 rtl_patchphy(tp, 0x16, 1 << 0);
2622 rtl_patchphy(tp, 0x14, 1 << 5);
2623 rtl_patchphy(tp, 0x0d, 1 << 5);
2624 rtl_writephy(tp, 0x1f, 0x0000);
2625 }
2626
2627 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2628 {
2629 static const struct phy_reg phy_reg_init[] = {
2630 { 0x1f, 0x0001 },
2631 { 0x12, 0x2300 },
2632 { 0x1d, 0x3d98 },
2633 { 0x1f, 0x0002 },
2634 { 0x0c, 0x7eb8 },
2635 { 0x06, 0x5461 },
2636 { 0x1f, 0x0003 },
2637 { 0x16, 0x0f0a },
2638 { 0x1f, 0x0000 }
2639 };
2640
2641 rtl_writephy_batch(tp, phy_reg_init);
2642
2643 rtl_patchphy(tp, 0x16, 1 << 0);
2644 rtl_patchphy(tp, 0x14, 1 << 5);
2645 rtl_patchphy(tp, 0x0d, 1 << 5);
2646 rtl_writephy(tp, 0x1f, 0x0000);
2647 }
2648
2649 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2650 {
2651 rtl8168c_3_hw_phy_config(tp);
2652 }
2653
2654 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
2655 /* Channel Estimation */
2656 { 0x1f, 0x0001 },
2657 { 0x06, 0x4064 },
2658 { 0x07, 0x2863 },
2659 { 0x08, 0x059c },
2660 { 0x09, 0x26b4 },
2661 { 0x0a, 0x6a19 },
2662 { 0x0b, 0xdcc8 },
2663 { 0x10, 0xf06d },
2664 { 0x14, 0x7f68 },
2665 { 0x18, 0x7fd9 },
2666 { 0x1c, 0xf0ff },
2667 { 0x1d, 0x3d9c },
2668 { 0x1f, 0x0003 },
2669 { 0x12, 0xf49f },
2670 { 0x13, 0x070b },
2671 { 0x1a, 0x05ad },
2672 { 0x14, 0x94c0 },
2673
2674 /*
2675 * Tx Error Issue
2676 * Enhance line driver power
2677 */
2678 { 0x1f, 0x0002 },
2679 { 0x06, 0x5561 },
2680 { 0x1f, 0x0005 },
2681 { 0x05, 0x8332 },
2682 { 0x06, 0x5561 },
2683
2684 /*
2685 * Can not link to 1Gbps with bad cable
2686 * Decrease SNR threshold form 21.07dB to 19.04dB
2687 */
2688 { 0x1f, 0x0001 },
2689 { 0x17, 0x0cc0 },
2690
2691 { 0x1f, 0x0000 },
2692 { 0x0d, 0xf880 }
2693 };
2694
2695 static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = {
2696 { 0x1f, 0x0002 },
2697 { 0x05, 0x669a },
2698 { 0x1f, 0x0005 },
2699 { 0x05, 0x8330 },
2700 { 0x06, 0x669a },
2701 { 0x1f, 0x0002 }
2702 };
2703
2704 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2705 {
2706 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2707
2708 /*
2709 * Rx Error Issue
2710 * Fine Tune Switching regulator parameter
2711 */
2712 rtl_writephy(tp, 0x1f, 0x0002);
2713 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2714 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2715
2716 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2717 int val;
2718
2719 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2720
2721 val = rtl_readphy(tp, 0x0d);
2722
2723 if ((val & 0x00ff) != 0x006c) {
2724 static const u32 set[] = {
2725 0x0065, 0x0066, 0x0067, 0x0068,
2726 0x0069, 0x006a, 0x006b, 0x006c
2727 };
2728 int i;
2729
2730 rtl_writephy(tp, 0x1f, 0x0002);
2731
2732 val &= 0xff00;
2733 for (i = 0; i < ARRAY_SIZE(set); i++)
2734 rtl_writephy(tp, 0x0d, val | set[i]);
2735 }
2736 } else {
2737 static const struct phy_reg phy_reg_init[] = {
2738 { 0x1f, 0x0002 },
2739 { 0x05, 0x6662 },
2740 { 0x1f, 0x0005 },
2741 { 0x05, 0x8330 },
2742 { 0x06, 0x6662 }
2743 };
2744
2745 rtl_writephy_batch(tp, phy_reg_init);
2746 }
2747
2748 /* RSET couple improve */
2749 rtl_writephy(tp, 0x1f, 0x0002);
2750 rtl_patchphy(tp, 0x0d, 0x0300);
2751 rtl_patchphy(tp, 0x0f, 0x0010);
2752
2753 /* Fine tune PLL performance */
2754 rtl_writephy(tp, 0x1f, 0x0002);
2755 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2756 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2757
2758 rtl_writephy(tp, 0x1f, 0x0005);
2759 rtl_writephy(tp, 0x05, 0x001b);
2760
2761 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2762
2763 rtl_writephy(tp, 0x1f, 0x0000);
2764 }
2765
2766 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2767 {
2768 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2769
2770 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2771 int val;
2772
2773 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2774
2775 val = rtl_readphy(tp, 0x0d);
2776 if ((val & 0x00ff) != 0x006c) {
2777 static const u32 set[] = {
2778 0x0065, 0x0066, 0x0067, 0x0068,
2779 0x0069, 0x006a, 0x006b, 0x006c
2780 };
2781 int i;
2782
2783 rtl_writephy(tp, 0x1f, 0x0002);
2784
2785 val &= 0xff00;
2786 for (i = 0; i < ARRAY_SIZE(set); i++)
2787 rtl_writephy(tp, 0x0d, val | set[i]);
2788 }
2789 } else {
2790 static const struct phy_reg phy_reg_init[] = {
2791 { 0x1f, 0x0002 },
2792 { 0x05, 0x2642 },
2793 { 0x1f, 0x0005 },
2794 { 0x05, 0x8330 },
2795 { 0x06, 0x2642 }
2796 };
2797
2798 rtl_writephy_batch(tp, phy_reg_init);
2799 }
2800
2801 /* Fine tune PLL performance */
2802 rtl_writephy(tp, 0x1f, 0x0002);
2803 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2804 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2805
2806 /* Switching regulator Slew rate */
2807 rtl_writephy(tp, 0x1f, 0x0002);
2808 rtl_patchphy(tp, 0x0f, 0x0017);
2809
2810 rtl_writephy(tp, 0x1f, 0x0005);
2811 rtl_writephy(tp, 0x05, 0x001b);
2812
2813 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2814
2815 rtl_writephy(tp, 0x1f, 0x0000);
2816 }
2817
2818 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2819 {
2820 static const struct phy_reg phy_reg_init[] = {
2821 { 0x1f, 0x0002 },
2822 { 0x10, 0x0008 },
2823 { 0x0d, 0x006c },
2824
2825 { 0x1f, 0x0000 },
2826 { 0x0d, 0xf880 },
2827
2828 { 0x1f, 0x0001 },
2829 { 0x17, 0x0cc0 },
2830
2831 { 0x1f, 0x0001 },
2832 { 0x0b, 0xa4d8 },
2833 { 0x09, 0x281c },
2834 { 0x07, 0x2883 },
2835 { 0x0a, 0x6b35 },
2836 { 0x1d, 0x3da4 },
2837 { 0x1c, 0xeffd },
2838 { 0x14, 0x7f52 },
2839 { 0x18, 0x7fc6 },
2840 { 0x08, 0x0601 },
2841 { 0x06, 0x4063 },
2842 { 0x10, 0xf074 },
2843 { 0x1f, 0x0003 },
2844 { 0x13, 0x0789 },
2845 { 0x12, 0xf4bd },
2846 { 0x1a, 0x04fd },
2847 { 0x14, 0x84b0 },
2848 { 0x1f, 0x0000 },
2849 { 0x00, 0x9200 },
2850
2851 { 0x1f, 0x0005 },
2852 { 0x01, 0x0340 },
2853 { 0x1f, 0x0001 },
2854 { 0x04, 0x4000 },
2855 { 0x03, 0x1d21 },
2856 { 0x02, 0x0c32 },
2857 { 0x01, 0x0200 },
2858 { 0x00, 0x5554 },
2859 { 0x04, 0x4800 },
2860 { 0x04, 0x4000 },
2861 { 0x04, 0xf000 },
2862 { 0x03, 0xdf01 },
2863 { 0x02, 0xdf20 },
2864 { 0x01, 0x101a },
2865 { 0x00, 0xa0ff },
2866 { 0x04, 0xf800 },
2867 { 0x04, 0xf000 },
2868 { 0x1f, 0x0000 },
2869
2870 { 0x1f, 0x0007 },
2871 { 0x1e, 0x0023 },
2872 { 0x16, 0x0000 },
2873 { 0x1f, 0x0000 }
2874 };
2875
2876 rtl_writephy_batch(tp, phy_reg_init);
2877 }
2878
2879 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2880 {
2881 static const struct phy_reg phy_reg_init[] = {
2882 { 0x1f, 0x0001 },
2883 { 0x17, 0x0cc0 },
2884
2885 { 0x1f, 0x0007 },
2886 { 0x1e, 0x002d },
2887 { 0x18, 0x0040 },
2888 { 0x1f, 0x0000 }
2889 };
2890
2891 rtl_writephy_batch(tp, phy_reg_init);
2892 rtl_patchphy(tp, 0x0d, 1 << 5);
2893 }
2894
2895 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2896 {
2897 static const struct phy_reg phy_reg_init[] = {
2898 /* Enable Delay cap */
2899 { 0x1f, 0x0005 },
2900 { 0x05, 0x8b80 },
2901 { 0x06, 0xc896 },
2902 { 0x1f, 0x0000 },
2903
2904 /* Channel estimation fine tune */
2905 { 0x1f, 0x0001 },
2906 { 0x0b, 0x6c20 },
2907 { 0x07, 0x2872 },
2908 { 0x1c, 0xefff },
2909 { 0x1f, 0x0003 },
2910 { 0x14, 0x6420 },
2911 { 0x1f, 0x0000 },
2912
2913 /* Update PFM & 10M TX idle timer */
2914 { 0x1f, 0x0007 },
2915 { 0x1e, 0x002f },
2916 { 0x15, 0x1919 },
2917 { 0x1f, 0x0000 },
2918
2919 { 0x1f, 0x0007 },
2920 { 0x1e, 0x00ac },
2921 { 0x18, 0x0006 },
2922 { 0x1f, 0x0000 }
2923 };
2924
2925 rtl_apply_firmware(tp);
2926
2927 rtl_writephy_batch(tp, phy_reg_init);
2928
2929 /* DCO enable for 10M IDLE Power */
2930 rtl_writephy(tp, 0x1f, 0x0007);
2931 rtl_writephy(tp, 0x1e, 0x0023);
2932 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
2933 rtl_writephy(tp, 0x1f, 0x0000);
2934
2935 /* For impedance matching */
2936 rtl_writephy(tp, 0x1f, 0x0002);
2937 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
2938 rtl_writephy(tp, 0x1f, 0x0000);
2939
2940 /* PHY auto speed down */
2941 rtl_writephy(tp, 0x1f, 0x0007);
2942 rtl_writephy(tp, 0x1e, 0x002d);
2943 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
2944 rtl_writephy(tp, 0x1f, 0x0000);
2945 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
2946
2947 rtl_writephy(tp, 0x1f, 0x0005);
2948 rtl_writephy(tp, 0x05, 0x8b86);
2949 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
2950 rtl_writephy(tp, 0x1f, 0x0000);
2951
2952 rtl_writephy(tp, 0x1f, 0x0005);
2953 rtl_writephy(tp, 0x05, 0x8b85);
2954 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
2955 rtl_writephy(tp, 0x1f, 0x0007);
2956 rtl_writephy(tp, 0x1e, 0x0020);
2957 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
2958 rtl_writephy(tp, 0x1f, 0x0006);
2959 rtl_writephy(tp, 0x00, 0x5a00);
2960 rtl_writephy(tp, 0x1f, 0x0000);
2961 rtl_writephy(tp, 0x0d, 0x0007);
2962 rtl_writephy(tp, 0x0e, 0x003c);
2963 rtl_writephy(tp, 0x0d, 0x4007);
2964 rtl_writephy(tp, 0x0e, 0x0000);
2965 rtl_writephy(tp, 0x0d, 0x0000);
2966 }
2967
2968 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
2969 {
2970 const u16 w[] = {
2971 addr[0] | (addr[1] << 8),
2972 addr[2] | (addr[3] << 8),
2973 addr[4] | (addr[5] << 8)
2974 };
2975
2976 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
2977 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
2978 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
2979 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
2980 }
2981
2982 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2983 {
2984 static const struct phy_reg phy_reg_init[] = {
2985 /* Enable Delay cap */
2986 { 0x1f, 0x0004 },
2987 { 0x1f, 0x0007 },
2988 { 0x1e, 0x00ac },
2989 { 0x18, 0x0006 },
2990 { 0x1f, 0x0002 },
2991 { 0x1f, 0x0000 },
2992 { 0x1f, 0x0000 },
2993
2994 /* Channel estimation fine tune */
2995 { 0x1f, 0x0003 },
2996 { 0x09, 0xa20f },
2997 { 0x1f, 0x0000 },
2998 { 0x1f, 0x0000 },
2999
3000 /* Green Setting */
3001 { 0x1f, 0x0005 },
3002 { 0x05, 0x8b5b },
3003 { 0x06, 0x9222 },
3004 { 0x05, 0x8b6d },
3005 { 0x06, 0x8000 },
3006 { 0x05, 0x8b76 },
3007 { 0x06, 0x8000 },
3008 { 0x1f, 0x0000 }
3009 };
3010
3011 rtl_apply_firmware(tp);
3012
3013 rtl_writephy_batch(tp, phy_reg_init);
3014
3015 /* For 4-corner performance improve */
3016 rtl_writephy(tp, 0x1f, 0x0005);
3017 rtl_writephy(tp, 0x05, 0x8b80);
3018 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3019 rtl_writephy(tp, 0x1f, 0x0000);
3020
3021 /* PHY auto speed down */
3022 rtl_writephy(tp, 0x1f, 0x0004);
3023 rtl_writephy(tp, 0x1f, 0x0007);
3024 rtl_writephy(tp, 0x1e, 0x002d);
3025 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3026 rtl_writephy(tp, 0x1f, 0x0002);
3027 rtl_writephy(tp, 0x1f, 0x0000);
3028 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3029
3030 /* improve 10M EEE waveform */
3031 rtl_writephy(tp, 0x1f, 0x0005);
3032 rtl_writephy(tp, 0x05, 0x8b86);
3033 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3034 rtl_writephy(tp, 0x1f, 0x0000);
3035
3036 /* Improve 2-pair detection performance */
3037 rtl_writephy(tp, 0x1f, 0x0005);
3038 rtl_writephy(tp, 0x05, 0x8b85);
3039 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3040 rtl_writephy(tp, 0x1f, 0x0000);
3041
3042 rtl8168f_config_eee_phy(tp);
3043 rtl_enable_eee(tp);
3044
3045 /* Green feature */
3046 rtl_writephy(tp, 0x1f, 0x0003);
3047 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3048 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3049 rtl_writephy(tp, 0x1f, 0x0000);
3050 rtl_writephy(tp, 0x1f, 0x0005);
3051 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3052 rtl_writephy(tp, 0x1f, 0x0000);
3053
3054 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3055 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3056 }
3057
3058 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3059 {
3060 /* For 4-corner performance improve */
3061 rtl_writephy(tp, 0x1f, 0x0005);
3062 rtl_writephy(tp, 0x05, 0x8b80);
3063 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3064 rtl_writephy(tp, 0x1f, 0x0000);
3065
3066 /* PHY auto speed down */
3067 rtl_writephy(tp, 0x1f, 0x0007);
3068 rtl_writephy(tp, 0x1e, 0x002d);
3069 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3070 rtl_writephy(tp, 0x1f, 0x0000);
3071 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3072
3073 /* Improve 10M EEE waveform */
3074 rtl_writephy(tp, 0x1f, 0x0005);
3075 rtl_writephy(tp, 0x05, 0x8b86);
3076 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3077 rtl_writephy(tp, 0x1f, 0x0000);
3078
3079 rtl8168f_config_eee_phy(tp);
3080 rtl_enable_eee(tp);
3081 }
3082
3083 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3084 {
3085 static const struct phy_reg phy_reg_init[] = {
3086 /* Channel estimation fine tune */
3087 { 0x1f, 0x0003 },
3088 { 0x09, 0xa20f },
3089 { 0x1f, 0x0000 },
3090
3091 /* Modify green table for giga & fnet */
3092 { 0x1f, 0x0005 },
3093 { 0x05, 0x8b55 },
3094 { 0x06, 0x0000 },
3095 { 0x05, 0x8b5e },
3096 { 0x06, 0x0000 },
3097 { 0x05, 0x8b67 },
3098 { 0x06, 0x0000 },
3099 { 0x05, 0x8b70 },
3100 { 0x06, 0x0000 },
3101 { 0x1f, 0x0000 },
3102 { 0x1f, 0x0007 },
3103 { 0x1e, 0x0078 },
3104 { 0x17, 0x0000 },
3105 { 0x19, 0x00fb },
3106 { 0x1f, 0x0000 },
3107
3108 /* Modify green table for 10M */
3109 { 0x1f, 0x0005 },
3110 { 0x05, 0x8b79 },
3111 { 0x06, 0xaa00 },
3112 { 0x1f, 0x0000 },
3113
3114 /* Disable hiimpedance detection (RTCT) */
3115 { 0x1f, 0x0003 },
3116 { 0x01, 0x328a },
3117 { 0x1f, 0x0000 }
3118 };
3119
3120 rtl_apply_firmware(tp);
3121
3122 rtl_writephy_batch(tp, phy_reg_init);
3123
3124 rtl8168f_hw_phy_config(tp);
3125
3126 /* Improve 2-pair detection performance */
3127 rtl_writephy(tp, 0x1f, 0x0005);
3128 rtl_writephy(tp, 0x05, 0x8b85);
3129 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3130 rtl_writephy(tp, 0x1f, 0x0000);
3131 }
3132
3133 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3134 {
3135 rtl_apply_firmware(tp);
3136
3137 rtl8168f_hw_phy_config(tp);
3138 }
3139
3140 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3141 {
3142 static const struct phy_reg phy_reg_init[] = {
3143 /* Channel estimation fine tune */
3144 { 0x1f, 0x0003 },
3145 { 0x09, 0xa20f },
3146 { 0x1f, 0x0000 },
3147
3148 /* Modify green table for giga & fnet */
3149 { 0x1f, 0x0005 },
3150 { 0x05, 0x8b55 },
3151 { 0x06, 0x0000 },
3152 { 0x05, 0x8b5e },
3153 { 0x06, 0x0000 },
3154 { 0x05, 0x8b67 },
3155 { 0x06, 0x0000 },
3156 { 0x05, 0x8b70 },
3157 { 0x06, 0x0000 },
3158 { 0x1f, 0x0000 },
3159 { 0x1f, 0x0007 },
3160 { 0x1e, 0x0078 },
3161 { 0x17, 0x0000 },
3162 { 0x19, 0x00aa },
3163 { 0x1f, 0x0000 },
3164
3165 /* Modify green table for 10M */
3166 { 0x1f, 0x0005 },
3167 { 0x05, 0x8b79 },
3168 { 0x06, 0xaa00 },
3169 { 0x1f, 0x0000 },
3170
3171 /* Disable hiimpedance detection (RTCT) */
3172 { 0x1f, 0x0003 },
3173 { 0x01, 0x328a },
3174 { 0x1f, 0x0000 }
3175 };
3176
3177
3178 rtl_apply_firmware(tp);
3179
3180 rtl8168f_hw_phy_config(tp);
3181
3182 /* Improve 2-pair detection performance */
3183 rtl_writephy(tp, 0x1f, 0x0005);
3184 rtl_writephy(tp, 0x05, 0x8b85);
3185 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3186 rtl_writephy(tp, 0x1f, 0x0000);
3187
3188 rtl_writephy_batch(tp, phy_reg_init);
3189
3190 /* Modify green table for giga */
3191 rtl_writephy(tp, 0x1f, 0x0005);
3192 rtl_writephy(tp, 0x05, 0x8b54);
3193 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3194 rtl_writephy(tp, 0x05, 0x8b5d);
3195 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3196 rtl_writephy(tp, 0x05, 0x8a7c);
3197 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3198 rtl_writephy(tp, 0x05, 0x8a7f);
3199 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3200 rtl_writephy(tp, 0x05, 0x8a82);
3201 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3202 rtl_writephy(tp, 0x05, 0x8a85);
3203 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3204 rtl_writephy(tp, 0x05, 0x8a88);
3205 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3206 rtl_writephy(tp, 0x1f, 0x0000);
3207
3208 /* uc same-seed solution */
3209 rtl_writephy(tp, 0x1f, 0x0005);
3210 rtl_writephy(tp, 0x05, 0x8b85);
3211 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3212 rtl_writephy(tp, 0x1f, 0x0000);
3213
3214 /* Green feature */
3215 rtl_writephy(tp, 0x1f, 0x0003);
3216 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3217 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3218 rtl_writephy(tp, 0x1f, 0x0000);
3219 }
3220
3221 static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3222 {
3223 phy_modify_paged(tp->phydev, 0x0a43, 0x10, BIT(2), 0);
3224 }
3225
3226 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3227 {
3228 struct phy_device *phydev = tp->phydev;
3229
3230 phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0);
3231 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6));
3232 phy_write(phydev, 0x1f, 0x0a43);
3233 phy_write(phydev, 0x13, 0x8084);
3234 phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13));
3235 phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0));
3236
3237 phy_write(phydev, 0x1f, 0x0000);
3238 }
3239
3240 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3241 {
3242 int ret;
3243
3244 rtl_apply_firmware(tp);
3245
3246 ret = phy_read_paged(tp->phydev, 0x0a46, 0x10);
3247 if (ret & BIT(8))
3248 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, BIT(15), 0);
3249 else
3250 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, 0, BIT(15));
3251
3252 ret = phy_read_paged(tp->phydev, 0x0a46, 0x13);
3253 if (ret & BIT(8))
3254 phy_modify_paged(tp->phydev, 0x0c41, 0x15, 0, BIT(1));
3255 else
3256 phy_modify_paged(tp->phydev, 0x0c41, 0x15, BIT(1), 0);
3257
3258 /* Enable PHY auto speed down */
3259 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3260
3261 rtl8168g_phy_adjust_10m_aldps(tp);
3262
3263 /* EEE auto-fallback function */
3264 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3265
3266 /* Enable UC LPF tune function */
3267 rtl_writephy(tp, 0x1f, 0x0a43);
3268 rtl_writephy(tp, 0x13, 0x8012);
3269 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3270
3271 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3272
3273 /* Improve SWR Efficiency */
3274 rtl_writephy(tp, 0x1f, 0x0bcd);
3275 rtl_writephy(tp, 0x14, 0x5065);
3276 rtl_writephy(tp, 0x14, 0xd065);
3277 rtl_writephy(tp, 0x1f, 0x0bc8);
3278 rtl_writephy(tp, 0x11, 0x5655);
3279 rtl_writephy(tp, 0x1f, 0x0bcd);
3280 rtl_writephy(tp, 0x14, 0x1065);
3281 rtl_writephy(tp, 0x14, 0x9065);
3282 rtl_writephy(tp, 0x14, 0x1065);
3283 rtl_writephy(tp, 0x1f, 0x0000);
3284
3285 rtl8168g_disable_aldps(tp);
3286 rtl8168g_config_eee_phy(tp);
3287 rtl_enable_eee(tp);
3288 }
3289
3290 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3291 {
3292 rtl_apply_firmware(tp);
3293 rtl8168g_config_eee_phy(tp);
3294 rtl_enable_eee(tp);
3295 }
3296
3297 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3298 {
3299 u16 dout_tapbin;
3300 u32 data;
3301
3302 rtl_apply_firmware(tp);
3303
3304 /* CHN EST parameters adjust - giga master */
3305 rtl_writephy(tp, 0x1f, 0x0a43);
3306 rtl_writephy(tp, 0x13, 0x809b);
3307 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3308 rtl_writephy(tp, 0x13, 0x80a2);
3309 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3310 rtl_writephy(tp, 0x13, 0x80a4);
3311 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3312 rtl_writephy(tp, 0x13, 0x809c);
3313 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3314 rtl_writephy(tp, 0x1f, 0x0000);
3315
3316 /* CHN EST parameters adjust - giga slave */
3317 rtl_writephy(tp, 0x1f, 0x0a43);
3318 rtl_writephy(tp, 0x13, 0x80ad);
3319 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3320 rtl_writephy(tp, 0x13, 0x80b4);
3321 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3322 rtl_writephy(tp, 0x13, 0x80ac);
3323 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3324 rtl_writephy(tp, 0x1f, 0x0000);
3325
3326 /* CHN EST parameters adjust - fnet */
3327 rtl_writephy(tp, 0x1f, 0x0a43);
3328 rtl_writephy(tp, 0x13, 0x808e);
3329 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3330 rtl_writephy(tp, 0x13, 0x8090);
3331 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3332 rtl_writephy(tp, 0x13, 0x8092);
3333 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3334 rtl_writephy(tp, 0x1f, 0x0000);
3335
3336 /* enable R-tune & PGA-retune function */
3337 dout_tapbin = 0;
3338 rtl_writephy(tp, 0x1f, 0x0a46);
3339 data = rtl_readphy(tp, 0x13);
3340 data &= 3;
3341 data <<= 2;
3342 dout_tapbin |= data;
3343 data = rtl_readphy(tp, 0x12);
3344 data &= 0xc000;
3345 data >>= 14;
3346 dout_tapbin |= data;
3347 dout_tapbin = ~(dout_tapbin^0x08);
3348 dout_tapbin <<= 12;
3349 dout_tapbin &= 0xf000;
3350 rtl_writephy(tp, 0x1f, 0x0a43);
3351 rtl_writephy(tp, 0x13, 0x827a);
3352 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3353 rtl_writephy(tp, 0x13, 0x827b);
3354 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3355 rtl_writephy(tp, 0x13, 0x827c);
3356 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3357 rtl_writephy(tp, 0x13, 0x827d);
3358 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3359
3360 rtl_writephy(tp, 0x1f, 0x0a43);
3361 rtl_writephy(tp, 0x13, 0x0811);
3362 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3363 rtl_writephy(tp, 0x1f, 0x0a42);
3364 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3365 rtl_writephy(tp, 0x1f, 0x0000);
3366
3367 /* enable GPHY 10M */
3368 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3369
3370 /* SAR ADC performance */
3371 phy_modify_paged(tp->phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14));
3372
3373 rtl_writephy(tp, 0x1f, 0x0a43);
3374 rtl_writephy(tp, 0x13, 0x803f);
3375 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3376 rtl_writephy(tp, 0x13, 0x8047);
3377 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3378 rtl_writephy(tp, 0x13, 0x804f);
3379 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3380 rtl_writephy(tp, 0x13, 0x8057);
3381 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3382 rtl_writephy(tp, 0x13, 0x805f);
3383 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3384 rtl_writephy(tp, 0x13, 0x8067);
3385 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3386 rtl_writephy(tp, 0x13, 0x806f);
3387 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3388 rtl_writephy(tp, 0x1f, 0x0000);
3389
3390 /* disable phy pfm mode */
3391 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3392
3393 rtl8168g_disable_aldps(tp);
3394 rtl8168h_config_eee_phy(tp);
3395 rtl_enable_eee(tp);
3396 }
3397
3398 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3399 {
3400 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3401 u16 rlen;
3402 u32 data;
3403
3404 rtl_apply_firmware(tp);
3405
3406 /* CHIN EST parameter update */
3407 rtl_writephy(tp, 0x1f, 0x0a43);
3408 rtl_writephy(tp, 0x13, 0x808a);
3409 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3410 rtl_writephy(tp, 0x1f, 0x0000);
3411
3412 /* enable R-tune & PGA-retune function */
3413 rtl_writephy(tp, 0x1f, 0x0a43);
3414 rtl_writephy(tp, 0x13, 0x0811);
3415 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3416 rtl_writephy(tp, 0x1f, 0x0a42);
3417 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3418 rtl_writephy(tp, 0x1f, 0x0000);
3419
3420 /* enable GPHY 10M */
3421 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3422
3423 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3424 data = r8168_mac_ocp_read(tp, 0xdd02);
3425 ioffset_p3 = ((data & 0x80)>>7);
3426 ioffset_p3 <<= 3;
3427
3428 data = r8168_mac_ocp_read(tp, 0xdd00);
3429 ioffset_p3 |= ((data & (0xe000))>>13);
3430 ioffset_p2 = ((data & (0x1e00))>>9);
3431 ioffset_p1 = ((data & (0x01e0))>>5);
3432 ioffset_p0 = ((data & 0x0010)>>4);
3433 ioffset_p0 <<= 3;
3434 ioffset_p0 |= (data & (0x07));
3435 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3436
3437 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3438 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3439 rtl_writephy(tp, 0x1f, 0x0bcf);
3440 rtl_writephy(tp, 0x16, data);
3441 rtl_writephy(tp, 0x1f, 0x0000);
3442 }
3443
3444 /* Modify rlen (TX LPF corner frequency) level */
3445 rtl_writephy(tp, 0x1f, 0x0bcd);
3446 data = rtl_readphy(tp, 0x16);
3447 data &= 0x000f;
3448 rlen = 0;
3449 if (data > 3)
3450 rlen = data - 3;
3451 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3452 rtl_writephy(tp, 0x17, data);
3453 rtl_writephy(tp, 0x1f, 0x0bcd);
3454 rtl_writephy(tp, 0x1f, 0x0000);
3455
3456 /* disable phy pfm mode */
3457 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3458
3459 rtl8168g_disable_aldps(tp);
3460 rtl8168g_config_eee_phy(tp);
3461 rtl_enable_eee(tp);
3462 }
3463
3464 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3465 {
3466 /* Enable PHY auto speed down */
3467 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3468
3469 rtl8168g_phy_adjust_10m_aldps(tp);
3470
3471 /* Enable EEE auto-fallback function */
3472 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3473
3474 /* Enable UC LPF tune function */
3475 rtl_writephy(tp, 0x1f, 0x0a43);
3476 rtl_writephy(tp, 0x13, 0x8012);
3477 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3478 rtl_writephy(tp, 0x1f, 0x0000);
3479
3480 /* set rg_sel_sdm_rate */
3481 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3482
3483 rtl8168g_disable_aldps(tp);
3484 rtl8168g_config_eee_phy(tp);
3485 rtl_enable_eee(tp);
3486 }
3487
3488 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3489 {
3490 rtl8168g_phy_adjust_10m_aldps(tp);
3491
3492 /* Enable UC LPF tune function */
3493 rtl_writephy(tp, 0x1f, 0x0a43);
3494 rtl_writephy(tp, 0x13, 0x8012);
3495 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3496 rtl_writephy(tp, 0x1f, 0x0000);
3497
3498 /* Set rg_sel_sdm_rate */
3499 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3500
3501 /* Channel estimation parameters */
3502 rtl_writephy(tp, 0x1f, 0x0a43);
3503 rtl_writephy(tp, 0x13, 0x80f3);
3504 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3505 rtl_writephy(tp, 0x13, 0x80f0);
3506 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3507 rtl_writephy(tp, 0x13, 0x80ef);
3508 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3509 rtl_writephy(tp, 0x13, 0x80f6);
3510 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3511 rtl_writephy(tp, 0x13, 0x80ec);
3512 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3513 rtl_writephy(tp, 0x13, 0x80ed);
3514 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3515 rtl_writephy(tp, 0x13, 0x80f2);
3516 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3517 rtl_writephy(tp, 0x13, 0x80f4);
3518 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3519 rtl_writephy(tp, 0x1f, 0x0a43);
3520 rtl_writephy(tp, 0x13, 0x8110);
3521 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3522 rtl_writephy(tp, 0x13, 0x810f);
3523 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3524 rtl_writephy(tp, 0x13, 0x8111);
3525 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3526 rtl_writephy(tp, 0x13, 0x8113);
3527 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3528 rtl_writephy(tp, 0x13, 0x8115);
3529 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3530 rtl_writephy(tp, 0x13, 0x810e);
3531 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3532 rtl_writephy(tp, 0x13, 0x810c);
3533 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3534 rtl_writephy(tp, 0x13, 0x810b);
3535 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3536 rtl_writephy(tp, 0x1f, 0x0a43);
3537 rtl_writephy(tp, 0x13, 0x80d1);
3538 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3539 rtl_writephy(tp, 0x13, 0x80cd);
3540 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3541 rtl_writephy(tp, 0x13, 0x80d3);
3542 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3543 rtl_writephy(tp, 0x13, 0x80d5);
3544 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3545 rtl_writephy(tp, 0x13, 0x80d7);
3546 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3547
3548 /* Force PWM-mode */
3549 rtl_writephy(tp, 0x1f, 0x0bcd);
3550 rtl_writephy(tp, 0x14, 0x5065);
3551 rtl_writephy(tp, 0x14, 0xd065);
3552 rtl_writephy(tp, 0x1f, 0x0bc8);
3553 rtl_writephy(tp, 0x12, 0x00ed);
3554 rtl_writephy(tp, 0x1f, 0x0bcd);
3555 rtl_writephy(tp, 0x14, 0x1065);
3556 rtl_writephy(tp, 0x14, 0x9065);
3557 rtl_writephy(tp, 0x14, 0x1065);
3558 rtl_writephy(tp, 0x1f, 0x0000);
3559
3560 rtl8168g_disable_aldps(tp);
3561 rtl8168g_config_eee_phy(tp);
3562 rtl_enable_eee(tp);
3563 }
3564
3565 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3566 {
3567 static const struct phy_reg phy_reg_init[] = {
3568 { 0x1f, 0x0003 },
3569 { 0x08, 0x441d },
3570 { 0x01, 0x9100 },
3571 { 0x1f, 0x0000 }
3572 };
3573
3574 rtl_writephy(tp, 0x1f, 0x0000);
3575 rtl_patchphy(tp, 0x11, 1 << 12);
3576 rtl_patchphy(tp, 0x19, 1 << 13);
3577 rtl_patchphy(tp, 0x10, 1 << 15);
3578
3579 rtl_writephy_batch(tp, phy_reg_init);
3580 }
3581
3582 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3583 {
3584 static const struct phy_reg phy_reg_init[] = {
3585 { 0x1f, 0x0005 },
3586 { 0x1a, 0x0000 },
3587 { 0x1f, 0x0000 },
3588
3589 { 0x1f, 0x0004 },
3590 { 0x1c, 0x0000 },
3591 { 0x1f, 0x0000 },
3592
3593 { 0x1f, 0x0001 },
3594 { 0x15, 0x7701 },
3595 { 0x1f, 0x0000 }
3596 };
3597
3598 /* Disable ALDPS before ram code */
3599 rtl_writephy(tp, 0x1f, 0x0000);
3600 rtl_writephy(tp, 0x18, 0x0310);
3601 msleep(100);
3602
3603 rtl_apply_firmware(tp);
3604
3605 rtl_writephy_batch(tp, phy_reg_init);
3606 }
3607
3608 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3609 {
3610 /* Disable ALDPS before setting firmware */
3611 rtl_writephy(tp, 0x1f, 0x0000);
3612 rtl_writephy(tp, 0x18, 0x0310);
3613 msleep(20);
3614
3615 rtl_apply_firmware(tp);
3616
3617 /* EEE setting */
3618 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3619 rtl_writephy(tp, 0x1f, 0x0004);
3620 rtl_writephy(tp, 0x10, 0x401f);
3621 rtl_writephy(tp, 0x19, 0x7030);
3622 rtl_writephy(tp, 0x1f, 0x0000);
3623 }
3624
3625 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3626 {
3627 static const struct phy_reg phy_reg_init[] = {
3628 { 0x1f, 0x0004 },
3629 { 0x10, 0xc07f },
3630 { 0x19, 0x7030 },
3631 { 0x1f, 0x0000 }
3632 };
3633
3634 /* Disable ALDPS before ram code */
3635 rtl_writephy(tp, 0x1f, 0x0000);
3636 rtl_writephy(tp, 0x18, 0x0310);
3637 msleep(100);
3638
3639 rtl_apply_firmware(tp);
3640
3641 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3642 rtl_writephy_batch(tp, phy_reg_init);
3643
3644 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3645 }
3646
3647 static void rtl8125_1_hw_phy_config(struct rtl8169_private *tp)
3648 {
3649 struct phy_device *phydev = tp->phydev;
3650
3651 phy_modify_paged(phydev, 0xad4, 0x10, 0x03ff, 0x0084);
3652 phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010);
3653 phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x0006);
3654 phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006);
3655 phy_modify_paged(phydev, 0xac0, 0x14, 0x0000, 0x1100);
3656 phy_modify_paged(phydev, 0xac8, 0x15, 0xf000, 0x7000);
3657 phy_modify_paged(phydev, 0xad1, 0x14, 0x0000, 0x0400);
3658 phy_modify_paged(phydev, 0xad1, 0x15, 0x0000, 0x03ff);
3659 phy_modify_paged(phydev, 0xad1, 0x16, 0x0000, 0x03ff);
3660
3661 phy_write(phydev, 0x1f, 0x0a43);
3662 phy_write(phydev, 0x13, 0x80ea);
3663 phy_modify(phydev, 0x14, 0xff00, 0xc400);
3664 phy_write(phydev, 0x13, 0x80eb);
3665 phy_modify(phydev, 0x14, 0x0700, 0x0300);
3666 phy_write(phydev, 0x13, 0x80f8);
3667 phy_modify(phydev, 0x14, 0xff00, 0x1c00);
3668 phy_write(phydev, 0x13, 0x80f1);
3669 phy_modify(phydev, 0x14, 0xff00, 0x3000);
3670 phy_write(phydev, 0x13, 0x80fe);
3671 phy_modify(phydev, 0x14, 0xff00, 0xa500);
3672 phy_write(phydev, 0x13, 0x8102);
3673 phy_modify(phydev, 0x14, 0xff00, 0x5000);
3674 phy_write(phydev, 0x13, 0x8105);
3675 phy_modify(phydev, 0x14, 0xff00, 0x3300);
3676 phy_write(phydev, 0x13, 0x8100);
3677 phy_modify(phydev, 0x14, 0xff00, 0x7000);
3678 phy_write(phydev, 0x13, 0x8104);
3679 phy_modify(phydev, 0x14, 0xff00, 0xf000);
3680 phy_write(phydev, 0x13, 0x8106);
3681 phy_modify(phydev, 0x14, 0xff00, 0x6500);
3682 phy_write(phydev, 0x13, 0x80dc);
3683 phy_modify(phydev, 0x14, 0xff00, 0xed00);
3684 phy_write(phydev, 0x13, 0x80df);
3685 phy_set_bits(phydev, 0x14, BIT(8));
3686 phy_write(phydev, 0x13, 0x80e1);
3687 phy_clear_bits(phydev, 0x14, BIT(8));
3688 phy_write(phydev, 0x1f, 0x0000);
3689
3690 phy_modify_paged(phydev, 0xbf0, 0x13, 0x003f, 0x0038);
3691 phy_write_paged(phydev, 0xa43, 0x13, 0x819f);
3692 phy_write_paged(phydev, 0xa43, 0x14, 0xd0b6);
3693
3694 phy_write_paged(phydev, 0xbc3, 0x12, 0x5555);
3695 phy_modify_paged(phydev, 0xbf0, 0x15, 0x0e00, 0x0a00);
3696 phy_modify_paged(phydev, 0xa5c, 0x10, 0x0400, 0x0000);
3697 phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800);
3698
3699 rtl8125_config_eee_phy(tp);
3700 rtl_enable_eee(tp);
3701 }
3702
3703 static void rtl8125_2_hw_phy_config(struct rtl8169_private *tp)
3704 {
3705 struct phy_device *phydev = tp->phydev;
3706 int i;
3707
3708 phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010);
3709 phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x03ff);
3710 phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006);
3711 phy_modify_paged(phydev, 0xac0, 0x14, 0x1100, 0x0000);
3712 phy_modify_paged(phydev, 0xacc, 0x10, 0x0003, 0x0002);
3713 phy_modify_paged(phydev, 0xad4, 0x10, 0x00e7, 0x0044);
3714 phy_modify_paged(phydev, 0xac1, 0x12, 0x0080, 0x0000);
3715 phy_modify_paged(phydev, 0xac8, 0x10, 0x0300, 0x0000);
3716 phy_modify_paged(phydev, 0xac5, 0x17, 0x0007, 0x0002);
3717 phy_write_paged(phydev, 0xad4, 0x16, 0x00a8);
3718 phy_write_paged(phydev, 0xac5, 0x16, 0x01ff);
3719 phy_modify_paged(phydev, 0xac8, 0x15, 0x00f0, 0x0030);
3720
3721 phy_write(phydev, 0x1f, 0x0b87);
3722 phy_write(phydev, 0x16, 0x80a2);
3723 phy_write(phydev, 0x17, 0x0153);
3724 phy_write(phydev, 0x16, 0x809c);
3725 phy_write(phydev, 0x17, 0x0153);
3726 phy_write(phydev, 0x1f, 0x0000);
3727
3728 phy_write(phydev, 0x1f, 0x0a43);
3729 phy_write(phydev, 0x13, 0x81B3);
3730 phy_write(phydev, 0x14, 0x0043);
3731 phy_write(phydev, 0x14, 0x00A7);
3732 phy_write(phydev, 0x14, 0x00D6);
3733 phy_write(phydev, 0x14, 0x00EC);
3734 phy_write(phydev, 0x14, 0x00F6);
3735 phy_write(phydev, 0x14, 0x00FB);
3736 phy_write(phydev, 0x14, 0x00FD);
3737 phy_write(phydev, 0x14, 0x00FF);
3738 phy_write(phydev, 0x14, 0x00BB);
3739 phy_write(phydev, 0x14, 0x0058);
3740 phy_write(phydev, 0x14, 0x0029);
3741 phy_write(phydev, 0x14, 0x0013);
3742 phy_write(phydev, 0x14, 0x0009);
3743 phy_write(phydev, 0x14, 0x0004);
3744 phy_write(phydev, 0x14, 0x0002);
3745 for (i = 0; i < 25; i++)
3746 phy_write(phydev, 0x14, 0x0000);
3747
3748 phy_write(phydev, 0x13, 0x8257);
3749 phy_write(phydev, 0x14, 0x020F);
3750
3751 phy_write(phydev, 0x13, 0x80EA);
3752 phy_write(phydev, 0x14, 0x7843);
3753 phy_write(phydev, 0x1f, 0x0000);
3754
3755 rtl_apply_firmware(tp);
3756
3757 phy_modify_paged(phydev, 0xd06, 0x14, 0x0000, 0x2000);
3758
3759 phy_write(phydev, 0x1f, 0x0a43);
3760 phy_write(phydev, 0x13, 0x81a2);
3761 phy_set_bits(phydev, 0x14, BIT(8));
3762 phy_write(phydev, 0x1f, 0x0000);
3763
3764 phy_modify_paged(phydev, 0xb54, 0x16, 0xff00, 0xdb00);
3765 phy_modify_paged(phydev, 0xa45, 0x12, 0x0001, 0x0000);
3766 phy_modify_paged(phydev, 0xa5d, 0x12, 0x0000, 0x0020);
3767 phy_modify_paged(phydev, 0xad4, 0x17, 0x0010, 0x0000);
3768 phy_modify_paged(phydev, 0xa86, 0x15, 0x0001, 0x0000);
3769 phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800);
3770
3771 rtl8125_config_eee_phy(tp);
3772 rtl_enable_eee(tp);
3773 }
3774
3775 static void rtl_hw_phy_config(struct net_device *dev)
3776 {
3777 static const rtl_generic_fct phy_configs[] = {
3778 /* PCI devices. */
3779 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
3780 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
3781 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
3782 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
3783 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
3784 /* PCI-E devices. */
3785 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
3786 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
3787 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
3788 [RTL_GIGA_MAC_VER_10] = NULL,
3789 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
3790 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config,
3791 [RTL_GIGA_MAC_VER_13] = NULL,
3792 [RTL_GIGA_MAC_VER_14] = NULL,
3793 [RTL_GIGA_MAC_VER_15] = NULL,
3794 [RTL_GIGA_MAC_VER_16] = NULL,
3795 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
3796 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
3797 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
3798 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
3799 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
3800 [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config,
3801 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
3802 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
3803 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
3804 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
3805 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config,
3806 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
3807 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
3808 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
3809 [RTL_GIGA_MAC_VER_31] = NULL,
3810 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
3811 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
3812 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
3813 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
3814 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
3815 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
3816 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
3817 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
3818 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
3819 [RTL_GIGA_MAC_VER_41] = NULL,
3820 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
3821 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
3822 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
3823 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config,
3824 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
3825 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config,
3826 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
3827 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config,
3828 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config,
3829 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
3830 [RTL_GIGA_MAC_VER_60] = rtl8125_1_hw_phy_config,
3831 [RTL_GIGA_MAC_VER_61] = rtl8125_2_hw_phy_config,
3832 };
3833 struct rtl8169_private *tp = netdev_priv(dev);
3834
3835 if (phy_configs[tp->mac_version])
3836 phy_configs[tp->mac_version](tp);
3837 }
3838
3839 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3840 {
3841 if (!test_and_set_bit(flag, tp->wk.flags))
3842 schedule_work(&tp->wk.work);
3843 }
3844
3845 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3846 {
3847 rtl_hw_phy_config(dev);
3848
3849 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3850 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3851 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3852 netif_dbg(tp, drv, dev,
3853 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3854 RTL_W8(tp, 0x82, 0x01);
3855 }
3856
3857 /* We may have called phy_speed_down before */
3858 phy_speed_up(tp->phydev);
3859
3860 genphy_soft_reset(tp->phydev);
3861 }
3862
3863 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3864 {
3865 rtl_lock_work(tp);
3866
3867 rtl_unlock_config_regs(tp);
3868
3869 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
3870 RTL_R32(tp, MAC4);
3871
3872 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3873 RTL_R32(tp, MAC0);
3874
3875 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3876 rtl_rar_exgmac_set(tp, addr);
3877
3878 rtl_lock_config_regs(tp);
3879
3880 rtl_unlock_work(tp);
3881 }
3882
3883 static int rtl_set_mac_address(struct net_device *dev, void *p)
3884 {
3885 struct rtl8169_private *tp = netdev_priv(dev);
3886 struct device *d = tp_to_dev(tp);
3887 int ret;
3888
3889 ret = eth_mac_addr(dev, p);
3890 if (ret)
3891 return ret;
3892
3893 pm_runtime_get_noresume(d);
3894
3895 if (pm_runtime_active(d))
3896 rtl_rar_set(tp, dev->dev_addr);
3897
3898 pm_runtime_put_noidle(d);
3899
3900 return 0;
3901 }
3902
3903 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3904 {
3905 struct rtl8169_private *tp = netdev_priv(dev);
3906
3907 if (!netif_running(dev))
3908 return -ENODEV;
3909
3910 return phy_mii_ioctl(tp->phydev, ifr, cmd);
3911 }
3912
3913 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3914 {
3915 switch (tp->mac_version) {
3916 case RTL_GIGA_MAC_VER_25:
3917 case RTL_GIGA_MAC_VER_26:
3918 case RTL_GIGA_MAC_VER_29:
3919 case RTL_GIGA_MAC_VER_30:
3920 case RTL_GIGA_MAC_VER_32:
3921 case RTL_GIGA_MAC_VER_33:
3922 case RTL_GIGA_MAC_VER_34:
3923 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
3924 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
3925 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3926 break;
3927 default:
3928 break;
3929 }
3930 }
3931
3932 static void rtl_pll_power_down(struct rtl8169_private *tp)
3933 {
3934 if (r8168_check_dash(tp))
3935 return;
3936
3937 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3938 tp->mac_version == RTL_GIGA_MAC_VER_33)
3939 rtl_ephy_write(tp, 0x19, 0xff64);
3940
3941 if (device_may_wakeup(tp_to_dev(tp))) {
3942 phy_speed_down(tp->phydev, false);
3943 rtl_wol_suspend_quirk(tp);
3944 return;
3945 }
3946
3947 switch (tp->mac_version) {
3948 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
3949 case RTL_GIGA_MAC_VER_37:
3950 case RTL_GIGA_MAC_VER_39:
3951 case RTL_GIGA_MAC_VER_43:
3952 case RTL_GIGA_MAC_VER_44:
3953 case RTL_GIGA_MAC_VER_45:
3954 case RTL_GIGA_MAC_VER_46:
3955 case RTL_GIGA_MAC_VER_47:
3956 case RTL_GIGA_MAC_VER_48:
3957 case RTL_GIGA_MAC_VER_50:
3958 case RTL_GIGA_MAC_VER_51:
3959 case RTL_GIGA_MAC_VER_60:
3960 case RTL_GIGA_MAC_VER_61:
3961 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
3962 break;
3963 case RTL_GIGA_MAC_VER_40:
3964 case RTL_GIGA_MAC_VER_41:
3965 case RTL_GIGA_MAC_VER_49:
3966 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
3967 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
3968 break;
3969 default:
3970 break;
3971 }
3972 }
3973
3974 static void rtl_pll_power_up(struct rtl8169_private *tp)
3975 {
3976 switch (tp->mac_version) {
3977 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
3978 case RTL_GIGA_MAC_VER_37:
3979 case RTL_GIGA_MAC_VER_39:
3980 case RTL_GIGA_MAC_VER_43:
3981 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
3982 break;
3983 case RTL_GIGA_MAC_VER_44:
3984 case RTL_GIGA_MAC_VER_45:
3985 case RTL_GIGA_MAC_VER_46:
3986 case RTL_GIGA_MAC_VER_47:
3987 case RTL_GIGA_MAC_VER_48:
3988 case RTL_GIGA_MAC_VER_50:
3989 case RTL_GIGA_MAC_VER_51:
3990 case RTL_GIGA_MAC_VER_60:
3991 case RTL_GIGA_MAC_VER_61:
3992 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
3993 break;
3994 case RTL_GIGA_MAC_VER_40:
3995 case RTL_GIGA_MAC_VER_41:
3996 case RTL_GIGA_MAC_VER_49:
3997 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
3998 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
3999 break;
4000 default:
4001 break;
4002 }
4003
4004 phy_resume(tp->phydev);
4005 /* give MAC/PHY some time to resume */
4006 msleep(20);
4007 }
4008
4009 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4010 {
4011 switch (tp->mac_version) {
4012 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4013 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4014 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4015 break;
4016 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4017 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4018 case RTL_GIGA_MAC_VER_38:
4019 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4020 break;
4021 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4022 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4023 break;
4024 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
4025 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_VLAN_8125 |
4026 RX_DMA_BURST);
4027 break;
4028 default:
4029 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4030 break;
4031 }
4032 }
4033
4034 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4035 {
4036 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4037 }
4038
4039 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4040 {
4041 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4042 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4043 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4044 }
4045
4046 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4047 {
4048 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4049 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4050 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4051 }
4052
4053 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4054 {
4055 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4056 }
4057
4058 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4059 {
4060 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4061 }
4062
4063 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4064 {
4065 RTL_W8(tp, MaxTxPacketSize, 0x3f);
4066 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4067 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4068 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4069 }
4070
4071 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4072 {
4073 RTL_W8(tp, MaxTxPacketSize, 0x0c);
4074 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4075 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4076 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4077 }
4078
4079 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4080 {
4081 rtl_tx_performance_tweak(tp,
4082 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4083 }
4084
4085 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4086 {
4087 rtl_tx_performance_tweak(tp,
4088 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4089 }
4090
4091 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4092 {
4093 r8168b_0_hw_jumbo_enable(tp);
4094
4095 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4096 }
4097
4098 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4099 {
4100 r8168b_0_hw_jumbo_disable(tp);
4101
4102 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4103 }
4104
4105 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4106 {
4107 rtl_unlock_config_regs(tp);
4108 switch (tp->mac_version) {
4109 case RTL_GIGA_MAC_VER_11:
4110 r8168b_0_hw_jumbo_enable(tp);
4111 break;
4112 case RTL_GIGA_MAC_VER_12:
4113 case RTL_GIGA_MAC_VER_17:
4114 r8168b_1_hw_jumbo_enable(tp);
4115 break;
4116 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
4117 r8168c_hw_jumbo_enable(tp);
4118 break;
4119 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
4120 r8168dp_hw_jumbo_enable(tp);
4121 break;
4122 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
4123 r8168e_hw_jumbo_enable(tp);
4124 break;
4125 default:
4126 break;
4127 }
4128 rtl_lock_config_regs(tp);
4129 }
4130
4131 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4132 {
4133 rtl_unlock_config_regs(tp);
4134 switch (tp->mac_version) {
4135 case RTL_GIGA_MAC_VER_11:
4136 r8168b_0_hw_jumbo_disable(tp);
4137 break;
4138 case RTL_GIGA_MAC_VER_12:
4139 case RTL_GIGA_MAC_VER_17:
4140 r8168b_1_hw_jumbo_disable(tp);
4141 break;
4142 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
4143 r8168c_hw_jumbo_disable(tp);
4144 break;
4145 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
4146 r8168dp_hw_jumbo_disable(tp);
4147 break;
4148 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
4149 r8168e_hw_jumbo_disable(tp);
4150 break;
4151 default:
4152 break;
4153 }
4154 rtl_lock_config_regs(tp);
4155 }
4156
4157 static void rtl_jumbo_config(struct rtl8169_private *tp, int mtu)
4158 {
4159 if (mtu > ETH_DATA_LEN)
4160 rtl_hw_jumbo_enable(tp);
4161 else
4162 rtl_hw_jumbo_disable(tp);
4163 }
4164
4165 DECLARE_RTL_COND(rtl_chipcmd_cond)
4166 {
4167 return RTL_R8(tp, ChipCmd) & CmdReset;
4168 }
4169
4170 static void rtl_hw_reset(struct rtl8169_private *tp)
4171 {
4172 RTL_W8(tp, ChipCmd, CmdReset);
4173
4174 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4175 }
4176
4177 static void rtl_request_firmware(struct rtl8169_private *tp)
4178 {
4179 struct rtl_fw *rtl_fw;
4180
4181 /* firmware loaded already or no firmware available */
4182 if (tp->rtl_fw || !tp->fw_name)
4183 return;
4184
4185 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4186 if (!rtl_fw) {
4187 netif_warn(tp, ifup, tp->dev, "Unable to load firmware, out of memory\n");
4188 return;
4189 }
4190
4191 rtl_fw->phy_write = rtl_writephy;
4192 rtl_fw->phy_read = rtl_readphy;
4193 rtl_fw->mac_mcu_write = mac_mcu_write;
4194 rtl_fw->mac_mcu_read = mac_mcu_read;
4195 rtl_fw->fw_name = tp->fw_name;
4196 rtl_fw->dev = tp_to_dev(tp);
4197
4198 if (rtl_fw_request_firmware(rtl_fw))
4199 kfree(rtl_fw);
4200 else
4201 tp->rtl_fw = rtl_fw;
4202 }
4203
4204 static void rtl_rx_close(struct rtl8169_private *tp)
4205 {
4206 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4207 }
4208
4209 DECLARE_RTL_COND(rtl_npq_cond)
4210 {
4211 return RTL_R8(tp, TxPoll) & NPQ;
4212 }
4213
4214 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4215 {
4216 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4217 }
4218
4219 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4220 {
4221 /* Disable interrupts */
4222 rtl8169_irq_mask_and_ack(tp);
4223
4224 rtl_rx_close(tp);
4225
4226 switch (tp->mac_version) {
4227 case RTL_GIGA_MAC_VER_27:
4228 case RTL_GIGA_MAC_VER_28:
4229 case RTL_GIGA_MAC_VER_31:
4230 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4231 break;
4232 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4233 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4234 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4235 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4236 break;
4237 default:
4238 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4239 udelay(100);
4240 break;
4241 }
4242
4243 rtl_hw_reset(tp);
4244 }
4245
4246 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4247 {
4248 u32 val = TX_DMA_BURST << TxDMAShift |
4249 InterFrameGap << TxInterFrameGapShift;
4250
4251 if (rtl_is_8168evl_up(tp))
4252 val |= TXCFG_AUTO_FIFO;
4253
4254 RTL_W32(tp, TxConfig, val);
4255 }
4256
4257 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4258 {
4259 /* Low hurts. Let's disable the filtering. */
4260 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4261 }
4262
4263 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4264 {
4265 /*
4266 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4267 * register to be written before TxDescAddrLow to work.
4268 * Switching from MMIO to I/O access fixes the issue as well.
4269 */
4270 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4271 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4272 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4273 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4274 }
4275
4276 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4277 {
4278 u32 val;
4279
4280 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4281 val = 0x000fff00;
4282 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4283 val = 0x00ffff00;
4284 else
4285 return;
4286
4287 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4288 val |= 0xff;
4289
4290 RTL_W32(tp, 0x7c, val);
4291 }
4292
4293 static void rtl_set_rx_mode(struct net_device *dev)
4294 {
4295 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
4296 /* Multicast hash filter */
4297 u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
4298 struct rtl8169_private *tp = netdev_priv(dev);
4299 u32 tmp;
4300
4301 if (dev->flags & IFF_PROMISC) {
4302 /* Unconditionally log net taps. */
4303 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4304 rx_mode |= AcceptAllPhys;
4305 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
4306 dev->flags & IFF_ALLMULTI ||
4307 tp->mac_version == RTL_GIGA_MAC_VER_35) {
4308 /* accept all multicasts */
4309 } else if (netdev_mc_empty(dev)) {
4310 rx_mode &= ~AcceptMulticast;
4311 } else {
4312 struct netdev_hw_addr *ha;
4313
4314 mc_filter[1] = mc_filter[0] = 0;
4315 netdev_for_each_mc_addr(ha, dev) {
4316 u32 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4317 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
4318 }
4319
4320 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4321 tmp = mc_filter[0];
4322 mc_filter[0] = swab32(mc_filter[1]);
4323 mc_filter[1] = swab32(tmp);
4324 }
4325 }
4326
4327 if (dev->features & NETIF_F_RXALL)
4328 rx_mode |= (AcceptErr | AcceptRunt);
4329
4330 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4331 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4332
4333 tmp = RTL_R32(tp, RxConfig);
4334 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_MASK) | rx_mode);
4335 }
4336
4337 DECLARE_RTL_COND(rtl_csiar_cond)
4338 {
4339 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4340 }
4341
4342 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4343 {
4344 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4345
4346 RTL_W32(tp, CSIDR, value);
4347 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4348 CSIAR_BYTE_ENABLE | func << 16);
4349
4350 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4351 }
4352
4353 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4354 {
4355 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4356
4357 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4358 CSIAR_BYTE_ENABLE);
4359
4360 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4361 RTL_R32(tp, CSIDR) : ~0;
4362 }
4363
4364 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4365 {
4366 struct pci_dev *pdev = tp->pci_dev;
4367 u32 csi;
4368
4369 /* According to Realtek the value at config space address 0x070f
4370 * controls the L0s/L1 entrance latency. We try standard ECAM access
4371 * first and if it fails fall back to CSI.
4372 */
4373 if (pdev->cfg_size > 0x070f &&
4374 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4375 return;
4376
4377 netdev_notice_once(tp->dev,
4378 "No native access to PCI extended config space, falling back to CSI\n");
4379 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4380 rtl_csi_write(tp, 0x070c, csi | val << 24);
4381 }
4382
4383 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4384 {
4385 rtl_csi_access_enable(tp, 0x27);
4386 }
4387
4388 struct ephy_info {
4389 unsigned int offset;
4390 u16 mask;
4391 u16 bits;
4392 };
4393
4394 static void __rtl_ephy_init(struct rtl8169_private *tp,
4395 const struct ephy_info *e, int len)
4396 {
4397 u16 w;
4398
4399 while (len-- > 0) {
4400 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4401 rtl_ephy_write(tp, e->offset, w);
4402 e++;
4403 }
4404 }
4405
4406 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
4407
4408 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4409 {
4410 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4411 PCI_EXP_LNKCTL_CLKREQ_EN);
4412 }
4413
4414 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4415 {
4416 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4417 PCI_EXP_LNKCTL_CLKREQ_EN);
4418 }
4419
4420 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
4421 {
4422 /* work around an issue when PCI reset occurs during L2/L3 state */
4423 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
4424 }
4425
4426 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4427 {
4428 /* Don't enable ASPM in the chip if OS can't control ASPM */
4429 if (enable && tp->aspm_manageable) {
4430 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4431 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4432 } else {
4433 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4434 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4435 }
4436
4437 udelay(10);
4438 }
4439
4440 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
4441 u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
4442 {
4443 /* Usage of dynamic vs. static FIFO is controlled by bit
4444 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
4445 */
4446 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
4447 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
4448 }
4449
4450 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
4451 u8 low, u8 high)
4452 {
4453 /* FIFO thresholds for pause flow control */
4454 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
4455 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
4456 }
4457
4458 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4459 {
4460 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4461 }
4462
4463 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4464 {
4465 rtl_hw_start_8168bb(tp);
4466
4467 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4468 }
4469
4470 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4471 {
4472 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4473
4474 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4475
4476 rtl_disable_clock_request(tp);
4477 }
4478
4479 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4480 {
4481 static const struct ephy_info e_info_8168cp[] = {
4482 { 0x01, 0, 0x0001 },
4483 { 0x02, 0x0800, 0x1000 },
4484 { 0x03, 0, 0x0042 },
4485 { 0x06, 0x0080, 0x0000 },
4486 { 0x07, 0, 0x2000 }
4487 };
4488
4489 rtl_set_def_aspm_entry_latency(tp);
4490
4491 rtl_ephy_init(tp, e_info_8168cp);
4492
4493 __rtl_hw_start_8168cp(tp);
4494 }
4495
4496 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4497 {
4498 rtl_set_def_aspm_entry_latency(tp);
4499
4500 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4501 }
4502
4503 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4504 {
4505 rtl_set_def_aspm_entry_latency(tp);
4506
4507 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4508
4509 /* Magic. */
4510 RTL_W8(tp, DBG_REG, 0x20);
4511 }
4512
4513 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4514 {
4515 static const struct ephy_info e_info_8168c_1[] = {
4516 { 0x02, 0x0800, 0x1000 },
4517 { 0x03, 0, 0x0002 },
4518 { 0x06, 0x0080, 0x0000 }
4519 };
4520
4521 rtl_set_def_aspm_entry_latency(tp);
4522
4523 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4524
4525 rtl_ephy_init(tp, e_info_8168c_1);
4526
4527 __rtl_hw_start_8168cp(tp);
4528 }
4529
4530 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4531 {
4532 static const struct ephy_info e_info_8168c_2[] = {
4533 { 0x01, 0, 0x0001 },
4534 { 0x03, 0x0400, 0x0020 }
4535 };
4536
4537 rtl_set_def_aspm_entry_latency(tp);
4538
4539 rtl_ephy_init(tp, e_info_8168c_2);
4540
4541 __rtl_hw_start_8168cp(tp);
4542 }
4543
4544 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4545 {
4546 rtl_hw_start_8168c_2(tp);
4547 }
4548
4549 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4550 {
4551 rtl_set_def_aspm_entry_latency(tp);
4552
4553 __rtl_hw_start_8168cp(tp);
4554 }
4555
4556 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4557 {
4558 rtl_set_def_aspm_entry_latency(tp);
4559
4560 rtl_disable_clock_request(tp);
4561
4562 if (tp->dev->mtu <= ETH_DATA_LEN)
4563 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4564 }
4565
4566 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4567 {
4568 rtl_set_def_aspm_entry_latency(tp);
4569
4570 if (tp->dev->mtu <= ETH_DATA_LEN)
4571 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4572
4573 rtl_disable_clock_request(tp);
4574 }
4575
4576 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4577 {
4578 static const struct ephy_info e_info_8168d_4[] = {
4579 { 0x0b, 0x0000, 0x0048 },
4580 { 0x19, 0x0020, 0x0050 },
4581 { 0x0c, 0x0100, 0x0020 },
4582 { 0x10, 0x0004, 0x0000 },
4583 };
4584
4585 rtl_set_def_aspm_entry_latency(tp);
4586
4587 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4588
4589 rtl_ephy_init(tp, e_info_8168d_4);
4590
4591 rtl_enable_clock_request(tp);
4592 }
4593
4594 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4595 {
4596 static const struct ephy_info e_info_8168e_1[] = {
4597 { 0x00, 0x0200, 0x0100 },
4598 { 0x00, 0x0000, 0x0004 },
4599 { 0x06, 0x0002, 0x0001 },
4600 { 0x06, 0x0000, 0x0030 },
4601 { 0x07, 0x0000, 0x2000 },
4602 { 0x00, 0x0000, 0x0020 },
4603 { 0x03, 0x5800, 0x2000 },
4604 { 0x03, 0x0000, 0x0001 },
4605 { 0x01, 0x0800, 0x1000 },
4606 { 0x07, 0x0000, 0x4000 },
4607 { 0x1e, 0x0000, 0x2000 },
4608 { 0x19, 0xffff, 0xfe6c },
4609 { 0x0a, 0x0000, 0x0040 }
4610 };
4611
4612 rtl_set_def_aspm_entry_latency(tp);
4613
4614 rtl_ephy_init(tp, e_info_8168e_1);
4615
4616 rtl_disable_clock_request(tp);
4617
4618 /* Reset tx FIFO pointer */
4619 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4620 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4621
4622 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4623 }
4624
4625 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4626 {
4627 static const struct ephy_info e_info_8168e_2[] = {
4628 { 0x09, 0x0000, 0x0080 },
4629 { 0x19, 0x0000, 0x0224 },
4630 { 0x00, 0x0000, 0x0004 },
4631 { 0x0c, 0x3df0, 0x0200 },
4632 };
4633
4634 rtl_set_def_aspm_entry_latency(tp);
4635
4636 rtl_ephy_init(tp, e_info_8168e_2);
4637
4638 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4639 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4640 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4641 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4642 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
4643 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4644 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4645
4646 rtl_disable_clock_request(tp);
4647
4648 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4649
4650 rtl8168_config_eee_mac(tp);
4651
4652 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4653 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4654 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4655
4656 rtl_hw_aspm_clkreq_enable(tp, true);
4657 }
4658
4659 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
4660 {
4661 rtl_set_def_aspm_entry_latency(tp);
4662
4663 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4664
4665 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4666 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4667 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4668 rtl_reset_packet_filter(tp);
4669 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4670 rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));
4671 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4672 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
4673
4674 rtl_disable_clock_request(tp);
4675
4676 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4677 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4678 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4679 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4680
4681 rtl8168_config_eee_mac(tp);
4682 }
4683
4684 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
4685 {
4686 static const struct ephy_info e_info_8168f_1[] = {
4687 { 0x06, 0x00c0, 0x0020 },
4688 { 0x08, 0x0001, 0x0002 },
4689 { 0x09, 0x0000, 0x0080 },
4690 { 0x19, 0x0000, 0x0224 },
4691 { 0x00, 0x0000, 0x0004 },
4692 { 0x0c, 0x3df0, 0x0200 },
4693 };
4694
4695 rtl_hw_start_8168f(tp);
4696
4697 rtl_ephy_init(tp, e_info_8168f_1);
4698
4699 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4700 }
4701
4702 static void rtl_hw_start_8411(struct rtl8169_private *tp)
4703 {
4704 static const struct ephy_info e_info_8168f_1[] = {
4705 { 0x06, 0x00c0, 0x0020 },
4706 { 0x0f, 0xffff, 0x5200 },
4707 { 0x19, 0x0000, 0x0224 },
4708 { 0x00, 0x0000, 0x0004 },
4709 { 0x0c, 0x3df0, 0x0200 },
4710 };
4711
4712 rtl_hw_start_8168f(tp);
4713 rtl_pcie_state_l2l3_disable(tp);
4714
4715 rtl_ephy_init(tp, e_info_8168f_1);
4716
4717 rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);
4718 }
4719
4720 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
4721 {
4722 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4723 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4724
4725 rtl_set_def_aspm_entry_latency(tp);
4726
4727 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4728
4729 rtl_reset_packet_filter(tp);
4730 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
4731
4732 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4733
4734 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4735 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4736
4737 rtl8168_config_eee_mac(tp);
4738
4739 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
4740 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4741
4742 rtl_pcie_state_l2l3_disable(tp);
4743 }
4744
4745 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
4746 {
4747 static const struct ephy_info e_info_8168g_1[] = {
4748 { 0x00, 0x0008, 0x0000 },
4749 { 0x0c, 0x3ff0, 0x0820 },
4750 { 0x1e, 0x0000, 0x0001 },
4751 { 0x19, 0x8000, 0x0000 }
4752 };
4753
4754 rtl_hw_start_8168g(tp);
4755
4756 /* disable aspm and clock request before access ephy */
4757 rtl_hw_aspm_clkreq_enable(tp, false);
4758 rtl_ephy_init(tp, e_info_8168g_1);
4759 rtl_hw_aspm_clkreq_enable(tp, true);
4760 }
4761
4762 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
4763 {
4764 static const struct ephy_info e_info_8168g_2[] = {
4765 { 0x00, 0x0008, 0x0000 },
4766 { 0x0c, 0x3ff0, 0x0820 },
4767 { 0x19, 0xffff, 0x7c00 },
4768 { 0x1e, 0xffff, 0x20eb },
4769 { 0x0d, 0xffff, 0x1666 },
4770 { 0x00, 0xffff, 0x10a3 },
4771 { 0x06, 0xffff, 0xf050 },
4772 { 0x04, 0x0000, 0x0010 },
4773 { 0x1d, 0x4000, 0x0000 },
4774 };
4775
4776 rtl_hw_start_8168g(tp);
4777
4778 /* disable aspm and clock request before access ephy */
4779 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4780 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4781 rtl_ephy_init(tp, e_info_8168g_2);
4782 }
4783
4784 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
4785 {
4786 static const struct ephy_info e_info_8411_2[] = {
4787 { 0x00, 0x0008, 0x0000 },
4788 { 0x0c, 0x37d0, 0x0820 },
4789 { 0x1e, 0x0000, 0x0001 },
4790 { 0x19, 0x8021, 0x0000 },
4791 { 0x1e, 0x0000, 0x2000 },
4792 { 0x0d, 0x0100, 0x0200 },
4793 { 0x00, 0x0000, 0x0080 },
4794 { 0x06, 0x0000, 0x0010 },
4795 { 0x04, 0x0000, 0x0010 },
4796 { 0x1d, 0x0000, 0x4000 },
4797 };
4798
4799 rtl_hw_start_8168g(tp);
4800
4801 /* disable aspm and clock request before access ephy */
4802 rtl_hw_aspm_clkreq_enable(tp, false);
4803 rtl_ephy_init(tp, e_info_8411_2);
4804
4805 /* The following Realtek-provided magic fixes an issue with the RX unit
4806 * getting confused after the PHY having been powered-down.
4807 */
4808 r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
4809 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
4810 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
4811 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
4812 r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
4813 r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
4814 r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
4815 r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
4816 mdelay(3);
4817 r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
4818
4819 r8168_mac_ocp_write(tp, 0xF800, 0xE008);
4820 r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
4821 r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
4822 r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
4823 r8168_mac_ocp_write(tp, 0xF808, 0xE027);
4824 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
4825 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
4826 r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
4827 r8168_mac_ocp_write(tp, 0xF810, 0xC602);
4828 r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
4829 r8168_mac_ocp_write(tp, 0xF814, 0x0000);
4830 r8168_mac_ocp_write(tp, 0xF816, 0xC502);
4831 r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
4832 r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
4833 r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
4834 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
4835 r8168_mac_ocp_write(tp, 0xF820, 0x080A);
4836 r8168_mac_ocp_write(tp, 0xF822, 0x6420);
4837 r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
4838 r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
4839 r8168_mac_ocp_write(tp, 0xF828, 0xC516);
4840 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
4841 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
4842 r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
4843 r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
4844 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
4845 r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
4846 r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
4847 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
4848 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
4849 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
4850 r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
4851 r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
4852 r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
4853 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
4854 r8168_mac_ocp_write(tp, 0xF846, 0xC404);
4855 r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
4856 r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
4857 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
4858 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
4859 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
4860 r8168_mac_ocp_write(tp, 0xF852, 0xE434);
4861 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
4862 r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
4863 r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
4864 r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
4865 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
4866 r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
4867 r8168_mac_ocp_write(tp, 0xF860, 0xF007);
4868 r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
4869 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
4870 r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
4871 r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
4872 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
4873 r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
4874 r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
4875 r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
4876 r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
4877 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
4878 r8168_mac_ocp_write(tp, 0xF876, 0xC516);
4879 r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
4880 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
4881 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
4882 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
4883 r8168_mac_ocp_write(tp, 0xF880, 0xC512);
4884 r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
4885 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
4886 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
4887 r8168_mac_ocp_write(tp, 0xF888, 0x483F);
4888 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
4889 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
4890 r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
4891 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
4892 r8168_mac_ocp_write(tp, 0xF892, 0xC505);
4893 r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
4894 r8168_mac_ocp_write(tp, 0xF896, 0xC502);
4895 r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
4896 r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
4897 r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
4898 r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
4899 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
4900 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
4901 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
4902 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
4903 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
4904 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
4905 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
4906 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
4907 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
4908 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
4909 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
4910 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
4911 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
4912 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
4913 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
4914 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
4915 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
4916 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
4917 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
4918 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
4919 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
4920 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
4921 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
4922 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
4923 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
4924 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
4925 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
4926 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
4927 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
4928 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
4929 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
4930
4931 r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
4932
4933 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
4934 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
4935 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
4936 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
4937 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
4938 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
4939 r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
4940
4941 rtl_hw_aspm_clkreq_enable(tp, true);
4942 }
4943
4944 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
4945 {
4946 static const struct ephy_info e_info_8168h_1[] = {
4947 { 0x1e, 0x0800, 0x0001 },
4948 { 0x1d, 0x0000, 0x0800 },
4949 { 0x05, 0xffff, 0x2089 },
4950 { 0x06, 0xffff, 0x5881 },
4951 { 0x04, 0xffff, 0x854a },
4952 { 0x01, 0xffff, 0x068b }
4953 };
4954 int rg_saw_cnt;
4955
4956 /* disable aspm and clock request before access ephy */
4957 rtl_hw_aspm_clkreq_enable(tp, false);
4958 rtl_ephy_init(tp, e_info_8168h_1);
4959
4960 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4961 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4962
4963 rtl_set_def_aspm_entry_latency(tp);
4964
4965 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4966
4967 rtl_reset_packet_filter(tp);
4968
4969 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
4970
4971 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);
4972
4973 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
4974
4975 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4976
4977 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4978 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4979
4980 rtl8168_config_eee_mac(tp);
4981
4982 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4983 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4984
4985 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
4986
4987 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4988
4989 rtl_pcie_state_l2l3_disable(tp);
4990
4991 rtl_writephy(tp, 0x1f, 0x0c42);
4992 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
4993 rtl_writephy(tp, 0x1f, 0x0000);
4994 if (rg_saw_cnt > 0) {
4995 u16 sw_cnt_1ms_ini;
4996
4997 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
4998 sw_cnt_1ms_ini &= 0x0fff;
4999 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
5000 }
5001
5002 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
5003 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
5004 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
5005 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
5006
5007 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5008 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5009 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5010 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5011
5012 rtl_hw_aspm_clkreq_enable(tp, true);
5013 }
5014
5015 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5016 {
5017 rtl8168ep_stop_cmac(tp);
5018
5019 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5020 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
5021
5022 rtl_set_def_aspm_entry_latency(tp);
5023
5024 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5025
5026 rtl_reset_packet_filter(tp);
5027
5028 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
5029
5030 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
5031
5032 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5033
5034 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5035 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5036
5037 rtl8168_config_eee_mac(tp);
5038
5039 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
5040
5041 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5042
5043 rtl_pcie_state_l2l3_disable(tp);
5044 }
5045
5046 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5047 {
5048 static const struct ephy_info e_info_8168ep_1[] = {
5049 { 0x00, 0xffff, 0x10ab },
5050 { 0x06, 0xffff, 0xf030 },
5051 { 0x08, 0xffff, 0x2006 },
5052 { 0x0d, 0xffff, 0x1666 },
5053 { 0x0c, 0x3ff0, 0x0000 }
5054 };
5055
5056 /* disable aspm and clock request before access ephy */
5057 rtl_hw_aspm_clkreq_enable(tp, false);
5058 rtl_ephy_init(tp, e_info_8168ep_1);
5059
5060 rtl_hw_start_8168ep(tp);
5061
5062 rtl_hw_aspm_clkreq_enable(tp, true);
5063 }
5064
5065 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5066 {
5067 static const struct ephy_info e_info_8168ep_2[] = {
5068 { 0x00, 0xffff, 0x10a3 },
5069 { 0x19, 0xffff, 0xfc00 },
5070 { 0x1e, 0xffff, 0x20ea }
5071 };
5072
5073 /* disable aspm and clock request before access ephy */
5074 rtl_hw_aspm_clkreq_enable(tp, false);
5075 rtl_ephy_init(tp, e_info_8168ep_2);
5076
5077 rtl_hw_start_8168ep(tp);
5078
5079 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5080 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5081
5082 rtl_hw_aspm_clkreq_enable(tp, true);
5083 }
5084
5085 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5086 {
5087 static const struct ephy_info e_info_8168ep_3[] = {
5088 { 0x00, 0x0000, 0x0080 },
5089 { 0x0d, 0x0100, 0x0200 },
5090 { 0x19, 0x8021, 0x0000 },
5091 { 0x1e, 0x0000, 0x2000 },
5092 };
5093
5094 /* disable aspm and clock request before access ephy */
5095 rtl_hw_aspm_clkreq_enable(tp, false);
5096 rtl_ephy_init(tp, e_info_8168ep_3);
5097
5098 rtl_hw_start_8168ep(tp);
5099
5100 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5101 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5102
5103 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
5104 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
5105 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
5106
5107 rtl_hw_aspm_clkreq_enable(tp, true);
5108 }
5109
5110 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5111 {
5112 static const struct ephy_info e_info_8102e_1[] = {
5113 { 0x01, 0, 0x6e65 },
5114 { 0x02, 0, 0x091f },
5115 { 0x03, 0, 0xc2f9 },
5116 { 0x06, 0, 0xafb5 },
5117 { 0x07, 0, 0x0e00 },
5118 { 0x19, 0, 0xec80 },
5119 { 0x01, 0, 0x2e65 },
5120 { 0x01, 0, 0x6e65 }
5121 };
5122 u8 cfg1;
5123
5124 rtl_set_def_aspm_entry_latency(tp);
5125
5126 RTL_W8(tp, DBG_REG, FIX_NAK_1);
5127
5128 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5129
5130 RTL_W8(tp, Config1,
5131 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5132 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5133
5134 cfg1 = RTL_R8(tp, Config1);
5135 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5136 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5137
5138 rtl_ephy_init(tp, e_info_8102e_1);
5139 }
5140
5141 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5142 {
5143 rtl_set_def_aspm_entry_latency(tp);
5144
5145 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5146
5147 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5148 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5149 }
5150
5151 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5152 {
5153 rtl_hw_start_8102e_2(tp);
5154
5155 rtl_ephy_write(tp, 0x03, 0xc2f9);
5156 }
5157
5158 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5159 {
5160 static const struct ephy_info e_info_8105e_1[] = {
5161 { 0x07, 0, 0x4000 },
5162 { 0x19, 0, 0x0200 },
5163 { 0x19, 0, 0x0020 },
5164 { 0x1e, 0, 0x2000 },
5165 { 0x03, 0, 0x0001 },
5166 { 0x19, 0, 0x0100 },
5167 { 0x19, 0, 0x0004 },
5168 { 0x0a, 0, 0x0020 }
5169 };
5170
5171 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5172 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5173
5174 /* Disable Early Tally Counter */
5175 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5176
5177 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5178 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5179
5180 rtl_ephy_init(tp, e_info_8105e_1);
5181
5182 rtl_pcie_state_l2l3_disable(tp);
5183 }
5184
5185 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5186 {
5187 rtl_hw_start_8105e_1(tp);
5188 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5189 }
5190
5191 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5192 {
5193 static const struct ephy_info e_info_8402[] = {
5194 { 0x19, 0xffff, 0xff64 },
5195 { 0x1e, 0, 0x4000 }
5196 };
5197
5198 rtl_set_def_aspm_entry_latency(tp);
5199
5200 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5201 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5202
5203 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5204
5205 rtl_ephy_init(tp, e_info_8402);
5206
5207 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5208
5209 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
5210 rtl_reset_packet_filter(tp);
5211 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5212 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5213 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
5214
5215 rtl_pcie_state_l2l3_disable(tp);
5216 }
5217
5218 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5219 {
5220 rtl_hw_aspm_clkreq_enable(tp, false);
5221
5222 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5223 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5224
5225 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5226 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5227 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5228
5229 rtl_pcie_state_l2l3_disable(tp);
5230 rtl_hw_aspm_clkreq_enable(tp, true);
5231 }
5232
5233 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
5234 {
5235 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
5236 }
5237
5238 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
5239 {
5240 rtl_pcie_state_l2l3_disable(tp);
5241
5242 RTL_W16(tp, 0x382, 0x221b);
5243 RTL_W8(tp, 0x4500, 0);
5244 RTL_W16(tp, 0x4800, 0);
5245
5246 /* disable UPS */
5247 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
5248
5249 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
5250
5251 r8168_mac_ocp_write(tp, 0xc140, 0xffff);
5252 r8168_mac_ocp_write(tp, 0xc142, 0xffff);
5253
5254 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
5255 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
5256 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
5257
5258 /* disable new tx descriptor format */
5259 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
5260
5261 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
5262 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
5263 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
5264 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
5265 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
5266 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
5267 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
5268 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
5269 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0067);
5270 r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00);
5271 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
5272 r8168_mac_ocp_modify(tp, 0xe84c, 0x0000, 0x00c0);
5273 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
5274 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
5275 udelay(1);
5276 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
5277 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
5278
5279 r8168_mac_ocp_write(tp, 0xe098, 0xc302);
5280
5281 rtl_udelay_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
5282
5283 rtl8125_config_eee_mac(tp);
5284
5285 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5286 udelay(10);
5287 }
5288
5289 static void rtl_hw_start_8125_1(struct rtl8169_private *tp)
5290 {
5291 static const struct ephy_info e_info_8125_1[] = {
5292 { 0x01, 0xffff, 0xa812 },
5293 { 0x09, 0xffff, 0x520c },
5294 { 0x04, 0xffff, 0xd000 },
5295 { 0x0d, 0xffff, 0xf702 },
5296 { 0x0a, 0xffff, 0x8653 },
5297 { 0x06, 0xffff, 0x001e },
5298 { 0x08, 0xffff, 0x3595 },
5299 { 0x20, 0xffff, 0x9455 },
5300 { 0x21, 0xffff, 0x99ff },
5301 { 0x02, 0xffff, 0x6046 },
5302 { 0x29, 0xffff, 0xfe00 },
5303 { 0x23, 0xffff, 0xab62 },
5304
5305 { 0x41, 0xffff, 0xa80c },
5306 { 0x49, 0xffff, 0x520c },
5307 { 0x44, 0xffff, 0xd000 },
5308 { 0x4d, 0xffff, 0xf702 },
5309 { 0x4a, 0xffff, 0x8653 },
5310 { 0x46, 0xffff, 0x001e },
5311 { 0x48, 0xffff, 0x3595 },
5312 { 0x60, 0xffff, 0x9455 },
5313 { 0x61, 0xffff, 0x99ff },
5314 { 0x42, 0xffff, 0x6046 },
5315 { 0x69, 0xffff, 0xfe00 },
5316 { 0x63, 0xffff, 0xab62 },
5317 };
5318
5319 rtl_set_def_aspm_entry_latency(tp);
5320
5321 /* disable aspm and clock request before access ephy */
5322 rtl_hw_aspm_clkreq_enable(tp, false);
5323 rtl_ephy_init(tp, e_info_8125_1);
5324
5325 rtl_hw_start_8125_common(tp);
5326 }
5327
5328 static void rtl_hw_start_8125_2(struct rtl8169_private *tp)
5329 {
5330 static const struct ephy_info e_info_8125_2[] = {
5331 { 0x04, 0xffff, 0xd000 },
5332 { 0x0a, 0xffff, 0x8653 },
5333 { 0x23, 0xffff, 0xab66 },
5334 { 0x20, 0xffff, 0x9455 },
5335 { 0x21, 0xffff, 0x99ff },
5336 { 0x29, 0xffff, 0xfe04 },
5337
5338 { 0x44, 0xffff, 0xd000 },
5339 { 0x4a, 0xffff, 0x8653 },
5340 { 0x63, 0xffff, 0xab66 },
5341 { 0x60, 0xffff, 0x9455 },
5342 { 0x61, 0xffff, 0x99ff },
5343 { 0x69, 0xffff, 0xfe04 },
5344 };
5345
5346 rtl_set_def_aspm_entry_latency(tp);
5347
5348 /* disable aspm and clock request before access ephy */
5349 rtl_hw_aspm_clkreq_enable(tp, false);
5350 rtl_ephy_init(tp, e_info_8125_2);
5351
5352 rtl_hw_start_8125_common(tp);
5353 }
5354
5355 static void rtl_hw_config(struct rtl8169_private *tp)
5356 {
5357 static const rtl_generic_fct hw_configs[] = {
5358 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
5359 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
5360 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
5361 [RTL_GIGA_MAC_VER_10] = NULL,
5362 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168bb,
5363 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168bef,
5364 [RTL_GIGA_MAC_VER_13] = NULL,
5365 [RTL_GIGA_MAC_VER_14] = NULL,
5366 [RTL_GIGA_MAC_VER_15] = NULL,
5367 [RTL_GIGA_MAC_VER_16] = NULL,
5368 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168bef,
5369 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
5370 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
5371 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
5372 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
5373 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
5374 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
5375 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
5376 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
5377 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
5378 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
5379 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
5380 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
5381 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
5382 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168dp,
5383 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
5384 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
5385 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
5386 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
5387 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
5388 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
5389 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
5390 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
5391 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
5392 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
5393 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
5394 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
5395 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
5396 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
5397 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
5398 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
5399 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
5400 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
5401 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
5402 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
5403 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125_1,
5404 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125_2,
5405 };
5406
5407 if (hw_configs[tp->mac_version])
5408 hw_configs[tp->mac_version](tp);
5409 }
5410
5411 static void rtl_hw_start_8125(struct rtl8169_private *tp)
5412 {
5413 int i;
5414
5415 /* disable interrupt coalescing */
5416 for (i = 0xa00; i < 0xb00; i += 4)
5417 RTL_W32(tp, i, 0);
5418
5419 rtl_hw_config(tp);
5420 }
5421
5422 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5423 {
5424 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5425 tp->mac_version == RTL_GIGA_MAC_VER_16)
5426 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5427 PCI_EXP_DEVCTL_NOSNOOP_EN);
5428
5429 if (rtl_is_8168evl_up(tp))
5430 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5431 else
5432 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5433
5434 rtl_hw_config(tp);
5435
5436 /* disable interrupt coalescing */
5437 RTL_W16(tp, IntrMitigate, 0x0000);
5438 }
5439
5440 static void rtl_hw_start_8169(struct rtl8169_private *tp)
5441 {
5442 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5443 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
5444
5445 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
5446
5447 tp->cp_cmd |= PCIMulRW;
5448
5449 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5450 tp->mac_version == RTL_GIGA_MAC_VER_03) {
5451 netif_dbg(tp, drv, tp->dev,
5452 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
5453 tp->cp_cmd |= (1 << 14);
5454 }
5455
5456 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5457
5458 rtl8169_set_magic_reg(tp, tp->mac_version);
5459
5460 RTL_W32(tp, RxMissed, 0);
5461
5462 /* disable interrupt coalescing */
5463 RTL_W16(tp, IntrMitigate, 0x0000);
5464 }
5465
5466 static void rtl_hw_start(struct rtl8169_private *tp)
5467 {
5468 rtl_unlock_config_regs(tp);
5469
5470 tp->cp_cmd &= CPCMD_MASK;
5471 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5472
5473 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5474 rtl_hw_start_8169(tp);
5475 else if (rtl_is_8125(tp))
5476 rtl_hw_start_8125(tp);
5477 else
5478 rtl_hw_start_8168(tp);
5479
5480 rtl_set_rx_max_size(tp);
5481 rtl_set_rx_tx_desc_registers(tp);
5482 rtl_lock_config_regs(tp);
5483
5484 rtl_jumbo_config(tp, tp->dev->mtu);
5485
5486 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5487 RTL_R16(tp, CPlusCmd);
5488 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
5489 rtl_init_rxcfg(tp);
5490 rtl_set_tx_config_registers(tp);
5491 rtl_set_rx_mode(tp->dev);
5492 rtl_irq_enable(tp);
5493 }
5494
5495 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5496 {
5497 struct rtl8169_private *tp = netdev_priv(dev);
5498
5499 rtl_jumbo_config(tp, new_mtu);
5500
5501 dev->mtu = new_mtu;
5502 netdev_update_features(dev);
5503
5504 return 0;
5505 }
5506
5507 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5508 {
5509 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5510 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5511 }
5512
5513 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5514 {
5515 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5516
5517 /* Force memory writes to complete before releasing descriptor */
5518 dma_wmb();
5519
5520 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5521 }
5522
5523 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5524 struct RxDesc *desc)
5525 {
5526 struct device *d = tp_to_dev(tp);
5527 int node = dev_to_node(d);
5528 dma_addr_t mapping;
5529 struct page *data;
5530
5531 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
5532 if (!data)
5533 return NULL;
5534
5535 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5536 if (unlikely(dma_mapping_error(d, mapping))) {
5537 if (net_ratelimit())
5538 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5539 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
5540 return NULL;
5541 }
5542
5543 desc->addr = cpu_to_le64(mapping);
5544 rtl8169_mark_to_asic(desc);
5545
5546 return data;
5547 }
5548
5549 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5550 {
5551 unsigned int i;
5552
5553 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
5554 dma_unmap_page(tp_to_dev(tp),
5555 le64_to_cpu(tp->RxDescArray[i].addr),
5556 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5557 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
5558 tp->Rx_databuff[i] = NULL;
5559 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5560 }
5561 }
5562
5563 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5564 {
5565 desc->opts1 |= cpu_to_le32(RingEnd);
5566 }
5567
5568 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5569 {
5570 unsigned int i;
5571
5572 for (i = 0; i < NUM_RX_DESC; i++) {
5573 struct page *data;
5574
5575 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5576 if (!data) {
5577 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5578 goto err_out;
5579 }
5580 tp->Rx_databuff[i] = data;
5581 }
5582
5583 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5584 return 0;
5585
5586 err_out:
5587 rtl8169_rx_clear(tp);
5588 return -ENOMEM;
5589 }
5590
5591 static int rtl8169_init_ring(struct rtl8169_private *tp)
5592 {
5593 rtl8169_init_ring_indexes(tp);
5594
5595 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5596 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5597
5598 return rtl8169_rx_fill(tp);
5599 }
5600
5601 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5602 struct TxDesc *desc)
5603 {
5604 unsigned int len = tx_skb->len;
5605
5606 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5607
5608 desc->opts1 = 0x00;
5609 desc->opts2 = 0x00;
5610 desc->addr = 0x00;
5611 tx_skb->len = 0;
5612 }
5613
5614 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5615 unsigned int n)
5616 {
5617 unsigned int i;
5618
5619 for (i = 0; i < n; i++) {
5620 unsigned int entry = (start + i) % NUM_TX_DESC;
5621 struct ring_info *tx_skb = tp->tx_skb + entry;
5622 unsigned int len = tx_skb->len;
5623
5624 if (len) {
5625 struct sk_buff *skb = tx_skb->skb;
5626
5627 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5628 tp->TxDescArray + entry);
5629 if (skb) {
5630 dev_consume_skb_any(skb);
5631 tx_skb->skb = NULL;
5632 }
5633 }
5634 }
5635 }
5636
5637 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5638 {
5639 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5640 tp->cur_tx = tp->dirty_tx = 0;
5641 netdev_reset_queue(tp->dev);
5642 }
5643
5644 static void rtl_reset_work(struct rtl8169_private *tp)
5645 {
5646 struct net_device *dev = tp->dev;
5647 int i;
5648
5649 napi_disable(&tp->napi);
5650 netif_stop_queue(dev);
5651 synchronize_rcu();
5652
5653 rtl8169_hw_reset(tp);
5654
5655 for (i = 0; i < NUM_RX_DESC; i++)
5656 rtl8169_mark_to_asic(tp->RxDescArray + i);
5657
5658 rtl8169_tx_clear(tp);
5659 rtl8169_init_ring_indexes(tp);
5660
5661 napi_enable(&tp->napi);
5662 rtl_hw_start(tp);
5663 netif_wake_queue(dev);
5664 }
5665
5666 static void rtl8169_tx_timeout(struct net_device *dev)
5667 {
5668 struct rtl8169_private *tp = netdev_priv(dev);
5669
5670 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5671 }
5672
5673 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5674 {
5675 u32 status = opts0 | len;
5676
5677 if (entry == NUM_TX_DESC - 1)
5678 status |= RingEnd;
5679
5680 return cpu_to_le32(status);
5681 }
5682
5683 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5684 u32 *opts)
5685 {
5686 struct skb_shared_info *info = skb_shinfo(skb);
5687 unsigned int cur_frag, entry;
5688 struct TxDesc *uninitialized_var(txd);
5689 struct device *d = tp_to_dev(tp);
5690
5691 entry = tp->cur_tx;
5692 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5693 const skb_frag_t *frag = info->frags + cur_frag;
5694 dma_addr_t mapping;
5695 u32 len;
5696 void *addr;
5697
5698 entry = (entry + 1) % NUM_TX_DESC;
5699
5700 txd = tp->TxDescArray + entry;
5701 len = skb_frag_size(frag);
5702 addr = skb_frag_address(frag);
5703 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5704 if (unlikely(dma_mapping_error(d, mapping))) {
5705 if (net_ratelimit())
5706 netif_err(tp, drv, tp->dev,
5707 "Failed to map TX fragments DMA!\n");
5708 goto err_out;
5709 }
5710
5711 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5712 txd->opts2 = cpu_to_le32(opts[1]);
5713 txd->addr = cpu_to_le64(mapping);
5714
5715 tp->tx_skb[entry].len = len;
5716 }
5717
5718 if (cur_frag) {
5719 tp->tx_skb[entry].skb = skb;
5720 txd->opts1 |= cpu_to_le32(LastFrag);
5721 }
5722
5723 return cur_frag;
5724
5725 err_out:
5726 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5727 return -EIO;
5728 }
5729
5730 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5731 {
5732 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5733 }
5734
5735 /* msdn_giant_send_check()
5736 * According to the document of microsoft, the TCP Pseudo Header excludes the
5737 * packet length for IPv6 TCP large packets.
5738 */
5739 static int msdn_giant_send_check(struct sk_buff *skb)
5740 {
5741 const struct ipv6hdr *ipv6h;
5742 struct tcphdr *th;
5743 int ret;
5744
5745 ret = skb_cow_head(skb, 0);
5746 if (ret)
5747 return ret;
5748
5749 ipv6h = ipv6_hdr(skb);
5750 th = tcp_hdr(skb);
5751
5752 th->check = 0;
5753 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5754
5755 return ret;
5756 }
5757
5758 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
5759 {
5760 u32 mss = skb_shinfo(skb)->gso_size;
5761
5762 if (mss) {
5763 opts[0] |= TD_LSO;
5764 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5765 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5766 const struct iphdr *ip = ip_hdr(skb);
5767
5768 if (ip->protocol == IPPROTO_TCP)
5769 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5770 else if (ip->protocol == IPPROTO_UDP)
5771 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5772 else
5773 WARN_ON_ONCE(1);
5774 }
5775 }
5776
5777 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5778 struct sk_buff *skb, u32 *opts)
5779 {
5780 u32 transport_offset = (u32)skb_transport_offset(skb);
5781 u32 mss = skb_shinfo(skb)->gso_size;
5782
5783 if (mss) {
5784 switch (vlan_get_protocol(skb)) {
5785 case htons(ETH_P_IP):
5786 opts[0] |= TD1_GTSENV4;
5787 break;
5788
5789 case htons(ETH_P_IPV6):
5790 if (msdn_giant_send_check(skb))
5791 return false;
5792
5793 opts[0] |= TD1_GTSENV6;
5794 break;
5795
5796 default:
5797 WARN_ON_ONCE(1);
5798 break;
5799 }
5800
5801 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5802 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
5803 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5804 u8 ip_protocol;
5805
5806 switch (vlan_get_protocol(skb)) {
5807 case htons(ETH_P_IP):
5808 opts[1] |= TD1_IPv4_CS;
5809 ip_protocol = ip_hdr(skb)->protocol;
5810 break;
5811
5812 case htons(ETH_P_IPV6):
5813 opts[1] |= TD1_IPv6_CS;
5814 ip_protocol = ipv6_hdr(skb)->nexthdr;
5815 break;
5816
5817 default:
5818 ip_protocol = IPPROTO_RAW;
5819 break;
5820 }
5821
5822 if (ip_protocol == IPPROTO_TCP)
5823 opts[1] |= TD1_TCP_CS;
5824 else if (ip_protocol == IPPROTO_UDP)
5825 opts[1] |= TD1_UDP_CS;
5826 else
5827 WARN_ON_ONCE(1);
5828
5829 opts[1] |= transport_offset << TCPHO_SHIFT;
5830 } else {
5831 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5832 return !eth_skb_pad(skb);
5833 }
5834
5835 return true;
5836 }
5837
5838 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
5839 unsigned int nr_frags)
5840 {
5841 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
5842
5843 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
5844 return slots_avail > nr_frags;
5845 }
5846
5847 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
5848 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
5849 {
5850 switch (tp->mac_version) {
5851 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5852 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
5853 return false;
5854 default:
5855 return true;
5856 }
5857 }
5858
5859 static void rtl8169_doorbell(struct rtl8169_private *tp)
5860 {
5861 if (rtl_is_8125(tp))
5862 RTL_W16(tp, TxPoll_8125, BIT(0));
5863 else
5864 RTL_W8(tp, TxPoll, NPQ);
5865 }
5866
5867 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5868 struct net_device *dev)
5869 {
5870 struct rtl8169_private *tp = netdev_priv(dev);
5871 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5872 struct TxDesc *txd = tp->TxDescArray + entry;
5873 struct device *d = tp_to_dev(tp);
5874 dma_addr_t mapping;
5875 u32 opts[2], len;
5876 bool stop_queue;
5877 bool door_bell;
5878 int frags;
5879
5880 if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
5881 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5882 goto err_stop_0;
5883 }
5884
5885 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5886 goto err_stop_0;
5887
5888 opts[1] = rtl8169_tx_vlan_tag(skb);
5889 opts[0] = DescOwn;
5890
5891 if (rtl_chip_supports_csum_v2(tp)) {
5892 if (!rtl8169_tso_csum_v2(tp, skb, opts))
5893 goto err_dma_0;
5894 } else {
5895 rtl8169_tso_csum_v1(skb, opts);
5896 }
5897
5898 len = skb_headlen(skb);
5899 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5900 if (unlikely(dma_mapping_error(d, mapping))) {
5901 if (net_ratelimit())
5902 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5903 goto err_dma_0;
5904 }
5905
5906 tp->tx_skb[entry].len = len;
5907 txd->addr = cpu_to_le64(mapping);
5908
5909 frags = rtl8169_xmit_frags(tp, skb, opts);
5910 if (frags < 0)
5911 goto err_dma_1;
5912 else if (frags)
5913 opts[0] |= FirstFrag;
5914 else {
5915 opts[0] |= FirstFrag | LastFrag;
5916 tp->tx_skb[entry].skb = skb;
5917 }
5918
5919 txd->opts2 = cpu_to_le32(opts[1]);
5920
5921 skb_tx_timestamp(skb);
5922
5923 /* Force memory writes to complete before releasing descriptor */
5924 dma_wmb();
5925
5926 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
5927
5928 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5929
5930 /* Force all memory writes to complete before notifying device */
5931 wmb();
5932
5933 tp->cur_tx += frags + 1;
5934
5935 stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS);
5936 if (unlikely(stop_queue)) {
5937 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5938 * not miss a ring update when it notices a stopped queue.
5939 */
5940 smp_wmb();
5941 netif_stop_queue(dev);
5942 door_bell = true;
5943 }
5944
5945 if (door_bell)
5946 rtl8169_doorbell(tp);
5947
5948 if (unlikely(stop_queue)) {
5949 /* Sync with rtl_tx:
5950 * - publish queue status and cur_tx ring index (write barrier)
5951 * - refresh dirty_tx ring index (read barrier).
5952 * May the current thread have a pessimistic view of the ring
5953 * status and forget to wake up queue, a racing rtl_tx thread
5954 * can't.
5955 */
5956 smp_mb();
5957 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
5958 netif_start_queue(dev);
5959 }
5960
5961 return NETDEV_TX_OK;
5962
5963 err_dma_1:
5964 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5965 err_dma_0:
5966 dev_kfree_skb_any(skb);
5967 dev->stats.tx_dropped++;
5968 return NETDEV_TX_OK;
5969
5970 err_stop_0:
5971 netif_stop_queue(dev);
5972 dev->stats.tx_dropped++;
5973 return NETDEV_TX_BUSY;
5974 }
5975
5976 static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
5977 struct net_device *dev,
5978 netdev_features_t features)
5979 {
5980 int transport_offset = skb_transport_offset(skb);
5981 struct rtl8169_private *tp = netdev_priv(dev);
5982
5983 if (skb_is_gso(skb)) {
5984 if (transport_offset > GTTCPHO_MAX &&
5985 rtl_chip_supports_csum_v2(tp))
5986 features &= ~NETIF_F_ALL_TSO;
5987 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5988 if (skb->len < ETH_ZLEN) {
5989 switch (tp->mac_version) {
5990 case RTL_GIGA_MAC_VER_11:
5991 case RTL_GIGA_MAC_VER_12:
5992 case RTL_GIGA_MAC_VER_17:
5993 case RTL_GIGA_MAC_VER_34:
5994 features &= ~NETIF_F_CSUM_MASK;
5995 break;
5996 default:
5997 break;
5998 }
5999 }
6000
6001 if (transport_offset > TCPHO_MAX &&
6002 rtl_chip_supports_csum_v2(tp))
6003 features &= ~NETIF_F_CSUM_MASK;
6004 }
6005
6006 return vlan_features_check(skb, features);
6007 }
6008
6009 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6010 {
6011 struct rtl8169_private *tp = netdev_priv(dev);
6012 struct pci_dev *pdev = tp->pci_dev;
6013 u16 pci_status, pci_cmd;
6014
6015 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6016 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6017
6018 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6019 pci_cmd, pci_status);
6020
6021 /*
6022 * The recovery sequence below admits a very elaborated explanation:
6023 * - it seems to work;
6024 * - I did not see what else could be done;
6025 * - it makes iop3xx happy.
6026 *
6027 * Feel free to adjust to your needs.
6028 */
6029 if (pdev->broken_parity_status)
6030 pci_cmd &= ~PCI_COMMAND_PARITY;
6031 else
6032 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6033
6034 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6035
6036 pci_write_config_word(pdev, PCI_STATUS,
6037 pci_status & (PCI_STATUS_DETECTED_PARITY |
6038 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6039 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6040
6041 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6042 }
6043
6044 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
6045 int budget)
6046 {
6047 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
6048
6049 dirty_tx = tp->dirty_tx;
6050 smp_rmb();
6051 tx_left = tp->cur_tx - dirty_tx;
6052
6053 while (tx_left > 0) {
6054 unsigned int entry = dirty_tx % NUM_TX_DESC;
6055 struct ring_info *tx_skb = tp->tx_skb + entry;
6056 u32 status;
6057
6058 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6059 if (status & DescOwn)
6060 break;
6061
6062 /* This barrier is needed to keep us from reading
6063 * any other fields out of the Tx descriptor until
6064 * we know the status of DescOwn
6065 */
6066 dma_rmb();
6067
6068 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6069 tp->TxDescArray + entry);
6070 if (tx_skb->skb) {
6071 pkts_compl++;
6072 bytes_compl += tx_skb->skb->len;
6073 napi_consume_skb(tx_skb->skb, budget);
6074 tx_skb->skb = NULL;
6075 }
6076 dirty_tx++;
6077 tx_left--;
6078 }
6079
6080 if (tp->dirty_tx != dirty_tx) {
6081 netdev_completed_queue(dev, pkts_compl, bytes_compl);
6082
6083 u64_stats_update_begin(&tp->tx_stats.syncp);
6084 tp->tx_stats.packets += pkts_compl;
6085 tp->tx_stats.bytes += bytes_compl;
6086 u64_stats_update_end(&tp->tx_stats.syncp);
6087
6088 tp->dirty_tx = dirty_tx;
6089 /* Sync with rtl8169_start_xmit:
6090 * - publish dirty_tx ring index (write barrier)
6091 * - refresh cur_tx ring index and queue status (read barrier)
6092 * May the current thread miss the stopped queue condition,
6093 * a racing xmit thread can only have a right view of the
6094 * ring status.
6095 */
6096 smp_mb();
6097 if (netif_queue_stopped(dev) &&
6098 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
6099 netif_wake_queue(dev);
6100 }
6101 /*
6102 * 8168 hack: TxPoll requests are lost when the Tx packets are
6103 * too close. Let's kick an extra TxPoll request when a burst
6104 * of start_xmit activity is detected (if it is not detected,
6105 * it is slow enough). -- FR
6106 */
6107 if (tp->cur_tx != dirty_tx)
6108 rtl8169_doorbell(tp);
6109 }
6110 }
6111
6112 static inline int rtl8169_fragmented_frame(u32 status)
6113 {
6114 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6115 }
6116
6117 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6118 {
6119 u32 status = opts1 & RxProtoMask;
6120
6121 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6122 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6123 skb->ip_summed = CHECKSUM_UNNECESSARY;
6124 else
6125 skb_checksum_none_assert(skb);
6126 }
6127
6128 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6129 {
6130 unsigned int cur_rx, rx_left;
6131 unsigned int count;
6132
6133 cur_rx = tp->cur_rx;
6134
6135 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6136 unsigned int entry = cur_rx % NUM_RX_DESC;
6137 const void *rx_buf = page_address(tp->Rx_databuff[entry]);
6138 struct RxDesc *desc = tp->RxDescArray + entry;
6139 u32 status;
6140
6141 status = le32_to_cpu(desc->opts1);
6142 if (status & DescOwn)
6143 break;
6144
6145 /* This barrier is needed to keep us from reading
6146 * any other fields out of the Rx descriptor until
6147 * we know the status of DescOwn
6148 */
6149 dma_rmb();
6150
6151 if (unlikely(status & RxRES)) {
6152 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6153 status);
6154 dev->stats.rx_errors++;
6155 if (status & (RxRWT | RxRUNT))
6156 dev->stats.rx_length_errors++;
6157 if (status & RxCRC)
6158 dev->stats.rx_crc_errors++;
6159 if (status & (RxRUNT | RxCRC) && !(status & RxRWT) &&
6160 dev->features & NETIF_F_RXALL) {
6161 goto process_pkt;
6162 }
6163 } else {
6164 unsigned int pkt_size;
6165 struct sk_buff *skb;
6166
6167 process_pkt:
6168 pkt_size = status & GENMASK(13, 0);
6169 if (likely(!(dev->features & NETIF_F_RXFCS)))
6170 pkt_size -= ETH_FCS_LEN;
6171 /*
6172 * The driver does not support incoming fragmented
6173 * frames. They are seen as a symptom of over-mtu
6174 * sized frames.
6175 */
6176 if (unlikely(rtl8169_fragmented_frame(status))) {
6177 dev->stats.rx_dropped++;
6178 dev->stats.rx_length_errors++;
6179 goto release_descriptor;
6180 }
6181
6182 skb = napi_alloc_skb(&tp->napi, pkt_size);
6183 if (unlikely(!skb)) {
6184 dev->stats.rx_dropped++;
6185 goto release_descriptor;
6186 }
6187
6188 dma_sync_single_for_cpu(tp_to_dev(tp),
6189 le64_to_cpu(desc->addr),
6190 pkt_size, DMA_FROM_DEVICE);
6191 prefetch(rx_buf);
6192 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
6193 skb->tail += pkt_size;
6194 skb->len = pkt_size;
6195
6196 dma_sync_single_for_device(tp_to_dev(tp),
6197 le64_to_cpu(desc->addr),
6198 pkt_size, DMA_FROM_DEVICE);
6199
6200 rtl8169_rx_csum(skb, status);
6201 skb->protocol = eth_type_trans(skb, dev);
6202
6203 rtl8169_rx_vlan_tag(desc, skb);
6204
6205 if (skb->pkt_type == PACKET_MULTICAST)
6206 dev->stats.multicast++;
6207
6208 napi_gro_receive(&tp->napi, skb);
6209
6210 u64_stats_update_begin(&tp->rx_stats.syncp);
6211 tp->rx_stats.packets++;
6212 tp->rx_stats.bytes += pkt_size;
6213 u64_stats_update_end(&tp->rx_stats.syncp);
6214 }
6215 release_descriptor:
6216 desc->opts2 = 0;
6217 rtl8169_mark_to_asic(desc);
6218 }
6219
6220 count = cur_rx - tp->cur_rx;
6221 tp->cur_rx = cur_rx;
6222
6223 return count;
6224 }
6225
6226 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6227 {
6228 struct rtl8169_private *tp = dev_instance;
6229 u32 status = rtl_get_events(tp);
6230
6231 if (!tp->irq_enabled || (status & 0xffff) == 0xffff ||
6232 !(status & tp->irq_mask))
6233 return IRQ_NONE;
6234
6235 if (unlikely(status & SYSErr)) {
6236 rtl8169_pcierr_interrupt(tp->dev);
6237 goto out;
6238 }
6239
6240 if (status & LinkChg)
6241 phy_mac_interrupt(tp->phydev);
6242
6243 if (unlikely(status & RxFIFOOver &&
6244 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6245 netif_stop_queue(tp->dev);
6246 /* XXX - Hack alert. See rtl_task(). */
6247 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6248 }
6249
6250 rtl_irq_disable(tp);
6251 napi_schedule_irqoff(&tp->napi);
6252 out:
6253 rtl_ack_events(tp, status);
6254
6255 return IRQ_HANDLED;
6256 }
6257
6258 static void rtl_task(struct work_struct *work)
6259 {
6260 static const struct {
6261 int bitnr;
6262 void (*action)(struct rtl8169_private *);
6263 } rtl_work[] = {
6264 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6265 };
6266 struct rtl8169_private *tp =
6267 container_of(work, struct rtl8169_private, wk.work);
6268 struct net_device *dev = tp->dev;
6269 int i;
6270
6271 rtl_lock_work(tp);
6272
6273 if (!netif_running(dev) ||
6274 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6275 goto out_unlock;
6276
6277 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6278 bool pending;
6279
6280 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6281 if (pending)
6282 rtl_work[i].action(tp);
6283 }
6284
6285 out_unlock:
6286 rtl_unlock_work(tp);
6287 }
6288
6289 static int rtl8169_poll(struct napi_struct *napi, int budget)
6290 {
6291 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6292 struct net_device *dev = tp->dev;
6293 int work_done;
6294
6295 work_done = rtl_rx(dev, tp, (u32) budget);
6296
6297 rtl_tx(dev, tp, budget);
6298
6299 if (work_done < budget) {
6300 napi_complete_done(napi, work_done);
6301 rtl_irq_enable(tp);
6302 }
6303
6304 return work_done;
6305 }
6306
6307 static void rtl8169_rx_missed(struct net_device *dev)
6308 {
6309 struct rtl8169_private *tp = netdev_priv(dev);
6310
6311 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6312 return;
6313
6314 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6315 RTL_W32(tp, RxMissed, 0);
6316 }
6317
6318 static void r8169_phylink_handler(struct net_device *ndev)
6319 {
6320 struct rtl8169_private *tp = netdev_priv(ndev);
6321
6322 if (netif_carrier_ok(ndev)) {
6323 rtl_link_chg_patch(tp);
6324 pm_request_resume(&tp->pci_dev->dev);
6325 } else {
6326 pm_runtime_idle(&tp->pci_dev->dev);
6327 }
6328
6329 if (net_ratelimit())
6330 phy_print_status(tp->phydev);
6331 }
6332
6333 static int r8169_phy_connect(struct rtl8169_private *tp)
6334 {
6335 struct phy_device *phydev = tp->phydev;
6336 phy_interface_t phy_mode;
6337 int ret;
6338
6339 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6340 PHY_INTERFACE_MODE_MII;
6341
6342 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6343 phy_mode);
6344 if (ret)
6345 return ret;
6346
6347 if (!tp->supports_gmii)
6348 phy_set_max_speed(phydev, SPEED_100);
6349
6350 phy_support_asym_pause(phydev);
6351
6352 phy_attached_info(phydev);
6353
6354 return 0;
6355 }
6356
6357 static void rtl8169_down(struct net_device *dev)
6358 {
6359 struct rtl8169_private *tp = netdev_priv(dev);
6360
6361 phy_stop(tp->phydev);
6362
6363 napi_disable(&tp->napi);
6364 netif_stop_queue(dev);
6365
6366 rtl8169_hw_reset(tp);
6367 /*
6368 * At this point device interrupts can not be enabled in any function,
6369 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6370 * and napi is disabled (rtl8169_poll).
6371 */
6372 rtl8169_rx_missed(dev);
6373
6374 /* Give a racing hard_start_xmit a few cycles to complete. */
6375 synchronize_rcu();
6376
6377 rtl8169_tx_clear(tp);
6378
6379 rtl8169_rx_clear(tp);
6380
6381 rtl_pll_power_down(tp);
6382 }
6383
6384 static int rtl8169_close(struct net_device *dev)
6385 {
6386 struct rtl8169_private *tp = netdev_priv(dev);
6387 struct pci_dev *pdev = tp->pci_dev;
6388
6389 pm_runtime_get_sync(&pdev->dev);
6390
6391 /* Update counters before going down */
6392 rtl8169_update_counters(tp);
6393
6394 rtl_lock_work(tp);
6395 /* Clear all task flags */
6396 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6397
6398 rtl8169_down(dev);
6399 rtl_unlock_work(tp);
6400
6401 cancel_work_sync(&tp->wk.work);
6402
6403 phy_disconnect(tp->phydev);
6404
6405 pci_free_irq(pdev, 0, tp);
6406
6407 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6408 tp->RxPhyAddr);
6409 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6410 tp->TxPhyAddr);
6411 tp->TxDescArray = NULL;
6412 tp->RxDescArray = NULL;
6413
6414 pm_runtime_put_sync(&pdev->dev);
6415
6416 return 0;
6417 }
6418
6419 #ifdef CONFIG_NET_POLL_CONTROLLER
6420 static void rtl8169_netpoll(struct net_device *dev)
6421 {
6422 struct rtl8169_private *tp = netdev_priv(dev);
6423
6424 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6425 }
6426 #endif
6427
6428 static int rtl_open(struct net_device *dev)
6429 {
6430 struct rtl8169_private *tp = netdev_priv(dev);
6431 struct pci_dev *pdev = tp->pci_dev;
6432 int retval = -ENOMEM;
6433
6434 pm_runtime_get_sync(&pdev->dev);
6435
6436 /*
6437 * Rx and Tx descriptors needs 256 bytes alignment.
6438 * dma_alloc_coherent provides more.
6439 */
6440 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6441 &tp->TxPhyAddr, GFP_KERNEL);
6442 if (!tp->TxDescArray)
6443 goto err_pm_runtime_put;
6444
6445 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6446 &tp->RxPhyAddr, GFP_KERNEL);
6447 if (!tp->RxDescArray)
6448 goto err_free_tx_0;
6449
6450 retval = rtl8169_init_ring(tp);
6451 if (retval < 0)
6452 goto err_free_rx_1;
6453
6454 rtl_request_firmware(tp);
6455
6456 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6457 dev->name);
6458 if (retval < 0)
6459 goto err_release_fw_2;
6460
6461 retval = r8169_phy_connect(tp);
6462 if (retval)
6463 goto err_free_irq;
6464
6465 rtl_lock_work(tp);
6466
6467 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6468
6469 napi_enable(&tp->napi);
6470
6471 rtl8169_init_phy(dev, tp);
6472
6473 rtl_pll_power_up(tp);
6474
6475 rtl_hw_start(tp);
6476
6477 if (!rtl8169_init_counter_offsets(tp))
6478 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6479
6480 phy_start(tp->phydev);
6481 netif_start_queue(dev);
6482
6483 rtl_unlock_work(tp);
6484
6485 pm_runtime_put_sync(&pdev->dev);
6486 out:
6487 return retval;
6488
6489 err_free_irq:
6490 pci_free_irq(pdev, 0, tp);
6491 err_release_fw_2:
6492 rtl_release_firmware(tp);
6493 rtl8169_rx_clear(tp);
6494 err_free_rx_1:
6495 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6496 tp->RxPhyAddr);
6497 tp->RxDescArray = NULL;
6498 err_free_tx_0:
6499 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6500 tp->TxPhyAddr);
6501 tp->TxDescArray = NULL;
6502 err_pm_runtime_put:
6503 pm_runtime_put_noidle(&pdev->dev);
6504 goto out;
6505 }
6506
6507 static void
6508 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6509 {
6510 struct rtl8169_private *tp = netdev_priv(dev);
6511 struct pci_dev *pdev = tp->pci_dev;
6512 struct rtl8169_counters *counters = tp->counters;
6513 unsigned int start;
6514
6515 pm_runtime_get_noresume(&pdev->dev);
6516
6517 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6518 rtl8169_rx_missed(dev);
6519
6520 do {
6521 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6522 stats->rx_packets = tp->rx_stats.packets;
6523 stats->rx_bytes = tp->rx_stats.bytes;
6524 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6525
6526 do {
6527 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6528 stats->tx_packets = tp->tx_stats.packets;
6529 stats->tx_bytes = tp->tx_stats.bytes;
6530 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6531
6532 stats->rx_dropped = dev->stats.rx_dropped;
6533 stats->tx_dropped = dev->stats.tx_dropped;
6534 stats->rx_length_errors = dev->stats.rx_length_errors;
6535 stats->rx_errors = dev->stats.rx_errors;
6536 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6537 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6538 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6539 stats->multicast = dev->stats.multicast;
6540
6541 /*
6542 * Fetch additional counter values missing in stats collected by driver
6543 * from tally counters.
6544 */
6545 if (pm_runtime_active(&pdev->dev))
6546 rtl8169_update_counters(tp);
6547
6548 /*
6549 * Subtract values fetched during initalization.
6550 * See rtl8169_init_counter_offsets for a description why we do that.
6551 */
6552 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6553 le64_to_cpu(tp->tc_offset.tx_errors);
6554 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6555 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6556 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6557 le16_to_cpu(tp->tc_offset.tx_aborted);
6558
6559 pm_runtime_put_noidle(&pdev->dev);
6560 }
6561
6562 static void rtl8169_net_suspend(struct net_device *dev)
6563 {
6564 struct rtl8169_private *tp = netdev_priv(dev);
6565
6566 if (!netif_running(dev))
6567 return;
6568
6569 phy_stop(tp->phydev);
6570 netif_device_detach(dev);
6571
6572 rtl_lock_work(tp);
6573 napi_disable(&tp->napi);
6574 /* Clear all task flags */
6575 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6576
6577 rtl_unlock_work(tp);
6578
6579 rtl_pll_power_down(tp);
6580 }
6581
6582 #ifdef CONFIG_PM
6583
6584 static int rtl8169_suspend(struct device *device)
6585 {
6586 struct net_device *dev = dev_get_drvdata(device);
6587 struct rtl8169_private *tp = netdev_priv(dev);
6588
6589 rtl8169_net_suspend(dev);
6590 clk_disable_unprepare(tp->clk);
6591
6592 return 0;
6593 }
6594
6595 static void __rtl8169_resume(struct net_device *dev)
6596 {
6597 struct rtl8169_private *tp = netdev_priv(dev);
6598
6599 netif_device_attach(dev);
6600
6601 rtl_pll_power_up(tp);
6602 rtl8169_init_phy(dev, tp);
6603
6604 phy_start(tp->phydev);
6605
6606 rtl_lock_work(tp);
6607 napi_enable(&tp->napi);
6608 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6609 rtl_reset_work(tp);
6610 rtl_unlock_work(tp);
6611 }
6612
6613 static int rtl8169_resume(struct device *device)
6614 {
6615 struct net_device *dev = dev_get_drvdata(device);
6616 struct rtl8169_private *tp = netdev_priv(dev);
6617
6618 rtl_rar_set(tp, dev->dev_addr);
6619
6620 clk_prepare_enable(tp->clk);
6621
6622 if (netif_running(dev))
6623 __rtl8169_resume(dev);
6624
6625 return 0;
6626 }
6627
6628 static int rtl8169_runtime_suspend(struct device *device)
6629 {
6630 struct net_device *dev = dev_get_drvdata(device);
6631 struct rtl8169_private *tp = netdev_priv(dev);
6632
6633 if (!tp->TxDescArray)
6634 return 0;
6635
6636 rtl_lock_work(tp);
6637 __rtl8169_set_wol(tp, WAKE_ANY);
6638 rtl_unlock_work(tp);
6639
6640 rtl8169_net_suspend(dev);
6641
6642 /* Update counters before going runtime suspend */
6643 rtl8169_rx_missed(dev);
6644 rtl8169_update_counters(tp);
6645
6646 return 0;
6647 }
6648
6649 static int rtl8169_runtime_resume(struct device *device)
6650 {
6651 struct net_device *dev = dev_get_drvdata(device);
6652 struct rtl8169_private *tp = netdev_priv(dev);
6653
6654 rtl_rar_set(tp, dev->dev_addr);
6655
6656 if (!tp->TxDescArray)
6657 return 0;
6658
6659 rtl_lock_work(tp);
6660 __rtl8169_set_wol(tp, tp->saved_wolopts);
6661 rtl_unlock_work(tp);
6662
6663 __rtl8169_resume(dev);
6664
6665 return 0;
6666 }
6667
6668 static int rtl8169_runtime_idle(struct device *device)
6669 {
6670 struct net_device *dev = dev_get_drvdata(device);
6671
6672 if (!netif_running(dev) || !netif_carrier_ok(dev))
6673 pm_schedule_suspend(device, 10000);
6674
6675 return -EBUSY;
6676 }
6677
6678 static const struct dev_pm_ops rtl8169_pm_ops = {
6679 .suspend = rtl8169_suspend,
6680 .resume = rtl8169_resume,
6681 .freeze = rtl8169_suspend,
6682 .thaw = rtl8169_resume,
6683 .poweroff = rtl8169_suspend,
6684 .restore = rtl8169_resume,
6685 .runtime_suspend = rtl8169_runtime_suspend,
6686 .runtime_resume = rtl8169_runtime_resume,
6687 .runtime_idle = rtl8169_runtime_idle,
6688 };
6689
6690 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
6691
6692 #else /* !CONFIG_PM */
6693
6694 #define RTL8169_PM_OPS NULL
6695
6696 #endif /* !CONFIG_PM */
6697
6698 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6699 {
6700 /* WoL fails with 8168b when the receiver is disabled. */
6701 switch (tp->mac_version) {
6702 case RTL_GIGA_MAC_VER_11:
6703 case RTL_GIGA_MAC_VER_12:
6704 case RTL_GIGA_MAC_VER_17:
6705 pci_clear_master(tp->pci_dev);
6706
6707 RTL_W8(tp, ChipCmd, CmdRxEnb);
6708 /* PCI commit */
6709 RTL_R8(tp, ChipCmd);
6710 break;
6711 default:
6712 break;
6713 }
6714 }
6715
6716 static void rtl_shutdown(struct pci_dev *pdev)
6717 {
6718 struct net_device *dev = pci_get_drvdata(pdev);
6719 struct rtl8169_private *tp = netdev_priv(dev);
6720
6721 rtl8169_net_suspend(dev);
6722
6723 /* Restore original MAC address */
6724 rtl_rar_set(tp, dev->perm_addr);
6725
6726 rtl8169_hw_reset(tp);
6727
6728 if (system_state == SYSTEM_POWER_OFF) {
6729 if (tp->saved_wolopts) {
6730 rtl_wol_suspend_quirk(tp);
6731 rtl_wol_shutdown_quirk(tp);
6732 }
6733
6734 pci_wake_from_d3(pdev, true);
6735 pci_set_power_state(pdev, PCI_D3hot);
6736 }
6737 }
6738
6739 static void rtl_remove_one(struct pci_dev *pdev)
6740 {
6741 struct net_device *dev = pci_get_drvdata(pdev);
6742 struct rtl8169_private *tp = netdev_priv(dev);
6743
6744 if (r8168_check_dash(tp))
6745 rtl8168_driver_stop(tp);
6746
6747 netif_napi_del(&tp->napi);
6748
6749 unregister_netdev(dev);
6750 mdiobus_unregister(tp->phydev->mdio.bus);
6751
6752 rtl_release_firmware(tp);
6753
6754 if (pci_dev_run_wake(pdev))
6755 pm_runtime_get_noresume(&pdev->dev);
6756
6757 /* restore original MAC address */
6758 rtl_rar_set(tp, dev->perm_addr);
6759 }
6760
6761 static const struct net_device_ops rtl_netdev_ops = {
6762 .ndo_open = rtl_open,
6763 .ndo_stop = rtl8169_close,
6764 .ndo_get_stats64 = rtl8169_get_stats64,
6765 .ndo_start_xmit = rtl8169_start_xmit,
6766 .ndo_features_check = rtl8169_features_check,
6767 .ndo_tx_timeout = rtl8169_tx_timeout,
6768 .ndo_validate_addr = eth_validate_addr,
6769 .ndo_change_mtu = rtl8169_change_mtu,
6770 .ndo_fix_features = rtl8169_fix_features,
6771 .ndo_set_features = rtl8169_set_features,
6772 .ndo_set_mac_address = rtl_set_mac_address,
6773 .ndo_do_ioctl = rtl8169_ioctl,
6774 .ndo_set_rx_mode = rtl_set_rx_mode,
6775 #ifdef CONFIG_NET_POLL_CONTROLLER
6776 .ndo_poll_controller = rtl8169_netpoll,
6777 #endif
6778
6779 };
6780
6781 static void rtl_set_irq_mask(struct rtl8169_private *tp)
6782 {
6783 tp->irq_mask = RTL_EVENT_NAPI | LinkChg;
6784
6785 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6786 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
6787 else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
6788 /* special workaround needed */
6789 tp->irq_mask |= RxFIFOOver;
6790 else
6791 tp->irq_mask |= RxOverflow;
6792 }
6793
6794 static int rtl_alloc_irq(struct rtl8169_private *tp)
6795 {
6796 unsigned int flags;
6797
6798 switch (tp->mac_version) {
6799 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
6800 rtl_unlock_config_regs(tp);
6801 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
6802 rtl_lock_config_regs(tp);
6803 /* fall through */
6804 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_24:
6805 flags = PCI_IRQ_LEGACY;
6806 break;
6807 default:
6808 flags = PCI_IRQ_ALL_TYPES;
6809 break;
6810 }
6811
6812 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
6813 }
6814
6815 static void rtl_read_mac_address(struct rtl8169_private *tp,
6816 u8 mac_addr[ETH_ALEN])
6817 {
6818 /* Get MAC address */
6819 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
6820 u32 value = rtl_eri_read(tp, 0xe0);
6821
6822 mac_addr[0] = (value >> 0) & 0xff;
6823 mac_addr[1] = (value >> 8) & 0xff;
6824 mac_addr[2] = (value >> 16) & 0xff;
6825 mac_addr[3] = (value >> 24) & 0xff;
6826
6827 value = rtl_eri_read(tp, 0xe4);
6828 mac_addr[4] = (value >> 0) & 0xff;
6829 mac_addr[5] = (value >> 8) & 0xff;
6830 } else if (rtl_is_8125(tp)) {
6831 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
6832 }
6833 }
6834
6835 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6836 {
6837 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
6838 }
6839
6840 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6841 {
6842 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6843 }
6844
6845 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
6846 {
6847 struct rtl8169_private *tp = mii_bus->priv;
6848
6849 if (phyaddr > 0)
6850 return -ENODEV;
6851
6852 return rtl_readphy(tp, phyreg);
6853 }
6854
6855 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
6856 int phyreg, u16 val)
6857 {
6858 struct rtl8169_private *tp = mii_bus->priv;
6859
6860 if (phyaddr > 0)
6861 return -ENODEV;
6862
6863 rtl_writephy(tp, phyreg, val);
6864
6865 return 0;
6866 }
6867
6868 static int r8169_mdio_register(struct rtl8169_private *tp)
6869 {
6870 struct pci_dev *pdev = tp->pci_dev;
6871 struct mii_bus *new_bus;
6872 int ret;
6873
6874 new_bus = devm_mdiobus_alloc(&pdev->dev);
6875 if (!new_bus)
6876 return -ENOMEM;
6877
6878 new_bus->name = "r8169";
6879 new_bus->priv = tp;
6880 new_bus->parent = &pdev->dev;
6881 new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
6882 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
6883
6884 new_bus->read = r8169_mdio_read_reg;
6885 new_bus->write = r8169_mdio_write_reg;
6886
6887 ret = mdiobus_register(new_bus);
6888 if (ret)
6889 return ret;
6890
6891 tp->phydev = mdiobus_get_phy(new_bus, 0);
6892 if (!tp->phydev) {
6893 mdiobus_unregister(new_bus);
6894 return -ENODEV;
6895 }
6896
6897 /* PHY will be woken up in rtl_open() */
6898 phy_suspend(tp->phydev);
6899
6900 return 0;
6901 }
6902
6903 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6904 {
6905 tp->ocp_base = OCP_STD_PHY_BASE;
6906
6907 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
6908
6909 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6910 return;
6911
6912 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6913 return;
6914
6915 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6916 msleep(1);
6917 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6918
6919 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
6920
6921 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6922 return;
6923
6924 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
6925
6926 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
6927 }
6928
6929 static void rtl_hw_init_8125(struct rtl8169_private *tp)
6930 {
6931 tp->ocp_base = OCP_STD_PHY_BASE;
6932
6933 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
6934
6935 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6936 return;
6937
6938 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6939 msleep(1);
6940 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6941
6942 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
6943
6944 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6945 return;
6946
6947 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
6948 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
6949 r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
6950
6951 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
6952 }
6953
6954 static void rtl_hw_initialize(struct rtl8169_private *tp)
6955 {
6956 switch (tp->mac_version) {
6957 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
6958 rtl8168ep_stop_cmac(tp);
6959 /* fall through */
6960 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
6961 rtl_hw_init_8168g(tp);
6962 break;
6963 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
6964 rtl_hw_init_8125(tp);
6965 break;
6966 default:
6967 break;
6968 }
6969 }
6970
6971 static int rtl_jumbo_max(struct rtl8169_private *tp)
6972 {
6973 /* Non-GBit versions don't support jumbo frames */
6974 if (!tp->supports_gmii)
6975 return JUMBO_1K;
6976
6977 switch (tp->mac_version) {
6978 /* RTL8169 */
6979 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
6980 return JUMBO_7K;
6981 /* RTL8168b */
6982 case RTL_GIGA_MAC_VER_11:
6983 case RTL_GIGA_MAC_VER_12:
6984 case RTL_GIGA_MAC_VER_17:
6985 return JUMBO_4K;
6986 /* RTL8168c */
6987 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
6988 return JUMBO_6K;
6989 default:
6990 return JUMBO_9K;
6991 }
6992 }
6993
6994 static void rtl_disable_clk(void *data)
6995 {
6996 clk_disable_unprepare(data);
6997 }
6998
6999 static int rtl_get_ether_clk(struct rtl8169_private *tp)
7000 {
7001 struct device *d = tp_to_dev(tp);
7002 struct clk *clk;
7003 int rc;
7004
7005 clk = devm_clk_get(d, "ether_clk");
7006 if (IS_ERR(clk)) {
7007 rc = PTR_ERR(clk);
7008 if (rc == -ENOENT)
7009 /* clk-core allows NULL (for suspend / resume) */
7010 rc = 0;
7011 else if (rc != -EPROBE_DEFER)
7012 dev_err(d, "failed to get clk: %d\n", rc);
7013 } else {
7014 tp->clk = clk;
7015 rc = clk_prepare_enable(clk);
7016 if (rc)
7017 dev_err(d, "failed to enable clk: %d\n", rc);
7018 else
7019 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
7020 }
7021
7022 return rc;
7023 }
7024
7025 static void rtl_init_mac_address(struct rtl8169_private *tp)
7026 {
7027 struct net_device *dev = tp->dev;
7028 u8 *mac_addr = dev->dev_addr;
7029 int rc;
7030
7031 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
7032 if (!rc)
7033 goto done;
7034
7035 rtl_read_mac_address(tp, mac_addr);
7036 if (is_valid_ether_addr(mac_addr))
7037 goto done;
7038
7039 rtl_read_mac_from_reg(tp, mac_addr, MAC0);
7040 if (is_valid_ether_addr(mac_addr))
7041 goto done;
7042
7043 eth_hw_addr_random(dev);
7044 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
7045 done:
7046 rtl_rar_set(tp, mac_addr);
7047 }
7048
7049 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7050 {
7051 struct rtl8169_private *tp;
7052 struct net_device *dev;
7053 int chipset, region;
7054 int jumbo_max, rc;
7055
7056 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7057 if (!dev)
7058 return -ENOMEM;
7059
7060 SET_NETDEV_DEV(dev, &pdev->dev);
7061 dev->netdev_ops = &rtl_netdev_ops;
7062 tp = netdev_priv(dev);
7063 tp->dev = dev;
7064 tp->pci_dev = pdev;
7065 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7066 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
7067
7068 /* Get the *optional* external "ether_clk" used on some boards */
7069 rc = rtl_get_ether_clk(tp);
7070 if (rc)
7071 return rc;
7072
7073 /* Disable ASPM completely as that cause random device stop working
7074 * problems as well as full system hangs for some PCIe devices users.
7075 */
7076 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
7077 PCIE_LINK_STATE_L1);
7078 tp->aspm_manageable = !rc;
7079
7080 /* enable device (incl. PCI PM wakeup and hotplug setup) */
7081 rc = pcim_enable_device(pdev);
7082 if (rc < 0) {
7083 dev_err(&pdev->dev, "enable failure\n");
7084 return rc;
7085 }
7086
7087 if (pcim_set_mwi(pdev) < 0)
7088 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7089
7090 /* use first MMIO region */
7091 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7092 if (region < 0) {
7093 dev_err(&pdev->dev, "no MMIO resource found\n");
7094 return -ENODEV;
7095 }
7096
7097 /* check for weird/broken PCI region reporting */
7098 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7099 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7100 return -ENODEV;
7101 }
7102
7103 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7104 if (rc < 0) {
7105 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7106 return rc;
7107 }
7108
7109 tp->mmio_addr = pcim_iomap_table(pdev)[region];
7110
7111 /* Identify chip attached to board */
7112 rtl8169_get_mac_version(tp);
7113 if (tp->mac_version == RTL_GIGA_MAC_NONE)
7114 return -ENODEV;
7115
7116 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7117
7118 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
7119 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
7120 dev->features |= NETIF_F_HIGHDMA;
7121
7122 rtl_init_rxcfg(tp);
7123
7124 rtl8169_irq_mask_and_ack(tp);
7125
7126 rtl_hw_initialize(tp);
7127
7128 rtl_hw_reset(tp);
7129
7130 pci_set_master(pdev);
7131
7132 chipset = tp->mac_version;
7133
7134 rc = rtl_alloc_irq(tp);
7135 if (rc < 0) {
7136 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7137 return rc;
7138 }
7139
7140 mutex_init(&tp->wk.mutex);
7141 INIT_WORK(&tp->wk.work, rtl_task);
7142 u64_stats_init(&tp->rx_stats.syncp);
7143 u64_stats_init(&tp->tx_stats.syncp);
7144
7145 rtl_init_mac_address(tp);
7146
7147 dev->ethtool_ops = &rtl8169_ethtool_ops;
7148
7149 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7150
7151 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7152 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7153 NETIF_F_HW_VLAN_CTAG_RX;
7154 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7155 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7156 NETIF_F_HW_VLAN_CTAG_RX;
7157 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7158 NETIF_F_HIGHDMA;
7159 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7160
7161 tp->cp_cmd |= RxChkSum;
7162 /* RTL8125 uses register RxConfig for VLAN offloading config */
7163 if (!rtl_is_8125(tp))
7164 tp->cp_cmd |= RxVlan;
7165 /*
7166 * Pretend we are using VLANs; This bypasses a nasty bug where
7167 * Interrupts stop flowing on high load on 8110SCd controllers.
7168 */
7169 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7170 /* Disallow toggling */
7171 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7172
7173 if (rtl_chip_supports_csum_v2(tp)) {
7174 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7175 dev->features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7176 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2;
7177 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2;
7178 } else {
7179 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1;
7180 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1;
7181 }
7182
7183 /* RTL8168e-vl and one RTL8168c variant are known to have a
7184 * HW issue with TSO.
7185 */
7186 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
7187 tp->mac_version == RTL_GIGA_MAC_VER_22) {
7188 dev->vlan_features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG);
7189 dev->hw_features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG);
7190 dev->features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG);
7191 }
7192
7193 dev->hw_features |= NETIF_F_RXALL;
7194 dev->hw_features |= NETIF_F_RXFCS;
7195
7196 /* MTU range: 60 - hw-specific max */
7197 dev->min_mtu = ETH_ZLEN;
7198 jumbo_max = rtl_jumbo_max(tp);
7199 dev->max_mtu = jumbo_max;
7200
7201 rtl_set_irq_mask(tp);
7202
7203 tp->fw_name = rtl_chip_infos[chipset].fw_name;
7204
7205 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7206 &tp->counters_phys_addr,
7207 GFP_KERNEL);
7208 if (!tp->counters)
7209 return -ENOMEM;
7210
7211 pci_set_drvdata(pdev, dev);
7212
7213 rc = r8169_mdio_register(tp);
7214 if (rc)
7215 return rc;
7216
7217 /* chip gets powered up in rtl_open() */
7218 rtl_pll_power_down(tp);
7219
7220 rc = register_netdev(dev);
7221 if (rc)
7222 goto err_mdio_unregister;
7223
7224 netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
7225 rtl_chip_infos[chipset].name, dev->dev_addr,
7226 (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
7227 pci_irq_vector(pdev, 0));
7228
7229 if (jumbo_max > JUMBO_1K)
7230 netif_info(tp, probe, dev,
7231 "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7232 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7233 "ok" : "ko");
7234
7235 if (r8168_check_dash(tp))
7236 rtl8168_driver_start(tp);
7237
7238 if (pci_dev_run_wake(pdev))
7239 pm_runtime_put_sync(&pdev->dev);
7240
7241 return 0;
7242
7243 err_mdio_unregister:
7244 mdiobus_unregister(tp->phydev->mdio.bus);
7245 return rc;
7246 }
7247
7248 static struct pci_driver rtl8169_pci_driver = {
7249 .name = MODULENAME,
7250 .id_table = rtl8169_pci_tbl,
7251 .probe = rtl_init_one,
7252 .remove = rtl_remove_one,
7253 .shutdown = rtl_shutdown,
7254 .driver.pm = RTL8169_PM_OPS,
7255 };
7256
7257 module_pci_driver(rtl8169_pci_driver);
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