]> git.proxmox.com Git - mirror_ubuntu-focal-kernel.git/blob - drivers/net/ethernet/realtek/r8169_main.c
projects / mirror_ubuntu-focal-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
r8169: improve handling of Abit Fatal1ty F-190HD
[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / realtek / r8169_main.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 *
5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
7 * Copyright (c) a lot of people too. Please respect their work.
8 *
9 * See MAINTAINERS file for support contact information.
10 */
11
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/pci.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/ethtool.h>
20 #include <linux/phy.h>
21 #include <linux/if_vlan.h>
22 #include <linux/crc32.h>
23 #include <linux/in.h>
24 #include <linux/io.h>
25 #include <linux/ip.h>
26 #include <linux/tcp.h>
27 #include <linux/interrupt.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/prefetch.h>
31 #include <linux/pci-aspm.h>
32 #include <linux/ipv6.h>
33 #include <net/ip6_checksum.h>
34
35 #include "r8169_firmware.h"
36
37 #define MODULENAME "r8169"
38
39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
47 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
48 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
49 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
50 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
51 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
52 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
53 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
54 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
55 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
56 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
57 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
58
59 #define R8169_MSG_DEFAULT \
60 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
61
62 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
63 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
64 static const int multicast_filter_limit = 32;
65
66 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
67 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
68
69 #define R8169_REGS_SIZE 256
70 #define R8169_RX_BUF_SIZE (SZ_16K - 1)
71 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
72 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
73 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
74 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
75
76 #define RTL_CFG_NO_GBIT 1
77
78 /* write/read MMIO register */
79 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
80 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
81 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
82 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
83 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
84 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
85
86 enum mac_version {
87 /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */
88 RTL_GIGA_MAC_VER_02,
89 RTL_GIGA_MAC_VER_03,
90 RTL_GIGA_MAC_VER_04,
91 RTL_GIGA_MAC_VER_05,
92 RTL_GIGA_MAC_VER_06,
93 RTL_GIGA_MAC_VER_07,
94 RTL_GIGA_MAC_VER_08,
95 RTL_GIGA_MAC_VER_09,
96 RTL_GIGA_MAC_VER_10,
97 RTL_GIGA_MAC_VER_11,
98 RTL_GIGA_MAC_VER_12,
99 RTL_GIGA_MAC_VER_13,
100 RTL_GIGA_MAC_VER_14,
101 RTL_GIGA_MAC_VER_15,
102 RTL_GIGA_MAC_VER_16,
103 RTL_GIGA_MAC_VER_17,
104 RTL_GIGA_MAC_VER_18,
105 RTL_GIGA_MAC_VER_19,
106 RTL_GIGA_MAC_VER_20,
107 RTL_GIGA_MAC_VER_21,
108 RTL_GIGA_MAC_VER_22,
109 RTL_GIGA_MAC_VER_23,
110 RTL_GIGA_MAC_VER_24,
111 RTL_GIGA_MAC_VER_25,
112 RTL_GIGA_MAC_VER_26,
113 RTL_GIGA_MAC_VER_27,
114 RTL_GIGA_MAC_VER_28,
115 RTL_GIGA_MAC_VER_29,
116 RTL_GIGA_MAC_VER_30,
117 RTL_GIGA_MAC_VER_31,
118 RTL_GIGA_MAC_VER_32,
119 RTL_GIGA_MAC_VER_33,
120 RTL_GIGA_MAC_VER_34,
121 RTL_GIGA_MAC_VER_35,
122 RTL_GIGA_MAC_VER_36,
123 RTL_GIGA_MAC_VER_37,
124 RTL_GIGA_MAC_VER_38,
125 RTL_GIGA_MAC_VER_39,
126 RTL_GIGA_MAC_VER_40,
127 RTL_GIGA_MAC_VER_41,
128 RTL_GIGA_MAC_VER_42,
129 RTL_GIGA_MAC_VER_43,
130 RTL_GIGA_MAC_VER_44,
131 RTL_GIGA_MAC_VER_45,
132 RTL_GIGA_MAC_VER_46,
133 RTL_GIGA_MAC_VER_47,
134 RTL_GIGA_MAC_VER_48,
135 RTL_GIGA_MAC_VER_49,
136 RTL_GIGA_MAC_VER_50,
137 RTL_GIGA_MAC_VER_51,
138 RTL_GIGA_MAC_NONE
139 };
140
141 #define JUMBO_1K ETH_DATA_LEN
142 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
143 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
144 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
145 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
146
147 static const struct {
148 const char *name;
149 const char *fw_name;
150 } rtl_chip_infos[] = {
151 /* PCI devices. */
152 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
153 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
154 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
155 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
156 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
157 /* PCI-E devices. */
158 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
159 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
160 [RTL_GIGA_MAC_VER_09] = {"RTL8102e" },
161 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
162 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
163 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
164 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" },
165 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" },
166 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" },
167 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
168 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
169 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
170 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
171 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
172 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
173 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
174 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
175 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
176 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
177 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
178 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
179 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
180 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
181 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
182 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
183 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
184 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
185 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
186 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
187 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
188 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
189 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
190 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
191 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
192 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
193 [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g", FIRMWARE_8168G_3},
194 [RTL_GIGA_MAC_VER_43] = {"RTL8106e", FIRMWARE_8106E_2},
195 [RTL_GIGA_MAC_VER_44] = {"RTL8411", FIRMWARE_8411_2 },
196 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
197 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
198 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
199 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
200 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
201 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
202 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
203 };
204
205 static const struct pci_device_id rtl8169_pci_tbl[] = {
206 { PCI_VDEVICE(REALTEK, 0x2502) },
207 { PCI_VDEVICE(REALTEK, 0x2600) },
208 { PCI_VDEVICE(REALTEK, 0x8129) },
209 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
210 { PCI_VDEVICE(REALTEK, 0x8161) },
211 { PCI_VDEVICE(REALTEK, 0x8167) },
212 { PCI_VDEVICE(REALTEK, 0x8168) },
213 { PCI_VDEVICE(NCUBE, 0x8168) },
214 { PCI_VDEVICE(REALTEK, 0x8169) },
215 { PCI_VENDOR_ID_DLINK, 0x4300,
216 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
217 { PCI_VDEVICE(DLINK, 0x4300) },
218 { PCI_VDEVICE(DLINK, 0x4302) },
219 { PCI_VDEVICE(AT, 0xc107) },
220 { PCI_VDEVICE(USR, 0x0116) },
221 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
222 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
223 {}
224 };
225
226 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
227
228 static struct {
229 u32 msg_enable;
230 } debug = { -1 };
231
232 enum rtl_registers {
233 MAC0 = 0, /* Ethernet hardware address. */
234 MAC4 = 4,
235 MAR0 = 8, /* Multicast filter. */
236 CounterAddrLow = 0x10,
237 CounterAddrHigh = 0x14,
238 TxDescStartAddrLow = 0x20,
239 TxDescStartAddrHigh = 0x24,
240 TxHDescStartAddrLow = 0x28,
241 TxHDescStartAddrHigh = 0x2c,
242 FLASH = 0x30,
243 ERSR = 0x36,
244 ChipCmd = 0x37,
245 TxPoll = 0x38,
246 IntrMask = 0x3c,
247 IntrStatus = 0x3e,
248
249 TxConfig = 0x40,
250 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
251 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
252
253 RxConfig = 0x44,
254 #define RX128_INT_EN (1 << 15) /* 8111c and later */
255 #define RX_MULTI_EN (1 << 14) /* 8111c only */
256 #define RXCFG_FIFO_SHIFT 13
257 /* No threshold before first PCI xfer */
258 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
259 #define RX_EARLY_OFF (1 << 11)
260 #define RXCFG_DMA_SHIFT 8
261 /* Unlimited maximum PCI burst. */
262 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
263
264 RxMissed = 0x4c,
265 Cfg9346 = 0x50,
266 Config0 = 0x51,
267 Config1 = 0x52,
268 Config2 = 0x53,
269 #define PME_SIGNAL (1 << 5) /* 8168c and later */
270
271 Config3 = 0x54,
272 Config4 = 0x55,
273 Config5 = 0x56,
274 MultiIntr = 0x5c,
275 PHYAR = 0x60,
276 PHYstatus = 0x6c,
277 RxMaxSize = 0xda,
278 CPlusCmd = 0xe0,
279 IntrMitigate = 0xe2,
280
281 #define RTL_COALESCE_MASK 0x0f
282 #define RTL_COALESCE_SHIFT 4
283 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
284 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
285
286 RxDescAddrLow = 0xe4,
287 RxDescAddrHigh = 0xe8,
288 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
289
290 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
291
292 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
293
294 #define TxPacketMax (8064 >> 7)
295 #define EarlySize 0x27
296
297 FuncEvent = 0xf0,
298 FuncEventMask = 0xf4,
299 FuncPresetState = 0xf8,
300 IBCR0 = 0xf8,
301 IBCR2 = 0xf9,
302 IBIMR0 = 0xfa,
303 IBISR0 = 0xfb,
304 FuncForceEvent = 0xfc,
305 };
306
307 enum rtl8168_8101_registers {
308 CSIDR = 0x64,
309 CSIAR = 0x68,
310 #define CSIAR_FLAG 0x80000000
311 #define CSIAR_WRITE_CMD 0x80000000
312 #define CSIAR_BYTE_ENABLE 0x0000f000
313 #define CSIAR_ADDR_MASK 0x00000fff
314 PMCH = 0x6f,
315 EPHYAR = 0x80,
316 #define EPHYAR_FLAG 0x80000000
317 #define EPHYAR_WRITE_CMD 0x80000000
318 #define EPHYAR_REG_MASK 0x1f
319 #define EPHYAR_REG_SHIFT 16
320 #define EPHYAR_DATA_MASK 0xffff
321 DLLPR = 0xd0,
322 #define PFM_EN (1 << 6)
323 #define TX_10M_PS_EN (1 << 7)
324 DBG_REG = 0xd1,
325 #define FIX_NAK_1 (1 << 4)
326 #define FIX_NAK_2 (1 << 3)
327 TWSI = 0xd2,
328 MCU = 0xd3,
329 #define NOW_IS_OOB (1 << 7)
330 #define TX_EMPTY (1 << 5)
331 #define RX_EMPTY (1 << 4)
332 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
333 #define EN_NDP (1 << 3)
334 #define EN_OOB_RESET (1 << 2)
335 #define LINK_LIST_RDY (1 << 1)
336 EFUSEAR = 0xdc,
337 #define EFUSEAR_FLAG 0x80000000
338 #define EFUSEAR_WRITE_CMD 0x80000000
339 #define EFUSEAR_READ_CMD 0x00000000
340 #define EFUSEAR_REG_MASK 0x03ff
341 #define EFUSEAR_REG_SHIFT 8
342 #define EFUSEAR_DATA_MASK 0xff
343 MISC_1 = 0xf2,
344 #define PFM_D3COLD_EN (1 << 6)
345 };
346
347 enum rtl8168_registers {
348 LED_FREQ = 0x1a,
349 EEE_LED = 0x1b,
350 ERIDR = 0x70,
351 ERIAR = 0x74,
352 #define ERIAR_FLAG 0x80000000
353 #define ERIAR_WRITE_CMD 0x80000000
354 #define ERIAR_READ_CMD 0x00000000
355 #define ERIAR_ADDR_BYTE_ALIGN 4
356 #define ERIAR_TYPE_SHIFT 16
357 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
358 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
359 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
360 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
361 #define ERIAR_MASK_SHIFT 12
362 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
363 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
364 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
365 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
366 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
367 EPHY_RXER_NUM = 0x7c,
368 OCPDR = 0xb0, /* OCP GPHY access */
369 #define OCPDR_WRITE_CMD 0x80000000
370 #define OCPDR_READ_CMD 0x00000000
371 #define OCPDR_REG_MASK 0x7f
372 #define OCPDR_GPHY_REG_SHIFT 16
373 #define OCPDR_DATA_MASK 0xffff
374 OCPAR = 0xb4,
375 #define OCPAR_FLAG 0x80000000
376 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
377 #define OCPAR_GPHY_READ_CMD 0x0000f060
378 GPHY_OCP = 0xb8,
379 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
380 MISC = 0xf0, /* 8168e only. */
381 #define TXPLA_RST (1 << 29)
382 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
383 #define PWM_EN (1 << 22)
384 #define RXDV_GATED_EN (1 << 19)
385 #define EARLY_TALLY_EN (1 << 16)
386 };
387
388 enum rtl_register_content {
389 /* InterruptStatusBits */
390 SYSErr = 0x8000,
391 PCSTimeout = 0x4000,
392 SWInt = 0x0100,
393 TxDescUnavail = 0x0080,
394 RxFIFOOver = 0x0040,
395 LinkChg = 0x0020,
396 RxOverflow = 0x0010,
397 TxErr = 0x0008,
398 TxOK = 0x0004,
399 RxErr = 0x0002,
400 RxOK = 0x0001,
401
402 /* RxStatusDesc */
403 RxRWT = (1 << 22),
404 RxRES = (1 << 21),
405 RxRUNT = (1 << 20),
406 RxCRC = (1 << 19),
407
408 /* ChipCmdBits */
409 StopReq = 0x80,
410 CmdReset = 0x10,
411 CmdRxEnb = 0x08,
412 CmdTxEnb = 0x04,
413 RxBufEmpty = 0x01,
414
415 /* TXPoll register p.5 */
416 HPQ = 0x80, /* Poll cmd on the high prio queue */
417 NPQ = 0x40, /* Poll cmd on the low prio queue */
418 FSWInt = 0x01, /* Forced software interrupt */
419
420 /* Cfg9346Bits */
421 Cfg9346_Lock = 0x00,
422 Cfg9346_Unlock = 0xc0,
423
424 /* rx_mode_bits */
425 AcceptErr = 0x20,
426 AcceptRunt = 0x10,
427 AcceptBroadcast = 0x08,
428 AcceptMulticast = 0x04,
429 AcceptMyPhys = 0x02,
430 AcceptAllPhys = 0x01,
431 #define RX_CONFIG_ACCEPT_MASK 0x3f
432
433 /* TxConfigBits */
434 TxInterFrameGapShift = 24,
435 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
436
437 /* Config1 register p.24 */
438 LEDS1 = (1 << 7),
439 LEDS0 = (1 << 6),
440 Speed_down = (1 << 4),
441 MEMMAP = (1 << 3),
442 IOMAP = (1 << 2),
443 VPD = (1 << 1),
444 PMEnable = (1 << 0), /* Power Management Enable */
445
446 /* Config2 register p. 25 */
447 ClkReqEn = (1 << 7), /* Clock Request Enable */
448 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
449 PCI_Clock_66MHz = 0x01,
450 PCI_Clock_33MHz = 0x00,
451
452 /* Config3 register p.25 */
453 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
454 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
455 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
456 Rdy_to_L23 = (1 << 1), /* L23 Enable */
457 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
458
459 /* Config4 register */
460 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
461
462 /* Config5 register p.27 */
463 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
464 MWF = (1 << 5), /* Accept Multicast wakeup frame */
465 UWF = (1 << 4), /* Accept Unicast wakeup frame */
466 Spi_en = (1 << 3),
467 LanWake = (1 << 1), /* LanWake enable/disable */
468 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
469 ASPM_en = (1 << 0), /* ASPM enable */
470
471 /* CPlusCmd p.31 */
472 EnableBist = (1 << 15), // 8168 8101
473 Mac_dbgo_oe = (1 << 14), // 8168 8101
474 Normal_mode = (1 << 13), // unused
475 Force_half_dup = (1 << 12), // 8168 8101
476 Force_rxflow_en = (1 << 11), // 8168 8101
477 Force_txflow_en = (1 << 10), // 8168 8101
478 Cxpl_dbg_sel = (1 << 9), // 8168 8101
479 ASF = (1 << 8), // 8168 8101
480 PktCntrDisable = (1 << 7), // 8168 8101
481 Mac_dbgo_sel = 0x001c, // 8168
482 RxVlan = (1 << 6),
483 RxChkSum = (1 << 5),
484 PCIDAC = (1 << 4),
485 PCIMulRW = (1 << 3),
486 #define INTT_MASK GENMASK(1, 0)
487 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
488
489 /* rtl8169_PHYstatus */
490 TBI_Enable = 0x80,
491 TxFlowCtrl = 0x40,
492 RxFlowCtrl = 0x20,
493 _1000bpsF = 0x10,
494 _100bps = 0x08,
495 _10bps = 0x04,
496 LinkStatus = 0x02,
497 FullDup = 0x01,
498
499 /* ResetCounterCommand */
500 CounterReset = 0x1,
501
502 /* DumpCounterCommand */
503 CounterDump = 0x8,
504
505 /* magic enable v2 */
506 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
507 };
508
509 enum rtl_desc_bit {
510 /* First doubleword. */
511 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
512 RingEnd = (1 << 30), /* End of descriptor ring */
513 FirstFrag = (1 << 29), /* First segment of a packet */
514 LastFrag = (1 << 28), /* Final segment of a packet */
515 };
516
517 /* Generic case. */
518 enum rtl_tx_desc_bit {
519 /* First doubleword. */
520 TD_LSO = (1 << 27), /* Large Send Offload */
521 #define TD_MSS_MAX 0x07ffu /* MSS value */
522
523 /* Second doubleword. */
524 TxVlanTag = (1 << 17), /* Add VLAN tag */
525 };
526
527 /* 8169, 8168b and 810x except 8102e. */
528 enum rtl_tx_desc_bit_0 {
529 /* First doubleword. */
530 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
531 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
532 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
533 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
534 };
535
536 /* 8102e, 8168c and beyond. */
537 enum rtl_tx_desc_bit_1 {
538 /* First doubleword. */
539 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
540 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
541 #define GTTCPHO_SHIFT 18
542 #define GTTCPHO_MAX 0x7fU
543
544 /* Second doubleword. */
545 #define TCPHO_SHIFT 18
546 #define TCPHO_MAX 0x3ffU
547 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
548 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
549 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
550 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
551 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
552 };
553
554 enum rtl_rx_desc_bit {
555 /* Rx private */
556 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
557 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
558
559 #define RxProtoUDP (PID1)
560 #define RxProtoTCP (PID0)
561 #define RxProtoIP (PID1 | PID0)
562 #define RxProtoMask RxProtoIP
563
564 IPFail = (1 << 16), /* IP checksum failed */
565 UDPFail = (1 << 15), /* UDP/IP checksum failed */
566 TCPFail = (1 << 14), /* TCP/IP checksum failed */
567 RxVlanTag = (1 << 16), /* VLAN tag available */
568 };
569
570 #define RsvdMask 0x3fffc000
571
572 struct TxDesc {
573 __le32 opts1;
574 __le32 opts2;
575 __le64 addr;
576 };
577
578 struct RxDesc {
579 __le32 opts1;
580 __le32 opts2;
581 __le64 addr;
582 };
583
584 struct ring_info {
585 struct sk_buff *skb;
586 u32 len;
587 };
588
589 struct rtl8169_counters {
590 __le64 tx_packets;
591 __le64 rx_packets;
592 __le64 tx_errors;
593 __le32 rx_errors;
594 __le16 rx_missed;
595 __le16 align_errors;
596 __le32 tx_one_collision;
597 __le32 tx_multi_collision;
598 __le64 rx_unicast;
599 __le64 rx_broadcast;
600 __le32 rx_multicast;
601 __le16 tx_aborted;
602 __le16 tx_underun;
603 };
604
605 struct rtl8169_tc_offsets {
606 bool inited;
607 __le64 tx_errors;
608 __le32 tx_multi_collision;
609 __le16 tx_aborted;
610 };
611
612 enum rtl_flag {
613 RTL_FLAG_TASK_ENABLED = 0,
614 RTL_FLAG_TASK_RESET_PENDING,
615 RTL_FLAG_MAX
616 };
617
618 struct rtl8169_stats {
619 u64 packets;
620 u64 bytes;
621 struct u64_stats_sync syncp;
622 };
623
624 struct rtl8169_private {
625 void __iomem *mmio_addr; /* memory map physical address */
626 struct pci_dev *pci_dev;
627 struct net_device *dev;
628 struct phy_device *phydev;
629 struct napi_struct napi;
630 u32 msg_enable;
631 enum mac_version mac_version;
632 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
633 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
634 u32 dirty_tx;
635 struct rtl8169_stats rx_stats;
636 struct rtl8169_stats tx_stats;
637 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
638 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
639 dma_addr_t TxPhyAddr;
640 dma_addr_t RxPhyAddr;
641 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
642 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
643 u16 cp_cmd;
644 u16 irq_mask;
645 struct clk *clk;
646
647 struct {
648 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
649 struct mutex mutex;
650 struct work_struct work;
651 } wk;
652
653 unsigned irq_enabled:1;
654 unsigned supports_gmii:1;
655 dma_addr_t counters_phys_addr;
656 struct rtl8169_counters *counters;
657 struct rtl8169_tc_offsets tc_offset;
658 u32 saved_wolopts;
659
660 const char *fw_name;
661 struct rtl_fw *rtl_fw;
662
663 u32 ocp_base;
664 };
665
666 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
667
668 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
669 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
670 module_param_named(debug, debug.msg_enable, int, 0);
671 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
672 MODULE_SOFTDEP("pre: realtek");
673 MODULE_LICENSE("GPL");
674 MODULE_FIRMWARE(FIRMWARE_8168D_1);
675 MODULE_FIRMWARE(FIRMWARE_8168D_2);
676 MODULE_FIRMWARE(FIRMWARE_8168E_1);
677 MODULE_FIRMWARE(FIRMWARE_8168E_2);
678 MODULE_FIRMWARE(FIRMWARE_8168E_3);
679 MODULE_FIRMWARE(FIRMWARE_8105E_1);
680 MODULE_FIRMWARE(FIRMWARE_8168F_1);
681 MODULE_FIRMWARE(FIRMWARE_8168F_2);
682 MODULE_FIRMWARE(FIRMWARE_8402_1);
683 MODULE_FIRMWARE(FIRMWARE_8411_1);
684 MODULE_FIRMWARE(FIRMWARE_8411_2);
685 MODULE_FIRMWARE(FIRMWARE_8106E_1);
686 MODULE_FIRMWARE(FIRMWARE_8106E_2);
687 MODULE_FIRMWARE(FIRMWARE_8168G_2);
688 MODULE_FIRMWARE(FIRMWARE_8168G_3);
689 MODULE_FIRMWARE(FIRMWARE_8168H_1);
690 MODULE_FIRMWARE(FIRMWARE_8168H_2);
691 MODULE_FIRMWARE(FIRMWARE_8107E_1);
692 MODULE_FIRMWARE(FIRMWARE_8107E_2);
693
694 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
695 {
696 return &tp->pci_dev->dev;
697 }
698
699 static void rtl_lock_work(struct rtl8169_private *tp)
700 {
701 mutex_lock(&tp->wk.mutex);
702 }
703
704 static void rtl_unlock_work(struct rtl8169_private *tp)
705 {
706 mutex_unlock(&tp->wk.mutex);
707 }
708
709 static void rtl_lock_config_regs(struct rtl8169_private *tp)
710 {
711 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
712 }
713
714 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
715 {
716 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
717 }
718
719 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
720 {
721 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
722 PCI_EXP_DEVCTL_READRQ, force);
723 }
724
725 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
726 {
727 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
728 tp->mac_version != RTL_GIGA_MAC_VER_39;
729 }
730
731 struct rtl_cond {
732 bool (*check)(struct rtl8169_private *);
733 const char *msg;
734 };
735
736 static void rtl_udelay(unsigned int d)
737 {
738 udelay(d);
739 }
740
741 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
742 void (*delay)(unsigned int), unsigned int d, int n,
743 bool high)
744 {
745 int i;
746
747 for (i = 0; i < n; i++) {
748 if (c->check(tp) == high)
749 return true;
750 delay(d);
751 }
752 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
753 c->msg, !high, n, d);
754 return false;
755 }
756
757 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
758 const struct rtl_cond *c,
759 unsigned int d, int n)
760 {
761 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
762 }
763
764 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
765 const struct rtl_cond *c,
766 unsigned int d, int n)
767 {
768 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
769 }
770
771 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
772 const struct rtl_cond *c,
773 unsigned int d, int n)
774 {
775 return rtl_loop_wait(tp, c, msleep, d, n, true);
776 }
777
778 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
779 const struct rtl_cond *c,
780 unsigned int d, int n)
781 {
782 return rtl_loop_wait(tp, c, msleep, d, n, false);
783 }
784
785 #define DECLARE_RTL_COND(name) \
786 static bool name ## _check(struct rtl8169_private *); \
787 \
788 static const struct rtl_cond name = { \
789 .check = name ## _check, \
790 .msg = #name \
791 }; \
792 \
793 static bool name ## _check(struct rtl8169_private *tp)
794
795 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
796 {
797 if (reg & 0xffff0001) {
798 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
799 return true;
800 }
801 return false;
802 }
803
804 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
805 {
806 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
807 }
808
809 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
810 {
811 if (rtl_ocp_reg_failure(tp, reg))
812 return;
813
814 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
815
816 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
817 }
818
819 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
820 {
821 if (rtl_ocp_reg_failure(tp, reg))
822 return 0;
823
824 RTL_W32(tp, GPHY_OCP, reg << 15);
825
826 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
827 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
828 }
829
830 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
831 {
832 if (rtl_ocp_reg_failure(tp, reg))
833 return;
834
835 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
836 }
837
838 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
839 {
840 if (rtl_ocp_reg_failure(tp, reg))
841 return 0;
842
843 RTL_W32(tp, OCPDR, reg << 15);
844
845 return RTL_R32(tp, OCPDR);
846 }
847
848 #define OCP_STD_PHY_BASE 0xa400
849
850 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
851 {
852 if (reg == 0x1f) {
853 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
854 return;
855 }
856
857 if (tp->ocp_base != OCP_STD_PHY_BASE)
858 reg -= 0x10;
859
860 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
861 }
862
863 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
864 {
865 if (tp->ocp_base != OCP_STD_PHY_BASE)
866 reg -= 0x10;
867
868 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
869 }
870
871 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
872 {
873 if (reg == 0x1f) {
874 tp->ocp_base = value << 4;
875 return;
876 }
877
878 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
879 }
880
881 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
882 {
883 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
884 }
885
886 DECLARE_RTL_COND(rtl_phyar_cond)
887 {
888 return RTL_R32(tp, PHYAR) & 0x80000000;
889 }
890
891 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
892 {
893 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
894
895 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
896 /*
897 * According to hardware specs a 20us delay is required after write
898 * complete indication, but before sending next command.
899 */
900 udelay(20);
901 }
902
903 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
904 {
905 int value;
906
907 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
908
909 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
910 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
911
912 /*
913 * According to hardware specs a 20us delay is required after read
914 * complete indication, but before sending next command.
915 */
916 udelay(20);
917
918 return value;
919 }
920
921 DECLARE_RTL_COND(rtl_ocpar_cond)
922 {
923 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
924 }
925
926 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
927 {
928 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
929 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
930 RTL_W32(tp, EPHY_RXER_NUM, 0);
931
932 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
933 }
934
935 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
936 {
937 r8168dp_1_mdio_access(tp, reg,
938 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
939 }
940
941 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
942 {
943 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
944
945 mdelay(1);
946 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
947 RTL_W32(tp, EPHY_RXER_NUM, 0);
948
949 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
950 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
951 }
952
953 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
954
955 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
956 {
957 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
958 }
959
960 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
961 {
962 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
963 }
964
965 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
966 {
967 r8168dp_2_mdio_start(tp);
968
969 r8169_mdio_write(tp, reg, value);
970
971 r8168dp_2_mdio_stop(tp);
972 }
973
974 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
975 {
976 int value;
977
978 r8168dp_2_mdio_start(tp);
979
980 value = r8169_mdio_read(tp, reg);
981
982 r8168dp_2_mdio_stop(tp);
983
984 return value;
985 }
986
987 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
988 {
989 switch (tp->mac_version) {
990 case RTL_GIGA_MAC_VER_27:
991 r8168dp_1_mdio_write(tp, location, val);
992 break;
993 case RTL_GIGA_MAC_VER_28:
994 case RTL_GIGA_MAC_VER_31:
995 r8168dp_2_mdio_write(tp, location, val);
996 break;
997 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
998 r8168g_mdio_write(tp, location, val);
999 break;
1000 default:
1001 r8169_mdio_write(tp, location, val);
1002 break;
1003 }
1004 }
1005
1006 static int rtl_readphy(struct rtl8169_private *tp, int location)
1007 {
1008 switch (tp->mac_version) {
1009 case RTL_GIGA_MAC_VER_27:
1010 return r8168dp_1_mdio_read(tp, location);
1011 case RTL_GIGA_MAC_VER_28:
1012 case RTL_GIGA_MAC_VER_31:
1013 return r8168dp_2_mdio_read(tp, location);
1014 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1015 return r8168g_mdio_read(tp, location);
1016 default:
1017 return r8169_mdio_read(tp, location);
1018 }
1019 }
1020
1021 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1022 {
1023 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1024 }
1025
1026 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1027 {
1028 int val;
1029
1030 val = rtl_readphy(tp, reg_addr);
1031 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1032 }
1033
1034 DECLARE_RTL_COND(rtl_ephyar_cond)
1035 {
1036 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1037 }
1038
1039 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1040 {
1041 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1042 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1043
1044 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1045
1046 udelay(10);
1047 }
1048
1049 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1050 {
1051 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1052
1053 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1054 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1055 }
1056
1057 DECLARE_RTL_COND(rtl_eriar_cond)
1058 {
1059 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1060 }
1061
1062 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1063 u32 val, int type)
1064 {
1065 BUG_ON((addr & 3) || (mask == 0));
1066 RTL_W32(tp, ERIDR, val);
1067 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1068
1069 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1070 }
1071
1072 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1073 u32 val)
1074 {
1075 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1076 }
1077
1078 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1079 {
1080 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1081
1082 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1083 RTL_R32(tp, ERIDR) : ~0;
1084 }
1085
1086 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1087 {
1088 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1089 }
1090
1091 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1092 u32 m)
1093 {
1094 u32 val;
1095
1096 val = rtl_eri_read(tp, addr);
1097 rtl_eri_write(tp, addr, mask, (val & ~m) | p);
1098 }
1099
1100 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,
1101 u32 p)
1102 {
1103 rtl_w0w1_eri(tp, addr, mask, p, 0);
1104 }
1105
1106 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
1107 u32 m)
1108 {
1109 rtl_w0w1_eri(tp, addr, mask, 0, m);
1110 }
1111
1112 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1113 {
1114 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1115 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1116 RTL_R32(tp, OCPDR) : ~0;
1117 }
1118
1119 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1120 {
1121 return _rtl_eri_read(tp, reg, ERIAR_OOB);
1122 }
1123
1124 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1125 u32 data)
1126 {
1127 RTL_W32(tp, OCPDR, data);
1128 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1129 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1130 }
1131
1132 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1133 u32 data)
1134 {
1135 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1136 data, ERIAR_OOB);
1137 }
1138
1139 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1140 {
1141 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1142
1143 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1144 }
1145
1146 #define OOB_CMD_RESET 0x00
1147 #define OOB_CMD_DRIVER_START 0x05
1148 #define OOB_CMD_DRIVER_STOP 0x06
1149
1150 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1151 {
1152 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1153 }
1154
1155 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1156 {
1157 u16 reg;
1158
1159 reg = rtl8168_get_ocp_reg(tp);
1160
1161 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1162 }
1163
1164 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1165 {
1166 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1167 }
1168
1169 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1170 {
1171 return RTL_R8(tp, IBISR0) & 0x20;
1172 }
1173
1174 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1175 {
1176 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1177 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1178 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1179 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1180 }
1181
1182 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1183 {
1184 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1185 rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1186 }
1187
1188 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1189 {
1190 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1191 r8168ep_ocp_write(tp, 0x01, 0x30,
1192 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1193 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1194 }
1195
1196 static void rtl8168_driver_start(struct rtl8169_private *tp)
1197 {
1198 switch (tp->mac_version) {
1199 case RTL_GIGA_MAC_VER_27:
1200 case RTL_GIGA_MAC_VER_28:
1201 case RTL_GIGA_MAC_VER_31:
1202 rtl8168dp_driver_start(tp);
1203 break;
1204 case RTL_GIGA_MAC_VER_49:
1205 case RTL_GIGA_MAC_VER_50:
1206 case RTL_GIGA_MAC_VER_51:
1207 rtl8168ep_driver_start(tp);
1208 break;
1209 default:
1210 BUG();
1211 break;
1212 }
1213 }
1214
1215 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1216 {
1217 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1218 rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1219 }
1220
1221 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1222 {
1223 rtl8168ep_stop_cmac(tp);
1224 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1225 r8168ep_ocp_write(tp, 0x01, 0x30,
1226 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1227 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1228 }
1229
1230 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1231 {
1232 switch (tp->mac_version) {
1233 case RTL_GIGA_MAC_VER_27:
1234 case RTL_GIGA_MAC_VER_28:
1235 case RTL_GIGA_MAC_VER_31:
1236 rtl8168dp_driver_stop(tp);
1237 break;
1238 case RTL_GIGA_MAC_VER_49:
1239 case RTL_GIGA_MAC_VER_50:
1240 case RTL_GIGA_MAC_VER_51:
1241 rtl8168ep_driver_stop(tp);
1242 break;
1243 default:
1244 BUG();
1245 break;
1246 }
1247 }
1248
1249 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1250 {
1251 u16 reg = rtl8168_get_ocp_reg(tp);
1252
1253 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1254 }
1255
1256 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1257 {
1258 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1259 }
1260
1261 static bool r8168_check_dash(struct rtl8169_private *tp)
1262 {
1263 switch (tp->mac_version) {
1264 case RTL_GIGA_MAC_VER_27:
1265 case RTL_GIGA_MAC_VER_28:
1266 case RTL_GIGA_MAC_VER_31:
1267 return r8168dp_check_dash(tp);
1268 case RTL_GIGA_MAC_VER_49:
1269 case RTL_GIGA_MAC_VER_50:
1270 case RTL_GIGA_MAC_VER_51:
1271 return r8168ep_check_dash(tp);
1272 default:
1273 return false;
1274 }
1275 }
1276
1277 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1278 {
1279 rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1280 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1281 }
1282
1283 DECLARE_RTL_COND(rtl_efusear_cond)
1284 {
1285 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1286 }
1287
1288 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1289 {
1290 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1291
1292 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1293 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1294 }
1295
1296 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1297 {
1298 RTL_W16(tp, IntrStatus, bits);
1299 }
1300
1301 static void rtl_irq_disable(struct rtl8169_private *tp)
1302 {
1303 RTL_W16(tp, IntrMask, 0);
1304 tp->irq_enabled = 0;
1305 }
1306
1307 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1308 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1309 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1310
1311 static void rtl_irq_enable(struct rtl8169_private *tp)
1312 {
1313 tp->irq_enabled = 1;
1314 RTL_W16(tp, IntrMask, tp->irq_mask);
1315 }
1316
1317 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1318 {
1319 rtl_irq_disable(tp);
1320 rtl_ack_events(tp, 0xffff);
1321 /* PCI commit */
1322 RTL_R8(tp, ChipCmd);
1323 }
1324
1325 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1326 {
1327 struct net_device *dev = tp->dev;
1328 struct phy_device *phydev = tp->phydev;
1329
1330 if (!netif_running(dev))
1331 return;
1332
1333 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1334 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1335 if (phydev->speed == SPEED_1000) {
1336 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1337 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1338 } else if (phydev->speed == SPEED_100) {
1339 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1340 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1341 } else {
1342 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1343 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1344 }
1345 rtl_reset_packet_filter(tp);
1346 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1347 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1348 if (phydev->speed == SPEED_1000) {
1349 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1350 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1351 } else {
1352 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1353 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1354 }
1355 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1356 if (phydev->speed == SPEED_10) {
1357 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1358 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1359 } else {
1360 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1361 }
1362 }
1363 }
1364
1365 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1366
1367 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1368 {
1369 struct rtl8169_private *tp = netdev_priv(dev);
1370
1371 rtl_lock_work(tp);
1372 wol->supported = WAKE_ANY;
1373 wol->wolopts = tp->saved_wolopts;
1374 rtl_unlock_work(tp);
1375 }
1376
1377 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1378 {
1379 unsigned int i, tmp;
1380 static const struct {
1381 u32 opt;
1382 u16 reg;
1383 u8 mask;
1384 } cfg[] = {
1385 { WAKE_PHY, Config3, LinkUp },
1386 { WAKE_UCAST, Config5, UWF },
1387 { WAKE_BCAST, Config5, BWF },
1388 { WAKE_MCAST, Config5, MWF },
1389 { WAKE_ANY, Config5, LanWake },
1390 { WAKE_MAGIC, Config3, MagicPacket }
1391 };
1392 u8 options;
1393
1394 rtl_unlock_config_regs(tp);
1395
1396 if (rtl_is_8168evl_up(tp)) {
1397 tmp = ARRAY_SIZE(cfg) - 1;
1398 if (wolopts & WAKE_MAGIC)
1399 rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
1400 MagicPacket_v2);
1401 else
1402 rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
1403 MagicPacket_v2);
1404 } else {
1405 tmp = ARRAY_SIZE(cfg);
1406 }
1407
1408 for (i = 0; i < tmp; i++) {
1409 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1410 if (wolopts & cfg[i].opt)
1411 options |= cfg[i].mask;
1412 RTL_W8(tp, cfg[i].reg, options);
1413 }
1414
1415 switch (tp->mac_version) {
1416 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_17:
1417 options = RTL_R8(tp, Config1) & ~PMEnable;
1418 if (wolopts)
1419 options |= PMEnable;
1420 RTL_W8(tp, Config1, options);
1421 break;
1422 default:
1423 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1424 if (wolopts)
1425 options |= PME_SIGNAL;
1426 RTL_W8(tp, Config2, options);
1427 break;
1428 }
1429
1430 rtl_lock_config_regs(tp);
1431
1432 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1433 }
1434
1435 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1436 {
1437 struct rtl8169_private *tp = netdev_priv(dev);
1438 struct device *d = tp_to_dev(tp);
1439
1440 if (wol->wolopts & ~WAKE_ANY)
1441 return -EINVAL;
1442
1443 pm_runtime_get_noresume(d);
1444
1445 rtl_lock_work(tp);
1446
1447 tp->saved_wolopts = wol->wolopts;
1448
1449 if (pm_runtime_active(d))
1450 __rtl8169_set_wol(tp, tp->saved_wolopts);
1451
1452 rtl_unlock_work(tp);
1453
1454 pm_runtime_put_noidle(d);
1455
1456 return 0;
1457 }
1458
1459 static void rtl8169_get_drvinfo(struct net_device *dev,
1460 struct ethtool_drvinfo *info)
1461 {
1462 struct rtl8169_private *tp = netdev_priv(dev);
1463 struct rtl_fw *rtl_fw = tp->rtl_fw;
1464
1465 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1466 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1467 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1468 if (rtl_fw)
1469 strlcpy(info->fw_version, rtl_fw->version,
1470 sizeof(info->fw_version));
1471 }
1472
1473 static int rtl8169_get_regs_len(struct net_device *dev)
1474 {
1475 return R8169_REGS_SIZE;
1476 }
1477
1478 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1479 netdev_features_t features)
1480 {
1481 struct rtl8169_private *tp = netdev_priv(dev);
1482
1483 if (dev->mtu > TD_MSS_MAX)
1484 features &= ~NETIF_F_ALL_TSO;
1485
1486 if (dev->mtu > JUMBO_1K &&
1487 tp->mac_version > RTL_GIGA_MAC_VER_06)
1488 features &= ~NETIF_F_IP_CSUM;
1489
1490 return features;
1491 }
1492
1493 static int rtl8169_set_features(struct net_device *dev,
1494 netdev_features_t features)
1495 {
1496 struct rtl8169_private *tp = netdev_priv(dev);
1497 u32 rx_config;
1498
1499 rtl_lock_work(tp);
1500
1501 rx_config = RTL_R32(tp, RxConfig);
1502 if (features & NETIF_F_RXALL)
1503 rx_config |= (AcceptErr | AcceptRunt);
1504 else
1505 rx_config &= ~(AcceptErr | AcceptRunt);
1506
1507 RTL_W32(tp, RxConfig, rx_config);
1508
1509 if (features & NETIF_F_RXCSUM)
1510 tp->cp_cmd |= RxChkSum;
1511 else
1512 tp->cp_cmd &= ~RxChkSum;
1513
1514 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1515 tp->cp_cmd |= RxVlan;
1516 else
1517 tp->cp_cmd &= ~RxVlan;
1518
1519 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1520 RTL_R16(tp, CPlusCmd);
1521
1522 rtl_unlock_work(tp);
1523
1524 return 0;
1525 }
1526
1527 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1528 {
1529 return (skb_vlan_tag_present(skb)) ?
1530 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1531 }
1532
1533 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1534 {
1535 u32 opts2 = le32_to_cpu(desc->opts2);
1536
1537 if (opts2 & RxVlanTag)
1538 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1539 }
1540
1541 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1542 void *p)
1543 {
1544 struct rtl8169_private *tp = netdev_priv(dev);
1545 u32 __iomem *data = tp->mmio_addr;
1546 u32 *dw = p;
1547 int i;
1548
1549 rtl_lock_work(tp);
1550 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1551 memcpy_fromio(dw++, data++, 4);
1552 rtl_unlock_work(tp);
1553 }
1554
1555 static u32 rtl8169_get_msglevel(struct net_device *dev)
1556 {
1557 struct rtl8169_private *tp = netdev_priv(dev);
1558
1559 return tp->msg_enable;
1560 }
1561
1562 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1563 {
1564 struct rtl8169_private *tp = netdev_priv(dev);
1565
1566 tp->msg_enable = value;
1567 }
1568
1569 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1570 "tx_packets",
1571 "rx_packets",
1572 "tx_errors",
1573 "rx_errors",
1574 "rx_missed",
1575 "align_errors",
1576 "tx_single_collisions",
1577 "tx_multi_collisions",
1578 "unicast",
1579 "broadcast",
1580 "multicast",
1581 "tx_aborted",
1582 "tx_underrun",
1583 };
1584
1585 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1586 {
1587 switch (sset) {
1588 case ETH_SS_STATS:
1589 return ARRAY_SIZE(rtl8169_gstrings);
1590 default:
1591 return -EOPNOTSUPP;
1592 }
1593 }
1594
1595 DECLARE_RTL_COND(rtl_counters_cond)
1596 {
1597 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1598 }
1599
1600 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1601 {
1602 dma_addr_t paddr = tp->counters_phys_addr;
1603 u32 cmd;
1604
1605 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1606 RTL_R32(tp, CounterAddrHigh);
1607 cmd = (u64)paddr & DMA_BIT_MASK(32);
1608 RTL_W32(tp, CounterAddrLow, cmd);
1609 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1610
1611 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1612 }
1613
1614 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1615 {
1616 /*
1617 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1618 * tally counters.
1619 */
1620 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1621 return true;
1622
1623 return rtl8169_do_counters(tp, CounterReset);
1624 }
1625
1626 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1627 {
1628 u8 val = RTL_R8(tp, ChipCmd);
1629
1630 /*
1631 * Some chips are unable to dump tally counters when the receiver
1632 * is disabled. If 0xff chip may be in a PCI power-save state.
1633 */
1634 if (!(val & CmdRxEnb) || val == 0xff)
1635 return true;
1636
1637 return rtl8169_do_counters(tp, CounterDump);
1638 }
1639
1640 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1641 {
1642 struct rtl8169_counters *counters = tp->counters;
1643 bool ret = false;
1644
1645 /*
1646 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1647 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1648 * reset by a power cycle, while the counter values collected by the
1649 * driver are reset at every driver unload/load cycle.
1650 *
1651 * To make sure the HW values returned by @get_stats64 match the SW
1652 * values, we collect the initial values at first open(*) and use them
1653 * as offsets to normalize the values returned by @get_stats64.
1654 *
1655 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1656 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1657 * set at open time by rtl_hw_start.
1658 */
1659
1660 if (tp->tc_offset.inited)
1661 return true;
1662
1663 /* If both, reset and update fail, propagate to caller. */
1664 if (rtl8169_reset_counters(tp))
1665 ret = true;
1666
1667 if (rtl8169_update_counters(tp))
1668 ret = true;
1669
1670 tp->tc_offset.tx_errors = counters->tx_errors;
1671 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1672 tp->tc_offset.tx_aborted = counters->tx_aborted;
1673 tp->tc_offset.inited = true;
1674
1675 return ret;
1676 }
1677
1678 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1679 struct ethtool_stats *stats, u64 *data)
1680 {
1681 struct rtl8169_private *tp = netdev_priv(dev);
1682 struct device *d = tp_to_dev(tp);
1683 struct rtl8169_counters *counters = tp->counters;
1684
1685 ASSERT_RTNL();
1686
1687 pm_runtime_get_noresume(d);
1688
1689 if (pm_runtime_active(d))
1690 rtl8169_update_counters(tp);
1691
1692 pm_runtime_put_noidle(d);
1693
1694 data[0] = le64_to_cpu(counters->tx_packets);
1695 data[1] = le64_to_cpu(counters->rx_packets);
1696 data[2] = le64_to_cpu(counters->tx_errors);
1697 data[3] = le32_to_cpu(counters->rx_errors);
1698 data[4] = le16_to_cpu(counters->rx_missed);
1699 data[5] = le16_to_cpu(counters->align_errors);
1700 data[6] = le32_to_cpu(counters->tx_one_collision);
1701 data[7] = le32_to_cpu(counters->tx_multi_collision);
1702 data[8] = le64_to_cpu(counters->rx_unicast);
1703 data[9] = le64_to_cpu(counters->rx_broadcast);
1704 data[10] = le32_to_cpu(counters->rx_multicast);
1705 data[11] = le16_to_cpu(counters->tx_aborted);
1706 data[12] = le16_to_cpu(counters->tx_underun);
1707 }
1708
1709 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1710 {
1711 switch(stringset) {
1712 case ETH_SS_STATS:
1713 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1714 break;
1715 }
1716 }
1717
1718 /*
1719 * Interrupt coalescing
1720 *
1721 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1722 * > 8169, 8168 and 810x line of chipsets
1723 *
1724 * 8169, 8168, and 8136(810x) serial chipsets support it.
1725 *
1726 * > 2 - the Tx timer unit at gigabit speed
1727 *
1728 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1729 * (0xe0) bit 1 and bit 0.
1730 *
1731 * For 8169
1732 * bit[1:0] \ speed 1000M 100M 10M
1733 * 0 0 320ns 2.56us 40.96us
1734 * 0 1 2.56us 20.48us 327.7us
1735 * 1 0 5.12us 40.96us 655.4us
1736 * 1 1 10.24us 81.92us 1.31ms
1737 *
1738 * For the other
1739 * bit[1:0] \ speed 1000M 100M 10M
1740 * 0 0 5us 2.56us 40.96us
1741 * 0 1 40us 20.48us 327.7us
1742 * 1 0 80us 40.96us 655.4us
1743 * 1 1 160us 81.92us 1.31ms
1744 */
1745
1746 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1747 struct rtl_coalesce_scale {
1748 /* Rx / Tx */
1749 u32 nsecs[2];
1750 };
1751
1752 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1753 struct rtl_coalesce_info {
1754 u32 speed;
1755 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
1756 };
1757
1758 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1759 #define rxtx_x1822(r, t) { \
1760 {{(r), (t)}}, \
1761 {{(r)*8, (t)*8}}, \
1762 {{(r)*8*2, (t)*8*2}}, \
1763 {{(r)*8*2*2, (t)*8*2*2}}, \
1764 }
1765 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1766 /* speed delays: rx00 tx00 */
1767 { SPEED_10, rxtx_x1822(40960, 40960) },
1768 { SPEED_100, rxtx_x1822( 2560, 2560) },
1769 { SPEED_1000, rxtx_x1822( 320, 320) },
1770 { 0 },
1771 };
1772
1773 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1774 /* speed delays: rx00 tx00 */
1775 { SPEED_10, rxtx_x1822(40960, 40960) },
1776 { SPEED_100, rxtx_x1822( 2560, 2560) },
1777 { SPEED_1000, rxtx_x1822( 5000, 5000) },
1778 { 0 },
1779 };
1780 #undef rxtx_x1822
1781
1782 /* get rx/tx scale vector corresponding to current speed */
1783 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1784 {
1785 struct rtl8169_private *tp = netdev_priv(dev);
1786 const struct rtl_coalesce_info *ci;
1787
1788 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1789 ci = rtl_coalesce_info_8169;
1790 else
1791 ci = rtl_coalesce_info_8168_8136;
1792
1793 for (; ci->speed; ci++) {
1794 if (tp->phydev->speed == ci->speed)
1795 return ci;
1796 }
1797
1798 return ERR_PTR(-ELNRNG);
1799 }
1800
1801 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1802 {
1803 struct rtl8169_private *tp = netdev_priv(dev);
1804 const struct rtl_coalesce_info *ci;
1805 const struct rtl_coalesce_scale *scale;
1806 struct {
1807 u32 *max_frames;
1808 u32 *usecs;
1809 } coal_settings [] = {
1810 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1811 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1812 }, *p = coal_settings;
1813 int i;
1814 u16 w;
1815
1816 memset(ec, 0, sizeof(*ec));
1817
1818 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1819 ci = rtl_coalesce_info(dev);
1820 if (IS_ERR(ci))
1821 return PTR_ERR(ci);
1822
1823 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1824
1825 /* read IntrMitigate and adjust according to scale */
1826 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1827 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1828 w >>= RTL_COALESCE_SHIFT;
1829 *p->usecs = w & RTL_COALESCE_MASK;
1830 }
1831
1832 for (i = 0; i < 2; i++) {
1833 p = coal_settings + i;
1834 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1835
1836 /*
1837 * ethtool_coalesce says it is illegal to set both usecs and
1838 * max_frames to 0.
1839 */
1840 if (!*p->usecs && !*p->max_frames)
1841 *p->max_frames = 1;
1842 }
1843
1844 return 0;
1845 }
1846
1847 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1848 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1849 struct net_device *dev, u32 nsec, u16 *cp01)
1850 {
1851 const struct rtl_coalesce_info *ci;
1852 u16 i;
1853
1854 ci = rtl_coalesce_info(dev);
1855 if (IS_ERR(ci))
1856 return ERR_CAST(ci);
1857
1858 for (i = 0; i < 4; i++) {
1859 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1860 ci->scalev[i].nsecs[1]);
1861 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1862 *cp01 = i;
1863 return &ci->scalev[i];
1864 }
1865 }
1866
1867 return ERR_PTR(-EINVAL);
1868 }
1869
1870 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1871 {
1872 struct rtl8169_private *tp = netdev_priv(dev);
1873 const struct rtl_coalesce_scale *scale;
1874 struct {
1875 u32 frames;
1876 u32 usecs;
1877 } coal_settings [] = {
1878 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1879 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1880 }, *p = coal_settings;
1881 u16 w = 0, cp01;
1882 int i;
1883
1884 scale = rtl_coalesce_choose_scale(dev,
1885 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1886 if (IS_ERR(scale))
1887 return PTR_ERR(scale);
1888
1889 for (i = 0; i < 2; i++, p++) {
1890 u32 units;
1891
1892 /*
1893 * accept max_frames=1 we returned in rtl_get_coalesce.
1894 * accept it not only when usecs=0 because of e.g. the following scenario:
1895 *
1896 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1897 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1898 * - then user does `ethtool -C eth0 rx-usecs 100`
1899 *
1900 * since ethtool sends to kernel whole ethtool_coalesce
1901 * settings, if we do not handle rx_usecs=!0, rx_frames=1
1902 * we'll reject it below in `frames % 4 != 0`.
1903 */
1904 if (p->frames == 1) {
1905 p->frames = 0;
1906 }
1907
1908 units = p->usecs * 1000 / scale->nsecs[i];
1909 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
1910 return -EINVAL;
1911
1912 w <<= RTL_COALESCE_SHIFT;
1913 w |= units;
1914 w <<= RTL_COALESCE_SHIFT;
1915 w |= p->frames >> 2;
1916 }
1917
1918 rtl_lock_work(tp);
1919
1920 RTL_W16(tp, IntrMitigate, swab16(w));
1921
1922 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1923 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1924 RTL_R16(tp, CPlusCmd);
1925
1926 rtl_unlock_work(tp);
1927
1928 return 0;
1929 }
1930
1931 static int rtl_get_eee_supp(struct rtl8169_private *tp)
1932 {
1933 struct phy_device *phydev = tp->phydev;
1934 int ret;
1935
1936 switch (tp->mac_version) {
1937 case RTL_GIGA_MAC_VER_34:
1938 case RTL_GIGA_MAC_VER_35:
1939 case RTL_GIGA_MAC_VER_36:
1940 case RTL_GIGA_MAC_VER_38:
1941 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1942 break;
1943 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1944 ret = phy_read_paged(phydev, 0x0a5c, 0x12);
1945 break;
1946 default:
1947 ret = -EPROTONOSUPPORT;
1948 break;
1949 }
1950
1951 return ret;
1952 }
1953
1954 static int rtl_get_eee_lpadv(struct rtl8169_private *tp)
1955 {
1956 struct phy_device *phydev = tp->phydev;
1957 int ret;
1958
1959 switch (tp->mac_version) {
1960 case RTL_GIGA_MAC_VER_34:
1961 case RTL_GIGA_MAC_VER_35:
1962 case RTL_GIGA_MAC_VER_36:
1963 case RTL_GIGA_MAC_VER_38:
1964 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
1965 break;
1966 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1967 ret = phy_read_paged(phydev, 0x0a5d, 0x11);
1968 break;
1969 default:
1970 ret = -EPROTONOSUPPORT;
1971 break;
1972 }
1973
1974 return ret;
1975 }
1976
1977 static int rtl_get_eee_adv(struct rtl8169_private *tp)
1978 {
1979 struct phy_device *phydev = tp->phydev;
1980 int ret;
1981
1982 switch (tp->mac_version) {
1983 case RTL_GIGA_MAC_VER_34:
1984 case RTL_GIGA_MAC_VER_35:
1985 case RTL_GIGA_MAC_VER_36:
1986 case RTL_GIGA_MAC_VER_38:
1987 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
1988 break;
1989 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1990 ret = phy_read_paged(phydev, 0x0a5d, 0x10);
1991 break;
1992 default:
1993 ret = -EPROTONOSUPPORT;
1994 break;
1995 }
1996
1997 return ret;
1998 }
1999
2000 static int rtl_set_eee_adv(struct rtl8169_private *tp, int val)
2001 {
2002 struct phy_device *phydev = tp->phydev;
2003 int ret = 0;
2004
2005 switch (tp->mac_version) {
2006 case RTL_GIGA_MAC_VER_34:
2007 case RTL_GIGA_MAC_VER_35:
2008 case RTL_GIGA_MAC_VER_36:
2009 case RTL_GIGA_MAC_VER_38:
2010 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
2011 break;
2012 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2013 phy_write_paged(phydev, 0x0a5d, 0x10, val);
2014 break;
2015 default:
2016 ret = -EPROTONOSUPPORT;
2017 break;
2018 }
2019
2020 return ret;
2021 }
2022
2023 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
2024 {
2025 struct rtl8169_private *tp = netdev_priv(dev);
2026 struct device *d = tp_to_dev(tp);
2027 int ret;
2028
2029 pm_runtime_get_noresume(d);
2030
2031 if (!pm_runtime_active(d)) {
2032 ret = -EOPNOTSUPP;
2033 goto out;
2034 }
2035
2036 /* Get Supported EEE */
2037 ret = rtl_get_eee_supp(tp);
2038 if (ret < 0)
2039 goto out;
2040 data->supported = mmd_eee_cap_to_ethtool_sup_t(ret);
2041
2042 /* Get advertisement EEE */
2043 ret = rtl_get_eee_adv(tp);
2044 if (ret < 0)
2045 goto out;
2046 data->advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2047 data->eee_enabled = !!data->advertised;
2048
2049 /* Get LP advertisement EEE */
2050 ret = rtl_get_eee_lpadv(tp);
2051 if (ret < 0)
2052 goto out;
2053 data->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2054 data->eee_active = !!(data->advertised & data->lp_advertised);
2055 out:
2056 pm_runtime_put_noidle(d);
2057 return ret < 0 ? ret : 0;
2058 }
2059
2060 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
2061 {
2062 struct rtl8169_private *tp = netdev_priv(dev);
2063 struct device *d = tp_to_dev(tp);
2064 int old_adv, adv = 0, cap, ret;
2065
2066 pm_runtime_get_noresume(d);
2067
2068 if (!dev->phydev || !pm_runtime_active(d)) {
2069 ret = -EOPNOTSUPP;
2070 goto out;
2071 }
2072
2073 if (dev->phydev->autoneg == AUTONEG_DISABLE ||
2074 dev->phydev->duplex != DUPLEX_FULL) {
2075 ret = -EPROTONOSUPPORT;
2076 goto out;
2077 }
2078
2079 /* Get Supported EEE */
2080 ret = rtl_get_eee_supp(tp);
2081 if (ret < 0)
2082 goto out;
2083 cap = ret;
2084
2085 ret = rtl_get_eee_adv(tp);
2086 if (ret < 0)
2087 goto out;
2088 old_adv = ret;
2089
2090 if (data->eee_enabled) {
2091 adv = !data->advertised ? cap :
2092 ethtool_adv_to_mmd_eee_adv_t(data->advertised) & cap;
2093 /* Mask prohibited EEE modes */
2094 adv &= ~dev->phydev->eee_broken_modes;
2095 }
2096
2097 if (old_adv != adv) {
2098 ret = rtl_set_eee_adv(tp, adv);
2099 if (ret < 0)
2100 goto out;
2101
2102 /* Restart autonegotiation so the new modes get sent to the
2103 * link partner.
2104 */
2105 ret = phy_restart_aneg(dev->phydev);
2106 }
2107
2108 out:
2109 pm_runtime_put_noidle(d);
2110 return ret < 0 ? ret : 0;
2111 }
2112
2113 static const struct ethtool_ops rtl8169_ethtool_ops = {
2114 .get_drvinfo = rtl8169_get_drvinfo,
2115 .get_regs_len = rtl8169_get_regs_len,
2116 .get_link = ethtool_op_get_link,
2117 .get_coalesce = rtl_get_coalesce,
2118 .set_coalesce = rtl_set_coalesce,
2119 .get_msglevel = rtl8169_get_msglevel,
2120 .set_msglevel = rtl8169_set_msglevel,
2121 .get_regs = rtl8169_get_regs,
2122 .get_wol = rtl8169_get_wol,
2123 .set_wol = rtl8169_set_wol,
2124 .get_strings = rtl8169_get_strings,
2125 .get_sset_count = rtl8169_get_sset_count,
2126 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2127 .get_ts_info = ethtool_op_get_ts_info,
2128 .nway_reset = phy_ethtool_nway_reset,
2129 .get_eee = rtl8169_get_eee,
2130 .set_eee = rtl8169_set_eee,
2131 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2132 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2133 };
2134
2135 static void rtl_enable_eee(struct rtl8169_private *tp)
2136 {
2137 int supported = rtl_get_eee_supp(tp);
2138
2139 if (supported > 0)
2140 rtl_set_eee_adv(tp, supported);
2141 }
2142
2143 static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2144 {
2145 /*
2146 * The driver currently handles the 8168Bf and the 8168Be identically
2147 * but they can be identified more specifically through the test below
2148 * if needed:
2149 *
2150 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2151 *
2152 * Same thing for the 8101Eb and the 8101Ec:
2153 *
2154 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2155 */
2156 static const struct rtl_mac_info {
2157 u16 mask;
2158 u16 val;
2159 u16 mac_version;
2160 } mac_info[] = {
2161 /* 8168EP family. */
2162 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2163 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2164 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2165
2166 /* 8168H family. */
2167 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2168 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2169
2170 /* 8168G family. */
2171 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2172 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2173 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2174 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2175
2176 /* 8168F family. */
2177 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2178 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2179 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2180
2181 /* 8168E family. */
2182 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2183 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2184 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2185
2186 /* 8168D family. */
2187 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2188 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2189
2190 /* 8168DP family. */
2191 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2192 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2193 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2194
2195 /* 8168C family. */
2196 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2197 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2198 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2199 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2200 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2201 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2202 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2203
2204 /* 8168B family. */
2205 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2206 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2207 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2208
2209 /* 8101 family. */
2210 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2211 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2212 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2213 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2214 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2215 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2216 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2217 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2218 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2219 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2220 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2221 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2222 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2223 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2224 /* FIXME: where did these entries come from ? -- FR */
2225 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2226 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2227
2228 /* 8110 family. */
2229 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2230 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2231 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2232 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2233 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2234
2235 /* Catch-all */
2236 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
2237 };
2238 const struct rtl_mac_info *p = mac_info;
2239 u16 reg = RTL_R32(tp, TxConfig) >> 20;
2240
2241 while ((reg & p->mask) != p->val)
2242 p++;
2243 tp->mac_version = p->mac_version;
2244
2245 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2246 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2247 } else if (!tp->supports_gmii) {
2248 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2249 tp->mac_version = RTL_GIGA_MAC_VER_43;
2250 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2251 tp->mac_version = RTL_GIGA_MAC_VER_47;
2252 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2253 tp->mac_version = RTL_GIGA_MAC_VER_48;
2254 }
2255 }
2256
2257 struct phy_reg {
2258 u16 reg;
2259 u16 val;
2260 };
2261
2262 static void __rtl_writephy_batch(struct rtl8169_private *tp,
2263 const struct phy_reg *regs, int len)
2264 {
2265 while (len-- > 0) {
2266 rtl_writephy(tp, regs->reg, regs->val);
2267 regs++;
2268 }
2269 }
2270
2271 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a))
2272
2273 static void rtl_release_firmware(struct rtl8169_private *tp)
2274 {
2275 if (tp->rtl_fw) {
2276 rtl_fw_release_firmware(tp->rtl_fw);
2277 kfree(tp->rtl_fw);
2278 tp->rtl_fw = NULL;
2279 }
2280 }
2281
2282 static void rtl_apply_firmware(struct rtl8169_private *tp)
2283 {
2284 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2285 if (tp->rtl_fw)
2286 rtl_fw_write_firmware(tp, tp->rtl_fw);
2287 }
2288
2289 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2290 {
2291 if (rtl_readphy(tp, reg) != val)
2292 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2293 else
2294 rtl_apply_firmware(tp);
2295 }
2296
2297 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2298 {
2299 /* Adjust EEE LED frequency */
2300 if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2301 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2302
2303 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);
2304 }
2305
2306 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2307 {
2308 struct phy_device *phydev = tp->phydev;
2309
2310 phy_write(phydev, 0x1f, 0x0007);
2311 phy_write(phydev, 0x1e, 0x0020);
2312 phy_set_bits(phydev, 0x15, BIT(8));
2313
2314 phy_write(phydev, 0x1f, 0x0005);
2315 phy_write(phydev, 0x05, 0x8b85);
2316 phy_set_bits(phydev, 0x06, BIT(13));
2317
2318 phy_write(phydev, 0x1f, 0x0000);
2319 }
2320
2321 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2322 {
2323 phy_modify_paged(tp->phydev, 0x0a43, 0x11, 0, BIT(4));
2324 }
2325
2326 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2327 {
2328 static const struct phy_reg phy_reg_init[] = {
2329 { 0x1f, 0x0001 },
2330 { 0x06, 0x006e },
2331 { 0x08, 0x0708 },
2332 { 0x15, 0x4000 },
2333 { 0x18, 0x65c7 },
2334
2335 { 0x1f, 0x0001 },
2336 { 0x03, 0x00a1 },
2337 { 0x02, 0x0008 },
2338 { 0x01, 0x0120 },
2339 { 0x00, 0x1000 },
2340 { 0x04, 0x0800 },
2341 { 0x04, 0x0000 },
2342
2343 { 0x03, 0xff41 },
2344 { 0x02, 0xdf60 },
2345 { 0x01, 0x0140 },
2346 { 0x00, 0x0077 },
2347 { 0x04, 0x7800 },
2348 { 0x04, 0x7000 },
2349
2350 { 0x03, 0x802f },
2351 { 0x02, 0x4f02 },
2352 { 0x01, 0x0409 },
2353 { 0x00, 0xf0f9 },
2354 { 0x04, 0x9800 },
2355 { 0x04, 0x9000 },
2356
2357 { 0x03, 0xdf01 },
2358 { 0x02, 0xdf20 },
2359 { 0x01, 0xff95 },
2360 { 0x00, 0xba00 },
2361 { 0x04, 0xa800 },
2362 { 0x04, 0xa000 },
2363
2364 { 0x03, 0xff41 },
2365 { 0x02, 0xdf20 },
2366 { 0x01, 0x0140 },
2367 { 0x00, 0x00bb },
2368 { 0x04, 0xb800 },
2369 { 0x04, 0xb000 },
2370
2371 { 0x03, 0xdf41 },
2372 { 0x02, 0xdc60 },
2373 { 0x01, 0x6340 },
2374 { 0x00, 0x007d },
2375 { 0x04, 0xd800 },
2376 { 0x04, 0xd000 },
2377
2378 { 0x03, 0xdf01 },
2379 { 0x02, 0xdf20 },
2380 { 0x01, 0x100a },
2381 { 0x00, 0xa0ff },
2382 { 0x04, 0xf800 },
2383 { 0x04, 0xf000 },
2384
2385 { 0x1f, 0x0000 },
2386 { 0x0b, 0x0000 },
2387 { 0x00, 0x9200 }
2388 };
2389
2390 rtl_writephy_batch(tp, phy_reg_init);
2391 }
2392
2393 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2394 {
2395 static const struct phy_reg phy_reg_init[] = {
2396 { 0x1f, 0x0002 },
2397 { 0x01, 0x90d0 },
2398 { 0x1f, 0x0000 }
2399 };
2400
2401 rtl_writephy_batch(tp, phy_reg_init);
2402 }
2403
2404 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2405 {
2406 struct pci_dev *pdev = tp->pci_dev;
2407
2408 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2409 (pdev->subsystem_device != 0xe000))
2410 return;
2411
2412 rtl_writephy(tp, 0x1f, 0x0001);
2413 rtl_writephy(tp, 0x10, 0xf01b);
2414 rtl_writephy(tp, 0x1f, 0x0000);
2415 }
2416
2417 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2418 {
2419 static const struct phy_reg phy_reg_init[] = {
2420 { 0x1f, 0x0001 },
2421 { 0x04, 0x0000 },
2422 { 0x03, 0x00a1 },
2423 { 0x02, 0x0008 },
2424 { 0x01, 0x0120 },
2425 { 0x00, 0x1000 },
2426 { 0x04, 0x0800 },
2427 { 0x04, 0x9000 },
2428 { 0x03, 0x802f },
2429 { 0x02, 0x4f02 },
2430 { 0x01, 0x0409 },
2431 { 0x00, 0xf099 },
2432 { 0x04, 0x9800 },
2433 { 0x04, 0xa000 },
2434 { 0x03, 0xdf01 },
2435 { 0x02, 0xdf20 },
2436 { 0x01, 0xff95 },
2437 { 0x00, 0xba00 },
2438 { 0x04, 0xa800 },
2439 { 0x04, 0xf000 },
2440 { 0x03, 0xdf01 },
2441 { 0x02, 0xdf20 },
2442 { 0x01, 0x101a },
2443 { 0x00, 0xa0ff },
2444 { 0x04, 0xf800 },
2445 { 0x04, 0x0000 },
2446 { 0x1f, 0x0000 },
2447
2448 { 0x1f, 0x0001 },
2449 { 0x10, 0xf41b },
2450 { 0x14, 0xfb54 },
2451 { 0x18, 0xf5c7 },
2452 { 0x1f, 0x0000 },
2453
2454 { 0x1f, 0x0001 },
2455 { 0x17, 0x0cc0 },
2456 { 0x1f, 0x0000 }
2457 };
2458
2459 rtl_writephy_batch(tp, phy_reg_init);
2460
2461 rtl8169scd_hw_phy_config_quirk(tp);
2462 }
2463
2464 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2465 {
2466 static const struct phy_reg phy_reg_init[] = {
2467 { 0x1f, 0x0001 },
2468 { 0x04, 0x0000 },
2469 { 0x03, 0x00a1 },
2470 { 0x02, 0x0008 },
2471 { 0x01, 0x0120 },
2472 { 0x00, 0x1000 },
2473 { 0x04, 0x0800 },
2474 { 0x04, 0x9000 },
2475 { 0x03, 0x802f },
2476 { 0x02, 0x4f02 },
2477 { 0x01, 0x0409 },
2478 { 0x00, 0xf099 },
2479 { 0x04, 0x9800 },
2480 { 0x04, 0xa000 },
2481 { 0x03, 0xdf01 },
2482 { 0x02, 0xdf20 },
2483 { 0x01, 0xff95 },
2484 { 0x00, 0xba00 },
2485 { 0x04, 0xa800 },
2486 { 0x04, 0xf000 },
2487 { 0x03, 0xdf01 },
2488 { 0x02, 0xdf20 },
2489 { 0x01, 0x101a },
2490 { 0x00, 0xa0ff },
2491 { 0x04, 0xf800 },
2492 { 0x04, 0x0000 },
2493 { 0x1f, 0x0000 },
2494
2495 { 0x1f, 0x0001 },
2496 { 0x0b, 0x8480 },
2497 { 0x1f, 0x0000 },
2498
2499 { 0x1f, 0x0001 },
2500 { 0x18, 0x67c7 },
2501 { 0x04, 0x2000 },
2502 { 0x03, 0x002f },
2503 { 0x02, 0x4360 },
2504 { 0x01, 0x0109 },
2505 { 0x00, 0x3022 },
2506 { 0x04, 0x2800 },
2507 { 0x1f, 0x0000 },
2508
2509 { 0x1f, 0x0001 },
2510 { 0x17, 0x0cc0 },
2511 { 0x1f, 0x0000 }
2512 };
2513
2514 rtl_writephy_batch(tp, phy_reg_init);
2515 }
2516
2517 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2518 {
2519 static const struct phy_reg phy_reg_init[] = {
2520 { 0x10, 0xf41b },
2521 { 0x1f, 0x0000 }
2522 };
2523
2524 rtl_writephy(tp, 0x1f, 0x0001);
2525 rtl_patchphy(tp, 0x16, 1 << 0);
2526
2527 rtl_writephy_batch(tp, phy_reg_init);
2528 }
2529
2530 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2531 {
2532 static const struct phy_reg phy_reg_init[] = {
2533 { 0x1f, 0x0001 },
2534 { 0x10, 0xf41b },
2535 { 0x1f, 0x0000 }
2536 };
2537
2538 rtl_writephy_batch(tp, phy_reg_init);
2539 }
2540
2541 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2542 {
2543 static const struct phy_reg phy_reg_init[] = {
2544 { 0x1f, 0x0000 },
2545 { 0x1d, 0x0f00 },
2546 { 0x1f, 0x0002 },
2547 { 0x0c, 0x1ec8 },
2548 { 0x1f, 0x0000 }
2549 };
2550
2551 rtl_writephy_batch(tp, phy_reg_init);
2552 }
2553
2554 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2555 {
2556 static const struct phy_reg phy_reg_init[] = {
2557 { 0x1f, 0x0001 },
2558 { 0x1d, 0x3d98 },
2559 { 0x1f, 0x0000 }
2560 };
2561
2562 rtl_writephy(tp, 0x1f, 0x0000);
2563 rtl_patchphy(tp, 0x14, 1 << 5);
2564 rtl_patchphy(tp, 0x0d, 1 << 5);
2565
2566 rtl_writephy_batch(tp, phy_reg_init);
2567 }
2568
2569 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2570 {
2571 static const struct phy_reg phy_reg_init[] = {
2572 { 0x1f, 0x0001 },
2573 { 0x12, 0x2300 },
2574 { 0x1f, 0x0002 },
2575 { 0x00, 0x88d4 },
2576 { 0x01, 0x82b1 },
2577 { 0x03, 0x7002 },
2578 { 0x08, 0x9e30 },
2579 { 0x09, 0x01f0 },
2580 { 0x0a, 0x5500 },
2581 { 0x0c, 0x00c8 },
2582 { 0x1f, 0x0003 },
2583 { 0x12, 0xc096 },
2584 { 0x16, 0x000a },
2585 { 0x1f, 0x0000 },
2586 { 0x1f, 0x0000 },
2587 { 0x09, 0x2000 },
2588 { 0x09, 0x0000 }
2589 };
2590
2591 rtl_writephy_batch(tp, phy_reg_init);
2592
2593 rtl_patchphy(tp, 0x14, 1 << 5);
2594 rtl_patchphy(tp, 0x0d, 1 << 5);
2595 rtl_writephy(tp, 0x1f, 0x0000);
2596 }
2597
2598 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2599 {
2600 static const struct phy_reg phy_reg_init[] = {
2601 { 0x1f, 0x0001 },
2602 { 0x12, 0x2300 },
2603 { 0x03, 0x802f },
2604 { 0x02, 0x4f02 },
2605 { 0x01, 0x0409 },
2606 { 0x00, 0xf099 },
2607 { 0x04, 0x9800 },
2608 { 0x04, 0x9000 },
2609 { 0x1d, 0x3d98 },
2610 { 0x1f, 0x0002 },
2611 { 0x0c, 0x7eb8 },
2612 { 0x06, 0x0761 },
2613 { 0x1f, 0x0003 },
2614 { 0x16, 0x0f0a },
2615 { 0x1f, 0x0000 }
2616 };
2617
2618 rtl_writephy_batch(tp, phy_reg_init);
2619
2620 rtl_patchphy(tp, 0x16, 1 << 0);
2621 rtl_patchphy(tp, 0x14, 1 << 5);
2622 rtl_patchphy(tp, 0x0d, 1 << 5);
2623 rtl_writephy(tp, 0x1f, 0x0000);
2624 }
2625
2626 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2627 {
2628 static const struct phy_reg phy_reg_init[] = {
2629 { 0x1f, 0x0001 },
2630 { 0x12, 0x2300 },
2631 { 0x1d, 0x3d98 },
2632 { 0x1f, 0x0002 },
2633 { 0x0c, 0x7eb8 },
2634 { 0x06, 0x5461 },
2635 { 0x1f, 0x0003 },
2636 { 0x16, 0x0f0a },
2637 { 0x1f, 0x0000 }
2638 };
2639
2640 rtl_writephy_batch(tp, phy_reg_init);
2641
2642 rtl_patchphy(tp, 0x16, 1 << 0);
2643 rtl_patchphy(tp, 0x14, 1 << 5);
2644 rtl_patchphy(tp, 0x0d, 1 << 5);
2645 rtl_writephy(tp, 0x1f, 0x0000);
2646 }
2647
2648 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2649 {
2650 rtl8168c_3_hw_phy_config(tp);
2651 }
2652
2653 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
2654 /* Channel Estimation */
2655 { 0x1f, 0x0001 },
2656 { 0x06, 0x4064 },
2657 { 0x07, 0x2863 },
2658 { 0x08, 0x059c },
2659 { 0x09, 0x26b4 },
2660 { 0x0a, 0x6a19 },
2661 { 0x0b, 0xdcc8 },
2662 { 0x10, 0xf06d },
2663 { 0x14, 0x7f68 },
2664 { 0x18, 0x7fd9 },
2665 { 0x1c, 0xf0ff },
2666 { 0x1d, 0x3d9c },
2667 { 0x1f, 0x0003 },
2668 { 0x12, 0xf49f },
2669 { 0x13, 0x070b },
2670 { 0x1a, 0x05ad },
2671 { 0x14, 0x94c0 },
2672
2673 /*
2674 * Tx Error Issue
2675 * Enhance line driver power
2676 */
2677 { 0x1f, 0x0002 },
2678 { 0x06, 0x5561 },
2679 { 0x1f, 0x0005 },
2680 { 0x05, 0x8332 },
2681 { 0x06, 0x5561 },
2682
2683 /*
2684 * Can not link to 1Gbps with bad cable
2685 * Decrease SNR threshold form 21.07dB to 19.04dB
2686 */
2687 { 0x1f, 0x0001 },
2688 { 0x17, 0x0cc0 },
2689
2690 { 0x1f, 0x0000 },
2691 { 0x0d, 0xf880 }
2692 };
2693
2694 static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = {
2695 { 0x1f, 0x0002 },
2696 { 0x05, 0x669a },
2697 { 0x1f, 0x0005 },
2698 { 0x05, 0x8330 },
2699 { 0x06, 0x669a },
2700 { 0x1f, 0x0002 }
2701 };
2702
2703 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2704 {
2705 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2706
2707 /*
2708 * Rx Error Issue
2709 * Fine Tune Switching regulator parameter
2710 */
2711 rtl_writephy(tp, 0x1f, 0x0002);
2712 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2713 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2714
2715 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2716 int val;
2717
2718 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2719
2720 val = rtl_readphy(tp, 0x0d);
2721
2722 if ((val & 0x00ff) != 0x006c) {
2723 static const u32 set[] = {
2724 0x0065, 0x0066, 0x0067, 0x0068,
2725 0x0069, 0x006a, 0x006b, 0x006c
2726 };
2727 int i;
2728
2729 rtl_writephy(tp, 0x1f, 0x0002);
2730
2731 val &= 0xff00;
2732 for (i = 0; i < ARRAY_SIZE(set); i++)
2733 rtl_writephy(tp, 0x0d, val | set[i]);
2734 }
2735 } else {
2736 static const struct phy_reg phy_reg_init[] = {
2737 { 0x1f, 0x0002 },
2738 { 0x05, 0x6662 },
2739 { 0x1f, 0x0005 },
2740 { 0x05, 0x8330 },
2741 { 0x06, 0x6662 }
2742 };
2743
2744 rtl_writephy_batch(tp, phy_reg_init);
2745 }
2746
2747 /* RSET couple improve */
2748 rtl_writephy(tp, 0x1f, 0x0002);
2749 rtl_patchphy(tp, 0x0d, 0x0300);
2750 rtl_patchphy(tp, 0x0f, 0x0010);
2751
2752 /* Fine tune PLL performance */
2753 rtl_writephy(tp, 0x1f, 0x0002);
2754 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2755 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2756
2757 rtl_writephy(tp, 0x1f, 0x0005);
2758 rtl_writephy(tp, 0x05, 0x001b);
2759
2760 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2761
2762 rtl_writephy(tp, 0x1f, 0x0000);
2763 }
2764
2765 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2766 {
2767 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2768
2769 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2770 int val;
2771
2772 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2773
2774 val = rtl_readphy(tp, 0x0d);
2775 if ((val & 0x00ff) != 0x006c) {
2776 static const u32 set[] = {
2777 0x0065, 0x0066, 0x0067, 0x0068,
2778 0x0069, 0x006a, 0x006b, 0x006c
2779 };
2780 int i;
2781
2782 rtl_writephy(tp, 0x1f, 0x0002);
2783
2784 val &= 0xff00;
2785 for (i = 0; i < ARRAY_SIZE(set); i++)
2786 rtl_writephy(tp, 0x0d, val | set[i]);
2787 }
2788 } else {
2789 static const struct phy_reg phy_reg_init[] = {
2790 { 0x1f, 0x0002 },
2791 { 0x05, 0x2642 },
2792 { 0x1f, 0x0005 },
2793 { 0x05, 0x8330 },
2794 { 0x06, 0x2642 }
2795 };
2796
2797 rtl_writephy_batch(tp, phy_reg_init);
2798 }
2799
2800 /* Fine tune PLL performance */
2801 rtl_writephy(tp, 0x1f, 0x0002);
2802 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2803 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2804
2805 /* Switching regulator Slew rate */
2806 rtl_writephy(tp, 0x1f, 0x0002);
2807 rtl_patchphy(tp, 0x0f, 0x0017);
2808
2809 rtl_writephy(tp, 0x1f, 0x0005);
2810 rtl_writephy(tp, 0x05, 0x001b);
2811
2812 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2813
2814 rtl_writephy(tp, 0x1f, 0x0000);
2815 }
2816
2817 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2818 {
2819 static const struct phy_reg phy_reg_init[] = {
2820 { 0x1f, 0x0002 },
2821 { 0x10, 0x0008 },
2822 { 0x0d, 0x006c },
2823
2824 { 0x1f, 0x0000 },
2825 { 0x0d, 0xf880 },
2826
2827 { 0x1f, 0x0001 },
2828 { 0x17, 0x0cc0 },
2829
2830 { 0x1f, 0x0001 },
2831 { 0x0b, 0xa4d8 },
2832 { 0x09, 0x281c },
2833 { 0x07, 0x2883 },
2834 { 0x0a, 0x6b35 },
2835 { 0x1d, 0x3da4 },
2836 { 0x1c, 0xeffd },
2837 { 0x14, 0x7f52 },
2838 { 0x18, 0x7fc6 },
2839 { 0x08, 0x0601 },
2840 { 0x06, 0x4063 },
2841 { 0x10, 0xf074 },
2842 { 0x1f, 0x0003 },
2843 { 0x13, 0x0789 },
2844 { 0x12, 0xf4bd },
2845 { 0x1a, 0x04fd },
2846 { 0x14, 0x84b0 },
2847 { 0x1f, 0x0000 },
2848 { 0x00, 0x9200 },
2849
2850 { 0x1f, 0x0005 },
2851 { 0x01, 0x0340 },
2852 { 0x1f, 0x0001 },
2853 { 0x04, 0x4000 },
2854 { 0x03, 0x1d21 },
2855 { 0x02, 0x0c32 },
2856 { 0x01, 0x0200 },
2857 { 0x00, 0x5554 },
2858 { 0x04, 0x4800 },
2859 { 0x04, 0x4000 },
2860 { 0x04, 0xf000 },
2861 { 0x03, 0xdf01 },
2862 { 0x02, 0xdf20 },
2863 { 0x01, 0x101a },
2864 { 0x00, 0xa0ff },
2865 { 0x04, 0xf800 },
2866 { 0x04, 0xf000 },
2867 { 0x1f, 0x0000 },
2868
2869 { 0x1f, 0x0007 },
2870 { 0x1e, 0x0023 },
2871 { 0x16, 0x0000 },
2872 { 0x1f, 0x0000 }
2873 };
2874
2875 rtl_writephy_batch(tp, phy_reg_init);
2876 }
2877
2878 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2879 {
2880 static const struct phy_reg phy_reg_init[] = {
2881 { 0x1f, 0x0001 },
2882 { 0x17, 0x0cc0 },
2883
2884 { 0x1f, 0x0007 },
2885 { 0x1e, 0x002d },
2886 { 0x18, 0x0040 },
2887 { 0x1f, 0x0000 }
2888 };
2889
2890 rtl_writephy_batch(tp, phy_reg_init);
2891 rtl_patchphy(tp, 0x0d, 1 << 5);
2892 }
2893
2894 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2895 {
2896 static const struct phy_reg phy_reg_init[] = {
2897 /* Enable Delay cap */
2898 { 0x1f, 0x0005 },
2899 { 0x05, 0x8b80 },
2900 { 0x06, 0xc896 },
2901 { 0x1f, 0x0000 },
2902
2903 /* Channel estimation fine tune */
2904 { 0x1f, 0x0001 },
2905 { 0x0b, 0x6c20 },
2906 { 0x07, 0x2872 },
2907 { 0x1c, 0xefff },
2908 { 0x1f, 0x0003 },
2909 { 0x14, 0x6420 },
2910 { 0x1f, 0x0000 },
2911
2912 /* Update PFM & 10M TX idle timer */
2913 { 0x1f, 0x0007 },
2914 { 0x1e, 0x002f },
2915 { 0x15, 0x1919 },
2916 { 0x1f, 0x0000 },
2917
2918 { 0x1f, 0x0007 },
2919 { 0x1e, 0x00ac },
2920 { 0x18, 0x0006 },
2921 { 0x1f, 0x0000 }
2922 };
2923
2924 rtl_apply_firmware(tp);
2925
2926 rtl_writephy_batch(tp, phy_reg_init);
2927
2928 /* DCO enable for 10M IDLE Power */
2929 rtl_writephy(tp, 0x1f, 0x0007);
2930 rtl_writephy(tp, 0x1e, 0x0023);
2931 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
2932 rtl_writephy(tp, 0x1f, 0x0000);
2933
2934 /* For impedance matching */
2935 rtl_writephy(tp, 0x1f, 0x0002);
2936 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
2937 rtl_writephy(tp, 0x1f, 0x0000);
2938
2939 /* PHY auto speed down */
2940 rtl_writephy(tp, 0x1f, 0x0007);
2941 rtl_writephy(tp, 0x1e, 0x002d);
2942 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
2943 rtl_writephy(tp, 0x1f, 0x0000);
2944 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
2945
2946 rtl_writephy(tp, 0x1f, 0x0005);
2947 rtl_writephy(tp, 0x05, 0x8b86);
2948 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
2949 rtl_writephy(tp, 0x1f, 0x0000);
2950
2951 rtl_writephy(tp, 0x1f, 0x0005);
2952 rtl_writephy(tp, 0x05, 0x8b85);
2953 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
2954 rtl_writephy(tp, 0x1f, 0x0007);
2955 rtl_writephy(tp, 0x1e, 0x0020);
2956 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
2957 rtl_writephy(tp, 0x1f, 0x0006);
2958 rtl_writephy(tp, 0x00, 0x5a00);
2959 rtl_writephy(tp, 0x1f, 0x0000);
2960 rtl_writephy(tp, 0x0d, 0x0007);
2961 rtl_writephy(tp, 0x0e, 0x003c);
2962 rtl_writephy(tp, 0x0d, 0x4007);
2963 rtl_writephy(tp, 0x0e, 0x0000);
2964 rtl_writephy(tp, 0x0d, 0x0000);
2965 }
2966
2967 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
2968 {
2969 const u16 w[] = {
2970 addr[0] | (addr[1] << 8),
2971 addr[2] | (addr[3] << 8),
2972 addr[4] | (addr[5] << 8)
2973 };
2974
2975 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
2976 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
2977 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
2978 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
2979 }
2980
2981 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2982 {
2983 static const struct phy_reg phy_reg_init[] = {
2984 /* Enable Delay cap */
2985 { 0x1f, 0x0004 },
2986 { 0x1f, 0x0007 },
2987 { 0x1e, 0x00ac },
2988 { 0x18, 0x0006 },
2989 { 0x1f, 0x0002 },
2990 { 0x1f, 0x0000 },
2991 { 0x1f, 0x0000 },
2992
2993 /* Channel estimation fine tune */
2994 { 0x1f, 0x0003 },
2995 { 0x09, 0xa20f },
2996 { 0x1f, 0x0000 },
2997 { 0x1f, 0x0000 },
2998
2999 /* Green Setting */
3000 { 0x1f, 0x0005 },
3001 { 0x05, 0x8b5b },
3002 { 0x06, 0x9222 },
3003 { 0x05, 0x8b6d },
3004 { 0x06, 0x8000 },
3005 { 0x05, 0x8b76 },
3006 { 0x06, 0x8000 },
3007 { 0x1f, 0x0000 }
3008 };
3009
3010 rtl_apply_firmware(tp);
3011
3012 rtl_writephy_batch(tp, phy_reg_init);
3013
3014 /* For 4-corner performance improve */
3015 rtl_writephy(tp, 0x1f, 0x0005);
3016 rtl_writephy(tp, 0x05, 0x8b80);
3017 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3018 rtl_writephy(tp, 0x1f, 0x0000);
3019
3020 /* PHY auto speed down */
3021 rtl_writephy(tp, 0x1f, 0x0004);
3022 rtl_writephy(tp, 0x1f, 0x0007);
3023 rtl_writephy(tp, 0x1e, 0x002d);
3024 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3025 rtl_writephy(tp, 0x1f, 0x0002);
3026 rtl_writephy(tp, 0x1f, 0x0000);
3027 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3028
3029 /* improve 10M EEE waveform */
3030 rtl_writephy(tp, 0x1f, 0x0005);
3031 rtl_writephy(tp, 0x05, 0x8b86);
3032 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3033 rtl_writephy(tp, 0x1f, 0x0000);
3034
3035 /* Improve 2-pair detection performance */
3036 rtl_writephy(tp, 0x1f, 0x0005);
3037 rtl_writephy(tp, 0x05, 0x8b85);
3038 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3039 rtl_writephy(tp, 0x1f, 0x0000);
3040
3041 rtl8168f_config_eee_phy(tp);
3042 rtl_enable_eee(tp);
3043
3044 /* Green feature */
3045 rtl_writephy(tp, 0x1f, 0x0003);
3046 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3047 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3048 rtl_writephy(tp, 0x1f, 0x0000);
3049 rtl_writephy(tp, 0x1f, 0x0005);
3050 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3051 rtl_writephy(tp, 0x1f, 0x0000);
3052
3053 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3054 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3055 }
3056
3057 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3058 {
3059 /* For 4-corner performance improve */
3060 rtl_writephy(tp, 0x1f, 0x0005);
3061 rtl_writephy(tp, 0x05, 0x8b80);
3062 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3063 rtl_writephy(tp, 0x1f, 0x0000);
3064
3065 /* PHY auto speed down */
3066 rtl_writephy(tp, 0x1f, 0x0007);
3067 rtl_writephy(tp, 0x1e, 0x002d);
3068 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3069 rtl_writephy(tp, 0x1f, 0x0000);
3070 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3071
3072 /* Improve 10M EEE waveform */
3073 rtl_writephy(tp, 0x1f, 0x0005);
3074 rtl_writephy(tp, 0x05, 0x8b86);
3075 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3076 rtl_writephy(tp, 0x1f, 0x0000);
3077
3078 rtl8168f_config_eee_phy(tp);
3079 rtl_enable_eee(tp);
3080 }
3081
3082 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3083 {
3084 static const struct phy_reg phy_reg_init[] = {
3085 /* Channel estimation fine tune */
3086 { 0x1f, 0x0003 },
3087 { 0x09, 0xa20f },
3088 { 0x1f, 0x0000 },
3089
3090 /* Modify green table for giga & fnet */
3091 { 0x1f, 0x0005 },
3092 { 0x05, 0x8b55 },
3093 { 0x06, 0x0000 },
3094 { 0x05, 0x8b5e },
3095 { 0x06, 0x0000 },
3096 { 0x05, 0x8b67 },
3097 { 0x06, 0x0000 },
3098 { 0x05, 0x8b70 },
3099 { 0x06, 0x0000 },
3100 { 0x1f, 0x0000 },
3101 { 0x1f, 0x0007 },
3102 { 0x1e, 0x0078 },
3103 { 0x17, 0x0000 },
3104 { 0x19, 0x00fb },
3105 { 0x1f, 0x0000 },
3106
3107 /* Modify green table for 10M */
3108 { 0x1f, 0x0005 },
3109 { 0x05, 0x8b79 },
3110 { 0x06, 0xaa00 },
3111 { 0x1f, 0x0000 },
3112
3113 /* Disable hiimpedance detection (RTCT) */
3114 { 0x1f, 0x0003 },
3115 { 0x01, 0x328a },
3116 { 0x1f, 0x0000 }
3117 };
3118
3119 rtl_apply_firmware(tp);
3120
3121 rtl_writephy_batch(tp, phy_reg_init);
3122
3123 rtl8168f_hw_phy_config(tp);
3124
3125 /* Improve 2-pair detection performance */
3126 rtl_writephy(tp, 0x1f, 0x0005);
3127 rtl_writephy(tp, 0x05, 0x8b85);
3128 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3129 rtl_writephy(tp, 0x1f, 0x0000);
3130 }
3131
3132 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3133 {
3134 rtl_apply_firmware(tp);
3135
3136 rtl8168f_hw_phy_config(tp);
3137 }
3138
3139 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3140 {
3141 static const struct phy_reg phy_reg_init[] = {
3142 /* Channel estimation fine tune */
3143 { 0x1f, 0x0003 },
3144 { 0x09, 0xa20f },
3145 { 0x1f, 0x0000 },
3146
3147 /* Modify green table for giga & fnet */
3148 { 0x1f, 0x0005 },
3149 { 0x05, 0x8b55 },
3150 { 0x06, 0x0000 },
3151 { 0x05, 0x8b5e },
3152 { 0x06, 0x0000 },
3153 { 0x05, 0x8b67 },
3154 { 0x06, 0x0000 },
3155 { 0x05, 0x8b70 },
3156 { 0x06, 0x0000 },
3157 { 0x1f, 0x0000 },
3158 { 0x1f, 0x0007 },
3159 { 0x1e, 0x0078 },
3160 { 0x17, 0x0000 },
3161 { 0x19, 0x00aa },
3162 { 0x1f, 0x0000 },
3163
3164 /* Modify green table for 10M */
3165 { 0x1f, 0x0005 },
3166 { 0x05, 0x8b79 },
3167 { 0x06, 0xaa00 },
3168 { 0x1f, 0x0000 },
3169
3170 /* Disable hiimpedance detection (RTCT) */
3171 { 0x1f, 0x0003 },
3172 { 0x01, 0x328a },
3173 { 0x1f, 0x0000 }
3174 };
3175
3176
3177 rtl_apply_firmware(tp);
3178
3179 rtl8168f_hw_phy_config(tp);
3180
3181 /* Improve 2-pair detection performance */
3182 rtl_writephy(tp, 0x1f, 0x0005);
3183 rtl_writephy(tp, 0x05, 0x8b85);
3184 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3185 rtl_writephy(tp, 0x1f, 0x0000);
3186
3187 rtl_writephy_batch(tp, phy_reg_init);
3188
3189 /* Modify green table for giga */
3190 rtl_writephy(tp, 0x1f, 0x0005);
3191 rtl_writephy(tp, 0x05, 0x8b54);
3192 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3193 rtl_writephy(tp, 0x05, 0x8b5d);
3194 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3195 rtl_writephy(tp, 0x05, 0x8a7c);
3196 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3197 rtl_writephy(tp, 0x05, 0x8a7f);
3198 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3199 rtl_writephy(tp, 0x05, 0x8a82);
3200 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3201 rtl_writephy(tp, 0x05, 0x8a85);
3202 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3203 rtl_writephy(tp, 0x05, 0x8a88);
3204 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3205 rtl_writephy(tp, 0x1f, 0x0000);
3206
3207 /* uc same-seed solution */
3208 rtl_writephy(tp, 0x1f, 0x0005);
3209 rtl_writephy(tp, 0x05, 0x8b85);
3210 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3211 rtl_writephy(tp, 0x1f, 0x0000);
3212
3213 /* Green feature */
3214 rtl_writephy(tp, 0x1f, 0x0003);
3215 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3216 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3217 rtl_writephy(tp, 0x1f, 0x0000);
3218 }
3219
3220 static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3221 {
3222 phy_modify_paged(tp->phydev, 0x0a43, 0x10, BIT(2), 0);
3223 }
3224
3225 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3226 {
3227 struct phy_device *phydev = tp->phydev;
3228
3229 phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0);
3230 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6));
3231 phy_write(phydev, 0x1f, 0x0a43);
3232 phy_write(phydev, 0x13, 0x8084);
3233 phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13));
3234 phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0));
3235
3236 phy_write(phydev, 0x1f, 0x0000);
3237 }
3238
3239 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3240 {
3241 int ret;
3242
3243 rtl_apply_firmware(tp);
3244
3245 ret = phy_read_paged(tp->phydev, 0x0a46, 0x10);
3246 if (ret & BIT(8))
3247 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, BIT(15), 0);
3248 else
3249 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, 0, BIT(15));
3250
3251 ret = phy_read_paged(tp->phydev, 0x0a46, 0x13);
3252 if (ret & BIT(8))
3253 phy_modify_paged(tp->phydev, 0x0c41, 0x12, 0, BIT(1));
3254 else
3255 phy_modify_paged(tp->phydev, 0x0c41, 0x12, BIT(1), 0);
3256
3257 /* Enable PHY auto speed down */
3258 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3259
3260 rtl8168g_phy_adjust_10m_aldps(tp);
3261
3262 /* EEE auto-fallback function */
3263 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3264
3265 /* Enable UC LPF tune function */
3266 rtl_writephy(tp, 0x1f, 0x0a43);
3267 rtl_writephy(tp, 0x13, 0x8012);
3268 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3269
3270 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3271
3272 /* Improve SWR Efficiency */
3273 rtl_writephy(tp, 0x1f, 0x0bcd);
3274 rtl_writephy(tp, 0x14, 0x5065);
3275 rtl_writephy(tp, 0x14, 0xd065);
3276 rtl_writephy(tp, 0x1f, 0x0bc8);
3277 rtl_writephy(tp, 0x11, 0x5655);
3278 rtl_writephy(tp, 0x1f, 0x0bcd);
3279 rtl_writephy(tp, 0x14, 0x1065);
3280 rtl_writephy(tp, 0x14, 0x9065);
3281 rtl_writephy(tp, 0x14, 0x1065);
3282 rtl_writephy(tp, 0x1f, 0x0000);
3283
3284 rtl8168g_disable_aldps(tp);
3285 rtl8168g_config_eee_phy(tp);
3286 rtl_enable_eee(tp);
3287 }
3288
3289 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3290 {
3291 rtl_apply_firmware(tp);
3292 rtl8168g_config_eee_phy(tp);
3293 rtl_enable_eee(tp);
3294 }
3295
3296 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3297 {
3298 u16 dout_tapbin;
3299 u32 data;
3300
3301 rtl_apply_firmware(tp);
3302
3303 /* CHN EST parameters adjust - giga master */
3304 rtl_writephy(tp, 0x1f, 0x0a43);
3305 rtl_writephy(tp, 0x13, 0x809b);
3306 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3307 rtl_writephy(tp, 0x13, 0x80a2);
3308 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3309 rtl_writephy(tp, 0x13, 0x80a4);
3310 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3311 rtl_writephy(tp, 0x13, 0x809c);
3312 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3313 rtl_writephy(tp, 0x1f, 0x0000);
3314
3315 /* CHN EST parameters adjust - giga slave */
3316 rtl_writephy(tp, 0x1f, 0x0a43);
3317 rtl_writephy(tp, 0x13, 0x80ad);
3318 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3319 rtl_writephy(tp, 0x13, 0x80b4);
3320 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3321 rtl_writephy(tp, 0x13, 0x80ac);
3322 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3323 rtl_writephy(tp, 0x1f, 0x0000);
3324
3325 /* CHN EST parameters adjust - fnet */
3326 rtl_writephy(tp, 0x1f, 0x0a43);
3327 rtl_writephy(tp, 0x13, 0x808e);
3328 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3329 rtl_writephy(tp, 0x13, 0x8090);
3330 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3331 rtl_writephy(tp, 0x13, 0x8092);
3332 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3333 rtl_writephy(tp, 0x1f, 0x0000);
3334
3335 /* enable R-tune & PGA-retune function */
3336 dout_tapbin = 0;
3337 rtl_writephy(tp, 0x1f, 0x0a46);
3338 data = rtl_readphy(tp, 0x13);
3339 data &= 3;
3340 data <<= 2;
3341 dout_tapbin |= data;
3342 data = rtl_readphy(tp, 0x12);
3343 data &= 0xc000;
3344 data >>= 14;
3345 dout_tapbin |= data;
3346 dout_tapbin = ~(dout_tapbin^0x08);
3347 dout_tapbin <<= 12;
3348 dout_tapbin &= 0xf000;
3349 rtl_writephy(tp, 0x1f, 0x0a43);
3350 rtl_writephy(tp, 0x13, 0x827a);
3351 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3352 rtl_writephy(tp, 0x13, 0x827b);
3353 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3354 rtl_writephy(tp, 0x13, 0x827c);
3355 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3356 rtl_writephy(tp, 0x13, 0x827d);
3357 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3358
3359 rtl_writephy(tp, 0x1f, 0x0a43);
3360 rtl_writephy(tp, 0x13, 0x0811);
3361 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3362 rtl_writephy(tp, 0x1f, 0x0a42);
3363 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3364 rtl_writephy(tp, 0x1f, 0x0000);
3365
3366 /* enable GPHY 10M */
3367 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3368
3369 /* SAR ADC performance */
3370 phy_modify_paged(tp->phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14));
3371
3372 rtl_writephy(tp, 0x1f, 0x0a43);
3373 rtl_writephy(tp, 0x13, 0x803f);
3374 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3375 rtl_writephy(tp, 0x13, 0x8047);
3376 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3377 rtl_writephy(tp, 0x13, 0x804f);
3378 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3379 rtl_writephy(tp, 0x13, 0x8057);
3380 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3381 rtl_writephy(tp, 0x13, 0x805f);
3382 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3383 rtl_writephy(tp, 0x13, 0x8067);
3384 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3385 rtl_writephy(tp, 0x13, 0x806f);
3386 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3387 rtl_writephy(tp, 0x1f, 0x0000);
3388
3389 /* disable phy pfm mode */
3390 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3391
3392 rtl8168g_disable_aldps(tp);
3393 rtl8168g_config_eee_phy(tp);
3394 rtl_enable_eee(tp);
3395 }
3396
3397 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3398 {
3399 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3400 u16 rlen;
3401 u32 data;
3402
3403 rtl_apply_firmware(tp);
3404
3405 /* CHIN EST parameter update */
3406 rtl_writephy(tp, 0x1f, 0x0a43);
3407 rtl_writephy(tp, 0x13, 0x808a);
3408 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3409 rtl_writephy(tp, 0x1f, 0x0000);
3410
3411 /* enable R-tune & PGA-retune function */
3412 rtl_writephy(tp, 0x1f, 0x0a43);
3413 rtl_writephy(tp, 0x13, 0x0811);
3414 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3415 rtl_writephy(tp, 0x1f, 0x0a42);
3416 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3417 rtl_writephy(tp, 0x1f, 0x0000);
3418
3419 /* enable GPHY 10M */
3420 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3421
3422 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3423 data = r8168_mac_ocp_read(tp, 0xdd02);
3424 ioffset_p3 = ((data & 0x80)>>7);
3425 ioffset_p3 <<= 3;
3426
3427 data = r8168_mac_ocp_read(tp, 0xdd00);
3428 ioffset_p3 |= ((data & (0xe000))>>13);
3429 ioffset_p2 = ((data & (0x1e00))>>9);
3430 ioffset_p1 = ((data & (0x01e0))>>5);
3431 ioffset_p0 = ((data & 0x0010)>>4);
3432 ioffset_p0 <<= 3;
3433 ioffset_p0 |= (data & (0x07));
3434 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3435
3436 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3437 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3438 rtl_writephy(tp, 0x1f, 0x0bcf);
3439 rtl_writephy(tp, 0x16, data);
3440 rtl_writephy(tp, 0x1f, 0x0000);
3441 }
3442
3443 /* Modify rlen (TX LPF corner frequency) level */
3444 rtl_writephy(tp, 0x1f, 0x0bcd);
3445 data = rtl_readphy(tp, 0x16);
3446 data &= 0x000f;
3447 rlen = 0;
3448 if (data > 3)
3449 rlen = data - 3;
3450 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3451 rtl_writephy(tp, 0x17, data);
3452 rtl_writephy(tp, 0x1f, 0x0bcd);
3453 rtl_writephy(tp, 0x1f, 0x0000);
3454
3455 /* disable phy pfm mode */
3456 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3457
3458 rtl8168g_disable_aldps(tp);
3459 rtl8168g_config_eee_phy(tp);
3460 rtl_enable_eee(tp);
3461 }
3462
3463 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3464 {
3465 /* Enable PHY auto speed down */
3466 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3467
3468 rtl8168g_phy_adjust_10m_aldps(tp);
3469
3470 /* Enable EEE auto-fallback function */
3471 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3472
3473 /* Enable UC LPF tune function */
3474 rtl_writephy(tp, 0x1f, 0x0a43);
3475 rtl_writephy(tp, 0x13, 0x8012);
3476 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3477 rtl_writephy(tp, 0x1f, 0x0000);
3478
3479 /* set rg_sel_sdm_rate */
3480 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3481
3482 rtl8168g_disable_aldps(tp);
3483 rtl8168g_config_eee_phy(tp);
3484 rtl_enable_eee(tp);
3485 }
3486
3487 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3488 {
3489 rtl8168g_phy_adjust_10m_aldps(tp);
3490
3491 /* Enable UC LPF tune function */
3492 rtl_writephy(tp, 0x1f, 0x0a43);
3493 rtl_writephy(tp, 0x13, 0x8012);
3494 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3495 rtl_writephy(tp, 0x1f, 0x0000);
3496
3497 /* Set rg_sel_sdm_rate */
3498 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3499
3500 /* Channel estimation parameters */
3501 rtl_writephy(tp, 0x1f, 0x0a43);
3502 rtl_writephy(tp, 0x13, 0x80f3);
3503 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3504 rtl_writephy(tp, 0x13, 0x80f0);
3505 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3506 rtl_writephy(tp, 0x13, 0x80ef);
3507 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3508 rtl_writephy(tp, 0x13, 0x80f6);
3509 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3510 rtl_writephy(tp, 0x13, 0x80ec);
3511 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3512 rtl_writephy(tp, 0x13, 0x80ed);
3513 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3514 rtl_writephy(tp, 0x13, 0x80f2);
3515 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3516 rtl_writephy(tp, 0x13, 0x80f4);
3517 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3518 rtl_writephy(tp, 0x1f, 0x0a43);
3519 rtl_writephy(tp, 0x13, 0x8110);
3520 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3521 rtl_writephy(tp, 0x13, 0x810f);
3522 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3523 rtl_writephy(tp, 0x13, 0x8111);
3524 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3525 rtl_writephy(tp, 0x13, 0x8113);
3526 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3527 rtl_writephy(tp, 0x13, 0x8115);
3528 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3529 rtl_writephy(tp, 0x13, 0x810e);
3530 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3531 rtl_writephy(tp, 0x13, 0x810c);
3532 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3533 rtl_writephy(tp, 0x13, 0x810b);
3534 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3535 rtl_writephy(tp, 0x1f, 0x0a43);
3536 rtl_writephy(tp, 0x13, 0x80d1);
3537 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3538 rtl_writephy(tp, 0x13, 0x80cd);
3539 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3540 rtl_writephy(tp, 0x13, 0x80d3);
3541 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3542 rtl_writephy(tp, 0x13, 0x80d5);
3543 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3544 rtl_writephy(tp, 0x13, 0x80d7);
3545 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3546
3547 /* Force PWM-mode */
3548 rtl_writephy(tp, 0x1f, 0x0bcd);
3549 rtl_writephy(tp, 0x14, 0x5065);
3550 rtl_writephy(tp, 0x14, 0xd065);
3551 rtl_writephy(tp, 0x1f, 0x0bc8);
3552 rtl_writephy(tp, 0x12, 0x00ed);
3553 rtl_writephy(tp, 0x1f, 0x0bcd);
3554 rtl_writephy(tp, 0x14, 0x1065);
3555 rtl_writephy(tp, 0x14, 0x9065);
3556 rtl_writephy(tp, 0x14, 0x1065);
3557 rtl_writephy(tp, 0x1f, 0x0000);
3558
3559 rtl8168g_disable_aldps(tp);
3560 rtl8168g_config_eee_phy(tp);
3561 rtl_enable_eee(tp);
3562 }
3563
3564 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3565 {
3566 static const struct phy_reg phy_reg_init[] = {
3567 { 0x1f, 0x0003 },
3568 { 0x08, 0x441d },
3569 { 0x01, 0x9100 },
3570 { 0x1f, 0x0000 }
3571 };
3572
3573 rtl_writephy(tp, 0x1f, 0x0000);
3574 rtl_patchphy(tp, 0x11, 1 << 12);
3575 rtl_patchphy(tp, 0x19, 1 << 13);
3576 rtl_patchphy(tp, 0x10, 1 << 15);
3577
3578 rtl_writephy_batch(tp, phy_reg_init);
3579 }
3580
3581 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3582 {
3583 static const struct phy_reg phy_reg_init[] = {
3584 { 0x1f, 0x0005 },
3585 { 0x1a, 0x0000 },
3586 { 0x1f, 0x0000 },
3587
3588 { 0x1f, 0x0004 },
3589 { 0x1c, 0x0000 },
3590 { 0x1f, 0x0000 },
3591
3592 { 0x1f, 0x0001 },
3593 { 0x15, 0x7701 },
3594 { 0x1f, 0x0000 }
3595 };
3596
3597 /* Disable ALDPS before ram code */
3598 rtl_writephy(tp, 0x1f, 0x0000);
3599 rtl_writephy(tp, 0x18, 0x0310);
3600 msleep(100);
3601
3602 rtl_apply_firmware(tp);
3603
3604 rtl_writephy_batch(tp, phy_reg_init);
3605 }
3606
3607 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3608 {
3609 /* Disable ALDPS before setting firmware */
3610 rtl_writephy(tp, 0x1f, 0x0000);
3611 rtl_writephy(tp, 0x18, 0x0310);
3612 msleep(20);
3613
3614 rtl_apply_firmware(tp);
3615
3616 /* EEE setting */
3617 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3618 rtl_writephy(tp, 0x1f, 0x0004);
3619 rtl_writephy(tp, 0x10, 0x401f);
3620 rtl_writephy(tp, 0x19, 0x7030);
3621 rtl_writephy(tp, 0x1f, 0x0000);
3622 }
3623
3624 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3625 {
3626 static const struct phy_reg phy_reg_init[] = {
3627 { 0x1f, 0x0004 },
3628 { 0x10, 0xc07f },
3629 { 0x19, 0x7030 },
3630 { 0x1f, 0x0000 }
3631 };
3632
3633 /* Disable ALDPS before ram code */
3634 rtl_writephy(tp, 0x1f, 0x0000);
3635 rtl_writephy(tp, 0x18, 0x0310);
3636 msleep(100);
3637
3638 rtl_apply_firmware(tp);
3639
3640 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3641 rtl_writephy_batch(tp, phy_reg_init);
3642
3643 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3644 }
3645
3646 static void rtl_hw_phy_config(struct net_device *dev)
3647 {
3648 static const rtl_generic_fct phy_configs[] = {
3649 /* PCI devices. */
3650 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
3651 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
3652 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
3653 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
3654 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
3655 /* PCI-E devices. */
3656 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
3657 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
3658 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
3659 [RTL_GIGA_MAC_VER_10] = NULL,
3660 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
3661 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config,
3662 [RTL_GIGA_MAC_VER_13] = NULL,
3663 [RTL_GIGA_MAC_VER_14] = NULL,
3664 [RTL_GIGA_MAC_VER_15] = NULL,
3665 [RTL_GIGA_MAC_VER_16] = NULL,
3666 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
3667 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
3668 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
3669 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
3670 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
3671 [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config,
3672 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
3673 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
3674 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
3675 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
3676 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config,
3677 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
3678 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
3679 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
3680 [RTL_GIGA_MAC_VER_31] = NULL,
3681 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
3682 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
3683 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
3684 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
3685 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
3686 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
3687 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
3688 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
3689 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
3690 [RTL_GIGA_MAC_VER_41] = NULL,
3691 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
3692 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
3693 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
3694 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config,
3695 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
3696 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config,
3697 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
3698 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config,
3699 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config,
3700 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
3701 };
3702 struct rtl8169_private *tp = netdev_priv(dev);
3703
3704 if (phy_configs[tp->mac_version])
3705 phy_configs[tp->mac_version](tp);
3706 }
3707
3708 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3709 {
3710 if (!test_and_set_bit(flag, tp->wk.flags))
3711 schedule_work(&tp->wk.work);
3712 }
3713
3714 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3715 {
3716 rtl_hw_phy_config(dev);
3717
3718 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3719 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3720 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3721 netif_dbg(tp, drv, dev,
3722 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3723 RTL_W8(tp, 0x82, 0x01);
3724 }
3725
3726 /* We may have called phy_speed_down before */
3727 phy_speed_up(tp->phydev);
3728
3729 genphy_soft_reset(tp->phydev);
3730 }
3731
3732 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3733 {
3734 rtl_lock_work(tp);
3735
3736 rtl_unlock_config_regs(tp);
3737
3738 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
3739 RTL_R32(tp, MAC4);
3740
3741 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3742 RTL_R32(tp, MAC0);
3743
3744 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3745 rtl_rar_exgmac_set(tp, addr);
3746
3747 rtl_lock_config_regs(tp);
3748
3749 rtl_unlock_work(tp);
3750 }
3751
3752 static int rtl_set_mac_address(struct net_device *dev, void *p)
3753 {
3754 struct rtl8169_private *tp = netdev_priv(dev);
3755 struct device *d = tp_to_dev(tp);
3756 int ret;
3757
3758 ret = eth_mac_addr(dev, p);
3759 if (ret)
3760 return ret;
3761
3762 pm_runtime_get_noresume(d);
3763
3764 if (pm_runtime_active(d))
3765 rtl_rar_set(tp, dev->dev_addr);
3766
3767 pm_runtime_put_noidle(d);
3768
3769 return 0;
3770 }
3771
3772 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3773 {
3774 struct rtl8169_private *tp = netdev_priv(dev);
3775
3776 if (!netif_running(dev))
3777 return -ENODEV;
3778
3779 return phy_mii_ioctl(tp->phydev, ifr, cmd);
3780 }
3781
3782 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3783 {
3784 switch (tp->mac_version) {
3785 case RTL_GIGA_MAC_VER_25:
3786 case RTL_GIGA_MAC_VER_26:
3787 case RTL_GIGA_MAC_VER_29:
3788 case RTL_GIGA_MAC_VER_30:
3789 case RTL_GIGA_MAC_VER_32:
3790 case RTL_GIGA_MAC_VER_33:
3791 case RTL_GIGA_MAC_VER_34:
3792 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
3793 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
3794 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3795 break;
3796 default:
3797 break;
3798 }
3799 }
3800
3801 static void rtl_pll_power_down(struct rtl8169_private *tp)
3802 {
3803 if (r8168_check_dash(tp))
3804 return;
3805
3806 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3807 tp->mac_version == RTL_GIGA_MAC_VER_33)
3808 rtl_ephy_write(tp, 0x19, 0xff64);
3809
3810 if (device_may_wakeup(tp_to_dev(tp))) {
3811 phy_speed_down(tp->phydev, false);
3812 rtl_wol_suspend_quirk(tp);
3813 return;
3814 }
3815
3816 switch (tp->mac_version) {
3817 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
3818 case RTL_GIGA_MAC_VER_37:
3819 case RTL_GIGA_MAC_VER_39:
3820 case RTL_GIGA_MAC_VER_43:
3821 case RTL_GIGA_MAC_VER_44:
3822 case RTL_GIGA_MAC_VER_45:
3823 case RTL_GIGA_MAC_VER_46:
3824 case RTL_GIGA_MAC_VER_47:
3825 case RTL_GIGA_MAC_VER_48:
3826 case RTL_GIGA_MAC_VER_50:
3827 case RTL_GIGA_MAC_VER_51:
3828 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
3829 break;
3830 case RTL_GIGA_MAC_VER_40:
3831 case RTL_GIGA_MAC_VER_41:
3832 case RTL_GIGA_MAC_VER_49:
3833 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
3834 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
3835 break;
3836 default:
3837 break;
3838 }
3839 }
3840
3841 static void rtl_pll_power_up(struct rtl8169_private *tp)
3842 {
3843 switch (tp->mac_version) {
3844 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
3845 case RTL_GIGA_MAC_VER_37:
3846 case RTL_GIGA_MAC_VER_39:
3847 case RTL_GIGA_MAC_VER_43:
3848 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
3849 break;
3850 case RTL_GIGA_MAC_VER_44:
3851 case RTL_GIGA_MAC_VER_45:
3852 case RTL_GIGA_MAC_VER_46:
3853 case RTL_GIGA_MAC_VER_47:
3854 case RTL_GIGA_MAC_VER_48:
3855 case RTL_GIGA_MAC_VER_50:
3856 case RTL_GIGA_MAC_VER_51:
3857 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
3858 break;
3859 case RTL_GIGA_MAC_VER_40:
3860 case RTL_GIGA_MAC_VER_41:
3861 case RTL_GIGA_MAC_VER_49:
3862 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
3863 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
3864 break;
3865 default:
3866 break;
3867 }
3868
3869 phy_resume(tp->phydev);
3870 /* give MAC/PHY some time to resume */
3871 msleep(20);
3872 }
3873
3874 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3875 {
3876 switch (tp->mac_version) {
3877 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
3878 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
3879 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3880 break;
3881 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
3882 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
3883 case RTL_GIGA_MAC_VER_38:
3884 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3885 break;
3886 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
3887 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
3888 break;
3889 default:
3890 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
3891 break;
3892 }
3893 }
3894
3895 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3896 {
3897 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
3898 }
3899
3900 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3901 {
3902 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3903 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
3904 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
3905 }
3906
3907 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3908 {
3909 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3910 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
3911 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
3912 }
3913
3914 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3915 {
3916 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3917 }
3918
3919 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3920 {
3921 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3922 }
3923
3924 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3925 {
3926 RTL_W8(tp, MaxTxPacketSize, 0x3f);
3927 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3928 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
3929 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
3930 }
3931
3932 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3933 {
3934 RTL_W8(tp, MaxTxPacketSize, 0x0c);
3935 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3936 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
3937 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
3938 }
3939
3940 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3941 {
3942 rtl_tx_performance_tweak(tp,
3943 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
3944 }
3945
3946 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3947 {
3948 rtl_tx_performance_tweak(tp,
3949 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
3950 }
3951
3952 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3953 {
3954 r8168b_0_hw_jumbo_enable(tp);
3955
3956 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
3957 }
3958
3959 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3960 {
3961 r8168b_0_hw_jumbo_disable(tp);
3962
3963 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
3964 }
3965
3966 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3967 {
3968 rtl_unlock_config_regs(tp);
3969 switch (tp->mac_version) {
3970 case RTL_GIGA_MAC_VER_11:
3971 r8168b_0_hw_jumbo_enable(tp);
3972 break;
3973 case RTL_GIGA_MAC_VER_12:
3974 case RTL_GIGA_MAC_VER_17:
3975 r8168b_1_hw_jumbo_enable(tp);
3976 break;
3977 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
3978 r8168c_hw_jumbo_enable(tp);
3979 break;
3980 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
3981 r8168dp_hw_jumbo_enable(tp);
3982 break;
3983 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
3984 r8168e_hw_jumbo_enable(tp);
3985 break;
3986 default:
3987 break;
3988 }
3989 rtl_lock_config_regs(tp);
3990 }
3991
3992 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3993 {
3994 rtl_unlock_config_regs(tp);
3995 switch (tp->mac_version) {
3996 case RTL_GIGA_MAC_VER_11:
3997 r8168b_0_hw_jumbo_disable(tp);
3998 break;
3999 case RTL_GIGA_MAC_VER_12:
4000 case RTL_GIGA_MAC_VER_17:
4001 r8168b_1_hw_jumbo_disable(tp);
4002 break;
4003 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
4004 r8168c_hw_jumbo_disable(tp);
4005 break;
4006 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
4007 r8168dp_hw_jumbo_disable(tp);
4008 break;
4009 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
4010 r8168e_hw_jumbo_disable(tp);
4011 break;
4012 default:
4013 break;
4014 }
4015 rtl_lock_config_regs(tp);
4016 }
4017
4018 DECLARE_RTL_COND(rtl_chipcmd_cond)
4019 {
4020 return RTL_R8(tp, ChipCmd) & CmdReset;
4021 }
4022
4023 static void rtl_hw_reset(struct rtl8169_private *tp)
4024 {
4025 RTL_W8(tp, ChipCmd, CmdReset);
4026
4027 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4028 }
4029
4030 static void rtl_request_firmware(struct rtl8169_private *tp)
4031 {
4032 struct rtl_fw *rtl_fw;
4033
4034 /* firmware loaded already or no firmware available */
4035 if (tp->rtl_fw || !tp->fw_name)
4036 return;
4037
4038 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4039 if (!rtl_fw) {
4040 netif_warn(tp, ifup, tp->dev, "Unable to load firmware, out of memory\n");
4041 return;
4042 }
4043
4044 rtl_fw->phy_write = rtl_writephy;
4045 rtl_fw->phy_read = rtl_readphy;
4046 rtl_fw->mac_mcu_write = mac_mcu_write;
4047 rtl_fw->mac_mcu_read = mac_mcu_read;
4048 rtl_fw->fw_name = tp->fw_name;
4049 rtl_fw->dev = tp_to_dev(tp);
4050
4051 if (rtl_fw_request_firmware(rtl_fw))
4052 kfree(rtl_fw);
4053 else
4054 tp->rtl_fw = rtl_fw;
4055 }
4056
4057 static void rtl_rx_close(struct rtl8169_private *tp)
4058 {
4059 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4060 }
4061
4062 DECLARE_RTL_COND(rtl_npq_cond)
4063 {
4064 return RTL_R8(tp, TxPoll) & NPQ;
4065 }
4066
4067 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4068 {
4069 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4070 }
4071
4072 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4073 {
4074 /* Disable interrupts */
4075 rtl8169_irq_mask_and_ack(tp);
4076
4077 rtl_rx_close(tp);
4078
4079 switch (tp->mac_version) {
4080 case RTL_GIGA_MAC_VER_27:
4081 case RTL_GIGA_MAC_VER_28:
4082 case RTL_GIGA_MAC_VER_31:
4083 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4084 break;
4085 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4086 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4087 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4088 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4089 break;
4090 default:
4091 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4092 udelay(100);
4093 break;
4094 }
4095
4096 rtl_hw_reset(tp);
4097 }
4098
4099 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4100 {
4101 u32 val = TX_DMA_BURST << TxDMAShift |
4102 InterFrameGap << TxInterFrameGapShift;
4103
4104 if (rtl_is_8168evl_up(tp))
4105 val |= TXCFG_AUTO_FIFO;
4106
4107 RTL_W32(tp, TxConfig, val);
4108 }
4109
4110 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4111 {
4112 /* Low hurts. Let's disable the filtering. */
4113 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4114 }
4115
4116 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4117 {
4118 /*
4119 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4120 * register to be written before TxDescAddrLow to work.
4121 * Switching from MMIO to I/O access fixes the issue as well.
4122 */
4123 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4124 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4125 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4126 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4127 }
4128
4129 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4130 {
4131 u32 val;
4132
4133 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4134 val = 0x000fff00;
4135 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4136 val = 0x00ffff00;
4137 else
4138 return;
4139
4140 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4141 val |= 0xff;
4142
4143 RTL_W32(tp, 0x7c, val);
4144 }
4145
4146 static void rtl_set_rx_mode(struct net_device *dev)
4147 {
4148 struct rtl8169_private *tp = netdev_priv(dev);
4149 u32 mc_filter[2]; /* Multicast hash filter */
4150 int rx_mode;
4151 u32 tmp = 0;
4152
4153 if (dev->flags & IFF_PROMISC) {
4154 /* Unconditionally log net taps. */
4155 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4156 rx_mode =
4157 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4158 AcceptAllPhys;
4159 mc_filter[1] = mc_filter[0] = 0xffffffff;
4160 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4161 (dev->flags & IFF_ALLMULTI)) {
4162 /* Too many to filter perfectly -- accept all multicasts. */
4163 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4164 mc_filter[1] = mc_filter[0] = 0xffffffff;
4165 } else {
4166 struct netdev_hw_addr *ha;
4167
4168 rx_mode = AcceptBroadcast | AcceptMyPhys;
4169 mc_filter[1] = mc_filter[0] = 0;
4170 netdev_for_each_mc_addr(ha, dev) {
4171 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4172 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4173 rx_mode |= AcceptMulticast;
4174 }
4175 }
4176
4177 if (dev->features & NETIF_F_RXALL)
4178 rx_mode |= (AcceptErr | AcceptRunt);
4179
4180 tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4181
4182 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4183 u32 data = mc_filter[0];
4184
4185 mc_filter[0] = swab32(mc_filter[1]);
4186 mc_filter[1] = swab32(data);
4187 }
4188
4189 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4190 mc_filter[1] = mc_filter[0] = 0xffffffff;
4191
4192 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4193 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4194
4195 RTL_W32(tp, RxConfig, tmp);
4196 }
4197
4198 DECLARE_RTL_COND(rtl_csiar_cond)
4199 {
4200 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4201 }
4202
4203 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4204 {
4205 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4206
4207 RTL_W32(tp, CSIDR, value);
4208 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4209 CSIAR_BYTE_ENABLE | func << 16);
4210
4211 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4212 }
4213
4214 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4215 {
4216 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4217
4218 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4219 CSIAR_BYTE_ENABLE);
4220
4221 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4222 RTL_R32(tp, CSIDR) : ~0;
4223 }
4224
4225 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4226 {
4227 struct pci_dev *pdev = tp->pci_dev;
4228 u32 csi;
4229
4230 /* According to Realtek the value at config space address 0x070f
4231 * controls the L0s/L1 entrance latency. We try standard ECAM access
4232 * first and if it fails fall back to CSI.
4233 */
4234 if (pdev->cfg_size > 0x070f &&
4235 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4236 return;
4237
4238 netdev_notice_once(tp->dev,
4239 "No native access to PCI extended config space, falling back to CSI\n");
4240 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4241 rtl_csi_write(tp, 0x070c, csi | val << 24);
4242 }
4243
4244 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4245 {
4246 rtl_csi_access_enable(tp, 0x27);
4247 }
4248
4249 struct ephy_info {
4250 unsigned int offset;
4251 u16 mask;
4252 u16 bits;
4253 };
4254
4255 static void __rtl_ephy_init(struct rtl8169_private *tp,
4256 const struct ephy_info *e, int len)
4257 {
4258 u16 w;
4259
4260 while (len-- > 0) {
4261 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4262 rtl_ephy_write(tp, e->offset, w);
4263 e++;
4264 }
4265 }
4266
4267 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
4268
4269 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4270 {
4271 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4272 PCI_EXP_LNKCTL_CLKREQ_EN);
4273 }
4274
4275 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4276 {
4277 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4278 PCI_EXP_LNKCTL_CLKREQ_EN);
4279 }
4280
4281 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
4282 {
4283 /* work around an issue when PCI reset occurs during L2/L3 state */
4284 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
4285 }
4286
4287 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4288 {
4289 if (enable) {
4290 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4291 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4292 } else {
4293 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4294 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4295 }
4296
4297 udelay(10);
4298 }
4299
4300 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
4301 u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
4302 {
4303 /* Usage of dynamic vs. static FIFO is controlled by bit
4304 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
4305 */
4306 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
4307 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
4308 }
4309
4310 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
4311 u8 low, u8 high)
4312 {
4313 /* FIFO thresholds for pause flow control */
4314 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
4315 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
4316 }
4317
4318 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4319 {
4320 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4321
4322 if (tp->dev->mtu <= ETH_DATA_LEN) {
4323 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4324 PCI_EXP_DEVCTL_NOSNOOP_EN);
4325 }
4326 }
4327
4328 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4329 {
4330 rtl_hw_start_8168bb(tp);
4331
4332 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4333 }
4334
4335 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4336 {
4337 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4338
4339 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4340
4341 if (tp->dev->mtu <= ETH_DATA_LEN)
4342 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4343
4344 rtl_disable_clock_request(tp);
4345 }
4346
4347 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4348 {
4349 static const struct ephy_info e_info_8168cp[] = {
4350 { 0x01, 0, 0x0001 },
4351 { 0x02, 0x0800, 0x1000 },
4352 { 0x03, 0, 0x0042 },
4353 { 0x06, 0x0080, 0x0000 },
4354 { 0x07, 0, 0x2000 }
4355 };
4356
4357 rtl_set_def_aspm_entry_latency(tp);
4358
4359 rtl_ephy_init(tp, e_info_8168cp);
4360
4361 __rtl_hw_start_8168cp(tp);
4362 }
4363
4364 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4365 {
4366 rtl_set_def_aspm_entry_latency(tp);
4367
4368 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4369
4370 if (tp->dev->mtu <= ETH_DATA_LEN)
4371 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4372 }
4373
4374 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4375 {
4376 rtl_set_def_aspm_entry_latency(tp);
4377
4378 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4379
4380 /* Magic. */
4381 RTL_W8(tp, DBG_REG, 0x20);
4382
4383 if (tp->dev->mtu <= ETH_DATA_LEN)
4384 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4385 }
4386
4387 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4388 {
4389 static const struct ephy_info e_info_8168c_1[] = {
4390 { 0x02, 0x0800, 0x1000 },
4391 { 0x03, 0, 0x0002 },
4392 { 0x06, 0x0080, 0x0000 }
4393 };
4394
4395 rtl_set_def_aspm_entry_latency(tp);
4396
4397 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4398
4399 rtl_ephy_init(tp, e_info_8168c_1);
4400
4401 __rtl_hw_start_8168cp(tp);
4402 }
4403
4404 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4405 {
4406 static const struct ephy_info e_info_8168c_2[] = {
4407 { 0x01, 0, 0x0001 },
4408 { 0x03, 0x0400, 0x0220 }
4409 };
4410
4411 rtl_set_def_aspm_entry_latency(tp);
4412
4413 rtl_ephy_init(tp, e_info_8168c_2);
4414
4415 __rtl_hw_start_8168cp(tp);
4416 }
4417
4418 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4419 {
4420 rtl_hw_start_8168c_2(tp);
4421 }
4422
4423 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4424 {
4425 rtl_set_def_aspm_entry_latency(tp);
4426
4427 __rtl_hw_start_8168cp(tp);
4428 }
4429
4430 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4431 {
4432 rtl_set_def_aspm_entry_latency(tp);
4433
4434 rtl_disable_clock_request(tp);
4435
4436 if (tp->dev->mtu <= ETH_DATA_LEN)
4437 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4438 }
4439
4440 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4441 {
4442 rtl_set_def_aspm_entry_latency(tp);
4443
4444 if (tp->dev->mtu <= ETH_DATA_LEN)
4445 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4446
4447 rtl_disable_clock_request(tp);
4448 }
4449
4450 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4451 {
4452 static const struct ephy_info e_info_8168d_4[] = {
4453 { 0x0b, 0x0000, 0x0048 },
4454 { 0x19, 0x0020, 0x0050 },
4455 { 0x0c, 0x0100, 0x0020 }
4456 };
4457
4458 rtl_set_def_aspm_entry_latency(tp);
4459
4460 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4461
4462 rtl_ephy_init(tp, e_info_8168d_4);
4463
4464 rtl_enable_clock_request(tp);
4465 }
4466
4467 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4468 {
4469 static const struct ephy_info e_info_8168e_1[] = {
4470 { 0x00, 0x0200, 0x0100 },
4471 { 0x00, 0x0000, 0x0004 },
4472 { 0x06, 0x0002, 0x0001 },
4473 { 0x06, 0x0000, 0x0030 },
4474 { 0x07, 0x0000, 0x2000 },
4475 { 0x00, 0x0000, 0x0020 },
4476 { 0x03, 0x5800, 0x2000 },
4477 { 0x03, 0x0000, 0x0001 },
4478 { 0x01, 0x0800, 0x1000 },
4479 { 0x07, 0x0000, 0x4000 },
4480 { 0x1e, 0x0000, 0x2000 },
4481 { 0x19, 0xffff, 0xfe6c },
4482 { 0x0a, 0x0000, 0x0040 }
4483 };
4484
4485 rtl_set_def_aspm_entry_latency(tp);
4486
4487 rtl_ephy_init(tp, e_info_8168e_1);
4488
4489 if (tp->dev->mtu <= ETH_DATA_LEN)
4490 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4491
4492 rtl_disable_clock_request(tp);
4493
4494 /* Reset tx FIFO pointer */
4495 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4496 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4497
4498 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4499 }
4500
4501 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4502 {
4503 static const struct ephy_info e_info_8168e_2[] = {
4504 { 0x09, 0x0000, 0x0080 },
4505 { 0x19, 0x0000, 0x0224 }
4506 };
4507
4508 rtl_set_def_aspm_entry_latency(tp);
4509
4510 rtl_ephy_init(tp, e_info_8168e_2);
4511
4512 if (tp->dev->mtu <= ETH_DATA_LEN)
4513 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4514
4515 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4516 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4517 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4518 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4519 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
4520 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4521 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4522
4523 rtl_disable_clock_request(tp);
4524
4525 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4526
4527 rtl8168_config_eee_mac(tp);
4528
4529 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4530 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4531 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4532
4533 rtl_hw_aspm_clkreq_enable(tp, true);
4534 }
4535
4536 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
4537 {
4538 rtl_set_def_aspm_entry_latency(tp);
4539
4540 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4541
4542 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4543 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4544 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4545 rtl_reset_packet_filter(tp);
4546 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4547 rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));
4548 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4549 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
4550
4551 rtl_disable_clock_request(tp);
4552
4553 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4554 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4555 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4556 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4557
4558 rtl8168_config_eee_mac(tp);
4559 }
4560
4561 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
4562 {
4563 static const struct ephy_info e_info_8168f_1[] = {
4564 { 0x06, 0x00c0, 0x0020 },
4565 { 0x08, 0x0001, 0x0002 },
4566 { 0x09, 0x0000, 0x0080 },
4567 { 0x19, 0x0000, 0x0224 }
4568 };
4569
4570 rtl_hw_start_8168f(tp);
4571
4572 rtl_ephy_init(tp, e_info_8168f_1);
4573
4574 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4575 }
4576
4577 static void rtl_hw_start_8411(struct rtl8169_private *tp)
4578 {
4579 static const struct ephy_info e_info_8168f_1[] = {
4580 { 0x06, 0x00c0, 0x0020 },
4581 { 0x0f, 0xffff, 0x5200 },
4582 { 0x1e, 0x0000, 0x4000 },
4583 { 0x19, 0x0000, 0x0224 }
4584 };
4585
4586 rtl_hw_start_8168f(tp);
4587 rtl_pcie_state_l2l3_disable(tp);
4588
4589 rtl_ephy_init(tp, e_info_8168f_1);
4590
4591 rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);
4592 }
4593
4594 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
4595 {
4596 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4597 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4598
4599 rtl_set_def_aspm_entry_latency(tp);
4600
4601 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4602
4603 rtl_reset_packet_filter(tp);
4604 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
4605
4606 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4607
4608 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4609 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4610
4611 rtl8168_config_eee_mac(tp);
4612
4613 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
4614 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4615
4616 rtl_pcie_state_l2l3_disable(tp);
4617 }
4618
4619 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
4620 {
4621 static const struct ephy_info e_info_8168g_1[] = {
4622 { 0x00, 0x0000, 0x0008 },
4623 { 0x0c, 0x37d0, 0x0820 },
4624 { 0x1e, 0x0000, 0x0001 },
4625 { 0x19, 0x8000, 0x0000 }
4626 };
4627
4628 rtl_hw_start_8168g(tp);
4629
4630 /* disable aspm and clock request before access ephy */
4631 rtl_hw_aspm_clkreq_enable(tp, false);
4632 rtl_ephy_init(tp, e_info_8168g_1);
4633 rtl_hw_aspm_clkreq_enable(tp, true);
4634 }
4635
4636 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
4637 {
4638 static const struct ephy_info e_info_8168g_2[] = {
4639 { 0x00, 0x0000, 0x0008 },
4640 { 0x0c, 0x3df0, 0x0200 },
4641 { 0x19, 0xffff, 0xfc00 },
4642 { 0x1e, 0xffff, 0x20eb }
4643 };
4644
4645 rtl_hw_start_8168g(tp);
4646
4647 /* disable aspm and clock request before access ephy */
4648 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4649 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4650 rtl_ephy_init(tp, e_info_8168g_2);
4651 }
4652
4653 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
4654 {
4655 static const struct ephy_info e_info_8411_2[] = {
4656 { 0x00, 0x0000, 0x0008 },
4657 { 0x0c, 0x3df0, 0x0200 },
4658 { 0x0f, 0xffff, 0x5200 },
4659 { 0x19, 0x0020, 0x0000 },
4660 { 0x1e, 0x0000, 0x2000 }
4661 };
4662
4663 rtl_hw_start_8168g(tp);
4664
4665 /* disable aspm and clock request before access ephy */
4666 rtl_hw_aspm_clkreq_enable(tp, false);
4667 rtl_ephy_init(tp, e_info_8411_2);
4668 rtl_hw_aspm_clkreq_enable(tp, true);
4669 }
4670
4671 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
4672 {
4673 int rg_saw_cnt;
4674 u32 data;
4675 static const struct ephy_info e_info_8168h_1[] = {
4676 { 0x1e, 0x0800, 0x0001 },
4677 { 0x1d, 0x0000, 0x0800 },
4678 { 0x05, 0xffff, 0x2089 },
4679 { 0x06, 0xffff, 0x5881 },
4680 { 0x04, 0xffff, 0x154a },
4681 { 0x01, 0xffff, 0x068b }
4682 };
4683
4684 /* disable aspm and clock request before access ephy */
4685 rtl_hw_aspm_clkreq_enable(tp, false);
4686 rtl_ephy_init(tp, e_info_8168h_1);
4687
4688 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4689 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4690
4691 rtl_set_def_aspm_entry_latency(tp);
4692
4693 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4694
4695 rtl_reset_packet_filter(tp);
4696
4697 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
4698
4699 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);
4700
4701 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
4702
4703 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4704
4705 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4706 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4707
4708 rtl8168_config_eee_mac(tp);
4709
4710 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4711 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4712
4713 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
4714
4715 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4716
4717 rtl_pcie_state_l2l3_disable(tp);
4718
4719 rtl_writephy(tp, 0x1f, 0x0c42);
4720 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
4721 rtl_writephy(tp, 0x1f, 0x0000);
4722 if (rg_saw_cnt > 0) {
4723 u16 sw_cnt_1ms_ini;
4724
4725 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
4726 sw_cnt_1ms_ini &= 0x0fff;
4727 data = r8168_mac_ocp_read(tp, 0xd412);
4728 data &= ~0x0fff;
4729 data |= sw_cnt_1ms_ini;
4730 r8168_mac_ocp_write(tp, 0xd412, data);
4731 }
4732
4733 data = r8168_mac_ocp_read(tp, 0xe056);
4734 data &= ~0xf0;
4735 data |= 0x70;
4736 r8168_mac_ocp_write(tp, 0xe056, data);
4737
4738 data = r8168_mac_ocp_read(tp, 0xe052);
4739 data &= ~0x6000;
4740 data |= 0x8008;
4741 r8168_mac_ocp_write(tp, 0xe052, data);
4742
4743 data = r8168_mac_ocp_read(tp, 0xe0d6);
4744 data &= ~0x01ff;
4745 data |= 0x017f;
4746 r8168_mac_ocp_write(tp, 0xe0d6, data);
4747
4748 data = r8168_mac_ocp_read(tp, 0xd420);
4749 data &= ~0x0fff;
4750 data |= 0x047f;
4751 r8168_mac_ocp_write(tp, 0xd420, data);
4752
4753 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
4754 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
4755 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
4756 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
4757
4758 rtl_hw_aspm_clkreq_enable(tp, true);
4759 }
4760
4761 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
4762 {
4763 rtl8168ep_stop_cmac(tp);
4764
4765 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4766 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
4767
4768 rtl_set_def_aspm_entry_latency(tp);
4769
4770 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4771
4772 rtl_reset_packet_filter(tp);
4773
4774 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
4775
4776 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
4777
4778 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4779
4780 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4781 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4782
4783 rtl8168_config_eee_mac(tp);
4784
4785 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
4786
4787 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
4788
4789 rtl_pcie_state_l2l3_disable(tp);
4790 }
4791
4792 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
4793 {
4794 static const struct ephy_info e_info_8168ep_1[] = {
4795 { 0x00, 0xffff, 0x10ab },
4796 { 0x06, 0xffff, 0xf030 },
4797 { 0x08, 0xffff, 0x2006 },
4798 { 0x0d, 0xffff, 0x1666 },
4799 { 0x0c, 0x3ff0, 0x0000 }
4800 };
4801
4802 /* disable aspm and clock request before access ephy */
4803 rtl_hw_aspm_clkreq_enable(tp, false);
4804 rtl_ephy_init(tp, e_info_8168ep_1);
4805
4806 rtl_hw_start_8168ep(tp);
4807
4808 rtl_hw_aspm_clkreq_enable(tp, true);
4809 }
4810
4811 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
4812 {
4813 static const struct ephy_info e_info_8168ep_2[] = {
4814 { 0x00, 0xffff, 0x10a3 },
4815 { 0x19, 0xffff, 0xfc00 },
4816 { 0x1e, 0xffff, 0x20ea }
4817 };
4818
4819 /* disable aspm and clock request before access ephy */
4820 rtl_hw_aspm_clkreq_enable(tp, false);
4821 rtl_ephy_init(tp, e_info_8168ep_2);
4822
4823 rtl_hw_start_8168ep(tp);
4824
4825 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4826 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4827
4828 rtl_hw_aspm_clkreq_enable(tp, true);
4829 }
4830
4831 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
4832 {
4833 u32 data;
4834 static const struct ephy_info e_info_8168ep_3[] = {
4835 { 0x00, 0xffff, 0x10a3 },
4836 { 0x19, 0xffff, 0x7c00 },
4837 { 0x1e, 0xffff, 0x20eb },
4838 { 0x0d, 0xffff, 0x1666 }
4839 };
4840
4841 /* disable aspm and clock request before access ephy */
4842 rtl_hw_aspm_clkreq_enable(tp, false);
4843 rtl_ephy_init(tp, e_info_8168ep_3);
4844
4845 rtl_hw_start_8168ep(tp);
4846
4847 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4848 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4849
4850 data = r8168_mac_ocp_read(tp, 0xd3e2);
4851 data &= 0xf000;
4852 data |= 0x0271;
4853 r8168_mac_ocp_write(tp, 0xd3e2, data);
4854
4855 data = r8168_mac_ocp_read(tp, 0xd3e4);
4856 data &= 0xff00;
4857 r8168_mac_ocp_write(tp, 0xd3e4, data);
4858
4859 data = r8168_mac_ocp_read(tp, 0xe860);
4860 data |= 0x0080;
4861 r8168_mac_ocp_write(tp, 0xe860, data);
4862
4863 rtl_hw_aspm_clkreq_enable(tp, true);
4864 }
4865
4866 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
4867 {
4868 static const struct ephy_info e_info_8102e_1[] = {
4869 { 0x01, 0, 0x6e65 },
4870 { 0x02, 0, 0x091f },
4871 { 0x03, 0, 0xc2f9 },
4872 { 0x06, 0, 0xafb5 },
4873 { 0x07, 0, 0x0e00 },
4874 { 0x19, 0, 0xec80 },
4875 { 0x01, 0, 0x2e65 },
4876 { 0x01, 0, 0x6e65 }
4877 };
4878 u8 cfg1;
4879
4880 rtl_set_def_aspm_entry_latency(tp);
4881
4882 RTL_W8(tp, DBG_REG, FIX_NAK_1);
4883
4884 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4885
4886 RTL_W8(tp, Config1,
4887 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4888 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4889
4890 cfg1 = RTL_R8(tp, Config1);
4891 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4892 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
4893
4894 rtl_ephy_init(tp, e_info_8102e_1);
4895 }
4896
4897 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
4898 {
4899 rtl_set_def_aspm_entry_latency(tp);
4900
4901 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4902
4903 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
4904 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4905 }
4906
4907 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
4908 {
4909 rtl_hw_start_8102e_2(tp);
4910
4911 rtl_ephy_write(tp, 0x03, 0xc2f9);
4912 }
4913
4914 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
4915 {
4916 static const struct ephy_info e_info_8105e_1[] = {
4917 { 0x07, 0, 0x4000 },
4918 { 0x19, 0, 0x0200 },
4919 { 0x19, 0, 0x0020 },
4920 { 0x1e, 0, 0x2000 },
4921 { 0x03, 0, 0x0001 },
4922 { 0x19, 0, 0x0100 },
4923 { 0x19, 0, 0x0004 },
4924 { 0x0a, 0, 0x0020 }
4925 };
4926
4927 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4928 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
4929
4930 /* Disable Early Tally Counter */
4931 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
4932
4933 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
4934 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4935
4936 rtl_ephy_init(tp, e_info_8105e_1);
4937
4938 rtl_pcie_state_l2l3_disable(tp);
4939 }
4940
4941 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
4942 {
4943 rtl_hw_start_8105e_1(tp);
4944 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
4945 }
4946
4947 static void rtl_hw_start_8402(struct rtl8169_private *tp)
4948 {
4949 static const struct ephy_info e_info_8402[] = {
4950 { 0x19, 0xffff, 0xff64 },
4951 { 0x1e, 0, 0x4000 }
4952 };
4953
4954 rtl_set_def_aspm_entry_latency(tp);
4955
4956 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4957 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
4958
4959 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4960
4961 rtl_ephy_init(tp, e_info_8402);
4962
4963 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4964
4965 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
4966 rtl_reset_packet_filter(tp);
4967 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4968 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4969 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
4970
4971 rtl_pcie_state_l2l3_disable(tp);
4972 }
4973
4974 static void rtl_hw_start_8106(struct rtl8169_private *tp)
4975 {
4976 rtl_hw_aspm_clkreq_enable(tp, false);
4977
4978 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4979 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
4980
4981 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
4982 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
4983 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4984
4985 rtl_pcie_state_l2l3_disable(tp);
4986 rtl_hw_aspm_clkreq_enable(tp, true);
4987 }
4988
4989 static void rtl_hw_config(struct rtl8169_private *tp)
4990 {
4991 static const rtl_generic_fct hw_configs[] = {
4992 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
4993 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
4994 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
4995 [RTL_GIGA_MAC_VER_10] = NULL,
4996 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168bb,
4997 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168bef,
4998 [RTL_GIGA_MAC_VER_13] = NULL,
4999 [RTL_GIGA_MAC_VER_14] = NULL,
5000 [RTL_GIGA_MAC_VER_15] = NULL,
5001 [RTL_GIGA_MAC_VER_16] = NULL,
5002 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168bef,
5003 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
5004 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
5005 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
5006 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
5007 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
5008 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
5009 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
5010 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
5011 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
5012 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
5013 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
5014 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
5015 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
5016 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168dp,
5017 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
5018 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
5019 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
5020 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
5021 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
5022 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
5023 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
5024 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
5025 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
5026 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
5027 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
5028 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
5029 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
5030 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
5031 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
5032 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
5033 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
5034 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
5035 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
5036 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
5037 };
5038
5039 if (hw_configs[tp->mac_version])
5040 hw_configs[tp->mac_version](tp);
5041 }
5042
5043 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5044 {
5045 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5046 tp->mac_version == RTL_GIGA_MAC_VER_16)
5047 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5048 PCI_EXP_DEVCTL_NOSNOOP_EN);
5049
5050 if (rtl_is_8168evl_up(tp))
5051 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5052 else
5053 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5054
5055 rtl_hw_config(tp);
5056 }
5057
5058 static void rtl_hw_start_8169(struct rtl8169_private *tp)
5059 {
5060 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5061 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
5062
5063 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
5064
5065 tp->cp_cmd |= PCIMulRW;
5066
5067 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5068 tp->mac_version == RTL_GIGA_MAC_VER_03) {
5069 netif_dbg(tp, drv, tp->dev,
5070 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
5071 tp->cp_cmd |= (1 << 14);
5072 }
5073
5074 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5075
5076 rtl8169_set_magic_reg(tp, tp->mac_version);
5077
5078 RTL_W32(tp, RxMissed, 0);
5079 }
5080
5081 static void rtl_hw_start(struct rtl8169_private *tp)
5082 {
5083 rtl_unlock_config_regs(tp);
5084
5085 tp->cp_cmd &= CPCMD_MASK;
5086 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5087
5088 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5089 rtl_hw_start_8169(tp);
5090 else
5091 rtl_hw_start_8168(tp);
5092
5093 rtl_set_rx_max_size(tp);
5094 rtl_set_rx_tx_desc_registers(tp);
5095 rtl_lock_config_regs(tp);
5096
5097 /* disable interrupt coalescing */
5098 RTL_W16(tp, IntrMitigate, 0x0000);
5099 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5100 RTL_R8(tp, IntrMask);
5101 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
5102 rtl_init_rxcfg(tp);
5103 rtl_set_tx_config_registers(tp);
5104
5105 rtl_set_rx_mode(tp->dev);
5106 /* no early-rx interrupts */
5107 RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
5108 rtl_irq_enable(tp);
5109 }
5110
5111 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5112 {
5113 struct rtl8169_private *tp = netdev_priv(dev);
5114
5115 if (new_mtu > ETH_DATA_LEN)
5116 rtl_hw_jumbo_enable(tp);
5117 else
5118 rtl_hw_jumbo_disable(tp);
5119
5120 dev->mtu = new_mtu;
5121 netdev_update_features(dev);
5122
5123 return 0;
5124 }
5125
5126 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5127 {
5128 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5129 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5130 }
5131
5132 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5133 void **data_buff, struct RxDesc *desc)
5134 {
5135 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5136 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5137
5138 kfree(*data_buff);
5139 *data_buff = NULL;
5140 rtl8169_make_unusable_by_asic(desc);
5141 }
5142
5143 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5144 {
5145 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5146
5147 /* Force memory writes to complete before releasing descriptor */
5148 dma_wmb();
5149
5150 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5151 }
5152
5153 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5154 struct RxDesc *desc)
5155 {
5156 void *data;
5157 dma_addr_t mapping;
5158 struct device *d = tp_to_dev(tp);
5159 int node = dev_to_node(d);
5160
5161 data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5162 if (!data)
5163 return NULL;
5164
5165 /* Memory should be properly aligned, but better check. */
5166 if (!IS_ALIGNED((unsigned long)data, 8)) {
5167 netdev_err_once(tp->dev, "RX buffer not 8-byte-aligned\n");
5168 goto err_out;
5169 }
5170
5171 mapping = dma_map_single(d, data, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5172 if (unlikely(dma_mapping_error(d, mapping))) {
5173 if (net_ratelimit())
5174 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5175 goto err_out;
5176 }
5177
5178 desc->addr = cpu_to_le64(mapping);
5179 rtl8169_mark_to_asic(desc);
5180 return data;
5181
5182 err_out:
5183 kfree(data);
5184 return NULL;
5185 }
5186
5187 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5188 {
5189 unsigned int i;
5190
5191 for (i = 0; i < NUM_RX_DESC; i++) {
5192 if (tp->Rx_databuff[i]) {
5193 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5194 tp->RxDescArray + i);
5195 }
5196 }
5197 }
5198
5199 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5200 {
5201 desc->opts1 |= cpu_to_le32(RingEnd);
5202 }
5203
5204 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5205 {
5206 unsigned int i;
5207
5208 for (i = 0; i < NUM_RX_DESC; i++) {
5209 void *data;
5210
5211 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5212 if (!data) {
5213 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5214 goto err_out;
5215 }
5216 tp->Rx_databuff[i] = data;
5217 }
5218
5219 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5220 return 0;
5221
5222 err_out:
5223 rtl8169_rx_clear(tp);
5224 return -ENOMEM;
5225 }
5226
5227 static int rtl8169_init_ring(struct rtl8169_private *tp)
5228 {
5229 rtl8169_init_ring_indexes(tp);
5230
5231 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5232 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5233
5234 return rtl8169_rx_fill(tp);
5235 }
5236
5237 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5238 struct TxDesc *desc)
5239 {
5240 unsigned int len = tx_skb->len;
5241
5242 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5243
5244 desc->opts1 = 0x00;
5245 desc->opts2 = 0x00;
5246 desc->addr = 0x00;
5247 tx_skb->len = 0;
5248 }
5249
5250 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5251 unsigned int n)
5252 {
5253 unsigned int i;
5254
5255 for (i = 0; i < n; i++) {
5256 unsigned int entry = (start + i) % NUM_TX_DESC;
5257 struct ring_info *tx_skb = tp->tx_skb + entry;
5258 unsigned int len = tx_skb->len;
5259
5260 if (len) {
5261 struct sk_buff *skb = tx_skb->skb;
5262
5263 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5264 tp->TxDescArray + entry);
5265 if (skb) {
5266 dev_consume_skb_any(skb);
5267 tx_skb->skb = NULL;
5268 }
5269 }
5270 }
5271 }
5272
5273 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5274 {
5275 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5276 tp->cur_tx = tp->dirty_tx = 0;
5277 netdev_reset_queue(tp->dev);
5278 }
5279
5280 static void rtl_reset_work(struct rtl8169_private *tp)
5281 {
5282 struct net_device *dev = tp->dev;
5283 int i;
5284
5285 napi_disable(&tp->napi);
5286 netif_stop_queue(dev);
5287 synchronize_rcu();
5288
5289 rtl8169_hw_reset(tp);
5290
5291 for (i = 0; i < NUM_RX_DESC; i++)
5292 rtl8169_mark_to_asic(tp->RxDescArray + i);
5293
5294 rtl8169_tx_clear(tp);
5295 rtl8169_init_ring_indexes(tp);
5296
5297 napi_enable(&tp->napi);
5298 rtl_hw_start(tp);
5299 netif_wake_queue(dev);
5300 }
5301
5302 static void rtl8169_tx_timeout(struct net_device *dev)
5303 {
5304 struct rtl8169_private *tp = netdev_priv(dev);
5305
5306 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5307 }
5308
5309 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5310 {
5311 u32 status = opts0 | len;
5312
5313 if (entry == NUM_TX_DESC - 1)
5314 status |= RingEnd;
5315
5316 return cpu_to_le32(status);
5317 }
5318
5319 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5320 u32 *opts)
5321 {
5322 struct skb_shared_info *info = skb_shinfo(skb);
5323 unsigned int cur_frag, entry;
5324 struct TxDesc *uninitialized_var(txd);
5325 struct device *d = tp_to_dev(tp);
5326
5327 entry = tp->cur_tx;
5328 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5329 const skb_frag_t *frag = info->frags + cur_frag;
5330 dma_addr_t mapping;
5331 u32 len;
5332 void *addr;
5333
5334 entry = (entry + 1) % NUM_TX_DESC;
5335
5336 txd = tp->TxDescArray + entry;
5337 len = skb_frag_size(frag);
5338 addr = skb_frag_address(frag);
5339 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5340 if (unlikely(dma_mapping_error(d, mapping))) {
5341 if (net_ratelimit())
5342 netif_err(tp, drv, tp->dev,
5343 "Failed to map TX fragments DMA!\n");
5344 goto err_out;
5345 }
5346
5347 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5348 txd->opts2 = cpu_to_le32(opts[1]);
5349 txd->addr = cpu_to_le64(mapping);
5350
5351 tp->tx_skb[entry].len = len;
5352 }
5353
5354 if (cur_frag) {
5355 tp->tx_skb[entry].skb = skb;
5356 txd->opts1 |= cpu_to_le32(LastFrag);
5357 }
5358
5359 return cur_frag;
5360
5361 err_out:
5362 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5363 return -EIO;
5364 }
5365
5366 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5367 {
5368 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5369 }
5370
5371 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5372 struct net_device *dev);
5373 /* r8169_csum_workaround()
5374 * The hw limites the value the transport offset. When the offset is out of the
5375 * range, calculate the checksum by sw.
5376 */
5377 static void r8169_csum_workaround(struct rtl8169_private *tp,
5378 struct sk_buff *skb)
5379 {
5380 if (skb_is_gso(skb)) {
5381 netdev_features_t features = tp->dev->features;
5382 struct sk_buff *segs, *nskb;
5383
5384 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5385 segs = skb_gso_segment(skb, features);
5386 if (IS_ERR(segs) || !segs)
5387 goto drop;
5388
5389 do {
5390 nskb = segs;
5391 segs = segs->next;
5392 nskb->next = NULL;
5393 rtl8169_start_xmit(nskb, tp->dev);
5394 } while (segs);
5395
5396 dev_consume_skb_any(skb);
5397 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5398 if (skb_checksum_help(skb) < 0)
5399 goto drop;
5400
5401 rtl8169_start_xmit(skb, tp->dev);
5402 } else {
5403 drop:
5404 tp->dev->stats.tx_dropped++;
5405 dev_kfree_skb_any(skb);
5406 }
5407 }
5408
5409 /* msdn_giant_send_check()
5410 * According to the document of microsoft, the TCP Pseudo Header excludes the
5411 * packet length for IPv6 TCP large packets.
5412 */
5413 static int msdn_giant_send_check(struct sk_buff *skb)
5414 {
5415 const struct ipv6hdr *ipv6h;
5416 struct tcphdr *th;
5417 int ret;
5418
5419 ret = skb_cow_head(skb, 0);
5420 if (ret)
5421 return ret;
5422
5423 ipv6h = ipv6_hdr(skb);
5424 th = tcp_hdr(skb);
5425
5426 th->check = 0;
5427 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5428
5429 return ret;
5430 }
5431
5432 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
5433 {
5434 u32 mss = skb_shinfo(skb)->gso_size;
5435
5436 if (mss) {
5437 opts[0] |= TD_LSO;
5438 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5439 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5440 const struct iphdr *ip = ip_hdr(skb);
5441
5442 if (ip->protocol == IPPROTO_TCP)
5443 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5444 else if (ip->protocol == IPPROTO_UDP)
5445 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5446 else
5447 WARN_ON_ONCE(1);
5448 }
5449 }
5450
5451 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5452 struct sk_buff *skb, u32 *opts)
5453 {
5454 u32 transport_offset = (u32)skb_transport_offset(skb);
5455 u32 mss = skb_shinfo(skb)->gso_size;
5456
5457 if (mss) {
5458 if (transport_offset > GTTCPHO_MAX) {
5459 netif_warn(tp, tx_err, tp->dev,
5460 "Invalid transport offset 0x%x for TSO\n",
5461 transport_offset);
5462 return false;
5463 }
5464
5465 switch (vlan_get_protocol(skb)) {
5466 case htons(ETH_P_IP):
5467 opts[0] |= TD1_GTSENV4;
5468 break;
5469
5470 case htons(ETH_P_IPV6):
5471 if (msdn_giant_send_check(skb))
5472 return false;
5473
5474 opts[0] |= TD1_GTSENV6;
5475 break;
5476
5477 default:
5478 WARN_ON_ONCE(1);
5479 break;
5480 }
5481
5482 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5483 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
5484 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5485 u8 ip_protocol;
5486
5487 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5488 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
5489
5490 if (transport_offset > TCPHO_MAX) {
5491 netif_warn(tp, tx_err, tp->dev,
5492 "Invalid transport offset 0x%x\n",
5493 transport_offset);
5494 return false;
5495 }
5496
5497 switch (vlan_get_protocol(skb)) {
5498 case htons(ETH_P_IP):
5499 opts[1] |= TD1_IPv4_CS;
5500 ip_protocol = ip_hdr(skb)->protocol;
5501 break;
5502
5503 case htons(ETH_P_IPV6):
5504 opts[1] |= TD1_IPv6_CS;
5505 ip_protocol = ipv6_hdr(skb)->nexthdr;
5506 break;
5507
5508 default:
5509 ip_protocol = IPPROTO_RAW;
5510 break;
5511 }
5512
5513 if (ip_protocol == IPPROTO_TCP)
5514 opts[1] |= TD1_TCP_CS;
5515 else if (ip_protocol == IPPROTO_UDP)
5516 opts[1] |= TD1_UDP_CS;
5517 else
5518 WARN_ON_ONCE(1);
5519
5520 opts[1] |= transport_offset << TCPHO_SHIFT;
5521 } else {
5522 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5523 return !eth_skb_pad(skb);
5524 }
5525
5526 return true;
5527 }
5528
5529 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
5530 unsigned int nr_frags)
5531 {
5532 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
5533
5534 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
5535 return slots_avail > nr_frags;
5536 }
5537
5538 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
5539 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
5540 {
5541 switch (tp->mac_version) {
5542 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5543 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
5544 return false;
5545 default:
5546 return true;
5547 }
5548 }
5549
5550 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5551 struct net_device *dev)
5552 {
5553 struct rtl8169_private *tp = netdev_priv(dev);
5554 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5555 struct TxDesc *txd = tp->TxDescArray + entry;
5556 struct device *d = tp_to_dev(tp);
5557 dma_addr_t mapping;
5558 u32 opts[2], len;
5559 int frags;
5560
5561 if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
5562 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5563 goto err_stop_0;
5564 }
5565
5566 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5567 goto err_stop_0;
5568
5569 opts[1] = rtl8169_tx_vlan_tag(skb);
5570 opts[0] = DescOwn;
5571
5572 if (rtl_chip_supports_csum_v2(tp)) {
5573 if (!rtl8169_tso_csum_v2(tp, skb, opts)) {
5574 r8169_csum_workaround(tp, skb);
5575 return NETDEV_TX_OK;
5576 }
5577 } else {
5578 rtl8169_tso_csum_v1(skb, opts);
5579 }
5580
5581 len = skb_headlen(skb);
5582 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5583 if (unlikely(dma_mapping_error(d, mapping))) {
5584 if (net_ratelimit())
5585 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5586 goto err_dma_0;
5587 }
5588
5589 tp->tx_skb[entry].len = len;
5590 txd->addr = cpu_to_le64(mapping);
5591
5592 frags = rtl8169_xmit_frags(tp, skb, opts);
5593 if (frags < 0)
5594 goto err_dma_1;
5595 else if (frags)
5596 opts[0] |= FirstFrag;
5597 else {
5598 opts[0] |= FirstFrag | LastFrag;
5599 tp->tx_skb[entry].skb = skb;
5600 }
5601
5602 txd->opts2 = cpu_to_le32(opts[1]);
5603
5604 netdev_sent_queue(dev, skb->len);
5605
5606 skb_tx_timestamp(skb);
5607
5608 /* Force memory writes to complete before releasing descriptor */
5609 dma_wmb();
5610
5611 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5612
5613 /* Force all memory writes to complete before notifying device */
5614 wmb();
5615
5616 tp->cur_tx += frags + 1;
5617
5618 RTL_W8(tp, TxPoll, NPQ);
5619
5620 if (!rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
5621 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5622 * not miss a ring update when it notices a stopped queue.
5623 */
5624 smp_wmb();
5625 netif_stop_queue(dev);
5626 /* Sync with rtl_tx:
5627 * - publish queue status and cur_tx ring index (write barrier)
5628 * - refresh dirty_tx ring index (read barrier).
5629 * May the current thread have a pessimistic view of the ring
5630 * status and forget to wake up queue, a racing rtl_tx thread
5631 * can't.
5632 */
5633 smp_mb();
5634 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
5635 netif_start_queue(dev);
5636 }
5637
5638 return NETDEV_TX_OK;
5639
5640 err_dma_1:
5641 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5642 err_dma_0:
5643 dev_kfree_skb_any(skb);
5644 dev->stats.tx_dropped++;
5645 return NETDEV_TX_OK;
5646
5647 err_stop_0:
5648 netif_stop_queue(dev);
5649 dev->stats.tx_dropped++;
5650 return NETDEV_TX_BUSY;
5651 }
5652
5653 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5654 {
5655 struct rtl8169_private *tp = netdev_priv(dev);
5656 struct pci_dev *pdev = tp->pci_dev;
5657 u16 pci_status, pci_cmd;
5658
5659 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5660 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5661
5662 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5663 pci_cmd, pci_status);
5664
5665 /*
5666 * The recovery sequence below admits a very elaborated explanation:
5667 * - it seems to work;
5668 * - I did not see what else could be done;
5669 * - it makes iop3xx happy.
5670 *
5671 * Feel free to adjust to your needs.
5672 */
5673 if (pdev->broken_parity_status)
5674 pci_cmd &= ~PCI_COMMAND_PARITY;
5675 else
5676 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5677
5678 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5679
5680 pci_write_config_word(pdev, PCI_STATUS,
5681 pci_status & (PCI_STATUS_DETECTED_PARITY |
5682 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5683 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5684
5685 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5686 }
5687
5688 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
5689 int budget)
5690 {
5691 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
5692
5693 dirty_tx = tp->dirty_tx;
5694 smp_rmb();
5695 tx_left = tp->cur_tx - dirty_tx;
5696
5697 while (tx_left > 0) {
5698 unsigned int entry = dirty_tx % NUM_TX_DESC;
5699 struct ring_info *tx_skb = tp->tx_skb + entry;
5700 u32 status;
5701
5702 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5703 if (status & DescOwn)
5704 break;
5705
5706 /* This barrier is needed to keep us from reading
5707 * any other fields out of the Tx descriptor until
5708 * we know the status of DescOwn
5709 */
5710 dma_rmb();
5711
5712 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5713 tp->TxDescArray + entry);
5714 if (status & LastFrag) {
5715 pkts_compl++;
5716 bytes_compl += tx_skb->skb->len;
5717 napi_consume_skb(tx_skb->skb, budget);
5718 tx_skb->skb = NULL;
5719 }
5720 dirty_tx++;
5721 tx_left--;
5722 }
5723
5724 if (tp->dirty_tx != dirty_tx) {
5725 netdev_completed_queue(dev, pkts_compl, bytes_compl);
5726
5727 u64_stats_update_begin(&tp->tx_stats.syncp);
5728 tp->tx_stats.packets += pkts_compl;
5729 tp->tx_stats.bytes += bytes_compl;
5730 u64_stats_update_end(&tp->tx_stats.syncp);
5731
5732 tp->dirty_tx = dirty_tx;
5733 /* Sync with rtl8169_start_xmit:
5734 * - publish dirty_tx ring index (write barrier)
5735 * - refresh cur_tx ring index and queue status (read barrier)
5736 * May the current thread miss the stopped queue condition,
5737 * a racing xmit thread can only have a right view of the
5738 * ring status.
5739 */
5740 smp_mb();
5741 if (netif_queue_stopped(dev) &&
5742 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
5743 netif_wake_queue(dev);
5744 }
5745 /*
5746 * 8168 hack: TxPoll requests are lost when the Tx packets are
5747 * too close. Let's kick an extra TxPoll request when a burst
5748 * of start_xmit activity is detected (if it is not detected,
5749 * it is slow enough). -- FR
5750 */
5751 if (tp->cur_tx != dirty_tx)
5752 RTL_W8(tp, TxPoll, NPQ);
5753 }
5754 }
5755
5756 static inline int rtl8169_fragmented_frame(u32 status)
5757 {
5758 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5759 }
5760
5761 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5762 {
5763 u32 status = opts1 & RxProtoMask;
5764
5765 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5766 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5767 skb->ip_summed = CHECKSUM_UNNECESSARY;
5768 else
5769 skb_checksum_none_assert(skb);
5770 }
5771
5772 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5773 struct rtl8169_private *tp,
5774 int pkt_size,
5775 dma_addr_t addr)
5776 {
5777 struct sk_buff *skb;
5778 struct device *d = tp_to_dev(tp);
5779
5780 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5781 prefetch(data);
5782 skb = napi_alloc_skb(&tp->napi, pkt_size);
5783 if (skb)
5784 skb_copy_to_linear_data(skb, data, pkt_size);
5785 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5786
5787 return skb;
5788 }
5789
5790 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5791 {
5792 unsigned int cur_rx, rx_left;
5793 unsigned int count;
5794
5795 cur_rx = tp->cur_rx;
5796
5797 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
5798 unsigned int entry = cur_rx % NUM_RX_DESC;
5799 struct RxDesc *desc = tp->RxDescArray + entry;
5800 u32 status;
5801
5802 status = le32_to_cpu(desc->opts1);
5803 if (status & DescOwn)
5804 break;
5805
5806 /* This barrier is needed to keep us from reading
5807 * any other fields out of the Rx descriptor until
5808 * we know the status of DescOwn
5809 */
5810 dma_rmb();
5811
5812 if (unlikely(status & RxRES)) {
5813 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5814 status);
5815 dev->stats.rx_errors++;
5816 if (status & (RxRWT | RxRUNT))
5817 dev->stats.rx_length_errors++;
5818 if (status & RxCRC)
5819 dev->stats.rx_crc_errors++;
5820 if (status & (RxRUNT | RxCRC) && !(status & RxRWT) &&
5821 dev->features & NETIF_F_RXALL) {
5822 goto process_pkt;
5823 }
5824 } else {
5825 struct sk_buff *skb;
5826 dma_addr_t addr;
5827 int pkt_size;
5828
5829 process_pkt:
5830 addr = le64_to_cpu(desc->addr);
5831 if (likely(!(dev->features & NETIF_F_RXFCS)))
5832 pkt_size = (status & 0x00003fff) - 4;
5833 else
5834 pkt_size = status & 0x00003fff;
5835
5836 /*
5837 * The driver does not support incoming fragmented
5838 * frames. They are seen as a symptom of over-mtu
5839 * sized frames.
5840 */
5841 if (unlikely(rtl8169_fragmented_frame(status))) {
5842 dev->stats.rx_dropped++;
5843 dev->stats.rx_length_errors++;
5844 goto release_descriptor;
5845 }
5846
5847 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5848 tp, pkt_size, addr);
5849 if (!skb) {
5850 dev->stats.rx_dropped++;
5851 goto release_descriptor;
5852 }
5853
5854 rtl8169_rx_csum(skb, status);
5855 skb_put(skb, pkt_size);
5856 skb->protocol = eth_type_trans(skb, dev);
5857
5858 rtl8169_rx_vlan_tag(desc, skb);
5859
5860 if (skb->pkt_type == PACKET_MULTICAST)
5861 dev->stats.multicast++;
5862
5863 napi_gro_receive(&tp->napi, skb);
5864
5865 u64_stats_update_begin(&tp->rx_stats.syncp);
5866 tp->rx_stats.packets++;
5867 tp->rx_stats.bytes += pkt_size;
5868 u64_stats_update_end(&tp->rx_stats.syncp);
5869 }
5870 release_descriptor:
5871 desc->opts2 = 0;
5872 rtl8169_mark_to_asic(desc);
5873 }
5874
5875 count = cur_rx - tp->cur_rx;
5876 tp->cur_rx = cur_rx;
5877
5878 return count;
5879 }
5880
5881 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5882 {
5883 struct rtl8169_private *tp = dev_instance;
5884 u16 status = RTL_R16(tp, IntrStatus);
5885
5886 if (!tp->irq_enabled || status == 0xffff || !(status & tp->irq_mask))
5887 return IRQ_NONE;
5888
5889 if (unlikely(status & SYSErr)) {
5890 rtl8169_pcierr_interrupt(tp->dev);
5891 goto out;
5892 }
5893
5894 if (status & LinkChg)
5895 phy_mac_interrupt(tp->phydev);
5896
5897 if (unlikely(status & RxFIFOOver &&
5898 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
5899 netif_stop_queue(tp->dev);
5900 /* XXX - Hack alert. See rtl_task(). */
5901 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
5902 }
5903
5904 rtl_irq_disable(tp);
5905 napi_schedule_irqoff(&tp->napi);
5906 out:
5907 rtl_ack_events(tp, status);
5908
5909 return IRQ_HANDLED;
5910 }
5911
5912 static void rtl_task(struct work_struct *work)
5913 {
5914 static const struct {
5915 int bitnr;
5916 void (*action)(struct rtl8169_private *);
5917 } rtl_work[] = {
5918 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
5919 };
5920 struct rtl8169_private *tp =
5921 container_of(work, struct rtl8169_private, wk.work);
5922 struct net_device *dev = tp->dev;
5923 int i;
5924
5925 rtl_lock_work(tp);
5926
5927 if (!netif_running(dev) ||
5928 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
5929 goto out_unlock;
5930
5931 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
5932 bool pending;
5933
5934 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
5935 if (pending)
5936 rtl_work[i].action(tp);
5937 }
5938
5939 out_unlock:
5940 rtl_unlock_work(tp);
5941 }
5942
5943 static int rtl8169_poll(struct napi_struct *napi, int budget)
5944 {
5945 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5946 struct net_device *dev = tp->dev;
5947 int work_done;
5948
5949 work_done = rtl_rx(dev, tp, (u32) budget);
5950
5951 rtl_tx(dev, tp, budget);
5952
5953 if (work_done < budget) {
5954 napi_complete_done(napi, work_done);
5955 rtl_irq_enable(tp);
5956 }
5957
5958 return work_done;
5959 }
5960
5961 static void rtl8169_rx_missed(struct net_device *dev)
5962 {
5963 struct rtl8169_private *tp = netdev_priv(dev);
5964
5965 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5966 return;
5967
5968 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
5969 RTL_W32(tp, RxMissed, 0);
5970 }
5971
5972 static void r8169_phylink_handler(struct net_device *ndev)
5973 {
5974 struct rtl8169_private *tp = netdev_priv(ndev);
5975
5976 if (netif_carrier_ok(ndev)) {
5977 rtl_link_chg_patch(tp);
5978 pm_request_resume(&tp->pci_dev->dev);
5979 } else {
5980 pm_runtime_idle(&tp->pci_dev->dev);
5981 }
5982
5983 if (net_ratelimit())
5984 phy_print_status(tp->phydev);
5985 }
5986
5987 static int r8169_phy_connect(struct rtl8169_private *tp)
5988 {
5989 struct phy_device *phydev = tp->phydev;
5990 phy_interface_t phy_mode;
5991 int ret;
5992
5993 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
5994 PHY_INTERFACE_MODE_MII;
5995
5996 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
5997 phy_mode);
5998 if (ret)
5999 return ret;
6000
6001 if (tp->supports_gmii)
6002 phy_remove_link_mode(phydev,
6003 ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
6004 else
6005 phy_set_max_speed(phydev, SPEED_100);
6006
6007 phy_support_asym_pause(phydev);
6008
6009 phy_attached_info(phydev);
6010
6011 return 0;
6012 }
6013
6014 static void rtl8169_down(struct net_device *dev)
6015 {
6016 struct rtl8169_private *tp = netdev_priv(dev);
6017
6018 phy_stop(tp->phydev);
6019
6020 napi_disable(&tp->napi);
6021 netif_stop_queue(dev);
6022
6023 rtl8169_hw_reset(tp);
6024 /*
6025 * At this point device interrupts can not be enabled in any function,
6026 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6027 * and napi is disabled (rtl8169_poll).
6028 */
6029 rtl8169_rx_missed(dev);
6030
6031 /* Give a racing hard_start_xmit a few cycles to complete. */
6032 synchronize_rcu();
6033
6034 rtl8169_tx_clear(tp);
6035
6036 rtl8169_rx_clear(tp);
6037
6038 rtl_pll_power_down(tp);
6039 }
6040
6041 static int rtl8169_close(struct net_device *dev)
6042 {
6043 struct rtl8169_private *tp = netdev_priv(dev);
6044 struct pci_dev *pdev = tp->pci_dev;
6045
6046 pm_runtime_get_sync(&pdev->dev);
6047
6048 /* Update counters before going down */
6049 rtl8169_update_counters(tp);
6050
6051 rtl_lock_work(tp);
6052 /* Clear all task flags */
6053 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6054
6055 rtl8169_down(dev);
6056 rtl_unlock_work(tp);
6057
6058 cancel_work_sync(&tp->wk.work);
6059
6060 phy_disconnect(tp->phydev);
6061
6062 pci_free_irq(pdev, 0, tp);
6063
6064 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6065 tp->RxPhyAddr);
6066 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6067 tp->TxPhyAddr);
6068 tp->TxDescArray = NULL;
6069 tp->RxDescArray = NULL;
6070
6071 pm_runtime_put_sync(&pdev->dev);
6072
6073 return 0;
6074 }
6075
6076 #ifdef CONFIG_NET_POLL_CONTROLLER
6077 static void rtl8169_netpoll(struct net_device *dev)
6078 {
6079 struct rtl8169_private *tp = netdev_priv(dev);
6080
6081 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6082 }
6083 #endif
6084
6085 static int rtl_open(struct net_device *dev)
6086 {
6087 struct rtl8169_private *tp = netdev_priv(dev);
6088 struct pci_dev *pdev = tp->pci_dev;
6089 int retval = -ENOMEM;
6090
6091 pm_runtime_get_sync(&pdev->dev);
6092
6093 /*
6094 * Rx and Tx descriptors needs 256 bytes alignment.
6095 * dma_alloc_coherent provides more.
6096 */
6097 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6098 &tp->TxPhyAddr, GFP_KERNEL);
6099 if (!tp->TxDescArray)
6100 goto err_pm_runtime_put;
6101
6102 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6103 &tp->RxPhyAddr, GFP_KERNEL);
6104 if (!tp->RxDescArray)
6105 goto err_free_tx_0;
6106
6107 retval = rtl8169_init_ring(tp);
6108 if (retval < 0)
6109 goto err_free_rx_1;
6110
6111 rtl_request_firmware(tp);
6112
6113 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6114 dev->name);
6115 if (retval < 0)
6116 goto err_release_fw_2;
6117
6118 retval = r8169_phy_connect(tp);
6119 if (retval)
6120 goto err_free_irq;
6121
6122 rtl_lock_work(tp);
6123
6124 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6125
6126 napi_enable(&tp->napi);
6127
6128 rtl8169_init_phy(dev, tp);
6129
6130 rtl_pll_power_up(tp);
6131
6132 rtl_hw_start(tp);
6133
6134 if (!rtl8169_init_counter_offsets(tp))
6135 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6136
6137 phy_start(tp->phydev);
6138 netif_start_queue(dev);
6139
6140 rtl_unlock_work(tp);
6141
6142 pm_runtime_put_sync(&pdev->dev);
6143 out:
6144 return retval;
6145
6146 err_free_irq:
6147 pci_free_irq(pdev, 0, tp);
6148 err_release_fw_2:
6149 rtl_release_firmware(tp);
6150 rtl8169_rx_clear(tp);
6151 err_free_rx_1:
6152 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6153 tp->RxPhyAddr);
6154 tp->RxDescArray = NULL;
6155 err_free_tx_0:
6156 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6157 tp->TxPhyAddr);
6158 tp->TxDescArray = NULL;
6159 err_pm_runtime_put:
6160 pm_runtime_put_noidle(&pdev->dev);
6161 goto out;
6162 }
6163
6164 static void
6165 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6166 {
6167 struct rtl8169_private *tp = netdev_priv(dev);
6168 struct pci_dev *pdev = tp->pci_dev;
6169 struct rtl8169_counters *counters = tp->counters;
6170 unsigned int start;
6171
6172 pm_runtime_get_noresume(&pdev->dev);
6173
6174 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6175 rtl8169_rx_missed(dev);
6176
6177 do {
6178 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6179 stats->rx_packets = tp->rx_stats.packets;
6180 stats->rx_bytes = tp->rx_stats.bytes;
6181 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6182
6183 do {
6184 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6185 stats->tx_packets = tp->tx_stats.packets;
6186 stats->tx_bytes = tp->tx_stats.bytes;
6187 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6188
6189 stats->rx_dropped = dev->stats.rx_dropped;
6190 stats->tx_dropped = dev->stats.tx_dropped;
6191 stats->rx_length_errors = dev->stats.rx_length_errors;
6192 stats->rx_errors = dev->stats.rx_errors;
6193 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6194 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6195 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6196 stats->multicast = dev->stats.multicast;
6197
6198 /*
6199 * Fetch additonal counter values missing in stats collected by driver
6200 * from tally counters.
6201 */
6202 if (pm_runtime_active(&pdev->dev))
6203 rtl8169_update_counters(tp);
6204
6205 /*
6206 * Subtract values fetched during initalization.
6207 * See rtl8169_init_counter_offsets for a description why we do that.
6208 */
6209 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6210 le64_to_cpu(tp->tc_offset.tx_errors);
6211 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6212 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6213 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6214 le16_to_cpu(tp->tc_offset.tx_aborted);
6215
6216 pm_runtime_put_noidle(&pdev->dev);
6217 }
6218
6219 static void rtl8169_net_suspend(struct net_device *dev)
6220 {
6221 struct rtl8169_private *tp = netdev_priv(dev);
6222
6223 if (!netif_running(dev))
6224 return;
6225
6226 phy_stop(tp->phydev);
6227 netif_device_detach(dev);
6228
6229 rtl_lock_work(tp);
6230 napi_disable(&tp->napi);
6231 /* Clear all task flags */
6232 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6233
6234 rtl_unlock_work(tp);
6235
6236 rtl_pll_power_down(tp);
6237 }
6238
6239 #ifdef CONFIG_PM
6240
6241 static int rtl8169_suspend(struct device *device)
6242 {
6243 struct net_device *dev = dev_get_drvdata(device);
6244 struct rtl8169_private *tp = netdev_priv(dev);
6245
6246 rtl8169_net_suspend(dev);
6247 clk_disable_unprepare(tp->clk);
6248
6249 return 0;
6250 }
6251
6252 static void __rtl8169_resume(struct net_device *dev)
6253 {
6254 struct rtl8169_private *tp = netdev_priv(dev);
6255
6256 netif_device_attach(dev);
6257
6258 rtl_pll_power_up(tp);
6259 rtl8169_init_phy(dev, tp);
6260
6261 phy_start(tp->phydev);
6262
6263 rtl_lock_work(tp);
6264 napi_enable(&tp->napi);
6265 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6266 rtl_reset_work(tp);
6267 rtl_unlock_work(tp);
6268 }
6269
6270 static int rtl8169_resume(struct device *device)
6271 {
6272 struct net_device *dev = dev_get_drvdata(device);
6273 struct rtl8169_private *tp = netdev_priv(dev);
6274
6275 rtl_rar_set(tp, dev->dev_addr);
6276
6277 clk_prepare_enable(tp->clk);
6278
6279 if (netif_running(dev))
6280 __rtl8169_resume(dev);
6281
6282 return 0;
6283 }
6284
6285 static int rtl8169_runtime_suspend(struct device *device)
6286 {
6287 struct net_device *dev = dev_get_drvdata(device);
6288 struct rtl8169_private *tp = netdev_priv(dev);
6289
6290 if (!tp->TxDescArray)
6291 return 0;
6292
6293 rtl_lock_work(tp);
6294 __rtl8169_set_wol(tp, WAKE_ANY);
6295 rtl_unlock_work(tp);
6296
6297 rtl8169_net_suspend(dev);
6298
6299 /* Update counters before going runtime suspend */
6300 rtl8169_rx_missed(dev);
6301 rtl8169_update_counters(tp);
6302
6303 return 0;
6304 }
6305
6306 static int rtl8169_runtime_resume(struct device *device)
6307 {
6308 struct net_device *dev = dev_get_drvdata(device);
6309 struct rtl8169_private *tp = netdev_priv(dev);
6310
6311 rtl_rar_set(tp, dev->dev_addr);
6312
6313 if (!tp->TxDescArray)
6314 return 0;
6315
6316 rtl_lock_work(tp);
6317 __rtl8169_set_wol(tp, tp->saved_wolopts);
6318 rtl_unlock_work(tp);
6319
6320 __rtl8169_resume(dev);
6321
6322 return 0;
6323 }
6324
6325 static int rtl8169_runtime_idle(struct device *device)
6326 {
6327 struct net_device *dev = dev_get_drvdata(device);
6328
6329 if (!netif_running(dev) || !netif_carrier_ok(dev))
6330 pm_schedule_suspend(device, 10000);
6331
6332 return -EBUSY;
6333 }
6334
6335 static const struct dev_pm_ops rtl8169_pm_ops = {
6336 .suspend = rtl8169_suspend,
6337 .resume = rtl8169_resume,
6338 .freeze = rtl8169_suspend,
6339 .thaw = rtl8169_resume,
6340 .poweroff = rtl8169_suspend,
6341 .restore = rtl8169_resume,
6342 .runtime_suspend = rtl8169_runtime_suspend,
6343 .runtime_resume = rtl8169_runtime_resume,
6344 .runtime_idle = rtl8169_runtime_idle,
6345 };
6346
6347 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
6348
6349 #else /* !CONFIG_PM */
6350
6351 #define RTL8169_PM_OPS NULL
6352
6353 #endif /* !CONFIG_PM */
6354
6355 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6356 {
6357 /* WoL fails with 8168b when the receiver is disabled. */
6358 switch (tp->mac_version) {
6359 case RTL_GIGA_MAC_VER_11:
6360 case RTL_GIGA_MAC_VER_12:
6361 case RTL_GIGA_MAC_VER_17:
6362 pci_clear_master(tp->pci_dev);
6363
6364 RTL_W8(tp, ChipCmd, CmdRxEnb);
6365 /* PCI commit */
6366 RTL_R8(tp, ChipCmd);
6367 break;
6368 default:
6369 break;
6370 }
6371 }
6372
6373 static void rtl_shutdown(struct pci_dev *pdev)
6374 {
6375 struct net_device *dev = pci_get_drvdata(pdev);
6376 struct rtl8169_private *tp = netdev_priv(dev);
6377
6378 rtl8169_net_suspend(dev);
6379
6380 /* Restore original MAC address */
6381 rtl_rar_set(tp, dev->perm_addr);
6382
6383 rtl8169_hw_reset(tp);
6384
6385 if (system_state == SYSTEM_POWER_OFF) {
6386 if (tp->saved_wolopts) {
6387 rtl_wol_suspend_quirk(tp);
6388 rtl_wol_shutdown_quirk(tp);
6389 }
6390
6391 pci_wake_from_d3(pdev, true);
6392 pci_set_power_state(pdev, PCI_D3hot);
6393 }
6394 }
6395
6396 static void rtl_remove_one(struct pci_dev *pdev)
6397 {
6398 struct net_device *dev = pci_get_drvdata(pdev);
6399 struct rtl8169_private *tp = netdev_priv(dev);
6400
6401 if (r8168_check_dash(tp))
6402 rtl8168_driver_stop(tp);
6403
6404 netif_napi_del(&tp->napi);
6405
6406 unregister_netdev(dev);
6407 mdiobus_unregister(tp->phydev->mdio.bus);
6408
6409 rtl_release_firmware(tp);
6410
6411 if (pci_dev_run_wake(pdev))
6412 pm_runtime_get_noresume(&pdev->dev);
6413
6414 /* restore original MAC address */
6415 rtl_rar_set(tp, dev->perm_addr);
6416 }
6417
6418 static const struct net_device_ops rtl_netdev_ops = {
6419 .ndo_open = rtl_open,
6420 .ndo_stop = rtl8169_close,
6421 .ndo_get_stats64 = rtl8169_get_stats64,
6422 .ndo_start_xmit = rtl8169_start_xmit,
6423 .ndo_tx_timeout = rtl8169_tx_timeout,
6424 .ndo_validate_addr = eth_validate_addr,
6425 .ndo_change_mtu = rtl8169_change_mtu,
6426 .ndo_fix_features = rtl8169_fix_features,
6427 .ndo_set_features = rtl8169_set_features,
6428 .ndo_set_mac_address = rtl_set_mac_address,
6429 .ndo_do_ioctl = rtl8169_ioctl,
6430 .ndo_set_rx_mode = rtl_set_rx_mode,
6431 #ifdef CONFIG_NET_POLL_CONTROLLER
6432 .ndo_poll_controller = rtl8169_netpoll,
6433 #endif
6434
6435 };
6436
6437 static void rtl_set_irq_mask(struct rtl8169_private *tp)
6438 {
6439 tp->irq_mask = RTL_EVENT_NAPI | LinkChg;
6440
6441 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6442 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
6443 else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
6444 /* special workaround needed */
6445 tp->irq_mask |= RxFIFOOver;
6446 else
6447 tp->irq_mask |= RxOverflow;
6448 }
6449
6450 static int rtl_alloc_irq(struct rtl8169_private *tp)
6451 {
6452 unsigned int flags;
6453
6454 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
6455 rtl_unlock_config_regs(tp);
6456 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
6457 rtl_lock_config_regs(tp);
6458 flags = PCI_IRQ_LEGACY;
6459 } else {
6460 flags = PCI_IRQ_ALL_TYPES;
6461 }
6462
6463 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
6464 }
6465
6466 static void rtl_read_mac_address(struct rtl8169_private *tp,
6467 u8 mac_addr[ETH_ALEN])
6468 {
6469 /* Get MAC address */
6470 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
6471 u32 value = rtl_eri_read(tp, 0xe0);
6472
6473 mac_addr[0] = (value >> 0) & 0xff;
6474 mac_addr[1] = (value >> 8) & 0xff;
6475 mac_addr[2] = (value >> 16) & 0xff;
6476 mac_addr[3] = (value >> 24) & 0xff;
6477
6478 value = rtl_eri_read(tp, 0xe4);
6479 mac_addr[4] = (value >> 0) & 0xff;
6480 mac_addr[5] = (value >> 8) & 0xff;
6481 }
6482 }
6483
6484 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6485 {
6486 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
6487 }
6488
6489 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6490 {
6491 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6492 }
6493
6494 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
6495 {
6496 struct rtl8169_private *tp = mii_bus->priv;
6497
6498 if (phyaddr > 0)
6499 return -ENODEV;
6500
6501 return rtl_readphy(tp, phyreg);
6502 }
6503
6504 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
6505 int phyreg, u16 val)
6506 {
6507 struct rtl8169_private *tp = mii_bus->priv;
6508
6509 if (phyaddr > 0)
6510 return -ENODEV;
6511
6512 rtl_writephy(tp, phyreg, val);
6513
6514 return 0;
6515 }
6516
6517 static int r8169_mdio_register(struct rtl8169_private *tp)
6518 {
6519 struct pci_dev *pdev = tp->pci_dev;
6520 struct mii_bus *new_bus;
6521 int ret;
6522
6523 new_bus = devm_mdiobus_alloc(&pdev->dev);
6524 if (!new_bus)
6525 return -ENOMEM;
6526
6527 new_bus->name = "r8169";
6528 new_bus->priv = tp;
6529 new_bus->parent = &pdev->dev;
6530 new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
6531 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
6532
6533 new_bus->read = r8169_mdio_read_reg;
6534 new_bus->write = r8169_mdio_write_reg;
6535
6536 ret = mdiobus_register(new_bus);
6537 if (ret)
6538 return ret;
6539
6540 tp->phydev = mdiobus_get_phy(new_bus, 0);
6541 if (!tp->phydev) {
6542 mdiobus_unregister(new_bus);
6543 return -ENODEV;
6544 }
6545
6546 /* PHY will be woken up in rtl_open() */
6547 phy_suspend(tp->phydev);
6548
6549 return 0;
6550 }
6551
6552 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6553 {
6554 u32 data;
6555
6556 tp->ocp_base = OCP_STD_PHY_BASE;
6557
6558 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
6559
6560 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6561 return;
6562
6563 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6564 return;
6565
6566 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6567 msleep(1);
6568 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6569
6570 data = r8168_mac_ocp_read(tp, 0xe8de);
6571 data &= ~(1 << 14);
6572 r8168_mac_ocp_write(tp, 0xe8de, data);
6573
6574 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6575 return;
6576
6577 data = r8168_mac_ocp_read(tp, 0xe8de);
6578 data |= (1 << 15);
6579 r8168_mac_ocp_write(tp, 0xe8de, data);
6580
6581 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
6582 }
6583
6584 static void rtl_hw_initialize(struct rtl8169_private *tp)
6585 {
6586 switch (tp->mac_version) {
6587 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
6588 rtl8168ep_stop_cmac(tp);
6589 /* fall through */
6590 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
6591 rtl_hw_init_8168g(tp);
6592 break;
6593 default:
6594 break;
6595 }
6596 }
6597
6598 static int rtl_jumbo_max(struct rtl8169_private *tp)
6599 {
6600 /* Non-GBit versions don't support jumbo frames */
6601 if (!tp->supports_gmii)
6602 return JUMBO_1K;
6603
6604 switch (tp->mac_version) {
6605 /* RTL8169 */
6606 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
6607 return JUMBO_7K;
6608 /* RTL8168b */
6609 case RTL_GIGA_MAC_VER_11:
6610 case RTL_GIGA_MAC_VER_12:
6611 case RTL_GIGA_MAC_VER_17:
6612 return JUMBO_4K;
6613 /* RTL8168c */
6614 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
6615 return JUMBO_6K;
6616 default:
6617 return JUMBO_9K;
6618 }
6619 }
6620
6621 static void rtl_disable_clk(void *data)
6622 {
6623 clk_disable_unprepare(data);
6624 }
6625
6626 static int rtl_get_ether_clk(struct rtl8169_private *tp)
6627 {
6628 struct device *d = tp_to_dev(tp);
6629 struct clk *clk;
6630 int rc;
6631
6632 clk = devm_clk_get(d, "ether_clk");
6633 if (IS_ERR(clk)) {
6634 rc = PTR_ERR(clk);
6635 if (rc == -ENOENT)
6636 /* clk-core allows NULL (for suspend / resume) */
6637 rc = 0;
6638 else if (rc != -EPROBE_DEFER)
6639 dev_err(d, "failed to get clk: %d\n", rc);
6640 } else {
6641 tp->clk = clk;
6642 rc = clk_prepare_enable(clk);
6643 if (rc)
6644 dev_err(d, "failed to enable clk: %d\n", rc);
6645 else
6646 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
6647 }
6648
6649 return rc;
6650 }
6651
6652 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6653 {
6654 /* align to u16 for is_valid_ether_addr() */
6655 u8 mac_addr[ETH_ALEN] __aligned(2) = {};
6656 struct rtl8169_private *tp;
6657 struct net_device *dev;
6658 int chipset, region, i;
6659 int jumbo_max, rc;
6660
6661 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
6662 if (!dev)
6663 return -ENOMEM;
6664
6665 SET_NETDEV_DEV(dev, &pdev->dev);
6666 dev->netdev_ops = &rtl_netdev_ops;
6667 tp = netdev_priv(dev);
6668 tp->dev = dev;
6669 tp->pci_dev = pdev;
6670 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6671 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
6672
6673 /* Get the *optional* external "ether_clk" used on some boards */
6674 rc = rtl_get_ether_clk(tp);
6675 if (rc)
6676 return rc;
6677
6678 /* Disable ASPM completely as that cause random device stop working
6679 * problems as well as full system hangs for some PCIe devices users.
6680 */
6681 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
6682
6683 /* enable device (incl. PCI PM wakeup and hotplug setup) */
6684 rc = pcim_enable_device(pdev);
6685 if (rc < 0) {
6686 dev_err(&pdev->dev, "enable failure\n");
6687 return rc;
6688 }
6689
6690 if (pcim_set_mwi(pdev) < 0)
6691 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
6692
6693 /* use first MMIO region */
6694 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
6695 if (region < 0) {
6696 dev_err(&pdev->dev, "no MMIO resource found\n");
6697 return -ENODEV;
6698 }
6699
6700 /* check for weird/broken PCI region reporting */
6701 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6702 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
6703 return -ENODEV;
6704 }
6705
6706 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
6707 if (rc < 0) {
6708 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
6709 return rc;
6710 }
6711
6712 tp->mmio_addr = pcim_iomap_table(pdev)[region];
6713
6714 /* Identify chip attached to board */
6715 rtl8169_get_mac_version(tp);
6716 if (tp->mac_version == RTL_GIGA_MAC_NONE)
6717 return -ENODEV;
6718
6719 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
6720
6721 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
6722 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
6723 dev->features |= NETIF_F_HIGHDMA;
6724 } else {
6725 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6726 if (rc < 0) {
6727 dev_err(&pdev->dev, "DMA configuration failed\n");
6728 return rc;
6729 }
6730 }
6731
6732 rtl_init_rxcfg(tp);
6733
6734 rtl8169_irq_mask_and_ack(tp);
6735
6736 rtl_hw_initialize(tp);
6737
6738 rtl_hw_reset(tp);
6739
6740 pci_set_master(pdev);
6741
6742 chipset = tp->mac_version;
6743
6744 rc = rtl_alloc_irq(tp);
6745 if (rc < 0) {
6746 dev_err(&pdev->dev, "Can't allocate interrupt\n");
6747 return rc;
6748 }
6749
6750 mutex_init(&tp->wk.mutex);
6751 INIT_WORK(&tp->wk.work, rtl_task);
6752 u64_stats_init(&tp->rx_stats.syncp);
6753 u64_stats_init(&tp->tx_stats.syncp);
6754
6755 /* get MAC address */
6756 rc = eth_platform_get_mac_address(&pdev->dev, mac_addr);
6757 if (rc)
6758 rtl_read_mac_address(tp, mac_addr);
6759
6760 if (is_valid_ether_addr(mac_addr))
6761 rtl_rar_set(tp, mac_addr);
6762
6763 for (i = 0; i < ETH_ALEN; i++)
6764 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
6765
6766 dev->ethtool_ops = &rtl8169_ethtool_ops;
6767
6768 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
6769
6770 /* don't enable SG, IP_CSUM and TSO by default - it might not work
6771 * properly for all devices */
6772 dev->features |= NETIF_F_RXCSUM |
6773 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
6774
6775 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6776 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
6777 NETIF_F_HW_VLAN_CTAG_RX;
6778 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6779 NETIF_F_HIGHDMA;
6780 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
6781
6782 tp->cp_cmd |= RxChkSum | RxVlan;
6783
6784 /*
6785 * Pretend we are using VLANs; This bypasses a nasty bug where
6786 * Interrupts stop flowing on high load on 8110SCd controllers.
6787 */
6788 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6789 /* Disallow toggling */
6790 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
6791
6792 if (rtl_chip_supports_csum_v2(tp))
6793 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
6794
6795 dev->hw_features |= NETIF_F_RXALL;
6796 dev->hw_features |= NETIF_F_RXFCS;
6797
6798 /* MTU range: 60 - hw-specific max */
6799 dev->min_mtu = ETH_ZLEN;
6800 jumbo_max = rtl_jumbo_max(tp);
6801 dev->max_mtu = jumbo_max;
6802
6803 rtl_set_irq_mask(tp);
6804
6805 tp->fw_name = rtl_chip_infos[chipset].fw_name;
6806
6807 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
6808 &tp->counters_phys_addr,
6809 GFP_KERNEL);
6810 if (!tp->counters)
6811 return -ENOMEM;
6812
6813 pci_set_drvdata(pdev, dev);
6814
6815 rc = r8169_mdio_register(tp);
6816 if (rc)
6817 return rc;
6818
6819 /* chip gets powered up in rtl_open() */
6820 rtl_pll_power_down(tp);
6821
6822 rc = register_netdev(dev);
6823 if (rc)
6824 goto err_mdio_unregister;
6825
6826 netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
6827 rtl_chip_infos[chipset].name, dev->dev_addr,
6828 (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
6829 pci_irq_vector(pdev, 0));
6830
6831 if (jumbo_max > JUMBO_1K)
6832 netif_info(tp, probe, dev,
6833 "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
6834 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
6835 "ok" : "ko");
6836
6837 if (r8168_check_dash(tp))
6838 rtl8168_driver_start(tp);
6839
6840 if (pci_dev_run_wake(pdev))
6841 pm_runtime_put_sync(&pdev->dev);
6842
6843 return 0;
6844
6845 err_mdio_unregister:
6846 mdiobus_unregister(tp->phydev->mdio.bus);
6847 return rc;
6848 }
6849
6850 static struct pci_driver rtl8169_pci_driver = {
6851 .name = MODULENAME,
6852 .id_table = rtl8169_pci_tbl,
6853 .probe = rtl_init_one,
6854 .remove = rtl_remove_one,
6855 .shutdown = rtl_shutdown,
6856 .driver.pm = RTL8169_PM_OPS,
6857 };
6858
6859 module_pci_driver(rtl8169_pci_driver);
Ubuntu Focal Linux kernel mirror