1 // SPDX-License-Identifier: GPL-2.0-only
3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
7 * Copyright (c) a lot of people too. Please respect their work.
9 * See MAINTAINERS file for support contact information.
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/pci.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/ethtool.h>
20 #include <linux/phy.h>
21 #include <linux/if_vlan.h>
22 #include <linux/crc32.h>
26 #include <linux/tcp.h>
27 #include <linux/interrupt.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/prefetch.h>
31 #include <linux/pci-aspm.h>
32 #include <linux/ipv6.h>
33 #include <net/ip6_checksum.h>
35 #include "r8169_firmware.h"
37 #define MODULENAME "r8169"
39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
47 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
48 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
49 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
50 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
51 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
52 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
53 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
54 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
55 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
56 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
57 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
59 #define R8169_MSG_DEFAULT \
60 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
62 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
63 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
64 #define MC_FILTER_LIMIT 32
66 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
67 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
69 #define R8169_REGS_SIZE 256
70 #define R8169_RX_BUF_SIZE (SZ_16K - 1)
71 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
72 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
73 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
74 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
76 #define RTL_CFG_NO_GBIT 1
78 /* write/read MMIO register */
79 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
80 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
81 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
82 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
83 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
84 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
87 /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */
141 #define JUMBO_1K ETH_DATA_LEN
142 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
143 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
144 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
145 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
147 static const struct {
150 } rtl_chip_infos
[] = {
152 [RTL_GIGA_MAC_VER_02
] = {"RTL8169s" },
153 [RTL_GIGA_MAC_VER_03
] = {"RTL8110s" },
154 [RTL_GIGA_MAC_VER_04
] = {"RTL8169sb/8110sb" },
155 [RTL_GIGA_MAC_VER_05
] = {"RTL8169sc/8110sc" },
156 [RTL_GIGA_MAC_VER_06
] = {"RTL8169sc/8110sc" },
158 [RTL_GIGA_MAC_VER_07
] = {"RTL8102e" },
159 [RTL_GIGA_MAC_VER_08
] = {"RTL8102e" },
160 [RTL_GIGA_MAC_VER_09
] = {"RTL8102e/RTL8103e" },
161 [RTL_GIGA_MAC_VER_10
] = {"RTL8101e" },
162 [RTL_GIGA_MAC_VER_11
] = {"RTL8168b/8111b" },
163 [RTL_GIGA_MAC_VER_12
] = {"RTL8168b/8111b" },
164 [RTL_GIGA_MAC_VER_13
] = {"RTL8101e" },
165 [RTL_GIGA_MAC_VER_14
] = {"RTL8100e" },
166 [RTL_GIGA_MAC_VER_15
] = {"RTL8100e" },
167 [RTL_GIGA_MAC_VER_16
] = {"RTL8101e" },
168 [RTL_GIGA_MAC_VER_17
] = {"RTL8168b/8111b" },
169 [RTL_GIGA_MAC_VER_18
] = {"RTL8168cp/8111cp" },
170 [RTL_GIGA_MAC_VER_19
] = {"RTL8168c/8111c" },
171 [RTL_GIGA_MAC_VER_20
] = {"RTL8168c/8111c" },
172 [RTL_GIGA_MAC_VER_21
] = {"RTL8168c/8111c" },
173 [RTL_GIGA_MAC_VER_22
] = {"RTL8168c/8111c" },
174 [RTL_GIGA_MAC_VER_23
] = {"RTL8168cp/8111cp" },
175 [RTL_GIGA_MAC_VER_24
] = {"RTL8168cp/8111cp" },
176 [RTL_GIGA_MAC_VER_25
] = {"RTL8168d/8111d", FIRMWARE_8168D_1
},
177 [RTL_GIGA_MAC_VER_26
] = {"RTL8168d/8111d", FIRMWARE_8168D_2
},
178 [RTL_GIGA_MAC_VER_27
] = {"RTL8168dp/8111dp" },
179 [RTL_GIGA_MAC_VER_28
] = {"RTL8168dp/8111dp" },
180 [RTL_GIGA_MAC_VER_29
] = {"RTL8105e", FIRMWARE_8105E_1
},
181 [RTL_GIGA_MAC_VER_30
] = {"RTL8105e", FIRMWARE_8105E_1
},
182 [RTL_GIGA_MAC_VER_31
] = {"RTL8168dp/8111dp" },
183 [RTL_GIGA_MAC_VER_32
] = {"RTL8168e/8111e", FIRMWARE_8168E_1
},
184 [RTL_GIGA_MAC_VER_33
] = {"RTL8168e/8111e", FIRMWARE_8168E_2
},
185 [RTL_GIGA_MAC_VER_34
] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3
},
186 [RTL_GIGA_MAC_VER_35
] = {"RTL8168f/8111f", FIRMWARE_8168F_1
},
187 [RTL_GIGA_MAC_VER_36
] = {"RTL8168f/8111f", FIRMWARE_8168F_2
},
188 [RTL_GIGA_MAC_VER_37
] = {"RTL8402", FIRMWARE_8402_1
},
189 [RTL_GIGA_MAC_VER_38
] = {"RTL8411", FIRMWARE_8411_1
},
190 [RTL_GIGA_MAC_VER_39
] = {"RTL8106e", FIRMWARE_8106E_1
},
191 [RTL_GIGA_MAC_VER_40
] = {"RTL8168g/8111g", FIRMWARE_8168G_2
},
192 [RTL_GIGA_MAC_VER_41
] = {"RTL8168g/8111g" },
193 [RTL_GIGA_MAC_VER_42
] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3
},
194 [RTL_GIGA_MAC_VER_43
] = {"RTL8106eus", FIRMWARE_8106E_2
},
195 [RTL_GIGA_MAC_VER_44
] = {"RTL8411b", FIRMWARE_8411_2
},
196 [RTL_GIGA_MAC_VER_45
] = {"RTL8168h/8111h", FIRMWARE_8168H_1
},
197 [RTL_GIGA_MAC_VER_46
] = {"RTL8168h/8111h", FIRMWARE_8168H_2
},
198 [RTL_GIGA_MAC_VER_47
] = {"RTL8107e", FIRMWARE_8107E_1
},
199 [RTL_GIGA_MAC_VER_48
] = {"RTL8107e", FIRMWARE_8107E_2
},
200 [RTL_GIGA_MAC_VER_49
] = {"RTL8168ep/8111ep" },
201 [RTL_GIGA_MAC_VER_50
] = {"RTL8168ep/8111ep" },
202 [RTL_GIGA_MAC_VER_51
] = {"RTL8168ep/8111ep" },
205 static const struct pci_device_id rtl8169_pci_tbl
[] = {
206 { PCI_VDEVICE(REALTEK
, 0x2502) },
207 { PCI_VDEVICE(REALTEK
, 0x2600) },
208 { PCI_VDEVICE(REALTEK
, 0x8129) },
209 { PCI_VDEVICE(REALTEK
, 0x8136), RTL_CFG_NO_GBIT
},
210 { PCI_VDEVICE(REALTEK
, 0x8161) },
211 { PCI_VDEVICE(REALTEK
, 0x8167) },
212 { PCI_VDEVICE(REALTEK
, 0x8168) },
213 { PCI_VDEVICE(NCUBE
, 0x8168) },
214 { PCI_VDEVICE(REALTEK
, 0x8169) },
215 { PCI_VENDOR_ID_DLINK
, 0x4300,
216 PCI_VENDOR_ID_DLINK
, 0x4b10, 0, 0 },
217 { PCI_VDEVICE(DLINK
, 0x4300) },
218 { PCI_VDEVICE(DLINK
, 0x4302) },
219 { PCI_VDEVICE(AT
, 0xc107) },
220 { PCI_VDEVICE(USR
, 0x0116) },
221 { PCI_VENDOR_ID_LINKSYS
, 0x1032, PCI_ANY_ID
, 0x0024 },
222 { 0x0001, 0x8168, PCI_ANY_ID
, 0x2410 },
226 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
233 MAC0
= 0, /* Ethernet hardware address. */
235 MAR0
= 8, /* Multicast filter. */
236 CounterAddrLow
= 0x10,
237 CounterAddrHigh
= 0x14,
238 TxDescStartAddrLow
= 0x20,
239 TxDescStartAddrHigh
= 0x24,
240 TxHDescStartAddrLow
= 0x28,
241 TxHDescStartAddrHigh
= 0x2c,
250 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
251 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
254 #define RX128_INT_EN (1 << 15) /* 8111c and later */
255 #define RX_MULTI_EN (1 << 14) /* 8111c only */
256 #define RXCFG_FIFO_SHIFT 13
257 /* No threshold before first PCI xfer */
258 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
259 #define RX_EARLY_OFF (1 << 11)
260 #define RXCFG_DMA_SHIFT 8
261 /* Unlimited maximum PCI burst. */
262 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
269 #define PME_SIGNAL (1 << 5) /* 8168c and later */
280 #define RTL_COALESCE_MASK 0x0f
281 #define RTL_COALESCE_SHIFT 4
282 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
283 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
285 RxDescAddrLow
= 0xe4,
286 RxDescAddrHigh
= 0xe8,
287 EarlyTxThres
= 0xec, /* 8169. Unit of 32 bytes. */
289 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
291 MaxTxPacketSize
= 0xec, /* 8101/8168. Unit of 128 bytes. */
293 #define TxPacketMax (8064 >> 7)
294 #define EarlySize 0x27
297 FuncEventMask
= 0xf4,
298 FuncPresetState
= 0xf8,
303 FuncForceEvent
= 0xfc,
306 enum rtl8168_8101_registers
{
309 #define CSIAR_FLAG 0x80000000
310 #define CSIAR_WRITE_CMD 0x80000000
311 #define CSIAR_BYTE_ENABLE 0x0000f000
312 #define CSIAR_ADDR_MASK 0x00000fff
315 #define EPHYAR_FLAG 0x80000000
316 #define EPHYAR_WRITE_CMD 0x80000000
317 #define EPHYAR_REG_MASK 0x1f
318 #define EPHYAR_REG_SHIFT 16
319 #define EPHYAR_DATA_MASK 0xffff
321 #define PFM_EN (1 << 6)
322 #define TX_10M_PS_EN (1 << 7)
324 #define FIX_NAK_1 (1 << 4)
325 #define FIX_NAK_2 (1 << 3)
328 #define NOW_IS_OOB (1 << 7)
329 #define TX_EMPTY (1 << 5)
330 #define RX_EMPTY (1 << 4)
331 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
332 #define EN_NDP (1 << 3)
333 #define EN_OOB_RESET (1 << 2)
334 #define LINK_LIST_RDY (1 << 1)
336 #define EFUSEAR_FLAG 0x80000000
337 #define EFUSEAR_WRITE_CMD 0x80000000
338 #define EFUSEAR_READ_CMD 0x00000000
339 #define EFUSEAR_REG_MASK 0x03ff
340 #define EFUSEAR_REG_SHIFT 8
341 #define EFUSEAR_DATA_MASK 0xff
343 #define PFM_D3COLD_EN (1 << 6)
346 enum rtl8168_registers
{
351 #define ERIAR_FLAG 0x80000000
352 #define ERIAR_WRITE_CMD 0x80000000
353 #define ERIAR_READ_CMD 0x00000000
354 #define ERIAR_ADDR_BYTE_ALIGN 4
355 #define ERIAR_TYPE_SHIFT 16
356 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
357 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
358 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
359 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
360 #define ERIAR_MASK_SHIFT 12
361 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
362 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
363 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
364 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
365 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
366 EPHY_RXER_NUM
= 0x7c,
367 OCPDR
= 0xb0, /* OCP GPHY access */
368 #define OCPDR_WRITE_CMD 0x80000000
369 #define OCPDR_READ_CMD 0x00000000
370 #define OCPDR_REG_MASK 0x7f
371 #define OCPDR_GPHY_REG_SHIFT 16
372 #define OCPDR_DATA_MASK 0xffff
374 #define OCPAR_FLAG 0x80000000
375 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
376 #define OCPAR_GPHY_READ_CMD 0x0000f060
378 RDSAR1
= 0xd0, /* 8168c only. Undocumented on 8168dp */
379 MISC
= 0xf0, /* 8168e only. */
380 #define TXPLA_RST (1 << 29)
381 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
382 #define PWM_EN (1 << 22)
383 #define RXDV_GATED_EN (1 << 19)
384 #define EARLY_TALLY_EN (1 << 16)
387 enum rtl_register_content
{
388 /* InterruptStatusBits */
392 TxDescUnavail
= 0x0080,
414 /* TXPoll register p.5 */
415 HPQ
= 0x80, /* Poll cmd on the high prio queue */
416 NPQ
= 0x40, /* Poll cmd on the low prio queue */
417 FSWInt
= 0x01, /* Forced software interrupt */
421 Cfg9346_Unlock
= 0xc0,
426 AcceptBroadcast
= 0x08,
427 AcceptMulticast
= 0x04,
429 AcceptAllPhys
= 0x01,
430 #define RX_CONFIG_ACCEPT_MASK 0x3f
433 TxInterFrameGapShift
= 24,
434 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
436 /* Config1 register p.24 */
439 Speed_down
= (1 << 4),
443 PMEnable
= (1 << 0), /* Power Management Enable */
445 /* Config2 register p. 25 */
446 ClkReqEn
= (1 << 7), /* Clock Request Enable */
447 MSIEnable
= (1 << 5), /* 8169 only. Reserved in the 8168. */
448 PCI_Clock_66MHz
= 0x01,
449 PCI_Clock_33MHz
= 0x00,
451 /* Config3 register p.25 */
452 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
453 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
454 Jumbo_En0
= (1 << 2), /* 8168 only. Reserved in the 8168b */
455 Rdy_to_L23
= (1 << 1), /* L23 Enable */
456 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
458 /* Config4 register */
459 Jumbo_En1
= (1 << 1), /* 8168 only. Reserved in the 8168b */
461 /* Config5 register p.27 */
462 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
463 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
464 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
466 LanWake
= (1 << 1), /* LanWake enable/disable */
467 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
468 ASPM_en
= (1 << 0), /* ASPM enable */
471 EnableBist
= (1 << 15), // 8168 8101
472 Mac_dbgo_oe
= (1 << 14), // 8168 8101
473 Normal_mode
= (1 << 13), // unused
474 Force_half_dup
= (1 << 12), // 8168 8101
475 Force_rxflow_en
= (1 << 11), // 8168 8101
476 Force_txflow_en
= (1 << 10), // 8168 8101
477 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
478 ASF
= (1 << 8), // 8168 8101
479 PktCntrDisable
= (1 << 7), // 8168 8101
480 Mac_dbgo_sel
= 0x001c, // 8168
485 #define INTT_MASK GENMASK(1, 0)
486 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
488 /* rtl8169_PHYstatus */
498 /* ResetCounterCommand */
501 /* DumpCounterCommand */
504 /* magic enable v2 */
505 MagicPacket_v2
= (1 << 16), /* Wake up when receives a Magic Packet */
509 /* First doubleword. */
510 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
511 RingEnd
= (1 << 30), /* End of descriptor ring */
512 FirstFrag
= (1 << 29), /* First segment of a packet */
513 LastFrag
= (1 << 28), /* Final segment of a packet */
517 enum rtl_tx_desc_bit
{
518 /* First doubleword. */
519 TD_LSO
= (1 << 27), /* Large Send Offload */
520 #define TD_MSS_MAX 0x07ffu /* MSS value */
522 /* Second doubleword. */
523 TxVlanTag
= (1 << 17), /* Add VLAN tag */
526 /* 8169, 8168b and 810x except 8102e. */
527 enum rtl_tx_desc_bit_0
{
528 /* First doubleword. */
529 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
530 TD0_TCP_CS
= (1 << 16), /* Calculate TCP/IP checksum */
531 TD0_UDP_CS
= (1 << 17), /* Calculate UDP/IP checksum */
532 TD0_IP_CS
= (1 << 18), /* Calculate IP checksum */
535 /* 8102e, 8168c and beyond. */
536 enum rtl_tx_desc_bit_1
{
537 /* First doubleword. */
538 TD1_GTSENV4
= (1 << 26), /* Giant Send for IPv4 */
539 TD1_GTSENV6
= (1 << 25), /* Giant Send for IPv6 */
540 #define GTTCPHO_SHIFT 18
541 #define GTTCPHO_MAX 0x7f
543 /* Second doubleword. */
544 #define TCPHO_SHIFT 18
545 #define TCPHO_MAX 0x3ff
546 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
547 TD1_IPv6_CS
= (1 << 28), /* Calculate IPv6 checksum */
548 TD1_IPv4_CS
= (1 << 29), /* Calculate IPv4 checksum */
549 TD1_TCP_CS
= (1 << 30), /* Calculate TCP/IP checksum */
550 TD1_UDP_CS
= (1 << 31), /* Calculate UDP/IP checksum */
553 enum rtl_rx_desc_bit
{
555 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
556 PID0
= (1 << 17), /* Protocol ID bit 0/2 */
558 #define RxProtoUDP (PID1)
559 #define RxProtoTCP (PID0)
560 #define RxProtoIP (PID1 | PID0)
561 #define RxProtoMask RxProtoIP
563 IPFail
= (1 << 16), /* IP checksum failed */
564 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
565 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
566 RxVlanTag
= (1 << 16), /* VLAN tag available */
569 #define RsvdMask 0x3fffc000
571 #define RTL_GSO_MAX_SIZE_V1 32000
572 #define RTL_GSO_MAX_SEGS_V1 24
573 #define RTL_GSO_MAX_SIZE_V2 64000
574 #define RTL_GSO_MAX_SEGS_V2 64
593 struct rtl8169_counters
{
600 __le32 tx_one_collision
;
601 __le32 tx_multi_collision
;
609 struct rtl8169_tc_offsets
{
612 __le32 tx_multi_collision
;
617 RTL_FLAG_TASK_ENABLED
= 0,
618 RTL_FLAG_TASK_RESET_PENDING
,
622 struct rtl8169_stats
{
625 struct u64_stats_sync syncp
;
628 struct rtl8169_private
{
629 void __iomem
*mmio_addr
; /* memory map physical address */
630 struct pci_dev
*pci_dev
;
631 struct net_device
*dev
;
632 struct phy_device
*phydev
;
633 struct napi_struct napi
;
635 enum mac_version mac_version
;
636 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
637 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
639 struct rtl8169_stats rx_stats
;
640 struct rtl8169_stats tx_stats
;
641 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
642 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
643 dma_addr_t TxPhyAddr
;
644 dma_addr_t RxPhyAddr
;
645 struct page
*Rx_databuff
[NUM_RX_DESC
]; /* Rx data buffers */
646 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
652 DECLARE_BITMAP(flags
, RTL_FLAG_MAX
);
654 struct work_struct work
;
657 unsigned irq_enabled
:1;
658 unsigned supports_gmii
:1;
659 unsigned aspm_manageable
:1;
660 dma_addr_t counters_phys_addr
;
661 struct rtl8169_counters
*counters
;
662 struct rtl8169_tc_offsets tc_offset
;
666 struct rtl_fw
*rtl_fw
;
671 typedef void (*rtl_generic_fct
)(struct rtl8169_private
*tp
);
673 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
674 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
675 module_param_named(debug
, debug
.msg_enable
, int, 0);
676 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
677 MODULE_SOFTDEP("pre: realtek");
678 MODULE_LICENSE("GPL");
679 MODULE_FIRMWARE(FIRMWARE_8168D_1
);
680 MODULE_FIRMWARE(FIRMWARE_8168D_2
);
681 MODULE_FIRMWARE(FIRMWARE_8168E_1
);
682 MODULE_FIRMWARE(FIRMWARE_8168E_2
);
683 MODULE_FIRMWARE(FIRMWARE_8168E_3
);
684 MODULE_FIRMWARE(FIRMWARE_8105E_1
);
685 MODULE_FIRMWARE(FIRMWARE_8168F_1
);
686 MODULE_FIRMWARE(FIRMWARE_8168F_2
);
687 MODULE_FIRMWARE(FIRMWARE_8402_1
);
688 MODULE_FIRMWARE(FIRMWARE_8411_1
);
689 MODULE_FIRMWARE(FIRMWARE_8411_2
);
690 MODULE_FIRMWARE(FIRMWARE_8106E_1
);
691 MODULE_FIRMWARE(FIRMWARE_8106E_2
);
692 MODULE_FIRMWARE(FIRMWARE_8168G_2
);
693 MODULE_FIRMWARE(FIRMWARE_8168G_3
);
694 MODULE_FIRMWARE(FIRMWARE_8168H_1
);
695 MODULE_FIRMWARE(FIRMWARE_8168H_2
);
696 MODULE_FIRMWARE(FIRMWARE_8107E_1
);
697 MODULE_FIRMWARE(FIRMWARE_8107E_2
);
699 static inline struct device
*tp_to_dev(struct rtl8169_private
*tp
)
701 return &tp
->pci_dev
->dev
;
704 static void rtl_lock_work(struct rtl8169_private
*tp
)
706 mutex_lock(&tp
->wk
.mutex
);
709 static void rtl_unlock_work(struct rtl8169_private
*tp
)
711 mutex_unlock(&tp
->wk
.mutex
);
714 static void rtl_lock_config_regs(struct rtl8169_private
*tp
)
716 RTL_W8(tp
, Cfg9346
, Cfg9346_Lock
);
719 static void rtl_unlock_config_regs(struct rtl8169_private
*tp
)
721 RTL_W8(tp
, Cfg9346
, Cfg9346_Unlock
);
724 static void rtl_tx_performance_tweak(struct rtl8169_private
*tp
, u16 force
)
726 pcie_capability_clear_and_set_word(tp
->pci_dev
, PCI_EXP_DEVCTL
,
727 PCI_EXP_DEVCTL_READRQ
, force
);
730 static bool rtl_is_8168evl_up(struct rtl8169_private
*tp
)
732 return tp
->mac_version
>= RTL_GIGA_MAC_VER_34
&&
733 tp
->mac_version
!= RTL_GIGA_MAC_VER_39
&&
734 tp
->mac_version
<= RTL_GIGA_MAC_VER_51
;
737 static bool rtl_supports_eee(struct rtl8169_private
*tp
)
739 return tp
->mac_version
>= RTL_GIGA_MAC_VER_34
&&
740 tp
->mac_version
!= RTL_GIGA_MAC_VER_37
&&
741 tp
->mac_version
!= RTL_GIGA_MAC_VER_39
;
744 static void rtl_read_mac_from_reg(struct rtl8169_private
*tp
, u8
*mac
, int reg
)
748 for (i
= 0; i
< ETH_ALEN
; i
++)
749 mac
[i
] = RTL_R8(tp
, reg
+ i
);
753 bool (*check
)(struct rtl8169_private
*);
757 static void rtl_udelay(unsigned int d
)
762 static bool rtl_loop_wait(struct rtl8169_private
*tp
, const struct rtl_cond
*c
,
763 void (*delay
)(unsigned int), unsigned int d
, int n
,
768 for (i
= 0; i
< n
; i
++) {
769 if (c
->check(tp
) == high
)
773 netif_err(tp
, drv
, tp
->dev
, "%s == %d (loop: %d, delay: %d).\n",
774 c
->msg
, !high
, n
, d
);
778 static bool rtl_udelay_loop_wait_high(struct rtl8169_private
*tp
,
779 const struct rtl_cond
*c
,
780 unsigned int d
, int n
)
782 return rtl_loop_wait(tp
, c
, rtl_udelay
, d
, n
, true);
785 static bool rtl_udelay_loop_wait_low(struct rtl8169_private
*tp
,
786 const struct rtl_cond
*c
,
787 unsigned int d
, int n
)
789 return rtl_loop_wait(tp
, c
, rtl_udelay
, d
, n
, false);
792 static bool rtl_msleep_loop_wait_high(struct rtl8169_private
*tp
,
793 const struct rtl_cond
*c
,
794 unsigned int d
, int n
)
796 return rtl_loop_wait(tp
, c
, msleep
, d
, n
, true);
799 static bool rtl_msleep_loop_wait_low(struct rtl8169_private
*tp
,
800 const struct rtl_cond
*c
,
801 unsigned int d
, int n
)
803 return rtl_loop_wait(tp
, c
, msleep
, d
, n
, false);
806 #define DECLARE_RTL_COND(name) \
807 static bool name ## _check(struct rtl8169_private *); \
809 static const struct rtl_cond name = { \
810 .check = name ## _check, \
814 static bool name ## _check(struct rtl8169_private *tp)
816 static bool rtl_ocp_reg_failure(struct rtl8169_private
*tp
, u32 reg
)
818 if (reg
& 0xffff0001) {
819 netif_err(tp
, drv
, tp
->dev
, "Invalid ocp reg %x!\n", reg
);
825 DECLARE_RTL_COND(rtl_ocp_gphy_cond
)
827 return RTL_R32(tp
, GPHY_OCP
) & OCPAR_FLAG
;
830 static void r8168_phy_ocp_write(struct rtl8169_private
*tp
, u32 reg
, u32 data
)
832 if (rtl_ocp_reg_failure(tp
, reg
))
835 RTL_W32(tp
, GPHY_OCP
, OCPAR_FLAG
| (reg
<< 15) | data
);
837 rtl_udelay_loop_wait_low(tp
, &rtl_ocp_gphy_cond
, 25, 10);
840 static int r8168_phy_ocp_read(struct rtl8169_private
*tp
, u32 reg
)
842 if (rtl_ocp_reg_failure(tp
, reg
))
845 RTL_W32(tp
, GPHY_OCP
, reg
<< 15);
847 return rtl_udelay_loop_wait_high(tp
, &rtl_ocp_gphy_cond
, 25, 10) ?
848 (RTL_R32(tp
, GPHY_OCP
) & 0xffff) : -ETIMEDOUT
;
851 static void r8168_mac_ocp_write(struct rtl8169_private
*tp
, u32 reg
, u32 data
)
853 if (rtl_ocp_reg_failure(tp
, reg
))
856 RTL_W32(tp
, OCPDR
, OCPAR_FLAG
| (reg
<< 15) | data
);
859 static u16
r8168_mac_ocp_read(struct rtl8169_private
*tp
, u32 reg
)
861 if (rtl_ocp_reg_failure(tp
, reg
))
864 RTL_W32(tp
, OCPDR
, reg
<< 15);
866 return RTL_R32(tp
, OCPDR
);
869 static void r8168_mac_ocp_modify(struct rtl8169_private
*tp
, u32 reg
, u16 mask
,
872 u16 data
= r8168_mac_ocp_read(tp
, reg
);
874 r8168_mac_ocp_write(tp
, reg
, (data
& ~mask
) | set
);
877 #define OCP_STD_PHY_BASE 0xa400
879 static void r8168g_mdio_write(struct rtl8169_private
*tp
, int reg
, int value
)
882 tp
->ocp_base
= value
? value
<< 4 : OCP_STD_PHY_BASE
;
886 if (tp
->ocp_base
!= OCP_STD_PHY_BASE
)
889 r8168_phy_ocp_write(tp
, tp
->ocp_base
+ reg
* 2, value
);
892 static int r8168g_mdio_read(struct rtl8169_private
*tp
, int reg
)
894 if (tp
->ocp_base
!= OCP_STD_PHY_BASE
)
897 return r8168_phy_ocp_read(tp
, tp
->ocp_base
+ reg
* 2);
900 static void mac_mcu_write(struct rtl8169_private
*tp
, int reg
, int value
)
903 tp
->ocp_base
= value
<< 4;
907 r8168_mac_ocp_write(tp
, tp
->ocp_base
+ reg
, value
);
910 static int mac_mcu_read(struct rtl8169_private
*tp
, int reg
)
912 return r8168_mac_ocp_read(tp
, tp
->ocp_base
+ reg
);
915 DECLARE_RTL_COND(rtl_phyar_cond
)
917 return RTL_R32(tp
, PHYAR
) & 0x80000000;
920 static void r8169_mdio_write(struct rtl8169_private
*tp
, int reg
, int value
)
922 RTL_W32(tp
, PHYAR
, 0x80000000 | (reg
& 0x1f) << 16 | (value
& 0xffff));
924 rtl_udelay_loop_wait_low(tp
, &rtl_phyar_cond
, 25, 20);
926 * According to hardware specs a 20us delay is required after write
927 * complete indication, but before sending next command.
932 static int r8169_mdio_read(struct rtl8169_private
*tp
, int reg
)
936 RTL_W32(tp
, PHYAR
, 0x0 | (reg
& 0x1f) << 16);
938 value
= rtl_udelay_loop_wait_high(tp
, &rtl_phyar_cond
, 25, 20) ?
939 RTL_R32(tp
, PHYAR
) & 0xffff : -ETIMEDOUT
;
942 * According to hardware specs a 20us delay is required after read
943 * complete indication, but before sending next command.
950 DECLARE_RTL_COND(rtl_ocpar_cond
)
952 return RTL_R32(tp
, OCPAR
) & OCPAR_FLAG
;
955 static void r8168dp_1_mdio_access(struct rtl8169_private
*tp
, int reg
, u32 data
)
957 RTL_W32(tp
, OCPDR
, data
| ((reg
& OCPDR_REG_MASK
) << OCPDR_GPHY_REG_SHIFT
));
958 RTL_W32(tp
, OCPAR
, OCPAR_GPHY_WRITE_CMD
);
959 RTL_W32(tp
, EPHY_RXER_NUM
, 0);
961 rtl_udelay_loop_wait_low(tp
, &rtl_ocpar_cond
, 1000, 100);
964 static void r8168dp_1_mdio_write(struct rtl8169_private
*tp
, int reg
, int value
)
966 r8168dp_1_mdio_access(tp
, reg
,
967 OCPDR_WRITE_CMD
| (value
& OCPDR_DATA_MASK
));
970 static int r8168dp_1_mdio_read(struct rtl8169_private
*tp
, int reg
)
972 r8168dp_1_mdio_access(tp
, reg
, OCPDR_READ_CMD
);
975 RTL_W32(tp
, OCPAR
, OCPAR_GPHY_READ_CMD
);
976 RTL_W32(tp
, EPHY_RXER_NUM
, 0);
978 return rtl_udelay_loop_wait_high(tp
, &rtl_ocpar_cond
, 1000, 100) ?
979 RTL_R32(tp
, OCPDR
) & OCPDR_DATA_MASK
: -ETIMEDOUT
;
982 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
984 static void r8168dp_2_mdio_start(struct rtl8169_private
*tp
)
986 RTL_W32(tp
, 0xd0, RTL_R32(tp
, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT
);
989 static void r8168dp_2_mdio_stop(struct rtl8169_private
*tp
)
991 RTL_W32(tp
, 0xd0, RTL_R32(tp
, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT
);
994 static void r8168dp_2_mdio_write(struct rtl8169_private
*tp
, int reg
, int value
)
996 r8168dp_2_mdio_start(tp
);
998 r8169_mdio_write(tp
, reg
, value
);
1000 r8168dp_2_mdio_stop(tp
);
1003 static int r8168dp_2_mdio_read(struct rtl8169_private
*tp
, int reg
)
1007 r8168dp_2_mdio_start(tp
);
1009 value
= r8169_mdio_read(tp
, reg
);
1011 r8168dp_2_mdio_stop(tp
);
1016 static void rtl_writephy(struct rtl8169_private
*tp
, int location
, int val
)
1018 switch (tp
->mac_version
) {
1019 case RTL_GIGA_MAC_VER_27
:
1020 r8168dp_1_mdio_write(tp
, location
, val
);
1022 case RTL_GIGA_MAC_VER_28
:
1023 case RTL_GIGA_MAC_VER_31
:
1024 r8168dp_2_mdio_write(tp
, location
, val
);
1026 case RTL_GIGA_MAC_VER_40
... RTL_GIGA_MAC_VER_51
:
1027 r8168g_mdio_write(tp
, location
, val
);
1030 r8169_mdio_write(tp
, location
, val
);
1035 static int rtl_readphy(struct rtl8169_private
*tp
, int location
)
1037 switch (tp
->mac_version
) {
1038 case RTL_GIGA_MAC_VER_27
:
1039 return r8168dp_1_mdio_read(tp
, location
);
1040 case RTL_GIGA_MAC_VER_28
:
1041 case RTL_GIGA_MAC_VER_31
:
1042 return r8168dp_2_mdio_read(tp
, location
);
1043 case RTL_GIGA_MAC_VER_40
... RTL_GIGA_MAC_VER_51
:
1044 return r8168g_mdio_read(tp
, location
);
1046 return r8169_mdio_read(tp
, location
);
1050 static void rtl_patchphy(struct rtl8169_private
*tp
, int reg_addr
, int value
)
1052 rtl_writephy(tp
, reg_addr
, rtl_readphy(tp
, reg_addr
) | value
);
1055 static void rtl_w0w1_phy(struct rtl8169_private
*tp
, int reg_addr
, int p
, int m
)
1059 val
= rtl_readphy(tp
, reg_addr
);
1060 rtl_writephy(tp
, reg_addr
, (val
& ~m
) | p
);
1063 DECLARE_RTL_COND(rtl_ephyar_cond
)
1065 return RTL_R32(tp
, EPHYAR
) & EPHYAR_FLAG
;
1068 static void rtl_ephy_write(struct rtl8169_private
*tp
, int reg_addr
, int value
)
1070 RTL_W32(tp
, EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
1071 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
1073 rtl_udelay_loop_wait_low(tp
, &rtl_ephyar_cond
, 10, 100);
1078 static u16
rtl_ephy_read(struct rtl8169_private
*tp
, int reg_addr
)
1080 RTL_W32(tp
, EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
1082 return rtl_udelay_loop_wait_high(tp
, &rtl_ephyar_cond
, 10, 100) ?
1083 RTL_R32(tp
, EPHYAR
) & EPHYAR_DATA_MASK
: ~0;
1086 DECLARE_RTL_COND(rtl_eriar_cond
)
1088 return RTL_R32(tp
, ERIAR
) & ERIAR_FLAG
;
1091 static void _rtl_eri_write(struct rtl8169_private
*tp
, int addr
, u32 mask
,
1094 BUG_ON((addr
& 3) || (mask
== 0));
1095 RTL_W32(tp
, ERIDR
, val
);
1096 RTL_W32(tp
, ERIAR
, ERIAR_WRITE_CMD
| type
| mask
| addr
);
1098 rtl_udelay_loop_wait_low(tp
, &rtl_eriar_cond
, 100, 100);
1101 static void rtl_eri_write(struct rtl8169_private
*tp
, int addr
, u32 mask
,
1104 _rtl_eri_write(tp
, addr
, mask
, val
, ERIAR_EXGMAC
);
1107 static u32
_rtl_eri_read(struct rtl8169_private
*tp
, int addr
, int type
)
1109 RTL_W32(tp
, ERIAR
, ERIAR_READ_CMD
| type
| ERIAR_MASK_1111
| addr
);
1111 return rtl_udelay_loop_wait_high(tp
, &rtl_eriar_cond
, 100, 100) ?
1112 RTL_R32(tp
, ERIDR
) : ~0;
1115 static u32
rtl_eri_read(struct rtl8169_private
*tp
, int addr
)
1117 return _rtl_eri_read(tp
, addr
, ERIAR_EXGMAC
);
1120 static void rtl_w0w1_eri(struct rtl8169_private
*tp
, int addr
, u32 mask
, u32 p
,
1125 val
= rtl_eri_read(tp
, addr
);
1126 rtl_eri_write(tp
, addr
, mask
, (val
& ~m
) | p
);
1129 static void rtl_eri_set_bits(struct rtl8169_private
*tp
, int addr
, u32 mask
,
1132 rtl_w0w1_eri(tp
, addr
, mask
, p
, 0);
1135 static void rtl_eri_clear_bits(struct rtl8169_private
*tp
, int addr
, u32 mask
,
1138 rtl_w0w1_eri(tp
, addr
, mask
, 0, m
);
1141 static u32
r8168dp_ocp_read(struct rtl8169_private
*tp
, u8 mask
, u16 reg
)
1143 RTL_W32(tp
, OCPAR
, ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
1144 return rtl_udelay_loop_wait_high(tp
, &rtl_ocpar_cond
, 100, 20) ?
1145 RTL_R32(tp
, OCPDR
) : ~0;
1148 static u32
r8168ep_ocp_read(struct rtl8169_private
*tp
, u8 mask
, u16 reg
)
1150 return _rtl_eri_read(tp
, reg
, ERIAR_OOB
);
1153 static void r8168dp_ocp_write(struct rtl8169_private
*tp
, u8 mask
, u16 reg
,
1156 RTL_W32(tp
, OCPDR
, data
);
1157 RTL_W32(tp
, OCPAR
, OCPAR_FLAG
| ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
1158 rtl_udelay_loop_wait_low(tp
, &rtl_ocpar_cond
, 100, 20);
1161 static void r8168ep_ocp_write(struct rtl8169_private
*tp
, u8 mask
, u16 reg
,
1164 _rtl_eri_write(tp
, reg
, ((u32
)mask
& 0x0f) << ERIAR_MASK_SHIFT
,
1168 static void r8168dp_oob_notify(struct rtl8169_private
*tp
, u8 cmd
)
1170 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_0001
, cmd
);
1172 r8168dp_ocp_write(tp
, 0x1, 0x30, 0x00000001);
1175 #define OOB_CMD_RESET 0x00
1176 #define OOB_CMD_DRIVER_START 0x05
1177 #define OOB_CMD_DRIVER_STOP 0x06
1179 static u16
rtl8168_get_ocp_reg(struct rtl8169_private
*tp
)
1181 return (tp
->mac_version
== RTL_GIGA_MAC_VER_31
) ? 0xb8 : 0x10;
1184 DECLARE_RTL_COND(rtl_dp_ocp_read_cond
)
1188 reg
= rtl8168_get_ocp_reg(tp
);
1190 return r8168dp_ocp_read(tp
, 0x0f, reg
) & 0x00000800;
1193 DECLARE_RTL_COND(rtl_ep_ocp_read_cond
)
1195 return r8168ep_ocp_read(tp
, 0x0f, 0x124) & 0x00000001;
1198 DECLARE_RTL_COND(rtl_ocp_tx_cond
)
1200 return RTL_R8(tp
, IBISR0
) & 0x20;
1203 static void rtl8168ep_stop_cmac(struct rtl8169_private
*tp
)
1205 RTL_W8(tp
, IBCR2
, RTL_R8(tp
, IBCR2
) & ~0x01);
1206 rtl_msleep_loop_wait_high(tp
, &rtl_ocp_tx_cond
, 50, 2000);
1207 RTL_W8(tp
, IBISR0
, RTL_R8(tp
, IBISR0
) | 0x20);
1208 RTL_W8(tp
, IBCR0
, RTL_R8(tp
, IBCR0
) & ~0x01);
1211 static void rtl8168dp_driver_start(struct rtl8169_private
*tp
)
1213 r8168dp_oob_notify(tp
, OOB_CMD_DRIVER_START
);
1214 rtl_msleep_loop_wait_high(tp
, &rtl_dp_ocp_read_cond
, 10, 10);
1217 static void rtl8168ep_driver_start(struct rtl8169_private
*tp
)
1219 r8168ep_ocp_write(tp
, 0x01, 0x180, OOB_CMD_DRIVER_START
);
1220 r8168ep_ocp_write(tp
, 0x01, 0x30,
1221 r8168ep_ocp_read(tp
, 0x01, 0x30) | 0x01);
1222 rtl_msleep_loop_wait_high(tp
, &rtl_ep_ocp_read_cond
, 10, 10);
1225 static void rtl8168_driver_start(struct rtl8169_private
*tp
)
1227 switch (tp
->mac_version
) {
1228 case RTL_GIGA_MAC_VER_27
:
1229 case RTL_GIGA_MAC_VER_28
:
1230 case RTL_GIGA_MAC_VER_31
:
1231 rtl8168dp_driver_start(tp
);
1233 case RTL_GIGA_MAC_VER_49
:
1234 case RTL_GIGA_MAC_VER_50
:
1235 case RTL_GIGA_MAC_VER_51
:
1236 rtl8168ep_driver_start(tp
);
1244 static void rtl8168dp_driver_stop(struct rtl8169_private
*tp
)
1246 r8168dp_oob_notify(tp
, OOB_CMD_DRIVER_STOP
);
1247 rtl_msleep_loop_wait_low(tp
, &rtl_dp_ocp_read_cond
, 10, 10);
1250 static void rtl8168ep_driver_stop(struct rtl8169_private
*tp
)
1252 rtl8168ep_stop_cmac(tp
);
1253 r8168ep_ocp_write(tp
, 0x01, 0x180, OOB_CMD_DRIVER_STOP
);
1254 r8168ep_ocp_write(tp
, 0x01, 0x30,
1255 r8168ep_ocp_read(tp
, 0x01, 0x30) | 0x01);
1256 rtl_msleep_loop_wait_low(tp
, &rtl_ep_ocp_read_cond
, 10, 10);
1259 static void rtl8168_driver_stop(struct rtl8169_private
*tp
)
1261 switch (tp
->mac_version
) {
1262 case RTL_GIGA_MAC_VER_27
:
1263 case RTL_GIGA_MAC_VER_28
:
1264 case RTL_GIGA_MAC_VER_31
:
1265 rtl8168dp_driver_stop(tp
);
1267 case RTL_GIGA_MAC_VER_49
:
1268 case RTL_GIGA_MAC_VER_50
:
1269 case RTL_GIGA_MAC_VER_51
:
1270 rtl8168ep_driver_stop(tp
);
1278 static bool r8168dp_check_dash(struct rtl8169_private
*tp
)
1280 u16 reg
= rtl8168_get_ocp_reg(tp
);
1282 return !!(r8168dp_ocp_read(tp
, 0x0f, reg
) & 0x00008000);
1285 static bool r8168ep_check_dash(struct rtl8169_private
*tp
)
1287 return !!(r8168ep_ocp_read(tp
, 0x0f, 0x128) & 0x00000001);
1290 static bool r8168_check_dash(struct rtl8169_private
*tp
)
1292 switch (tp
->mac_version
) {
1293 case RTL_GIGA_MAC_VER_27
:
1294 case RTL_GIGA_MAC_VER_28
:
1295 case RTL_GIGA_MAC_VER_31
:
1296 return r8168dp_check_dash(tp
);
1297 case RTL_GIGA_MAC_VER_49
:
1298 case RTL_GIGA_MAC_VER_50
:
1299 case RTL_GIGA_MAC_VER_51
:
1300 return r8168ep_check_dash(tp
);
1306 static void rtl_reset_packet_filter(struct rtl8169_private
*tp
)
1308 rtl_eri_clear_bits(tp
, 0xdc, ERIAR_MASK_0001
, BIT(0));
1309 rtl_eri_set_bits(tp
, 0xdc, ERIAR_MASK_0001
, BIT(0));
1312 DECLARE_RTL_COND(rtl_efusear_cond
)
1314 return RTL_R32(tp
, EFUSEAR
) & EFUSEAR_FLAG
;
1317 static u8
rtl8168d_efuse_read(struct rtl8169_private
*tp
, int reg_addr
)
1319 RTL_W32(tp
, EFUSEAR
, (reg_addr
& EFUSEAR_REG_MASK
) << EFUSEAR_REG_SHIFT
);
1321 return rtl_udelay_loop_wait_high(tp
, &rtl_efusear_cond
, 100, 300) ?
1322 RTL_R32(tp
, EFUSEAR
) & EFUSEAR_DATA_MASK
: ~0;
1325 static u32
rtl_get_events(struct rtl8169_private
*tp
)
1327 return RTL_R16(tp
, IntrStatus
);
1330 static void rtl_ack_events(struct rtl8169_private
*tp
, u32 bits
)
1332 RTL_W16(tp
, IntrStatus
, bits
);
1335 static void rtl_irq_disable(struct rtl8169_private
*tp
)
1337 RTL_W16(tp
, IntrMask
, 0);
1338 tp
->irq_enabled
= 0;
1341 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1342 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1343 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1345 static void rtl_irq_enable(struct rtl8169_private
*tp
)
1347 tp
->irq_enabled
= 1;
1348 RTL_W16(tp
, IntrMask
, tp
->irq_mask
);
1351 static void rtl8169_irq_mask_and_ack(struct rtl8169_private
*tp
)
1353 rtl_irq_disable(tp
);
1354 rtl_ack_events(tp
, 0xffffffff);
1356 RTL_R8(tp
, ChipCmd
);
1359 static void rtl_link_chg_patch(struct rtl8169_private
*tp
)
1361 struct net_device
*dev
= tp
->dev
;
1362 struct phy_device
*phydev
= tp
->phydev
;
1364 if (!netif_running(dev
))
1367 if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
||
1368 tp
->mac_version
== RTL_GIGA_MAC_VER_38
) {
1369 if (phydev
->speed
== SPEED_1000
) {
1370 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x00000011);
1371 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x00000005);
1372 } else if (phydev
->speed
== SPEED_100
) {
1373 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x0000001f);
1374 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x00000005);
1376 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x0000001f);
1377 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x0000003f);
1379 rtl_reset_packet_filter(tp
);
1380 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_35
||
1381 tp
->mac_version
== RTL_GIGA_MAC_VER_36
) {
1382 if (phydev
->speed
== SPEED_1000
) {
1383 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x00000011);
1384 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x00000005);
1386 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x0000001f);
1387 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x0000003f);
1389 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_37
) {
1390 if (phydev
->speed
== SPEED_10
) {
1391 rtl_eri_write(tp
, 0x1d0, ERIAR_MASK_0011
, 0x4d02);
1392 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_0011
, 0x0060a);
1394 rtl_eri_write(tp
, 0x1d0, ERIAR_MASK_0011
, 0x0000);
1399 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1401 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1403 struct rtl8169_private
*tp
= netdev_priv(dev
);
1406 wol
->supported
= WAKE_ANY
;
1407 wol
->wolopts
= tp
->saved_wolopts
;
1408 rtl_unlock_work(tp
);
1411 static void __rtl8169_set_wol(struct rtl8169_private
*tp
, u32 wolopts
)
1413 unsigned int i
, tmp
;
1414 static const struct {
1419 { WAKE_PHY
, Config3
, LinkUp
},
1420 { WAKE_UCAST
, Config5
, UWF
},
1421 { WAKE_BCAST
, Config5
, BWF
},
1422 { WAKE_MCAST
, Config5
, MWF
},
1423 { WAKE_ANY
, Config5
, LanWake
},
1424 { WAKE_MAGIC
, Config3
, MagicPacket
}
1428 rtl_unlock_config_regs(tp
);
1430 if (rtl_is_8168evl_up(tp
)) {
1431 tmp
= ARRAY_SIZE(cfg
) - 1;
1432 if (wolopts
& WAKE_MAGIC
)
1433 rtl_eri_set_bits(tp
, 0x0dc, ERIAR_MASK_0100
,
1436 rtl_eri_clear_bits(tp
, 0x0dc, ERIAR_MASK_0100
,
1439 tmp
= ARRAY_SIZE(cfg
);
1442 for (i
= 0; i
< tmp
; i
++) {
1443 options
= RTL_R8(tp
, cfg
[i
].reg
) & ~cfg
[i
].mask
;
1444 if (wolopts
& cfg
[i
].opt
)
1445 options
|= cfg
[i
].mask
;
1446 RTL_W8(tp
, cfg
[i
].reg
, options
);
1449 switch (tp
->mac_version
) {
1450 case RTL_GIGA_MAC_VER_02
... RTL_GIGA_MAC_VER_06
:
1451 options
= RTL_R8(tp
, Config1
) & ~PMEnable
;
1453 options
|= PMEnable
;
1454 RTL_W8(tp
, Config1
, options
);
1456 case RTL_GIGA_MAC_VER_34
:
1457 case RTL_GIGA_MAC_VER_37
:
1458 case RTL_GIGA_MAC_VER_39
... RTL_GIGA_MAC_VER_51
:
1459 options
= RTL_R8(tp
, Config2
) & ~PME_SIGNAL
;
1461 options
|= PME_SIGNAL
;
1462 RTL_W8(tp
, Config2
, options
);
1468 rtl_lock_config_regs(tp
);
1470 device_set_wakeup_enable(tp_to_dev(tp
), wolopts
);
1473 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1475 struct rtl8169_private
*tp
= netdev_priv(dev
);
1476 struct device
*d
= tp_to_dev(tp
);
1478 if (wol
->wolopts
& ~WAKE_ANY
)
1481 pm_runtime_get_noresume(d
);
1485 tp
->saved_wolopts
= wol
->wolopts
;
1487 if (pm_runtime_active(d
))
1488 __rtl8169_set_wol(tp
, tp
->saved_wolopts
);
1490 rtl_unlock_work(tp
);
1492 pm_runtime_put_noidle(d
);
1497 static void rtl8169_get_drvinfo(struct net_device
*dev
,
1498 struct ethtool_drvinfo
*info
)
1500 struct rtl8169_private
*tp
= netdev_priv(dev
);
1501 struct rtl_fw
*rtl_fw
= tp
->rtl_fw
;
1503 strlcpy(info
->driver
, MODULENAME
, sizeof(info
->driver
));
1504 strlcpy(info
->bus_info
, pci_name(tp
->pci_dev
), sizeof(info
->bus_info
));
1505 BUILD_BUG_ON(sizeof(info
->fw_version
) < sizeof(rtl_fw
->version
));
1507 strlcpy(info
->fw_version
, rtl_fw
->version
,
1508 sizeof(info
->fw_version
));
1511 static int rtl8169_get_regs_len(struct net_device
*dev
)
1513 return R8169_REGS_SIZE
;
1516 static netdev_features_t
rtl8169_fix_features(struct net_device
*dev
,
1517 netdev_features_t features
)
1519 struct rtl8169_private
*tp
= netdev_priv(dev
);
1521 if (dev
->mtu
> TD_MSS_MAX
)
1522 features
&= ~NETIF_F_ALL_TSO
;
1524 if (dev
->mtu
> JUMBO_1K
&&
1525 tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
1526 features
&= ~NETIF_F_IP_CSUM
;
1531 static int rtl8169_set_features(struct net_device
*dev
,
1532 netdev_features_t features
)
1534 struct rtl8169_private
*tp
= netdev_priv(dev
);
1539 rx_config
= RTL_R32(tp
, RxConfig
);
1540 if (features
& NETIF_F_RXALL
)
1541 rx_config
|= (AcceptErr
| AcceptRunt
);
1543 rx_config
&= ~(AcceptErr
| AcceptRunt
);
1545 RTL_W32(tp
, RxConfig
, rx_config
);
1547 if (features
& NETIF_F_RXCSUM
)
1548 tp
->cp_cmd
|= RxChkSum
;
1550 tp
->cp_cmd
&= ~RxChkSum
;
1552 if (features
& NETIF_F_HW_VLAN_CTAG_RX
)
1553 tp
->cp_cmd
|= RxVlan
;
1555 tp
->cp_cmd
&= ~RxVlan
;
1557 RTL_W16(tp
, CPlusCmd
, tp
->cp_cmd
);
1558 RTL_R16(tp
, CPlusCmd
);
1560 rtl_unlock_work(tp
);
1565 static inline u32
rtl8169_tx_vlan_tag(struct sk_buff
*skb
)
1567 return (skb_vlan_tag_present(skb
)) ?
1568 TxVlanTag
| swab16(skb_vlan_tag_get(skb
)) : 0x00;
1571 static void rtl8169_rx_vlan_tag(struct RxDesc
*desc
, struct sk_buff
*skb
)
1573 u32 opts2
= le32_to_cpu(desc
->opts2
);
1575 if (opts2
& RxVlanTag
)
1576 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
), swab16(opts2
& 0xffff));
1579 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1582 struct rtl8169_private
*tp
= netdev_priv(dev
);
1583 u32 __iomem
*data
= tp
->mmio_addr
;
1588 for (i
= 0; i
< R8169_REGS_SIZE
; i
+= 4)
1589 memcpy_fromio(dw
++, data
++, 4);
1590 rtl_unlock_work(tp
);
1593 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
1595 struct rtl8169_private
*tp
= netdev_priv(dev
);
1597 return tp
->msg_enable
;
1600 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
1602 struct rtl8169_private
*tp
= netdev_priv(dev
);
1604 tp
->msg_enable
= value
;
1607 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
1614 "tx_single_collisions",
1615 "tx_multi_collisions",
1623 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
1627 return ARRAY_SIZE(rtl8169_gstrings
);
1633 DECLARE_RTL_COND(rtl_counters_cond
)
1635 return RTL_R32(tp
, CounterAddrLow
) & (CounterReset
| CounterDump
);
1638 static bool rtl8169_do_counters(struct rtl8169_private
*tp
, u32 counter_cmd
)
1640 dma_addr_t paddr
= tp
->counters_phys_addr
;
1643 RTL_W32(tp
, CounterAddrHigh
, (u64
)paddr
>> 32);
1644 RTL_R32(tp
, CounterAddrHigh
);
1645 cmd
= (u64
)paddr
& DMA_BIT_MASK(32);
1646 RTL_W32(tp
, CounterAddrLow
, cmd
);
1647 RTL_W32(tp
, CounterAddrLow
, cmd
| counter_cmd
);
1649 return rtl_udelay_loop_wait_low(tp
, &rtl_counters_cond
, 10, 1000);
1652 static bool rtl8169_reset_counters(struct rtl8169_private
*tp
)
1655 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1658 if (tp
->mac_version
< RTL_GIGA_MAC_VER_19
)
1661 return rtl8169_do_counters(tp
, CounterReset
);
1664 static bool rtl8169_update_counters(struct rtl8169_private
*tp
)
1666 u8 val
= RTL_R8(tp
, ChipCmd
);
1669 * Some chips are unable to dump tally counters when the receiver
1670 * is disabled. If 0xff chip may be in a PCI power-save state.
1672 if (!(val
& CmdRxEnb
) || val
== 0xff)
1675 return rtl8169_do_counters(tp
, CounterDump
);
1678 static bool rtl8169_init_counter_offsets(struct rtl8169_private
*tp
)
1680 struct rtl8169_counters
*counters
= tp
->counters
;
1684 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1685 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1686 * reset by a power cycle, while the counter values collected by the
1687 * driver are reset at every driver unload/load cycle.
1689 * To make sure the HW values returned by @get_stats64 match the SW
1690 * values, we collect the initial values at first open(*) and use them
1691 * as offsets to normalize the values returned by @get_stats64.
1693 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1694 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1695 * set at open time by rtl_hw_start.
1698 if (tp
->tc_offset
.inited
)
1701 /* If both, reset and update fail, propagate to caller. */
1702 if (rtl8169_reset_counters(tp
))
1705 if (rtl8169_update_counters(tp
))
1708 tp
->tc_offset
.tx_errors
= counters
->tx_errors
;
1709 tp
->tc_offset
.tx_multi_collision
= counters
->tx_multi_collision
;
1710 tp
->tc_offset
.tx_aborted
= counters
->tx_aborted
;
1711 tp
->tc_offset
.inited
= true;
1716 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
1717 struct ethtool_stats
*stats
, u64
*data
)
1719 struct rtl8169_private
*tp
= netdev_priv(dev
);
1720 struct device
*d
= tp_to_dev(tp
);
1721 struct rtl8169_counters
*counters
= tp
->counters
;
1725 pm_runtime_get_noresume(d
);
1727 if (pm_runtime_active(d
))
1728 rtl8169_update_counters(tp
);
1730 pm_runtime_put_noidle(d
);
1732 data
[0] = le64_to_cpu(counters
->tx_packets
);
1733 data
[1] = le64_to_cpu(counters
->rx_packets
);
1734 data
[2] = le64_to_cpu(counters
->tx_errors
);
1735 data
[3] = le32_to_cpu(counters
->rx_errors
);
1736 data
[4] = le16_to_cpu(counters
->rx_missed
);
1737 data
[5] = le16_to_cpu(counters
->align_errors
);
1738 data
[6] = le32_to_cpu(counters
->tx_one_collision
);
1739 data
[7] = le32_to_cpu(counters
->tx_multi_collision
);
1740 data
[8] = le64_to_cpu(counters
->rx_unicast
);
1741 data
[9] = le64_to_cpu(counters
->rx_broadcast
);
1742 data
[10] = le32_to_cpu(counters
->rx_multicast
);
1743 data
[11] = le16_to_cpu(counters
->tx_aborted
);
1744 data
[12] = le16_to_cpu(counters
->tx_underun
);
1747 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1751 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
1757 * Interrupt coalescing
1759 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1760 * > 8169, 8168 and 810x line of chipsets
1762 * 8169, 8168, and 8136(810x) serial chipsets support it.
1764 * > 2 - the Tx timer unit at gigabit speed
1766 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1767 * (0xe0) bit 1 and bit 0.
1770 * bit[1:0] \ speed 1000M 100M 10M
1771 * 0 0 320ns 2.56us 40.96us
1772 * 0 1 2.56us 20.48us 327.7us
1773 * 1 0 5.12us 40.96us 655.4us
1774 * 1 1 10.24us 81.92us 1.31ms
1777 * bit[1:0] \ speed 1000M 100M 10M
1778 * 0 0 5us 2.56us 40.96us
1779 * 0 1 40us 20.48us 327.7us
1780 * 1 0 80us 40.96us 655.4us
1781 * 1 1 160us 81.92us 1.31ms
1784 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1785 struct rtl_coalesce_scale
{
1790 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1791 struct rtl_coalesce_info
{
1793 struct rtl_coalesce_scale scalev
[4]; /* each CPlusCmd[0:1] case */
1796 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1797 #define rxtx_x1822(r, t) { \
1800 {{(r)*8*2, (t)*8*2}}, \
1801 {{(r)*8*2*2, (t)*8*2*2}}, \
1803 static const struct rtl_coalesce_info rtl_coalesce_info_8169
[] = {
1804 /* speed delays: rx00 tx00 */
1805 { SPEED_10
, rxtx_x1822(40960, 40960) },
1806 { SPEED_100
, rxtx_x1822( 2560, 2560) },
1807 { SPEED_1000
, rxtx_x1822( 320, 320) },
1811 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136
[] = {
1812 /* speed delays: rx00 tx00 */
1813 { SPEED_10
, rxtx_x1822(40960, 40960) },
1814 { SPEED_100
, rxtx_x1822( 2560, 2560) },
1815 { SPEED_1000
, rxtx_x1822( 5000, 5000) },
1820 /* get rx/tx scale vector corresponding to current speed */
1821 static const struct rtl_coalesce_info
*rtl_coalesce_info(struct net_device
*dev
)
1823 struct rtl8169_private
*tp
= netdev_priv(dev
);
1824 const struct rtl_coalesce_info
*ci
;
1826 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
1827 ci
= rtl_coalesce_info_8169
;
1829 ci
= rtl_coalesce_info_8168_8136
;
1831 for (; ci
->speed
; ci
++) {
1832 if (tp
->phydev
->speed
== ci
->speed
)
1836 return ERR_PTR(-ELNRNG
);
1839 static int rtl_get_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
1841 struct rtl8169_private
*tp
= netdev_priv(dev
);
1842 const struct rtl_coalesce_info
*ci
;
1843 const struct rtl_coalesce_scale
*scale
;
1847 } coal_settings
[] = {
1848 { &ec
->rx_max_coalesced_frames
, &ec
->rx_coalesce_usecs
},
1849 { &ec
->tx_max_coalesced_frames
, &ec
->tx_coalesce_usecs
}
1850 }, *p
= coal_settings
;
1854 memset(ec
, 0, sizeof(*ec
));
1856 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1857 ci
= rtl_coalesce_info(dev
);
1861 scale
= &ci
->scalev
[tp
->cp_cmd
& INTT_MASK
];
1863 /* read IntrMitigate and adjust according to scale */
1864 for (w
= RTL_R16(tp
, IntrMitigate
); w
; w
>>= RTL_COALESCE_SHIFT
, p
++) {
1865 *p
->max_frames
= (w
& RTL_COALESCE_MASK
) << 2;
1866 w
>>= RTL_COALESCE_SHIFT
;
1867 *p
->usecs
= w
& RTL_COALESCE_MASK
;
1870 for (i
= 0; i
< 2; i
++) {
1871 p
= coal_settings
+ i
;
1872 *p
->usecs
= (*p
->usecs
* scale
->nsecs
[i
]) / 1000;
1875 * ethtool_coalesce says it is illegal to set both usecs and
1878 if (!*p
->usecs
&& !*p
->max_frames
)
1885 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1886 static const struct rtl_coalesce_scale
*rtl_coalesce_choose_scale(
1887 struct net_device
*dev
, u32 nsec
, u16
*cp01
)
1889 const struct rtl_coalesce_info
*ci
;
1892 ci
= rtl_coalesce_info(dev
);
1894 return ERR_CAST(ci
);
1896 for (i
= 0; i
< 4; i
++) {
1897 u32 rxtx_maxscale
= max(ci
->scalev
[i
].nsecs
[0],
1898 ci
->scalev
[i
].nsecs
[1]);
1899 if (nsec
<= rxtx_maxscale
* RTL_COALESCE_T_MAX
) {
1901 return &ci
->scalev
[i
];
1905 return ERR_PTR(-EINVAL
);
1908 static int rtl_set_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
1910 struct rtl8169_private
*tp
= netdev_priv(dev
);
1911 const struct rtl_coalesce_scale
*scale
;
1915 } coal_settings
[] = {
1916 { ec
->rx_max_coalesced_frames
, ec
->rx_coalesce_usecs
},
1917 { ec
->tx_max_coalesced_frames
, ec
->tx_coalesce_usecs
}
1918 }, *p
= coal_settings
;
1922 scale
= rtl_coalesce_choose_scale(dev
,
1923 max(p
[0].usecs
, p
[1].usecs
) * 1000, &cp01
);
1925 return PTR_ERR(scale
);
1927 for (i
= 0; i
< 2; i
++, p
++) {
1931 * accept max_frames=1 we returned in rtl_get_coalesce.
1932 * accept it not only when usecs=0 because of e.g. the following scenario:
1934 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1935 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1936 * - then user does `ethtool -C eth0 rx-usecs 100`
1938 * since ethtool sends to kernel whole ethtool_coalesce
1939 * settings, if we do not handle rx_usecs=!0, rx_frames=1
1940 * we'll reject it below in `frames % 4 != 0`.
1942 if (p
->frames
== 1) {
1946 units
= p
->usecs
* 1000 / scale
->nsecs
[i
];
1947 if (p
->frames
> RTL_COALESCE_FRAME_MAX
|| p
->frames
% 4)
1950 w
<<= RTL_COALESCE_SHIFT
;
1952 w
<<= RTL_COALESCE_SHIFT
;
1953 w
|= p
->frames
>> 2;
1958 RTL_W16(tp
, IntrMitigate
, swab16(w
));
1960 tp
->cp_cmd
= (tp
->cp_cmd
& ~INTT_MASK
) | cp01
;
1961 RTL_W16(tp
, CPlusCmd
, tp
->cp_cmd
);
1962 RTL_R16(tp
, CPlusCmd
);
1964 rtl_unlock_work(tp
);
1969 static int rtl8169_get_eee(struct net_device
*dev
, struct ethtool_eee
*data
)
1971 struct rtl8169_private
*tp
= netdev_priv(dev
);
1972 struct device
*d
= tp_to_dev(tp
);
1975 if (!rtl_supports_eee(tp
))
1978 pm_runtime_get_noresume(d
);
1980 if (!pm_runtime_active(d
)) {
1983 ret
= phy_ethtool_get_eee(tp
->phydev
, data
);
1986 pm_runtime_put_noidle(d
);
1991 static int rtl8169_set_eee(struct net_device
*dev
, struct ethtool_eee
*data
)
1993 struct rtl8169_private
*tp
= netdev_priv(dev
);
1994 struct device
*d
= tp_to_dev(tp
);
1997 if (!rtl_supports_eee(tp
))
2000 pm_runtime_get_noresume(d
);
2002 if (!pm_runtime_active(d
)) {
2007 if (dev
->phydev
->autoneg
== AUTONEG_DISABLE
||
2008 dev
->phydev
->duplex
!= DUPLEX_FULL
) {
2009 ret
= -EPROTONOSUPPORT
;
2013 ret
= phy_ethtool_set_eee(tp
->phydev
, data
);
2015 pm_runtime_put_noidle(d
);
2019 static const struct ethtool_ops rtl8169_ethtool_ops
= {
2020 .get_drvinfo
= rtl8169_get_drvinfo
,
2021 .get_regs_len
= rtl8169_get_regs_len
,
2022 .get_link
= ethtool_op_get_link
,
2023 .get_coalesce
= rtl_get_coalesce
,
2024 .set_coalesce
= rtl_set_coalesce
,
2025 .get_msglevel
= rtl8169_get_msglevel
,
2026 .set_msglevel
= rtl8169_set_msglevel
,
2027 .get_regs
= rtl8169_get_regs
,
2028 .get_wol
= rtl8169_get_wol
,
2029 .set_wol
= rtl8169_set_wol
,
2030 .get_strings
= rtl8169_get_strings
,
2031 .get_sset_count
= rtl8169_get_sset_count
,
2032 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
2033 .get_ts_info
= ethtool_op_get_ts_info
,
2034 .nway_reset
= phy_ethtool_nway_reset
,
2035 .get_eee
= rtl8169_get_eee
,
2036 .set_eee
= rtl8169_set_eee
,
2037 .get_link_ksettings
= phy_ethtool_get_link_ksettings
,
2038 .set_link_ksettings
= phy_ethtool_set_link_ksettings
,
2041 static void rtl_enable_eee(struct rtl8169_private
*tp
)
2043 struct phy_device
*phydev
= tp
->phydev
;
2044 int supported
= phy_read_mmd(phydev
, MDIO_MMD_PCS
, MDIO_PCS_EEE_ABLE
);
2047 phy_write_mmd(phydev
, MDIO_MMD_AN
, MDIO_AN_EEE_ADV
, supported
);
2050 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
)
2053 * The driver currently handles the 8168Bf and the 8168Be identically
2054 * but they can be identified more specifically through the test below
2057 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2059 * Same thing for the 8101Eb and the 8101Ec:
2061 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2063 static const struct rtl_mac_info
{
2068 /* 8168EP family. */
2069 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51
},
2070 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50
},
2071 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49
},
2074 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46
},
2075 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45
},
2078 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44
},
2079 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42
},
2080 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41
},
2081 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40
},
2084 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38
},
2085 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36
},
2086 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35
},
2089 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34
},
2090 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32
},
2091 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33
},
2094 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25
},
2095 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26
},
2097 /* 8168DP family. */
2098 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27
},
2099 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28
},
2100 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31
},
2103 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23
},
2104 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18
},
2105 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24
},
2106 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19
},
2107 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20
},
2108 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21
},
2109 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22
},
2112 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12
},
2113 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17
},
2114 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11
},
2117 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39
},
2118 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37
},
2119 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29
},
2120 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30
},
2121 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08
},
2122 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08
},
2123 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07
},
2124 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07
},
2125 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13
},
2126 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10
},
2127 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16
},
2128 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09
},
2129 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09
},
2130 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16
},
2131 /* FIXME: where did these entries come from ? -- FR */
2132 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15
},
2133 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14
},
2136 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06
},
2137 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05
},
2138 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04
},
2139 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03
},
2140 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02
},
2143 { 0x000, 0x000, RTL_GIGA_MAC_NONE
}
2145 const struct rtl_mac_info
*p
= mac_info
;
2146 u16 reg
= RTL_R32(tp
, TxConfig
) >> 20;
2148 while ((reg
& p
->mask
) != p
->val
)
2150 tp
->mac_version
= p
->mac_version
;
2152 if (tp
->mac_version
== RTL_GIGA_MAC_NONE
) {
2153 dev_err(tp_to_dev(tp
), "unknown chip XID %03x\n", reg
& 0xfcf);
2154 } else if (!tp
->supports_gmii
) {
2155 if (tp
->mac_version
== RTL_GIGA_MAC_VER_42
)
2156 tp
->mac_version
= RTL_GIGA_MAC_VER_43
;
2157 else if (tp
->mac_version
== RTL_GIGA_MAC_VER_45
)
2158 tp
->mac_version
= RTL_GIGA_MAC_VER_47
;
2159 else if (tp
->mac_version
== RTL_GIGA_MAC_VER_46
)
2160 tp
->mac_version
= RTL_GIGA_MAC_VER_48
;
2169 static void __rtl_writephy_batch(struct rtl8169_private
*tp
,
2170 const struct phy_reg
*regs
, int len
)
2173 rtl_writephy(tp
, regs
->reg
, regs
->val
);
2178 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a))
2180 static void rtl_release_firmware(struct rtl8169_private
*tp
)
2183 rtl_fw_release_firmware(tp
->rtl_fw
);
2189 static void rtl_apply_firmware(struct rtl8169_private
*tp
)
2191 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2193 rtl_fw_write_firmware(tp
, tp
->rtl_fw
);
2196 static void rtl_apply_firmware_cond(struct rtl8169_private
*tp
, u8 reg
, u16 val
)
2198 if (rtl_readphy(tp
, reg
) != val
)
2199 netif_warn(tp
, hw
, tp
->dev
, "chipset not ready for firmware\n");
2201 rtl_apply_firmware(tp
);
2204 static void rtl8168_config_eee_mac(struct rtl8169_private
*tp
)
2206 /* Adjust EEE LED frequency */
2207 if (tp
->mac_version
!= RTL_GIGA_MAC_VER_38
)
2208 RTL_W8(tp
, EEE_LED
, RTL_R8(tp
, EEE_LED
) & ~0x07);
2210 rtl_eri_set_bits(tp
, 0x1b0, ERIAR_MASK_1111
, 0x0003);
2213 static void rtl8168f_config_eee_phy(struct rtl8169_private
*tp
)
2215 struct phy_device
*phydev
= tp
->phydev
;
2217 phy_write(phydev
, 0x1f, 0x0007);
2218 phy_write(phydev
, 0x1e, 0x0020);
2219 phy_set_bits(phydev
, 0x15, BIT(8));
2221 phy_write(phydev
, 0x1f, 0x0005);
2222 phy_write(phydev
, 0x05, 0x8b85);
2223 phy_set_bits(phydev
, 0x06, BIT(13));
2225 phy_write(phydev
, 0x1f, 0x0000);
2228 static void rtl8168g_config_eee_phy(struct rtl8169_private
*tp
)
2230 phy_modify_paged(tp
->phydev
, 0x0a43, 0x11, 0, BIT(4));
2233 static void rtl8168h_config_eee_phy(struct rtl8169_private
*tp
)
2235 struct phy_device
*phydev
= tp
->phydev
;
2237 rtl8168g_config_eee_phy(tp
);
2239 phy_modify_paged(phydev
, 0xa4a, 0x11, 0x0000, 0x0200);
2240 phy_modify_paged(phydev
, 0xa42, 0x14, 0x0000, 0x0080);
2243 static void rtl8169s_hw_phy_config(struct rtl8169_private
*tp
)
2245 static const struct phy_reg phy_reg_init
[] = {
2307 rtl_writephy_batch(tp
, phy_reg_init
);
2310 static void rtl8169sb_hw_phy_config(struct rtl8169_private
*tp
)
2312 static const struct phy_reg phy_reg_init
[] = {
2318 rtl_writephy_batch(tp
, phy_reg_init
);
2321 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private
*tp
)
2323 struct pci_dev
*pdev
= tp
->pci_dev
;
2325 if ((pdev
->subsystem_vendor
!= PCI_VENDOR_ID_GIGABYTE
) ||
2326 (pdev
->subsystem_device
!= 0xe000))
2329 rtl_writephy(tp
, 0x1f, 0x0001);
2330 rtl_writephy(tp
, 0x10, 0xf01b);
2331 rtl_writephy(tp
, 0x1f, 0x0000);
2334 static void rtl8169scd_hw_phy_config(struct rtl8169_private
*tp
)
2336 static const struct phy_reg phy_reg_init
[] = {
2376 rtl_writephy_batch(tp
, phy_reg_init
);
2378 rtl8169scd_hw_phy_config_quirk(tp
);
2381 static void rtl8169sce_hw_phy_config(struct rtl8169_private
*tp
)
2383 static const struct phy_reg phy_reg_init
[] = {
2431 rtl_writephy_batch(tp
, phy_reg_init
);
2434 static void rtl8168bb_hw_phy_config(struct rtl8169_private
*tp
)
2436 static const struct phy_reg phy_reg_init
[] = {
2441 rtl_writephy(tp
, 0x1f, 0x0001);
2442 rtl_patchphy(tp
, 0x16, 1 << 0);
2444 rtl_writephy_batch(tp
, phy_reg_init
);
2447 static void rtl8168bef_hw_phy_config(struct rtl8169_private
*tp
)
2449 static const struct phy_reg phy_reg_init
[] = {
2455 rtl_writephy_batch(tp
, phy_reg_init
);
2458 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private
*tp
)
2460 static const struct phy_reg phy_reg_init
[] = {
2468 rtl_writephy_batch(tp
, phy_reg_init
);
2471 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private
*tp
)
2473 static const struct phy_reg phy_reg_init
[] = {
2479 rtl_writephy(tp
, 0x1f, 0x0000);
2480 rtl_patchphy(tp
, 0x14, 1 << 5);
2481 rtl_patchphy(tp
, 0x0d, 1 << 5);
2483 rtl_writephy_batch(tp
, phy_reg_init
);
2486 static void rtl8168c_1_hw_phy_config(struct rtl8169_private
*tp
)
2488 static const struct phy_reg phy_reg_init
[] = {
2508 rtl_writephy_batch(tp
, phy_reg_init
);
2510 rtl_patchphy(tp
, 0x14, 1 << 5);
2511 rtl_patchphy(tp
, 0x0d, 1 << 5);
2512 rtl_writephy(tp
, 0x1f, 0x0000);
2515 static void rtl8168c_2_hw_phy_config(struct rtl8169_private
*tp
)
2517 static const struct phy_reg phy_reg_init
[] = {
2535 rtl_writephy_batch(tp
, phy_reg_init
);
2537 rtl_patchphy(tp
, 0x16, 1 << 0);
2538 rtl_patchphy(tp
, 0x14, 1 << 5);
2539 rtl_patchphy(tp
, 0x0d, 1 << 5);
2540 rtl_writephy(tp
, 0x1f, 0x0000);
2543 static void rtl8168c_3_hw_phy_config(struct rtl8169_private
*tp
)
2545 static const struct phy_reg phy_reg_init
[] = {
2557 rtl_writephy_batch(tp
, phy_reg_init
);
2559 rtl_patchphy(tp
, 0x16, 1 << 0);
2560 rtl_patchphy(tp
, 0x14, 1 << 5);
2561 rtl_patchphy(tp
, 0x0d, 1 << 5);
2562 rtl_writephy(tp
, 0x1f, 0x0000);
2565 static void rtl8168c_4_hw_phy_config(struct rtl8169_private
*tp
)
2567 rtl8168c_3_hw_phy_config(tp
);
2570 static const struct phy_reg rtl8168d_1_phy_reg_init_0
[] = {
2571 /* Channel Estimation */
2592 * Enhance line driver power
2601 * Can not link to 1Gbps with bad cable
2602 * Decrease SNR threshold form 21.07dB to 19.04dB
2611 static const struct phy_reg rtl8168d_1_phy_reg_init_1
[] = {
2620 static void rtl8168d_1_hw_phy_config(struct rtl8169_private
*tp
)
2622 rtl_writephy_batch(tp
, rtl8168d_1_phy_reg_init_0
);
2626 * Fine Tune Switching regulator parameter
2628 rtl_writephy(tp
, 0x1f, 0x0002);
2629 rtl_w0w1_phy(tp
, 0x0b, 0x0010, 0x00ef);
2630 rtl_w0w1_phy(tp
, 0x0c, 0xa200, 0x5d00);
2632 if (rtl8168d_efuse_read(tp
, 0x01) == 0xb1) {
2635 rtl_writephy_batch(tp
, rtl8168d_1_phy_reg_init_1
);
2637 val
= rtl_readphy(tp
, 0x0d);
2639 if ((val
& 0x00ff) != 0x006c) {
2640 static const u32 set
[] = {
2641 0x0065, 0x0066, 0x0067, 0x0068,
2642 0x0069, 0x006a, 0x006b, 0x006c
2646 rtl_writephy(tp
, 0x1f, 0x0002);
2649 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2650 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
2653 static const struct phy_reg phy_reg_init
[] = {
2661 rtl_writephy_batch(tp
, phy_reg_init
);
2664 /* RSET couple improve */
2665 rtl_writephy(tp
, 0x1f, 0x0002);
2666 rtl_patchphy(tp
, 0x0d, 0x0300);
2667 rtl_patchphy(tp
, 0x0f, 0x0010);
2669 /* Fine tune PLL performance */
2670 rtl_writephy(tp
, 0x1f, 0x0002);
2671 rtl_w0w1_phy(tp
, 0x02, 0x0100, 0x0600);
2672 rtl_w0w1_phy(tp
, 0x03, 0x0000, 0xe000);
2674 rtl_writephy(tp
, 0x1f, 0x0005);
2675 rtl_writephy(tp
, 0x05, 0x001b);
2677 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xbf00);
2679 rtl_writephy(tp
, 0x1f, 0x0000);
2682 static void rtl8168d_2_hw_phy_config(struct rtl8169_private
*tp
)
2684 rtl_writephy_batch(tp
, rtl8168d_1_phy_reg_init_0
);
2686 if (rtl8168d_efuse_read(tp
, 0x01) == 0xb1) {
2689 rtl_writephy_batch(tp
, rtl8168d_1_phy_reg_init_1
);
2691 val
= rtl_readphy(tp
, 0x0d);
2692 if ((val
& 0x00ff) != 0x006c) {
2693 static const u32 set
[] = {
2694 0x0065, 0x0066, 0x0067, 0x0068,
2695 0x0069, 0x006a, 0x006b, 0x006c
2699 rtl_writephy(tp
, 0x1f, 0x0002);
2702 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2703 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
2706 static const struct phy_reg phy_reg_init
[] = {
2714 rtl_writephy_batch(tp
, phy_reg_init
);
2717 /* Fine tune PLL performance */
2718 rtl_writephy(tp
, 0x1f, 0x0002);
2719 rtl_w0w1_phy(tp
, 0x02, 0x0100, 0x0600);
2720 rtl_w0w1_phy(tp
, 0x03, 0x0000, 0xe000);
2722 /* Switching regulator Slew rate */
2723 rtl_writephy(tp
, 0x1f, 0x0002);
2724 rtl_patchphy(tp
, 0x0f, 0x0017);
2726 rtl_writephy(tp
, 0x1f, 0x0005);
2727 rtl_writephy(tp
, 0x05, 0x001b);
2729 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xb300);
2731 rtl_writephy(tp
, 0x1f, 0x0000);
2734 static void rtl8168d_3_hw_phy_config(struct rtl8169_private
*tp
)
2736 static const struct phy_reg phy_reg_init
[] = {
2792 rtl_writephy_batch(tp
, phy_reg_init
);
2795 static void rtl8168d_4_hw_phy_config(struct rtl8169_private
*tp
)
2797 static const struct phy_reg phy_reg_init
[] = {
2807 rtl_writephy_batch(tp
, phy_reg_init
);
2808 rtl_patchphy(tp
, 0x0d, 1 << 5);
2811 static void rtl8168e_1_hw_phy_config(struct rtl8169_private
*tp
)
2813 static const struct phy_reg phy_reg_init
[] = {
2814 /* Enable Delay cap */
2820 /* Channel estimation fine tune */
2829 /* Update PFM & 10M TX idle timer */
2841 rtl_apply_firmware(tp
);
2843 rtl_writephy_batch(tp
, phy_reg_init
);
2845 /* DCO enable for 10M IDLE Power */
2846 rtl_writephy(tp
, 0x1f, 0x0007);
2847 rtl_writephy(tp
, 0x1e, 0x0023);
2848 rtl_w0w1_phy(tp
, 0x17, 0x0006, 0x0000);
2849 rtl_writephy(tp
, 0x1f, 0x0000);
2851 /* For impedance matching */
2852 rtl_writephy(tp
, 0x1f, 0x0002);
2853 rtl_w0w1_phy(tp
, 0x08, 0x8000, 0x7f00);
2854 rtl_writephy(tp
, 0x1f, 0x0000);
2856 /* PHY auto speed down */
2857 rtl_writephy(tp
, 0x1f, 0x0007);
2858 rtl_writephy(tp
, 0x1e, 0x002d);
2859 rtl_w0w1_phy(tp
, 0x18, 0x0050, 0x0000);
2860 rtl_writephy(tp
, 0x1f, 0x0000);
2861 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
2863 rtl_writephy(tp
, 0x1f, 0x0005);
2864 rtl_writephy(tp
, 0x05, 0x8b86);
2865 rtl_w0w1_phy(tp
, 0x06, 0x0001, 0x0000);
2866 rtl_writephy(tp
, 0x1f, 0x0000);
2868 rtl_writephy(tp
, 0x1f, 0x0005);
2869 rtl_writephy(tp
, 0x05, 0x8b85);
2870 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x2000);
2871 rtl_writephy(tp
, 0x1f, 0x0007);
2872 rtl_writephy(tp
, 0x1e, 0x0020);
2873 rtl_w0w1_phy(tp
, 0x15, 0x0000, 0x1100);
2874 rtl_writephy(tp
, 0x1f, 0x0006);
2875 rtl_writephy(tp
, 0x00, 0x5a00);
2876 rtl_writephy(tp
, 0x1f, 0x0000);
2877 rtl_writephy(tp
, 0x0d, 0x0007);
2878 rtl_writephy(tp
, 0x0e, 0x003c);
2879 rtl_writephy(tp
, 0x0d, 0x4007);
2880 rtl_writephy(tp
, 0x0e, 0x0000);
2881 rtl_writephy(tp
, 0x0d, 0x0000);
2884 static void rtl_rar_exgmac_set(struct rtl8169_private
*tp
, u8
*addr
)
2887 addr
[0] | (addr
[1] << 8),
2888 addr
[2] | (addr
[3] << 8),
2889 addr
[4] | (addr
[5] << 8)
2892 rtl_eri_write(tp
, 0xe0, ERIAR_MASK_1111
, w
[0] | (w
[1] << 16));
2893 rtl_eri_write(tp
, 0xe4, ERIAR_MASK_1111
, w
[2]);
2894 rtl_eri_write(tp
, 0xf0, ERIAR_MASK_1111
, w
[0] << 16);
2895 rtl_eri_write(tp
, 0xf4, ERIAR_MASK_1111
, w
[1] | (w
[2] << 16));
2898 static void rtl8168e_2_hw_phy_config(struct rtl8169_private
*tp
)
2900 static const struct phy_reg phy_reg_init
[] = {
2901 /* Enable Delay cap */
2910 /* Channel estimation fine tune */
2927 rtl_apply_firmware(tp
);
2929 rtl_writephy_batch(tp
, phy_reg_init
);
2931 /* For 4-corner performance improve */
2932 rtl_writephy(tp
, 0x1f, 0x0005);
2933 rtl_writephy(tp
, 0x05, 0x8b80);
2934 rtl_w0w1_phy(tp
, 0x17, 0x0006, 0x0000);
2935 rtl_writephy(tp
, 0x1f, 0x0000);
2937 /* PHY auto speed down */
2938 rtl_writephy(tp
, 0x1f, 0x0004);
2939 rtl_writephy(tp
, 0x1f, 0x0007);
2940 rtl_writephy(tp
, 0x1e, 0x002d);
2941 rtl_w0w1_phy(tp
, 0x18, 0x0010, 0x0000);
2942 rtl_writephy(tp
, 0x1f, 0x0002);
2943 rtl_writephy(tp
, 0x1f, 0x0000);
2944 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
2946 /* improve 10M EEE waveform */
2947 rtl_writephy(tp
, 0x1f, 0x0005);
2948 rtl_writephy(tp
, 0x05, 0x8b86);
2949 rtl_w0w1_phy(tp
, 0x06, 0x0001, 0x0000);
2950 rtl_writephy(tp
, 0x1f, 0x0000);
2952 /* Improve 2-pair detection performance */
2953 rtl_writephy(tp
, 0x1f, 0x0005);
2954 rtl_writephy(tp
, 0x05, 0x8b85);
2955 rtl_w0w1_phy(tp
, 0x06, 0x4000, 0x0000);
2956 rtl_writephy(tp
, 0x1f, 0x0000);
2958 rtl8168f_config_eee_phy(tp
);
2962 rtl_writephy(tp
, 0x1f, 0x0003);
2963 rtl_w0w1_phy(tp
, 0x19, 0x0001, 0x0000);
2964 rtl_w0w1_phy(tp
, 0x10, 0x0400, 0x0000);
2965 rtl_writephy(tp
, 0x1f, 0x0000);
2966 rtl_writephy(tp
, 0x1f, 0x0005);
2967 rtl_w0w1_phy(tp
, 0x01, 0x0100, 0x0000);
2968 rtl_writephy(tp
, 0x1f, 0x0000);
2970 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
2971 rtl_rar_exgmac_set(tp
, tp
->dev
->dev_addr
);
2974 static void rtl8168f_hw_phy_config(struct rtl8169_private
*tp
)
2976 /* For 4-corner performance improve */
2977 rtl_writephy(tp
, 0x1f, 0x0005);
2978 rtl_writephy(tp
, 0x05, 0x8b80);
2979 rtl_w0w1_phy(tp
, 0x06, 0x0006, 0x0000);
2980 rtl_writephy(tp
, 0x1f, 0x0000);
2982 /* PHY auto speed down */
2983 rtl_writephy(tp
, 0x1f, 0x0007);
2984 rtl_writephy(tp
, 0x1e, 0x002d);
2985 rtl_w0w1_phy(tp
, 0x18, 0x0010, 0x0000);
2986 rtl_writephy(tp
, 0x1f, 0x0000);
2987 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
2989 /* Improve 10M EEE waveform */
2990 rtl_writephy(tp
, 0x1f, 0x0005);
2991 rtl_writephy(tp
, 0x05, 0x8b86);
2992 rtl_w0w1_phy(tp
, 0x06, 0x0001, 0x0000);
2993 rtl_writephy(tp
, 0x1f, 0x0000);
2995 rtl8168f_config_eee_phy(tp
);
2999 static void rtl8168f_1_hw_phy_config(struct rtl8169_private
*tp
)
3001 static const struct phy_reg phy_reg_init
[] = {
3002 /* Channel estimation fine tune */
3007 /* Modify green table for giga & fnet */
3024 /* Modify green table for 10M */
3030 /* Disable hiimpedance detection (RTCT) */
3036 rtl_apply_firmware(tp
);
3038 rtl_writephy_batch(tp
, phy_reg_init
);
3040 rtl8168f_hw_phy_config(tp
);
3042 /* Improve 2-pair detection performance */
3043 rtl_writephy(tp
, 0x1f, 0x0005);
3044 rtl_writephy(tp
, 0x05, 0x8b85);
3045 rtl_w0w1_phy(tp
, 0x06, 0x4000, 0x0000);
3046 rtl_writephy(tp
, 0x1f, 0x0000);
3049 static void rtl8168f_2_hw_phy_config(struct rtl8169_private
*tp
)
3051 rtl_apply_firmware(tp
);
3053 rtl8168f_hw_phy_config(tp
);
3056 static void rtl8411_hw_phy_config(struct rtl8169_private
*tp
)
3058 static const struct phy_reg phy_reg_init
[] = {
3059 /* Channel estimation fine tune */
3064 /* Modify green table for giga & fnet */
3081 /* Modify green table for 10M */
3087 /* Disable hiimpedance detection (RTCT) */
3094 rtl_apply_firmware(tp
);
3096 rtl8168f_hw_phy_config(tp
);
3098 /* Improve 2-pair detection performance */
3099 rtl_writephy(tp
, 0x1f, 0x0005);
3100 rtl_writephy(tp
, 0x05, 0x8b85);
3101 rtl_w0w1_phy(tp
, 0x06, 0x4000, 0x0000);
3102 rtl_writephy(tp
, 0x1f, 0x0000);
3104 rtl_writephy_batch(tp
, phy_reg_init
);
3106 /* Modify green table for giga */
3107 rtl_writephy(tp
, 0x1f, 0x0005);
3108 rtl_writephy(tp
, 0x05, 0x8b54);
3109 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0800);
3110 rtl_writephy(tp
, 0x05, 0x8b5d);
3111 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0800);
3112 rtl_writephy(tp
, 0x05, 0x8a7c);
3113 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0100);
3114 rtl_writephy(tp
, 0x05, 0x8a7f);
3115 rtl_w0w1_phy(tp
, 0x06, 0x0100, 0x0000);
3116 rtl_writephy(tp
, 0x05, 0x8a82);
3117 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0100);
3118 rtl_writephy(tp
, 0x05, 0x8a85);
3119 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0100);
3120 rtl_writephy(tp
, 0x05, 0x8a88);
3121 rtl_w0w1_phy(tp
, 0x06, 0x0000, 0x0100);
3122 rtl_writephy(tp
, 0x1f, 0x0000);
3124 /* uc same-seed solution */
3125 rtl_writephy(tp
, 0x1f, 0x0005);
3126 rtl_writephy(tp
, 0x05, 0x8b85);
3127 rtl_w0w1_phy(tp
, 0x06, 0x8000, 0x0000);
3128 rtl_writephy(tp
, 0x1f, 0x0000);
3131 rtl_writephy(tp
, 0x1f, 0x0003);
3132 rtl_w0w1_phy(tp
, 0x19, 0x0000, 0x0001);
3133 rtl_w0w1_phy(tp
, 0x10, 0x0000, 0x0400);
3134 rtl_writephy(tp
, 0x1f, 0x0000);
3137 static void rtl8168g_disable_aldps(struct rtl8169_private
*tp
)
3139 phy_modify_paged(tp
->phydev
, 0x0a43, 0x10, BIT(2), 0);
3142 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private
*tp
)
3144 struct phy_device
*phydev
= tp
->phydev
;
3146 phy_modify_paged(phydev
, 0x0bcc, 0x14, BIT(8), 0);
3147 phy_modify_paged(phydev
, 0x0a44, 0x11, 0, BIT(7) | BIT(6));
3148 phy_write(phydev
, 0x1f, 0x0a43);
3149 phy_write(phydev
, 0x13, 0x8084);
3150 phy_clear_bits(phydev
, 0x14, BIT(14) | BIT(13));
3151 phy_set_bits(phydev
, 0x10, BIT(12) | BIT(1) | BIT(0));
3153 phy_write(phydev
, 0x1f, 0x0000);
3156 static void rtl8168g_1_hw_phy_config(struct rtl8169_private
*tp
)
3160 rtl_apply_firmware(tp
);
3162 ret
= phy_read_paged(tp
->phydev
, 0x0a46, 0x10);
3164 phy_modify_paged(tp
->phydev
, 0x0bcc, 0x12, BIT(15), 0);
3166 phy_modify_paged(tp
->phydev
, 0x0bcc, 0x12, 0, BIT(15));
3168 ret
= phy_read_paged(tp
->phydev
, 0x0a46, 0x13);
3170 phy_modify_paged(tp
->phydev
, 0x0c41, 0x15, 0, BIT(1));
3172 phy_modify_paged(tp
->phydev
, 0x0c41, 0x15, BIT(1), 0);
3174 /* Enable PHY auto speed down */
3175 phy_modify_paged(tp
->phydev
, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3177 rtl8168g_phy_adjust_10m_aldps(tp
);
3179 /* EEE auto-fallback function */
3180 phy_modify_paged(tp
->phydev
, 0x0a4b, 0x11, 0, BIT(2));
3182 /* Enable UC LPF tune function */
3183 rtl_writephy(tp
, 0x1f, 0x0a43);
3184 rtl_writephy(tp
, 0x13, 0x8012);
3185 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
3187 phy_modify_paged(tp
->phydev
, 0x0c42, 0x11, BIT(13), BIT(14));
3189 /* Improve SWR Efficiency */
3190 rtl_writephy(tp
, 0x1f, 0x0bcd);
3191 rtl_writephy(tp
, 0x14, 0x5065);
3192 rtl_writephy(tp
, 0x14, 0xd065);
3193 rtl_writephy(tp
, 0x1f, 0x0bc8);
3194 rtl_writephy(tp
, 0x11, 0x5655);
3195 rtl_writephy(tp
, 0x1f, 0x0bcd);
3196 rtl_writephy(tp
, 0x14, 0x1065);
3197 rtl_writephy(tp
, 0x14, 0x9065);
3198 rtl_writephy(tp
, 0x14, 0x1065);
3199 rtl_writephy(tp
, 0x1f, 0x0000);
3201 rtl8168g_disable_aldps(tp
);
3202 rtl8168g_config_eee_phy(tp
);
3206 static void rtl8168g_2_hw_phy_config(struct rtl8169_private
*tp
)
3208 rtl_apply_firmware(tp
);
3209 rtl8168g_config_eee_phy(tp
);
3213 static void rtl8168h_1_hw_phy_config(struct rtl8169_private
*tp
)
3218 rtl_apply_firmware(tp
);
3220 /* CHN EST parameters adjust - giga master */
3221 rtl_writephy(tp
, 0x1f, 0x0a43);
3222 rtl_writephy(tp
, 0x13, 0x809b);
3223 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0xf800);
3224 rtl_writephy(tp
, 0x13, 0x80a2);
3225 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0xff00);
3226 rtl_writephy(tp
, 0x13, 0x80a4);
3227 rtl_w0w1_phy(tp
, 0x14, 0x8500, 0xff00);
3228 rtl_writephy(tp
, 0x13, 0x809c);
3229 rtl_w0w1_phy(tp
, 0x14, 0xbd00, 0xff00);
3230 rtl_writephy(tp
, 0x1f, 0x0000);
3232 /* CHN EST parameters adjust - giga slave */
3233 rtl_writephy(tp
, 0x1f, 0x0a43);
3234 rtl_writephy(tp
, 0x13, 0x80ad);
3235 rtl_w0w1_phy(tp
, 0x14, 0x7000, 0xf800);
3236 rtl_writephy(tp
, 0x13, 0x80b4);
3237 rtl_w0w1_phy(tp
, 0x14, 0x5000, 0xff00);
3238 rtl_writephy(tp
, 0x13, 0x80ac);
3239 rtl_w0w1_phy(tp
, 0x14, 0x4000, 0xff00);
3240 rtl_writephy(tp
, 0x1f, 0x0000);
3242 /* CHN EST parameters adjust - fnet */
3243 rtl_writephy(tp
, 0x1f, 0x0a43);
3244 rtl_writephy(tp
, 0x13, 0x808e);
3245 rtl_w0w1_phy(tp
, 0x14, 0x1200, 0xff00);
3246 rtl_writephy(tp
, 0x13, 0x8090);
3247 rtl_w0w1_phy(tp
, 0x14, 0xe500, 0xff00);
3248 rtl_writephy(tp
, 0x13, 0x8092);
3249 rtl_w0w1_phy(tp
, 0x14, 0x9f00, 0xff00);
3250 rtl_writephy(tp
, 0x1f, 0x0000);
3252 /* enable R-tune & PGA-retune function */
3254 rtl_writephy(tp
, 0x1f, 0x0a46);
3255 data
= rtl_readphy(tp
, 0x13);
3258 dout_tapbin
|= data
;
3259 data
= rtl_readphy(tp
, 0x12);
3262 dout_tapbin
|= data
;
3263 dout_tapbin
= ~(dout_tapbin
^0x08);
3265 dout_tapbin
&= 0xf000;
3266 rtl_writephy(tp
, 0x1f, 0x0a43);
3267 rtl_writephy(tp
, 0x13, 0x827a);
3268 rtl_w0w1_phy(tp
, 0x14, dout_tapbin
, 0xf000);
3269 rtl_writephy(tp
, 0x13, 0x827b);
3270 rtl_w0w1_phy(tp
, 0x14, dout_tapbin
, 0xf000);
3271 rtl_writephy(tp
, 0x13, 0x827c);
3272 rtl_w0w1_phy(tp
, 0x14, dout_tapbin
, 0xf000);
3273 rtl_writephy(tp
, 0x13, 0x827d);
3274 rtl_w0w1_phy(tp
, 0x14, dout_tapbin
, 0xf000);
3276 rtl_writephy(tp
, 0x1f, 0x0a43);
3277 rtl_writephy(tp
, 0x13, 0x0811);
3278 rtl_w0w1_phy(tp
, 0x14, 0x0800, 0x0000);
3279 rtl_writephy(tp
, 0x1f, 0x0a42);
3280 rtl_w0w1_phy(tp
, 0x16, 0x0002, 0x0000);
3281 rtl_writephy(tp
, 0x1f, 0x0000);
3283 /* enable GPHY 10M */
3284 phy_modify_paged(tp
->phydev
, 0x0a44, 0x11, 0, BIT(11));
3286 /* SAR ADC performance */
3287 phy_modify_paged(tp
->phydev
, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14));
3289 rtl_writephy(tp
, 0x1f, 0x0a43);
3290 rtl_writephy(tp
, 0x13, 0x803f);
3291 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3292 rtl_writephy(tp
, 0x13, 0x8047);
3293 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3294 rtl_writephy(tp
, 0x13, 0x804f);
3295 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3296 rtl_writephy(tp
, 0x13, 0x8057);
3297 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3298 rtl_writephy(tp
, 0x13, 0x805f);
3299 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3300 rtl_writephy(tp
, 0x13, 0x8067);
3301 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3302 rtl_writephy(tp
, 0x13, 0x806f);
3303 rtl_w0w1_phy(tp
, 0x14, 0x0000, 0x3000);
3304 rtl_writephy(tp
, 0x1f, 0x0000);
3306 /* disable phy pfm mode */
3307 phy_modify_paged(tp
->phydev
, 0x0a44, 0x11, BIT(7), 0);
3309 rtl8168g_disable_aldps(tp
);
3310 rtl8168h_config_eee_phy(tp
);
3314 static void rtl8168h_2_hw_phy_config(struct rtl8169_private
*tp
)
3316 u16 ioffset_p3
, ioffset_p2
, ioffset_p1
, ioffset_p0
;
3320 rtl_apply_firmware(tp
);
3322 /* CHIN EST parameter update */
3323 rtl_writephy(tp
, 0x1f, 0x0a43);
3324 rtl_writephy(tp
, 0x13, 0x808a);
3325 rtl_w0w1_phy(tp
, 0x14, 0x000a, 0x003f);
3326 rtl_writephy(tp
, 0x1f, 0x0000);
3328 /* enable R-tune & PGA-retune function */
3329 rtl_writephy(tp
, 0x1f, 0x0a43);
3330 rtl_writephy(tp
, 0x13, 0x0811);
3331 rtl_w0w1_phy(tp
, 0x14, 0x0800, 0x0000);
3332 rtl_writephy(tp
, 0x1f, 0x0a42);
3333 rtl_w0w1_phy(tp
, 0x16, 0x0002, 0x0000);
3334 rtl_writephy(tp
, 0x1f, 0x0000);
3336 /* enable GPHY 10M */
3337 phy_modify_paged(tp
->phydev
, 0x0a44, 0x11, 0, BIT(11));
3339 r8168_mac_ocp_write(tp
, 0xdd02, 0x807d);
3340 data
= r8168_mac_ocp_read(tp
, 0xdd02);
3341 ioffset_p3
= ((data
& 0x80)>>7);
3344 data
= r8168_mac_ocp_read(tp
, 0xdd00);
3345 ioffset_p3
|= ((data
& (0xe000))>>13);
3346 ioffset_p2
= ((data
& (0x1e00))>>9);
3347 ioffset_p1
= ((data
& (0x01e0))>>5);
3348 ioffset_p0
= ((data
& 0x0010)>>4);
3350 ioffset_p0
|= (data
& (0x07));
3351 data
= (ioffset_p3
<<12)|(ioffset_p2
<<8)|(ioffset_p1
<<4)|(ioffset_p0
);
3353 if ((ioffset_p3
!= 0x0f) || (ioffset_p2
!= 0x0f) ||
3354 (ioffset_p1
!= 0x0f) || (ioffset_p0
!= 0x0f)) {
3355 rtl_writephy(tp
, 0x1f, 0x0bcf);
3356 rtl_writephy(tp
, 0x16, data
);
3357 rtl_writephy(tp
, 0x1f, 0x0000);
3360 /* Modify rlen (TX LPF corner frequency) level */
3361 rtl_writephy(tp
, 0x1f, 0x0bcd);
3362 data
= rtl_readphy(tp
, 0x16);
3367 data
= rlen
| (rlen
<<4) | (rlen
<<8) | (rlen
<<12);
3368 rtl_writephy(tp
, 0x17, data
);
3369 rtl_writephy(tp
, 0x1f, 0x0bcd);
3370 rtl_writephy(tp
, 0x1f, 0x0000);
3372 /* disable phy pfm mode */
3373 phy_modify_paged(tp
->phydev
, 0x0a44, 0x11, BIT(7), 0);
3375 rtl8168g_disable_aldps(tp
);
3376 rtl8168g_config_eee_phy(tp
);
3380 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private
*tp
)
3382 /* Enable PHY auto speed down */
3383 phy_modify_paged(tp
->phydev
, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3385 rtl8168g_phy_adjust_10m_aldps(tp
);
3387 /* Enable EEE auto-fallback function */
3388 phy_modify_paged(tp
->phydev
, 0x0a4b, 0x11, 0, BIT(2));
3390 /* Enable UC LPF tune function */
3391 rtl_writephy(tp
, 0x1f, 0x0a43);
3392 rtl_writephy(tp
, 0x13, 0x8012);
3393 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
3394 rtl_writephy(tp
, 0x1f, 0x0000);
3396 /* set rg_sel_sdm_rate */
3397 phy_modify_paged(tp
->phydev
, 0x0c42, 0x11, BIT(13), BIT(14));
3399 rtl8168g_disable_aldps(tp
);
3400 rtl8168g_config_eee_phy(tp
);
3404 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private
*tp
)
3406 rtl8168g_phy_adjust_10m_aldps(tp
);
3408 /* Enable UC LPF tune function */
3409 rtl_writephy(tp
, 0x1f, 0x0a43);
3410 rtl_writephy(tp
, 0x13, 0x8012);
3411 rtl_w0w1_phy(tp
, 0x14, 0x8000, 0x0000);
3412 rtl_writephy(tp
, 0x1f, 0x0000);
3414 /* Set rg_sel_sdm_rate */
3415 phy_modify_paged(tp
->phydev
, 0x0c42, 0x11, BIT(13), BIT(14));
3417 /* Channel estimation parameters */
3418 rtl_writephy(tp
, 0x1f, 0x0a43);
3419 rtl_writephy(tp
, 0x13, 0x80f3);
3420 rtl_w0w1_phy(tp
, 0x14, 0x8b00, ~0x8bff);
3421 rtl_writephy(tp
, 0x13, 0x80f0);
3422 rtl_w0w1_phy(tp
, 0x14, 0x3a00, ~0x3aff);
3423 rtl_writephy(tp
, 0x13, 0x80ef);
3424 rtl_w0w1_phy(tp
, 0x14, 0x0500, ~0x05ff);
3425 rtl_writephy(tp
, 0x13, 0x80f6);
3426 rtl_w0w1_phy(tp
, 0x14, 0x6e00, ~0x6eff);
3427 rtl_writephy(tp
, 0x13, 0x80ec);
3428 rtl_w0w1_phy(tp
, 0x14, 0x6800, ~0x68ff);
3429 rtl_writephy(tp
, 0x13, 0x80ed);
3430 rtl_w0w1_phy(tp
, 0x14, 0x7c00, ~0x7cff);
3431 rtl_writephy(tp
, 0x13, 0x80f2);
3432 rtl_w0w1_phy(tp
, 0x14, 0xf400, ~0xf4ff);
3433 rtl_writephy(tp
, 0x13, 0x80f4);
3434 rtl_w0w1_phy(tp
, 0x14, 0x8500, ~0x85ff);
3435 rtl_writephy(tp
, 0x1f, 0x0a43);
3436 rtl_writephy(tp
, 0x13, 0x8110);
3437 rtl_w0w1_phy(tp
, 0x14, 0xa800, ~0xa8ff);
3438 rtl_writephy(tp
, 0x13, 0x810f);
3439 rtl_w0w1_phy(tp
, 0x14, 0x1d00, ~0x1dff);
3440 rtl_writephy(tp
, 0x13, 0x8111);
3441 rtl_w0w1_phy(tp
, 0x14, 0xf500, ~0xf5ff);
3442 rtl_writephy(tp
, 0x13, 0x8113);
3443 rtl_w0w1_phy(tp
, 0x14, 0x6100, ~0x61ff);
3444 rtl_writephy(tp
, 0x13, 0x8115);
3445 rtl_w0w1_phy(tp
, 0x14, 0x9200, ~0x92ff);
3446 rtl_writephy(tp
, 0x13, 0x810e);
3447 rtl_w0w1_phy(tp
, 0x14, 0x0400, ~0x04ff);
3448 rtl_writephy(tp
, 0x13, 0x810c);
3449 rtl_w0w1_phy(tp
, 0x14, 0x7c00, ~0x7cff);
3450 rtl_writephy(tp
, 0x13, 0x810b);
3451 rtl_w0w1_phy(tp
, 0x14, 0x5a00, ~0x5aff);
3452 rtl_writephy(tp
, 0x1f, 0x0a43);
3453 rtl_writephy(tp
, 0x13, 0x80d1);
3454 rtl_w0w1_phy(tp
, 0x14, 0xff00, ~0xffff);
3455 rtl_writephy(tp
, 0x13, 0x80cd);
3456 rtl_w0w1_phy(tp
, 0x14, 0x9e00, ~0x9eff);
3457 rtl_writephy(tp
, 0x13, 0x80d3);
3458 rtl_w0w1_phy(tp
, 0x14, 0x0e00, ~0x0eff);
3459 rtl_writephy(tp
, 0x13, 0x80d5);
3460 rtl_w0w1_phy(tp
, 0x14, 0xca00, ~0xcaff);
3461 rtl_writephy(tp
, 0x13, 0x80d7);
3462 rtl_w0w1_phy(tp
, 0x14, 0x8400, ~0x84ff);
3464 /* Force PWM-mode */
3465 rtl_writephy(tp
, 0x1f, 0x0bcd);
3466 rtl_writephy(tp
, 0x14, 0x5065);
3467 rtl_writephy(tp
, 0x14, 0xd065);
3468 rtl_writephy(tp
, 0x1f, 0x0bc8);
3469 rtl_writephy(tp
, 0x12, 0x00ed);
3470 rtl_writephy(tp
, 0x1f, 0x0bcd);
3471 rtl_writephy(tp
, 0x14, 0x1065);
3472 rtl_writephy(tp
, 0x14, 0x9065);
3473 rtl_writephy(tp
, 0x14, 0x1065);
3474 rtl_writephy(tp
, 0x1f, 0x0000);
3476 rtl8168g_disable_aldps(tp
);
3477 rtl8168g_config_eee_phy(tp
);
3481 static void rtl8102e_hw_phy_config(struct rtl8169_private
*tp
)
3483 static const struct phy_reg phy_reg_init
[] = {
3490 rtl_writephy(tp
, 0x1f, 0x0000);
3491 rtl_patchphy(tp
, 0x11, 1 << 12);
3492 rtl_patchphy(tp
, 0x19, 1 << 13);
3493 rtl_patchphy(tp
, 0x10, 1 << 15);
3495 rtl_writephy_batch(tp
, phy_reg_init
);
3498 static void rtl8105e_hw_phy_config(struct rtl8169_private
*tp
)
3500 static const struct phy_reg phy_reg_init
[] = {
3514 /* Disable ALDPS before ram code */
3515 rtl_writephy(tp
, 0x1f, 0x0000);
3516 rtl_writephy(tp
, 0x18, 0x0310);
3519 rtl_apply_firmware(tp
);
3521 rtl_writephy_batch(tp
, phy_reg_init
);
3524 static void rtl8402_hw_phy_config(struct rtl8169_private
*tp
)
3526 /* Disable ALDPS before setting firmware */
3527 rtl_writephy(tp
, 0x1f, 0x0000);
3528 rtl_writephy(tp
, 0x18, 0x0310);
3531 rtl_apply_firmware(tp
);
3534 rtl_eri_write(tp
, 0x1b0, ERIAR_MASK_0011
, 0x0000);
3535 rtl_writephy(tp
, 0x1f, 0x0004);
3536 rtl_writephy(tp
, 0x10, 0x401f);
3537 rtl_writephy(tp
, 0x19, 0x7030);
3538 rtl_writephy(tp
, 0x1f, 0x0000);
3541 static void rtl8106e_hw_phy_config(struct rtl8169_private
*tp
)
3543 static const struct phy_reg phy_reg_init
[] = {
3550 /* Disable ALDPS before ram code */
3551 rtl_writephy(tp
, 0x1f, 0x0000);
3552 rtl_writephy(tp
, 0x18, 0x0310);
3555 rtl_apply_firmware(tp
);
3557 rtl_eri_write(tp
, 0x1b0, ERIAR_MASK_0011
, 0x0000);
3558 rtl_writephy_batch(tp
, phy_reg_init
);
3560 rtl_eri_write(tp
, 0x1d0, ERIAR_MASK_0011
, 0x0000);
3563 static void rtl_hw_phy_config(struct net_device
*dev
)
3565 static const rtl_generic_fct phy_configs
[] = {
3567 [RTL_GIGA_MAC_VER_02
] = rtl8169s_hw_phy_config
,
3568 [RTL_GIGA_MAC_VER_03
] = rtl8169s_hw_phy_config
,
3569 [RTL_GIGA_MAC_VER_04
] = rtl8169sb_hw_phy_config
,
3570 [RTL_GIGA_MAC_VER_05
] = rtl8169scd_hw_phy_config
,
3571 [RTL_GIGA_MAC_VER_06
] = rtl8169sce_hw_phy_config
,
3572 /* PCI-E devices. */
3573 [RTL_GIGA_MAC_VER_07
] = rtl8102e_hw_phy_config
,
3574 [RTL_GIGA_MAC_VER_08
] = rtl8102e_hw_phy_config
,
3575 [RTL_GIGA_MAC_VER_09
] = rtl8102e_hw_phy_config
,
3576 [RTL_GIGA_MAC_VER_10
] = NULL
,
3577 [RTL_GIGA_MAC_VER_11
] = rtl8168bb_hw_phy_config
,
3578 [RTL_GIGA_MAC_VER_12
] = rtl8168bef_hw_phy_config
,
3579 [RTL_GIGA_MAC_VER_13
] = NULL
,
3580 [RTL_GIGA_MAC_VER_14
] = NULL
,
3581 [RTL_GIGA_MAC_VER_15
] = NULL
,
3582 [RTL_GIGA_MAC_VER_16
] = NULL
,
3583 [RTL_GIGA_MAC_VER_17
] = rtl8168bef_hw_phy_config
,
3584 [RTL_GIGA_MAC_VER_18
] = rtl8168cp_1_hw_phy_config
,
3585 [RTL_GIGA_MAC_VER_19
] = rtl8168c_1_hw_phy_config
,
3586 [RTL_GIGA_MAC_VER_20
] = rtl8168c_2_hw_phy_config
,
3587 [RTL_GIGA_MAC_VER_21
] = rtl8168c_3_hw_phy_config
,
3588 [RTL_GIGA_MAC_VER_22
] = rtl8168c_4_hw_phy_config
,
3589 [RTL_GIGA_MAC_VER_23
] = rtl8168cp_2_hw_phy_config
,
3590 [RTL_GIGA_MAC_VER_24
] = rtl8168cp_2_hw_phy_config
,
3591 [RTL_GIGA_MAC_VER_25
] = rtl8168d_1_hw_phy_config
,
3592 [RTL_GIGA_MAC_VER_26
] = rtl8168d_2_hw_phy_config
,
3593 [RTL_GIGA_MAC_VER_27
] = rtl8168d_3_hw_phy_config
,
3594 [RTL_GIGA_MAC_VER_28
] = rtl8168d_4_hw_phy_config
,
3595 [RTL_GIGA_MAC_VER_29
] = rtl8105e_hw_phy_config
,
3596 [RTL_GIGA_MAC_VER_30
] = rtl8105e_hw_phy_config
,
3597 [RTL_GIGA_MAC_VER_31
] = NULL
,
3598 [RTL_GIGA_MAC_VER_32
] = rtl8168e_1_hw_phy_config
,
3599 [RTL_GIGA_MAC_VER_33
] = rtl8168e_1_hw_phy_config
,
3600 [RTL_GIGA_MAC_VER_34
] = rtl8168e_2_hw_phy_config
,
3601 [RTL_GIGA_MAC_VER_35
] = rtl8168f_1_hw_phy_config
,
3602 [RTL_GIGA_MAC_VER_36
] = rtl8168f_2_hw_phy_config
,
3603 [RTL_GIGA_MAC_VER_37
] = rtl8402_hw_phy_config
,
3604 [RTL_GIGA_MAC_VER_38
] = rtl8411_hw_phy_config
,
3605 [RTL_GIGA_MAC_VER_39
] = rtl8106e_hw_phy_config
,
3606 [RTL_GIGA_MAC_VER_40
] = rtl8168g_1_hw_phy_config
,
3607 [RTL_GIGA_MAC_VER_41
] = NULL
,
3608 [RTL_GIGA_MAC_VER_42
] = rtl8168g_2_hw_phy_config
,
3609 [RTL_GIGA_MAC_VER_43
] = rtl8168g_2_hw_phy_config
,
3610 [RTL_GIGA_MAC_VER_44
] = rtl8168g_2_hw_phy_config
,
3611 [RTL_GIGA_MAC_VER_45
] = rtl8168h_1_hw_phy_config
,
3612 [RTL_GIGA_MAC_VER_46
] = rtl8168h_2_hw_phy_config
,
3613 [RTL_GIGA_MAC_VER_47
] = rtl8168h_1_hw_phy_config
,
3614 [RTL_GIGA_MAC_VER_48
] = rtl8168h_2_hw_phy_config
,
3615 [RTL_GIGA_MAC_VER_49
] = rtl8168ep_1_hw_phy_config
,
3616 [RTL_GIGA_MAC_VER_50
] = rtl8168ep_2_hw_phy_config
,
3617 [RTL_GIGA_MAC_VER_51
] = rtl8168ep_2_hw_phy_config
,
3619 struct rtl8169_private
*tp
= netdev_priv(dev
);
3621 if (phy_configs
[tp
->mac_version
])
3622 phy_configs
[tp
->mac_version
](tp
);
3625 static void rtl_schedule_task(struct rtl8169_private
*tp
, enum rtl_flag flag
)
3627 if (!test_and_set_bit(flag
, tp
->wk
.flags
))
3628 schedule_work(&tp
->wk
.work
);
3631 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
3633 rtl_hw_phy_config(dev
);
3635 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
3636 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
3637 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
3638 netif_dbg(tp
, drv
, dev
,
3639 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3640 RTL_W8(tp
, 0x82, 0x01);
3643 /* We may have called phy_speed_down before */
3644 phy_speed_up(tp
->phydev
);
3646 genphy_soft_reset(tp
->phydev
);
3649 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
3653 rtl_unlock_config_regs(tp
);
3655 RTL_W32(tp
, MAC4
, addr
[4] | addr
[5] << 8);
3658 RTL_W32(tp
, MAC0
, addr
[0] | addr
[1] << 8 | addr
[2] << 16 | addr
[3] << 24);
3661 if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
)
3662 rtl_rar_exgmac_set(tp
, addr
);
3664 rtl_lock_config_regs(tp
);
3666 rtl_unlock_work(tp
);
3669 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
3671 struct rtl8169_private
*tp
= netdev_priv(dev
);
3672 struct device
*d
= tp_to_dev(tp
);
3675 ret
= eth_mac_addr(dev
, p
);
3679 pm_runtime_get_noresume(d
);
3681 if (pm_runtime_active(d
))
3682 rtl_rar_set(tp
, dev
->dev_addr
);
3684 pm_runtime_put_noidle(d
);
3689 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
3691 struct rtl8169_private
*tp
= netdev_priv(dev
);
3693 if (!netif_running(dev
))
3696 return phy_mii_ioctl(tp
->phydev
, ifr
, cmd
);
3699 static void rtl_wol_suspend_quirk(struct rtl8169_private
*tp
)
3701 switch (tp
->mac_version
) {
3702 case RTL_GIGA_MAC_VER_25
:
3703 case RTL_GIGA_MAC_VER_26
:
3704 case RTL_GIGA_MAC_VER_29
:
3705 case RTL_GIGA_MAC_VER_30
:
3706 case RTL_GIGA_MAC_VER_32
:
3707 case RTL_GIGA_MAC_VER_33
:
3708 case RTL_GIGA_MAC_VER_34
:
3709 case RTL_GIGA_MAC_VER_37
... RTL_GIGA_MAC_VER_51
:
3710 RTL_W32(tp
, RxConfig
, RTL_R32(tp
, RxConfig
) |
3711 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
);
3718 static void rtl_pll_power_down(struct rtl8169_private
*tp
)
3720 if (r8168_check_dash(tp
))
3723 if (tp
->mac_version
== RTL_GIGA_MAC_VER_32
||
3724 tp
->mac_version
== RTL_GIGA_MAC_VER_33
)
3725 rtl_ephy_write(tp
, 0x19, 0xff64);
3727 if (device_may_wakeup(tp_to_dev(tp
))) {
3728 phy_speed_down(tp
->phydev
, false);
3729 rtl_wol_suspend_quirk(tp
);
3733 switch (tp
->mac_version
) {
3734 case RTL_GIGA_MAC_VER_25
... RTL_GIGA_MAC_VER_33
:
3735 case RTL_GIGA_MAC_VER_37
:
3736 case RTL_GIGA_MAC_VER_39
:
3737 case RTL_GIGA_MAC_VER_43
:
3738 case RTL_GIGA_MAC_VER_44
:
3739 case RTL_GIGA_MAC_VER_45
:
3740 case RTL_GIGA_MAC_VER_46
:
3741 case RTL_GIGA_MAC_VER_47
:
3742 case RTL_GIGA_MAC_VER_48
:
3743 case RTL_GIGA_MAC_VER_50
:
3744 case RTL_GIGA_MAC_VER_51
:
3745 RTL_W8(tp
, PMCH
, RTL_R8(tp
, PMCH
) & ~0x80);
3747 case RTL_GIGA_MAC_VER_40
:
3748 case RTL_GIGA_MAC_VER_41
:
3749 case RTL_GIGA_MAC_VER_49
:
3750 rtl_eri_clear_bits(tp
, 0x1a8, ERIAR_MASK_1111
, 0xfc000000);
3751 RTL_W8(tp
, PMCH
, RTL_R8(tp
, PMCH
) & ~0x80);
3758 static void rtl_pll_power_up(struct rtl8169_private
*tp
)
3760 switch (tp
->mac_version
) {
3761 case RTL_GIGA_MAC_VER_25
... RTL_GIGA_MAC_VER_33
:
3762 case RTL_GIGA_MAC_VER_37
:
3763 case RTL_GIGA_MAC_VER_39
:
3764 case RTL_GIGA_MAC_VER_43
:
3765 RTL_W8(tp
, PMCH
, RTL_R8(tp
, PMCH
) | 0x80);
3767 case RTL_GIGA_MAC_VER_44
:
3768 case RTL_GIGA_MAC_VER_45
:
3769 case RTL_GIGA_MAC_VER_46
:
3770 case RTL_GIGA_MAC_VER_47
:
3771 case RTL_GIGA_MAC_VER_48
:
3772 case RTL_GIGA_MAC_VER_50
:
3773 case RTL_GIGA_MAC_VER_51
:
3774 RTL_W8(tp
, PMCH
, RTL_R8(tp
, PMCH
) | 0xc0);
3776 case RTL_GIGA_MAC_VER_40
:
3777 case RTL_GIGA_MAC_VER_41
:
3778 case RTL_GIGA_MAC_VER_49
:
3779 RTL_W8(tp
, PMCH
, RTL_R8(tp
, PMCH
) | 0xc0);
3780 rtl_eri_set_bits(tp
, 0x1a8, ERIAR_MASK_1111
, 0xfc000000);
3786 phy_resume(tp
->phydev
);
3787 /* give MAC/PHY some time to resume */
3791 static void rtl_init_rxcfg(struct rtl8169_private
*tp
)
3793 switch (tp
->mac_version
) {
3794 case RTL_GIGA_MAC_VER_02
... RTL_GIGA_MAC_VER_06
:
3795 case RTL_GIGA_MAC_VER_10
... RTL_GIGA_MAC_VER_17
:
3796 RTL_W32(tp
, RxConfig
, RX_FIFO_THRESH
| RX_DMA_BURST
);
3798 case RTL_GIGA_MAC_VER_18
... RTL_GIGA_MAC_VER_24
:
3799 case RTL_GIGA_MAC_VER_34
... RTL_GIGA_MAC_VER_36
:
3800 case RTL_GIGA_MAC_VER_38
:
3801 RTL_W32(tp
, RxConfig
, RX128_INT_EN
| RX_MULTI_EN
| RX_DMA_BURST
);
3803 case RTL_GIGA_MAC_VER_40
... RTL_GIGA_MAC_VER_51
:
3804 RTL_W32(tp
, RxConfig
, RX128_INT_EN
| RX_MULTI_EN
| RX_DMA_BURST
| RX_EARLY_OFF
);
3807 RTL_W32(tp
, RxConfig
, RX128_INT_EN
| RX_DMA_BURST
);
3812 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
3814 tp
->dirty_tx
= tp
->cur_tx
= tp
->cur_rx
= 0;
3817 static void r8168c_hw_jumbo_enable(struct rtl8169_private
*tp
)
3819 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) | Jumbo_En0
);
3820 RTL_W8(tp
, Config4
, RTL_R8(tp
, Config4
) | Jumbo_En1
);
3821 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_512B
);
3824 static void r8168c_hw_jumbo_disable(struct rtl8169_private
*tp
)
3826 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) & ~Jumbo_En0
);
3827 RTL_W8(tp
, Config4
, RTL_R8(tp
, Config4
) & ~Jumbo_En1
);
3828 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
3831 static void r8168dp_hw_jumbo_enable(struct rtl8169_private
*tp
)
3833 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) | Jumbo_En0
);
3836 static void r8168dp_hw_jumbo_disable(struct rtl8169_private
*tp
)
3838 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) & ~Jumbo_En0
);
3841 static void r8168e_hw_jumbo_enable(struct rtl8169_private
*tp
)
3843 RTL_W8(tp
, MaxTxPacketSize
, 0x3f);
3844 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) | Jumbo_En0
);
3845 RTL_W8(tp
, Config4
, RTL_R8(tp
, Config4
) | 0x01);
3846 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_512B
);
3849 static void r8168e_hw_jumbo_disable(struct rtl8169_private
*tp
)
3851 RTL_W8(tp
, MaxTxPacketSize
, 0x0c);
3852 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) & ~Jumbo_En0
);
3853 RTL_W8(tp
, Config4
, RTL_R8(tp
, Config4
) & ~0x01);
3854 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
3857 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private
*tp
)
3859 rtl_tx_performance_tweak(tp
,
3860 PCI_EXP_DEVCTL_READRQ_512B
| PCI_EXP_DEVCTL_NOSNOOP_EN
);
3863 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private
*tp
)
3865 rtl_tx_performance_tweak(tp
,
3866 PCI_EXP_DEVCTL_READRQ_4096B
| PCI_EXP_DEVCTL_NOSNOOP_EN
);
3869 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private
*tp
)
3871 r8168b_0_hw_jumbo_enable(tp
);
3873 RTL_W8(tp
, Config4
, RTL_R8(tp
, Config4
) | (1 << 0));
3876 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private
*tp
)
3878 r8168b_0_hw_jumbo_disable(tp
);
3880 RTL_W8(tp
, Config4
, RTL_R8(tp
, Config4
) & ~(1 << 0));
3883 static void rtl_hw_jumbo_enable(struct rtl8169_private
*tp
)
3885 rtl_unlock_config_regs(tp
);
3886 switch (tp
->mac_version
) {
3887 case RTL_GIGA_MAC_VER_11
:
3888 r8168b_0_hw_jumbo_enable(tp
);
3890 case RTL_GIGA_MAC_VER_12
:
3891 case RTL_GIGA_MAC_VER_17
:
3892 r8168b_1_hw_jumbo_enable(tp
);
3894 case RTL_GIGA_MAC_VER_18
... RTL_GIGA_MAC_VER_26
:
3895 r8168c_hw_jumbo_enable(tp
);
3897 case RTL_GIGA_MAC_VER_27
... RTL_GIGA_MAC_VER_28
:
3898 r8168dp_hw_jumbo_enable(tp
);
3900 case RTL_GIGA_MAC_VER_31
... RTL_GIGA_MAC_VER_34
:
3901 r8168e_hw_jumbo_enable(tp
);
3906 rtl_lock_config_regs(tp
);
3909 static void rtl_hw_jumbo_disable(struct rtl8169_private
*tp
)
3911 rtl_unlock_config_regs(tp
);
3912 switch (tp
->mac_version
) {
3913 case RTL_GIGA_MAC_VER_11
:
3914 r8168b_0_hw_jumbo_disable(tp
);
3916 case RTL_GIGA_MAC_VER_12
:
3917 case RTL_GIGA_MAC_VER_17
:
3918 r8168b_1_hw_jumbo_disable(tp
);
3920 case RTL_GIGA_MAC_VER_18
... RTL_GIGA_MAC_VER_26
:
3921 r8168c_hw_jumbo_disable(tp
);
3923 case RTL_GIGA_MAC_VER_27
... RTL_GIGA_MAC_VER_28
:
3924 r8168dp_hw_jumbo_disable(tp
);
3926 case RTL_GIGA_MAC_VER_31
... RTL_GIGA_MAC_VER_34
:
3927 r8168e_hw_jumbo_disable(tp
);
3932 rtl_lock_config_regs(tp
);
3935 DECLARE_RTL_COND(rtl_chipcmd_cond
)
3937 return RTL_R8(tp
, ChipCmd
) & CmdReset
;
3940 static void rtl_hw_reset(struct rtl8169_private
*tp
)
3942 RTL_W8(tp
, ChipCmd
, CmdReset
);
3944 rtl_udelay_loop_wait_low(tp
, &rtl_chipcmd_cond
, 100, 100);
3947 static void rtl_request_firmware(struct rtl8169_private
*tp
)
3949 struct rtl_fw
*rtl_fw
;
3951 /* firmware loaded already or no firmware available */
3952 if (tp
->rtl_fw
|| !tp
->fw_name
)
3955 rtl_fw
= kzalloc(sizeof(*rtl_fw
), GFP_KERNEL
);
3957 netif_warn(tp
, ifup
, tp
->dev
, "Unable to load firmware, out of memory\n");
3961 rtl_fw
->phy_write
= rtl_writephy
;
3962 rtl_fw
->phy_read
= rtl_readphy
;
3963 rtl_fw
->mac_mcu_write
= mac_mcu_write
;
3964 rtl_fw
->mac_mcu_read
= mac_mcu_read
;
3965 rtl_fw
->fw_name
= tp
->fw_name
;
3966 rtl_fw
->dev
= tp_to_dev(tp
);
3968 if (rtl_fw_request_firmware(rtl_fw
))
3971 tp
->rtl_fw
= rtl_fw
;
3974 static void rtl_rx_close(struct rtl8169_private
*tp
)
3976 RTL_W32(tp
, RxConfig
, RTL_R32(tp
, RxConfig
) & ~RX_CONFIG_ACCEPT_MASK
);
3979 DECLARE_RTL_COND(rtl_npq_cond
)
3981 return RTL_R8(tp
, TxPoll
) & NPQ
;
3984 DECLARE_RTL_COND(rtl_txcfg_empty_cond
)
3986 return RTL_R32(tp
, TxConfig
) & TXCFG_EMPTY
;
3989 static void rtl8169_hw_reset(struct rtl8169_private
*tp
)
3991 /* Disable interrupts */
3992 rtl8169_irq_mask_and_ack(tp
);
3996 switch (tp
->mac_version
) {
3997 case RTL_GIGA_MAC_VER_27
:
3998 case RTL_GIGA_MAC_VER_28
:
3999 case RTL_GIGA_MAC_VER_31
:
4000 rtl_udelay_loop_wait_low(tp
, &rtl_npq_cond
, 20, 42*42);
4002 case RTL_GIGA_MAC_VER_34
... RTL_GIGA_MAC_VER_38
:
4003 case RTL_GIGA_MAC_VER_40
... RTL_GIGA_MAC_VER_51
:
4004 RTL_W8(tp
, ChipCmd
, RTL_R8(tp
, ChipCmd
) | StopReq
);
4005 rtl_udelay_loop_wait_high(tp
, &rtl_txcfg_empty_cond
, 100, 666);
4008 RTL_W8(tp
, ChipCmd
, RTL_R8(tp
, ChipCmd
) | StopReq
);
4016 static void rtl_set_tx_config_registers(struct rtl8169_private
*tp
)
4018 u32 val
= TX_DMA_BURST
<< TxDMAShift
|
4019 InterFrameGap
<< TxInterFrameGapShift
;
4021 if (rtl_is_8168evl_up(tp
))
4022 val
|= TXCFG_AUTO_FIFO
;
4024 RTL_W32(tp
, TxConfig
, val
);
4027 static void rtl_set_rx_max_size(struct rtl8169_private
*tp
)
4029 /* Low hurts. Let's disable the filtering. */
4030 RTL_W16(tp
, RxMaxSize
, R8169_RX_BUF_SIZE
+ 1);
4033 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
)
4036 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4037 * register to be written before TxDescAddrLow to work.
4038 * Switching from MMIO to I/O access fixes the issue as well.
4040 RTL_W32(tp
, TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
4041 RTL_W32(tp
, TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_BIT_MASK(32));
4042 RTL_W32(tp
, RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
4043 RTL_W32(tp
, RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_BIT_MASK(32));
4046 static void rtl8169_set_magic_reg(struct rtl8169_private
*tp
, unsigned mac_version
)
4050 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
4052 else if (tp
->mac_version
== RTL_GIGA_MAC_VER_06
)
4057 if (RTL_R8(tp
, Config2
) & PCI_Clock_66MHz
)
4060 RTL_W32(tp
, 0x7c, val
);
4063 static void rtl_set_rx_mode(struct net_device
*dev
)
4065 u32 rx_mode
= AcceptBroadcast
| AcceptMyPhys
| AcceptMulticast
;
4066 /* Multicast hash filter */
4067 u32 mc_filter
[2] = { 0xffffffff, 0xffffffff };
4068 struct rtl8169_private
*tp
= netdev_priv(dev
);
4071 if (dev
->flags
& IFF_PROMISC
) {
4072 /* Unconditionally log net taps. */
4073 netif_notice(tp
, link
, dev
, "Promiscuous mode enabled\n");
4074 rx_mode
|= AcceptAllPhys
;
4075 } else if (netdev_mc_count(dev
) > MC_FILTER_LIMIT
||
4076 dev
->flags
& IFF_ALLMULTI
||
4077 tp
->mac_version
== RTL_GIGA_MAC_VER_35
) {
4078 /* accept all multicasts */
4079 } else if (netdev_mc_empty(dev
)) {
4080 rx_mode
&= ~AcceptMulticast
;
4082 struct netdev_hw_addr
*ha
;
4084 mc_filter
[1] = mc_filter
[0] = 0;
4085 netdev_for_each_mc_addr(ha
, dev
) {
4086 u32 bit_nr
= ether_crc(ETH_ALEN
, ha
->addr
) >> 26;
4087 mc_filter
[bit_nr
>> 5] |= BIT(bit_nr
& 31);
4090 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
4092 mc_filter
[0] = swab32(mc_filter
[1]);
4093 mc_filter
[1] = swab32(tmp
);
4097 if (dev
->features
& NETIF_F_RXALL
)
4098 rx_mode
|= (AcceptErr
| AcceptRunt
);
4100 RTL_W32(tp
, MAR0
+ 4, mc_filter
[1]);
4101 RTL_W32(tp
, MAR0
+ 0, mc_filter
[0]);
4103 tmp
= RTL_R32(tp
, RxConfig
);
4104 RTL_W32(tp
, RxConfig
, (tmp
& ~RX_CONFIG_ACCEPT_MASK
) | rx_mode
);
4107 DECLARE_RTL_COND(rtl_csiar_cond
)
4109 return RTL_R32(tp
, CSIAR
) & CSIAR_FLAG
;
4112 static void rtl_csi_write(struct rtl8169_private
*tp
, int addr
, int value
)
4114 u32 func
= PCI_FUNC(tp
->pci_dev
->devfn
);
4116 RTL_W32(tp
, CSIDR
, value
);
4117 RTL_W32(tp
, CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
4118 CSIAR_BYTE_ENABLE
| func
<< 16);
4120 rtl_udelay_loop_wait_low(tp
, &rtl_csiar_cond
, 10, 100);
4123 static u32
rtl_csi_read(struct rtl8169_private
*tp
, int addr
)
4125 u32 func
= PCI_FUNC(tp
->pci_dev
->devfn
);
4127 RTL_W32(tp
, CSIAR
, (addr
& CSIAR_ADDR_MASK
) | func
<< 16 |
4130 return rtl_udelay_loop_wait_high(tp
, &rtl_csiar_cond
, 10, 100) ?
4131 RTL_R32(tp
, CSIDR
) : ~0;
4134 static void rtl_csi_access_enable(struct rtl8169_private
*tp
, u8 val
)
4136 struct pci_dev
*pdev
= tp
->pci_dev
;
4139 /* According to Realtek the value at config space address 0x070f
4140 * controls the L0s/L1 entrance latency. We try standard ECAM access
4141 * first and if it fails fall back to CSI.
4143 if (pdev
->cfg_size
> 0x070f &&
4144 pci_write_config_byte(pdev
, 0x070f, val
) == PCIBIOS_SUCCESSFUL
)
4147 netdev_notice_once(tp
->dev
,
4148 "No native access to PCI extended config space, falling back to CSI\n");
4149 csi
= rtl_csi_read(tp
, 0x070c) & 0x00ffffff;
4150 rtl_csi_write(tp
, 0x070c, csi
| val
<< 24);
4153 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private
*tp
)
4155 rtl_csi_access_enable(tp
, 0x27);
4159 unsigned int offset
;
4164 static void __rtl_ephy_init(struct rtl8169_private
*tp
,
4165 const struct ephy_info
*e
, int len
)
4170 w
= (rtl_ephy_read(tp
, e
->offset
) & ~e
->mask
) | e
->bits
;
4171 rtl_ephy_write(tp
, e
->offset
, w
);
4176 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
4178 static void rtl_disable_clock_request(struct rtl8169_private
*tp
)
4180 pcie_capability_clear_word(tp
->pci_dev
, PCI_EXP_LNKCTL
,
4181 PCI_EXP_LNKCTL_CLKREQ_EN
);
4184 static void rtl_enable_clock_request(struct rtl8169_private
*tp
)
4186 pcie_capability_set_word(tp
->pci_dev
, PCI_EXP_LNKCTL
,
4187 PCI_EXP_LNKCTL_CLKREQ_EN
);
4190 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private
*tp
)
4192 /* work around an issue when PCI reset occurs during L2/L3 state */
4193 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) & ~Rdy_to_L23
);
4196 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private
*tp
, bool enable
)
4198 /* Don't enable ASPM in the chip if OS can't control ASPM */
4199 if (enable
&& tp
->aspm_manageable
) {
4200 RTL_W8(tp
, Config5
, RTL_R8(tp
, Config5
) | ASPM_en
);
4201 RTL_W8(tp
, Config2
, RTL_R8(tp
, Config2
) | ClkReqEn
);
4203 RTL_W8(tp
, Config2
, RTL_R8(tp
, Config2
) & ~ClkReqEn
);
4204 RTL_W8(tp
, Config5
, RTL_R8(tp
, Config5
) & ~ASPM_en
);
4210 static void rtl_set_fifo_size(struct rtl8169_private
*tp
, u16 rx_stat
,
4211 u16 tx_stat
, u16 rx_dyn
, u16 tx_dyn
)
4213 /* Usage of dynamic vs. static FIFO is controlled by bit
4214 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
4216 rtl_eri_write(tp
, 0xc8, ERIAR_MASK_1111
, (rx_stat
<< 16) | rx_dyn
);
4217 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_1111
, (tx_stat
<< 16) | tx_dyn
);
4220 static void rtl8168g_set_pause_thresholds(struct rtl8169_private
*tp
,
4223 /* FIFO thresholds for pause flow control */
4224 rtl_eri_write(tp
, 0xcc, ERIAR_MASK_0001
, low
);
4225 rtl_eri_write(tp
, 0xd0, ERIAR_MASK_0001
, high
);
4228 static void rtl_hw_start_8168bb(struct rtl8169_private
*tp
)
4230 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) & ~Beacon_en
);
4232 if (tp
->dev
->mtu
<= ETH_DATA_LEN
) {
4233 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
|
4234 PCI_EXP_DEVCTL_NOSNOOP_EN
);
4238 static void rtl_hw_start_8168bef(struct rtl8169_private
*tp
)
4240 rtl_hw_start_8168bb(tp
);
4242 RTL_W8(tp
, Config4
, RTL_R8(tp
, Config4
) & ~(1 << 0));
4245 static void __rtl_hw_start_8168cp(struct rtl8169_private
*tp
)
4247 RTL_W8(tp
, Config1
, RTL_R8(tp
, Config1
) | Speed_down
);
4249 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) & ~Beacon_en
);
4251 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
4252 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
4254 rtl_disable_clock_request(tp
);
4257 static void rtl_hw_start_8168cp_1(struct rtl8169_private
*tp
)
4259 static const struct ephy_info e_info_8168cp
[] = {
4260 { 0x01, 0, 0x0001 },
4261 { 0x02, 0x0800, 0x1000 },
4262 { 0x03, 0, 0x0042 },
4263 { 0x06, 0x0080, 0x0000 },
4267 rtl_set_def_aspm_entry_latency(tp
);
4269 rtl_ephy_init(tp
, e_info_8168cp
);
4271 __rtl_hw_start_8168cp(tp
);
4274 static void rtl_hw_start_8168cp_2(struct rtl8169_private
*tp
)
4276 rtl_set_def_aspm_entry_latency(tp
);
4278 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) & ~Beacon_en
);
4280 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
4281 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
4284 static void rtl_hw_start_8168cp_3(struct rtl8169_private
*tp
)
4286 rtl_set_def_aspm_entry_latency(tp
);
4288 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) & ~Beacon_en
);
4291 RTL_W8(tp
, DBG_REG
, 0x20);
4293 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
4294 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
4297 static void rtl_hw_start_8168c_1(struct rtl8169_private
*tp
)
4299 static const struct ephy_info e_info_8168c_1
[] = {
4300 { 0x02, 0x0800, 0x1000 },
4301 { 0x03, 0, 0x0002 },
4302 { 0x06, 0x0080, 0x0000 }
4305 rtl_set_def_aspm_entry_latency(tp
);
4307 RTL_W8(tp
, DBG_REG
, 0x06 | FIX_NAK_1
| FIX_NAK_2
);
4309 rtl_ephy_init(tp
, e_info_8168c_1
);
4311 __rtl_hw_start_8168cp(tp
);
4314 static void rtl_hw_start_8168c_2(struct rtl8169_private
*tp
)
4316 static const struct ephy_info e_info_8168c_2
[] = {
4317 { 0x01, 0, 0x0001 },
4318 { 0x03, 0x0400, 0x0020 }
4321 rtl_set_def_aspm_entry_latency(tp
);
4323 rtl_ephy_init(tp
, e_info_8168c_2
);
4325 __rtl_hw_start_8168cp(tp
);
4328 static void rtl_hw_start_8168c_3(struct rtl8169_private
*tp
)
4330 rtl_hw_start_8168c_2(tp
);
4333 static void rtl_hw_start_8168c_4(struct rtl8169_private
*tp
)
4335 rtl_set_def_aspm_entry_latency(tp
);
4337 __rtl_hw_start_8168cp(tp
);
4340 static void rtl_hw_start_8168d(struct rtl8169_private
*tp
)
4342 rtl_set_def_aspm_entry_latency(tp
);
4344 rtl_disable_clock_request(tp
);
4346 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
4347 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
4350 static void rtl_hw_start_8168dp(struct rtl8169_private
*tp
)
4352 rtl_set_def_aspm_entry_latency(tp
);
4354 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
4355 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
4357 rtl_disable_clock_request(tp
);
4360 static void rtl_hw_start_8168d_4(struct rtl8169_private
*tp
)
4362 static const struct ephy_info e_info_8168d_4
[] = {
4363 { 0x0b, 0x0000, 0x0048 },
4364 { 0x19, 0x0020, 0x0050 },
4365 { 0x0c, 0x0100, 0x0020 },
4366 { 0x10, 0x0004, 0x0000 },
4369 rtl_set_def_aspm_entry_latency(tp
);
4371 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
4373 rtl_ephy_init(tp
, e_info_8168d_4
);
4375 rtl_enable_clock_request(tp
);
4378 static void rtl_hw_start_8168e_1(struct rtl8169_private
*tp
)
4380 static const struct ephy_info e_info_8168e_1
[] = {
4381 { 0x00, 0x0200, 0x0100 },
4382 { 0x00, 0x0000, 0x0004 },
4383 { 0x06, 0x0002, 0x0001 },
4384 { 0x06, 0x0000, 0x0030 },
4385 { 0x07, 0x0000, 0x2000 },
4386 { 0x00, 0x0000, 0x0020 },
4387 { 0x03, 0x5800, 0x2000 },
4388 { 0x03, 0x0000, 0x0001 },
4389 { 0x01, 0x0800, 0x1000 },
4390 { 0x07, 0x0000, 0x4000 },
4391 { 0x1e, 0x0000, 0x2000 },
4392 { 0x19, 0xffff, 0xfe6c },
4393 { 0x0a, 0x0000, 0x0040 }
4396 rtl_set_def_aspm_entry_latency(tp
);
4398 rtl_ephy_init(tp
, e_info_8168e_1
);
4400 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
4401 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
4403 rtl_disable_clock_request(tp
);
4405 /* Reset tx FIFO pointer */
4406 RTL_W32(tp
, MISC
, RTL_R32(tp
, MISC
) | TXPLA_RST
);
4407 RTL_W32(tp
, MISC
, RTL_R32(tp
, MISC
) & ~TXPLA_RST
);
4409 RTL_W8(tp
, Config5
, RTL_R8(tp
, Config5
) & ~Spi_en
);
4412 static void rtl_hw_start_8168e_2(struct rtl8169_private
*tp
)
4414 static const struct ephy_info e_info_8168e_2
[] = {
4415 { 0x09, 0x0000, 0x0080 },
4416 { 0x19, 0x0000, 0x0224 },
4417 { 0x00, 0x0000, 0x0004 },
4418 { 0x0c, 0x3df0, 0x0200 },
4421 rtl_set_def_aspm_entry_latency(tp
);
4423 rtl_ephy_init(tp
, e_info_8168e_2
);
4425 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
4426 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
4428 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000);
4429 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000);
4430 rtl_set_fifo_size(tp
, 0x10, 0x10, 0x02, 0x06);
4431 rtl_eri_write(tp
, 0xcc, ERIAR_MASK_1111
, 0x00000050);
4432 rtl_eri_write(tp
, 0xd0, ERIAR_MASK_1111
, 0x07ff0060);
4433 rtl_eri_set_bits(tp
, 0x1b0, ERIAR_MASK_0001
, BIT(4));
4434 rtl_w0w1_eri(tp
, 0x0d4, ERIAR_MASK_0011
, 0x0c00, 0xff00);
4436 rtl_disable_clock_request(tp
);
4438 RTL_W8(tp
, MCU
, RTL_R8(tp
, MCU
) & ~NOW_IS_OOB
);
4440 rtl8168_config_eee_mac(tp
);
4442 RTL_W8(tp
, DLLPR
, RTL_R8(tp
, DLLPR
) | PFM_EN
);
4443 RTL_W32(tp
, MISC
, RTL_R32(tp
, MISC
) | PWM_EN
);
4444 RTL_W8(tp
, Config5
, RTL_R8(tp
, Config5
) & ~Spi_en
);
4446 rtl_hw_aspm_clkreq_enable(tp
, true);
4449 static void rtl_hw_start_8168f(struct rtl8169_private
*tp
)
4451 rtl_set_def_aspm_entry_latency(tp
);
4453 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
4455 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000);
4456 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000);
4457 rtl_set_fifo_size(tp
, 0x10, 0x10, 0x02, 0x06);
4458 rtl_reset_packet_filter(tp
);
4459 rtl_eri_set_bits(tp
, 0x1b0, ERIAR_MASK_0001
, BIT(4));
4460 rtl_eri_set_bits(tp
, 0x1d0, ERIAR_MASK_0001
, BIT(4));
4461 rtl_eri_write(tp
, 0xcc, ERIAR_MASK_1111
, 0x00000050);
4462 rtl_eri_write(tp
, 0xd0, ERIAR_MASK_1111
, 0x00000060);
4464 rtl_disable_clock_request(tp
);
4466 RTL_W8(tp
, MCU
, RTL_R8(tp
, MCU
) & ~NOW_IS_OOB
);
4467 RTL_W8(tp
, DLLPR
, RTL_R8(tp
, DLLPR
) | PFM_EN
);
4468 RTL_W32(tp
, MISC
, RTL_R32(tp
, MISC
) | PWM_EN
);
4469 RTL_W8(tp
, Config5
, RTL_R8(tp
, Config5
) & ~Spi_en
);
4471 rtl8168_config_eee_mac(tp
);
4474 static void rtl_hw_start_8168f_1(struct rtl8169_private
*tp
)
4476 static const struct ephy_info e_info_8168f_1
[] = {
4477 { 0x06, 0x00c0, 0x0020 },
4478 { 0x08, 0x0001, 0x0002 },
4479 { 0x09, 0x0000, 0x0080 },
4480 { 0x19, 0x0000, 0x0224 },
4481 { 0x00, 0x0000, 0x0004 },
4482 { 0x0c, 0x3df0, 0x0200 },
4485 rtl_hw_start_8168f(tp
);
4487 rtl_ephy_init(tp
, e_info_8168f_1
);
4489 rtl_w0w1_eri(tp
, 0x0d4, ERIAR_MASK_0011
, 0x0c00, 0xff00);
4492 static void rtl_hw_start_8411(struct rtl8169_private
*tp
)
4494 static const struct ephy_info e_info_8168f_1
[] = {
4495 { 0x06, 0x00c0, 0x0020 },
4496 { 0x0f, 0xffff, 0x5200 },
4497 { 0x19, 0x0000, 0x0224 },
4498 { 0x00, 0x0000, 0x0004 },
4499 { 0x0c, 0x3df0, 0x0200 },
4502 rtl_hw_start_8168f(tp
);
4503 rtl_pcie_state_l2l3_disable(tp
);
4505 rtl_ephy_init(tp
, e_info_8168f_1
);
4507 rtl_eri_set_bits(tp
, 0x0d4, ERIAR_MASK_0011
, 0x0c00);
4510 static void rtl_hw_start_8168g(struct rtl8169_private
*tp
)
4512 rtl_set_fifo_size(tp
, 0x08, 0x10, 0x02, 0x06);
4513 rtl8168g_set_pause_thresholds(tp
, 0x38, 0x48);
4515 rtl_set_def_aspm_entry_latency(tp
);
4517 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
4519 rtl_reset_packet_filter(tp
);
4520 rtl_eri_write(tp
, 0x2f8, ERIAR_MASK_0011
, 0x1d8f);
4522 RTL_W32(tp
, MISC
, RTL_R32(tp
, MISC
) & ~RXDV_GATED_EN
);
4524 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000);
4525 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000);
4527 rtl8168_config_eee_mac(tp
);
4529 rtl_w0w1_eri(tp
, 0x2fc, ERIAR_MASK_0001
, 0x01, 0x06);
4530 rtl_eri_clear_bits(tp
, 0x1b0, ERIAR_MASK_0011
, BIT(12));
4532 rtl_pcie_state_l2l3_disable(tp
);
4535 static void rtl_hw_start_8168g_1(struct rtl8169_private
*tp
)
4537 static const struct ephy_info e_info_8168g_1
[] = {
4538 { 0x00, 0x0008, 0x0000 },
4539 { 0x0c, 0x3ff0, 0x0820 },
4540 { 0x1e, 0x0000, 0x0001 },
4541 { 0x19, 0x8000, 0x0000 }
4544 rtl_hw_start_8168g(tp
);
4546 /* disable aspm and clock request before access ephy */
4547 rtl_hw_aspm_clkreq_enable(tp
, false);
4548 rtl_ephy_init(tp
, e_info_8168g_1
);
4549 rtl_hw_aspm_clkreq_enable(tp
, true);
4552 static void rtl_hw_start_8168g_2(struct rtl8169_private
*tp
)
4554 static const struct ephy_info e_info_8168g_2
[] = {
4555 { 0x00, 0x0008, 0x0000 },
4556 { 0x0c, 0x3ff0, 0x0820 },
4557 { 0x19, 0xffff, 0x7c00 },
4558 { 0x1e, 0xffff, 0x20eb },
4559 { 0x0d, 0xffff, 0x1666 },
4560 { 0x00, 0xffff, 0x10a3 },
4561 { 0x06, 0xffff, 0xf050 },
4562 { 0x04, 0x0000, 0x0010 },
4563 { 0x1d, 0x4000, 0x0000 },
4566 rtl_hw_start_8168g(tp
);
4568 /* disable aspm and clock request before access ephy */
4569 RTL_W8(tp
, Config2
, RTL_R8(tp
, Config2
) & ~ClkReqEn
);
4570 RTL_W8(tp
, Config5
, RTL_R8(tp
, Config5
) & ~ASPM_en
);
4571 rtl_ephy_init(tp
, e_info_8168g_2
);
4574 static void rtl_hw_start_8411_2(struct rtl8169_private
*tp
)
4576 static const struct ephy_info e_info_8411_2
[] = {
4577 { 0x00, 0x0008, 0x0000 },
4578 { 0x0c, 0x37d0, 0x0820 },
4579 { 0x1e, 0x0000, 0x0001 },
4580 { 0x19, 0x8021, 0x0000 },
4581 { 0x1e, 0x0000, 0x2000 },
4582 { 0x0d, 0x0100, 0x0200 },
4583 { 0x00, 0x0000, 0x0080 },
4584 { 0x06, 0x0000, 0x0010 },
4585 { 0x04, 0x0000, 0x0010 },
4586 { 0x1d, 0x0000, 0x4000 },
4589 rtl_hw_start_8168g(tp
);
4591 /* disable aspm and clock request before access ephy */
4592 rtl_hw_aspm_clkreq_enable(tp
, false);
4593 rtl_ephy_init(tp
, e_info_8411_2
);
4595 /* The following Realtek-provided magic fixes an issue with the RX unit
4596 * getting confused after the PHY having been powered-down.
4598 r8168_mac_ocp_write(tp
, 0xFC28, 0x0000);
4599 r8168_mac_ocp_write(tp
, 0xFC2A, 0x0000);
4600 r8168_mac_ocp_write(tp
, 0xFC2C, 0x0000);
4601 r8168_mac_ocp_write(tp
, 0xFC2E, 0x0000);
4602 r8168_mac_ocp_write(tp
, 0xFC30, 0x0000);
4603 r8168_mac_ocp_write(tp
, 0xFC32, 0x0000);
4604 r8168_mac_ocp_write(tp
, 0xFC34, 0x0000);
4605 r8168_mac_ocp_write(tp
, 0xFC36, 0x0000);
4607 r8168_mac_ocp_write(tp
, 0xFC26, 0x0000);
4609 r8168_mac_ocp_write(tp
, 0xF800, 0xE008);
4610 r8168_mac_ocp_write(tp
, 0xF802, 0xE00A);
4611 r8168_mac_ocp_write(tp
, 0xF804, 0xE00C);
4612 r8168_mac_ocp_write(tp
, 0xF806, 0xE00E);
4613 r8168_mac_ocp_write(tp
, 0xF808, 0xE027);
4614 r8168_mac_ocp_write(tp
, 0xF80A, 0xE04F);
4615 r8168_mac_ocp_write(tp
, 0xF80C, 0xE05E);
4616 r8168_mac_ocp_write(tp
, 0xF80E, 0xE065);
4617 r8168_mac_ocp_write(tp
, 0xF810, 0xC602);
4618 r8168_mac_ocp_write(tp
, 0xF812, 0xBE00);
4619 r8168_mac_ocp_write(tp
, 0xF814, 0x0000);
4620 r8168_mac_ocp_write(tp
, 0xF816, 0xC502);
4621 r8168_mac_ocp_write(tp
, 0xF818, 0xBD00);
4622 r8168_mac_ocp_write(tp
, 0xF81A, 0x074C);
4623 r8168_mac_ocp_write(tp
, 0xF81C, 0xC302);
4624 r8168_mac_ocp_write(tp
, 0xF81E, 0xBB00);
4625 r8168_mac_ocp_write(tp
, 0xF820, 0x080A);
4626 r8168_mac_ocp_write(tp
, 0xF822, 0x6420);
4627 r8168_mac_ocp_write(tp
, 0xF824, 0x48C2);
4628 r8168_mac_ocp_write(tp
, 0xF826, 0x8C20);
4629 r8168_mac_ocp_write(tp
, 0xF828, 0xC516);
4630 r8168_mac_ocp_write(tp
, 0xF82A, 0x64A4);
4631 r8168_mac_ocp_write(tp
, 0xF82C, 0x49C0);
4632 r8168_mac_ocp_write(tp
, 0xF82E, 0xF009);
4633 r8168_mac_ocp_write(tp
, 0xF830, 0x74A2);
4634 r8168_mac_ocp_write(tp
, 0xF832, 0x8CA5);
4635 r8168_mac_ocp_write(tp
, 0xF834, 0x74A0);
4636 r8168_mac_ocp_write(tp
, 0xF836, 0xC50E);
4637 r8168_mac_ocp_write(tp
, 0xF838, 0x9CA2);
4638 r8168_mac_ocp_write(tp
, 0xF83A, 0x1C11);
4639 r8168_mac_ocp_write(tp
, 0xF83C, 0x9CA0);
4640 r8168_mac_ocp_write(tp
, 0xF83E, 0xE006);
4641 r8168_mac_ocp_write(tp
, 0xF840, 0x74F8);
4642 r8168_mac_ocp_write(tp
, 0xF842, 0x48C4);
4643 r8168_mac_ocp_write(tp
, 0xF844, 0x8CF8);
4644 r8168_mac_ocp_write(tp
, 0xF846, 0xC404);
4645 r8168_mac_ocp_write(tp
, 0xF848, 0xBC00);
4646 r8168_mac_ocp_write(tp
, 0xF84A, 0xC403);
4647 r8168_mac_ocp_write(tp
, 0xF84C, 0xBC00);
4648 r8168_mac_ocp_write(tp
, 0xF84E, 0x0BF2);
4649 r8168_mac_ocp_write(tp
, 0xF850, 0x0C0A);
4650 r8168_mac_ocp_write(tp
, 0xF852, 0xE434);
4651 r8168_mac_ocp_write(tp
, 0xF854, 0xD3C0);
4652 r8168_mac_ocp_write(tp
, 0xF856, 0x49D9);
4653 r8168_mac_ocp_write(tp
, 0xF858, 0xF01F);
4654 r8168_mac_ocp_write(tp
, 0xF85A, 0xC526);
4655 r8168_mac_ocp_write(tp
, 0xF85C, 0x64A5);
4656 r8168_mac_ocp_write(tp
, 0xF85E, 0x1400);
4657 r8168_mac_ocp_write(tp
, 0xF860, 0xF007);
4658 r8168_mac_ocp_write(tp
, 0xF862, 0x0C01);
4659 r8168_mac_ocp_write(tp
, 0xF864, 0x8CA5);
4660 r8168_mac_ocp_write(tp
, 0xF866, 0x1C15);
4661 r8168_mac_ocp_write(tp
, 0xF868, 0xC51B);
4662 r8168_mac_ocp_write(tp
, 0xF86A, 0x9CA0);
4663 r8168_mac_ocp_write(tp
, 0xF86C, 0xE013);
4664 r8168_mac_ocp_write(tp
, 0xF86E, 0xC519);
4665 r8168_mac_ocp_write(tp
, 0xF870, 0x74A0);
4666 r8168_mac_ocp_write(tp
, 0xF872, 0x48C4);
4667 r8168_mac_ocp_write(tp
, 0xF874, 0x8CA0);
4668 r8168_mac_ocp_write(tp
, 0xF876, 0xC516);
4669 r8168_mac_ocp_write(tp
, 0xF878, 0x74A4);
4670 r8168_mac_ocp_write(tp
, 0xF87A, 0x48C8);
4671 r8168_mac_ocp_write(tp
, 0xF87C, 0x48CA);
4672 r8168_mac_ocp_write(tp
, 0xF87E, 0x9CA4);
4673 r8168_mac_ocp_write(tp
, 0xF880, 0xC512);
4674 r8168_mac_ocp_write(tp
, 0xF882, 0x1B00);
4675 r8168_mac_ocp_write(tp
, 0xF884, 0x9BA0);
4676 r8168_mac_ocp_write(tp
, 0xF886, 0x1B1C);
4677 r8168_mac_ocp_write(tp
, 0xF888, 0x483F);
4678 r8168_mac_ocp_write(tp
, 0xF88A, 0x9BA2);
4679 r8168_mac_ocp_write(tp
, 0xF88C, 0x1B04);
4680 r8168_mac_ocp_write(tp
, 0xF88E, 0xC508);
4681 r8168_mac_ocp_write(tp
, 0xF890, 0x9BA0);
4682 r8168_mac_ocp_write(tp
, 0xF892, 0xC505);
4683 r8168_mac_ocp_write(tp
, 0xF894, 0xBD00);
4684 r8168_mac_ocp_write(tp
, 0xF896, 0xC502);
4685 r8168_mac_ocp_write(tp
, 0xF898, 0xBD00);
4686 r8168_mac_ocp_write(tp
, 0xF89A, 0x0300);
4687 r8168_mac_ocp_write(tp
, 0xF89C, 0x051E);
4688 r8168_mac_ocp_write(tp
, 0xF89E, 0xE434);
4689 r8168_mac_ocp_write(tp
, 0xF8A0, 0xE018);
4690 r8168_mac_ocp_write(tp
, 0xF8A2, 0xE092);
4691 r8168_mac_ocp_write(tp
, 0xF8A4, 0xDE20);
4692 r8168_mac_ocp_write(tp
, 0xF8A6, 0xD3C0);
4693 r8168_mac_ocp_write(tp
, 0xF8A8, 0xC50F);
4694 r8168_mac_ocp_write(tp
, 0xF8AA, 0x76A4);
4695 r8168_mac_ocp_write(tp
, 0xF8AC, 0x49E3);
4696 r8168_mac_ocp_write(tp
, 0xF8AE, 0xF007);
4697 r8168_mac_ocp_write(tp
, 0xF8B0, 0x49C0);
4698 r8168_mac_ocp_write(tp
, 0xF8B2, 0xF103);
4699 r8168_mac_ocp_write(tp
, 0xF8B4, 0xC607);
4700 r8168_mac_ocp_write(tp
, 0xF8B6, 0xBE00);
4701 r8168_mac_ocp_write(tp
, 0xF8B8, 0xC606);
4702 r8168_mac_ocp_write(tp
, 0xF8BA, 0xBE00);
4703 r8168_mac_ocp_write(tp
, 0xF8BC, 0xC602);
4704 r8168_mac_ocp_write(tp
, 0xF8BE, 0xBE00);
4705 r8168_mac_ocp_write(tp
, 0xF8C0, 0x0C4C);
4706 r8168_mac_ocp_write(tp
, 0xF8C2, 0x0C28);
4707 r8168_mac_ocp_write(tp
, 0xF8C4, 0x0C2C);
4708 r8168_mac_ocp_write(tp
, 0xF8C6, 0xDC00);
4709 r8168_mac_ocp_write(tp
, 0xF8C8, 0xC707);
4710 r8168_mac_ocp_write(tp
, 0xF8CA, 0x1D00);
4711 r8168_mac_ocp_write(tp
, 0xF8CC, 0x8DE2);
4712 r8168_mac_ocp_write(tp
, 0xF8CE, 0x48C1);
4713 r8168_mac_ocp_write(tp
, 0xF8D0, 0xC502);
4714 r8168_mac_ocp_write(tp
, 0xF8D2, 0xBD00);
4715 r8168_mac_ocp_write(tp
, 0xF8D4, 0x00AA);
4716 r8168_mac_ocp_write(tp
, 0xF8D6, 0xE0C0);
4717 r8168_mac_ocp_write(tp
, 0xF8D8, 0xC502);
4718 r8168_mac_ocp_write(tp
, 0xF8DA, 0xBD00);
4719 r8168_mac_ocp_write(tp
, 0xF8DC, 0x0132);
4721 r8168_mac_ocp_write(tp
, 0xFC26, 0x8000);
4723 r8168_mac_ocp_write(tp
, 0xFC2A, 0x0743);
4724 r8168_mac_ocp_write(tp
, 0xFC2C, 0x0801);
4725 r8168_mac_ocp_write(tp
, 0xFC2E, 0x0BE9);
4726 r8168_mac_ocp_write(tp
, 0xFC30, 0x02FD);
4727 r8168_mac_ocp_write(tp
, 0xFC32, 0x0C25);
4728 r8168_mac_ocp_write(tp
, 0xFC34, 0x00A9);
4729 r8168_mac_ocp_write(tp
, 0xFC36, 0x012D);
4731 rtl_hw_aspm_clkreq_enable(tp
, true);
4734 static void rtl_hw_start_8168h_1(struct rtl8169_private
*tp
)
4736 static const struct ephy_info e_info_8168h_1
[] = {
4737 { 0x1e, 0x0800, 0x0001 },
4738 { 0x1d, 0x0000, 0x0800 },
4739 { 0x05, 0xffff, 0x2089 },
4740 { 0x06, 0xffff, 0x5881 },
4741 { 0x04, 0xffff, 0x854a },
4742 { 0x01, 0xffff, 0x068b }
4746 /* disable aspm and clock request before access ephy */
4747 rtl_hw_aspm_clkreq_enable(tp
, false);
4748 rtl_ephy_init(tp
, e_info_8168h_1
);
4750 rtl_set_fifo_size(tp
, 0x08, 0x10, 0x02, 0x06);
4751 rtl8168g_set_pause_thresholds(tp
, 0x38, 0x48);
4753 rtl_set_def_aspm_entry_latency(tp
);
4755 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
4757 rtl_reset_packet_filter(tp
);
4759 rtl_eri_set_bits(tp
, 0xdc, ERIAR_MASK_1111
, BIT(4));
4761 rtl_eri_set_bits(tp
, 0xd4, ERIAR_MASK_1111
, 0x1f00);
4763 rtl_eri_write(tp
, 0x5f0, ERIAR_MASK_0011
, 0x4f87);
4765 RTL_W32(tp
, MISC
, RTL_R32(tp
, MISC
) & ~RXDV_GATED_EN
);
4767 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000);
4768 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000);
4770 rtl8168_config_eee_mac(tp
);
4772 RTL_W8(tp
, DLLPR
, RTL_R8(tp
, DLLPR
) & ~PFM_EN
);
4773 RTL_W8(tp
, MISC_1
, RTL_R8(tp
, MISC_1
) & ~PFM_D3COLD_EN
);
4775 RTL_W8(tp
, DLLPR
, RTL_R8(tp
, DLLPR
) & ~TX_10M_PS_EN
);
4777 rtl_eri_clear_bits(tp
, 0x1b0, ERIAR_MASK_0011
, BIT(12));
4779 rtl_pcie_state_l2l3_disable(tp
);
4781 rtl_writephy(tp
, 0x1f, 0x0c42);
4782 rg_saw_cnt
= (rtl_readphy(tp
, 0x13) & 0x3fff);
4783 rtl_writephy(tp
, 0x1f, 0x0000);
4784 if (rg_saw_cnt
> 0) {
4787 sw_cnt_1ms_ini
= 16000000/rg_saw_cnt
;
4788 sw_cnt_1ms_ini
&= 0x0fff;
4789 r8168_mac_ocp_modify(tp
, 0xd412, 0x0fff, sw_cnt_1ms_ini
);
4792 r8168_mac_ocp_modify(tp
, 0xe056, 0x00f0, 0x0070);
4793 r8168_mac_ocp_modify(tp
, 0xe052, 0x6000, 0x8008);
4794 r8168_mac_ocp_modify(tp
, 0xe0d6, 0x01ff, 0x017f);
4795 r8168_mac_ocp_modify(tp
, 0xd420, 0x0fff, 0x047f);
4797 r8168_mac_ocp_write(tp
, 0xe63e, 0x0001);
4798 r8168_mac_ocp_write(tp
, 0xe63e, 0x0000);
4799 r8168_mac_ocp_write(tp
, 0xc094, 0x0000);
4800 r8168_mac_ocp_write(tp
, 0xc09e, 0x0000);
4802 rtl_hw_aspm_clkreq_enable(tp
, true);
4805 static void rtl_hw_start_8168ep(struct rtl8169_private
*tp
)
4807 rtl8168ep_stop_cmac(tp
);
4809 rtl_set_fifo_size(tp
, 0x08, 0x10, 0x02, 0x06);
4810 rtl8168g_set_pause_thresholds(tp
, 0x2f, 0x5f);
4812 rtl_set_def_aspm_entry_latency(tp
);
4814 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
4816 rtl_reset_packet_filter(tp
);
4818 rtl_eri_set_bits(tp
, 0xd4, ERIAR_MASK_1111
, 0x1f80);
4820 rtl_eri_write(tp
, 0x5f0, ERIAR_MASK_0011
, 0x4f87);
4822 RTL_W32(tp
, MISC
, RTL_R32(tp
, MISC
) & ~RXDV_GATED_EN
);
4824 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000);
4825 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000);
4827 rtl8168_config_eee_mac(tp
);
4829 rtl_w0w1_eri(tp
, 0x2fc, ERIAR_MASK_0001
, 0x01, 0x06);
4831 RTL_W8(tp
, DLLPR
, RTL_R8(tp
, DLLPR
) & ~TX_10M_PS_EN
);
4833 rtl_pcie_state_l2l3_disable(tp
);
4836 static void rtl_hw_start_8168ep_1(struct rtl8169_private
*tp
)
4838 static const struct ephy_info e_info_8168ep_1
[] = {
4839 { 0x00, 0xffff, 0x10ab },
4840 { 0x06, 0xffff, 0xf030 },
4841 { 0x08, 0xffff, 0x2006 },
4842 { 0x0d, 0xffff, 0x1666 },
4843 { 0x0c, 0x3ff0, 0x0000 }
4846 /* disable aspm and clock request before access ephy */
4847 rtl_hw_aspm_clkreq_enable(tp
, false);
4848 rtl_ephy_init(tp
, e_info_8168ep_1
);
4850 rtl_hw_start_8168ep(tp
);
4852 rtl_hw_aspm_clkreq_enable(tp
, true);
4855 static void rtl_hw_start_8168ep_2(struct rtl8169_private
*tp
)
4857 static const struct ephy_info e_info_8168ep_2
[] = {
4858 { 0x00, 0xffff, 0x10a3 },
4859 { 0x19, 0xffff, 0xfc00 },
4860 { 0x1e, 0xffff, 0x20ea }
4863 /* disable aspm and clock request before access ephy */
4864 rtl_hw_aspm_clkreq_enable(tp
, false);
4865 rtl_ephy_init(tp
, e_info_8168ep_2
);
4867 rtl_hw_start_8168ep(tp
);
4869 RTL_W8(tp
, DLLPR
, RTL_R8(tp
, DLLPR
) & ~PFM_EN
);
4870 RTL_W8(tp
, MISC_1
, RTL_R8(tp
, MISC_1
) & ~PFM_D3COLD_EN
);
4872 rtl_hw_aspm_clkreq_enable(tp
, true);
4875 static void rtl_hw_start_8168ep_3(struct rtl8169_private
*tp
)
4877 static const struct ephy_info e_info_8168ep_3
[] = {
4878 { 0x00, 0x0000, 0x0080 },
4879 { 0x0d, 0x0100, 0x0200 },
4880 { 0x19, 0x8021, 0x0000 },
4881 { 0x1e, 0x0000, 0x2000 },
4884 /* disable aspm and clock request before access ephy */
4885 rtl_hw_aspm_clkreq_enable(tp
, false);
4886 rtl_ephy_init(tp
, e_info_8168ep_3
);
4888 rtl_hw_start_8168ep(tp
);
4890 RTL_W8(tp
, DLLPR
, RTL_R8(tp
, DLLPR
) & ~PFM_EN
);
4891 RTL_W8(tp
, MISC_1
, RTL_R8(tp
, MISC_1
) & ~PFM_D3COLD_EN
);
4893 r8168_mac_ocp_modify(tp
, 0xd3e2, 0x0fff, 0x0271);
4894 r8168_mac_ocp_modify(tp
, 0xd3e4, 0x00ff, 0x0000);
4895 r8168_mac_ocp_modify(tp
, 0xe860, 0x0000, 0x0080);
4897 rtl_hw_aspm_clkreq_enable(tp
, true);
4900 static void rtl_hw_start_8102e_1(struct rtl8169_private
*tp
)
4902 static const struct ephy_info e_info_8102e_1
[] = {
4903 { 0x01, 0, 0x6e65 },
4904 { 0x02, 0, 0x091f },
4905 { 0x03, 0, 0xc2f9 },
4906 { 0x06, 0, 0xafb5 },
4907 { 0x07, 0, 0x0e00 },
4908 { 0x19, 0, 0xec80 },
4909 { 0x01, 0, 0x2e65 },
4914 rtl_set_def_aspm_entry_latency(tp
);
4916 RTL_W8(tp
, DBG_REG
, FIX_NAK_1
);
4918 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
4921 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
4922 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) & ~Beacon_en
);
4924 cfg1
= RTL_R8(tp
, Config1
);
4925 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
4926 RTL_W8(tp
, Config1
, cfg1
& ~LEDS0
);
4928 rtl_ephy_init(tp
, e_info_8102e_1
);
4931 static void rtl_hw_start_8102e_2(struct rtl8169_private
*tp
)
4933 rtl_set_def_aspm_entry_latency(tp
);
4935 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
4937 RTL_W8(tp
, Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
4938 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) & ~Beacon_en
);
4941 static void rtl_hw_start_8102e_3(struct rtl8169_private
*tp
)
4943 rtl_hw_start_8102e_2(tp
);
4945 rtl_ephy_write(tp
, 0x03, 0xc2f9);
4948 static void rtl_hw_start_8105e_1(struct rtl8169_private
*tp
)
4950 static const struct ephy_info e_info_8105e_1
[] = {
4951 { 0x07, 0, 0x4000 },
4952 { 0x19, 0, 0x0200 },
4953 { 0x19, 0, 0x0020 },
4954 { 0x1e, 0, 0x2000 },
4955 { 0x03, 0, 0x0001 },
4956 { 0x19, 0, 0x0100 },
4957 { 0x19, 0, 0x0004 },
4961 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4962 RTL_W32(tp
, FuncEvent
, RTL_R32(tp
, FuncEvent
) | 0x002800);
4964 /* Disable Early Tally Counter */
4965 RTL_W32(tp
, FuncEvent
, RTL_R32(tp
, FuncEvent
) & ~0x010000);
4967 RTL_W8(tp
, MCU
, RTL_R8(tp
, MCU
) | EN_NDP
| EN_OOB_RESET
);
4968 RTL_W8(tp
, DLLPR
, RTL_R8(tp
, DLLPR
) | PFM_EN
);
4970 rtl_ephy_init(tp
, e_info_8105e_1
);
4972 rtl_pcie_state_l2l3_disable(tp
);
4975 static void rtl_hw_start_8105e_2(struct rtl8169_private
*tp
)
4977 rtl_hw_start_8105e_1(tp
);
4978 rtl_ephy_write(tp
, 0x1e, rtl_ephy_read(tp
, 0x1e) | 0x8000);
4981 static void rtl_hw_start_8402(struct rtl8169_private
*tp
)
4983 static const struct ephy_info e_info_8402
[] = {
4984 { 0x19, 0xffff, 0xff64 },
4988 rtl_set_def_aspm_entry_latency(tp
);
4990 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4991 RTL_W32(tp
, FuncEvent
, RTL_R32(tp
, FuncEvent
) | 0x002800);
4993 RTL_W8(tp
, MCU
, RTL_R8(tp
, MCU
) & ~NOW_IS_OOB
);
4995 rtl_ephy_init(tp
, e_info_8402
);
4997 rtl_tx_performance_tweak(tp
, PCI_EXP_DEVCTL_READRQ_4096B
);
4999 rtl_set_fifo_size(tp
, 0x00, 0x00, 0x02, 0x06);
5000 rtl_reset_packet_filter(tp
);
5001 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000);
5002 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000);
5003 rtl_w0w1_eri(tp
, 0x0d4, ERIAR_MASK_0011
, 0x0e00, 0xff00);
5005 rtl_pcie_state_l2l3_disable(tp
);
5008 static void rtl_hw_start_8106(struct rtl8169_private
*tp
)
5010 rtl_hw_aspm_clkreq_enable(tp
, false);
5012 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5013 RTL_W32(tp
, FuncEvent
, RTL_R32(tp
, FuncEvent
) | 0x002800);
5015 RTL_W32(tp
, MISC
, (RTL_R32(tp
, MISC
) | DISABLE_LAN_EN
) & ~EARLY_TALLY_EN
);
5016 RTL_W8(tp
, MCU
, RTL_R8(tp
, MCU
) | EN_NDP
| EN_OOB_RESET
);
5017 RTL_W8(tp
, DLLPR
, RTL_R8(tp
, DLLPR
) & ~PFM_EN
);
5019 rtl_pcie_state_l2l3_disable(tp
);
5020 rtl_hw_aspm_clkreq_enable(tp
, true);
5023 static void rtl_hw_config(struct rtl8169_private
*tp
)
5025 static const rtl_generic_fct hw_configs
[] = {
5026 [RTL_GIGA_MAC_VER_07
] = rtl_hw_start_8102e_1
,
5027 [RTL_GIGA_MAC_VER_08
] = rtl_hw_start_8102e_3
,
5028 [RTL_GIGA_MAC_VER_09
] = rtl_hw_start_8102e_2
,
5029 [RTL_GIGA_MAC_VER_10
] = NULL
,
5030 [RTL_GIGA_MAC_VER_11
] = rtl_hw_start_8168bb
,
5031 [RTL_GIGA_MAC_VER_12
] = rtl_hw_start_8168bef
,
5032 [RTL_GIGA_MAC_VER_13
] = NULL
,
5033 [RTL_GIGA_MAC_VER_14
] = NULL
,
5034 [RTL_GIGA_MAC_VER_15
] = NULL
,
5035 [RTL_GIGA_MAC_VER_16
] = NULL
,
5036 [RTL_GIGA_MAC_VER_17
] = rtl_hw_start_8168bef
,
5037 [RTL_GIGA_MAC_VER_18
] = rtl_hw_start_8168cp_1
,
5038 [RTL_GIGA_MAC_VER_19
] = rtl_hw_start_8168c_1
,
5039 [RTL_GIGA_MAC_VER_20
] = rtl_hw_start_8168c_2
,
5040 [RTL_GIGA_MAC_VER_21
] = rtl_hw_start_8168c_3
,
5041 [RTL_GIGA_MAC_VER_22
] = rtl_hw_start_8168c_4
,
5042 [RTL_GIGA_MAC_VER_23
] = rtl_hw_start_8168cp_2
,
5043 [RTL_GIGA_MAC_VER_24
] = rtl_hw_start_8168cp_3
,
5044 [RTL_GIGA_MAC_VER_25
] = rtl_hw_start_8168d
,
5045 [RTL_GIGA_MAC_VER_26
] = rtl_hw_start_8168d
,
5046 [RTL_GIGA_MAC_VER_27
] = rtl_hw_start_8168d
,
5047 [RTL_GIGA_MAC_VER_28
] = rtl_hw_start_8168d_4
,
5048 [RTL_GIGA_MAC_VER_29
] = rtl_hw_start_8105e_1
,
5049 [RTL_GIGA_MAC_VER_30
] = rtl_hw_start_8105e_2
,
5050 [RTL_GIGA_MAC_VER_31
] = rtl_hw_start_8168dp
,
5051 [RTL_GIGA_MAC_VER_32
] = rtl_hw_start_8168e_1
,
5052 [RTL_GIGA_MAC_VER_33
] = rtl_hw_start_8168e_1
,
5053 [RTL_GIGA_MAC_VER_34
] = rtl_hw_start_8168e_2
,
5054 [RTL_GIGA_MAC_VER_35
] = rtl_hw_start_8168f_1
,
5055 [RTL_GIGA_MAC_VER_36
] = rtl_hw_start_8168f_1
,
5056 [RTL_GIGA_MAC_VER_37
] = rtl_hw_start_8402
,
5057 [RTL_GIGA_MAC_VER_38
] = rtl_hw_start_8411
,
5058 [RTL_GIGA_MAC_VER_39
] = rtl_hw_start_8106
,
5059 [RTL_GIGA_MAC_VER_40
] = rtl_hw_start_8168g_1
,
5060 [RTL_GIGA_MAC_VER_41
] = rtl_hw_start_8168g_1
,
5061 [RTL_GIGA_MAC_VER_42
] = rtl_hw_start_8168g_2
,
5062 [RTL_GIGA_MAC_VER_43
] = rtl_hw_start_8168g_2
,
5063 [RTL_GIGA_MAC_VER_44
] = rtl_hw_start_8411_2
,
5064 [RTL_GIGA_MAC_VER_45
] = rtl_hw_start_8168h_1
,
5065 [RTL_GIGA_MAC_VER_46
] = rtl_hw_start_8168h_1
,
5066 [RTL_GIGA_MAC_VER_47
] = rtl_hw_start_8168h_1
,
5067 [RTL_GIGA_MAC_VER_48
] = rtl_hw_start_8168h_1
,
5068 [RTL_GIGA_MAC_VER_49
] = rtl_hw_start_8168ep_1
,
5069 [RTL_GIGA_MAC_VER_50
] = rtl_hw_start_8168ep_2
,
5070 [RTL_GIGA_MAC_VER_51
] = rtl_hw_start_8168ep_3
,
5073 if (hw_configs
[tp
->mac_version
])
5074 hw_configs
[tp
->mac_version
](tp
);
5077 static void rtl_hw_start_8168(struct rtl8169_private
*tp
)
5079 if (tp
->mac_version
== RTL_GIGA_MAC_VER_13
||
5080 tp
->mac_version
== RTL_GIGA_MAC_VER_16
)
5081 pcie_capability_set_word(tp
->pci_dev
, PCI_EXP_DEVCTL
,
5082 PCI_EXP_DEVCTL_NOSNOOP_EN
);
5084 if (rtl_is_8168evl_up(tp
))
5085 RTL_W8(tp
, MaxTxPacketSize
, EarlySize
);
5087 RTL_W8(tp
, MaxTxPacketSize
, TxPacketMax
);
5091 /* disable interrupt coalescing */
5092 RTL_W16(tp
, IntrMitigate
, 0x0000);
5095 static void rtl_hw_start_8169(struct rtl8169_private
*tp
)
5097 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
5098 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
5100 RTL_W8(tp
, EarlyTxThres
, NoEarlyTx
);
5102 tp
->cp_cmd
|= PCIMulRW
;
5104 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
5105 tp
->mac_version
== RTL_GIGA_MAC_VER_03
) {
5106 netif_dbg(tp
, drv
, tp
->dev
,
5107 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
5108 tp
->cp_cmd
|= (1 << 14);
5111 RTL_W16(tp
, CPlusCmd
, tp
->cp_cmd
);
5113 rtl8169_set_magic_reg(tp
, tp
->mac_version
);
5115 RTL_W32(tp
, RxMissed
, 0);
5117 /* disable interrupt coalescing */
5118 RTL_W16(tp
, IntrMitigate
, 0x0000);
5121 static void rtl_hw_start(struct rtl8169_private
*tp
)
5123 rtl_unlock_config_regs(tp
);
5125 tp
->cp_cmd
&= CPCMD_MASK
;
5126 RTL_W16(tp
, CPlusCmd
, tp
->cp_cmd
);
5128 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
5129 rtl_hw_start_8169(tp
);
5131 rtl_hw_start_8168(tp
);
5133 rtl_set_rx_max_size(tp
);
5134 rtl_set_rx_tx_desc_registers(tp
);
5135 rtl_lock_config_regs(tp
);
5137 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5138 RTL_R16(tp
, CPlusCmd
);
5139 RTL_W8(tp
, ChipCmd
, CmdTxEnb
| CmdRxEnb
);
5141 rtl_set_tx_config_registers(tp
);
5142 rtl_set_rx_mode(tp
->dev
);
5146 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
5148 struct rtl8169_private
*tp
= netdev_priv(dev
);
5150 if (new_mtu
> ETH_DATA_LEN
)
5151 rtl_hw_jumbo_enable(tp
);
5153 rtl_hw_jumbo_disable(tp
);
5156 netdev_update_features(dev
);
5161 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
5163 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
5164 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
5167 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
)
5169 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
5171 /* Force memory writes to complete before releasing descriptor */
5174 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| R8169_RX_BUF_SIZE
);
5177 static struct page
*rtl8169_alloc_rx_data(struct rtl8169_private
*tp
,
5178 struct RxDesc
*desc
)
5180 struct device
*d
= tp_to_dev(tp
);
5181 int node
= dev_to_node(d
);
5185 data
= alloc_pages_node(node
, GFP_KERNEL
, get_order(R8169_RX_BUF_SIZE
));
5189 mapping
= dma_map_page(d
, data
, 0, R8169_RX_BUF_SIZE
, DMA_FROM_DEVICE
);
5190 if (unlikely(dma_mapping_error(d
, mapping
))) {
5191 if (net_ratelimit())
5192 netif_err(tp
, drv
, tp
->dev
, "Failed to map RX DMA!\n");
5193 __free_pages(data
, get_order(R8169_RX_BUF_SIZE
));
5197 desc
->addr
= cpu_to_le64(mapping
);
5198 rtl8169_mark_to_asic(desc
);
5203 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
5207 for (i
= 0; i
< NUM_RX_DESC
&& tp
->Rx_databuff
[i
]; i
++) {
5208 dma_unmap_page(tp_to_dev(tp
),
5209 le64_to_cpu(tp
->RxDescArray
[i
].addr
),
5210 R8169_RX_BUF_SIZE
, DMA_FROM_DEVICE
);
5211 __free_pages(tp
->Rx_databuff
[i
], get_order(R8169_RX_BUF_SIZE
));
5212 tp
->Rx_databuff
[i
] = NULL
;
5213 rtl8169_make_unusable_by_asic(tp
->RxDescArray
+ i
);
5217 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
5219 desc
->opts1
|= cpu_to_le32(RingEnd
);
5222 static int rtl8169_rx_fill(struct rtl8169_private
*tp
)
5226 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
5229 data
= rtl8169_alloc_rx_data(tp
, tp
->RxDescArray
+ i
);
5231 rtl8169_make_unusable_by_asic(tp
->RxDescArray
+ i
);
5234 tp
->Rx_databuff
[i
] = data
;
5237 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
5241 rtl8169_rx_clear(tp
);
5245 static int rtl8169_init_ring(struct rtl8169_private
*tp
)
5247 rtl8169_init_ring_indexes(tp
);
5249 memset(tp
->tx_skb
, 0, sizeof(tp
->tx_skb
));
5250 memset(tp
->Rx_databuff
, 0, sizeof(tp
->Rx_databuff
));
5252 return rtl8169_rx_fill(tp
);
5255 static void rtl8169_unmap_tx_skb(struct device
*d
, struct ring_info
*tx_skb
,
5256 struct TxDesc
*desc
)
5258 unsigned int len
= tx_skb
->len
;
5260 dma_unmap_single(d
, le64_to_cpu(desc
->addr
), len
, DMA_TO_DEVICE
);
5268 static void rtl8169_tx_clear_range(struct rtl8169_private
*tp
, u32 start
,
5273 for (i
= 0; i
< n
; i
++) {
5274 unsigned int entry
= (start
+ i
) % NUM_TX_DESC
;
5275 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
5276 unsigned int len
= tx_skb
->len
;
5279 struct sk_buff
*skb
= tx_skb
->skb
;
5281 rtl8169_unmap_tx_skb(tp_to_dev(tp
), tx_skb
,
5282 tp
->TxDescArray
+ entry
);
5284 dev_consume_skb_any(skb
);
5291 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
5293 rtl8169_tx_clear_range(tp
, tp
->dirty_tx
, NUM_TX_DESC
);
5294 tp
->cur_tx
= tp
->dirty_tx
= 0;
5295 netdev_reset_queue(tp
->dev
);
5298 static void rtl_reset_work(struct rtl8169_private
*tp
)
5300 struct net_device
*dev
= tp
->dev
;
5303 napi_disable(&tp
->napi
);
5304 netif_stop_queue(dev
);
5307 rtl8169_hw_reset(tp
);
5309 for (i
= 0; i
< NUM_RX_DESC
; i
++)
5310 rtl8169_mark_to_asic(tp
->RxDescArray
+ i
);
5312 rtl8169_tx_clear(tp
);
5313 rtl8169_init_ring_indexes(tp
);
5315 napi_enable(&tp
->napi
);
5317 netif_wake_queue(dev
);
5320 static void rtl8169_tx_timeout(struct net_device
*dev
)
5322 struct rtl8169_private
*tp
= netdev_priv(dev
);
5324 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
5327 static __le32
rtl8169_get_txd_opts1(u32 opts0
, u32 len
, unsigned int entry
)
5329 u32 status
= opts0
| len
;
5331 if (entry
== NUM_TX_DESC
- 1)
5334 return cpu_to_le32(status
);
5337 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
5340 struct skb_shared_info
*info
= skb_shinfo(skb
);
5341 unsigned int cur_frag
, entry
;
5342 struct TxDesc
*uninitialized_var(txd
);
5343 struct device
*d
= tp_to_dev(tp
);
5346 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
5347 const skb_frag_t
*frag
= info
->frags
+ cur_frag
;
5352 entry
= (entry
+ 1) % NUM_TX_DESC
;
5354 txd
= tp
->TxDescArray
+ entry
;
5355 len
= skb_frag_size(frag
);
5356 addr
= skb_frag_address(frag
);
5357 mapping
= dma_map_single(d
, addr
, len
, DMA_TO_DEVICE
);
5358 if (unlikely(dma_mapping_error(d
, mapping
))) {
5359 if (net_ratelimit())
5360 netif_err(tp
, drv
, tp
->dev
,
5361 "Failed to map TX fragments DMA!\n");
5365 txd
->opts1
= rtl8169_get_txd_opts1(opts
[0], len
, entry
);
5366 txd
->opts2
= cpu_to_le32(opts
[1]);
5367 txd
->addr
= cpu_to_le64(mapping
);
5369 tp
->tx_skb
[entry
].len
= len
;
5373 tp
->tx_skb
[entry
].skb
= skb
;
5374 txd
->opts1
|= cpu_to_le32(LastFrag
);
5380 rtl8169_tx_clear_range(tp
, tp
->cur_tx
+ 1, cur_frag
);
5384 static bool rtl_test_hw_pad_bug(struct rtl8169_private
*tp
, struct sk_buff
*skb
)
5386 return skb
->len
< ETH_ZLEN
&& tp
->mac_version
== RTL_GIGA_MAC_VER_34
;
5389 /* msdn_giant_send_check()
5390 * According to the document of microsoft, the TCP Pseudo Header excludes the
5391 * packet length for IPv6 TCP large packets.
5393 static int msdn_giant_send_check(struct sk_buff
*skb
)
5395 const struct ipv6hdr
*ipv6h
;
5399 ret
= skb_cow_head(skb
, 0);
5403 ipv6h
= ipv6_hdr(skb
);
5407 th
->check
= ~tcp_v6_check(0, &ipv6h
->saddr
, &ipv6h
->daddr
, 0);
5412 static void rtl8169_tso_csum_v1(struct sk_buff
*skb
, u32
*opts
)
5414 u32 mss
= skb_shinfo(skb
)->gso_size
;
5418 opts
[0] |= min(mss
, TD_MSS_MAX
) << TD0_MSS_SHIFT
;
5419 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5420 const struct iphdr
*ip
= ip_hdr(skb
);
5422 if (ip
->protocol
== IPPROTO_TCP
)
5423 opts
[0] |= TD0_IP_CS
| TD0_TCP_CS
;
5424 else if (ip
->protocol
== IPPROTO_UDP
)
5425 opts
[0] |= TD0_IP_CS
| TD0_UDP_CS
;
5431 static bool rtl8169_tso_csum_v2(struct rtl8169_private
*tp
,
5432 struct sk_buff
*skb
, u32
*opts
)
5434 u32 transport_offset
= (u32
)skb_transport_offset(skb
);
5435 u32 mss
= skb_shinfo(skb
)->gso_size
;
5438 switch (vlan_get_protocol(skb
)) {
5439 case htons(ETH_P_IP
):
5440 opts
[0] |= TD1_GTSENV4
;
5443 case htons(ETH_P_IPV6
):
5444 if (msdn_giant_send_check(skb
))
5447 opts
[0] |= TD1_GTSENV6
;
5455 opts
[0] |= transport_offset
<< GTTCPHO_SHIFT
;
5456 opts
[1] |= min(mss
, TD_MSS_MAX
) << TD1_MSS_SHIFT
;
5457 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5460 switch (vlan_get_protocol(skb
)) {
5461 case htons(ETH_P_IP
):
5462 opts
[1] |= TD1_IPv4_CS
;
5463 ip_protocol
= ip_hdr(skb
)->protocol
;
5466 case htons(ETH_P_IPV6
):
5467 opts
[1] |= TD1_IPv6_CS
;
5468 ip_protocol
= ipv6_hdr(skb
)->nexthdr
;
5472 ip_protocol
= IPPROTO_RAW
;
5476 if (ip_protocol
== IPPROTO_TCP
)
5477 opts
[1] |= TD1_TCP_CS
;
5478 else if (ip_protocol
== IPPROTO_UDP
)
5479 opts
[1] |= TD1_UDP_CS
;
5483 opts
[1] |= transport_offset
<< TCPHO_SHIFT
;
5485 if (unlikely(rtl_test_hw_pad_bug(tp
, skb
)))
5486 return !eth_skb_pad(skb
);
5492 static bool rtl_tx_slots_avail(struct rtl8169_private
*tp
,
5493 unsigned int nr_frags
)
5495 unsigned int slots_avail
= tp
->dirty_tx
+ NUM_TX_DESC
- tp
->cur_tx
;
5497 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
5498 return slots_avail
> nr_frags
;
5501 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
5502 static bool rtl_chip_supports_csum_v2(struct rtl8169_private
*tp
)
5504 switch (tp
->mac_version
) {
5505 case RTL_GIGA_MAC_VER_02
... RTL_GIGA_MAC_VER_06
:
5506 case RTL_GIGA_MAC_VER_10
... RTL_GIGA_MAC_VER_17
:
5513 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
5514 struct net_device
*dev
)
5516 struct rtl8169_private
*tp
= netdev_priv(dev
);
5517 unsigned int entry
= tp
->cur_tx
% NUM_TX_DESC
;
5518 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
5519 struct device
*d
= tp_to_dev(tp
);
5526 if (unlikely(!rtl_tx_slots_avail(tp
, skb_shinfo(skb
)->nr_frags
))) {
5527 netif_err(tp
, drv
, dev
, "BUG! Tx Ring full when queue awake!\n");
5531 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
5534 opts
[1] = rtl8169_tx_vlan_tag(skb
);
5537 if (rtl_chip_supports_csum_v2(tp
)) {
5538 if (!rtl8169_tso_csum_v2(tp
, skb
, opts
))
5541 rtl8169_tso_csum_v1(skb
, opts
);
5544 len
= skb_headlen(skb
);
5545 mapping
= dma_map_single(d
, skb
->data
, len
, DMA_TO_DEVICE
);
5546 if (unlikely(dma_mapping_error(d
, mapping
))) {
5547 if (net_ratelimit())
5548 netif_err(tp
, drv
, dev
, "Failed to map TX DMA!\n");
5552 tp
->tx_skb
[entry
].len
= len
;
5553 txd
->addr
= cpu_to_le64(mapping
);
5555 frags
= rtl8169_xmit_frags(tp
, skb
, opts
);
5559 opts
[0] |= FirstFrag
;
5561 opts
[0] |= FirstFrag
| LastFrag
;
5562 tp
->tx_skb
[entry
].skb
= skb
;
5565 txd
->opts2
= cpu_to_le32(opts
[1]);
5567 skb_tx_timestamp(skb
);
5569 /* Force memory writes to complete before releasing descriptor */
5572 door_bell
= __netdev_sent_queue(dev
, skb
->len
, netdev_xmit_more());
5574 txd
->opts1
= rtl8169_get_txd_opts1(opts
[0], len
, entry
);
5576 /* Force all memory writes to complete before notifying device */
5579 tp
->cur_tx
+= frags
+ 1;
5581 stop_queue
= !rtl_tx_slots_avail(tp
, MAX_SKB_FRAGS
);
5582 if (unlikely(stop_queue
)) {
5583 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5584 * not miss a ring update when it notices a stopped queue.
5587 netif_stop_queue(dev
);
5592 RTL_W8(tp
, TxPoll
, NPQ
);
5594 if (unlikely(stop_queue
)) {
5595 /* Sync with rtl_tx:
5596 * - publish queue status and cur_tx ring index (write barrier)
5597 * - refresh dirty_tx ring index (read barrier).
5598 * May the current thread have a pessimistic view of the ring
5599 * status and forget to wake up queue, a racing rtl_tx thread
5603 if (rtl_tx_slots_avail(tp
, MAX_SKB_FRAGS
))
5604 netif_start_queue(dev
);
5607 return NETDEV_TX_OK
;
5610 rtl8169_unmap_tx_skb(d
, tp
->tx_skb
+ entry
, txd
);
5612 dev_kfree_skb_any(skb
);
5613 dev
->stats
.tx_dropped
++;
5614 return NETDEV_TX_OK
;
5617 netif_stop_queue(dev
);
5618 dev
->stats
.tx_dropped
++;
5619 return NETDEV_TX_BUSY
;
5622 static netdev_features_t
rtl8169_features_check(struct sk_buff
*skb
,
5623 struct net_device
*dev
,
5624 netdev_features_t features
)
5626 int transport_offset
= skb_transport_offset(skb
);
5627 struct rtl8169_private
*tp
= netdev_priv(dev
);
5629 if (skb_is_gso(skb
)) {
5630 if (transport_offset
> GTTCPHO_MAX
&&
5631 rtl_chip_supports_csum_v2(tp
))
5632 features
&= ~NETIF_F_ALL_TSO
;
5633 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5634 if (skb
->len
< ETH_ZLEN
) {
5635 switch (tp
->mac_version
) {
5636 case RTL_GIGA_MAC_VER_11
:
5637 case RTL_GIGA_MAC_VER_12
:
5638 case RTL_GIGA_MAC_VER_17
:
5639 case RTL_GIGA_MAC_VER_34
:
5640 features
&= ~NETIF_F_CSUM_MASK
;
5647 if (transport_offset
> TCPHO_MAX
&&
5648 rtl_chip_supports_csum_v2(tp
))
5649 features
&= ~NETIF_F_CSUM_MASK
;
5652 return vlan_features_check(skb
, features
);
5655 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
5657 struct rtl8169_private
*tp
= netdev_priv(dev
);
5658 struct pci_dev
*pdev
= tp
->pci_dev
;
5659 u16 pci_status
, pci_cmd
;
5661 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
5662 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
5664 netif_err(tp
, intr
, dev
, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5665 pci_cmd
, pci_status
);
5668 * The recovery sequence below admits a very elaborated explanation:
5669 * - it seems to work;
5670 * - I did not see what else could be done;
5671 * - it makes iop3xx happy.
5673 * Feel free to adjust to your needs.
5675 if (pdev
->broken_parity_status
)
5676 pci_cmd
&= ~PCI_COMMAND_PARITY
;
5678 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
5680 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
5682 pci_write_config_word(pdev
, PCI_STATUS
,
5683 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
5684 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
5685 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
5687 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
5690 static void rtl_tx(struct net_device
*dev
, struct rtl8169_private
*tp
,
5693 unsigned int dirty_tx
, tx_left
, bytes_compl
= 0, pkts_compl
= 0;
5695 dirty_tx
= tp
->dirty_tx
;
5697 tx_left
= tp
->cur_tx
- dirty_tx
;
5699 while (tx_left
> 0) {
5700 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
5701 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
5704 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
5705 if (status
& DescOwn
)
5708 /* This barrier is needed to keep us from reading
5709 * any other fields out of the Tx descriptor until
5710 * we know the status of DescOwn
5714 rtl8169_unmap_tx_skb(tp_to_dev(tp
), tx_skb
,
5715 tp
->TxDescArray
+ entry
);
5716 if (status
& LastFrag
) {
5718 bytes_compl
+= tx_skb
->skb
->len
;
5719 napi_consume_skb(tx_skb
->skb
, budget
);
5726 if (tp
->dirty_tx
!= dirty_tx
) {
5727 netdev_completed_queue(dev
, pkts_compl
, bytes_compl
);
5729 u64_stats_update_begin(&tp
->tx_stats
.syncp
);
5730 tp
->tx_stats
.packets
+= pkts_compl
;
5731 tp
->tx_stats
.bytes
+= bytes_compl
;
5732 u64_stats_update_end(&tp
->tx_stats
.syncp
);
5734 tp
->dirty_tx
= dirty_tx
;
5735 /* Sync with rtl8169_start_xmit:
5736 * - publish dirty_tx ring index (write barrier)
5737 * - refresh cur_tx ring index and queue status (read barrier)
5738 * May the current thread miss the stopped queue condition,
5739 * a racing xmit thread can only have a right view of the
5743 if (netif_queue_stopped(dev
) &&
5744 rtl_tx_slots_avail(tp
, MAX_SKB_FRAGS
)) {
5745 netif_wake_queue(dev
);
5748 * 8168 hack: TxPoll requests are lost when the Tx packets are
5749 * too close. Let's kick an extra TxPoll request when a burst
5750 * of start_xmit activity is detected (if it is not detected,
5751 * it is slow enough). -- FR
5753 if (tp
->cur_tx
!= dirty_tx
)
5754 RTL_W8(tp
, TxPoll
, NPQ
);
5758 static inline int rtl8169_fragmented_frame(u32 status
)
5760 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
5763 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, u32 opts1
)
5765 u32 status
= opts1
& RxProtoMask
;
5767 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
5768 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)))
5769 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
5771 skb_checksum_none_assert(skb
);
5774 static int rtl_rx(struct net_device
*dev
, struct rtl8169_private
*tp
, u32 budget
)
5776 unsigned int cur_rx
, rx_left
;
5779 cur_rx
= tp
->cur_rx
;
5781 for (rx_left
= min(budget
, NUM_RX_DESC
); rx_left
> 0; rx_left
--, cur_rx
++) {
5782 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
5783 const void *rx_buf
= page_address(tp
->Rx_databuff
[entry
]);
5784 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
5787 status
= le32_to_cpu(desc
->opts1
);
5788 if (status
& DescOwn
)
5791 /* This barrier is needed to keep us from reading
5792 * any other fields out of the Rx descriptor until
5793 * we know the status of DescOwn
5797 if (unlikely(status
& RxRES
)) {
5798 netif_info(tp
, rx_err
, dev
, "Rx ERROR. status = %08x\n",
5800 dev
->stats
.rx_errors
++;
5801 if (status
& (RxRWT
| RxRUNT
))
5802 dev
->stats
.rx_length_errors
++;
5804 dev
->stats
.rx_crc_errors
++;
5805 if (status
& (RxRUNT
| RxCRC
) && !(status
& RxRWT
) &&
5806 dev
->features
& NETIF_F_RXALL
) {
5810 unsigned int pkt_size
;
5811 struct sk_buff
*skb
;
5814 pkt_size
= status
& GENMASK(13, 0);
5815 if (likely(!(dev
->features
& NETIF_F_RXFCS
)))
5816 pkt_size
-= ETH_FCS_LEN
;
5818 * The driver does not support incoming fragmented
5819 * frames. They are seen as a symptom of over-mtu
5822 if (unlikely(rtl8169_fragmented_frame(status
))) {
5823 dev
->stats
.rx_dropped
++;
5824 dev
->stats
.rx_length_errors
++;
5825 goto release_descriptor
;
5828 skb
= napi_alloc_skb(&tp
->napi
, pkt_size
);
5829 if (unlikely(!skb
)) {
5830 dev
->stats
.rx_dropped
++;
5831 goto release_descriptor
;
5834 dma_sync_single_for_cpu(tp_to_dev(tp
),
5835 le64_to_cpu(desc
->addr
),
5836 pkt_size
, DMA_FROM_DEVICE
);
5838 skb_copy_to_linear_data(skb
, rx_buf
, pkt_size
);
5839 skb
->tail
+= pkt_size
;
5840 skb
->len
= pkt_size
;
5842 dma_sync_single_for_device(tp_to_dev(tp
),
5843 le64_to_cpu(desc
->addr
),
5844 pkt_size
, DMA_FROM_DEVICE
);
5846 rtl8169_rx_csum(skb
, status
);
5847 skb
->protocol
= eth_type_trans(skb
, dev
);
5849 rtl8169_rx_vlan_tag(desc
, skb
);
5851 if (skb
->pkt_type
== PACKET_MULTICAST
)
5852 dev
->stats
.multicast
++;
5854 napi_gro_receive(&tp
->napi
, skb
);
5856 u64_stats_update_begin(&tp
->rx_stats
.syncp
);
5857 tp
->rx_stats
.packets
++;
5858 tp
->rx_stats
.bytes
+= pkt_size
;
5859 u64_stats_update_end(&tp
->rx_stats
.syncp
);
5863 rtl8169_mark_to_asic(desc
);
5866 count
= cur_rx
- tp
->cur_rx
;
5867 tp
->cur_rx
= cur_rx
;
5872 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
5874 struct rtl8169_private
*tp
= dev_instance
;
5875 u32 status
= rtl_get_events(tp
);
5877 if (!tp
->irq_enabled
|| (status
& 0xffff) == 0xffff ||
5878 !(status
& tp
->irq_mask
))
5881 if (unlikely(status
& SYSErr
)) {
5882 rtl8169_pcierr_interrupt(tp
->dev
);
5886 if (status
& LinkChg
)
5887 phy_mac_interrupt(tp
->phydev
);
5889 if (unlikely(status
& RxFIFOOver
&&
5890 tp
->mac_version
== RTL_GIGA_MAC_VER_11
)) {
5891 netif_stop_queue(tp
->dev
);
5892 /* XXX - Hack alert. See rtl_task(). */
5893 set_bit(RTL_FLAG_TASK_RESET_PENDING
, tp
->wk
.flags
);
5896 rtl_irq_disable(tp
);
5897 napi_schedule_irqoff(&tp
->napi
);
5899 rtl_ack_events(tp
, status
);
5904 static void rtl_task(struct work_struct
*work
)
5906 static const struct {
5908 void (*action
)(struct rtl8169_private
*);
5910 { RTL_FLAG_TASK_RESET_PENDING
, rtl_reset_work
},
5912 struct rtl8169_private
*tp
=
5913 container_of(work
, struct rtl8169_private
, wk
.work
);
5914 struct net_device
*dev
= tp
->dev
;
5919 if (!netif_running(dev
) ||
5920 !test_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
))
5923 for (i
= 0; i
< ARRAY_SIZE(rtl_work
); i
++) {
5926 pending
= test_and_clear_bit(rtl_work
[i
].bitnr
, tp
->wk
.flags
);
5928 rtl_work
[i
].action(tp
);
5932 rtl_unlock_work(tp
);
5935 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
5937 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
5938 struct net_device
*dev
= tp
->dev
;
5941 work_done
= rtl_rx(dev
, tp
, (u32
) budget
);
5943 rtl_tx(dev
, tp
, budget
);
5945 if (work_done
< budget
) {
5946 napi_complete_done(napi
, work_done
);
5953 static void rtl8169_rx_missed(struct net_device
*dev
)
5955 struct rtl8169_private
*tp
= netdev_priv(dev
);
5957 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
5960 dev
->stats
.rx_missed_errors
+= RTL_R32(tp
, RxMissed
) & 0xffffff;
5961 RTL_W32(tp
, RxMissed
, 0);
5964 static void r8169_phylink_handler(struct net_device
*ndev
)
5966 struct rtl8169_private
*tp
= netdev_priv(ndev
);
5968 if (netif_carrier_ok(ndev
)) {
5969 rtl_link_chg_patch(tp
);
5970 pm_request_resume(&tp
->pci_dev
->dev
);
5972 pm_runtime_idle(&tp
->pci_dev
->dev
);
5975 if (net_ratelimit())
5976 phy_print_status(tp
->phydev
);
5979 static int r8169_phy_connect(struct rtl8169_private
*tp
)
5981 struct phy_device
*phydev
= tp
->phydev
;
5982 phy_interface_t phy_mode
;
5985 phy_mode
= tp
->supports_gmii
? PHY_INTERFACE_MODE_GMII
:
5986 PHY_INTERFACE_MODE_MII
;
5988 ret
= phy_connect_direct(tp
->dev
, phydev
, r8169_phylink_handler
,
5993 if (!tp
->supports_gmii
)
5994 phy_set_max_speed(phydev
, SPEED_100
);
5996 phy_support_asym_pause(phydev
);
5998 phy_attached_info(phydev
);
6003 static void rtl8169_down(struct net_device
*dev
)
6005 struct rtl8169_private
*tp
= netdev_priv(dev
);
6007 phy_stop(tp
->phydev
);
6009 napi_disable(&tp
->napi
);
6010 netif_stop_queue(dev
);
6012 rtl8169_hw_reset(tp
);
6014 * At this point device interrupts can not be enabled in any function,
6015 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6016 * and napi is disabled (rtl8169_poll).
6018 rtl8169_rx_missed(dev
);
6020 /* Give a racing hard_start_xmit a few cycles to complete. */
6023 rtl8169_tx_clear(tp
);
6025 rtl8169_rx_clear(tp
);
6027 rtl_pll_power_down(tp
);
6030 static int rtl8169_close(struct net_device
*dev
)
6032 struct rtl8169_private
*tp
= netdev_priv(dev
);
6033 struct pci_dev
*pdev
= tp
->pci_dev
;
6035 pm_runtime_get_sync(&pdev
->dev
);
6037 /* Update counters before going down */
6038 rtl8169_update_counters(tp
);
6041 /* Clear all task flags */
6042 bitmap_zero(tp
->wk
.flags
, RTL_FLAG_MAX
);
6045 rtl_unlock_work(tp
);
6047 cancel_work_sync(&tp
->wk
.work
);
6049 phy_disconnect(tp
->phydev
);
6051 pci_free_irq(pdev
, 0, tp
);
6053 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
6055 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
6057 tp
->TxDescArray
= NULL
;
6058 tp
->RxDescArray
= NULL
;
6060 pm_runtime_put_sync(&pdev
->dev
);
6065 #ifdef CONFIG_NET_POLL_CONTROLLER
6066 static void rtl8169_netpoll(struct net_device
*dev
)
6068 struct rtl8169_private
*tp
= netdev_priv(dev
);
6070 rtl8169_interrupt(pci_irq_vector(tp
->pci_dev
, 0), tp
);
6074 static int rtl_open(struct net_device
*dev
)
6076 struct rtl8169_private
*tp
= netdev_priv(dev
);
6077 struct pci_dev
*pdev
= tp
->pci_dev
;
6078 int retval
= -ENOMEM
;
6080 pm_runtime_get_sync(&pdev
->dev
);
6083 * Rx and Tx descriptors needs 256 bytes alignment.
6084 * dma_alloc_coherent provides more.
6086 tp
->TxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
,
6087 &tp
->TxPhyAddr
, GFP_KERNEL
);
6088 if (!tp
->TxDescArray
)
6089 goto err_pm_runtime_put
;
6091 tp
->RxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
,
6092 &tp
->RxPhyAddr
, GFP_KERNEL
);
6093 if (!tp
->RxDescArray
)
6096 retval
= rtl8169_init_ring(tp
);
6100 rtl_request_firmware(tp
);
6102 retval
= pci_request_irq(pdev
, 0, rtl8169_interrupt
, NULL
, tp
,
6105 goto err_release_fw_2
;
6107 retval
= r8169_phy_connect(tp
);
6113 set_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
6115 napi_enable(&tp
->napi
);
6117 rtl8169_init_phy(dev
, tp
);
6119 rtl_pll_power_up(tp
);
6123 if (!rtl8169_init_counter_offsets(tp
))
6124 netif_warn(tp
, hw
, dev
, "counter reset/update failed\n");
6126 phy_start(tp
->phydev
);
6127 netif_start_queue(dev
);
6129 rtl_unlock_work(tp
);
6131 pm_runtime_put_sync(&pdev
->dev
);
6136 pci_free_irq(pdev
, 0, tp
);
6138 rtl_release_firmware(tp
);
6139 rtl8169_rx_clear(tp
);
6141 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
6143 tp
->RxDescArray
= NULL
;
6145 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
6147 tp
->TxDescArray
= NULL
;
6149 pm_runtime_put_noidle(&pdev
->dev
);
6154 rtl8169_get_stats64(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
6156 struct rtl8169_private
*tp
= netdev_priv(dev
);
6157 struct pci_dev
*pdev
= tp
->pci_dev
;
6158 struct rtl8169_counters
*counters
= tp
->counters
;
6161 pm_runtime_get_noresume(&pdev
->dev
);
6163 if (netif_running(dev
) && pm_runtime_active(&pdev
->dev
))
6164 rtl8169_rx_missed(dev
);
6167 start
= u64_stats_fetch_begin_irq(&tp
->rx_stats
.syncp
);
6168 stats
->rx_packets
= tp
->rx_stats
.packets
;
6169 stats
->rx_bytes
= tp
->rx_stats
.bytes
;
6170 } while (u64_stats_fetch_retry_irq(&tp
->rx_stats
.syncp
, start
));
6173 start
= u64_stats_fetch_begin_irq(&tp
->tx_stats
.syncp
);
6174 stats
->tx_packets
= tp
->tx_stats
.packets
;
6175 stats
->tx_bytes
= tp
->tx_stats
.bytes
;
6176 } while (u64_stats_fetch_retry_irq(&tp
->tx_stats
.syncp
, start
));
6178 stats
->rx_dropped
= dev
->stats
.rx_dropped
;
6179 stats
->tx_dropped
= dev
->stats
.tx_dropped
;
6180 stats
->rx_length_errors
= dev
->stats
.rx_length_errors
;
6181 stats
->rx_errors
= dev
->stats
.rx_errors
;
6182 stats
->rx_crc_errors
= dev
->stats
.rx_crc_errors
;
6183 stats
->rx_fifo_errors
= dev
->stats
.rx_fifo_errors
;
6184 stats
->rx_missed_errors
= dev
->stats
.rx_missed_errors
;
6185 stats
->multicast
= dev
->stats
.multicast
;
6188 * Fetch additional counter values missing in stats collected by driver
6189 * from tally counters.
6191 if (pm_runtime_active(&pdev
->dev
))
6192 rtl8169_update_counters(tp
);
6195 * Subtract values fetched during initalization.
6196 * See rtl8169_init_counter_offsets for a description why we do that.
6198 stats
->tx_errors
= le64_to_cpu(counters
->tx_errors
) -
6199 le64_to_cpu(tp
->tc_offset
.tx_errors
);
6200 stats
->collisions
= le32_to_cpu(counters
->tx_multi_collision
) -
6201 le32_to_cpu(tp
->tc_offset
.tx_multi_collision
);
6202 stats
->tx_aborted_errors
= le16_to_cpu(counters
->tx_aborted
) -
6203 le16_to_cpu(tp
->tc_offset
.tx_aborted
);
6205 pm_runtime_put_noidle(&pdev
->dev
);
6208 static void rtl8169_net_suspend(struct net_device
*dev
)
6210 struct rtl8169_private
*tp
= netdev_priv(dev
);
6212 if (!netif_running(dev
))
6215 phy_stop(tp
->phydev
);
6216 netif_device_detach(dev
);
6219 napi_disable(&tp
->napi
);
6220 /* Clear all task flags */
6221 bitmap_zero(tp
->wk
.flags
, RTL_FLAG_MAX
);
6223 rtl_unlock_work(tp
);
6225 rtl_pll_power_down(tp
);
6230 static int rtl8169_suspend(struct device
*device
)
6232 struct net_device
*dev
= dev_get_drvdata(device
);
6233 struct rtl8169_private
*tp
= netdev_priv(dev
);
6235 rtl8169_net_suspend(dev
);
6236 clk_disable_unprepare(tp
->clk
);
6241 static void __rtl8169_resume(struct net_device
*dev
)
6243 struct rtl8169_private
*tp
= netdev_priv(dev
);
6245 netif_device_attach(dev
);
6247 rtl_pll_power_up(tp
);
6248 rtl8169_init_phy(dev
, tp
);
6250 phy_start(tp
->phydev
);
6253 napi_enable(&tp
->napi
);
6254 set_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
6256 rtl_unlock_work(tp
);
6259 static int rtl8169_resume(struct device
*device
)
6261 struct net_device
*dev
= dev_get_drvdata(device
);
6262 struct rtl8169_private
*tp
= netdev_priv(dev
);
6264 rtl_rar_set(tp
, dev
->dev_addr
);
6266 clk_prepare_enable(tp
->clk
);
6268 if (netif_running(dev
))
6269 __rtl8169_resume(dev
);
6274 static int rtl8169_runtime_suspend(struct device
*device
)
6276 struct net_device
*dev
= dev_get_drvdata(device
);
6277 struct rtl8169_private
*tp
= netdev_priv(dev
);
6279 if (!tp
->TxDescArray
)
6283 __rtl8169_set_wol(tp
, WAKE_ANY
);
6284 rtl_unlock_work(tp
);
6286 rtl8169_net_suspend(dev
);
6288 /* Update counters before going runtime suspend */
6289 rtl8169_rx_missed(dev
);
6290 rtl8169_update_counters(tp
);
6295 static int rtl8169_runtime_resume(struct device
*device
)
6297 struct net_device
*dev
= dev_get_drvdata(device
);
6298 struct rtl8169_private
*tp
= netdev_priv(dev
);
6300 rtl_rar_set(tp
, dev
->dev_addr
);
6302 if (!tp
->TxDescArray
)
6306 __rtl8169_set_wol(tp
, tp
->saved_wolopts
);
6307 rtl_unlock_work(tp
);
6309 __rtl8169_resume(dev
);
6314 static int rtl8169_runtime_idle(struct device
*device
)
6316 struct net_device
*dev
= dev_get_drvdata(device
);
6318 if (!netif_running(dev
) || !netif_carrier_ok(dev
))
6319 pm_schedule_suspend(device
, 10000);
6324 static const struct dev_pm_ops rtl8169_pm_ops
= {
6325 .suspend
= rtl8169_suspend
,
6326 .resume
= rtl8169_resume
,
6327 .freeze
= rtl8169_suspend
,
6328 .thaw
= rtl8169_resume
,
6329 .poweroff
= rtl8169_suspend
,
6330 .restore
= rtl8169_resume
,
6331 .runtime_suspend
= rtl8169_runtime_suspend
,
6332 .runtime_resume
= rtl8169_runtime_resume
,
6333 .runtime_idle
= rtl8169_runtime_idle
,
6336 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
6338 #else /* !CONFIG_PM */
6340 #define RTL8169_PM_OPS NULL
6342 #endif /* !CONFIG_PM */
6344 static void rtl_wol_shutdown_quirk(struct rtl8169_private
*tp
)
6346 /* WoL fails with 8168b when the receiver is disabled. */
6347 switch (tp
->mac_version
) {
6348 case RTL_GIGA_MAC_VER_11
:
6349 case RTL_GIGA_MAC_VER_12
:
6350 case RTL_GIGA_MAC_VER_17
:
6351 pci_clear_master(tp
->pci_dev
);
6353 RTL_W8(tp
, ChipCmd
, CmdRxEnb
);
6355 RTL_R8(tp
, ChipCmd
);
6362 static void rtl_shutdown(struct pci_dev
*pdev
)
6364 struct net_device
*dev
= pci_get_drvdata(pdev
);
6365 struct rtl8169_private
*tp
= netdev_priv(dev
);
6367 rtl8169_net_suspend(dev
);
6369 /* Restore original MAC address */
6370 rtl_rar_set(tp
, dev
->perm_addr
);
6372 rtl8169_hw_reset(tp
);
6374 if (system_state
== SYSTEM_POWER_OFF
) {
6375 if (tp
->saved_wolopts
) {
6376 rtl_wol_suspend_quirk(tp
);
6377 rtl_wol_shutdown_quirk(tp
);
6380 pci_wake_from_d3(pdev
, true);
6381 pci_set_power_state(pdev
, PCI_D3hot
);
6385 static void rtl_remove_one(struct pci_dev
*pdev
)
6387 struct net_device
*dev
= pci_get_drvdata(pdev
);
6388 struct rtl8169_private
*tp
= netdev_priv(dev
);
6390 if (r8168_check_dash(tp
))
6391 rtl8168_driver_stop(tp
);
6393 netif_napi_del(&tp
->napi
);
6395 unregister_netdev(dev
);
6396 mdiobus_unregister(tp
->phydev
->mdio
.bus
);
6398 rtl_release_firmware(tp
);
6400 if (pci_dev_run_wake(pdev
))
6401 pm_runtime_get_noresume(&pdev
->dev
);
6403 /* restore original MAC address */
6404 rtl_rar_set(tp
, dev
->perm_addr
);
6407 static const struct net_device_ops rtl_netdev_ops
= {
6408 .ndo_open
= rtl_open
,
6409 .ndo_stop
= rtl8169_close
,
6410 .ndo_get_stats64
= rtl8169_get_stats64
,
6411 .ndo_start_xmit
= rtl8169_start_xmit
,
6412 .ndo_features_check
= rtl8169_features_check
,
6413 .ndo_tx_timeout
= rtl8169_tx_timeout
,
6414 .ndo_validate_addr
= eth_validate_addr
,
6415 .ndo_change_mtu
= rtl8169_change_mtu
,
6416 .ndo_fix_features
= rtl8169_fix_features
,
6417 .ndo_set_features
= rtl8169_set_features
,
6418 .ndo_set_mac_address
= rtl_set_mac_address
,
6419 .ndo_do_ioctl
= rtl8169_ioctl
,
6420 .ndo_set_rx_mode
= rtl_set_rx_mode
,
6421 #ifdef CONFIG_NET_POLL_CONTROLLER
6422 .ndo_poll_controller
= rtl8169_netpoll
,
6427 static void rtl_set_irq_mask(struct rtl8169_private
*tp
)
6429 tp
->irq_mask
= RTL_EVENT_NAPI
| LinkChg
;
6431 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
6432 tp
->irq_mask
|= SYSErr
| RxOverflow
| RxFIFOOver
;
6433 else if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
)
6434 /* special workaround needed */
6435 tp
->irq_mask
|= RxFIFOOver
;
6437 tp
->irq_mask
|= RxOverflow
;
6440 static int rtl_alloc_irq(struct rtl8169_private
*tp
)
6444 switch (tp
->mac_version
) {
6445 case RTL_GIGA_MAC_VER_02
... RTL_GIGA_MAC_VER_06
:
6446 rtl_unlock_config_regs(tp
);
6447 RTL_W8(tp
, Config2
, RTL_R8(tp
, Config2
) & ~MSIEnable
);
6448 rtl_lock_config_regs(tp
);
6450 case RTL_GIGA_MAC_VER_07
... RTL_GIGA_MAC_VER_24
:
6451 flags
= PCI_IRQ_LEGACY
;
6454 flags
= PCI_IRQ_ALL_TYPES
;
6458 return pci_alloc_irq_vectors(tp
->pci_dev
, 1, 1, flags
);
6461 static void rtl_read_mac_address(struct rtl8169_private
*tp
,
6462 u8 mac_addr
[ETH_ALEN
])
6464 /* Get MAC address */
6465 if (rtl_is_8168evl_up(tp
) && tp
->mac_version
!= RTL_GIGA_MAC_VER_34
) {
6466 u32 value
= rtl_eri_read(tp
, 0xe0);
6468 mac_addr
[0] = (value
>> 0) & 0xff;
6469 mac_addr
[1] = (value
>> 8) & 0xff;
6470 mac_addr
[2] = (value
>> 16) & 0xff;
6471 mac_addr
[3] = (value
>> 24) & 0xff;
6473 value
= rtl_eri_read(tp
, 0xe4);
6474 mac_addr
[4] = (value
>> 0) & 0xff;
6475 mac_addr
[5] = (value
>> 8) & 0xff;
6479 DECLARE_RTL_COND(rtl_link_list_ready_cond
)
6481 return RTL_R8(tp
, MCU
) & LINK_LIST_RDY
;
6484 DECLARE_RTL_COND(rtl_rxtx_empty_cond
)
6486 return (RTL_R8(tp
, MCU
) & RXTX_EMPTY
) == RXTX_EMPTY
;
6489 static int r8169_mdio_read_reg(struct mii_bus
*mii_bus
, int phyaddr
, int phyreg
)
6491 struct rtl8169_private
*tp
= mii_bus
->priv
;
6496 return rtl_readphy(tp
, phyreg
);
6499 static int r8169_mdio_write_reg(struct mii_bus
*mii_bus
, int phyaddr
,
6500 int phyreg
, u16 val
)
6502 struct rtl8169_private
*tp
= mii_bus
->priv
;
6507 rtl_writephy(tp
, phyreg
, val
);
6512 static int r8169_mdio_register(struct rtl8169_private
*tp
)
6514 struct pci_dev
*pdev
= tp
->pci_dev
;
6515 struct mii_bus
*new_bus
;
6518 new_bus
= devm_mdiobus_alloc(&pdev
->dev
);
6522 new_bus
->name
= "r8169";
6524 new_bus
->parent
= &pdev
->dev
;
6525 new_bus
->irq
[0] = PHY_IGNORE_INTERRUPT
;
6526 snprintf(new_bus
->id
, MII_BUS_ID_SIZE
, "r8169-%x", pci_dev_id(pdev
));
6528 new_bus
->read
= r8169_mdio_read_reg
;
6529 new_bus
->write
= r8169_mdio_write_reg
;
6531 ret
= mdiobus_register(new_bus
);
6535 tp
->phydev
= mdiobus_get_phy(new_bus
, 0);
6537 mdiobus_unregister(new_bus
);
6541 /* PHY will be woken up in rtl_open() */
6542 phy_suspend(tp
->phydev
);
6547 static void rtl_hw_init_8168g(struct rtl8169_private
*tp
)
6549 tp
->ocp_base
= OCP_STD_PHY_BASE
;
6551 RTL_W32(tp
, MISC
, RTL_R32(tp
, MISC
) | RXDV_GATED_EN
);
6553 if (!rtl_udelay_loop_wait_high(tp
, &rtl_txcfg_empty_cond
, 100, 42))
6556 if (!rtl_udelay_loop_wait_high(tp
, &rtl_rxtx_empty_cond
, 100, 42))
6559 RTL_W8(tp
, ChipCmd
, RTL_R8(tp
, ChipCmd
) & ~(CmdTxEnb
| CmdRxEnb
));
6561 RTL_W8(tp
, MCU
, RTL_R8(tp
, MCU
) & ~NOW_IS_OOB
);
6563 r8168_mac_ocp_modify(tp
, 0xe8de, BIT(14), 0);
6565 if (!rtl_udelay_loop_wait_high(tp
, &rtl_link_list_ready_cond
, 100, 42))
6568 r8168_mac_ocp_modify(tp
, 0xe8de, 0, BIT(15));
6570 rtl_udelay_loop_wait_high(tp
, &rtl_link_list_ready_cond
, 100, 42);
6573 static void rtl_hw_initialize(struct rtl8169_private
*tp
)
6575 switch (tp
->mac_version
) {
6576 case RTL_GIGA_MAC_VER_49
... RTL_GIGA_MAC_VER_51
:
6577 rtl8168ep_stop_cmac(tp
);
6579 case RTL_GIGA_MAC_VER_40
... RTL_GIGA_MAC_VER_48
:
6580 rtl_hw_init_8168g(tp
);
6587 static int rtl_jumbo_max(struct rtl8169_private
*tp
)
6589 /* Non-GBit versions don't support jumbo frames */
6590 if (!tp
->supports_gmii
)
6593 switch (tp
->mac_version
) {
6595 case RTL_GIGA_MAC_VER_02
... RTL_GIGA_MAC_VER_06
:
6598 case RTL_GIGA_MAC_VER_11
:
6599 case RTL_GIGA_MAC_VER_12
:
6600 case RTL_GIGA_MAC_VER_17
:
6603 case RTL_GIGA_MAC_VER_18
... RTL_GIGA_MAC_VER_24
:
6610 static void rtl_disable_clk(void *data
)
6612 clk_disable_unprepare(data
);
6615 static int rtl_get_ether_clk(struct rtl8169_private
*tp
)
6617 struct device
*d
= tp_to_dev(tp
);
6621 clk
= devm_clk_get(d
, "ether_clk");
6625 /* clk-core allows NULL (for suspend / resume) */
6627 else if (rc
!= -EPROBE_DEFER
)
6628 dev_err(d
, "failed to get clk: %d\n", rc
);
6631 rc
= clk_prepare_enable(clk
);
6633 dev_err(d
, "failed to enable clk: %d\n", rc
);
6635 rc
= devm_add_action_or_reset(d
, rtl_disable_clk
, clk
);
6641 static void rtl_init_mac_address(struct rtl8169_private
*tp
)
6643 struct net_device
*dev
= tp
->dev
;
6644 u8
*mac_addr
= dev
->dev_addr
;
6647 rc
= eth_platform_get_mac_address(tp_to_dev(tp
), mac_addr
);
6651 rtl_read_mac_address(tp
, mac_addr
);
6652 if (is_valid_ether_addr(mac_addr
))
6655 rtl_read_mac_from_reg(tp
, mac_addr
, MAC0
);
6656 if (is_valid_ether_addr(mac_addr
))
6659 eth_hw_addr_random(dev
);
6660 dev_warn(tp_to_dev(tp
), "can't read MAC address, setting random one\n");
6662 rtl_rar_set(tp
, mac_addr
);
6665 static int rtl_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
6667 struct rtl8169_private
*tp
;
6668 struct net_device
*dev
;
6669 int chipset
, region
;
6672 dev
= devm_alloc_etherdev(&pdev
->dev
, sizeof (*tp
));
6676 SET_NETDEV_DEV(dev
, &pdev
->dev
);
6677 dev
->netdev_ops
= &rtl_netdev_ops
;
6678 tp
= netdev_priv(dev
);
6681 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
6682 tp
->supports_gmii
= ent
->driver_data
== RTL_CFG_NO_GBIT
? 0 : 1;
6684 /* Get the *optional* external "ether_clk" used on some boards */
6685 rc
= rtl_get_ether_clk(tp
);
6689 /* Disable ASPM completely as that cause random device stop working
6690 * problems as well as full system hangs for some PCIe devices users.
6692 rc
= pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
|
6693 PCIE_LINK_STATE_L1
);
6694 tp
->aspm_manageable
= !rc
;
6696 /* enable device (incl. PCI PM wakeup and hotplug setup) */
6697 rc
= pcim_enable_device(pdev
);
6699 dev_err(&pdev
->dev
, "enable failure\n");
6703 if (pcim_set_mwi(pdev
) < 0)
6704 dev_info(&pdev
->dev
, "Mem-Wr-Inval unavailable\n");
6706 /* use first MMIO region */
6707 region
= ffs(pci_select_bars(pdev
, IORESOURCE_MEM
)) - 1;
6709 dev_err(&pdev
->dev
, "no MMIO resource found\n");
6713 /* check for weird/broken PCI region reporting */
6714 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
6715 dev_err(&pdev
->dev
, "Invalid PCI region size(s), aborting\n");
6719 rc
= pcim_iomap_regions(pdev
, BIT(region
), MODULENAME
);
6721 dev_err(&pdev
->dev
, "cannot remap MMIO, aborting\n");
6725 tp
->mmio_addr
= pcim_iomap_table(pdev
)[region
];
6727 /* Identify chip attached to board */
6728 rtl8169_get_mac_version(tp
);
6729 if (tp
->mac_version
== RTL_GIGA_MAC_NONE
)
6732 tp
->cp_cmd
= RTL_R16(tp
, CPlusCmd
);
6734 if (sizeof(dma_addr_t
) > 4 && tp
->mac_version
>= RTL_GIGA_MAC_VER_18
&&
6735 !dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64)))
6736 dev
->features
|= NETIF_F_HIGHDMA
;
6740 rtl8169_irq_mask_and_ack(tp
);
6742 rtl_hw_initialize(tp
);
6746 pci_set_master(pdev
);
6748 chipset
= tp
->mac_version
;
6750 rc
= rtl_alloc_irq(tp
);
6752 dev_err(&pdev
->dev
, "Can't allocate interrupt\n");
6756 mutex_init(&tp
->wk
.mutex
);
6757 INIT_WORK(&tp
->wk
.work
, rtl_task
);
6758 u64_stats_init(&tp
->rx_stats
.syncp
);
6759 u64_stats_init(&tp
->tx_stats
.syncp
);
6761 rtl_init_mac_address(tp
);
6763 dev
->ethtool_ops
= &rtl8169_ethtool_ops
;
6765 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, NAPI_POLL_WEIGHT
);
6767 dev
->features
|= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
6768 NETIF_F_RXCSUM
| NETIF_F_HW_VLAN_CTAG_TX
|
6769 NETIF_F_HW_VLAN_CTAG_RX
;
6770 dev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
6771 NETIF_F_RXCSUM
| NETIF_F_HW_VLAN_CTAG_TX
|
6772 NETIF_F_HW_VLAN_CTAG_RX
;
6773 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
6775 dev
->priv_flags
|= IFF_LIVE_ADDR_CHANGE
;
6777 tp
->cp_cmd
|= RxChkSum
| RxVlan
;
6780 * Pretend we are using VLANs; This bypasses a nasty bug where
6781 * Interrupts stop flowing on high load on 8110SCd controllers.
6783 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
6784 /* Disallow toggling */
6785 dev
->hw_features
&= ~NETIF_F_HW_VLAN_CTAG_RX
;
6787 if (rtl_chip_supports_csum_v2(tp
)) {
6788 dev
->hw_features
|= NETIF_F_IPV6_CSUM
| NETIF_F_TSO6
;
6789 dev
->features
|= NETIF_F_IPV6_CSUM
| NETIF_F_TSO6
;
6790 dev
->gso_max_size
= RTL_GSO_MAX_SIZE_V2
;
6791 dev
->gso_max_segs
= RTL_GSO_MAX_SEGS_V2
;
6793 dev
->gso_max_size
= RTL_GSO_MAX_SIZE_V1
;
6794 dev
->gso_max_segs
= RTL_GSO_MAX_SEGS_V1
;
6797 /* RTL8168e-vl has a HW issue with TSO */
6798 if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
) {
6799 dev
->vlan_features
&= ~(NETIF_F_ALL_TSO
| NETIF_F_SG
);
6800 dev
->hw_features
&= ~(NETIF_F_ALL_TSO
| NETIF_F_SG
);
6801 dev
->features
&= ~(NETIF_F_ALL_TSO
| NETIF_F_SG
);
6804 dev
->hw_features
|= NETIF_F_RXALL
;
6805 dev
->hw_features
|= NETIF_F_RXFCS
;
6807 /* MTU range: 60 - hw-specific max */
6808 dev
->min_mtu
= ETH_ZLEN
;
6809 jumbo_max
= rtl_jumbo_max(tp
);
6810 dev
->max_mtu
= jumbo_max
;
6812 rtl_set_irq_mask(tp
);
6814 tp
->fw_name
= rtl_chip_infos
[chipset
].fw_name
;
6816 tp
->counters
= dmam_alloc_coherent (&pdev
->dev
, sizeof(*tp
->counters
),
6817 &tp
->counters_phys_addr
,
6822 pci_set_drvdata(pdev
, dev
);
6824 rc
= r8169_mdio_register(tp
);
6828 /* chip gets powered up in rtl_open() */
6829 rtl_pll_power_down(tp
);
6831 rc
= register_netdev(dev
);
6833 goto err_mdio_unregister
;
6835 netif_info(tp
, probe
, dev
, "%s, %pM, XID %03x, IRQ %d\n",
6836 rtl_chip_infos
[chipset
].name
, dev
->dev_addr
,
6837 (RTL_R32(tp
, TxConfig
) >> 20) & 0xfcf,
6838 pci_irq_vector(pdev
, 0));
6840 if (jumbo_max
> JUMBO_1K
)
6841 netif_info(tp
, probe
, dev
,
6842 "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
6843 jumbo_max
, tp
->mac_version
<= RTL_GIGA_MAC_VER_06
?
6846 if (r8168_check_dash(tp
))
6847 rtl8168_driver_start(tp
);
6849 if (pci_dev_run_wake(pdev
))
6850 pm_runtime_put_sync(&pdev
->dev
);
6854 err_mdio_unregister
:
6855 mdiobus_unregister(tp
->phydev
->mdio
.bus
);
6859 static struct pci_driver rtl8169_pci_driver
= {
6861 .id_table
= rtl8169_pci_tbl
,
6862 .probe
= rtl_init_one
,
6863 .remove
= rtl_remove_one
,
6864 .shutdown
= rtl_shutdown
,
6865 .driver
.pm
= RTL8169_PM_OPS
,
6868 module_pci_driver(rtl8169_pci_driver
);