]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blob - drivers/net/ethernet/realtek/r8169_main.c
projects / mirror_ubuntu-hirsute-kernel.git / blob
? search:


8910e900ec45e8ac9fb21792bfdd5b35cb4e7adb
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / realtek / r8169_main.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 *
5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
7 * Copyright (c) a lot of people too. Please respect their work.
8 *
9 * See MAINTAINERS file for support contact information.
10 */
11
12 #include <linux/module.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/ethtool.h>
19 #include <linux/phy.h>
20 #include <linux/if_vlan.h>
21 #include <linux/in.h>
22 #include <linux/io.h>
23 #include <linux/ip.h>
24 #include <linux/tcp.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/bitfield.h>
29 #include <linux/prefetch.h>
30 #include <linux/ipv6.h>
31 #include <net/ip6_checksum.h>
32
33 #include "r8169.h"
34 #include "r8169_firmware.h"
35
36 #define MODULENAME "r8169"
37
38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
53 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
54 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
55 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw"
56 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
57 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
58 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw"
59 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw"
60
61 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
62 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
63 #define MC_FILTER_LIMIT 32
64
65 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
66 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
67
68 #define R8169_REGS_SIZE 256
69 #define R8169_RX_BUF_SIZE (SZ_16K - 1)
70 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */
71 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
72 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
73 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
74
75 #define OCP_STD_PHY_BASE 0xa400
76
77 #define RTL_CFG_NO_GBIT 1
78
79 /* write/read MMIO register */
80 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
81 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
82 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
83 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
84 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
85 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
86
87 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
88 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
89 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
90 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
91
92 static const struct {
93 const char *name;
94 const char *fw_name;
95 } rtl_chip_infos[] = {
96 /* PCI devices. */
97 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
98 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
99 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
100 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
101 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
102 /* PCI-E devices. */
103 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
104 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
105 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" },
106 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
107 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
108 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
109 [RTL_GIGA_MAC_VER_13] = {"RTL8101e/RTL8100e" },
110 [RTL_GIGA_MAC_VER_14] = {"RTL8401" },
111 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
112 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
113 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
114 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
115 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
116 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
117 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
118 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
119 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
120 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
121 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
122 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
123 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
124 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
125 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
126 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
127 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
128 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
129 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
130 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
131 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
132 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
133 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
134 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
135 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
136 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
137 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3},
138 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2},
139 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 },
140 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
141 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
142 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
143 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
144 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
145 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
146 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
147 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3},
148 [RTL_GIGA_MAC_VER_60] = {"RTL8125A" },
149 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3},
150 /* reserve 62 for CFG_METHOD_4 in the vendor driver */
151 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2},
152 };
153
154 static const struct pci_device_id rtl8169_pci_tbl[] = {
155 { PCI_VDEVICE(REALTEK, 0x2502) },
156 { PCI_VDEVICE(REALTEK, 0x2600) },
157 { PCI_VDEVICE(REALTEK, 0x8129) },
158 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
159 { PCI_VDEVICE(REALTEK, 0x8161) },
160 { PCI_VDEVICE(REALTEK, 0x8167) },
161 { PCI_VDEVICE(REALTEK, 0x8168) },
162 { PCI_VDEVICE(NCUBE, 0x8168) },
163 { PCI_VDEVICE(REALTEK, 0x8169) },
164 { PCI_VENDOR_ID_DLINK, 0x4300,
165 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
166 { PCI_VDEVICE(DLINK, 0x4300) },
167 { PCI_VDEVICE(DLINK, 0x4302) },
168 { PCI_VDEVICE(AT, 0xc107) },
169 { PCI_VDEVICE(USR, 0x0116) },
170 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
171 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
172 { PCI_VDEVICE(REALTEK, 0x8125) },
173 { PCI_VDEVICE(REALTEK, 0x3000) },
174 {}
175 };
176
177 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
178
179 enum rtl_registers {
180 MAC0 = 0, /* Ethernet hardware address. */
181 MAC4 = 4,
182 MAR0 = 8, /* Multicast filter. */
183 CounterAddrLow = 0x10,
184 CounterAddrHigh = 0x14,
185 TxDescStartAddrLow = 0x20,
186 TxDescStartAddrHigh = 0x24,
187 TxHDescStartAddrLow = 0x28,
188 TxHDescStartAddrHigh = 0x2c,
189 FLASH = 0x30,
190 ERSR = 0x36,
191 ChipCmd = 0x37,
192 TxPoll = 0x38,
193 IntrMask = 0x3c,
194 IntrStatus = 0x3e,
195
196 TxConfig = 0x40,
197 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
198 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
199
200 RxConfig = 0x44,
201 #define RX128_INT_EN (1 << 15) /* 8111c and later */
202 #define RX_MULTI_EN (1 << 14) /* 8111c only */
203 #define RXCFG_FIFO_SHIFT 13
204 /* No threshold before first PCI xfer */
205 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
206 #define RX_EARLY_OFF (1 << 11)
207 #define RXCFG_DMA_SHIFT 8
208 /* Unlimited maximum PCI burst. */
209 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
210
211 Cfg9346 = 0x50,
212 Config0 = 0x51,
213 Config1 = 0x52,
214 Config2 = 0x53,
215 #define PME_SIGNAL (1 << 5) /* 8168c and later */
216
217 Config3 = 0x54,
218 Config4 = 0x55,
219 Config5 = 0x56,
220 PHYAR = 0x60,
221 PHYstatus = 0x6c,
222 RxMaxSize = 0xda,
223 CPlusCmd = 0xe0,
224 IntrMitigate = 0xe2,
225
226 #define RTL_COALESCE_TX_USECS GENMASK(15, 12)
227 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8)
228 #define RTL_COALESCE_RX_USECS GENMASK(7, 4)
229 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0)
230
231 #define RTL_COALESCE_T_MAX 0x0fU
232 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4)
233
234 RxDescAddrLow = 0xe4,
235 RxDescAddrHigh = 0xe8,
236 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
237
238 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
239
240 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
241
242 #define TxPacketMax (8064 >> 7)
243 #define EarlySize 0x27
244
245 FuncEvent = 0xf0,
246 FuncEventMask = 0xf4,
247 FuncPresetState = 0xf8,
248 IBCR0 = 0xf8,
249 IBCR2 = 0xf9,
250 IBIMR0 = 0xfa,
251 IBISR0 = 0xfb,
252 FuncForceEvent = 0xfc,
253 };
254
255 enum rtl8168_8101_registers {
256 CSIDR = 0x64,
257 CSIAR = 0x68,
258 #define CSIAR_FLAG 0x80000000
259 #define CSIAR_WRITE_CMD 0x80000000
260 #define CSIAR_BYTE_ENABLE 0x0000f000
261 #define CSIAR_ADDR_MASK 0x00000fff
262 PMCH = 0x6f,
263 EPHYAR = 0x80,
264 #define EPHYAR_FLAG 0x80000000
265 #define EPHYAR_WRITE_CMD 0x80000000
266 #define EPHYAR_REG_MASK 0x1f
267 #define EPHYAR_REG_SHIFT 16
268 #define EPHYAR_DATA_MASK 0xffff
269 DLLPR = 0xd0,
270 #define PFM_EN (1 << 6)
271 #define TX_10M_PS_EN (1 << 7)
272 DBG_REG = 0xd1,
273 #define FIX_NAK_1 (1 << 4)
274 #define FIX_NAK_2 (1 << 3)
275 TWSI = 0xd2,
276 MCU = 0xd3,
277 #define NOW_IS_OOB (1 << 7)
278 #define TX_EMPTY (1 << 5)
279 #define RX_EMPTY (1 << 4)
280 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
281 #define EN_NDP (1 << 3)
282 #define EN_OOB_RESET (1 << 2)
283 #define LINK_LIST_RDY (1 << 1)
284 EFUSEAR = 0xdc,
285 #define EFUSEAR_FLAG 0x80000000
286 #define EFUSEAR_WRITE_CMD 0x80000000
287 #define EFUSEAR_READ_CMD 0x00000000
288 #define EFUSEAR_REG_MASK 0x03ff
289 #define EFUSEAR_REG_SHIFT 8
290 #define EFUSEAR_DATA_MASK 0xff
291 MISC_1 = 0xf2,
292 #define PFM_D3COLD_EN (1 << 6)
293 };
294
295 enum rtl8168_registers {
296 LED_FREQ = 0x1a,
297 EEE_LED = 0x1b,
298 ERIDR = 0x70,
299 ERIAR = 0x74,
300 #define ERIAR_FLAG 0x80000000
301 #define ERIAR_WRITE_CMD 0x80000000
302 #define ERIAR_READ_CMD 0x00000000
303 #define ERIAR_ADDR_BYTE_ALIGN 4
304 #define ERIAR_TYPE_SHIFT 16
305 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
306 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
307 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
308 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
309 #define ERIAR_MASK_SHIFT 12
310 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
311 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
312 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
313 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
314 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
315 EPHY_RXER_NUM = 0x7c,
316 OCPDR = 0xb0, /* OCP GPHY access */
317 #define OCPDR_WRITE_CMD 0x80000000
318 #define OCPDR_READ_CMD 0x00000000
319 #define OCPDR_REG_MASK 0x7f
320 #define OCPDR_GPHY_REG_SHIFT 16
321 #define OCPDR_DATA_MASK 0xffff
322 OCPAR = 0xb4,
323 #define OCPAR_FLAG 0x80000000
324 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
325 #define OCPAR_GPHY_READ_CMD 0x0000f060
326 GPHY_OCP = 0xb8,
327 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
328 MISC = 0xf0, /* 8168e only. */
329 #define TXPLA_RST (1 << 29)
330 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
331 #define PWM_EN (1 << 22)
332 #define RXDV_GATED_EN (1 << 19)
333 #define EARLY_TALLY_EN (1 << 16)
334 };
335
336 enum rtl8125_registers {
337 IntrMask_8125 = 0x38,
338 IntrStatus_8125 = 0x3c,
339 TxPoll_8125 = 0x90,
340 MAC0_BKP = 0x19e0,
341 EEE_TXIDLE_TIMER_8125 = 0x6048,
342 };
343
344 #define RX_VLAN_INNER_8125 BIT(22)
345 #define RX_VLAN_OUTER_8125 BIT(23)
346 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
347
348 #define RX_FETCH_DFLT_8125 (8 << 27)
349
350 enum rtl_register_content {
351 /* InterruptStatusBits */
352 SYSErr = 0x8000,
353 PCSTimeout = 0x4000,
354 SWInt = 0x0100,
355 TxDescUnavail = 0x0080,
356 RxFIFOOver = 0x0040,
357 LinkChg = 0x0020,
358 RxOverflow = 0x0010,
359 TxErr = 0x0008,
360 TxOK = 0x0004,
361 RxErr = 0x0002,
362 RxOK = 0x0001,
363
364 /* RxStatusDesc */
365 RxRWT = (1 << 22),
366 RxRES = (1 << 21),
367 RxRUNT = (1 << 20),
368 RxCRC = (1 << 19),
369
370 /* ChipCmdBits */
371 StopReq = 0x80,
372 CmdReset = 0x10,
373 CmdRxEnb = 0x08,
374 CmdTxEnb = 0x04,
375 RxBufEmpty = 0x01,
376
377 /* TXPoll register p.5 */
378 HPQ = 0x80, /* Poll cmd on the high prio queue */
379 NPQ = 0x40, /* Poll cmd on the low prio queue */
380 FSWInt = 0x01, /* Forced software interrupt */
381
382 /* Cfg9346Bits */
383 Cfg9346_Lock = 0x00,
384 Cfg9346_Unlock = 0xc0,
385
386 /* rx_mode_bits */
387 AcceptErr = 0x20,
388 AcceptRunt = 0x10,
389 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30
390 AcceptBroadcast = 0x08,
391 AcceptMulticast = 0x04,
392 AcceptMyPhys = 0x02,
393 AcceptAllPhys = 0x01,
394 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f
395 #define RX_CONFIG_ACCEPT_MASK 0x3f
396
397 /* TxConfigBits */
398 TxInterFrameGapShift = 24,
399 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
400
401 /* Config1 register p.24 */
402 LEDS1 = (1 << 7),
403 LEDS0 = (1 << 6),
404 Speed_down = (1 << 4),
405 MEMMAP = (1 << 3),
406 IOMAP = (1 << 2),
407 VPD = (1 << 1),
408 PMEnable = (1 << 0), /* Power Management Enable */
409
410 /* Config2 register p. 25 */
411 ClkReqEn = (1 << 7), /* Clock Request Enable */
412 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
413 PCI_Clock_66MHz = 0x01,
414 PCI_Clock_33MHz = 0x00,
415
416 /* Config3 register p.25 */
417 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
418 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
419 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
420 Rdy_to_L23 = (1 << 1), /* L23 Enable */
421 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
422
423 /* Config4 register */
424 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
425
426 /* Config5 register p.27 */
427 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
428 MWF = (1 << 5), /* Accept Multicast wakeup frame */
429 UWF = (1 << 4), /* Accept Unicast wakeup frame */
430 Spi_en = (1 << 3),
431 LanWake = (1 << 1), /* LanWake enable/disable */
432 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
433 ASPM_en = (1 << 0), /* ASPM enable */
434
435 /* CPlusCmd p.31 */
436 EnableBist = (1 << 15), // 8168 8101
437 Mac_dbgo_oe = (1 << 14), // 8168 8101
438 EnAnaPLL = (1 << 14), // 8169
439 Normal_mode = (1 << 13), // unused
440 Force_half_dup = (1 << 12), // 8168 8101
441 Force_rxflow_en = (1 << 11), // 8168 8101
442 Force_txflow_en = (1 << 10), // 8168 8101
443 Cxpl_dbg_sel = (1 << 9), // 8168 8101
444 ASF = (1 << 8), // 8168 8101
445 PktCntrDisable = (1 << 7), // 8168 8101
446 Mac_dbgo_sel = 0x001c, // 8168
447 RxVlan = (1 << 6),
448 RxChkSum = (1 << 5),
449 PCIDAC = (1 << 4),
450 PCIMulRW = (1 << 3),
451 #define INTT_MASK GENMASK(1, 0)
452 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
453
454 /* rtl8169_PHYstatus */
455 TBI_Enable = 0x80,
456 TxFlowCtrl = 0x40,
457 RxFlowCtrl = 0x20,
458 _1000bpsF = 0x10,
459 _100bps = 0x08,
460 _10bps = 0x04,
461 LinkStatus = 0x02,
462 FullDup = 0x01,
463
464 /* ResetCounterCommand */
465 CounterReset = 0x1,
466
467 /* DumpCounterCommand */
468 CounterDump = 0x8,
469
470 /* magic enable v2 */
471 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
472 };
473
474 enum rtl_desc_bit {
475 /* First doubleword. */
476 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
477 RingEnd = (1 << 30), /* End of descriptor ring */
478 FirstFrag = (1 << 29), /* First segment of a packet */
479 LastFrag = (1 << 28), /* Final segment of a packet */
480 };
481
482 /* Generic case. */
483 enum rtl_tx_desc_bit {
484 /* First doubleword. */
485 TD_LSO = (1 << 27), /* Large Send Offload */
486 #define TD_MSS_MAX 0x07ffu /* MSS value */
487
488 /* Second doubleword. */
489 TxVlanTag = (1 << 17), /* Add VLAN tag */
490 };
491
492 /* 8169, 8168b and 810x except 8102e. */
493 enum rtl_tx_desc_bit_0 {
494 /* First doubleword. */
495 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
496 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
497 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
498 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
499 };
500
501 /* 8102e, 8168c and beyond. */
502 enum rtl_tx_desc_bit_1 {
503 /* First doubleword. */
504 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
505 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
506 #define GTTCPHO_SHIFT 18
507 #define GTTCPHO_MAX 0x7f
508
509 /* Second doubleword. */
510 #define TCPHO_SHIFT 18
511 #define TCPHO_MAX 0x3ff
512 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
513 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
514 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
515 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
516 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
517 };
518
519 enum rtl_rx_desc_bit {
520 /* Rx private */
521 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
522 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
523
524 #define RxProtoUDP (PID1)
525 #define RxProtoTCP (PID0)
526 #define RxProtoIP (PID1 | PID0)
527 #define RxProtoMask RxProtoIP
528
529 IPFail = (1 << 16), /* IP checksum failed */
530 UDPFail = (1 << 15), /* UDP/IP checksum failed */
531 TCPFail = (1 << 14), /* TCP/IP checksum failed */
532 RxVlanTag = (1 << 16), /* VLAN tag available */
533 };
534
535 #define RTL_GSO_MAX_SIZE_V1 32000
536 #define RTL_GSO_MAX_SEGS_V1 24
537 #define RTL_GSO_MAX_SIZE_V2 64000
538 #define RTL_GSO_MAX_SEGS_V2 64
539
540 struct TxDesc {
541 __le32 opts1;
542 __le32 opts2;
543 __le64 addr;
544 };
545
546 struct RxDesc {
547 __le32 opts1;
548 __le32 opts2;
549 __le64 addr;
550 };
551
552 struct ring_info {
553 struct sk_buff *skb;
554 u32 len;
555 };
556
557 struct rtl8169_counters {
558 __le64 tx_packets;
559 __le64 rx_packets;
560 __le64 tx_errors;
561 __le32 rx_errors;
562 __le16 rx_missed;
563 __le16 align_errors;
564 __le32 tx_one_collision;
565 __le32 tx_multi_collision;
566 __le64 rx_unicast;
567 __le64 rx_broadcast;
568 __le32 rx_multicast;
569 __le16 tx_aborted;
570 __le16 tx_underun;
571 };
572
573 struct rtl8169_tc_offsets {
574 bool inited;
575 __le64 tx_errors;
576 __le32 tx_multi_collision;
577 __le16 tx_aborted;
578 __le16 rx_missed;
579 };
580
581 enum rtl_flag {
582 RTL_FLAG_TASK_ENABLED = 0,
583 RTL_FLAG_TASK_RESET_PENDING,
584 RTL_FLAG_MAX
585 };
586
587 struct rtl8169_private {
588 void __iomem *mmio_addr; /* memory map physical address */
589 struct pci_dev *pci_dev;
590 struct net_device *dev;
591 struct phy_device *phydev;
592 struct napi_struct napi;
593 enum mac_version mac_version;
594 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
595 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
596 u32 dirty_tx;
597 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
598 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
599 dma_addr_t TxPhyAddr;
600 dma_addr_t RxPhyAddr;
601 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
602 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
603 u16 cp_cmd;
604 u32 irq_mask;
605 struct clk *clk;
606
607 struct {
608 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
609 struct work_struct work;
610 } wk;
611
612 unsigned supports_gmii:1;
613 unsigned aspm_manageable:1;
614 dma_addr_t counters_phys_addr;
615 struct rtl8169_counters *counters;
616 struct rtl8169_tc_offsets tc_offset;
617 u32 saved_wolopts;
618 int eee_adv;
619
620 const char *fw_name;
621 struct rtl_fw *rtl_fw;
622
623 u32 ocp_base;
624 };
625
626 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
627
628 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
629 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
630 MODULE_SOFTDEP("pre: realtek");
631 MODULE_LICENSE("GPL");
632 MODULE_FIRMWARE(FIRMWARE_8168D_1);
633 MODULE_FIRMWARE(FIRMWARE_8168D_2);
634 MODULE_FIRMWARE(FIRMWARE_8168E_1);
635 MODULE_FIRMWARE(FIRMWARE_8168E_2);
636 MODULE_FIRMWARE(FIRMWARE_8168E_3);
637 MODULE_FIRMWARE(FIRMWARE_8105E_1);
638 MODULE_FIRMWARE(FIRMWARE_8168F_1);
639 MODULE_FIRMWARE(FIRMWARE_8168F_2);
640 MODULE_FIRMWARE(FIRMWARE_8402_1);
641 MODULE_FIRMWARE(FIRMWARE_8411_1);
642 MODULE_FIRMWARE(FIRMWARE_8411_2);
643 MODULE_FIRMWARE(FIRMWARE_8106E_1);
644 MODULE_FIRMWARE(FIRMWARE_8106E_2);
645 MODULE_FIRMWARE(FIRMWARE_8168G_2);
646 MODULE_FIRMWARE(FIRMWARE_8168G_3);
647 MODULE_FIRMWARE(FIRMWARE_8168H_1);
648 MODULE_FIRMWARE(FIRMWARE_8168H_2);
649 MODULE_FIRMWARE(FIRMWARE_8168FP_3);
650 MODULE_FIRMWARE(FIRMWARE_8107E_1);
651 MODULE_FIRMWARE(FIRMWARE_8107E_2);
652 MODULE_FIRMWARE(FIRMWARE_8125A_3);
653 MODULE_FIRMWARE(FIRMWARE_8125B_2);
654
655 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
656 {
657 return &tp->pci_dev->dev;
658 }
659
660 static void rtl_lock_config_regs(struct rtl8169_private *tp)
661 {
662 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
663 }
664
665 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
666 {
667 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
668 }
669
670 static void rtl_pci_commit(struct rtl8169_private *tp)
671 {
672 /* Read an arbitrary register to commit a preceding PCI write */
673 RTL_R8(tp, ChipCmd);
674 }
675
676 static bool rtl_is_8125(struct rtl8169_private *tp)
677 {
678 return tp->mac_version >= RTL_GIGA_MAC_VER_60;
679 }
680
681 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
682 {
683 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
684 tp->mac_version != RTL_GIGA_MAC_VER_39 &&
685 tp->mac_version <= RTL_GIGA_MAC_VER_52;
686 }
687
688 static bool rtl_supports_eee(struct rtl8169_private *tp)
689 {
690 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
691 tp->mac_version != RTL_GIGA_MAC_VER_37 &&
692 tp->mac_version != RTL_GIGA_MAC_VER_39;
693 }
694
695 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
696 {
697 int i;
698
699 for (i = 0; i < ETH_ALEN; i++)
700 mac[i] = RTL_R8(tp, reg + i);
701 }
702
703 struct rtl_cond {
704 bool (*check)(struct rtl8169_private *);
705 const char *msg;
706 };
707
708 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
709 unsigned long usecs, int n, bool high)
710 {
711 int i;
712
713 for (i = 0; i < n; i++) {
714 if (c->check(tp) == high)
715 return true;
716 fsleep(usecs);
717 }
718
719 if (net_ratelimit())
720 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",
721 c->msg, !high, n, usecs);
722 return false;
723 }
724
725 static bool rtl_loop_wait_high(struct rtl8169_private *tp,
726 const struct rtl_cond *c,
727 unsigned long d, int n)
728 {
729 return rtl_loop_wait(tp, c, d, n, true);
730 }
731
732 static bool rtl_loop_wait_low(struct rtl8169_private *tp,
733 const struct rtl_cond *c,
734 unsigned long d, int n)
735 {
736 return rtl_loop_wait(tp, c, d, n, false);
737 }
738
739 #define DECLARE_RTL_COND(name) \
740 static bool name ## _check(struct rtl8169_private *); \
741 \
742 static const struct rtl_cond name = { \
743 .check = name ## _check, \
744 .msg = #name \
745 }; \
746 \
747 static bool name ## _check(struct rtl8169_private *tp)
748
749 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
750 {
751 if (reg & 0xffff0001) {
752 if (net_ratelimit())
753 netdev_err(tp->dev, "Invalid ocp reg %x!\n", reg);
754 return true;
755 }
756 return false;
757 }
758
759 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
760 {
761 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
762 }
763
764 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
765 {
766 if (rtl_ocp_reg_failure(tp, reg))
767 return;
768
769 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
770
771 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
772 }
773
774 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
775 {
776 if (rtl_ocp_reg_failure(tp, reg))
777 return 0;
778
779 RTL_W32(tp, GPHY_OCP, reg << 15);
780
781 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
782 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
783 }
784
785 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
786 {
787 if (rtl_ocp_reg_failure(tp, reg))
788 return;
789
790 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
791 }
792
793 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
794 {
795 if (rtl_ocp_reg_failure(tp, reg))
796 return 0;
797
798 RTL_W32(tp, OCPDR, reg << 15);
799
800 return RTL_R32(tp, OCPDR);
801 }
802
803 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
804 u16 set)
805 {
806 u16 data = r8168_mac_ocp_read(tp, reg);
807
808 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
809 }
810
811 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
812 {
813 if (reg == 0x1f) {
814 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
815 return;
816 }
817
818 if (tp->ocp_base != OCP_STD_PHY_BASE)
819 reg -= 0x10;
820
821 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
822 }
823
824 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
825 {
826 if (reg == 0x1f)
827 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
828
829 if (tp->ocp_base != OCP_STD_PHY_BASE)
830 reg -= 0x10;
831
832 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
833 }
834
835 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
836 {
837 if (reg == 0x1f) {
838 tp->ocp_base = value << 4;
839 return;
840 }
841
842 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
843 }
844
845 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
846 {
847 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
848 }
849
850 DECLARE_RTL_COND(rtl_phyar_cond)
851 {
852 return RTL_R32(tp, PHYAR) & 0x80000000;
853 }
854
855 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
856 {
857 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
858
859 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
860 /*
861 * According to hardware specs a 20us delay is required after write
862 * complete indication, but before sending next command.
863 */
864 udelay(20);
865 }
866
867 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
868 {
869 int value;
870
871 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
872
873 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
874 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
875
876 /*
877 * According to hardware specs a 20us delay is required after read
878 * complete indication, but before sending next command.
879 */
880 udelay(20);
881
882 return value;
883 }
884
885 DECLARE_RTL_COND(rtl_ocpar_cond)
886 {
887 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
888 }
889
890 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
891 {
892 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
893 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
894 RTL_W32(tp, EPHY_RXER_NUM, 0);
895
896 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
897 }
898
899 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
900 {
901 r8168dp_1_mdio_access(tp, reg,
902 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
903 }
904
905 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
906 {
907 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
908
909 mdelay(1);
910 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
911 RTL_W32(tp, EPHY_RXER_NUM, 0);
912
913 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
914 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
915 }
916
917 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
918
919 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
920 {
921 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
922 }
923
924 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
925 {
926 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
927 }
928
929 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
930 {
931 r8168dp_2_mdio_start(tp);
932
933 r8169_mdio_write(tp, reg, value);
934
935 r8168dp_2_mdio_stop(tp);
936 }
937
938 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
939 {
940 int value;
941
942 /* Work around issue with chip reporting wrong PHY ID */
943 if (reg == MII_PHYSID2)
944 return 0xc912;
945
946 r8168dp_2_mdio_start(tp);
947
948 value = r8169_mdio_read(tp, reg);
949
950 r8168dp_2_mdio_stop(tp);
951
952 return value;
953 }
954
955 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
956 {
957 switch (tp->mac_version) {
958 case RTL_GIGA_MAC_VER_27:
959 r8168dp_1_mdio_write(tp, location, val);
960 break;
961 case RTL_GIGA_MAC_VER_28:
962 case RTL_GIGA_MAC_VER_31:
963 r8168dp_2_mdio_write(tp, location, val);
964 break;
965 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
966 r8168g_mdio_write(tp, location, val);
967 break;
968 default:
969 r8169_mdio_write(tp, location, val);
970 break;
971 }
972 }
973
974 static int rtl_readphy(struct rtl8169_private *tp, int location)
975 {
976 switch (tp->mac_version) {
977 case RTL_GIGA_MAC_VER_27:
978 return r8168dp_1_mdio_read(tp, location);
979 case RTL_GIGA_MAC_VER_28:
980 case RTL_GIGA_MAC_VER_31:
981 return r8168dp_2_mdio_read(tp, location);
982 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
983 return r8168g_mdio_read(tp, location);
984 default:
985 return r8169_mdio_read(tp, location);
986 }
987 }
988
989 DECLARE_RTL_COND(rtl_ephyar_cond)
990 {
991 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
992 }
993
994 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
995 {
996 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
997 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
998
999 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1000
1001 udelay(10);
1002 }
1003
1004 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1005 {
1006 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1007
1008 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1009 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1010 }
1011
1012 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
1013 {
1014 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */
1015 if (tp->mac_version == RTL_GIGA_MAC_VER_52 && type == ERIAR_OOB)
1016 *cmd |= 0x7f0 << 18;
1017 }
1018
1019 DECLARE_RTL_COND(rtl_eriar_cond)
1020 {
1021 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1022 }
1023
1024 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1025 u32 val, int type)
1026 {
1027 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;
1028
1029 BUG_ON((addr & 3) || (mask == 0));
1030 RTL_W32(tp, ERIDR, val);
1031 r8168fp_adjust_ocp_cmd(tp, &cmd, type);
1032 RTL_W32(tp, ERIAR, cmd);
1033
1034 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1035 }
1036
1037 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1038 u32 val)
1039 {
1040 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1041 }
1042
1043 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1044 {
1045 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;
1046
1047 r8168fp_adjust_ocp_cmd(tp, &cmd, type);
1048 RTL_W32(tp, ERIAR, cmd);
1049
1050 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1051 RTL_R32(tp, ERIDR) : ~0;
1052 }
1053
1054 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1055 {
1056 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1057 }
1058
1059 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
1060 {
1061 u32 val = rtl_eri_read(tp, addr);
1062
1063 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);
1064 }
1065
1066 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
1067 {
1068 rtl_w0w1_eri(tp, addr, p, 0);
1069 }
1070
1071 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
1072 {
1073 rtl_w0w1_eri(tp, addr, 0, m);
1074 }
1075
1076 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)
1077 {
1078 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
1079 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1080 RTL_R32(tp, OCPDR) : ~0;
1081 }
1082
1083 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)
1084 {
1085 return _rtl_eri_read(tp, reg, ERIAR_OOB);
1086 }
1087
1088 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1089 u32 data)
1090 {
1091 RTL_W32(tp, OCPDR, data);
1092 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1093 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1094 }
1095
1096 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1097 u32 data)
1098 {
1099 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1100 data, ERIAR_OOB);
1101 }
1102
1103 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1104 {
1105 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1106
1107 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1108 }
1109
1110 #define OOB_CMD_RESET 0x00
1111 #define OOB_CMD_DRIVER_START 0x05
1112 #define OOB_CMD_DRIVER_STOP 0x06
1113
1114 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1115 {
1116 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1117 }
1118
1119 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1120 {
1121 u16 reg;
1122
1123 reg = rtl8168_get_ocp_reg(tp);
1124
1125 return r8168dp_ocp_read(tp, reg) & 0x00000800;
1126 }
1127
1128 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1129 {
1130 return r8168ep_ocp_read(tp, 0x124) & 0x00000001;
1131 }
1132
1133 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1134 {
1135 return RTL_R8(tp, IBISR0) & 0x20;
1136 }
1137
1138 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1139 {
1140 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1141 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);
1142 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1143 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1144 }
1145
1146 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1147 {
1148 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1149 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1150 }
1151
1152 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1153 {
1154 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1155 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1156 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1157 }
1158
1159 static void rtl8168_driver_start(struct rtl8169_private *tp)
1160 {
1161 switch (tp->mac_version) {
1162 case RTL_GIGA_MAC_VER_27:
1163 case RTL_GIGA_MAC_VER_28:
1164 case RTL_GIGA_MAC_VER_31:
1165 rtl8168dp_driver_start(tp);
1166 break;
1167 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
1168 rtl8168ep_driver_start(tp);
1169 break;
1170 default:
1171 BUG();
1172 break;
1173 }
1174 }
1175
1176 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1177 {
1178 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1179 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1180 }
1181
1182 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1183 {
1184 rtl8168ep_stop_cmac(tp);
1185 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1186 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1187 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1188 }
1189
1190 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1191 {
1192 switch (tp->mac_version) {
1193 case RTL_GIGA_MAC_VER_27:
1194 case RTL_GIGA_MAC_VER_28:
1195 case RTL_GIGA_MAC_VER_31:
1196 rtl8168dp_driver_stop(tp);
1197 break;
1198 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
1199 rtl8168ep_driver_stop(tp);
1200 break;
1201 default:
1202 BUG();
1203 break;
1204 }
1205 }
1206
1207 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1208 {
1209 u16 reg = rtl8168_get_ocp_reg(tp);
1210
1211 return !!(r8168dp_ocp_read(tp, reg) & 0x00008000);
1212 }
1213
1214 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1215 {
1216 return r8168ep_ocp_read(tp, 0x128) & 0x00000001;
1217 }
1218
1219 static bool r8168_check_dash(struct rtl8169_private *tp)
1220 {
1221 switch (tp->mac_version) {
1222 case RTL_GIGA_MAC_VER_27:
1223 case RTL_GIGA_MAC_VER_28:
1224 case RTL_GIGA_MAC_VER_31:
1225 return r8168dp_check_dash(tp);
1226 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
1227 return r8168ep_check_dash(tp);
1228 default:
1229 return false;
1230 }
1231 }
1232
1233 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1234 {
1235 rtl_eri_clear_bits(tp, 0xdc, BIT(0));
1236 rtl_eri_set_bits(tp, 0xdc, BIT(0));
1237 }
1238
1239 DECLARE_RTL_COND(rtl_efusear_cond)
1240 {
1241 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1242 }
1243
1244 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1245 {
1246 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1247
1248 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1249 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1250 }
1251
1252 static u32 rtl_get_events(struct rtl8169_private *tp)
1253 {
1254 if (rtl_is_8125(tp))
1255 return RTL_R32(tp, IntrStatus_8125);
1256 else
1257 return RTL_R16(tp, IntrStatus);
1258 }
1259
1260 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1261 {
1262 if (rtl_is_8125(tp))
1263 RTL_W32(tp, IntrStatus_8125, bits);
1264 else
1265 RTL_W16(tp, IntrStatus, bits);
1266 }
1267
1268 static void rtl_irq_disable(struct rtl8169_private *tp)
1269 {
1270 if (rtl_is_8125(tp))
1271 RTL_W32(tp, IntrMask_8125, 0);
1272 else
1273 RTL_W16(tp, IntrMask, 0);
1274 }
1275
1276 static void rtl_irq_enable(struct rtl8169_private *tp)
1277 {
1278 if (rtl_is_8125(tp))
1279 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1280 else
1281 RTL_W16(tp, IntrMask, tp->irq_mask);
1282 }
1283
1284 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1285 {
1286 rtl_irq_disable(tp);
1287 rtl_ack_events(tp, 0xffffffff);
1288 rtl_pci_commit(tp);
1289 }
1290
1291 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1292 {
1293 struct phy_device *phydev = tp->phydev;
1294
1295 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1296 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1297 if (phydev->speed == SPEED_1000) {
1298 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1299 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1300 } else if (phydev->speed == SPEED_100) {
1301 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1302 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1303 } else {
1304 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1305 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1306 }
1307 rtl_reset_packet_filter(tp);
1308 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1309 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1310 if (phydev->speed == SPEED_1000) {
1311 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1312 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1313 } else {
1314 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1315 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1316 }
1317 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1318 if (phydev->speed == SPEED_10) {
1319 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1320 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1321 } else {
1322 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1323 }
1324 }
1325 }
1326
1327 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1328
1329 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1330 {
1331 struct rtl8169_private *tp = netdev_priv(dev);
1332
1333 wol->supported = WAKE_ANY;
1334 wol->wolopts = tp->saved_wolopts;
1335 }
1336
1337 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1338 {
1339 static const struct {
1340 u32 opt;
1341 u16 reg;
1342 u8 mask;
1343 } cfg[] = {
1344 { WAKE_PHY, Config3, LinkUp },
1345 { WAKE_UCAST, Config5, UWF },
1346 { WAKE_BCAST, Config5, BWF },
1347 { WAKE_MCAST, Config5, MWF },
1348 { WAKE_ANY, Config5, LanWake },
1349 { WAKE_MAGIC, Config3, MagicPacket }
1350 };
1351 unsigned int i, tmp = ARRAY_SIZE(cfg);
1352 u8 options;
1353
1354 rtl_unlock_config_regs(tp);
1355
1356 if (rtl_is_8168evl_up(tp)) {
1357 tmp--;
1358 if (wolopts & WAKE_MAGIC)
1359 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);
1360 else
1361 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);
1362 } else if (rtl_is_8125(tp)) {
1363 tmp--;
1364 if (wolopts & WAKE_MAGIC)
1365 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1366 else
1367 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1368 }
1369
1370 for (i = 0; i < tmp; i++) {
1371 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1372 if (wolopts & cfg[i].opt)
1373 options |= cfg[i].mask;
1374 RTL_W8(tp, cfg[i].reg, options);
1375 }
1376
1377 switch (tp->mac_version) {
1378 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1379 options = RTL_R8(tp, Config1) & ~PMEnable;
1380 if (wolopts)
1381 options |= PMEnable;
1382 RTL_W8(tp, Config1, options);
1383 break;
1384 case RTL_GIGA_MAC_VER_34:
1385 case RTL_GIGA_MAC_VER_37:
1386 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1387 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1388 if (wolopts)
1389 options |= PME_SIGNAL;
1390 RTL_W8(tp, Config2, options);
1391 break;
1392 default:
1393 break;
1394 }
1395
1396 rtl_lock_config_regs(tp);
1397
1398 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1399 tp->dev->wol_enabled = wolopts ? 1 : 0;
1400 }
1401
1402 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1403 {
1404 struct rtl8169_private *tp = netdev_priv(dev);
1405
1406 if (wol->wolopts & ~WAKE_ANY)
1407 return -EINVAL;
1408
1409 tp->saved_wolopts = wol->wolopts;
1410 __rtl8169_set_wol(tp, tp->saved_wolopts);
1411
1412 return 0;
1413 }
1414
1415 static void rtl8169_get_drvinfo(struct net_device *dev,
1416 struct ethtool_drvinfo *info)
1417 {
1418 struct rtl8169_private *tp = netdev_priv(dev);
1419 struct rtl_fw *rtl_fw = tp->rtl_fw;
1420
1421 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1422 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1423 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1424 if (rtl_fw)
1425 strlcpy(info->fw_version, rtl_fw->version,
1426 sizeof(info->fw_version));
1427 }
1428
1429 static int rtl8169_get_regs_len(struct net_device *dev)
1430 {
1431 return R8169_REGS_SIZE;
1432 }
1433
1434 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1435 netdev_features_t features)
1436 {
1437 struct rtl8169_private *tp = netdev_priv(dev);
1438
1439 if (dev->mtu > TD_MSS_MAX)
1440 features &= ~NETIF_F_ALL_TSO;
1441
1442 if (dev->mtu > ETH_DATA_LEN &&
1443 tp->mac_version > RTL_GIGA_MAC_VER_06)
1444 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
1445
1446 return features;
1447 }
1448
1449 static void rtl_set_rx_config_features(struct rtl8169_private *tp,
1450 netdev_features_t features)
1451 {
1452 u32 rx_config = RTL_R32(tp, RxConfig);
1453
1454 if (features & NETIF_F_RXALL)
1455 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK;
1456 else
1457 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK;
1458
1459 if (rtl_is_8125(tp)) {
1460 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1461 rx_config |= RX_VLAN_8125;
1462 else
1463 rx_config &= ~RX_VLAN_8125;
1464 }
1465
1466 RTL_W32(tp, RxConfig, rx_config);
1467 }
1468
1469 static int rtl8169_set_features(struct net_device *dev,
1470 netdev_features_t features)
1471 {
1472 struct rtl8169_private *tp = netdev_priv(dev);
1473
1474 rtl_set_rx_config_features(tp, features);
1475
1476 if (features & NETIF_F_RXCSUM)
1477 tp->cp_cmd |= RxChkSum;
1478 else
1479 tp->cp_cmd &= ~RxChkSum;
1480
1481 if (!rtl_is_8125(tp)) {
1482 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1483 tp->cp_cmd |= RxVlan;
1484 else
1485 tp->cp_cmd &= ~RxVlan;
1486 }
1487
1488 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1489 rtl_pci_commit(tp);
1490
1491 return 0;
1492 }
1493
1494 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1495 {
1496 return (skb_vlan_tag_present(skb)) ?
1497 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1498 }
1499
1500 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1501 {
1502 u32 opts2 = le32_to_cpu(desc->opts2);
1503
1504 if (opts2 & RxVlanTag)
1505 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1506 }
1507
1508 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1509 void *p)
1510 {
1511 struct rtl8169_private *tp = netdev_priv(dev);
1512 u32 __iomem *data = tp->mmio_addr;
1513 u32 *dw = p;
1514 int i;
1515
1516 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1517 memcpy_fromio(dw++, data++, 4);
1518 }
1519
1520 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1521 "tx_packets",
1522 "rx_packets",
1523 "tx_errors",
1524 "rx_errors",
1525 "rx_missed",
1526 "align_errors",
1527 "tx_single_collisions",
1528 "tx_multi_collisions",
1529 "unicast",
1530 "broadcast",
1531 "multicast",
1532 "tx_aborted",
1533 "tx_underrun",
1534 };
1535
1536 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1537 {
1538 switch (sset) {
1539 case ETH_SS_STATS:
1540 return ARRAY_SIZE(rtl8169_gstrings);
1541 default:
1542 return -EOPNOTSUPP;
1543 }
1544 }
1545
1546 DECLARE_RTL_COND(rtl_counters_cond)
1547 {
1548 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1549 }
1550
1551 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1552 {
1553 dma_addr_t paddr = tp->counters_phys_addr;
1554 u32 cmd;
1555
1556 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1557 rtl_pci_commit(tp);
1558 cmd = (u64)paddr & DMA_BIT_MASK(32);
1559 RTL_W32(tp, CounterAddrLow, cmd);
1560 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1561
1562 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1563 }
1564
1565 static void rtl8169_reset_counters(struct rtl8169_private *tp)
1566 {
1567 /*
1568 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1569 * tally counters.
1570 */
1571 if (tp->mac_version >= RTL_GIGA_MAC_VER_19)
1572 rtl8169_do_counters(tp, CounterReset);
1573 }
1574
1575 static void rtl8169_update_counters(struct rtl8169_private *tp)
1576 {
1577 u8 val = RTL_R8(tp, ChipCmd);
1578
1579 /*
1580 * Some chips are unable to dump tally counters when the receiver
1581 * is disabled. If 0xff chip may be in a PCI power-save state.
1582 */
1583 if (val & CmdRxEnb && val != 0xff)
1584 rtl8169_do_counters(tp, CounterDump);
1585 }
1586
1587 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1588 {
1589 struct rtl8169_counters *counters = tp->counters;
1590
1591 /*
1592 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1593 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1594 * reset by a power cycle, while the counter values collected by the
1595 * driver are reset at every driver unload/load cycle.
1596 *
1597 * To make sure the HW values returned by @get_stats64 match the SW
1598 * values, we collect the initial values at first open(*) and use them
1599 * as offsets to normalize the values returned by @get_stats64.
1600 *
1601 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1602 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1603 * set at open time by rtl_hw_start.
1604 */
1605
1606 if (tp->tc_offset.inited)
1607 return;
1608
1609 rtl8169_reset_counters(tp);
1610 rtl8169_update_counters(tp);
1611
1612 tp->tc_offset.tx_errors = counters->tx_errors;
1613 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1614 tp->tc_offset.tx_aborted = counters->tx_aborted;
1615 tp->tc_offset.rx_missed = counters->rx_missed;
1616 tp->tc_offset.inited = true;
1617 }
1618
1619 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1620 struct ethtool_stats *stats, u64 *data)
1621 {
1622 struct rtl8169_private *tp = netdev_priv(dev);
1623 struct rtl8169_counters *counters;
1624
1625 counters = tp->counters;
1626 rtl8169_update_counters(tp);
1627
1628 data[0] = le64_to_cpu(counters->tx_packets);
1629 data[1] = le64_to_cpu(counters->rx_packets);
1630 data[2] = le64_to_cpu(counters->tx_errors);
1631 data[3] = le32_to_cpu(counters->rx_errors);
1632 data[4] = le16_to_cpu(counters->rx_missed);
1633 data[5] = le16_to_cpu(counters->align_errors);
1634 data[6] = le32_to_cpu(counters->tx_one_collision);
1635 data[7] = le32_to_cpu(counters->tx_multi_collision);
1636 data[8] = le64_to_cpu(counters->rx_unicast);
1637 data[9] = le64_to_cpu(counters->rx_broadcast);
1638 data[10] = le32_to_cpu(counters->rx_multicast);
1639 data[11] = le16_to_cpu(counters->tx_aborted);
1640 data[12] = le16_to_cpu(counters->tx_underun);
1641 }
1642
1643 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1644 {
1645 switch(stringset) {
1646 case ETH_SS_STATS:
1647 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1648 break;
1649 }
1650 }
1651
1652 /*
1653 * Interrupt coalescing
1654 *
1655 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1656 * > 8169, 8168 and 810x line of chipsets
1657 *
1658 * 8169, 8168, and 8136(810x) serial chipsets support it.
1659 *
1660 * > 2 - the Tx timer unit at gigabit speed
1661 *
1662 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1663 * (0xe0) bit 1 and bit 0.
1664 *
1665 * For 8169
1666 * bit[1:0] \ speed 1000M 100M 10M
1667 * 0 0 320ns 2.56us 40.96us
1668 * 0 1 2.56us 20.48us 327.7us
1669 * 1 0 5.12us 40.96us 655.4us
1670 * 1 1 10.24us 81.92us 1.31ms
1671 *
1672 * For the other
1673 * bit[1:0] \ speed 1000M 100M 10M
1674 * 0 0 5us 2.56us 40.96us
1675 * 0 1 40us 20.48us 327.7us
1676 * 1 0 80us 40.96us 655.4us
1677 * 1 1 160us 81.92us 1.31ms
1678 */
1679
1680 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1681 struct rtl_coalesce_info {
1682 u32 speed;
1683 u32 scale_nsecs[4];
1684 };
1685
1686 /* produce array with base delay *1, *8, *8*2, *8*2*2 */
1687 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) }
1688
1689 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1690 { SPEED_1000, COALESCE_DELAY(320) },
1691 { SPEED_100, COALESCE_DELAY(2560) },
1692 { SPEED_10, COALESCE_DELAY(40960) },
1693 { 0 },
1694 };
1695
1696 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1697 { SPEED_1000, COALESCE_DELAY(5000) },
1698 { SPEED_100, COALESCE_DELAY(2560) },
1699 { SPEED_10, COALESCE_DELAY(40960) },
1700 { 0 },
1701 };
1702 #undef COALESCE_DELAY
1703
1704 /* get rx/tx scale vector corresponding to current speed */
1705 static const struct rtl_coalesce_info *
1706 rtl_coalesce_info(struct rtl8169_private *tp)
1707 {
1708 const struct rtl_coalesce_info *ci;
1709
1710 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1711 ci = rtl_coalesce_info_8169;
1712 else
1713 ci = rtl_coalesce_info_8168_8136;
1714
1715 /* if speed is unknown assume highest one */
1716 if (tp->phydev->speed == SPEED_UNKNOWN)
1717 return ci;
1718
1719 for (; ci->speed; ci++) {
1720 if (tp->phydev->speed == ci->speed)
1721 return ci;
1722 }
1723
1724 return ERR_PTR(-ELNRNG);
1725 }
1726
1727 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1728 {
1729 struct rtl8169_private *tp = netdev_priv(dev);
1730 const struct rtl_coalesce_info *ci;
1731 u32 scale, c_us, c_fr;
1732 u16 intrmit;
1733
1734 if (rtl_is_8125(tp))
1735 return -EOPNOTSUPP;
1736
1737 memset(ec, 0, sizeof(*ec));
1738
1739 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1740 ci = rtl_coalesce_info(tp);
1741 if (IS_ERR(ci))
1742 return PTR_ERR(ci);
1743
1744 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];
1745
1746 intrmit = RTL_R16(tp, IntrMitigate);
1747
1748 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit);
1749 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1750
1751 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit);
1752 /* ethtool_coalesce states usecs and max_frames must not both be 0 */
1753 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1754
1755 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit);
1756 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1757
1758 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit);
1759 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1760
1761 return 0;
1762 }
1763
1764 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
1765 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,
1766 u16 *cp01)
1767 {
1768 const struct rtl_coalesce_info *ci;
1769 u16 i;
1770
1771 ci = rtl_coalesce_info(tp);
1772 if (IS_ERR(ci))
1773 return PTR_ERR(ci);
1774
1775 for (i = 0; i < 4; i++) {
1776 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) {
1777 *cp01 = i;
1778 return ci->scale_nsecs[i];
1779 }
1780 }
1781
1782 return -ERANGE;
1783 }
1784
1785 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1786 {
1787 struct rtl8169_private *tp = netdev_priv(dev);
1788 u32 tx_fr = ec->tx_max_coalesced_frames;
1789 u32 rx_fr = ec->rx_max_coalesced_frames;
1790 u32 coal_usec_max, units;
1791 u16 w = 0, cp01 = 0;
1792 int scale;
1793
1794 if (rtl_is_8125(tp))
1795 return -EOPNOTSUPP;
1796
1797 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX)
1798 return -ERANGE;
1799
1800 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs);
1801 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);
1802 if (scale < 0)
1803 return scale;
1804
1805 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it
1806 * not only when usecs=0 because of e.g. the following scenario:
1807 *
1808 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1809 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1810 * - then user does `ethtool -C eth0 rx-usecs 100`
1811 *
1812 * Since ethtool sends to kernel whole ethtool_coalesce settings,
1813 * if we want to ignore rx_frames then it has to be set to 0.
1814 */
1815 if (rx_fr == 1)
1816 rx_fr = 0;
1817 if (tx_fr == 1)
1818 tx_fr = 0;
1819
1820 /* HW requires time limit to be set if frame limit is set */
1821 if ((tx_fr && !ec->tx_coalesce_usecs) ||
1822 (rx_fr && !ec->rx_coalesce_usecs))
1823 return -EINVAL;
1824
1825 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4));
1826 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4));
1827
1828 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale);
1829 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units);
1830 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale);
1831 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units);
1832
1833 RTL_W16(tp, IntrMitigate, w);
1834
1835 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */
1836 if (rtl_is_8168evl_up(tp)) {
1837 if (!rx_fr && !tx_fr)
1838 /* disable packet counter */
1839 tp->cp_cmd |= PktCntrDisable;
1840 else
1841 tp->cp_cmd &= ~PktCntrDisable;
1842 }
1843
1844 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1845 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1846 rtl_pci_commit(tp);
1847
1848 return 0;
1849 }
1850
1851 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
1852 {
1853 struct rtl8169_private *tp = netdev_priv(dev);
1854
1855 if (!rtl_supports_eee(tp))
1856 return -EOPNOTSUPP;
1857
1858 return phy_ethtool_get_eee(tp->phydev, data);
1859 }
1860
1861 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
1862 {
1863 struct rtl8169_private *tp = netdev_priv(dev);
1864 int ret;
1865
1866 if (!rtl_supports_eee(tp))
1867 return -EOPNOTSUPP;
1868
1869 ret = phy_ethtool_set_eee(tp->phydev, data);
1870
1871 if (!ret)
1872 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,
1873 MDIO_AN_EEE_ADV);
1874 return ret;
1875 }
1876
1877 static const struct ethtool_ops rtl8169_ethtool_ops = {
1878 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
1879 ETHTOOL_COALESCE_MAX_FRAMES,
1880 .get_drvinfo = rtl8169_get_drvinfo,
1881 .get_regs_len = rtl8169_get_regs_len,
1882 .get_link = ethtool_op_get_link,
1883 .get_coalesce = rtl_get_coalesce,
1884 .set_coalesce = rtl_set_coalesce,
1885 .get_regs = rtl8169_get_regs,
1886 .get_wol = rtl8169_get_wol,
1887 .set_wol = rtl8169_set_wol,
1888 .get_strings = rtl8169_get_strings,
1889 .get_sset_count = rtl8169_get_sset_count,
1890 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1891 .get_ts_info = ethtool_op_get_ts_info,
1892 .nway_reset = phy_ethtool_nway_reset,
1893 .get_eee = rtl8169_get_eee,
1894 .set_eee = rtl8169_set_eee,
1895 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1896 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1897 };
1898
1899 static void rtl_enable_eee(struct rtl8169_private *tp)
1900 {
1901 struct phy_device *phydev = tp->phydev;
1902 int adv;
1903
1904 /* respect EEE advertisement the user may have set */
1905 if (tp->eee_adv >= 0)
1906 adv = tp->eee_adv;
1907 else
1908 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1909
1910 if (adv >= 0)
1911 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv);
1912 }
1913
1914 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii)
1915 {
1916 /*
1917 * The driver currently handles the 8168Bf and the 8168Be identically
1918 * but they can be identified more specifically through the test below
1919 * if needed:
1920 *
1921 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1922 *
1923 * Same thing for the 8101Eb and the 8101Ec:
1924 *
1925 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1926 */
1927 static const struct rtl_mac_info {
1928 u16 mask;
1929 u16 val;
1930 enum mac_version ver;
1931 } mac_info[] = {
1932 /* 8125B family. */
1933 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 },
1934
1935 /* 8125A family. */
1936 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 },
1937 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 },
1938
1939 /* RTL8117 */
1940 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 },
1941
1942 /* 8168EP family. */
1943 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
1944 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
1945 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
1946
1947 /* 8168H family. */
1948 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
1949 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
1950
1951 /* 8168G family. */
1952 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
1953 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
1954 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
1955 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
1956
1957 /* 8168F family. */
1958 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
1959 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
1960 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
1961
1962 /* 8168E family. */
1963 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
1964 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
1965 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
1966
1967 /* 8168D family. */
1968 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
1969 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
1970
1971 /* 8168DP family. */
1972 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
1973 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
1974 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
1975
1976 /* 8168C family. */
1977 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
1978 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
1979 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
1980 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
1981 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
1982 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
1983 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
1984
1985 /* 8168B family. */
1986 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
1987 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
1988 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
1989
1990 /* 8101 family. */
1991 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
1992 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
1993 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
1994 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
1995 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
1996 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
1997 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
1998 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
1999 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2000 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 },
2001 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2002 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2003 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2004 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2005 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2006 /* FIXME: where did these entries come from ? -- FR */
2007 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_13 },
2008 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_13 },
2009
2010 /* 8110 family. */
2011 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2012 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2013 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2014 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2015 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2016
2017 /* Catch-all */
2018 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
2019 };
2020 const struct rtl_mac_info *p = mac_info;
2021 enum mac_version ver;
2022
2023 while ((xid & p->mask) != p->val)
2024 p++;
2025 ver = p->ver;
2026
2027 if (ver != RTL_GIGA_MAC_NONE && !gmii) {
2028 if (ver == RTL_GIGA_MAC_VER_42)
2029 ver = RTL_GIGA_MAC_VER_43;
2030 else if (ver == RTL_GIGA_MAC_VER_45)
2031 ver = RTL_GIGA_MAC_VER_47;
2032 else if (ver == RTL_GIGA_MAC_VER_46)
2033 ver = RTL_GIGA_MAC_VER_48;
2034 }
2035
2036 return ver;
2037 }
2038
2039 static void rtl_release_firmware(struct rtl8169_private *tp)
2040 {
2041 if (tp->rtl_fw) {
2042 rtl_fw_release_firmware(tp->rtl_fw);
2043 kfree(tp->rtl_fw);
2044 tp->rtl_fw = NULL;
2045 }
2046 }
2047
2048 void r8169_apply_firmware(struct rtl8169_private *tp)
2049 {
2050 int val;
2051
2052 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2053 if (tp->rtl_fw) {
2054 rtl_fw_write_firmware(tp, tp->rtl_fw);
2055 /* At least one firmware doesn't reset tp->ocp_base. */
2056 tp->ocp_base = OCP_STD_PHY_BASE;
2057
2058 /* PHY soft reset may still be in progress */
2059 phy_read_poll_timeout(tp->phydev, MII_BMCR, val,
2060 !(val & BMCR_RESET),
2061 50000, 600000, true);
2062 }
2063 }
2064
2065 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2066 {
2067 /* Adjust EEE LED frequency */
2068 if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2069 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2070
2071 rtl_eri_set_bits(tp, 0x1b0, 0x0003);
2072 }
2073
2074 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)
2075 {
2076 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2077 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2078 }
2079
2080 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp)
2081 {
2082 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20);
2083 }
2084
2085 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)
2086 {
2087 rtl8125_set_eee_txidle_timer(tp);
2088 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2089 }
2090
2091 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
2092 {
2093 const u16 w[] = {
2094 addr[0] | (addr[1] << 8),
2095 addr[2] | (addr[3] << 8),
2096 addr[4] | (addr[5] << 8)
2097 };
2098
2099 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
2100 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
2101 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
2102 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
2103 }
2104
2105 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
2106 {
2107 u16 data1, data2, ioffset;
2108
2109 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
2110 data1 = r8168_mac_ocp_read(tp, 0xdd02);
2111 data2 = r8168_mac_ocp_read(tp, 0xdd00);
2112
2113 ioffset = (data2 >> 1) & 0x7ff8;
2114 ioffset |= data2 & 0x0007;
2115 if (data1 & BIT(7))
2116 ioffset |= BIT(15);
2117
2118 return ioffset;
2119 }
2120
2121 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
2122 {
2123 set_bit(flag, tp->wk.flags);
2124 schedule_work(&tp->wk.work);
2125 }
2126
2127 static void rtl8169_init_phy(struct rtl8169_private *tp)
2128 {
2129 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);
2130
2131 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2132 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2133 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2134 /* set undocumented MAC Reg C+CR Offset 0x82h */
2135 RTL_W8(tp, 0x82, 0x01);
2136 }
2137
2138 if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
2139 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
2140 tp->pci_dev->subsystem_device == 0xe000)
2141 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);
2142
2143 /* We may have called phy_speed_down before */
2144 phy_speed_up(tp->phydev);
2145
2146 if (rtl_supports_eee(tp))
2147 rtl_enable_eee(tp);
2148
2149 genphy_soft_reset(tp->phydev);
2150 }
2151
2152 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2153 {
2154 rtl_unlock_config_regs(tp);
2155
2156 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
2157 rtl_pci_commit(tp);
2158
2159 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
2160 rtl_pci_commit(tp);
2161
2162 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
2163 rtl_rar_exgmac_set(tp, addr);
2164
2165 rtl_lock_config_regs(tp);
2166 }
2167
2168 static int rtl_set_mac_address(struct net_device *dev, void *p)
2169 {
2170 struct rtl8169_private *tp = netdev_priv(dev);
2171 int ret;
2172
2173 ret = eth_mac_addr(dev, p);
2174 if (ret)
2175 return ret;
2176
2177 rtl_rar_set(tp, dev->dev_addr);
2178
2179 return 0;
2180 }
2181
2182 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
2183 {
2184 switch (tp->mac_version) {
2185 case RTL_GIGA_MAC_VER_25:
2186 case RTL_GIGA_MAC_VER_26:
2187 case RTL_GIGA_MAC_VER_29:
2188 case RTL_GIGA_MAC_VER_30:
2189 case RTL_GIGA_MAC_VER_32:
2190 case RTL_GIGA_MAC_VER_33:
2191 case RTL_GIGA_MAC_VER_34:
2192 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_63:
2193 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2194 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2195 break;
2196 default:
2197 break;
2198 }
2199 }
2200
2201 static void rtl_pll_power_down(struct rtl8169_private *tp)
2202 {
2203 if (r8168_check_dash(tp))
2204 return;
2205
2206 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
2207 tp->mac_version == RTL_GIGA_MAC_VER_33)
2208 rtl_ephy_write(tp, 0x19, 0xff64);
2209
2210 if (device_may_wakeup(tp_to_dev(tp))) {
2211 phy_speed_down(tp->phydev, false);
2212 rtl_wol_suspend_quirk(tp);
2213 return;
2214 }
2215
2216 switch (tp->mac_version) {
2217 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
2218 case RTL_GIGA_MAC_VER_37:
2219 case RTL_GIGA_MAC_VER_39:
2220 case RTL_GIGA_MAC_VER_43:
2221 case RTL_GIGA_MAC_VER_44:
2222 case RTL_GIGA_MAC_VER_45:
2223 case RTL_GIGA_MAC_VER_46:
2224 case RTL_GIGA_MAC_VER_47:
2225 case RTL_GIGA_MAC_VER_48:
2226 case RTL_GIGA_MAC_VER_50 ... RTL_GIGA_MAC_VER_63:
2227 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
2228 break;
2229 case RTL_GIGA_MAC_VER_40:
2230 case RTL_GIGA_MAC_VER_41:
2231 case RTL_GIGA_MAC_VER_49:
2232 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);
2233 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
2234 break;
2235 default:
2236 break;
2237 }
2238 }
2239
2240 static void rtl_pll_power_up(struct rtl8169_private *tp)
2241 {
2242 switch (tp->mac_version) {
2243 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
2244 case RTL_GIGA_MAC_VER_37:
2245 case RTL_GIGA_MAC_VER_39:
2246 case RTL_GIGA_MAC_VER_43:
2247 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
2248 break;
2249 case RTL_GIGA_MAC_VER_44:
2250 case RTL_GIGA_MAC_VER_45:
2251 case RTL_GIGA_MAC_VER_46:
2252 case RTL_GIGA_MAC_VER_47:
2253 case RTL_GIGA_MAC_VER_48:
2254 case RTL_GIGA_MAC_VER_50 ... RTL_GIGA_MAC_VER_63:
2255 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
2256 break;
2257 case RTL_GIGA_MAC_VER_40:
2258 case RTL_GIGA_MAC_VER_41:
2259 case RTL_GIGA_MAC_VER_49:
2260 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
2261 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);
2262 break;
2263 default:
2264 break;
2265 }
2266
2267 phy_resume(tp->phydev);
2268 }
2269
2270 static void rtl_init_rxcfg(struct rtl8169_private *tp)
2271 {
2272 switch (tp->mac_version) {
2273 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2274 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
2275 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
2276 break;
2277 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
2278 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2279 case RTL_GIGA_MAC_VER_38:
2280 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
2281 break;
2282 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
2283 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
2284 break;
2285 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63:
2286 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
2287 break;
2288 default:
2289 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
2290 break;
2291 }
2292 }
2293
2294 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2295 {
2296 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
2297 }
2298
2299 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
2300 {
2301 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2302 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
2303 }
2304
2305 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
2306 {
2307 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2308 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
2309 }
2310
2311 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
2312 {
2313 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2314 }
2315
2316 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
2317 {
2318 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2319 }
2320
2321 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
2322 {
2323 RTL_W8(tp, MaxTxPacketSize, 0x3f);
2324 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2325 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
2326 }
2327
2328 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
2329 {
2330 RTL_W8(tp, MaxTxPacketSize, 0x0c);
2331 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2332 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
2333 }
2334
2335 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
2336 {
2337 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
2338 }
2339
2340 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
2341 {
2342 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
2343 }
2344
2345 static void rtl_jumbo_config(struct rtl8169_private *tp)
2346 {
2347 bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
2348
2349 rtl_unlock_config_regs(tp);
2350 switch (tp->mac_version) {
2351 case RTL_GIGA_MAC_VER_12:
2352 case RTL_GIGA_MAC_VER_17:
2353 if (jumbo) {
2354 pcie_set_readrq(tp->pci_dev, 512);
2355 r8168b_1_hw_jumbo_enable(tp);
2356 } else {
2357 r8168b_1_hw_jumbo_disable(tp);
2358 }
2359 break;
2360 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
2361 if (jumbo) {
2362 pcie_set_readrq(tp->pci_dev, 512);
2363 r8168c_hw_jumbo_enable(tp);
2364 } else {
2365 r8168c_hw_jumbo_disable(tp);
2366 }
2367 break;
2368 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
2369 if (jumbo)
2370 r8168dp_hw_jumbo_enable(tp);
2371 else
2372 r8168dp_hw_jumbo_disable(tp);
2373 break;
2374 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
2375 if (jumbo) {
2376 pcie_set_readrq(tp->pci_dev, 512);
2377 r8168e_hw_jumbo_enable(tp);
2378 } else {
2379 r8168e_hw_jumbo_disable(tp);
2380 }
2381 break;
2382 default:
2383 break;
2384 }
2385 rtl_lock_config_regs(tp);
2386
2387 if (!jumbo && pci_is_pcie(tp->pci_dev) && tp->supports_gmii)
2388 pcie_set_readrq(tp->pci_dev, 4096);
2389 }
2390
2391 DECLARE_RTL_COND(rtl_chipcmd_cond)
2392 {
2393 return RTL_R8(tp, ChipCmd) & CmdReset;
2394 }
2395
2396 static void rtl_hw_reset(struct rtl8169_private *tp)
2397 {
2398 RTL_W8(tp, ChipCmd, CmdReset);
2399
2400 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
2401 }
2402
2403 static void rtl_request_firmware(struct rtl8169_private *tp)
2404 {
2405 struct rtl_fw *rtl_fw;
2406
2407 /* firmware loaded already or no firmware available */
2408 if (tp->rtl_fw || !tp->fw_name)
2409 return;
2410
2411 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
2412 if (!rtl_fw)
2413 return;
2414
2415 rtl_fw->phy_write = rtl_writephy;
2416 rtl_fw->phy_read = rtl_readphy;
2417 rtl_fw->mac_mcu_write = mac_mcu_write;
2418 rtl_fw->mac_mcu_read = mac_mcu_read;
2419 rtl_fw->fw_name = tp->fw_name;
2420 rtl_fw->dev = tp_to_dev(tp);
2421
2422 if (rtl_fw_request_firmware(rtl_fw))
2423 kfree(rtl_fw);
2424 else
2425 tp->rtl_fw = rtl_fw;
2426 }
2427
2428 static void rtl_rx_close(struct rtl8169_private *tp)
2429 {
2430 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
2431 }
2432
2433 DECLARE_RTL_COND(rtl_npq_cond)
2434 {
2435 return RTL_R8(tp, TxPoll) & NPQ;
2436 }
2437
2438 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
2439 {
2440 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
2441 }
2442
2443 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
2444 {
2445 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
2446 }
2447
2448 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2)
2449 {
2450 /* IntrMitigate has new functionality on RTL8125 */
2451 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;
2452 }
2453
2454 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
2455 {
2456 switch (tp->mac_version) {
2457 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
2458 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);
2459 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2460 break;
2461 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
2462 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2463 break;
2464 case RTL_GIGA_MAC_VER_63:
2465 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2466 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2467 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
2468 break;
2469 default:
2470 break;
2471 }
2472 }
2473
2474 static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
2475 {
2476 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
2477 fsleep(2000);
2478 rtl_wait_txrx_fifo_empty(tp);
2479 }
2480
2481 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
2482 {
2483 u32 val = TX_DMA_BURST << TxDMAShift |
2484 InterFrameGap << TxInterFrameGapShift;
2485
2486 if (rtl_is_8168evl_up(tp))
2487 val |= TXCFG_AUTO_FIFO;
2488
2489 RTL_W32(tp, TxConfig, val);
2490 }
2491
2492 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
2493 {
2494 /* Low hurts. Let's disable the filtering. */
2495 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
2496 }
2497
2498 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
2499 {
2500 /*
2501 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2502 * register to be written before TxDescAddrLow to work.
2503 * Switching from MMIO to I/O access fixes the issue as well.
2504 */
2505 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2506 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2507 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2508 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2509 }
2510
2511 static void rtl8169_set_magic_reg(struct rtl8169_private *tp)
2512 {
2513 u32 val;
2514
2515 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2516 val = 0x000fff00;
2517 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
2518 val = 0x00ffff00;
2519 else
2520 return;
2521
2522 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
2523 val |= 0xff;
2524
2525 RTL_W32(tp, 0x7c, val);
2526 }
2527
2528 static void rtl_set_rx_mode(struct net_device *dev)
2529 {
2530 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
2531 /* Multicast hash filter */
2532 u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
2533 struct rtl8169_private *tp = netdev_priv(dev);
2534 u32 tmp;
2535
2536 if (dev->flags & IFF_PROMISC) {
2537 rx_mode |= AcceptAllPhys;
2538 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
2539 dev->flags & IFF_ALLMULTI ||
2540 tp->mac_version == RTL_GIGA_MAC_VER_35) {
2541 /* accept all multicasts */
2542 } else if (netdev_mc_empty(dev)) {
2543 rx_mode &= ~AcceptMulticast;
2544 } else {
2545 struct netdev_hw_addr *ha;
2546
2547 mc_filter[1] = mc_filter[0] = 0;
2548 netdev_for_each_mc_addr(ha, dev) {
2549 u32 bit_nr = eth_hw_addr_crc(ha) >> 26;
2550 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
2551 }
2552
2553 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
2554 tmp = mc_filter[0];
2555 mc_filter[0] = swab32(mc_filter[1]);
2556 mc_filter[1] = swab32(tmp);
2557 }
2558 }
2559
2560 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2561 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
2562
2563 tmp = RTL_R32(tp, RxConfig);
2564 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
2565 }
2566
2567 DECLARE_RTL_COND(rtl_csiar_cond)
2568 {
2569 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
2570 }
2571
2572 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
2573 {
2574 u32 func = PCI_FUNC(tp->pci_dev->devfn);
2575
2576 RTL_W32(tp, CSIDR, value);
2577 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
2578 CSIAR_BYTE_ENABLE | func << 16);
2579
2580 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
2581 }
2582
2583 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
2584 {
2585 u32 func = PCI_FUNC(tp->pci_dev->devfn);
2586
2587 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
2588 CSIAR_BYTE_ENABLE);
2589
2590 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
2591 RTL_R32(tp, CSIDR) : ~0;
2592 }
2593
2594 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
2595 {
2596 struct pci_dev *pdev = tp->pci_dev;
2597 u32 csi;
2598
2599 /* According to Realtek the value at config space address 0x070f
2600 * controls the L0s/L1 entrance latency. We try standard ECAM access
2601 * first and if it fails fall back to CSI.
2602 */
2603 if (pdev->cfg_size > 0x070f &&
2604 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
2605 return;
2606
2607 netdev_notice_once(tp->dev,
2608 "No native access to PCI extended config space, falling back to CSI\n");
2609 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
2610 rtl_csi_write(tp, 0x070c, csi | val << 24);
2611 }
2612
2613 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
2614 {
2615 rtl_csi_access_enable(tp, 0x27);
2616 }
2617
2618 struct ephy_info {
2619 unsigned int offset;
2620 u16 mask;
2621 u16 bits;
2622 };
2623
2624 static void __rtl_ephy_init(struct rtl8169_private *tp,
2625 const struct ephy_info *e, int len)
2626 {
2627 u16 w;
2628
2629 while (len-- > 0) {
2630 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
2631 rtl_ephy_write(tp, e->offset, w);
2632 e++;
2633 }
2634 }
2635
2636 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2637
2638 static void rtl_disable_clock_request(struct rtl8169_private *tp)
2639 {
2640 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
2641 PCI_EXP_LNKCTL_CLKREQ_EN);
2642 }
2643
2644 static void rtl_enable_clock_request(struct rtl8169_private *tp)
2645 {
2646 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
2647 PCI_EXP_LNKCTL_CLKREQ_EN);
2648 }
2649
2650 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
2651 {
2652 /* work around an issue when PCI reset occurs during L2/L3 state */
2653 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
2654 }
2655
2656 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
2657 {
2658 /* Don't enable ASPM in the chip if OS can't control ASPM */
2659 if (enable && tp->aspm_manageable) {
2660 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
2661 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
2662 } else {
2663 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
2664 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
2665 }
2666
2667 udelay(10);
2668 }
2669
2670 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
2671 u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
2672 {
2673 /* Usage of dynamic vs. static FIFO is controlled by bit
2674 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
2675 */
2676 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
2677 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
2678 }
2679
2680 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
2681 u8 low, u8 high)
2682 {
2683 /* FIFO thresholds for pause flow control */
2684 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
2685 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
2686 }
2687
2688 static void rtl_hw_start_8168b(struct rtl8169_private *tp)
2689 {
2690 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2691 }
2692
2693 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
2694 {
2695 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
2696
2697 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2698
2699 rtl_disable_clock_request(tp);
2700 }
2701
2702 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
2703 {
2704 static const struct ephy_info e_info_8168cp[] = {
2705 { 0x01, 0, 0x0001 },
2706 { 0x02, 0x0800, 0x1000 },
2707 { 0x03, 0, 0x0042 },
2708 { 0x06, 0x0080, 0x0000 },
2709 { 0x07, 0, 0x2000 }
2710 };
2711
2712 rtl_set_def_aspm_entry_latency(tp);
2713
2714 rtl_ephy_init(tp, e_info_8168cp);
2715
2716 __rtl_hw_start_8168cp(tp);
2717 }
2718
2719 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
2720 {
2721 rtl_set_def_aspm_entry_latency(tp);
2722
2723 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2724 }
2725
2726 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
2727 {
2728 rtl_set_def_aspm_entry_latency(tp);
2729
2730 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2731
2732 /* Magic. */
2733 RTL_W8(tp, DBG_REG, 0x20);
2734 }
2735
2736 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
2737 {
2738 static const struct ephy_info e_info_8168c_1[] = {
2739 { 0x02, 0x0800, 0x1000 },
2740 { 0x03, 0, 0x0002 },
2741 { 0x06, 0x0080, 0x0000 }
2742 };
2743
2744 rtl_set_def_aspm_entry_latency(tp);
2745
2746 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2747
2748 rtl_ephy_init(tp, e_info_8168c_1);
2749
2750 __rtl_hw_start_8168cp(tp);
2751 }
2752
2753 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
2754 {
2755 static const struct ephy_info e_info_8168c_2[] = {
2756 { 0x01, 0, 0x0001 },
2757 { 0x03, 0x0400, 0x0020 }
2758 };
2759
2760 rtl_set_def_aspm_entry_latency(tp);
2761
2762 rtl_ephy_init(tp, e_info_8168c_2);
2763
2764 __rtl_hw_start_8168cp(tp);
2765 }
2766
2767 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
2768 {
2769 rtl_hw_start_8168c_2(tp);
2770 }
2771
2772 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
2773 {
2774 rtl_set_def_aspm_entry_latency(tp);
2775
2776 __rtl_hw_start_8168cp(tp);
2777 }
2778
2779 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
2780 {
2781 rtl_set_def_aspm_entry_latency(tp);
2782
2783 rtl_disable_clock_request(tp);
2784 }
2785
2786 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
2787 {
2788 static const struct ephy_info e_info_8168d_4[] = {
2789 { 0x0b, 0x0000, 0x0048 },
2790 { 0x19, 0x0020, 0x0050 },
2791 { 0x0c, 0x0100, 0x0020 },
2792 { 0x10, 0x0004, 0x0000 },
2793 };
2794
2795 rtl_set_def_aspm_entry_latency(tp);
2796
2797 rtl_ephy_init(tp, e_info_8168d_4);
2798
2799 rtl_enable_clock_request(tp);
2800 }
2801
2802 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
2803 {
2804 static const struct ephy_info e_info_8168e_1[] = {
2805 { 0x00, 0x0200, 0x0100 },
2806 { 0x00, 0x0000, 0x0004 },
2807 { 0x06, 0x0002, 0x0001 },
2808 { 0x06, 0x0000, 0x0030 },
2809 { 0x07, 0x0000, 0x2000 },
2810 { 0x00, 0x0000, 0x0020 },
2811 { 0x03, 0x5800, 0x2000 },
2812 { 0x03, 0x0000, 0x0001 },
2813 { 0x01, 0x0800, 0x1000 },
2814 { 0x07, 0x0000, 0x4000 },
2815 { 0x1e, 0x0000, 0x2000 },
2816 { 0x19, 0xffff, 0xfe6c },
2817 { 0x0a, 0x0000, 0x0040 }
2818 };
2819
2820 rtl_set_def_aspm_entry_latency(tp);
2821
2822 rtl_ephy_init(tp, e_info_8168e_1);
2823
2824 rtl_disable_clock_request(tp);
2825
2826 /* Reset tx FIFO pointer */
2827 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
2828 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
2829
2830 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2831 }
2832
2833 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
2834 {
2835 static const struct ephy_info e_info_8168e_2[] = {
2836 { 0x09, 0x0000, 0x0080 },
2837 { 0x19, 0x0000, 0x0224 },
2838 { 0x00, 0x0000, 0x0004 },
2839 { 0x0c, 0x3df0, 0x0200 },
2840 };
2841
2842 rtl_set_def_aspm_entry_latency(tp);
2843
2844 rtl_ephy_init(tp, e_info_8168e_2);
2845
2846 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2847 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2848 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2849 rtl_eri_set_bits(tp, 0x0d4, 0x1f00);
2850 rtl_eri_set_bits(tp, 0x1d0, BIT(1));
2851 rtl_reset_packet_filter(tp);
2852 rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2853 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2854 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
2855
2856 rtl_disable_clock_request(tp);
2857
2858 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2859
2860 rtl8168_config_eee_mac(tp);
2861
2862 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2863 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2864 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2865
2866 rtl_hw_aspm_clkreq_enable(tp, true);
2867 }
2868
2869 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
2870 {
2871 rtl_set_def_aspm_entry_latency(tp);
2872
2873 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2874 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2875 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2876 rtl_reset_packet_filter(tp);
2877 rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2878 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));
2879 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2880 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
2881
2882 rtl_disable_clock_request(tp);
2883
2884 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2885 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2886 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2887 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2888
2889 rtl8168_config_eee_mac(tp);
2890 }
2891
2892 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
2893 {
2894 static const struct ephy_info e_info_8168f_1[] = {
2895 { 0x06, 0x00c0, 0x0020 },
2896 { 0x08, 0x0001, 0x0002 },
2897 { 0x09, 0x0000, 0x0080 },
2898 { 0x19, 0x0000, 0x0224 },
2899 { 0x00, 0x0000, 0x0008 },
2900 { 0x0c, 0x3df0, 0x0200 },
2901 };
2902
2903 rtl_hw_start_8168f(tp);
2904
2905 rtl_ephy_init(tp, e_info_8168f_1);
2906
2907 rtl_eri_set_bits(tp, 0x0d4, 0x1f00);
2908 }
2909
2910 static void rtl_hw_start_8411(struct rtl8169_private *tp)
2911 {
2912 static const struct ephy_info e_info_8168f_1[] = {
2913 { 0x06, 0x00c0, 0x0020 },
2914 { 0x0f, 0xffff, 0x5200 },
2915 { 0x19, 0x0000, 0x0224 },
2916 { 0x00, 0x0000, 0x0008 },
2917 { 0x0c, 0x3df0, 0x0200 },
2918 };
2919
2920 rtl_hw_start_8168f(tp);
2921 rtl_pcie_state_l2l3_disable(tp);
2922
2923 rtl_ephy_init(tp, e_info_8168f_1);
2924
2925 rtl_eri_set_bits(tp, 0x0d4, 0x0c00);
2926 }
2927
2928 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
2929 {
2930 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
2931 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
2932
2933 rtl_set_def_aspm_entry_latency(tp);
2934
2935 rtl_reset_packet_filter(tp);
2936 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
2937
2938 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
2939
2940 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2941 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
2942 rtl_eri_set_bits(tp, 0x0d4, 0x1f80);
2943
2944 rtl8168_config_eee_mac(tp);
2945
2946 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
2947 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
2948
2949 rtl_pcie_state_l2l3_disable(tp);
2950 }
2951
2952 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
2953 {
2954 static const struct ephy_info e_info_8168g_1[] = {
2955 { 0x00, 0x0008, 0x0000 },
2956 { 0x0c, 0x3ff0, 0x0820 },
2957 { 0x1e, 0x0000, 0x0001 },
2958 { 0x19, 0x8000, 0x0000 }
2959 };
2960
2961 rtl_hw_start_8168g(tp);
2962
2963 /* disable aspm and clock request before access ephy */
2964 rtl_hw_aspm_clkreq_enable(tp, false);
2965 rtl_ephy_init(tp, e_info_8168g_1);
2966 rtl_hw_aspm_clkreq_enable(tp, true);
2967 }
2968
2969 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
2970 {
2971 static const struct ephy_info e_info_8168g_2[] = {
2972 { 0x00, 0x0008, 0x0000 },
2973 { 0x0c, 0x3ff0, 0x0820 },
2974 { 0x19, 0xffff, 0x7c00 },
2975 { 0x1e, 0xffff, 0x20eb },
2976 { 0x0d, 0xffff, 0x1666 },
2977 { 0x00, 0xffff, 0x10a3 },
2978 { 0x06, 0xffff, 0xf050 },
2979 { 0x04, 0x0000, 0x0010 },
2980 { 0x1d, 0x4000, 0x0000 },
2981 };
2982
2983 rtl_hw_start_8168g(tp);
2984
2985 /* disable aspm and clock request before access ephy */
2986 rtl_hw_aspm_clkreq_enable(tp, false);
2987 rtl_ephy_init(tp, e_info_8168g_2);
2988 }
2989
2990 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
2991 {
2992 static const struct ephy_info e_info_8411_2[] = {
2993 { 0x00, 0x0008, 0x0000 },
2994 { 0x0c, 0x37d0, 0x0820 },
2995 { 0x1e, 0x0000, 0x0001 },
2996 { 0x19, 0x8021, 0x0000 },
2997 { 0x1e, 0x0000, 0x2000 },
2998 { 0x0d, 0x0100, 0x0200 },
2999 { 0x00, 0x0000, 0x0080 },
3000 { 0x06, 0x0000, 0x0010 },
3001 { 0x04, 0x0000, 0x0010 },
3002 { 0x1d, 0x0000, 0x4000 },
3003 };
3004
3005 rtl_hw_start_8168g(tp);
3006
3007 /* disable aspm and clock request before access ephy */
3008 rtl_hw_aspm_clkreq_enable(tp, false);
3009 rtl_ephy_init(tp, e_info_8411_2);
3010
3011 /* The following Realtek-provided magic fixes an issue with the RX unit
3012 * getting confused after the PHY having been powered-down.
3013 */
3014 r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
3015 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
3016 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
3017 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
3018 r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
3019 r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
3020 r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
3021 r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
3022 mdelay(3);
3023 r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
3024
3025 r8168_mac_ocp_write(tp, 0xF800, 0xE008);
3026 r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
3027 r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
3028 r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
3029 r8168_mac_ocp_write(tp, 0xF808, 0xE027);
3030 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
3031 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
3032 r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
3033 r8168_mac_ocp_write(tp, 0xF810, 0xC602);
3034 r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
3035 r8168_mac_ocp_write(tp, 0xF814, 0x0000);
3036 r8168_mac_ocp_write(tp, 0xF816, 0xC502);
3037 r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
3038 r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
3039 r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
3040 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
3041 r8168_mac_ocp_write(tp, 0xF820, 0x080A);
3042 r8168_mac_ocp_write(tp, 0xF822, 0x6420);
3043 r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
3044 r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
3045 r8168_mac_ocp_write(tp, 0xF828, 0xC516);
3046 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
3047 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
3048 r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
3049 r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
3050 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
3051 r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
3052 r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
3053 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
3054 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
3055 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
3056 r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
3057 r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
3058 r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
3059 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
3060 r8168_mac_ocp_write(tp, 0xF846, 0xC404);
3061 r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
3062 r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
3063 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
3064 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
3065 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
3066 r8168_mac_ocp_write(tp, 0xF852, 0xE434);
3067 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
3068 r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
3069 r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
3070 r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
3071 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
3072 r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
3073 r8168_mac_ocp_write(tp, 0xF860, 0xF007);
3074 r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
3075 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
3076 r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
3077 r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
3078 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
3079 r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
3080 r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
3081 r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
3082 r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
3083 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
3084 r8168_mac_ocp_write(tp, 0xF876, 0xC516);
3085 r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
3086 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
3087 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
3088 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
3089 r8168_mac_ocp_write(tp, 0xF880, 0xC512);
3090 r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
3091 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
3092 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
3093 r8168_mac_ocp_write(tp, 0xF888, 0x483F);
3094 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
3095 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
3096 r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
3097 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
3098 r8168_mac_ocp_write(tp, 0xF892, 0xC505);
3099 r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
3100 r8168_mac_ocp_write(tp, 0xF896, 0xC502);
3101 r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
3102 r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
3103 r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
3104 r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
3105 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
3106 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
3107 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
3108 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
3109 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
3110 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
3111 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
3112 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
3113 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
3114 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
3115 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
3116 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
3117 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
3118 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
3119 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
3120 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
3121 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
3122 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
3123 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
3124 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
3125 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
3126 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
3127 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
3128 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
3129 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
3130 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
3131 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
3132 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
3133 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
3134 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
3135 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
3136
3137 r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
3138
3139 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
3140 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
3141 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
3142 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
3143 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
3144 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
3145 r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
3146
3147 rtl_hw_aspm_clkreq_enable(tp, true);
3148 }
3149
3150 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
3151 {
3152 static const struct ephy_info e_info_8168h_1[] = {
3153 { 0x1e, 0x0800, 0x0001 },
3154 { 0x1d, 0x0000, 0x0800 },
3155 { 0x05, 0xffff, 0x2089 },
3156 { 0x06, 0xffff, 0x5881 },
3157 { 0x04, 0xffff, 0x854a },
3158 { 0x01, 0xffff, 0x068b }
3159 };
3160 int rg_saw_cnt;
3161
3162 /* disable aspm and clock request before access ephy */
3163 rtl_hw_aspm_clkreq_enable(tp, false);
3164 rtl_ephy_init(tp, e_info_8168h_1);
3165
3166 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3167 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3168
3169 rtl_set_def_aspm_entry_latency(tp);
3170
3171 rtl_reset_packet_filter(tp);
3172
3173 rtl_eri_set_bits(tp, 0xd4, 0x1f00);
3174 rtl_eri_set_bits(tp, 0xdc, 0x001c);
3175
3176 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3177
3178 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3179
3180 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3181 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3182
3183 rtl8168_config_eee_mac(tp);
3184
3185 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3186 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3187
3188 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3189
3190 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3191
3192 rtl_pcie_state_l2l3_disable(tp);
3193
3194 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3195 if (rg_saw_cnt > 0) {
3196 u16 sw_cnt_1ms_ini;
3197
3198 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
3199 sw_cnt_1ms_ini &= 0x0fff;
3200 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3201 }
3202
3203 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3204 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
3205 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
3206 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3207
3208 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3209 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3210 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3211 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3212
3213 rtl_hw_aspm_clkreq_enable(tp, true);
3214 }
3215
3216 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
3217 {
3218 rtl8168ep_stop_cmac(tp);
3219
3220 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3221 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3222
3223 rtl_set_def_aspm_entry_latency(tp);
3224
3225 rtl_reset_packet_filter(tp);
3226
3227 rtl_eri_set_bits(tp, 0xd4, 0x1f80);
3228
3229 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3230
3231 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3232
3233 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3234 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3235
3236 rtl8168_config_eee_mac(tp);
3237
3238 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3239
3240 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3241
3242 rtl_pcie_state_l2l3_disable(tp);
3243 }
3244
3245 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
3246 {
3247 static const struct ephy_info e_info_8168ep_1[] = {
3248 { 0x00, 0xffff, 0x10ab },
3249 { 0x06, 0xffff, 0xf030 },
3250 { 0x08, 0xffff, 0x2006 },
3251 { 0x0d, 0xffff, 0x1666 },
3252 { 0x0c, 0x3ff0, 0x0000 }
3253 };
3254
3255 /* disable aspm and clock request before access ephy */
3256 rtl_hw_aspm_clkreq_enable(tp, false);
3257 rtl_ephy_init(tp, e_info_8168ep_1);
3258
3259 rtl_hw_start_8168ep(tp);
3260
3261 rtl_hw_aspm_clkreq_enable(tp, true);
3262 }
3263
3264 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
3265 {
3266 static const struct ephy_info e_info_8168ep_2[] = {
3267 { 0x00, 0xffff, 0x10a3 },
3268 { 0x19, 0xffff, 0xfc00 },
3269 { 0x1e, 0xffff, 0x20ea }
3270 };
3271
3272 /* disable aspm and clock request before access ephy */
3273 rtl_hw_aspm_clkreq_enable(tp, false);
3274 rtl_ephy_init(tp, e_info_8168ep_2);
3275
3276 rtl_hw_start_8168ep(tp);
3277
3278 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3279 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3280
3281 rtl_hw_aspm_clkreq_enable(tp, true);
3282 }
3283
3284 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
3285 {
3286 static const struct ephy_info e_info_8168ep_3[] = {
3287 { 0x00, 0x0000, 0x0080 },
3288 { 0x0d, 0x0100, 0x0200 },
3289 { 0x19, 0x8021, 0x0000 },
3290 { 0x1e, 0x0000, 0x2000 },
3291 };
3292
3293 /* disable aspm and clock request before access ephy */
3294 rtl_hw_aspm_clkreq_enable(tp, false);
3295 rtl_ephy_init(tp, e_info_8168ep_3);
3296
3297 rtl_hw_start_8168ep(tp);
3298
3299 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3300 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3301
3302 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
3303 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3304 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3305
3306 rtl_hw_aspm_clkreq_enable(tp, true);
3307 }
3308
3309 static void rtl_hw_start_8117(struct rtl8169_private *tp)
3310 {
3311 static const struct ephy_info e_info_8117[] = {
3312 { 0x19, 0x0040, 0x1100 },
3313 { 0x59, 0x0040, 0x1100 },
3314 };
3315 int rg_saw_cnt;
3316
3317 rtl8168ep_stop_cmac(tp);
3318
3319 /* disable aspm and clock request before access ephy */
3320 rtl_hw_aspm_clkreq_enable(tp, false);
3321 rtl_ephy_init(tp, e_info_8117);
3322
3323 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3324 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3325
3326 rtl_set_def_aspm_entry_latency(tp);
3327
3328 rtl_reset_packet_filter(tp);
3329
3330 rtl_eri_set_bits(tp, 0xd4, 0x1f90);
3331
3332 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3333
3334 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3335
3336 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3337 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3338
3339 rtl8168_config_eee_mac(tp);
3340
3341 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3342 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3343
3344 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3345
3346 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3347
3348 rtl_pcie_state_l2l3_disable(tp);
3349
3350 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3351 if (rg_saw_cnt > 0) {
3352 u16 sw_cnt_1ms_ini;
3353
3354 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
3355 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3356 }
3357
3358 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3359 r8168_mac_ocp_write(tp, 0xea80, 0x0003);
3360 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
3361 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3362
3363 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3364 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3365 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3366 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3367
3368 /* firmware is for MAC only */
3369 r8169_apply_firmware(tp);
3370
3371 rtl_hw_aspm_clkreq_enable(tp, true);
3372 }
3373
3374 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
3375 {
3376 static const struct ephy_info e_info_8102e_1[] = {
3377 { 0x01, 0, 0x6e65 },
3378 { 0x02, 0, 0x091f },
3379 { 0x03, 0, 0xc2f9 },
3380 { 0x06, 0, 0xafb5 },
3381 { 0x07, 0, 0x0e00 },
3382 { 0x19, 0, 0xec80 },
3383 { 0x01, 0, 0x2e65 },
3384 { 0x01, 0, 0x6e65 }
3385 };
3386 u8 cfg1;
3387
3388 rtl_set_def_aspm_entry_latency(tp);
3389
3390 RTL_W8(tp, DBG_REG, FIX_NAK_1);
3391
3392 RTL_W8(tp, Config1,
3393 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3394 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3395
3396 cfg1 = RTL_R8(tp, Config1);
3397 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3398 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
3399
3400 rtl_ephy_init(tp, e_info_8102e_1);
3401 }
3402
3403 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
3404 {
3405 rtl_set_def_aspm_entry_latency(tp);
3406
3407 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
3408 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3409 }
3410
3411 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
3412 {
3413 rtl_hw_start_8102e_2(tp);
3414
3415 rtl_ephy_write(tp, 0x03, 0xc2f9);
3416 }
3417
3418 static void rtl_hw_start_8401(struct rtl8169_private *tp)
3419 {
3420 static const struct ephy_info e_info_8401[] = {
3421 { 0x01, 0xffff, 0x6fe5 },
3422 { 0x03, 0xffff, 0x0599 },
3423 { 0x06, 0xffff, 0xaf25 },
3424 { 0x07, 0xffff, 0x8e68 },
3425 };
3426
3427 rtl_ephy_init(tp, e_info_8401);
3428 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3429 }
3430
3431 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
3432 {
3433 static const struct ephy_info e_info_8105e_1[] = {
3434 { 0x07, 0, 0x4000 },
3435 { 0x19, 0, 0x0200 },
3436 { 0x19, 0, 0x0020 },
3437 { 0x1e, 0, 0x2000 },
3438 { 0x03, 0, 0x0001 },
3439 { 0x19, 0, 0x0100 },
3440 { 0x19, 0, 0x0004 },
3441 { 0x0a, 0, 0x0020 }
3442 };
3443
3444 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3445 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3446
3447 /* Disable Early Tally Counter */
3448 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
3449
3450 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3451 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3452
3453 rtl_ephy_init(tp, e_info_8105e_1);
3454
3455 rtl_pcie_state_l2l3_disable(tp);
3456 }
3457
3458 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
3459 {
3460 rtl_hw_start_8105e_1(tp);
3461 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
3462 }
3463
3464 static void rtl_hw_start_8402(struct rtl8169_private *tp)
3465 {
3466 static const struct ephy_info e_info_8402[] = {
3467 { 0x19, 0xffff, 0xff64 },
3468 { 0x1e, 0, 0x4000 }
3469 };
3470
3471 rtl_set_def_aspm_entry_latency(tp);
3472
3473 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3474 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3475
3476 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3477
3478 rtl_ephy_init(tp, e_info_8402);
3479
3480 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
3481 rtl_reset_packet_filter(tp);
3482 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3483 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3484 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);
3485
3486 /* disable EEE */
3487 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3488
3489 rtl_pcie_state_l2l3_disable(tp);
3490 }
3491
3492 static void rtl_hw_start_8106(struct rtl8169_private *tp)
3493 {
3494 rtl_hw_aspm_clkreq_enable(tp, false);
3495
3496 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3497 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3498
3499 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3500 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3501 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3502
3503 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3504
3505 /* disable EEE */
3506 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3507
3508 rtl_pcie_state_l2l3_disable(tp);
3509 rtl_hw_aspm_clkreq_enable(tp, true);
3510 }
3511
3512 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
3513 {
3514 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
3515 }
3516
3517 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
3518 {
3519 rtl_pcie_state_l2l3_disable(tp);
3520
3521 RTL_W16(tp, 0x382, 0x221b);
3522 RTL_W8(tp, 0x4500, 0);
3523 RTL_W16(tp, 0x4800, 0);
3524
3525 /* disable UPS */
3526 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
3527
3528 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
3529
3530 r8168_mac_ocp_write(tp, 0xc140, 0xffff);
3531 r8168_mac_ocp_write(tp, 0xc142, 0xffff);
3532
3533 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
3534 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3535 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3536
3537 /* disable new tx descriptor format */
3538 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
3539
3540 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3541 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
3542 else
3543 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
3544
3545 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3546 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);
3547 else
3548 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
3549
3550 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
3551 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
3552 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
3553 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
3554 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
3555 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
3556 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
3557 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);
3558 r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00);
3559 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
3560
3561 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3562 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
3563 udelay(1);
3564 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
3565 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
3566
3567 r8168_mac_ocp_write(tp, 0xe098, 0xc302);
3568
3569 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
3570
3571 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3572 rtl8125b_config_eee_mac(tp);
3573 else
3574 rtl8125a_config_eee_mac(tp);
3575
3576 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3577 udelay(10);
3578 }
3579
3580 static void rtl_hw_start_8125a_1(struct rtl8169_private *tp)
3581 {
3582 static const struct ephy_info e_info_8125a_1[] = {
3583 { 0x01, 0xffff, 0xa812 },
3584 { 0x09, 0xffff, 0x520c },
3585 { 0x04, 0xffff, 0xd000 },
3586 { 0x0d, 0xffff, 0xf702 },
3587 { 0x0a, 0xffff, 0x8653 },
3588 { 0x06, 0xffff, 0x001e },
3589 { 0x08, 0xffff, 0x3595 },
3590 { 0x20, 0xffff, 0x9455 },
3591 { 0x21, 0xffff, 0x99ff },
3592 { 0x02, 0xffff, 0x6046 },
3593 { 0x29, 0xffff, 0xfe00 },
3594 { 0x23, 0xffff, 0xab62 },
3595
3596 { 0x41, 0xffff, 0xa80c },
3597 { 0x49, 0xffff, 0x520c },
3598 { 0x44, 0xffff, 0xd000 },
3599 { 0x4d, 0xffff, 0xf702 },
3600 { 0x4a, 0xffff, 0x8653 },
3601 { 0x46, 0xffff, 0x001e },
3602 { 0x48, 0xffff, 0x3595 },
3603 { 0x60, 0xffff, 0x9455 },
3604 { 0x61, 0xffff, 0x99ff },
3605 { 0x42, 0xffff, 0x6046 },
3606 { 0x69, 0xffff, 0xfe00 },
3607 { 0x63, 0xffff, 0xab62 },
3608 };
3609
3610 rtl_set_def_aspm_entry_latency(tp);
3611
3612 /* disable aspm and clock request before access ephy */
3613 rtl_hw_aspm_clkreq_enable(tp, false);
3614 rtl_ephy_init(tp, e_info_8125a_1);
3615
3616 rtl_hw_start_8125_common(tp);
3617 rtl_hw_aspm_clkreq_enable(tp, true);
3618 }
3619
3620 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)
3621 {
3622 static const struct ephy_info e_info_8125a_2[] = {
3623 { 0x04, 0xffff, 0xd000 },
3624 { 0x0a, 0xffff, 0x8653 },
3625 { 0x23, 0xffff, 0xab66 },
3626 { 0x20, 0xffff, 0x9455 },
3627 { 0x21, 0xffff, 0x99ff },
3628 { 0x29, 0xffff, 0xfe04 },
3629
3630 { 0x44, 0xffff, 0xd000 },
3631 { 0x4a, 0xffff, 0x8653 },
3632 { 0x63, 0xffff, 0xab66 },
3633 { 0x60, 0xffff, 0x9455 },
3634 { 0x61, 0xffff, 0x99ff },
3635 { 0x69, 0xffff, 0xfe04 },
3636 };
3637
3638 rtl_set_def_aspm_entry_latency(tp);
3639
3640 /* disable aspm and clock request before access ephy */
3641 rtl_hw_aspm_clkreq_enable(tp, false);
3642 rtl_ephy_init(tp, e_info_8125a_2);
3643
3644 rtl_hw_start_8125_common(tp);
3645 rtl_hw_aspm_clkreq_enable(tp, true);
3646 }
3647
3648 static void rtl_hw_start_8125b(struct rtl8169_private *tp)
3649 {
3650 static const struct ephy_info e_info_8125b[] = {
3651 { 0x0b, 0xffff, 0xa908 },
3652 { 0x1e, 0xffff, 0x20eb },
3653 { 0x4b, 0xffff, 0xa908 },
3654 { 0x5e, 0xffff, 0x20eb },
3655 { 0x22, 0x0030, 0x0020 },
3656 { 0x62, 0x0030, 0x0020 },
3657 };
3658
3659 rtl_set_def_aspm_entry_latency(tp);
3660 rtl_hw_aspm_clkreq_enable(tp, false);
3661
3662 rtl_ephy_init(tp, e_info_8125b);
3663 rtl_hw_start_8125_common(tp);
3664
3665 rtl_hw_aspm_clkreq_enable(tp, true);
3666 }
3667
3668 static void rtl_hw_config(struct rtl8169_private *tp)
3669 {
3670 static const rtl_generic_fct hw_configs[] = {
3671 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
3672 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
3673 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
3674 [RTL_GIGA_MAC_VER_10] = NULL,
3675 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b,
3676 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b,
3677 [RTL_GIGA_MAC_VER_13] = NULL,
3678 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401,
3679 [RTL_GIGA_MAC_VER_16] = NULL,
3680 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
3681 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
3682 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
3683 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
3684 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
3685 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
3686 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
3687 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
3688 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
3689 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
3690 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
3691 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
3692 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
3693 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
3694 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
3695 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
3696 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
3697 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
3698 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
3699 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
3700 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
3701 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
3702 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
3703 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
3704 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
3705 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
3706 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
3707 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
3708 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
3709 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
3710 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
3711 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
3712 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
3713 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
3714 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
3715 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
3716 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125a_1,
3717 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
3718 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
3719 };
3720
3721 if (hw_configs[tp->mac_version])
3722 hw_configs[tp->mac_version](tp);
3723 }
3724
3725 static void rtl_hw_start_8125(struct rtl8169_private *tp)
3726 {
3727 int i;
3728
3729 /* disable interrupt coalescing */
3730 for (i = 0xa00; i < 0xb00; i += 4)
3731 RTL_W32(tp, i, 0);
3732
3733 rtl_hw_config(tp);
3734 }
3735
3736 static void rtl_hw_start_8168(struct rtl8169_private *tp)
3737 {
3738 if (rtl_is_8168evl_up(tp))
3739 RTL_W8(tp, MaxTxPacketSize, EarlySize);
3740 else
3741 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
3742
3743 rtl_hw_config(tp);
3744
3745 /* disable interrupt coalescing */
3746 RTL_W16(tp, IntrMitigate, 0x0000);
3747 }
3748
3749 static void rtl_hw_start_8169(struct rtl8169_private *tp)
3750 {
3751 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
3752
3753 tp->cp_cmd |= PCIMulRW;
3754
3755 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3756 tp->mac_version == RTL_GIGA_MAC_VER_03)
3757 tp->cp_cmd |= EnAnaPLL;
3758
3759 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3760
3761 rtl8169_set_magic_reg(tp);
3762
3763 /* disable interrupt coalescing */
3764 RTL_W16(tp, IntrMitigate, 0x0000);
3765 }
3766
3767 static void rtl_hw_start(struct rtl8169_private *tp)
3768 {
3769 rtl_unlock_config_regs(tp);
3770
3771 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3772
3773 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3774 rtl_hw_start_8169(tp);
3775 else if (rtl_is_8125(tp))
3776 rtl_hw_start_8125(tp);
3777 else
3778 rtl_hw_start_8168(tp);
3779
3780 rtl_set_rx_max_size(tp);
3781 rtl_set_rx_tx_desc_registers(tp);
3782 rtl_lock_config_regs(tp);
3783
3784 rtl_jumbo_config(tp);
3785
3786 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3787 rtl_pci_commit(tp);
3788
3789 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
3790 rtl_init_rxcfg(tp);
3791 rtl_set_tx_config_registers(tp);
3792 rtl_set_rx_config_features(tp, tp->dev->features);
3793 rtl_set_rx_mode(tp->dev);
3794 rtl_irq_enable(tp);
3795 }
3796
3797 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3798 {
3799 struct rtl8169_private *tp = netdev_priv(dev);
3800
3801 dev->mtu = new_mtu;
3802 netdev_update_features(dev);
3803 rtl_jumbo_config(tp);
3804
3805 switch (tp->mac_version) {
3806 case RTL_GIGA_MAC_VER_61:
3807 case RTL_GIGA_MAC_VER_63:
3808 rtl8125_set_eee_txidle_timer(tp);
3809 break;
3810 default:
3811 break;
3812 }
3813
3814 return 0;
3815 }
3816
3817 static void rtl8169_mark_to_asic(struct RxDesc *desc)
3818 {
3819 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3820
3821 desc->opts2 = 0;
3822 /* Force memory writes to complete before releasing descriptor */
3823 dma_wmb();
3824 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE));
3825 }
3826
3827 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3828 struct RxDesc *desc)
3829 {
3830 struct device *d = tp_to_dev(tp);
3831 int node = dev_to_node(d);
3832 dma_addr_t mapping;
3833 struct page *data;
3834
3835 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
3836 if (!data)
3837 return NULL;
3838
3839 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3840 if (unlikely(dma_mapping_error(d, mapping))) {
3841 netdev_err(tp->dev, "Failed to map RX DMA!\n");
3842 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
3843 return NULL;
3844 }
3845
3846 desc->addr = cpu_to_le64(mapping);
3847 rtl8169_mark_to_asic(desc);
3848
3849 return data;
3850 }
3851
3852 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3853 {
3854 unsigned int i;
3855
3856 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
3857 dma_unmap_page(tp_to_dev(tp),
3858 le64_to_cpu(tp->RxDescArray[i].addr),
3859 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3860 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
3861 tp->Rx_databuff[i] = NULL;
3862 tp->RxDescArray[i].addr = 0;
3863 tp->RxDescArray[i].opts1 = 0;
3864 }
3865 }
3866
3867 static int rtl8169_rx_fill(struct rtl8169_private *tp)
3868 {
3869 unsigned int i;
3870
3871 for (i = 0; i < NUM_RX_DESC; i++) {
3872 struct page *data;
3873
3874 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3875 if (!data) {
3876 rtl8169_rx_clear(tp);
3877 return -ENOMEM;
3878 }
3879 tp->Rx_databuff[i] = data;
3880 }
3881
3882 /* mark as last descriptor in the ring */
3883 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);
3884
3885 return 0;
3886 }
3887
3888 static int rtl8169_init_ring(struct rtl8169_private *tp)
3889 {
3890 rtl8169_init_ring_indexes(tp);
3891
3892 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
3893 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
3894
3895 return rtl8169_rx_fill(tp);
3896 }
3897
3898 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)
3899 {
3900 struct ring_info *tx_skb = tp->tx_skb + entry;
3901 struct TxDesc *desc = tp->TxDescArray + entry;
3902
3903 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,
3904 DMA_TO_DEVICE);
3905 memset(desc, 0, sizeof(*desc));
3906 memset(tx_skb, 0, sizeof(*tx_skb));
3907 }
3908
3909 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
3910 unsigned int n)
3911 {
3912 unsigned int i;
3913
3914 for (i = 0; i < n; i++) {
3915 unsigned int entry = (start + i) % NUM_TX_DESC;
3916 struct ring_info *tx_skb = tp->tx_skb + entry;
3917 unsigned int len = tx_skb->len;
3918
3919 if (len) {
3920 struct sk_buff *skb = tx_skb->skb;
3921
3922 rtl8169_unmap_tx_skb(tp, entry);
3923 if (skb)
3924 dev_consume_skb_any(skb);
3925 }
3926 }
3927 }
3928
3929 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3930 {
3931 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
3932 netdev_reset_queue(tp->dev);
3933 }
3934
3935 static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down)
3936 {
3937 napi_disable(&tp->napi);
3938
3939 /* Give a racing hard_start_xmit a few cycles to complete. */
3940 synchronize_net();
3941
3942 /* Disable interrupts */
3943 rtl8169_irq_mask_and_ack(tp);
3944
3945 rtl_rx_close(tp);
3946
3947 if (going_down && tp->dev->wol_enabled)
3948 goto no_reset;
3949
3950 switch (tp->mac_version) {
3951 case RTL_GIGA_MAC_VER_27:
3952 case RTL_GIGA_MAC_VER_28:
3953 case RTL_GIGA_MAC_VER_31:
3954 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);
3955 break;
3956 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
3957 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3958 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
3959 break;
3960 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
3961 rtl_enable_rxdvgate(tp);
3962 fsleep(2000);
3963 break;
3964 default:
3965 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3966 fsleep(100);
3967 break;
3968 }
3969
3970 rtl_hw_reset(tp);
3971 no_reset:
3972 rtl8169_tx_clear(tp);
3973 rtl8169_init_ring_indexes(tp);
3974 }
3975
3976 static void rtl_reset_work(struct rtl8169_private *tp)
3977 {
3978 int i;
3979
3980 netif_stop_queue(tp->dev);
3981
3982 rtl8169_cleanup(tp, false);
3983
3984 for (i = 0; i < NUM_RX_DESC; i++)
3985 rtl8169_mark_to_asic(tp->RxDescArray + i);
3986
3987 napi_enable(&tp->napi);
3988 rtl_hw_start(tp);
3989 }
3990
3991 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue)
3992 {
3993 struct rtl8169_private *tp = netdev_priv(dev);
3994
3995 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
3996 }
3997
3998 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,
3999 void *addr, unsigned int entry, bool desc_own)
4000 {
4001 struct TxDesc *txd = tp->TxDescArray + entry;
4002 struct device *d = tp_to_dev(tp);
4003 dma_addr_t mapping;
4004 u32 opts1;
4005 int ret;
4006
4007 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4008 ret = dma_mapping_error(d, mapping);
4009 if (unlikely(ret)) {
4010 if (net_ratelimit())
4011 netdev_err(tp->dev, "Failed to map TX data!\n");
4012 return ret;
4013 }
4014
4015 txd->addr = cpu_to_le64(mapping);
4016 txd->opts2 = cpu_to_le32(opts[1]);
4017
4018 opts1 = opts[0] | len;
4019 if (entry == NUM_TX_DESC - 1)
4020 opts1 |= RingEnd;
4021 if (desc_own)
4022 opts1 |= DescOwn;
4023 txd->opts1 = cpu_to_le32(opts1);
4024
4025 tp->tx_skb[entry].len = len;
4026
4027 return 0;
4028 }
4029
4030 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4031 const u32 *opts, unsigned int entry)
4032 {
4033 struct skb_shared_info *info = skb_shinfo(skb);
4034 unsigned int cur_frag;
4035
4036 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4037 const skb_frag_t *frag = info->frags + cur_frag;
4038 void *addr = skb_frag_address(frag);
4039 u32 len = skb_frag_size(frag);
4040
4041 entry = (entry + 1) % NUM_TX_DESC;
4042
4043 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))
4044 goto err_out;
4045 }
4046
4047 return 0;
4048
4049 err_out:
4050 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4051 return -EIO;
4052 }
4053
4054 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp)
4055 {
4056 switch (tp->mac_version) {
4057 case RTL_GIGA_MAC_VER_34:
4058 case RTL_GIGA_MAC_VER_60:
4059 case RTL_GIGA_MAC_VER_61:
4060 case RTL_GIGA_MAC_VER_63:
4061 return true;
4062 default:
4063 return false;
4064 }
4065 }
4066
4067 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
4068 {
4069 u32 mss = skb_shinfo(skb)->gso_size;
4070
4071 if (mss) {
4072 opts[0] |= TD_LSO;
4073 opts[0] |= mss << TD0_MSS_SHIFT;
4074 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4075 const struct iphdr *ip = ip_hdr(skb);
4076
4077 if (ip->protocol == IPPROTO_TCP)
4078 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
4079 else if (ip->protocol == IPPROTO_UDP)
4080 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
4081 else
4082 WARN_ON_ONCE(1);
4083 }
4084 }
4085
4086 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
4087 struct sk_buff *skb, u32 *opts)
4088 {
4089 u32 transport_offset = (u32)skb_transport_offset(skb);
4090 struct skb_shared_info *shinfo = skb_shinfo(skb);
4091 u32 mss = shinfo->gso_size;
4092
4093 if (mss) {
4094 if (shinfo->gso_type & SKB_GSO_TCPV4) {
4095 opts[0] |= TD1_GTSENV4;
4096 } else if (shinfo->gso_type & SKB_GSO_TCPV6) {
4097 if (skb_cow_head(skb, 0))
4098 return false;
4099
4100 tcp_v6_gso_csum_prep(skb);
4101 opts[0] |= TD1_GTSENV6;
4102 } else {
4103 WARN_ON_ONCE(1);
4104 }
4105
4106 opts[0] |= transport_offset << GTTCPHO_SHIFT;
4107 opts[1] |= mss << TD1_MSS_SHIFT;
4108 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4109 u8 ip_protocol;
4110
4111 switch (vlan_get_protocol(skb)) {
4112 case htons(ETH_P_IP):
4113 opts[1] |= TD1_IPv4_CS;
4114 ip_protocol = ip_hdr(skb)->protocol;
4115 break;
4116
4117 case htons(ETH_P_IPV6):
4118 opts[1] |= TD1_IPv6_CS;
4119 ip_protocol = ipv6_hdr(skb)->nexthdr;
4120 break;
4121
4122 default:
4123 ip_protocol = IPPROTO_RAW;
4124 break;
4125 }
4126
4127 if (ip_protocol == IPPROTO_TCP)
4128 opts[1] |= TD1_TCP_CS;
4129 else if (ip_protocol == IPPROTO_UDP)
4130 opts[1] |= TD1_UDP_CS;
4131 else
4132 WARN_ON_ONCE(1);
4133
4134 opts[1] |= transport_offset << TCPHO_SHIFT;
4135 } else {
4136 if (unlikely(skb->len < ETH_ZLEN && rtl_test_hw_pad_bug(tp)))
4137 /* eth_skb_pad would free the skb on error */
4138 return !__skb_put_padto(skb, ETH_ZLEN, false);
4139 }
4140
4141 return true;
4142 }
4143
4144 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
4145 unsigned int nr_frags)
4146 {
4147 unsigned int slots_avail = READ_ONCE(tp->dirty_tx) + NUM_TX_DESC
4148 - READ_ONCE(tp->cur_tx);
4149
4150 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
4151 return slots_avail > nr_frags;
4152 }
4153
4154 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
4155 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
4156 {
4157 switch (tp->mac_version) {
4158 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4159 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4160 return false;
4161 default:
4162 return true;
4163 }
4164 }
4165
4166 static void rtl8169_doorbell(struct rtl8169_private *tp)
4167 {
4168 if (rtl_is_8125(tp))
4169 RTL_W16(tp, TxPoll_8125, BIT(0));
4170 else
4171 RTL_W8(tp, TxPoll, NPQ);
4172 }
4173
4174 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4175 struct net_device *dev)
4176 {
4177 unsigned int frags = skb_shinfo(skb)->nr_frags;
4178 struct rtl8169_private *tp = netdev_priv(dev);
4179 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4180 struct TxDesc *txd_first, *txd_last;
4181 bool stop_queue, door_bell;
4182 u32 opts[2];
4183
4184 txd_first = tp->TxDescArray + entry;
4185
4186 if (unlikely(!rtl_tx_slots_avail(tp, frags))) {
4187 if (net_ratelimit())
4188 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
4189 goto err_stop_0;
4190 }
4191
4192 if (unlikely(le32_to_cpu(txd_first->opts1) & DescOwn))
4193 goto err_stop_0;
4194
4195 opts[1] = rtl8169_tx_vlan_tag(skb);
4196 opts[0] = 0;
4197
4198 if (!rtl_chip_supports_csum_v2(tp))
4199 rtl8169_tso_csum_v1(skb, opts);
4200 else if (!rtl8169_tso_csum_v2(tp, skb, opts))
4201 goto err_dma_0;
4202
4203 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,
4204 entry, false)))
4205 goto err_dma_0;
4206
4207 if (frags) {
4208 if (rtl8169_xmit_frags(tp, skb, opts, entry))
4209 goto err_dma_1;
4210 entry = (entry + frags) % NUM_TX_DESC;
4211 }
4212
4213 txd_last = tp->TxDescArray + entry;
4214 txd_last->opts1 |= cpu_to_le32(LastFrag);
4215 tp->tx_skb[entry].skb = skb;
4216
4217 skb_tx_timestamp(skb);
4218
4219 /* Force memory writes to complete before releasing descriptor */
4220 dma_wmb();
4221
4222 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
4223
4224 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag);
4225
4226 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */
4227 smp_wmb();
4228
4229 tp->cur_tx += frags + 1;
4230
4231 stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS);
4232 if (unlikely(stop_queue)) {
4233 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
4234 * not miss a ring update when it notices a stopped queue.
4235 */
4236 smp_wmb();
4237 netif_stop_queue(dev);
4238 door_bell = true;
4239 }
4240
4241 if (door_bell)
4242 rtl8169_doorbell(tp);
4243
4244 if (unlikely(stop_queue)) {
4245 /* Sync with rtl_tx:
4246 * - publish queue status and cur_tx ring index (write barrier)
4247 * - refresh dirty_tx ring index (read barrier).
4248 * May the current thread have a pessimistic view of the ring
4249 * status and forget to wake up queue, a racing rtl_tx thread
4250 * can't.
4251 */
4252 smp_mb();
4253 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
4254 netif_start_queue(dev);
4255 }
4256
4257 return NETDEV_TX_OK;
4258
4259 err_dma_1:
4260 rtl8169_unmap_tx_skb(tp, entry);
4261 err_dma_0:
4262 dev_kfree_skb_any(skb);
4263 dev->stats.tx_dropped++;
4264 return NETDEV_TX_OK;
4265
4266 err_stop_0:
4267 netif_stop_queue(dev);
4268 dev->stats.tx_dropped++;
4269 return NETDEV_TX_BUSY;
4270 }
4271
4272 static unsigned int rtl_last_frag_len(struct sk_buff *skb)
4273 {
4274 struct skb_shared_info *info = skb_shinfo(skb);
4275 unsigned int nr_frags = info->nr_frags;
4276
4277 if (!nr_frags)
4278 return UINT_MAX;
4279
4280 return skb_frag_size(info->frags + nr_frags - 1);
4281 }
4282
4283 /* Workaround for hw issues with TSO on RTL8168evl */
4284 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb,
4285 netdev_features_t features)
4286 {
4287 /* IPv4 header has options field */
4288 if (vlan_get_protocol(skb) == htons(ETH_P_IP) &&
4289 ip_hdrlen(skb) > sizeof(struct iphdr))
4290 features &= ~NETIF_F_ALL_TSO;
4291
4292 /* IPv4 TCP header has options field */
4293 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 &&
4294 tcp_hdrlen(skb) > sizeof(struct tcphdr))
4295 features &= ~NETIF_F_ALL_TSO;
4296
4297 else if (rtl_last_frag_len(skb) <= 6)
4298 features &= ~NETIF_F_ALL_TSO;
4299
4300 return features;
4301 }
4302
4303 static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
4304 struct net_device *dev,
4305 netdev_features_t features)
4306 {
4307 int transport_offset = skb_transport_offset(skb);
4308 struct rtl8169_private *tp = netdev_priv(dev);
4309
4310 if (skb_is_gso(skb)) {
4311 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4312 features = rtl8168evl_fix_tso(skb, features);
4313
4314 if (transport_offset > GTTCPHO_MAX &&
4315 rtl_chip_supports_csum_v2(tp))
4316 features &= ~NETIF_F_ALL_TSO;
4317 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4318 /* work around hw bug on some chip versions */
4319 if (skb->len < ETH_ZLEN)
4320 features &= ~NETIF_F_CSUM_MASK;
4321
4322 if (transport_offset > TCPHO_MAX &&
4323 rtl_chip_supports_csum_v2(tp))
4324 features &= ~NETIF_F_CSUM_MASK;
4325 }
4326
4327 return vlan_features_check(skb, features);
4328 }
4329
4330 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4331 {
4332 struct rtl8169_private *tp = netdev_priv(dev);
4333 struct pci_dev *pdev = tp->pci_dev;
4334 int pci_status_errs;
4335 u16 pci_cmd;
4336
4337 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4338
4339 pci_status_errs = pci_status_get_and_clear_errors(pdev);
4340
4341 if (net_ratelimit())
4342 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n",
4343 pci_cmd, pci_status_errs);
4344 /*
4345 * The recovery sequence below admits a very elaborated explanation:
4346 * - it seems to work;
4347 * - I did not see what else could be done;
4348 * - it makes iop3xx happy.
4349 *
4350 * Feel free to adjust to your needs.
4351 */
4352 if (pdev->broken_parity_status)
4353 pci_cmd &= ~PCI_COMMAND_PARITY;
4354 else
4355 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4356
4357 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4358
4359 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4360 }
4361
4362 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
4363 int budget)
4364 {
4365 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0;
4366
4367 dirty_tx = tp->dirty_tx;
4368
4369 while (READ_ONCE(tp->cur_tx) != dirty_tx) {
4370 unsigned int entry = dirty_tx % NUM_TX_DESC;
4371 struct sk_buff *skb = tp->tx_skb[entry].skb;
4372 u32 status;
4373
4374 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4375 if (status & DescOwn)
4376 break;
4377
4378 rtl8169_unmap_tx_skb(tp, entry);
4379
4380 if (skb) {
4381 pkts_compl++;
4382 bytes_compl += skb->len;
4383 napi_consume_skb(skb, budget);
4384 }
4385 dirty_tx++;
4386 }
4387
4388 if (tp->dirty_tx != dirty_tx) {
4389 netdev_completed_queue(dev, pkts_compl, bytes_compl);
4390 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl);
4391
4392 /* Sync with rtl8169_start_xmit:
4393 * - publish dirty_tx ring index (write barrier)
4394 * - refresh cur_tx ring index and queue status (read barrier)
4395 * May the current thread miss the stopped queue condition,
4396 * a racing xmit thread can only have a right view of the
4397 * ring status.
4398 */
4399 smp_store_mb(tp->dirty_tx, dirty_tx);
4400 if (netif_queue_stopped(dev) &&
4401 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
4402 netif_wake_queue(dev);
4403 }
4404 /*
4405 * 8168 hack: TxPoll requests are lost when the Tx packets are
4406 * too close. Let's kick an extra TxPoll request when a burst
4407 * of start_xmit activity is detected (if it is not detected,
4408 * it is slow enough). -- FR
4409 */
4410 if (tp->cur_tx != dirty_tx)
4411 rtl8169_doorbell(tp);
4412 }
4413 }
4414
4415 static inline int rtl8169_fragmented_frame(u32 status)
4416 {
4417 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4418 }
4419
4420 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4421 {
4422 u32 status = opts1 & RxProtoMask;
4423
4424 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4425 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4426 skb->ip_summed = CHECKSUM_UNNECESSARY;
4427 else
4428 skb_checksum_none_assert(skb);
4429 }
4430
4431 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
4432 {
4433 unsigned int cur_rx, rx_left, count;
4434 struct device *d = tp_to_dev(tp);
4435
4436 cur_rx = tp->cur_rx;
4437
4438 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
4439 unsigned int pkt_size, entry = cur_rx % NUM_RX_DESC;
4440 struct RxDesc *desc = tp->RxDescArray + entry;
4441 struct sk_buff *skb;
4442 const void *rx_buf;
4443 dma_addr_t addr;
4444 u32 status;
4445
4446 status = le32_to_cpu(desc->opts1);
4447 if (status & DescOwn)
4448 break;
4449
4450 /* This barrier is needed to keep us from reading
4451 * any other fields out of the Rx descriptor until
4452 * we know the status of DescOwn
4453 */
4454 dma_rmb();
4455
4456 if (unlikely(status & RxRES)) {
4457 if (net_ratelimit())
4458 netdev_warn(dev, "Rx ERROR. status = %08x\n",
4459 status);
4460 dev->stats.rx_errors++;
4461 if (status & (RxRWT | RxRUNT))
4462 dev->stats.rx_length_errors++;
4463 if (status & RxCRC)
4464 dev->stats.rx_crc_errors++;
4465
4466 if (!(dev->features & NETIF_F_RXALL))
4467 goto release_descriptor;
4468 else if (status & RxRWT || !(status & (RxRUNT | RxCRC)))
4469 goto release_descriptor;
4470 }
4471
4472 pkt_size = status & GENMASK(13, 0);
4473 if (likely(!(dev->features & NETIF_F_RXFCS)))
4474 pkt_size -= ETH_FCS_LEN;
4475
4476 /* The driver does not support incoming fragmented frames.
4477 * They are seen as a symptom of over-mtu sized frames.
4478 */
4479 if (unlikely(rtl8169_fragmented_frame(status))) {
4480 dev->stats.rx_dropped++;
4481 dev->stats.rx_length_errors++;
4482 goto release_descriptor;
4483 }
4484
4485 skb = napi_alloc_skb(&tp->napi, pkt_size);
4486 if (unlikely(!skb)) {
4487 dev->stats.rx_dropped++;
4488 goto release_descriptor;
4489 }
4490
4491 addr = le64_to_cpu(desc->addr);
4492 rx_buf = page_address(tp->Rx_databuff[entry]);
4493
4494 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4495 prefetch(rx_buf);
4496 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
4497 skb->tail += pkt_size;
4498 skb->len = pkt_size;
4499 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4500
4501 rtl8169_rx_csum(skb, status);
4502 skb->protocol = eth_type_trans(skb, dev);
4503
4504 rtl8169_rx_vlan_tag(desc, skb);
4505
4506 if (skb->pkt_type == PACKET_MULTICAST)
4507 dev->stats.multicast++;
4508
4509 napi_gro_receive(&tp->napi, skb);
4510
4511 dev_sw_netstats_rx_add(dev, pkt_size);
4512 release_descriptor:
4513 rtl8169_mark_to_asic(desc);
4514 }
4515
4516 count = cur_rx - tp->cur_rx;
4517 tp->cur_rx = cur_rx;
4518
4519 return count;
4520 }
4521
4522 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4523 {
4524 struct rtl8169_private *tp = dev_instance;
4525 u32 status = rtl_get_events(tp);
4526
4527 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))
4528 return IRQ_NONE;
4529
4530 if (unlikely(status & SYSErr)) {
4531 rtl8169_pcierr_interrupt(tp->dev);
4532 goto out;
4533 }
4534
4535 if (status & LinkChg)
4536 phy_mac_interrupt(tp->phydev);
4537
4538 if (unlikely(status & RxFIFOOver &&
4539 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4540 netif_stop_queue(tp->dev);
4541 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4542 }
4543
4544 rtl_irq_disable(tp);
4545 napi_schedule(&tp->napi);
4546 out:
4547 rtl_ack_events(tp, status);
4548
4549 return IRQ_HANDLED;
4550 }
4551
4552 static void rtl_task(struct work_struct *work)
4553 {
4554 struct rtl8169_private *tp =
4555 container_of(work, struct rtl8169_private, wk.work);
4556
4557 rtnl_lock();
4558
4559 if (!netif_running(tp->dev) ||
4560 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
4561 goto out_unlock;
4562
4563 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {
4564 rtl_reset_work(tp);
4565 netif_wake_queue(tp->dev);
4566 }
4567 out_unlock:
4568 rtnl_unlock();
4569 }
4570
4571 static int rtl8169_poll(struct napi_struct *napi, int budget)
4572 {
4573 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4574 struct net_device *dev = tp->dev;
4575 int work_done;
4576
4577 work_done = rtl_rx(dev, tp, (u32) budget);
4578
4579 rtl_tx(dev, tp, budget);
4580
4581 if (work_done < budget && napi_complete_done(napi, work_done))
4582 rtl_irq_enable(tp);
4583
4584 return work_done;
4585 }
4586
4587 static void r8169_phylink_handler(struct net_device *ndev)
4588 {
4589 struct rtl8169_private *tp = netdev_priv(ndev);
4590
4591 if (netif_carrier_ok(ndev)) {
4592 rtl_link_chg_patch(tp);
4593 pm_request_resume(&tp->pci_dev->dev);
4594 } else {
4595 pm_runtime_idle(&tp->pci_dev->dev);
4596 }
4597
4598 if (net_ratelimit())
4599 phy_print_status(tp->phydev);
4600 }
4601
4602 static int r8169_phy_connect(struct rtl8169_private *tp)
4603 {
4604 struct phy_device *phydev = tp->phydev;
4605 phy_interface_t phy_mode;
4606 int ret;
4607
4608 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
4609 PHY_INTERFACE_MODE_MII;
4610
4611 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
4612 phy_mode);
4613 if (ret)
4614 return ret;
4615
4616 if (!tp->supports_gmii)
4617 phy_set_max_speed(phydev, SPEED_100);
4618
4619 phy_support_asym_pause(phydev);
4620
4621 phy_attached_info(phydev);
4622
4623 return 0;
4624 }
4625
4626 static void rtl8169_down(struct rtl8169_private *tp)
4627 {
4628 /* Clear all task flags */
4629 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
4630
4631 phy_stop(tp->phydev);
4632
4633 rtl8169_update_counters(tp);
4634
4635 rtl8169_cleanup(tp, true);
4636
4637 rtl_pll_power_down(tp);
4638 }
4639
4640 static void rtl8169_up(struct rtl8169_private *tp)
4641 {
4642 rtl_pll_power_up(tp);
4643 rtl8169_init_phy(tp);
4644 napi_enable(&tp->napi);
4645 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4646 rtl_reset_work(tp);
4647
4648 phy_start(tp->phydev);
4649 }
4650
4651 static int rtl8169_close(struct net_device *dev)
4652 {
4653 struct rtl8169_private *tp = netdev_priv(dev);
4654 struct pci_dev *pdev = tp->pci_dev;
4655
4656 pm_runtime_get_sync(&pdev->dev);
4657
4658 netif_stop_queue(dev);
4659 rtl8169_down(tp);
4660 rtl8169_rx_clear(tp);
4661
4662 cancel_work_sync(&tp->wk.work);
4663
4664 phy_disconnect(tp->phydev);
4665
4666 free_irq(pci_irq_vector(pdev, 0), tp);
4667
4668 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4669 tp->RxPhyAddr);
4670 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4671 tp->TxPhyAddr);
4672 tp->TxDescArray = NULL;
4673 tp->RxDescArray = NULL;
4674
4675 pm_runtime_put_sync(&pdev->dev);
4676
4677 return 0;
4678 }
4679
4680 #ifdef CONFIG_NET_POLL_CONTROLLER
4681 static void rtl8169_netpoll(struct net_device *dev)
4682 {
4683 struct rtl8169_private *tp = netdev_priv(dev);
4684
4685 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
4686 }
4687 #endif
4688
4689 static int rtl_open(struct net_device *dev)
4690 {
4691 struct rtl8169_private *tp = netdev_priv(dev);
4692 struct pci_dev *pdev = tp->pci_dev;
4693 unsigned long irqflags;
4694 int retval = -ENOMEM;
4695
4696 pm_runtime_get_sync(&pdev->dev);
4697
4698 /*
4699 * Rx and Tx descriptors needs 256 bytes alignment.
4700 * dma_alloc_coherent provides more.
4701 */
4702 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4703 &tp->TxPhyAddr, GFP_KERNEL);
4704 if (!tp->TxDescArray)
4705 goto out;
4706
4707 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4708 &tp->RxPhyAddr, GFP_KERNEL);
4709 if (!tp->RxDescArray)
4710 goto err_free_tx_0;
4711
4712 retval = rtl8169_init_ring(tp);
4713 if (retval < 0)
4714 goto err_free_rx_1;
4715
4716 rtl_request_firmware(tp);
4717
4718 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED;
4719 retval = request_irq(pci_irq_vector(pdev, 0), rtl8169_interrupt,
4720 irqflags, dev->name, tp);
4721 if (retval < 0)
4722 goto err_release_fw_2;
4723
4724 retval = r8169_phy_connect(tp);
4725 if (retval)
4726 goto err_free_irq;
4727
4728 rtl8169_up(tp);
4729 rtl8169_init_counter_offsets(tp);
4730 netif_start_queue(dev);
4731 out:
4732 pm_runtime_put_sync(&pdev->dev);
4733
4734 return retval;
4735
4736 err_free_irq:
4737 free_irq(pci_irq_vector(pdev, 0), tp);
4738 err_release_fw_2:
4739 rtl_release_firmware(tp);
4740 rtl8169_rx_clear(tp);
4741 err_free_rx_1:
4742 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4743 tp->RxPhyAddr);
4744 tp->RxDescArray = NULL;
4745 err_free_tx_0:
4746 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4747 tp->TxPhyAddr);
4748 tp->TxDescArray = NULL;
4749 goto out;
4750 }
4751
4752 static void
4753 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4754 {
4755 struct rtl8169_private *tp = netdev_priv(dev);
4756 struct pci_dev *pdev = tp->pci_dev;
4757 struct rtl8169_counters *counters = tp->counters;
4758
4759 pm_runtime_get_noresume(&pdev->dev);
4760
4761 netdev_stats_to_stats64(stats, &dev->stats);
4762 dev_fetch_sw_netstats(stats, dev->tstats);
4763
4764 /*
4765 * Fetch additional counter values missing in stats collected by driver
4766 * from tally counters.
4767 */
4768 if (pm_runtime_active(&pdev->dev))
4769 rtl8169_update_counters(tp);
4770
4771 /*
4772 * Subtract values fetched during initalization.
4773 * See rtl8169_init_counter_offsets for a description why we do that.
4774 */
4775 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
4776 le64_to_cpu(tp->tc_offset.tx_errors);
4777 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
4778 le32_to_cpu(tp->tc_offset.tx_multi_collision);
4779 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
4780 le16_to_cpu(tp->tc_offset.tx_aborted);
4781 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) -
4782 le16_to_cpu(tp->tc_offset.rx_missed);
4783
4784 pm_runtime_put_noidle(&pdev->dev);
4785 }
4786
4787 static void rtl8169_net_suspend(struct rtl8169_private *tp)
4788 {
4789 netif_device_detach(tp->dev);
4790
4791 if (netif_running(tp->dev))
4792 rtl8169_down(tp);
4793 }
4794
4795 #ifdef CONFIG_PM
4796
4797 static int rtl8169_net_resume(struct rtl8169_private *tp)
4798 {
4799 rtl_rar_set(tp, tp->dev->dev_addr);
4800
4801 if (tp->TxDescArray)
4802 rtl8169_up(tp);
4803
4804 netif_device_attach(tp->dev);
4805
4806 return 0;
4807 }
4808
4809 static int __maybe_unused rtl8169_suspend(struct device *device)
4810 {
4811 struct rtl8169_private *tp = dev_get_drvdata(device);
4812
4813 rtnl_lock();
4814 rtl8169_net_suspend(tp);
4815 if (!device_may_wakeup(tp_to_dev(tp)))
4816 clk_disable_unprepare(tp->clk);
4817 rtnl_unlock();
4818
4819 return 0;
4820 }
4821
4822 static int __maybe_unused rtl8169_resume(struct device *device)
4823 {
4824 struct rtl8169_private *tp = dev_get_drvdata(device);
4825
4826 if (!device_may_wakeup(tp_to_dev(tp)))
4827 clk_prepare_enable(tp->clk);
4828
4829 /* Reportedly at least Asus X453MA truncates packets otherwise */
4830 if (tp->mac_version == RTL_GIGA_MAC_VER_37)
4831 rtl_init_rxcfg(tp);
4832
4833 return rtl8169_net_resume(tp);
4834 }
4835
4836 static int rtl8169_runtime_suspend(struct device *device)
4837 {
4838 struct rtl8169_private *tp = dev_get_drvdata(device);
4839
4840 if (!tp->TxDescArray) {
4841 netif_device_detach(tp->dev);
4842 return 0;
4843 }
4844
4845 rtnl_lock();
4846 __rtl8169_set_wol(tp, WAKE_PHY);
4847 rtl8169_net_suspend(tp);
4848 rtnl_unlock();
4849
4850 return 0;
4851 }
4852
4853 static int rtl8169_runtime_resume(struct device *device)
4854 {
4855 struct rtl8169_private *tp = dev_get_drvdata(device);
4856
4857 __rtl8169_set_wol(tp, tp->saved_wolopts);
4858
4859 return rtl8169_net_resume(tp);
4860 }
4861
4862 static int rtl8169_runtime_idle(struct device *device)
4863 {
4864 struct rtl8169_private *tp = dev_get_drvdata(device);
4865
4866 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))
4867 pm_schedule_suspend(device, 10000);
4868
4869 return -EBUSY;
4870 }
4871
4872 static const struct dev_pm_ops rtl8169_pm_ops = {
4873 SET_SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume)
4874 SET_RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume,
4875 rtl8169_runtime_idle)
4876 };
4877
4878 #endif /* CONFIG_PM */
4879
4880 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
4881 {
4882 /* WoL fails with 8168b when the receiver is disabled. */
4883 switch (tp->mac_version) {
4884 case RTL_GIGA_MAC_VER_11:
4885 case RTL_GIGA_MAC_VER_12:
4886 case RTL_GIGA_MAC_VER_17:
4887 pci_clear_master(tp->pci_dev);
4888
4889 RTL_W8(tp, ChipCmd, CmdRxEnb);
4890 rtl_pci_commit(tp);
4891 break;
4892 default:
4893 break;
4894 }
4895 }
4896
4897 static void rtl_shutdown(struct pci_dev *pdev)
4898 {
4899 struct rtl8169_private *tp = pci_get_drvdata(pdev);
4900
4901 rtnl_lock();
4902 rtl8169_net_suspend(tp);
4903 rtnl_unlock();
4904
4905 /* Restore original MAC address */
4906 rtl_rar_set(tp, tp->dev->perm_addr);
4907
4908 if (system_state == SYSTEM_POWER_OFF) {
4909 if (tp->saved_wolopts) {
4910 rtl_wol_suspend_quirk(tp);
4911 rtl_wol_shutdown_quirk(tp);
4912 }
4913
4914 pci_wake_from_d3(pdev, true);
4915 pci_set_power_state(pdev, PCI_D3hot);
4916 }
4917 }
4918
4919 static void rtl_remove_one(struct pci_dev *pdev)
4920 {
4921 struct rtl8169_private *tp = pci_get_drvdata(pdev);
4922
4923 if (pci_dev_run_wake(pdev))
4924 pm_runtime_get_noresume(&pdev->dev);
4925
4926 unregister_netdev(tp->dev);
4927
4928 if (r8168_check_dash(tp))
4929 rtl8168_driver_stop(tp);
4930
4931 rtl_release_firmware(tp);
4932
4933 /* restore original MAC address */
4934 rtl_rar_set(tp, tp->dev->perm_addr);
4935 }
4936
4937 static const struct net_device_ops rtl_netdev_ops = {
4938 .ndo_open = rtl_open,
4939 .ndo_stop = rtl8169_close,
4940 .ndo_get_stats64 = rtl8169_get_stats64,
4941 .ndo_start_xmit = rtl8169_start_xmit,
4942 .ndo_features_check = rtl8169_features_check,
4943 .ndo_tx_timeout = rtl8169_tx_timeout,
4944 .ndo_validate_addr = eth_validate_addr,
4945 .ndo_change_mtu = rtl8169_change_mtu,
4946 .ndo_fix_features = rtl8169_fix_features,
4947 .ndo_set_features = rtl8169_set_features,
4948 .ndo_set_mac_address = rtl_set_mac_address,
4949 .ndo_do_ioctl = phy_do_ioctl_running,
4950 .ndo_set_rx_mode = rtl_set_rx_mode,
4951 #ifdef CONFIG_NET_POLL_CONTROLLER
4952 .ndo_poll_controller = rtl8169_netpoll,
4953 #endif
4954
4955 };
4956
4957 static void rtl_set_irq_mask(struct rtl8169_private *tp)
4958 {
4959 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;
4960
4961 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4962 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
4963 else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
4964 /* special workaround needed */
4965 tp->irq_mask |= RxFIFOOver;
4966 else
4967 tp->irq_mask |= RxOverflow;
4968 }
4969
4970 static int rtl_alloc_irq(struct rtl8169_private *tp)
4971 {
4972 unsigned int flags;
4973
4974 switch (tp->mac_version) {
4975 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4976 rtl_unlock_config_regs(tp);
4977 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
4978 rtl_lock_config_regs(tp);
4979 fallthrough;
4980 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
4981 flags = PCI_IRQ_LEGACY;
4982 break;
4983 default:
4984 flags = PCI_IRQ_ALL_TYPES;
4985 break;
4986 }
4987
4988 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
4989 }
4990
4991 static void rtl_read_mac_address(struct rtl8169_private *tp,
4992 u8 mac_addr[ETH_ALEN])
4993 {
4994 /* Get MAC address */
4995 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
4996 u32 value = rtl_eri_read(tp, 0xe0);
4997
4998 mac_addr[0] = (value >> 0) & 0xff;
4999 mac_addr[1] = (value >> 8) & 0xff;
5000 mac_addr[2] = (value >> 16) & 0xff;
5001 mac_addr[3] = (value >> 24) & 0xff;
5002
5003 value = rtl_eri_read(tp, 0xe4);
5004 mac_addr[4] = (value >> 0) & 0xff;
5005 mac_addr[5] = (value >> 8) & 0xff;
5006 } else if (rtl_is_8125(tp)) {
5007 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
5008 }
5009 }
5010
5011 DECLARE_RTL_COND(rtl_link_list_ready_cond)
5012 {
5013 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
5014 }
5015
5016 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)
5017 {
5018 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
5019 }
5020
5021 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
5022 {
5023 struct rtl8169_private *tp = mii_bus->priv;
5024
5025 if (phyaddr > 0)
5026 return -ENODEV;
5027
5028 return rtl_readphy(tp, phyreg);
5029 }
5030
5031 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
5032 int phyreg, u16 val)
5033 {
5034 struct rtl8169_private *tp = mii_bus->priv;
5035
5036 if (phyaddr > 0)
5037 return -ENODEV;
5038
5039 rtl_writephy(tp, phyreg, val);
5040
5041 return 0;
5042 }
5043
5044 static int r8169_mdio_register(struct rtl8169_private *tp)
5045 {
5046 struct pci_dev *pdev = tp->pci_dev;
5047 struct mii_bus *new_bus;
5048 int ret;
5049
5050 new_bus = devm_mdiobus_alloc(&pdev->dev);
5051 if (!new_bus)
5052 return -ENOMEM;
5053
5054 new_bus->name = "r8169";
5055 new_bus->priv = tp;
5056 new_bus->parent = &pdev->dev;
5057 new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
5058 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
5059
5060 new_bus->read = r8169_mdio_read_reg;
5061 new_bus->write = r8169_mdio_write_reg;
5062
5063 ret = devm_mdiobus_register(&pdev->dev, new_bus);
5064 if (ret)
5065 return ret;
5066
5067 tp->phydev = mdiobus_get_phy(new_bus, 0);
5068 if (!tp->phydev) {
5069 return -ENODEV;
5070 } else if (!tp->phydev->drv) {
5071 /* Most chip versions fail with the genphy driver.
5072 * Therefore ensure that the dedicated PHY driver is loaded.
5073 */
5074 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n",
5075 tp->phydev->phy_id);
5076 return -EUNATCH;
5077 }
5078
5079 /* PHY will be woken up in rtl_open() */
5080 phy_suspend(tp->phydev);
5081
5082 return 0;
5083 }
5084
5085 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
5086 {
5087 rtl_enable_rxdvgate(tp);
5088
5089 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5090 msleep(1);
5091 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5092
5093 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5094 r8168g_wait_ll_share_fifo_ready(tp);
5095
5096 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
5097 r8168g_wait_ll_share_fifo_ready(tp);
5098 }
5099
5100 static void rtl_hw_init_8125(struct rtl8169_private *tp)
5101 {
5102 rtl_enable_rxdvgate(tp);
5103
5104 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5105 msleep(1);
5106 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5107
5108 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5109 r8168g_wait_ll_share_fifo_ready(tp);
5110
5111 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
5112 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
5113 r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
5114 r8168g_wait_ll_share_fifo_ready(tp);
5115 }
5116
5117 static void rtl_hw_initialize(struct rtl8169_private *tp)
5118 {
5119 switch (tp->mac_version) {
5120 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
5121 rtl8168ep_stop_cmac(tp);
5122 fallthrough;
5123 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
5124 rtl_hw_init_8168g(tp);
5125 break;
5126 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63:
5127 rtl_hw_init_8125(tp);
5128 break;
5129 default:
5130 break;
5131 }
5132 }
5133
5134 static int rtl_jumbo_max(struct rtl8169_private *tp)
5135 {
5136 /* Non-GBit versions don't support jumbo frames */
5137 if (!tp->supports_gmii)
5138 return 0;
5139
5140 switch (tp->mac_version) {
5141 /* RTL8169 */
5142 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5143 return JUMBO_7K;
5144 /* RTL8168b */
5145 case RTL_GIGA_MAC_VER_11:
5146 case RTL_GIGA_MAC_VER_12:
5147 case RTL_GIGA_MAC_VER_17:
5148 return JUMBO_4K;
5149 /* RTL8168c */
5150 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
5151 return JUMBO_6K;
5152 default:
5153 return JUMBO_9K;
5154 }
5155 }
5156
5157 static void rtl_disable_clk(void *data)
5158 {
5159 clk_disable_unprepare(data);
5160 }
5161
5162 static int rtl_get_ether_clk(struct rtl8169_private *tp)
5163 {
5164 struct device *d = tp_to_dev(tp);
5165 struct clk *clk;
5166 int rc;
5167
5168 clk = devm_clk_get(d, "ether_clk");
5169 if (IS_ERR(clk)) {
5170 rc = PTR_ERR(clk);
5171 if (rc == -ENOENT)
5172 /* clk-core allows NULL (for suspend / resume) */
5173 rc = 0;
5174 else if (rc != -EPROBE_DEFER)
5175 dev_err(d, "failed to get clk: %d\n", rc);
5176 } else {
5177 tp->clk = clk;
5178 rc = clk_prepare_enable(clk);
5179 if (rc)
5180 dev_err(d, "failed to enable clk: %d\n", rc);
5181 else
5182 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
5183 }
5184
5185 return rc;
5186 }
5187
5188 static void rtl_init_mac_address(struct rtl8169_private *tp)
5189 {
5190 struct net_device *dev = tp->dev;
5191 u8 *mac_addr = dev->dev_addr;
5192 int rc;
5193
5194 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
5195 if (!rc)
5196 goto done;
5197
5198 rtl_read_mac_address(tp, mac_addr);
5199 if (is_valid_ether_addr(mac_addr))
5200 goto done;
5201
5202 rtl_read_mac_from_reg(tp, mac_addr, MAC0);
5203 if (is_valid_ether_addr(mac_addr))
5204 goto done;
5205
5206 eth_hw_addr_random(dev);
5207 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
5208 done:
5209 rtl_rar_set(tp, mac_addr);
5210 }
5211
5212 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5213 {
5214 struct rtl8169_private *tp;
5215 int jumbo_max, region, rc;
5216 enum mac_version chipset;
5217 struct net_device *dev;
5218 u16 xid;
5219
5220 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
5221 if (!dev)
5222 return -ENOMEM;
5223
5224 SET_NETDEV_DEV(dev, &pdev->dev);
5225 dev->netdev_ops = &rtl_netdev_ops;
5226 tp = netdev_priv(dev);
5227 tp->dev = dev;
5228 tp->pci_dev = pdev;
5229 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
5230 tp->eee_adv = -1;
5231 tp->ocp_base = OCP_STD_PHY_BASE;
5232
5233 dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev,
5234 struct pcpu_sw_netstats);
5235 if (!dev->tstats)
5236 return -ENOMEM;
5237
5238 /* Get the *optional* external "ether_clk" used on some boards */
5239 rc = rtl_get_ether_clk(tp);
5240 if (rc)
5241 return rc;
5242
5243 /* Disable ASPM completely as that cause random device stop working
5244 * problems as well as full system hangs for some PCIe devices users.
5245 */
5246 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
5247 PCIE_LINK_STATE_L1);
5248 tp->aspm_manageable = !rc;
5249
5250 /* enable device (incl. PCI PM wakeup and hotplug setup) */
5251 rc = pcim_enable_device(pdev);
5252 if (rc < 0) {
5253 dev_err(&pdev->dev, "enable failure\n");
5254 return rc;
5255 }
5256
5257 if (pcim_set_mwi(pdev) < 0)
5258 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
5259
5260 /* use first MMIO region */
5261 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
5262 if (region < 0) {
5263 dev_err(&pdev->dev, "no MMIO resource found\n");
5264 return -ENODEV;
5265 }
5266
5267 /* check for weird/broken PCI region reporting */
5268 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
5269 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
5270 return -ENODEV;
5271 }
5272
5273 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
5274 if (rc < 0) {
5275 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
5276 return rc;
5277 }
5278
5279 tp->mmio_addr = pcim_iomap_table(pdev)[region];
5280
5281 xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf;
5282
5283 /* Identify chip attached to board */
5284 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);
5285 if (chipset == RTL_GIGA_MAC_NONE) {
5286 dev_err(&pdev->dev, "unknown chip XID %03x\n", xid);
5287 return -ENODEV;
5288 }
5289
5290 tp->mac_version = chipset;
5291
5292 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;
5293
5294 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
5295 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
5296 dev->features |= NETIF_F_HIGHDMA;
5297
5298 rtl_init_rxcfg(tp);
5299
5300 rtl8169_irq_mask_and_ack(tp);
5301
5302 rtl_hw_initialize(tp);
5303
5304 rtl_hw_reset(tp);
5305
5306 pci_set_master(pdev);
5307
5308 rc = rtl_alloc_irq(tp);
5309 if (rc < 0) {
5310 dev_err(&pdev->dev, "Can't allocate interrupt\n");
5311 return rc;
5312 }
5313
5314 INIT_WORK(&tp->wk.work, rtl_task);
5315
5316 rtl_init_mac_address(tp);
5317
5318 dev->ethtool_ops = &rtl8169_ethtool_ops;
5319
5320 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
5321
5322 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
5323 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
5324 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
5325 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5326
5327 /*
5328 * Pretend we are using VLANs; This bypasses a nasty bug where
5329 * Interrupts stop flowing on high load on 8110SCd controllers.
5330 */
5331 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5332 /* Disallow toggling */
5333 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
5334
5335 if (rtl_chip_supports_csum_v2(tp))
5336 dev->hw_features |= NETIF_F_IPV6_CSUM;
5337
5338 dev->features |= dev->hw_features;
5339
5340 /* There has been a number of reports that using SG/TSO results in
5341 * tx timeouts. However for a lot of people SG/TSO works fine.
5342 * Therefore disable both features by default, but allow users to
5343 * enable them. Use at own risk!
5344 */
5345 if (rtl_chip_supports_csum_v2(tp)) {
5346 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
5347 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2;
5348 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2;
5349 } else {
5350 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
5351 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1;
5352 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1;
5353 }
5354
5355 dev->hw_features |= NETIF_F_RXALL;
5356 dev->hw_features |= NETIF_F_RXFCS;
5357
5358 /* configure chip for default features */
5359 rtl8169_set_features(dev, dev->features);
5360
5361 jumbo_max = rtl_jumbo_max(tp);
5362 if (jumbo_max)
5363 dev->max_mtu = jumbo_max;
5364
5365 rtl_set_irq_mask(tp);
5366
5367 tp->fw_name = rtl_chip_infos[chipset].fw_name;
5368
5369 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
5370 &tp->counters_phys_addr,
5371 GFP_KERNEL);
5372 if (!tp->counters)
5373 return -ENOMEM;
5374
5375 pci_set_drvdata(pdev, tp);
5376
5377 rc = r8169_mdio_register(tp);
5378 if (rc)
5379 return rc;
5380
5381 /* chip gets powered up in rtl_open() */
5382 rtl_pll_power_down(tp);
5383
5384 rc = register_netdev(dev);
5385 if (rc)
5386 return rc;
5387
5388 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n",
5389 rtl_chip_infos[chipset].name, dev->dev_addr, xid,
5390 pci_irq_vector(pdev, 0));
5391
5392 if (jumbo_max)
5393 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
5394 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
5395 "ok" : "ko");
5396
5397 if (r8168_check_dash(tp)) {
5398 netdev_info(dev, "DASH enabled\n");
5399 rtl8168_driver_start(tp);
5400 }
5401
5402 if (pci_dev_run_wake(pdev))
5403 pm_runtime_put_sync(&pdev->dev);
5404
5405 return 0;
5406 }
5407
5408 static struct pci_driver rtl8169_pci_driver = {
5409 .name = MODULENAME,
5410 .id_table = rtl8169_pci_tbl,
5411 .probe = rtl_init_one,
5412 .remove = rtl_remove_one,
5413 .shutdown = rtl_shutdown,
5414 #ifdef CONFIG_PM
5415 .driver.pm = &rtl8169_pm_ops,
5416 #endif
5417 };
5418
5419 module_pci_driver(rtl8169_pci_driver);
Ubuntu Hirsute Linux kernel mirror