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r8169: use the generic EEE management functions
[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / realtek / r8169_main.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 *
5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
7 * Copyright (c) a lot of people too. Please respect their work.
8 *
9 * See MAINTAINERS file for support contact information.
10 */
11
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/pci.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/ethtool.h>
20 #include <linux/phy.h>
21 #include <linux/if_vlan.h>
22 #include <linux/crc32.h>
23 #include <linux/in.h>
24 #include <linux/io.h>
25 #include <linux/ip.h>
26 #include <linux/tcp.h>
27 #include <linux/interrupt.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/prefetch.h>
31 #include <linux/pci-aspm.h>
32 #include <linux/ipv6.h>
33 #include <net/ip6_checksum.h>
34
35 #include "r8169_firmware.h"
36
37 #define MODULENAME "r8169"
38
39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
47 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
48 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
49 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
50 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
51 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
52 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
53 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
54 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
55 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
56 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
57 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
58
59 #define R8169_MSG_DEFAULT \
60 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
61
62 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
63 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
64 #define MC_FILTER_LIMIT 32
65
66 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
67 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
68
69 #define R8169_REGS_SIZE 256
70 #define R8169_RX_BUF_SIZE (SZ_16K - 1)
71 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
72 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
73 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
74 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
75
76 #define RTL_CFG_NO_GBIT 1
77
78 /* write/read MMIO register */
79 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
80 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
81 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
82 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
83 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
84 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
85
86 enum mac_version {
87 /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */
88 RTL_GIGA_MAC_VER_02,
89 RTL_GIGA_MAC_VER_03,
90 RTL_GIGA_MAC_VER_04,
91 RTL_GIGA_MAC_VER_05,
92 RTL_GIGA_MAC_VER_06,
93 RTL_GIGA_MAC_VER_07,
94 RTL_GIGA_MAC_VER_08,
95 RTL_GIGA_MAC_VER_09,
96 RTL_GIGA_MAC_VER_10,
97 RTL_GIGA_MAC_VER_11,
98 RTL_GIGA_MAC_VER_12,
99 RTL_GIGA_MAC_VER_13,
100 RTL_GIGA_MAC_VER_14,
101 RTL_GIGA_MAC_VER_15,
102 RTL_GIGA_MAC_VER_16,
103 RTL_GIGA_MAC_VER_17,
104 RTL_GIGA_MAC_VER_18,
105 RTL_GIGA_MAC_VER_19,
106 RTL_GIGA_MAC_VER_20,
107 RTL_GIGA_MAC_VER_21,
108 RTL_GIGA_MAC_VER_22,
109 RTL_GIGA_MAC_VER_23,
110 RTL_GIGA_MAC_VER_24,
111 RTL_GIGA_MAC_VER_25,
112 RTL_GIGA_MAC_VER_26,
113 RTL_GIGA_MAC_VER_27,
114 RTL_GIGA_MAC_VER_28,
115 RTL_GIGA_MAC_VER_29,
116 RTL_GIGA_MAC_VER_30,
117 RTL_GIGA_MAC_VER_31,
118 RTL_GIGA_MAC_VER_32,
119 RTL_GIGA_MAC_VER_33,
120 RTL_GIGA_MAC_VER_34,
121 RTL_GIGA_MAC_VER_35,
122 RTL_GIGA_MAC_VER_36,
123 RTL_GIGA_MAC_VER_37,
124 RTL_GIGA_MAC_VER_38,
125 RTL_GIGA_MAC_VER_39,
126 RTL_GIGA_MAC_VER_40,
127 RTL_GIGA_MAC_VER_41,
128 RTL_GIGA_MAC_VER_42,
129 RTL_GIGA_MAC_VER_43,
130 RTL_GIGA_MAC_VER_44,
131 RTL_GIGA_MAC_VER_45,
132 RTL_GIGA_MAC_VER_46,
133 RTL_GIGA_MAC_VER_47,
134 RTL_GIGA_MAC_VER_48,
135 RTL_GIGA_MAC_VER_49,
136 RTL_GIGA_MAC_VER_50,
137 RTL_GIGA_MAC_VER_51,
138 RTL_GIGA_MAC_NONE
139 };
140
141 #define JUMBO_1K ETH_DATA_LEN
142 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
143 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
144 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
145 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
146
147 static const struct {
148 const char *name;
149 const char *fw_name;
150 } rtl_chip_infos[] = {
151 /* PCI devices. */
152 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
153 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
154 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
155 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
156 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
157 /* PCI-E devices. */
158 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
159 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
160 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" },
161 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
162 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
163 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
164 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" },
165 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" },
166 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" },
167 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
168 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
169 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
170 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
171 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
172 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
173 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
174 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
175 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
176 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
177 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
178 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
179 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
180 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
181 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
182 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
183 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
184 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
185 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
186 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
187 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
188 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
189 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
190 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
191 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
192 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
193 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3},
194 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2},
195 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 },
196 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
197 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
198 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
199 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
200 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
201 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
202 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
203 };
204
205 static const struct pci_device_id rtl8169_pci_tbl[] = {
206 { PCI_VDEVICE(REALTEK, 0x2502) },
207 { PCI_VDEVICE(REALTEK, 0x2600) },
208 { PCI_VDEVICE(REALTEK, 0x8129) },
209 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
210 { PCI_VDEVICE(REALTEK, 0x8161) },
211 { PCI_VDEVICE(REALTEK, 0x8167) },
212 { PCI_VDEVICE(REALTEK, 0x8168) },
213 { PCI_VDEVICE(NCUBE, 0x8168) },
214 { PCI_VDEVICE(REALTEK, 0x8169) },
215 { PCI_VENDOR_ID_DLINK, 0x4300,
216 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
217 { PCI_VDEVICE(DLINK, 0x4300) },
218 { PCI_VDEVICE(DLINK, 0x4302) },
219 { PCI_VDEVICE(AT, 0xc107) },
220 { PCI_VDEVICE(USR, 0x0116) },
221 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
222 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
223 {}
224 };
225
226 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
227
228 static struct {
229 u32 msg_enable;
230 } debug = { -1 };
231
232 enum rtl_registers {
233 MAC0 = 0, /* Ethernet hardware address. */
234 MAC4 = 4,
235 MAR0 = 8, /* Multicast filter. */
236 CounterAddrLow = 0x10,
237 CounterAddrHigh = 0x14,
238 TxDescStartAddrLow = 0x20,
239 TxDescStartAddrHigh = 0x24,
240 TxHDescStartAddrLow = 0x28,
241 TxHDescStartAddrHigh = 0x2c,
242 FLASH = 0x30,
243 ERSR = 0x36,
244 ChipCmd = 0x37,
245 TxPoll = 0x38,
246 IntrMask = 0x3c,
247 IntrStatus = 0x3e,
248
249 TxConfig = 0x40,
250 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
251 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
252
253 RxConfig = 0x44,
254 #define RX128_INT_EN (1 << 15) /* 8111c and later */
255 #define RX_MULTI_EN (1 << 14) /* 8111c only */
256 #define RXCFG_FIFO_SHIFT 13
257 /* No threshold before first PCI xfer */
258 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
259 #define RX_EARLY_OFF (1 << 11)
260 #define RXCFG_DMA_SHIFT 8
261 /* Unlimited maximum PCI burst. */
262 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
263
264 RxMissed = 0x4c,
265 Cfg9346 = 0x50,
266 Config0 = 0x51,
267 Config1 = 0x52,
268 Config2 = 0x53,
269 #define PME_SIGNAL (1 << 5) /* 8168c and later */
270
271 Config3 = 0x54,
272 Config4 = 0x55,
273 Config5 = 0x56,
274 PHYAR = 0x60,
275 PHYstatus = 0x6c,
276 RxMaxSize = 0xda,
277 CPlusCmd = 0xe0,
278 IntrMitigate = 0xe2,
279
280 #define RTL_COALESCE_MASK 0x0f
281 #define RTL_COALESCE_SHIFT 4
282 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
283 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
284
285 RxDescAddrLow = 0xe4,
286 RxDescAddrHigh = 0xe8,
287 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
288
289 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
290
291 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
292
293 #define TxPacketMax (8064 >> 7)
294 #define EarlySize 0x27
295
296 FuncEvent = 0xf0,
297 FuncEventMask = 0xf4,
298 FuncPresetState = 0xf8,
299 IBCR0 = 0xf8,
300 IBCR2 = 0xf9,
301 IBIMR0 = 0xfa,
302 IBISR0 = 0xfb,
303 FuncForceEvent = 0xfc,
304 };
305
306 enum rtl8168_8101_registers {
307 CSIDR = 0x64,
308 CSIAR = 0x68,
309 #define CSIAR_FLAG 0x80000000
310 #define CSIAR_WRITE_CMD 0x80000000
311 #define CSIAR_BYTE_ENABLE 0x0000f000
312 #define CSIAR_ADDR_MASK 0x00000fff
313 PMCH = 0x6f,
314 EPHYAR = 0x80,
315 #define EPHYAR_FLAG 0x80000000
316 #define EPHYAR_WRITE_CMD 0x80000000
317 #define EPHYAR_REG_MASK 0x1f
318 #define EPHYAR_REG_SHIFT 16
319 #define EPHYAR_DATA_MASK 0xffff
320 DLLPR = 0xd0,
321 #define PFM_EN (1 << 6)
322 #define TX_10M_PS_EN (1 << 7)
323 DBG_REG = 0xd1,
324 #define FIX_NAK_1 (1 << 4)
325 #define FIX_NAK_2 (1 << 3)
326 TWSI = 0xd2,
327 MCU = 0xd3,
328 #define NOW_IS_OOB (1 << 7)
329 #define TX_EMPTY (1 << 5)
330 #define RX_EMPTY (1 << 4)
331 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
332 #define EN_NDP (1 << 3)
333 #define EN_OOB_RESET (1 << 2)
334 #define LINK_LIST_RDY (1 << 1)
335 EFUSEAR = 0xdc,
336 #define EFUSEAR_FLAG 0x80000000
337 #define EFUSEAR_WRITE_CMD 0x80000000
338 #define EFUSEAR_READ_CMD 0x00000000
339 #define EFUSEAR_REG_MASK 0x03ff
340 #define EFUSEAR_REG_SHIFT 8
341 #define EFUSEAR_DATA_MASK 0xff
342 MISC_1 = 0xf2,
343 #define PFM_D3COLD_EN (1 << 6)
344 };
345
346 enum rtl8168_registers {
347 LED_FREQ = 0x1a,
348 EEE_LED = 0x1b,
349 ERIDR = 0x70,
350 ERIAR = 0x74,
351 #define ERIAR_FLAG 0x80000000
352 #define ERIAR_WRITE_CMD 0x80000000
353 #define ERIAR_READ_CMD 0x00000000
354 #define ERIAR_ADDR_BYTE_ALIGN 4
355 #define ERIAR_TYPE_SHIFT 16
356 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
357 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
358 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
359 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
360 #define ERIAR_MASK_SHIFT 12
361 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
362 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
363 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
364 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
365 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
366 EPHY_RXER_NUM = 0x7c,
367 OCPDR = 0xb0, /* OCP GPHY access */
368 #define OCPDR_WRITE_CMD 0x80000000
369 #define OCPDR_READ_CMD 0x00000000
370 #define OCPDR_REG_MASK 0x7f
371 #define OCPDR_GPHY_REG_SHIFT 16
372 #define OCPDR_DATA_MASK 0xffff
373 OCPAR = 0xb4,
374 #define OCPAR_FLAG 0x80000000
375 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
376 #define OCPAR_GPHY_READ_CMD 0x0000f060
377 GPHY_OCP = 0xb8,
378 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
379 MISC = 0xf0, /* 8168e only. */
380 #define TXPLA_RST (1 << 29)
381 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
382 #define PWM_EN (1 << 22)
383 #define RXDV_GATED_EN (1 << 19)
384 #define EARLY_TALLY_EN (1 << 16)
385 };
386
387 enum rtl_register_content {
388 /* InterruptStatusBits */
389 SYSErr = 0x8000,
390 PCSTimeout = 0x4000,
391 SWInt = 0x0100,
392 TxDescUnavail = 0x0080,
393 RxFIFOOver = 0x0040,
394 LinkChg = 0x0020,
395 RxOverflow = 0x0010,
396 TxErr = 0x0008,
397 TxOK = 0x0004,
398 RxErr = 0x0002,
399 RxOK = 0x0001,
400
401 /* RxStatusDesc */
402 RxRWT = (1 << 22),
403 RxRES = (1 << 21),
404 RxRUNT = (1 << 20),
405 RxCRC = (1 << 19),
406
407 /* ChipCmdBits */
408 StopReq = 0x80,
409 CmdReset = 0x10,
410 CmdRxEnb = 0x08,
411 CmdTxEnb = 0x04,
412 RxBufEmpty = 0x01,
413
414 /* TXPoll register p.5 */
415 HPQ = 0x80, /* Poll cmd on the high prio queue */
416 NPQ = 0x40, /* Poll cmd on the low prio queue */
417 FSWInt = 0x01, /* Forced software interrupt */
418
419 /* Cfg9346Bits */
420 Cfg9346_Lock = 0x00,
421 Cfg9346_Unlock = 0xc0,
422
423 /* rx_mode_bits */
424 AcceptErr = 0x20,
425 AcceptRunt = 0x10,
426 AcceptBroadcast = 0x08,
427 AcceptMulticast = 0x04,
428 AcceptMyPhys = 0x02,
429 AcceptAllPhys = 0x01,
430 #define RX_CONFIG_ACCEPT_MASK 0x3f
431
432 /* TxConfigBits */
433 TxInterFrameGapShift = 24,
434 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
435
436 /* Config1 register p.24 */
437 LEDS1 = (1 << 7),
438 LEDS0 = (1 << 6),
439 Speed_down = (1 << 4),
440 MEMMAP = (1 << 3),
441 IOMAP = (1 << 2),
442 VPD = (1 << 1),
443 PMEnable = (1 << 0), /* Power Management Enable */
444
445 /* Config2 register p. 25 */
446 ClkReqEn = (1 << 7), /* Clock Request Enable */
447 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
448 PCI_Clock_66MHz = 0x01,
449 PCI_Clock_33MHz = 0x00,
450
451 /* Config3 register p.25 */
452 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
453 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
454 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
455 Rdy_to_L23 = (1 << 1), /* L23 Enable */
456 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
457
458 /* Config4 register */
459 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
460
461 /* Config5 register p.27 */
462 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
463 MWF = (1 << 5), /* Accept Multicast wakeup frame */
464 UWF = (1 << 4), /* Accept Unicast wakeup frame */
465 Spi_en = (1 << 3),
466 LanWake = (1 << 1), /* LanWake enable/disable */
467 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
468 ASPM_en = (1 << 0), /* ASPM enable */
469
470 /* CPlusCmd p.31 */
471 EnableBist = (1 << 15), // 8168 8101
472 Mac_dbgo_oe = (1 << 14), // 8168 8101
473 Normal_mode = (1 << 13), // unused
474 Force_half_dup = (1 << 12), // 8168 8101
475 Force_rxflow_en = (1 << 11), // 8168 8101
476 Force_txflow_en = (1 << 10), // 8168 8101
477 Cxpl_dbg_sel = (1 << 9), // 8168 8101
478 ASF = (1 << 8), // 8168 8101
479 PktCntrDisable = (1 << 7), // 8168 8101
480 Mac_dbgo_sel = 0x001c, // 8168
481 RxVlan = (1 << 6),
482 RxChkSum = (1 << 5),
483 PCIDAC = (1 << 4),
484 PCIMulRW = (1 << 3),
485 #define INTT_MASK GENMASK(1, 0)
486 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
487
488 /* rtl8169_PHYstatus */
489 TBI_Enable = 0x80,
490 TxFlowCtrl = 0x40,
491 RxFlowCtrl = 0x20,
492 _1000bpsF = 0x10,
493 _100bps = 0x08,
494 _10bps = 0x04,
495 LinkStatus = 0x02,
496 FullDup = 0x01,
497
498 /* ResetCounterCommand */
499 CounterReset = 0x1,
500
501 /* DumpCounterCommand */
502 CounterDump = 0x8,
503
504 /* magic enable v2 */
505 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
506 };
507
508 enum rtl_desc_bit {
509 /* First doubleword. */
510 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
511 RingEnd = (1 << 30), /* End of descriptor ring */
512 FirstFrag = (1 << 29), /* First segment of a packet */
513 LastFrag = (1 << 28), /* Final segment of a packet */
514 };
515
516 /* Generic case. */
517 enum rtl_tx_desc_bit {
518 /* First doubleword. */
519 TD_LSO = (1 << 27), /* Large Send Offload */
520 #define TD_MSS_MAX 0x07ffu /* MSS value */
521
522 /* Second doubleword. */
523 TxVlanTag = (1 << 17), /* Add VLAN tag */
524 };
525
526 /* 8169, 8168b and 810x except 8102e. */
527 enum rtl_tx_desc_bit_0 {
528 /* First doubleword. */
529 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
530 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
531 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
532 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
533 };
534
535 /* 8102e, 8168c and beyond. */
536 enum rtl_tx_desc_bit_1 {
537 /* First doubleword. */
538 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
539 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
540 #define GTTCPHO_SHIFT 18
541 #define GTTCPHO_MAX 0x7f
542
543 /* Second doubleword. */
544 #define TCPHO_SHIFT 18
545 #define TCPHO_MAX 0x3ff
546 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
547 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
548 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
549 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
550 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
551 };
552
553 enum rtl_rx_desc_bit {
554 /* Rx private */
555 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
556 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
557
558 #define RxProtoUDP (PID1)
559 #define RxProtoTCP (PID0)
560 #define RxProtoIP (PID1 | PID0)
561 #define RxProtoMask RxProtoIP
562
563 IPFail = (1 << 16), /* IP checksum failed */
564 UDPFail = (1 << 15), /* UDP/IP checksum failed */
565 TCPFail = (1 << 14), /* TCP/IP checksum failed */
566 RxVlanTag = (1 << 16), /* VLAN tag available */
567 };
568
569 #define RsvdMask 0x3fffc000
570
571 #define RTL_GSO_MAX_SIZE_V1 32000
572 #define RTL_GSO_MAX_SEGS_V1 24
573 #define RTL_GSO_MAX_SIZE_V2 64000
574 #define RTL_GSO_MAX_SEGS_V2 64
575
576 struct TxDesc {
577 __le32 opts1;
578 __le32 opts2;
579 __le64 addr;
580 };
581
582 struct RxDesc {
583 __le32 opts1;
584 __le32 opts2;
585 __le64 addr;
586 };
587
588 struct ring_info {
589 struct sk_buff *skb;
590 u32 len;
591 };
592
593 struct rtl8169_counters {
594 __le64 tx_packets;
595 __le64 rx_packets;
596 __le64 tx_errors;
597 __le32 rx_errors;
598 __le16 rx_missed;
599 __le16 align_errors;
600 __le32 tx_one_collision;
601 __le32 tx_multi_collision;
602 __le64 rx_unicast;
603 __le64 rx_broadcast;
604 __le32 rx_multicast;
605 __le16 tx_aborted;
606 __le16 tx_underun;
607 };
608
609 struct rtl8169_tc_offsets {
610 bool inited;
611 __le64 tx_errors;
612 __le32 tx_multi_collision;
613 __le16 tx_aborted;
614 };
615
616 enum rtl_flag {
617 RTL_FLAG_TASK_ENABLED = 0,
618 RTL_FLAG_TASK_RESET_PENDING,
619 RTL_FLAG_MAX
620 };
621
622 struct rtl8169_stats {
623 u64 packets;
624 u64 bytes;
625 struct u64_stats_sync syncp;
626 };
627
628 struct rtl8169_private {
629 void __iomem *mmio_addr; /* memory map physical address */
630 struct pci_dev *pci_dev;
631 struct net_device *dev;
632 struct phy_device *phydev;
633 struct napi_struct napi;
634 u32 msg_enable;
635 enum mac_version mac_version;
636 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
637 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
638 u32 dirty_tx;
639 struct rtl8169_stats rx_stats;
640 struct rtl8169_stats tx_stats;
641 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
642 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
643 dma_addr_t TxPhyAddr;
644 dma_addr_t RxPhyAddr;
645 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
646 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
647 u16 cp_cmd;
648 u16 irq_mask;
649 struct clk *clk;
650
651 struct {
652 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
653 struct mutex mutex;
654 struct work_struct work;
655 } wk;
656
657 unsigned irq_enabled:1;
658 unsigned supports_gmii:1;
659 unsigned aspm_manageable:1;
660 dma_addr_t counters_phys_addr;
661 struct rtl8169_counters *counters;
662 struct rtl8169_tc_offsets tc_offset;
663 u32 saved_wolopts;
664
665 const char *fw_name;
666 struct rtl_fw *rtl_fw;
667
668 u32 ocp_base;
669 };
670
671 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
672
673 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
674 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
675 module_param_named(debug, debug.msg_enable, int, 0);
676 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
677 MODULE_SOFTDEP("pre: realtek");
678 MODULE_LICENSE("GPL");
679 MODULE_FIRMWARE(FIRMWARE_8168D_1);
680 MODULE_FIRMWARE(FIRMWARE_8168D_2);
681 MODULE_FIRMWARE(FIRMWARE_8168E_1);
682 MODULE_FIRMWARE(FIRMWARE_8168E_2);
683 MODULE_FIRMWARE(FIRMWARE_8168E_3);
684 MODULE_FIRMWARE(FIRMWARE_8105E_1);
685 MODULE_FIRMWARE(FIRMWARE_8168F_1);
686 MODULE_FIRMWARE(FIRMWARE_8168F_2);
687 MODULE_FIRMWARE(FIRMWARE_8402_1);
688 MODULE_FIRMWARE(FIRMWARE_8411_1);
689 MODULE_FIRMWARE(FIRMWARE_8411_2);
690 MODULE_FIRMWARE(FIRMWARE_8106E_1);
691 MODULE_FIRMWARE(FIRMWARE_8106E_2);
692 MODULE_FIRMWARE(FIRMWARE_8168G_2);
693 MODULE_FIRMWARE(FIRMWARE_8168G_3);
694 MODULE_FIRMWARE(FIRMWARE_8168H_1);
695 MODULE_FIRMWARE(FIRMWARE_8168H_2);
696 MODULE_FIRMWARE(FIRMWARE_8107E_1);
697 MODULE_FIRMWARE(FIRMWARE_8107E_2);
698
699 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
700 {
701 return &tp->pci_dev->dev;
702 }
703
704 static void rtl_lock_work(struct rtl8169_private *tp)
705 {
706 mutex_lock(&tp->wk.mutex);
707 }
708
709 static void rtl_unlock_work(struct rtl8169_private *tp)
710 {
711 mutex_unlock(&tp->wk.mutex);
712 }
713
714 static void rtl_lock_config_regs(struct rtl8169_private *tp)
715 {
716 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
717 }
718
719 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
720 {
721 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
722 }
723
724 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
725 {
726 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
727 PCI_EXP_DEVCTL_READRQ, force);
728 }
729
730 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
731 {
732 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
733 tp->mac_version != RTL_GIGA_MAC_VER_39;
734 }
735
736 static bool rtl_supports_eee(struct rtl8169_private *tp)
737 {
738 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
739 tp->mac_version != RTL_GIGA_MAC_VER_37 &&
740 tp->mac_version != RTL_GIGA_MAC_VER_39;
741 }
742
743 struct rtl_cond {
744 bool (*check)(struct rtl8169_private *);
745 const char *msg;
746 };
747
748 static void rtl_udelay(unsigned int d)
749 {
750 udelay(d);
751 }
752
753 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
754 void (*delay)(unsigned int), unsigned int d, int n,
755 bool high)
756 {
757 int i;
758
759 for (i = 0; i < n; i++) {
760 if (c->check(tp) == high)
761 return true;
762 delay(d);
763 }
764 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
765 c->msg, !high, n, d);
766 return false;
767 }
768
769 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
770 const struct rtl_cond *c,
771 unsigned int d, int n)
772 {
773 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
774 }
775
776 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
777 const struct rtl_cond *c,
778 unsigned int d, int n)
779 {
780 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
781 }
782
783 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
784 const struct rtl_cond *c,
785 unsigned int d, int n)
786 {
787 return rtl_loop_wait(tp, c, msleep, d, n, true);
788 }
789
790 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
791 const struct rtl_cond *c,
792 unsigned int d, int n)
793 {
794 return rtl_loop_wait(tp, c, msleep, d, n, false);
795 }
796
797 #define DECLARE_RTL_COND(name) \
798 static bool name ## _check(struct rtl8169_private *); \
799 \
800 static const struct rtl_cond name = { \
801 .check = name ## _check, \
802 .msg = #name \
803 }; \
804 \
805 static bool name ## _check(struct rtl8169_private *tp)
806
807 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
808 {
809 if (reg & 0xffff0001) {
810 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
811 return true;
812 }
813 return false;
814 }
815
816 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
817 {
818 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
819 }
820
821 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
822 {
823 if (rtl_ocp_reg_failure(tp, reg))
824 return;
825
826 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
827
828 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
829 }
830
831 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
832 {
833 if (rtl_ocp_reg_failure(tp, reg))
834 return 0;
835
836 RTL_W32(tp, GPHY_OCP, reg << 15);
837
838 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
839 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
840 }
841
842 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
843 {
844 if (rtl_ocp_reg_failure(tp, reg))
845 return;
846
847 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
848 }
849
850 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
851 {
852 if (rtl_ocp_reg_failure(tp, reg))
853 return 0;
854
855 RTL_W32(tp, OCPDR, reg << 15);
856
857 return RTL_R32(tp, OCPDR);
858 }
859
860 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
861 u16 set)
862 {
863 u16 data = r8168_mac_ocp_read(tp, reg);
864
865 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
866 }
867
868 #define OCP_STD_PHY_BASE 0xa400
869
870 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
871 {
872 if (reg == 0x1f) {
873 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
874 return;
875 }
876
877 if (tp->ocp_base != OCP_STD_PHY_BASE)
878 reg -= 0x10;
879
880 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
881 }
882
883 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
884 {
885 if (tp->ocp_base != OCP_STD_PHY_BASE)
886 reg -= 0x10;
887
888 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
889 }
890
891 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
892 {
893 if (reg == 0x1f) {
894 tp->ocp_base = value << 4;
895 return;
896 }
897
898 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
899 }
900
901 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
902 {
903 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
904 }
905
906 DECLARE_RTL_COND(rtl_phyar_cond)
907 {
908 return RTL_R32(tp, PHYAR) & 0x80000000;
909 }
910
911 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
912 {
913 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
914
915 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
916 /*
917 * According to hardware specs a 20us delay is required after write
918 * complete indication, but before sending next command.
919 */
920 udelay(20);
921 }
922
923 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
924 {
925 int value;
926
927 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
928
929 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
930 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
931
932 /*
933 * According to hardware specs a 20us delay is required after read
934 * complete indication, but before sending next command.
935 */
936 udelay(20);
937
938 return value;
939 }
940
941 DECLARE_RTL_COND(rtl_ocpar_cond)
942 {
943 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
944 }
945
946 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
947 {
948 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
949 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
950 RTL_W32(tp, EPHY_RXER_NUM, 0);
951
952 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
953 }
954
955 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
956 {
957 r8168dp_1_mdio_access(tp, reg,
958 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
959 }
960
961 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
962 {
963 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
964
965 mdelay(1);
966 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
967 RTL_W32(tp, EPHY_RXER_NUM, 0);
968
969 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
970 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
971 }
972
973 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
974
975 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
976 {
977 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
978 }
979
980 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
981 {
982 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
983 }
984
985 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
986 {
987 r8168dp_2_mdio_start(tp);
988
989 r8169_mdio_write(tp, reg, value);
990
991 r8168dp_2_mdio_stop(tp);
992 }
993
994 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
995 {
996 int value;
997
998 r8168dp_2_mdio_start(tp);
999
1000 value = r8169_mdio_read(tp, reg);
1001
1002 r8168dp_2_mdio_stop(tp);
1003
1004 return value;
1005 }
1006
1007 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1008 {
1009 switch (tp->mac_version) {
1010 case RTL_GIGA_MAC_VER_27:
1011 r8168dp_1_mdio_write(tp, location, val);
1012 break;
1013 case RTL_GIGA_MAC_VER_28:
1014 case RTL_GIGA_MAC_VER_31:
1015 r8168dp_2_mdio_write(tp, location, val);
1016 break;
1017 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1018 r8168g_mdio_write(tp, location, val);
1019 break;
1020 default:
1021 r8169_mdio_write(tp, location, val);
1022 break;
1023 }
1024 }
1025
1026 static int rtl_readphy(struct rtl8169_private *tp, int location)
1027 {
1028 switch (tp->mac_version) {
1029 case RTL_GIGA_MAC_VER_27:
1030 return r8168dp_1_mdio_read(tp, location);
1031 case RTL_GIGA_MAC_VER_28:
1032 case RTL_GIGA_MAC_VER_31:
1033 return r8168dp_2_mdio_read(tp, location);
1034 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1035 return r8168g_mdio_read(tp, location);
1036 default:
1037 return r8169_mdio_read(tp, location);
1038 }
1039 }
1040
1041 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1042 {
1043 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1044 }
1045
1046 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1047 {
1048 int val;
1049
1050 val = rtl_readphy(tp, reg_addr);
1051 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1052 }
1053
1054 DECLARE_RTL_COND(rtl_ephyar_cond)
1055 {
1056 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1057 }
1058
1059 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1060 {
1061 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1062 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1063
1064 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1065
1066 udelay(10);
1067 }
1068
1069 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1070 {
1071 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1072
1073 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1074 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1075 }
1076
1077 DECLARE_RTL_COND(rtl_eriar_cond)
1078 {
1079 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1080 }
1081
1082 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1083 u32 val, int type)
1084 {
1085 BUG_ON((addr & 3) || (mask == 0));
1086 RTL_W32(tp, ERIDR, val);
1087 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1088
1089 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1090 }
1091
1092 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1093 u32 val)
1094 {
1095 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1096 }
1097
1098 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1099 {
1100 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1101
1102 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1103 RTL_R32(tp, ERIDR) : ~0;
1104 }
1105
1106 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1107 {
1108 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1109 }
1110
1111 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1112 u32 m)
1113 {
1114 u32 val;
1115
1116 val = rtl_eri_read(tp, addr);
1117 rtl_eri_write(tp, addr, mask, (val & ~m) | p);
1118 }
1119
1120 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,
1121 u32 p)
1122 {
1123 rtl_w0w1_eri(tp, addr, mask, p, 0);
1124 }
1125
1126 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
1127 u32 m)
1128 {
1129 rtl_w0w1_eri(tp, addr, mask, 0, m);
1130 }
1131
1132 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1133 {
1134 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1135 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1136 RTL_R32(tp, OCPDR) : ~0;
1137 }
1138
1139 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1140 {
1141 return _rtl_eri_read(tp, reg, ERIAR_OOB);
1142 }
1143
1144 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1145 u32 data)
1146 {
1147 RTL_W32(tp, OCPDR, data);
1148 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1149 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1150 }
1151
1152 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1153 u32 data)
1154 {
1155 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1156 data, ERIAR_OOB);
1157 }
1158
1159 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1160 {
1161 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1162
1163 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1164 }
1165
1166 #define OOB_CMD_RESET 0x00
1167 #define OOB_CMD_DRIVER_START 0x05
1168 #define OOB_CMD_DRIVER_STOP 0x06
1169
1170 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1171 {
1172 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1173 }
1174
1175 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1176 {
1177 u16 reg;
1178
1179 reg = rtl8168_get_ocp_reg(tp);
1180
1181 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1182 }
1183
1184 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1185 {
1186 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1187 }
1188
1189 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1190 {
1191 return RTL_R8(tp, IBISR0) & 0x20;
1192 }
1193
1194 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1195 {
1196 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1197 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1198 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1199 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1200 }
1201
1202 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1203 {
1204 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1205 rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1206 }
1207
1208 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1209 {
1210 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1211 r8168ep_ocp_write(tp, 0x01, 0x30,
1212 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1213 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1214 }
1215
1216 static void rtl8168_driver_start(struct rtl8169_private *tp)
1217 {
1218 switch (tp->mac_version) {
1219 case RTL_GIGA_MAC_VER_27:
1220 case RTL_GIGA_MAC_VER_28:
1221 case RTL_GIGA_MAC_VER_31:
1222 rtl8168dp_driver_start(tp);
1223 break;
1224 case RTL_GIGA_MAC_VER_49:
1225 case RTL_GIGA_MAC_VER_50:
1226 case RTL_GIGA_MAC_VER_51:
1227 rtl8168ep_driver_start(tp);
1228 break;
1229 default:
1230 BUG();
1231 break;
1232 }
1233 }
1234
1235 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1236 {
1237 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1238 rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1239 }
1240
1241 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1242 {
1243 rtl8168ep_stop_cmac(tp);
1244 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1245 r8168ep_ocp_write(tp, 0x01, 0x30,
1246 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1247 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1248 }
1249
1250 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1251 {
1252 switch (tp->mac_version) {
1253 case RTL_GIGA_MAC_VER_27:
1254 case RTL_GIGA_MAC_VER_28:
1255 case RTL_GIGA_MAC_VER_31:
1256 rtl8168dp_driver_stop(tp);
1257 break;
1258 case RTL_GIGA_MAC_VER_49:
1259 case RTL_GIGA_MAC_VER_50:
1260 case RTL_GIGA_MAC_VER_51:
1261 rtl8168ep_driver_stop(tp);
1262 break;
1263 default:
1264 BUG();
1265 break;
1266 }
1267 }
1268
1269 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1270 {
1271 u16 reg = rtl8168_get_ocp_reg(tp);
1272
1273 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1274 }
1275
1276 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1277 {
1278 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1279 }
1280
1281 static bool r8168_check_dash(struct rtl8169_private *tp)
1282 {
1283 switch (tp->mac_version) {
1284 case RTL_GIGA_MAC_VER_27:
1285 case RTL_GIGA_MAC_VER_28:
1286 case RTL_GIGA_MAC_VER_31:
1287 return r8168dp_check_dash(tp);
1288 case RTL_GIGA_MAC_VER_49:
1289 case RTL_GIGA_MAC_VER_50:
1290 case RTL_GIGA_MAC_VER_51:
1291 return r8168ep_check_dash(tp);
1292 default:
1293 return false;
1294 }
1295 }
1296
1297 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1298 {
1299 rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1300 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1301 }
1302
1303 DECLARE_RTL_COND(rtl_efusear_cond)
1304 {
1305 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1306 }
1307
1308 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1309 {
1310 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1311
1312 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1313 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1314 }
1315
1316 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1317 {
1318 RTL_W16(tp, IntrStatus, bits);
1319 }
1320
1321 static void rtl_irq_disable(struct rtl8169_private *tp)
1322 {
1323 RTL_W16(tp, IntrMask, 0);
1324 tp->irq_enabled = 0;
1325 }
1326
1327 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1328 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1329 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1330
1331 static void rtl_irq_enable(struct rtl8169_private *tp)
1332 {
1333 tp->irq_enabled = 1;
1334 RTL_W16(tp, IntrMask, tp->irq_mask);
1335 }
1336
1337 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1338 {
1339 rtl_irq_disable(tp);
1340 rtl_ack_events(tp, 0xffff);
1341 /* PCI commit */
1342 RTL_R8(tp, ChipCmd);
1343 }
1344
1345 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1346 {
1347 struct net_device *dev = tp->dev;
1348 struct phy_device *phydev = tp->phydev;
1349
1350 if (!netif_running(dev))
1351 return;
1352
1353 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1354 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1355 if (phydev->speed == SPEED_1000) {
1356 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1357 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1358 } else if (phydev->speed == SPEED_100) {
1359 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1360 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1361 } else {
1362 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1363 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1364 }
1365 rtl_reset_packet_filter(tp);
1366 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1367 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1368 if (phydev->speed == SPEED_1000) {
1369 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1370 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1371 } else {
1372 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1373 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1374 }
1375 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1376 if (phydev->speed == SPEED_10) {
1377 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1378 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1379 } else {
1380 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1381 }
1382 }
1383 }
1384
1385 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1386
1387 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1388 {
1389 struct rtl8169_private *tp = netdev_priv(dev);
1390
1391 rtl_lock_work(tp);
1392 wol->supported = WAKE_ANY;
1393 wol->wolopts = tp->saved_wolopts;
1394 rtl_unlock_work(tp);
1395 }
1396
1397 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1398 {
1399 unsigned int i, tmp;
1400 static const struct {
1401 u32 opt;
1402 u16 reg;
1403 u8 mask;
1404 } cfg[] = {
1405 { WAKE_PHY, Config3, LinkUp },
1406 { WAKE_UCAST, Config5, UWF },
1407 { WAKE_BCAST, Config5, BWF },
1408 { WAKE_MCAST, Config5, MWF },
1409 { WAKE_ANY, Config5, LanWake },
1410 { WAKE_MAGIC, Config3, MagicPacket }
1411 };
1412 u8 options;
1413
1414 rtl_unlock_config_regs(tp);
1415
1416 if (rtl_is_8168evl_up(tp)) {
1417 tmp = ARRAY_SIZE(cfg) - 1;
1418 if (wolopts & WAKE_MAGIC)
1419 rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
1420 MagicPacket_v2);
1421 else
1422 rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
1423 MagicPacket_v2);
1424 } else {
1425 tmp = ARRAY_SIZE(cfg);
1426 }
1427
1428 for (i = 0; i < tmp; i++) {
1429 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1430 if (wolopts & cfg[i].opt)
1431 options |= cfg[i].mask;
1432 RTL_W8(tp, cfg[i].reg, options);
1433 }
1434
1435 switch (tp->mac_version) {
1436 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1437 options = RTL_R8(tp, Config1) & ~PMEnable;
1438 if (wolopts)
1439 options |= PMEnable;
1440 RTL_W8(tp, Config1, options);
1441 break;
1442 case RTL_GIGA_MAC_VER_34:
1443 case RTL_GIGA_MAC_VER_37:
1444 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_51:
1445 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1446 if (wolopts)
1447 options |= PME_SIGNAL;
1448 RTL_W8(tp, Config2, options);
1449 break;
1450 default:
1451 break;
1452 }
1453
1454 rtl_lock_config_regs(tp);
1455
1456 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1457 }
1458
1459 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1460 {
1461 struct rtl8169_private *tp = netdev_priv(dev);
1462 struct device *d = tp_to_dev(tp);
1463
1464 if (wol->wolopts & ~WAKE_ANY)
1465 return -EINVAL;
1466
1467 pm_runtime_get_noresume(d);
1468
1469 rtl_lock_work(tp);
1470
1471 tp->saved_wolopts = wol->wolopts;
1472
1473 if (pm_runtime_active(d))
1474 __rtl8169_set_wol(tp, tp->saved_wolopts);
1475
1476 rtl_unlock_work(tp);
1477
1478 pm_runtime_put_noidle(d);
1479
1480 return 0;
1481 }
1482
1483 static void rtl8169_get_drvinfo(struct net_device *dev,
1484 struct ethtool_drvinfo *info)
1485 {
1486 struct rtl8169_private *tp = netdev_priv(dev);
1487 struct rtl_fw *rtl_fw = tp->rtl_fw;
1488
1489 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1490 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1491 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1492 if (rtl_fw)
1493 strlcpy(info->fw_version, rtl_fw->version,
1494 sizeof(info->fw_version));
1495 }
1496
1497 static int rtl8169_get_regs_len(struct net_device *dev)
1498 {
1499 return R8169_REGS_SIZE;
1500 }
1501
1502 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1503 netdev_features_t features)
1504 {
1505 struct rtl8169_private *tp = netdev_priv(dev);
1506
1507 if (dev->mtu > TD_MSS_MAX)
1508 features &= ~NETIF_F_ALL_TSO;
1509
1510 if (dev->mtu > JUMBO_1K &&
1511 tp->mac_version > RTL_GIGA_MAC_VER_06)
1512 features &= ~NETIF_F_IP_CSUM;
1513
1514 return features;
1515 }
1516
1517 static int rtl8169_set_features(struct net_device *dev,
1518 netdev_features_t features)
1519 {
1520 struct rtl8169_private *tp = netdev_priv(dev);
1521 u32 rx_config;
1522
1523 rtl_lock_work(tp);
1524
1525 rx_config = RTL_R32(tp, RxConfig);
1526 if (features & NETIF_F_RXALL)
1527 rx_config |= (AcceptErr | AcceptRunt);
1528 else
1529 rx_config &= ~(AcceptErr | AcceptRunt);
1530
1531 RTL_W32(tp, RxConfig, rx_config);
1532
1533 if (features & NETIF_F_RXCSUM)
1534 tp->cp_cmd |= RxChkSum;
1535 else
1536 tp->cp_cmd &= ~RxChkSum;
1537
1538 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1539 tp->cp_cmd |= RxVlan;
1540 else
1541 tp->cp_cmd &= ~RxVlan;
1542
1543 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1544 RTL_R16(tp, CPlusCmd);
1545
1546 rtl_unlock_work(tp);
1547
1548 return 0;
1549 }
1550
1551 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1552 {
1553 return (skb_vlan_tag_present(skb)) ?
1554 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1555 }
1556
1557 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1558 {
1559 u32 opts2 = le32_to_cpu(desc->opts2);
1560
1561 if (opts2 & RxVlanTag)
1562 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1563 }
1564
1565 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1566 void *p)
1567 {
1568 struct rtl8169_private *tp = netdev_priv(dev);
1569 u32 __iomem *data = tp->mmio_addr;
1570 u32 *dw = p;
1571 int i;
1572
1573 rtl_lock_work(tp);
1574 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1575 memcpy_fromio(dw++, data++, 4);
1576 rtl_unlock_work(tp);
1577 }
1578
1579 static u32 rtl8169_get_msglevel(struct net_device *dev)
1580 {
1581 struct rtl8169_private *tp = netdev_priv(dev);
1582
1583 return tp->msg_enable;
1584 }
1585
1586 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1587 {
1588 struct rtl8169_private *tp = netdev_priv(dev);
1589
1590 tp->msg_enable = value;
1591 }
1592
1593 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1594 "tx_packets",
1595 "rx_packets",
1596 "tx_errors",
1597 "rx_errors",
1598 "rx_missed",
1599 "align_errors",
1600 "tx_single_collisions",
1601 "tx_multi_collisions",
1602 "unicast",
1603 "broadcast",
1604 "multicast",
1605 "tx_aborted",
1606 "tx_underrun",
1607 };
1608
1609 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1610 {
1611 switch (sset) {
1612 case ETH_SS_STATS:
1613 return ARRAY_SIZE(rtl8169_gstrings);
1614 default:
1615 return -EOPNOTSUPP;
1616 }
1617 }
1618
1619 DECLARE_RTL_COND(rtl_counters_cond)
1620 {
1621 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1622 }
1623
1624 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1625 {
1626 dma_addr_t paddr = tp->counters_phys_addr;
1627 u32 cmd;
1628
1629 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1630 RTL_R32(tp, CounterAddrHigh);
1631 cmd = (u64)paddr & DMA_BIT_MASK(32);
1632 RTL_W32(tp, CounterAddrLow, cmd);
1633 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1634
1635 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1636 }
1637
1638 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1639 {
1640 /*
1641 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1642 * tally counters.
1643 */
1644 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1645 return true;
1646
1647 return rtl8169_do_counters(tp, CounterReset);
1648 }
1649
1650 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1651 {
1652 u8 val = RTL_R8(tp, ChipCmd);
1653
1654 /*
1655 * Some chips are unable to dump tally counters when the receiver
1656 * is disabled. If 0xff chip may be in a PCI power-save state.
1657 */
1658 if (!(val & CmdRxEnb) || val == 0xff)
1659 return true;
1660
1661 return rtl8169_do_counters(tp, CounterDump);
1662 }
1663
1664 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1665 {
1666 struct rtl8169_counters *counters = tp->counters;
1667 bool ret = false;
1668
1669 /*
1670 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1671 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1672 * reset by a power cycle, while the counter values collected by the
1673 * driver are reset at every driver unload/load cycle.
1674 *
1675 * To make sure the HW values returned by @get_stats64 match the SW
1676 * values, we collect the initial values at first open(*) and use them
1677 * as offsets to normalize the values returned by @get_stats64.
1678 *
1679 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1680 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1681 * set at open time by rtl_hw_start.
1682 */
1683
1684 if (tp->tc_offset.inited)
1685 return true;
1686
1687 /* If both, reset and update fail, propagate to caller. */
1688 if (rtl8169_reset_counters(tp))
1689 ret = true;
1690
1691 if (rtl8169_update_counters(tp))
1692 ret = true;
1693
1694 tp->tc_offset.tx_errors = counters->tx_errors;
1695 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1696 tp->tc_offset.tx_aborted = counters->tx_aborted;
1697 tp->tc_offset.inited = true;
1698
1699 return ret;
1700 }
1701
1702 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1703 struct ethtool_stats *stats, u64 *data)
1704 {
1705 struct rtl8169_private *tp = netdev_priv(dev);
1706 struct device *d = tp_to_dev(tp);
1707 struct rtl8169_counters *counters = tp->counters;
1708
1709 ASSERT_RTNL();
1710
1711 pm_runtime_get_noresume(d);
1712
1713 if (pm_runtime_active(d))
1714 rtl8169_update_counters(tp);
1715
1716 pm_runtime_put_noidle(d);
1717
1718 data[0] = le64_to_cpu(counters->tx_packets);
1719 data[1] = le64_to_cpu(counters->rx_packets);
1720 data[2] = le64_to_cpu(counters->tx_errors);
1721 data[3] = le32_to_cpu(counters->rx_errors);
1722 data[4] = le16_to_cpu(counters->rx_missed);
1723 data[5] = le16_to_cpu(counters->align_errors);
1724 data[6] = le32_to_cpu(counters->tx_one_collision);
1725 data[7] = le32_to_cpu(counters->tx_multi_collision);
1726 data[8] = le64_to_cpu(counters->rx_unicast);
1727 data[9] = le64_to_cpu(counters->rx_broadcast);
1728 data[10] = le32_to_cpu(counters->rx_multicast);
1729 data[11] = le16_to_cpu(counters->tx_aborted);
1730 data[12] = le16_to_cpu(counters->tx_underun);
1731 }
1732
1733 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1734 {
1735 switch(stringset) {
1736 case ETH_SS_STATS:
1737 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1738 break;
1739 }
1740 }
1741
1742 /*
1743 * Interrupt coalescing
1744 *
1745 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1746 * > 8169, 8168 and 810x line of chipsets
1747 *
1748 * 8169, 8168, and 8136(810x) serial chipsets support it.
1749 *
1750 * > 2 - the Tx timer unit at gigabit speed
1751 *
1752 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1753 * (0xe0) bit 1 and bit 0.
1754 *
1755 * For 8169
1756 * bit[1:0] \ speed 1000M 100M 10M
1757 * 0 0 320ns 2.56us 40.96us
1758 * 0 1 2.56us 20.48us 327.7us
1759 * 1 0 5.12us 40.96us 655.4us
1760 * 1 1 10.24us 81.92us 1.31ms
1761 *
1762 * For the other
1763 * bit[1:0] \ speed 1000M 100M 10M
1764 * 0 0 5us 2.56us 40.96us
1765 * 0 1 40us 20.48us 327.7us
1766 * 1 0 80us 40.96us 655.4us
1767 * 1 1 160us 81.92us 1.31ms
1768 */
1769
1770 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1771 struct rtl_coalesce_scale {
1772 /* Rx / Tx */
1773 u32 nsecs[2];
1774 };
1775
1776 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1777 struct rtl_coalesce_info {
1778 u32 speed;
1779 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
1780 };
1781
1782 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1783 #define rxtx_x1822(r, t) { \
1784 {{(r), (t)}}, \
1785 {{(r)*8, (t)*8}}, \
1786 {{(r)*8*2, (t)*8*2}}, \
1787 {{(r)*8*2*2, (t)*8*2*2}}, \
1788 }
1789 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1790 /* speed delays: rx00 tx00 */
1791 { SPEED_10, rxtx_x1822(40960, 40960) },
1792 { SPEED_100, rxtx_x1822( 2560, 2560) },
1793 { SPEED_1000, rxtx_x1822( 320, 320) },
1794 { 0 },
1795 };
1796
1797 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1798 /* speed delays: rx00 tx00 */
1799 { SPEED_10, rxtx_x1822(40960, 40960) },
1800 { SPEED_100, rxtx_x1822( 2560, 2560) },
1801 { SPEED_1000, rxtx_x1822( 5000, 5000) },
1802 { 0 },
1803 };
1804 #undef rxtx_x1822
1805
1806 /* get rx/tx scale vector corresponding to current speed */
1807 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1808 {
1809 struct rtl8169_private *tp = netdev_priv(dev);
1810 const struct rtl_coalesce_info *ci;
1811
1812 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1813 ci = rtl_coalesce_info_8169;
1814 else
1815 ci = rtl_coalesce_info_8168_8136;
1816
1817 for (; ci->speed; ci++) {
1818 if (tp->phydev->speed == ci->speed)
1819 return ci;
1820 }
1821
1822 return ERR_PTR(-ELNRNG);
1823 }
1824
1825 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1826 {
1827 struct rtl8169_private *tp = netdev_priv(dev);
1828 const struct rtl_coalesce_info *ci;
1829 const struct rtl_coalesce_scale *scale;
1830 struct {
1831 u32 *max_frames;
1832 u32 *usecs;
1833 } coal_settings [] = {
1834 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1835 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1836 }, *p = coal_settings;
1837 int i;
1838 u16 w;
1839
1840 memset(ec, 0, sizeof(*ec));
1841
1842 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1843 ci = rtl_coalesce_info(dev);
1844 if (IS_ERR(ci))
1845 return PTR_ERR(ci);
1846
1847 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1848
1849 /* read IntrMitigate and adjust according to scale */
1850 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1851 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1852 w >>= RTL_COALESCE_SHIFT;
1853 *p->usecs = w & RTL_COALESCE_MASK;
1854 }
1855
1856 for (i = 0; i < 2; i++) {
1857 p = coal_settings + i;
1858 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1859
1860 /*
1861 * ethtool_coalesce says it is illegal to set both usecs and
1862 * max_frames to 0.
1863 */
1864 if (!*p->usecs && !*p->max_frames)
1865 *p->max_frames = 1;
1866 }
1867
1868 return 0;
1869 }
1870
1871 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1872 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1873 struct net_device *dev, u32 nsec, u16 *cp01)
1874 {
1875 const struct rtl_coalesce_info *ci;
1876 u16 i;
1877
1878 ci = rtl_coalesce_info(dev);
1879 if (IS_ERR(ci))
1880 return ERR_CAST(ci);
1881
1882 for (i = 0; i < 4; i++) {
1883 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1884 ci->scalev[i].nsecs[1]);
1885 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1886 *cp01 = i;
1887 return &ci->scalev[i];
1888 }
1889 }
1890
1891 return ERR_PTR(-EINVAL);
1892 }
1893
1894 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1895 {
1896 struct rtl8169_private *tp = netdev_priv(dev);
1897 const struct rtl_coalesce_scale *scale;
1898 struct {
1899 u32 frames;
1900 u32 usecs;
1901 } coal_settings [] = {
1902 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1903 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1904 }, *p = coal_settings;
1905 u16 w = 0, cp01;
1906 int i;
1907
1908 scale = rtl_coalesce_choose_scale(dev,
1909 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1910 if (IS_ERR(scale))
1911 return PTR_ERR(scale);
1912
1913 for (i = 0; i < 2; i++, p++) {
1914 u32 units;
1915
1916 /*
1917 * accept max_frames=1 we returned in rtl_get_coalesce.
1918 * accept it not only when usecs=0 because of e.g. the following scenario:
1919 *
1920 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1921 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1922 * - then user does `ethtool -C eth0 rx-usecs 100`
1923 *
1924 * since ethtool sends to kernel whole ethtool_coalesce
1925 * settings, if we do not handle rx_usecs=!0, rx_frames=1
1926 * we'll reject it below in `frames % 4 != 0`.
1927 */
1928 if (p->frames == 1) {
1929 p->frames = 0;
1930 }
1931
1932 units = p->usecs * 1000 / scale->nsecs[i];
1933 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
1934 return -EINVAL;
1935
1936 w <<= RTL_COALESCE_SHIFT;
1937 w |= units;
1938 w <<= RTL_COALESCE_SHIFT;
1939 w |= p->frames >> 2;
1940 }
1941
1942 rtl_lock_work(tp);
1943
1944 RTL_W16(tp, IntrMitigate, swab16(w));
1945
1946 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1947 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1948 RTL_R16(tp, CPlusCmd);
1949
1950 rtl_unlock_work(tp);
1951
1952 return 0;
1953 }
1954
1955 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
1956 {
1957 struct rtl8169_private *tp = netdev_priv(dev);
1958 struct device *d = tp_to_dev(tp);
1959 int ret;
1960
1961 if (!rtl_supports_eee(tp))
1962 return -EOPNOTSUPP;
1963
1964 pm_runtime_get_noresume(d);
1965
1966 if (!pm_runtime_active(d)) {
1967 ret = -EOPNOTSUPP;
1968 } else {
1969 ret = phy_ethtool_get_eee(tp->phydev, data);
1970 }
1971
1972 pm_runtime_put_noidle(d);
1973
1974 return ret;
1975 }
1976
1977 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
1978 {
1979 struct rtl8169_private *tp = netdev_priv(dev);
1980 struct device *d = tp_to_dev(tp);
1981 int ret;
1982
1983 if (!rtl_supports_eee(tp))
1984 return -EOPNOTSUPP;
1985
1986 pm_runtime_get_noresume(d);
1987
1988 if (!pm_runtime_active(d)) {
1989 ret = -EOPNOTSUPP;
1990 goto out;
1991 }
1992
1993 if (dev->phydev->autoneg == AUTONEG_DISABLE ||
1994 dev->phydev->duplex != DUPLEX_FULL) {
1995 ret = -EPROTONOSUPPORT;
1996 goto out;
1997 }
1998
1999 ret = phy_ethtool_set_eee(tp->phydev, data);
2000 out:
2001 pm_runtime_put_noidle(d);
2002 return ret;
2003 }
2004
2005 static const struct ethtool_ops rtl8169_ethtool_ops = {
2006 .get_drvinfo = rtl8169_get_drvinfo,
2007 .get_regs_len = rtl8169_get_regs_len,
2008 .get_link = ethtool_op_get_link,
2009 .get_coalesce = rtl_get_coalesce,
2010 .set_coalesce = rtl_set_coalesce,
2011 .get_msglevel = rtl8169_get_msglevel,
2012 .set_msglevel = rtl8169_set_msglevel,
2013 .get_regs = rtl8169_get_regs,
2014 .get_wol = rtl8169_get_wol,
2015 .set_wol = rtl8169_set_wol,
2016 .get_strings = rtl8169_get_strings,
2017 .get_sset_count = rtl8169_get_sset_count,
2018 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2019 .get_ts_info = ethtool_op_get_ts_info,
2020 .nway_reset = phy_ethtool_nway_reset,
2021 .get_eee = rtl8169_get_eee,
2022 .set_eee = rtl8169_set_eee,
2023 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2024 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2025 };
2026
2027 static void rtl_enable_eee(struct rtl8169_private *tp)
2028 {
2029 struct phy_device *phydev = tp->phydev;
2030 int supported = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
2031
2032 if (supported > 0)
2033 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, supported);
2034 }
2035
2036 static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2037 {
2038 /*
2039 * The driver currently handles the 8168Bf and the 8168Be identically
2040 * but they can be identified more specifically through the test below
2041 * if needed:
2042 *
2043 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2044 *
2045 * Same thing for the 8101Eb and the 8101Ec:
2046 *
2047 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2048 */
2049 static const struct rtl_mac_info {
2050 u16 mask;
2051 u16 val;
2052 u16 mac_version;
2053 } mac_info[] = {
2054 /* 8168EP family. */
2055 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2056 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2057 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2058
2059 /* 8168H family. */
2060 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2061 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2062
2063 /* 8168G family. */
2064 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2065 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2066 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2067 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2068
2069 /* 8168F family. */
2070 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2071 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2072 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2073
2074 /* 8168E family. */
2075 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2076 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2077 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2078
2079 /* 8168D family. */
2080 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2081 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2082
2083 /* 8168DP family. */
2084 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2085 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2086 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2087
2088 /* 8168C family. */
2089 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2090 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2091 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2092 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2093 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2094 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2095 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2096
2097 /* 8168B family. */
2098 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2099 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2100 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2101
2102 /* 8101 family. */
2103 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2104 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2105 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2106 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2107 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2108 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2109 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2110 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2111 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2112 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2113 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2114 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2115 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2116 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2117 /* FIXME: where did these entries come from ? -- FR */
2118 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2119 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2120
2121 /* 8110 family. */
2122 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2123 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2124 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2125 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2126 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2127
2128 /* Catch-all */
2129 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
2130 };
2131 const struct rtl_mac_info *p = mac_info;
2132 u16 reg = RTL_R32(tp, TxConfig) >> 20;
2133
2134 while ((reg & p->mask) != p->val)
2135 p++;
2136 tp->mac_version = p->mac_version;
2137
2138 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2139 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2140 } else if (!tp->supports_gmii) {
2141 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2142 tp->mac_version = RTL_GIGA_MAC_VER_43;
2143 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2144 tp->mac_version = RTL_GIGA_MAC_VER_47;
2145 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2146 tp->mac_version = RTL_GIGA_MAC_VER_48;
2147 }
2148 }
2149
2150 struct phy_reg {
2151 u16 reg;
2152 u16 val;
2153 };
2154
2155 static void __rtl_writephy_batch(struct rtl8169_private *tp,
2156 const struct phy_reg *regs, int len)
2157 {
2158 while (len-- > 0) {
2159 rtl_writephy(tp, regs->reg, regs->val);
2160 regs++;
2161 }
2162 }
2163
2164 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a))
2165
2166 static void rtl_release_firmware(struct rtl8169_private *tp)
2167 {
2168 if (tp->rtl_fw) {
2169 rtl_fw_release_firmware(tp->rtl_fw);
2170 kfree(tp->rtl_fw);
2171 tp->rtl_fw = NULL;
2172 }
2173 }
2174
2175 static void rtl_apply_firmware(struct rtl8169_private *tp)
2176 {
2177 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2178 if (tp->rtl_fw)
2179 rtl_fw_write_firmware(tp, tp->rtl_fw);
2180 }
2181
2182 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2183 {
2184 if (rtl_readphy(tp, reg) != val)
2185 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2186 else
2187 rtl_apply_firmware(tp);
2188 }
2189
2190 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2191 {
2192 /* Adjust EEE LED frequency */
2193 if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2194 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2195
2196 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);
2197 }
2198
2199 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2200 {
2201 struct phy_device *phydev = tp->phydev;
2202
2203 phy_write(phydev, 0x1f, 0x0007);
2204 phy_write(phydev, 0x1e, 0x0020);
2205 phy_set_bits(phydev, 0x15, BIT(8));
2206
2207 phy_write(phydev, 0x1f, 0x0005);
2208 phy_write(phydev, 0x05, 0x8b85);
2209 phy_set_bits(phydev, 0x06, BIT(13));
2210
2211 phy_write(phydev, 0x1f, 0x0000);
2212 }
2213
2214 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2215 {
2216 phy_modify_paged(tp->phydev, 0x0a43, 0x11, 0, BIT(4));
2217 }
2218
2219 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2220 {
2221 static const struct phy_reg phy_reg_init[] = {
2222 { 0x1f, 0x0001 },
2223 { 0x06, 0x006e },
2224 { 0x08, 0x0708 },
2225 { 0x15, 0x4000 },
2226 { 0x18, 0x65c7 },
2227
2228 { 0x1f, 0x0001 },
2229 { 0x03, 0x00a1 },
2230 { 0x02, 0x0008 },
2231 { 0x01, 0x0120 },
2232 { 0x00, 0x1000 },
2233 { 0x04, 0x0800 },
2234 { 0x04, 0x0000 },
2235
2236 { 0x03, 0xff41 },
2237 { 0x02, 0xdf60 },
2238 { 0x01, 0x0140 },
2239 { 0x00, 0x0077 },
2240 { 0x04, 0x7800 },
2241 { 0x04, 0x7000 },
2242
2243 { 0x03, 0x802f },
2244 { 0x02, 0x4f02 },
2245 { 0x01, 0x0409 },
2246 { 0x00, 0xf0f9 },
2247 { 0x04, 0x9800 },
2248 { 0x04, 0x9000 },
2249
2250 { 0x03, 0xdf01 },
2251 { 0x02, 0xdf20 },
2252 { 0x01, 0xff95 },
2253 { 0x00, 0xba00 },
2254 { 0x04, 0xa800 },
2255 { 0x04, 0xa000 },
2256
2257 { 0x03, 0xff41 },
2258 { 0x02, 0xdf20 },
2259 { 0x01, 0x0140 },
2260 { 0x00, 0x00bb },
2261 { 0x04, 0xb800 },
2262 { 0x04, 0xb000 },
2263
2264 { 0x03, 0xdf41 },
2265 { 0x02, 0xdc60 },
2266 { 0x01, 0x6340 },
2267 { 0x00, 0x007d },
2268 { 0x04, 0xd800 },
2269 { 0x04, 0xd000 },
2270
2271 { 0x03, 0xdf01 },
2272 { 0x02, 0xdf20 },
2273 { 0x01, 0x100a },
2274 { 0x00, 0xa0ff },
2275 { 0x04, 0xf800 },
2276 { 0x04, 0xf000 },
2277
2278 { 0x1f, 0x0000 },
2279 { 0x0b, 0x0000 },
2280 { 0x00, 0x9200 }
2281 };
2282
2283 rtl_writephy_batch(tp, phy_reg_init);
2284 }
2285
2286 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2287 {
2288 static const struct phy_reg phy_reg_init[] = {
2289 { 0x1f, 0x0002 },
2290 { 0x01, 0x90d0 },
2291 { 0x1f, 0x0000 }
2292 };
2293
2294 rtl_writephy_batch(tp, phy_reg_init);
2295 }
2296
2297 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2298 {
2299 struct pci_dev *pdev = tp->pci_dev;
2300
2301 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2302 (pdev->subsystem_device != 0xe000))
2303 return;
2304
2305 rtl_writephy(tp, 0x1f, 0x0001);
2306 rtl_writephy(tp, 0x10, 0xf01b);
2307 rtl_writephy(tp, 0x1f, 0x0000);
2308 }
2309
2310 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2311 {
2312 static const struct phy_reg phy_reg_init[] = {
2313 { 0x1f, 0x0001 },
2314 { 0x04, 0x0000 },
2315 { 0x03, 0x00a1 },
2316 { 0x02, 0x0008 },
2317 { 0x01, 0x0120 },
2318 { 0x00, 0x1000 },
2319 { 0x04, 0x0800 },
2320 { 0x04, 0x9000 },
2321 { 0x03, 0x802f },
2322 { 0x02, 0x4f02 },
2323 { 0x01, 0x0409 },
2324 { 0x00, 0xf099 },
2325 { 0x04, 0x9800 },
2326 { 0x04, 0xa000 },
2327 { 0x03, 0xdf01 },
2328 { 0x02, 0xdf20 },
2329 { 0x01, 0xff95 },
2330 { 0x00, 0xba00 },
2331 { 0x04, 0xa800 },
2332 { 0x04, 0xf000 },
2333 { 0x03, 0xdf01 },
2334 { 0x02, 0xdf20 },
2335 { 0x01, 0x101a },
2336 { 0x00, 0xa0ff },
2337 { 0x04, 0xf800 },
2338 { 0x04, 0x0000 },
2339 { 0x1f, 0x0000 },
2340
2341 { 0x1f, 0x0001 },
2342 { 0x10, 0xf41b },
2343 { 0x14, 0xfb54 },
2344 { 0x18, 0xf5c7 },
2345 { 0x1f, 0x0000 },
2346
2347 { 0x1f, 0x0001 },
2348 { 0x17, 0x0cc0 },
2349 { 0x1f, 0x0000 }
2350 };
2351
2352 rtl_writephy_batch(tp, phy_reg_init);
2353
2354 rtl8169scd_hw_phy_config_quirk(tp);
2355 }
2356
2357 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2358 {
2359 static const struct phy_reg phy_reg_init[] = {
2360 { 0x1f, 0x0001 },
2361 { 0x04, 0x0000 },
2362 { 0x03, 0x00a1 },
2363 { 0x02, 0x0008 },
2364 { 0x01, 0x0120 },
2365 { 0x00, 0x1000 },
2366 { 0x04, 0x0800 },
2367 { 0x04, 0x9000 },
2368 { 0x03, 0x802f },
2369 { 0x02, 0x4f02 },
2370 { 0x01, 0x0409 },
2371 { 0x00, 0xf099 },
2372 { 0x04, 0x9800 },
2373 { 0x04, 0xa000 },
2374 { 0x03, 0xdf01 },
2375 { 0x02, 0xdf20 },
2376 { 0x01, 0xff95 },
2377 { 0x00, 0xba00 },
2378 { 0x04, 0xa800 },
2379 { 0x04, 0xf000 },
2380 { 0x03, 0xdf01 },
2381 { 0x02, 0xdf20 },
2382 { 0x01, 0x101a },
2383 { 0x00, 0xa0ff },
2384 { 0x04, 0xf800 },
2385 { 0x04, 0x0000 },
2386 { 0x1f, 0x0000 },
2387
2388 { 0x1f, 0x0001 },
2389 { 0x0b, 0x8480 },
2390 { 0x1f, 0x0000 },
2391
2392 { 0x1f, 0x0001 },
2393 { 0x18, 0x67c7 },
2394 { 0x04, 0x2000 },
2395 { 0x03, 0x002f },
2396 { 0x02, 0x4360 },
2397 { 0x01, 0x0109 },
2398 { 0x00, 0x3022 },
2399 { 0x04, 0x2800 },
2400 { 0x1f, 0x0000 },
2401
2402 { 0x1f, 0x0001 },
2403 { 0x17, 0x0cc0 },
2404 { 0x1f, 0x0000 }
2405 };
2406
2407 rtl_writephy_batch(tp, phy_reg_init);
2408 }
2409
2410 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2411 {
2412 static const struct phy_reg phy_reg_init[] = {
2413 { 0x10, 0xf41b },
2414 { 0x1f, 0x0000 }
2415 };
2416
2417 rtl_writephy(tp, 0x1f, 0x0001);
2418 rtl_patchphy(tp, 0x16, 1 << 0);
2419
2420 rtl_writephy_batch(tp, phy_reg_init);
2421 }
2422
2423 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2424 {
2425 static const struct phy_reg phy_reg_init[] = {
2426 { 0x1f, 0x0001 },
2427 { 0x10, 0xf41b },
2428 { 0x1f, 0x0000 }
2429 };
2430
2431 rtl_writephy_batch(tp, phy_reg_init);
2432 }
2433
2434 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2435 {
2436 static const struct phy_reg phy_reg_init[] = {
2437 { 0x1f, 0x0000 },
2438 { 0x1d, 0x0f00 },
2439 { 0x1f, 0x0002 },
2440 { 0x0c, 0x1ec8 },
2441 { 0x1f, 0x0000 }
2442 };
2443
2444 rtl_writephy_batch(tp, phy_reg_init);
2445 }
2446
2447 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2448 {
2449 static const struct phy_reg phy_reg_init[] = {
2450 { 0x1f, 0x0001 },
2451 { 0x1d, 0x3d98 },
2452 { 0x1f, 0x0000 }
2453 };
2454
2455 rtl_writephy(tp, 0x1f, 0x0000);
2456 rtl_patchphy(tp, 0x14, 1 << 5);
2457 rtl_patchphy(tp, 0x0d, 1 << 5);
2458
2459 rtl_writephy_batch(tp, phy_reg_init);
2460 }
2461
2462 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2463 {
2464 static const struct phy_reg phy_reg_init[] = {
2465 { 0x1f, 0x0001 },
2466 { 0x12, 0x2300 },
2467 { 0x1f, 0x0002 },
2468 { 0x00, 0x88d4 },
2469 { 0x01, 0x82b1 },
2470 { 0x03, 0x7002 },
2471 { 0x08, 0x9e30 },
2472 { 0x09, 0x01f0 },
2473 { 0x0a, 0x5500 },
2474 { 0x0c, 0x00c8 },
2475 { 0x1f, 0x0003 },
2476 { 0x12, 0xc096 },
2477 { 0x16, 0x000a },
2478 { 0x1f, 0x0000 },
2479 { 0x1f, 0x0000 },
2480 { 0x09, 0x2000 },
2481 { 0x09, 0x0000 }
2482 };
2483
2484 rtl_writephy_batch(tp, phy_reg_init);
2485
2486 rtl_patchphy(tp, 0x14, 1 << 5);
2487 rtl_patchphy(tp, 0x0d, 1 << 5);
2488 rtl_writephy(tp, 0x1f, 0x0000);
2489 }
2490
2491 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2492 {
2493 static const struct phy_reg phy_reg_init[] = {
2494 { 0x1f, 0x0001 },
2495 { 0x12, 0x2300 },
2496 { 0x03, 0x802f },
2497 { 0x02, 0x4f02 },
2498 { 0x01, 0x0409 },
2499 { 0x00, 0xf099 },
2500 { 0x04, 0x9800 },
2501 { 0x04, 0x9000 },
2502 { 0x1d, 0x3d98 },
2503 { 0x1f, 0x0002 },
2504 { 0x0c, 0x7eb8 },
2505 { 0x06, 0x0761 },
2506 { 0x1f, 0x0003 },
2507 { 0x16, 0x0f0a },
2508 { 0x1f, 0x0000 }
2509 };
2510
2511 rtl_writephy_batch(tp, phy_reg_init);
2512
2513 rtl_patchphy(tp, 0x16, 1 << 0);
2514 rtl_patchphy(tp, 0x14, 1 << 5);
2515 rtl_patchphy(tp, 0x0d, 1 << 5);
2516 rtl_writephy(tp, 0x1f, 0x0000);
2517 }
2518
2519 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2520 {
2521 static const struct phy_reg phy_reg_init[] = {
2522 { 0x1f, 0x0001 },
2523 { 0x12, 0x2300 },
2524 { 0x1d, 0x3d98 },
2525 { 0x1f, 0x0002 },
2526 { 0x0c, 0x7eb8 },
2527 { 0x06, 0x5461 },
2528 { 0x1f, 0x0003 },
2529 { 0x16, 0x0f0a },
2530 { 0x1f, 0x0000 }
2531 };
2532
2533 rtl_writephy_batch(tp, phy_reg_init);
2534
2535 rtl_patchphy(tp, 0x16, 1 << 0);
2536 rtl_patchphy(tp, 0x14, 1 << 5);
2537 rtl_patchphy(tp, 0x0d, 1 << 5);
2538 rtl_writephy(tp, 0x1f, 0x0000);
2539 }
2540
2541 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2542 {
2543 rtl8168c_3_hw_phy_config(tp);
2544 }
2545
2546 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
2547 /* Channel Estimation */
2548 { 0x1f, 0x0001 },
2549 { 0x06, 0x4064 },
2550 { 0x07, 0x2863 },
2551 { 0x08, 0x059c },
2552 { 0x09, 0x26b4 },
2553 { 0x0a, 0x6a19 },
2554 { 0x0b, 0xdcc8 },
2555 { 0x10, 0xf06d },
2556 { 0x14, 0x7f68 },
2557 { 0x18, 0x7fd9 },
2558 { 0x1c, 0xf0ff },
2559 { 0x1d, 0x3d9c },
2560 { 0x1f, 0x0003 },
2561 { 0x12, 0xf49f },
2562 { 0x13, 0x070b },
2563 { 0x1a, 0x05ad },
2564 { 0x14, 0x94c0 },
2565
2566 /*
2567 * Tx Error Issue
2568 * Enhance line driver power
2569 */
2570 { 0x1f, 0x0002 },
2571 { 0x06, 0x5561 },
2572 { 0x1f, 0x0005 },
2573 { 0x05, 0x8332 },
2574 { 0x06, 0x5561 },
2575
2576 /*
2577 * Can not link to 1Gbps with bad cable
2578 * Decrease SNR threshold form 21.07dB to 19.04dB
2579 */
2580 { 0x1f, 0x0001 },
2581 { 0x17, 0x0cc0 },
2582
2583 { 0x1f, 0x0000 },
2584 { 0x0d, 0xf880 }
2585 };
2586
2587 static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = {
2588 { 0x1f, 0x0002 },
2589 { 0x05, 0x669a },
2590 { 0x1f, 0x0005 },
2591 { 0x05, 0x8330 },
2592 { 0x06, 0x669a },
2593 { 0x1f, 0x0002 }
2594 };
2595
2596 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2597 {
2598 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2599
2600 /*
2601 * Rx Error Issue
2602 * Fine Tune Switching regulator parameter
2603 */
2604 rtl_writephy(tp, 0x1f, 0x0002);
2605 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2606 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2607
2608 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2609 int val;
2610
2611 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2612
2613 val = rtl_readphy(tp, 0x0d);
2614
2615 if ((val & 0x00ff) != 0x006c) {
2616 static const u32 set[] = {
2617 0x0065, 0x0066, 0x0067, 0x0068,
2618 0x0069, 0x006a, 0x006b, 0x006c
2619 };
2620 int i;
2621
2622 rtl_writephy(tp, 0x1f, 0x0002);
2623
2624 val &= 0xff00;
2625 for (i = 0; i < ARRAY_SIZE(set); i++)
2626 rtl_writephy(tp, 0x0d, val | set[i]);
2627 }
2628 } else {
2629 static const struct phy_reg phy_reg_init[] = {
2630 { 0x1f, 0x0002 },
2631 { 0x05, 0x6662 },
2632 { 0x1f, 0x0005 },
2633 { 0x05, 0x8330 },
2634 { 0x06, 0x6662 }
2635 };
2636
2637 rtl_writephy_batch(tp, phy_reg_init);
2638 }
2639
2640 /* RSET couple improve */
2641 rtl_writephy(tp, 0x1f, 0x0002);
2642 rtl_patchphy(tp, 0x0d, 0x0300);
2643 rtl_patchphy(tp, 0x0f, 0x0010);
2644
2645 /* Fine tune PLL performance */
2646 rtl_writephy(tp, 0x1f, 0x0002);
2647 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2648 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2649
2650 rtl_writephy(tp, 0x1f, 0x0005);
2651 rtl_writephy(tp, 0x05, 0x001b);
2652
2653 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2654
2655 rtl_writephy(tp, 0x1f, 0x0000);
2656 }
2657
2658 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2659 {
2660 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2661
2662 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2663 int val;
2664
2665 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2666
2667 val = rtl_readphy(tp, 0x0d);
2668 if ((val & 0x00ff) != 0x006c) {
2669 static const u32 set[] = {
2670 0x0065, 0x0066, 0x0067, 0x0068,
2671 0x0069, 0x006a, 0x006b, 0x006c
2672 };
2673 int i;
2674
2675 rtl_writephy(tp, 0x1f, 0x0002);
2676
2677 val &= 0xff00;
2678 for (i = 0; i < ARRAY_SIZE(set); i++)
2679 rtl_writephy(tp, 0x0d, val | set[i]);
2680 }
2681 } else {
2682 static const struct phy_reg phy_reg_init[] = {
2683 { 0x1f, 0x0002 },
2684 { 0x05, 0x2642 },
2685 { 0x1f, 0x0005 },
2686 { 0x05, 0x8330 },
2687 { 0x06, 0x2642 }
2688 };
2689
2690 rtl_writephy_batch(tp, phy_reg_init);
2691 }
2692
2693 /* Fine tune PLL performance */
2694 rtl_writephy(tp, 0x1f, 0x0002);
2695 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2696 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2697
2698 /* Switching regulator Slew rate */
2699 rtl_writephy(tp, 0x1f, 0x0002);
2700 rtl_patchphy(tp, 0x0f, 0x0017);
2701
2702 rtl_writephy(tp, 0x1f, 0x0005);
2703 rtl_writephy(tp, 0x05, 0x001b);
2704
2705 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2706
2707 rtl_writephy(tp, 0x1f, 0x0000);
2708 }
2709
2710 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2711 {
2712 static const struct phy_reg phy_reg_init[] = {
2713 { 0x1f, 0x0002 },
2714 { 0x10, 0x0008 },
2715 { 0x0d, 0x006c },
2716
2717 { 0x1f, 0x0000 },
2718 { 0x0d, 0xf880 },
2719
2720 { 0x1f, 0x0001 },
2721 { 0x17, 0x0cc0 },
2722
2723 { 0x1f, 0x0001 },
2724 { 0x0b, 0xa4d8 },
2725 { 0x09, 0x281c },
2726 { 0x07, 0x2883 },
2727 { 0x0a, 0x6b35 },
2728 { 0x1d, 0x3da4 },
2729 { 0x1c, 0xeffd },
2730 { 0x14, 0x7f52 },
2731 { 0x18, 0x7fc6 },
2732 { 0x08, 0x0601 },
2733 { 0x06, 0x4063 },
2734 { 0x10, 0xf074 },
2735 { 0x1f, 0x0003 },
2736 { 0x13, 0x0789 },
2737 { 0x12, 0xf4bd },
2738 { 0x1a, 0x04fd },
2739 { 0x14, 0x84b0 },
2740 { 0x1f, 0x0000 },
2741 { 0x00, 0x9200 },
2742
2743 { 0x1f, 0x0005 },
2744 { 0x01, 0x0340 },
2745 { 0x1f, 0x0001 },
2746 { 0x04, 0x4000 },
2747 { 0x03, 0x1d21 },
2748 { 0x02, 0x0c32 },
2749 { 0x01, 0x0200 },
2750 { 0x00, 0x5554 },
2751 { 0x04, 0x4800 },
2752 { 0x04, 0x4000 },
2753 { 0x04, 0xf000 },
2754 { 0x03, 0xdf01 },
2755 { 0x02, 0xdf20 },
2756 { 0x01, 0x101a },
2757 { 0x00, 0xa0ff },
2758 { 0x04, 0xf800 },
2759 { 0x04, 0xf000 },
2760 { 0x1f, 0x0000 },
2761
2762 { 0x1f, 0x0007 },
2763 { 0x1e, 0x0023 },
2764 { 0x16, 0x0000 },
2765 { 0x1f, 0x0000 }
2766 };
2767
2768 rtl_writephy_batch(tp, phy_reg_init);
2769 }
2770
2771 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2772 {
2773 static const struct phy_reg phy_reg_init[] = {
2774 { 0x1f, 0x0001 },
2775 { 0x17, 0x0cc0 },
2776
2777 { 0x1f, 0x0007 },
2778 { 0x1e, 0x002d },
2779 { 0x18, 0x0040 },
2780 { 0x1f, 0x0000 }
2781 };
2782
2783 rtl_writephy_batch(tp, phy_reg_init);
2784 rtl_patchphy(tp, 0x0d, 1 << 5);
2785 }
2786
2787 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2788 {
2789 static const struct phy_reg phy_reg_init[] = {
2790 /* Enable Delay cap */
2791 { 0x1f, 0x0005 },
2792 { 0x05, 0x8b80 },
2793 { 0x06, 0xc896 },
2794 { 0x1f, 0x0000 },
2795
2796 /* Channel estimation fine tune */
2797 { 0x1f, 0x0001 },
2798 { 0x0b, 0x6c20 },
2799 { 0x07, 0x2872 },
2800 { 0x1c, 0xefff },
2801 { 0x1f, 0x0003 },
2802 { 0x14, 0x6420 },
2803 { 0x1f, 0x0000 },
2804
2805 /* Update PFM & 10M TX idle timer */
2806 { 0x1f, 0x0007 },
2807 { 0x1e, 0x002f },
2808 { 0x15, 0x1919 },
2809 { 0x1f, 0x0000 },
2810
2811 { 0x1f, 0x0007 },
2812 { 0x1e, 0x00ac },
2813 { 0x18, 0x0006 },
2814 { 0x1f, 0x0000 }
2815 };
2816
2817 rtl_apply_firmware(tp);
2818
2819 rtl_writephy_batch(tp, phy_reg_init);
2820
2821 /* DCO enable for 10M IDLE Power */
2822 rtl_writephy(tp, 0x1f, 0x0007);
2823 rtl_writephy(tp, 0x1e, 0x0023);
2824 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
2825 rtl_writephy(tp, 0x1f, 0x0000);
2826
2827 /* For impedance matching */
2828 rtl_writephy(tp, 0x1f, 0x0002);
2829 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
2830 rtl_writephy(tp, 0x1f, 0x0000);
2831
2832 /* PHY auto speed down */
2833 rtl_writephy(tp, 0x1f, 0x0007);
2834 rtl_writephy(tp, 0x1e, 0x002d);
2835 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
2836 rtl_writephy(tp, 0x1f, 0x0000);
2837 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
2838
2839 rtl_writephy(tp, 0x1f, 0x0005);
2840 rtl_writephy(tp, 0x05, 0x8b86);
2841 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
2842 rtl_writephy(tp, 0x1f, 0x0000);
2843
2844 rtl_writephy(tp, 0x1f, 0x0005);
2845 rtl_writephy(tp, 0x05, 0x8b85);
2846 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
2847 rtl_writephy(tp, 0x1f, 0x0007);
2848 rtl_writephy(tp, 0x1e, 0x0020);
2849 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
2850 rtl_writephy(tp, 0x1f, 0x0006);
2851 rtl_writephy(tp, 0x00, 0x5a00);
2852 rtl_writephy(tp, 0x1f, 0x0000);
2853 rtl_writephy(tp, 0x0d, 0x0007);
2854 rtl_writephy(tp, 0x0e, 0x003c);
2855 rtl_writephy(tp, 0x0d, 0x4007);
2856 rtl_writephy(tp, 0x0e, 0x0000);
2857 rtl_writephy(tp, 0x0d, 0x0000);
2858 }
2859
2860 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
2861 {
2862 const u16 w[] = {
2863 addr[0] | (addr[1] << 8),
2864 addr[2] | (addr[3] << 8),
2865 addr[4] | (addr[5] << 8)
2866 };
2867
2868 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
2869 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
2870 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
2871 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
2872 }
2873
2874 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2875 {
2876 static const struct phy_reg phy_reg_init[] = {
2877 /* Enable Delay cap */
2878 { 0x1f, 0x0004 },
2879 { 0x1f, 0x0007 },
2880 { 0x1e, 0x00ac },
2881 { 0x18, 0x0006 },
2882 { 0x1f, 0x0002 },
2883 { 0x1f, 0x0000 },
2884 { 0x1f, 0x0000 },
2885
2886 /* Channel estimation fine tune */
2887 { 0x1f, 0x0003 },
2888 { 0x09, 0xa20f },
2889 { 0x1f, 0x0000 },
2890 { 0x1f, 0x0000 },
2891
2892 /* Green Setting */
2893 { 0x1f, 0x0005 },
2894 { 0x05, 0x8b5b },
2895 { 0x06, 0x9222 },
2896 { 0x05, 0x8b6d },
2897 { 0x06, 0x8000 },
2898 { 0x05, 0x8b76 },
2899 { 0x06, 0x8000 },
2900 { 0x1f, 0x0000 }
2901 };
2902
2903 rtl_apply_firmware(tp);
2904
2905 rtl_writephy_batch(tp, phy_reg_init);
2906
2907 /* For 4-corner performance improve */
2908 rtl_writephy(tp, 0x1f, 0x0005);
2909 rtl_writephy(tp, 0x05, 0x8b80);
2910 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
2911 rtl_writephy(tp, 0x1f, 0x0000);
2912
2913 /* PHY auto speed down */
2914 rtl_writephy(tp, 0x1f, 0x0004);
2915 rtl_writephy(tp, 0x1f, 0x0007);
2916 rtl_writephy(tp, 0x1e, 0x002d);
2917 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
2918 rtl_writephy(tp, 0x1f, 0x0002);
2919 rtl_writephy(tp, 0x1f, 0x0000);
2920 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
2921
2922 /* improve 10M EEE waveform */
2923 rtl_writephy(tp, 0x1f, 0x0005);
2924 rtl_writephy(tp, 0x05, 0x8b86);
2925 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
2926 rtl_writephy(tp, 0x1f, 0x0000);
2927
2928 /* Improve 2-pair detection performance */
2929 rtl_writephy(tp, 0x1f, 0x0005);
2930 rtl_writephy(tp, 0x05, 0x8b85);
2931 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
2932 rtl_writephy(tp, 0x1f, 0x0000);
2933
2934 rtl8168f_config_eee_phy(tp);
2935 rtl_enable_eee(tp);
2936
2937 /* Green feature */
2938 rtl_writephy(tp, 0x1f, 0x0003);
2939 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
2940 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
2941 rtl_writephy(tp, 0x1f, 0x0000);
2942 rtl_writephy(tp, 0x1f, 0x0005);
2943 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
2944 rtl_writephy(tp, 0x1f, 0x0000);
2945
2946 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
2947 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
2948 }
2949
2950 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
2951 {
2952 /* For 4-corner performance improve */
2953 rtl_writephy(tp, 0x1f, 0x0005);
2954 rtl_writephy(tp, 0x05, 0x8b80);
2955 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
2956 rtl_writephy(tp, 0x1f, 0x0000);
2957
2958 /* PHY auto speed down */
2959 rtl_writephy(tp, 0x1f, 0x0007);
2960 rtl_writephy(tp, 0x1e, 0x002d);
2961 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
2962 rtl_writephy(tp, 0x1f, 0x0000);
2963 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
2964
2965 /* Improve 10M EEE waveform */
2966 rtl_writephy(tp, 0x1f, 0x0005);
2967 rtl_writephy(tp, 0x05, 0x8b86);
2968 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
2969 rtl_writephy(tp, 0x1f, 0x0000);
2970
2971 rtl8168f_config_eee_phy(tp);
2972 rtl_enable_eee(tp);
2973 }
2974
2975 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
2976 {
2977 static const struct phy_reg phy_reg_init[] = {
2978 /* Channel estimation fine tune */
2979 { 0x1f, 0x0003 },
2980 { 0x09, 0xa20f },
2981 { 0x1f, 0x0000 },
2982
2983 /* Modify green table for giga & fnet */
2984 { 0x1f, 0x0005 },
2985 { 0x05, 0x8b55 },
2986 { 0x06, 0x0000 },
2987 { 0x05, 0x8b5e },
2988 { 0x06, 0x0000 },
2989 { 0x05, 0x8b67 },
2990 { 0x06, 0x0000 },
2991 { 0x05, 0x8b70 },
2992 { 0x06, 0x0000 },
2993 { 0x1f, 0x0000 },
2994 { 0x1f, 0x0007 },
2995 { 0x1e, 0x0078 },
2996 { 0x17, 0x0000 },
2997 { 0x19, 0x00fb },
2998 { 0x1f, 0x0000 },
2999
3000 /* Modify green table for 10M */
3001 { 0x1f, 0x0005 },
3002 { 0x05, 0x8b79 },
3003 { 0x06, 0xaa00 },
3004 { 0x1f, 0x0000 },
3005
3006 /* Disable hiimpedance detection (RTCT) */
3007 { 0x1f, 0x0003 },
3008 { 0x01, 0x328a },
3009 { 0x1f, 0x0000 }
3010 };
3011
3012 rtl_apply_firmware(tp);
3013
3014 rtl_writephy_batch(tp, phy_reg_init);
3015
3016 rtl8168f_hw_phy_config(tp);
3017
3018 /* Improve 2-pair detection performance */
3019 rtl_writephy(tp, 0x1f, 0x0005);
3020 rtl_writephy(tp, 0x05, 0x8b85);
3021 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3022 rtl_writephy(tp, 0x1f, 0x0000);
3023 }
3024
3025 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3026 {
3027 rtl_apply_firmware(tp);
3028
3029 rtl8168f_hw_phy_config(tp);
3030 }
3031
3032 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3033 {
3034 static const struct phy_reg phy_reg_init[] = {
3035 /* Channel estimation fine tune */
3036 { 0x1f, 0x0003 },
3037 { 0x09, 0xa20f },
3038 { 0x1f, 0x0000 },
3039
3040 /* Modify green table for giga & fnet */
3041 { 0x1f, 0x0005 },
3042 { 0x05, 0x8b55 },
3043 { 0x06, 0x0000 },
3044 { 0x05, 0x8b5e },
3045 { 0x06, 0x0000 },
3046 { 0x05, 0x8b67 },
3047 { 0x06, 0x0000 },
3048 { 0x05, 0x8b70 },
3049 { 0x06, 0x0000 },
3050 { 0x1f, 0x0000 },
3051 { 0x1f, 0x0007 },
3052 { 0x1e, 0x0078 },
3053 { 0x17, 0x0000 },
3054 { 0x19, 0x00aa },
3055 { 0x1f, 0x0000 },
3056
3057 /* Modify green table for 10M */
3058 { 0x1f, 0x0005 },
3059 { 0x05, 0x8b79 },
3060 { 0x06, 0xaa00 },
3061 { 0x1f, 0x0000 },
3062
3063 /* Disable hiimpedance detection (RTCT) */
3064 { 0x1f, 0x0003 },
3065 { 0x01, 0x328a },
3066 { 0x1f, 0x0000 }
3067 };
3068
3069
3070 rtl_apply_firmware(tp);
3071
3072 rtl8168f_hw_phy_config(tp);
3073
3074 /* Improve 2-pair detection performance */
3075 rtl_writephy(tp, 0x1f, 0x0005);
3076 rtl_writephy(tp, 0x05, 0x8b85);
3077 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3078 rtl_writephy(tp, 0x1f, 0x0000);
3079
3080 rtl_writephy_batch(tp, phy_reg_init);
3081
3082 /* Modify green table for giga */
3083 rtl_writephy(tp, 0x1f, 0x0005);
3084 rtl_writephy(tp, 0x05, 0x8b54);
3085 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3086 rtl_writephy(tp, 0x05, 0x8b5d);
3087 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3088 rtl_writephy(tp, 0x05, 0x8a7c);
3089 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3090 rtl_writephy(tp, 0x05, 0x8a7f);
3091 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3092 rtl_writephy(tp, 0x05, 0x8a82);
3093 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3094 rtl_writephy(tp, 0x05, 0x8a85);
3095 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3096 rtl_writephy(tp, 0x05, 0x8a88);
3097 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3098 rtl_writephy(tp, 0x1f, 0x0000);
3099
3100 /* uc same-seed solution */
3101 rtl_writephy(tp, 0x1f, 0x0005);
3102 rtl_writephy(tp, 0x05, 0x8b85);
3103 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3104 rtl_writephy(tp, 0x1f, 0x0000);
3105
3106 /* Green feature */
3107 rtl_writephy(tp, 0x1f, 0x0003);
3108 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3109 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3110 rtl_writephy(tp, 0x1f, 0x0000);
3111 }
3112
3113 static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3114 {
3115 phy_modify_paged(tp->phydev, 0x0a43, 0x10, BIT(2), 0);
3116 }
3117
3118 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3119 {
3120 struct phy_device *phydev = tp->phydev;
3121
3122 phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0);
3123 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6));
3124 phy_write(phydev, 0x1f, 0x0a43);
3125 phy_write(phydev, 0x13, 0x8084);
3126 phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13));
3127 phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0));
3128
3129 phy_write(phydev, 0x1f, 0x0000);
3130 }
3131
3132 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3133 {
3134 int ret;
3135
3136 rtl_apply_firmware(tp);
3137
3138 ret = phy_read_paged(tp->phydev, 0x0a46, 0x10);
3139 if (ret & BIT(8))
3140 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, BIT(15), 0);
3141 else
3142 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, 0, BIT(15));
3143
3144 ret = phy_read_paged(tp->phydev, 0x0a46, 0x13);
3145 if (ret & BIT(8))
3146 phy_modify_paged(tp->phydev, 0x0c41, 0x15, 0, BIT(1));
3147 else
3148 phy_modify_paged(tp->phydev, 0x0c41, 0x15, BIT(1), 0);
3149
3150 /* Enable PHY auto speed down */
3151 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3152
3153 rtl8168g_phy_adjust_10m_aldps(tp);
3154
3155 /* EEE auto-fallback function */
3156 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3157
3158 /* Enable UC LPF tune function */
3159 rtl_writephy(tp, 0x1f, 0x0a43);
3160 rtl_writephy(tp, 0x13, 0x8012);
3161 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3162
3163 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3164
3165 /* Improve SWR Efficiency */
3166 rtl_writephy(tp, 0x1f, 0x0bcd);
3167 rtl_writephy(tp, 0x14, 0x5065);
3168 rtl_writephy(tp, 0x14, 0xd065);
3169 rtl_writephy(tp, 0x1f, 0x0bc8);
3170 rtl_writephy(tp, 0x11, 0x5655);
3171 rtl_writephy(tp, 0x1f, 0x0bcd);
3172 rtl_writephy(tp, 0x14, 0x1065);
3173 rtl_writephy(tp, 0x14, 0x9065);
3174 rtl_writephy(tp, 0x14, 0x1065);
3175 rtl_writephy(tp, 0x1f, 0x0000);
3176
3177 rtl8168g_disable_aldps(tp);
3178 rtl8168g_config_eee_phy(tp);
3179 rtl_enable_eee(tp);
3180 }
3181
3182 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3183 {
3184 rtl_apply_firmware(tp);
3185 rtl8168g_config_eee_phy(tp);
3186 rtl_enable_eee(tp);
3187 }
3188
3189 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3190 {
3191 u16 dout_tapbin;
3192 u32 data;
3193
3194 rtl_apply_firmware(tp);
3195
3196 /* CHN EST parameters adjust - giga master */
3197 rtl_writephy(tp, 0x1f, 0x0a43);
3198 rtl_writephy(tp, 0x13, 0x809b);
3199 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3200 rtl_writephy(tp, 0x13, 0x80a2);
3201 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3202 rtl_writephy(tp, 0x13, 0x80a4);
3203 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3204 rtl_writephy(tp, 0x13, 0x809c);
3205 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3206 rtl_writephy(tp, 0x1f, 0x0000);
3207
3208 /* CHN EST parameters adjust - giga slave */
3209 rtl_writephy(tp, 0x1f, 0x0a43);
3210 rtl_writephy(tp, 0x13, 0x80ad);
3211 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3212 rtl_writephy(tp, 0x13, 0x80b4);
3213 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3214 rtl_writephy(tp, 0x13, 0x80ac);
3215 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3216 rtl_writephy(tp, 0x1f, 0x0000);
3217
3218 /* CHN EST parameters adjust - fnet */
3219 rtl_writephy(tp, 0x1f, 0x0a43);
3220 rtl_writephy(tp, 0x13, 0x808e);
3221 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3222 rtl_writephy(tp, 0x13, 0x8090);
3223 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3224 rtl_writephy(tp, 0x13, 0x8092);
3225 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3226 rtl_writephy(tp, 0x1f, 0x0000);
3227
3228 /* enable R-tune & PGA-retune function */
3229 dout_tapbin = 0;
3230 rtl_writephy(tp, 0x1f, 0x0a46);
3231 data = rtl_readphy(tp, 0x13);
3232 data &= 3;
3233 data <<= 2;
3234 dout_tapbin |= data;
3235 data = rtl_readphy(tp, 0x12);
3236 data &= 0xc000;
3237 data >>= 14;
3238 dout_tapbin |= data;
3239 dout_tapbin = ~(dout_tapbin^0x08);
3240 dout_tapbin <<= 12;
3241 dout_tapbin &= 0xf000;
3242 rtl_writephy(tp, 0x1f, 0x0a43);
3243 rtl_writephy(tp, 0x13, 0x827a);
3244 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3245 rtl_writephy(tp, 0x13, 0x827b);
3246 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3247 rtl_writephy(tp, 0x13, 0x827c);
3248 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3249 rtl_writephy(tp, 0x13, 0x827d);
3250 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3251
3252 rtl_writephy(tp, 0x1f, 0x0a43);
3253 rtl_writephy(tp, 0x13, 0x0811);
3254 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3255 rtl_writephy(tp, 0x1f, 0x0a42);
3256 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3257 rtl_writephy(tp, 0x1f, 0x0000);
3258
3259 /* enable GPHY 10M */
3260 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3261
3262 /* SAR ADC performance */
3263 phy_modify_paged(tp->phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14));
3264
3265 rtl_writephy(tp, 0x1f, 0x0a43);
3266 rtl_writephy(tp, 0x13, 0x803f);
3267 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3268 rtl_writephy(tp, 0x13, 0x8047);
3269 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3270 rtl_writephy(tp, 0x13, 0x804f);
3271 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3272 rtl_writephy(tp, 0x13, 0x8057);
3273 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3274 rtl_writephy(tp, 0x13, 0x805f);
3275 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3276 rtl_writephy(tp, 0x13, 0x8067);
3277 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3278 rtl_writephy(tp, 0x13, 0x806f);
3279 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3280 rtl_writephy(tp, 0x1f, 0x0000);
3281
3282 /* disable phy pfm mode */
3283 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3284
3285 rtl8168g_disable_aldps(tp);
3286 rtl8168g_config_eee_phy(tp);
3287 rtl_enable_eee(tp);
3288 }
3289
3290 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3291 {
3292 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3293 u16 rlen;
3294 u32 data;
3295
3296 rtl_apply_firmware(tp);
3297
3298 /* CHIN EST parameter update */
3299 rtl_writephy(tp, 0x1f, 0x0a43);
3300 rtl_writephy(tp, 0x13, 0x808a);
3301 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3302 rtl_writephy(tp, 0x1f, 0x0000);
3303
3304 /* enable R-tune & PGA-retune function */
3305 rtl_writephy(tp, 0x1f, 0x0a43);
3306 rtl_writephy(tp, 0x13, 0x0811);
3307 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3308 rtl_writephy(tp, 0x1f, 0x0a42);
3309 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3310 rtl_writephy(tp, 0x1f, 0x0000);
3311
3312 /* enable GPHY 10M */
3313 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3314
3315 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3316 data = r8168_mac_ocp_read(tp, 0xdd02);
3317 ioffset_p3 = ((data & 0x80)>>7);
3318 ioffset_p3 <<= 3;
3319
3320 data = r8168_mac_ocp_read(tp, 0xdd00);
3321 ioffset_p3 |= ((data & (0xe000))>>13);
3322 ioffset_p2 = ((data & (0x1e00))>>9);
3323 ioffset_p1 = ((data & (0x01e0))>>5);
3324 ioffset_p0 = ((data & 0x0010)>>4);
3325 ioffset_p0 <<= 3;
3326 ioffset_p0 |= (data & (0x07));
3327 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3328
3329 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3330 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3331 rtl_writephy(tp, 0x1f, 0x0bcf);
3332 rtl_writephy(tp, 0x16, data);
3333 rtl_writephy(tp, 0x1f, 0x0000);
3334 }
3335
3336 /* Modify rlen (TX LPF corner frequency) level */
3337 rtl_writephy(tp, 0x1f, 0x0bcd);
3338 data = rtl_readphy(tp, 0x16);
3339 data &= 0x000f;
3340 rlen = 0;
3341 if (data > 3)
3342 rlen = data - 3;
3343 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3344 rtl_writephy(tp, 0x17, data);
3345 rtl_writephy(tp, 0x1f, 0x0bcd);
3346 rtl_writephy(tp, 0x1f, 0x0000);
3347
3348 /* disable phy pfm mode */
3349 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3350
3351 rtl8168g_disable_aldps(tp);
3352 rtl8168g_config_eee_phy(tp);
3353 rtl_enable_eee(tp);
3354 }
3355
3356 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3357 {
3358 /* Enable PHY auto speed down */
3359 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3360
3361 rtl8168g_phy_adjust_10m_aldps(tp);
3362
3363 /* Enable EEE auto-fallback function */
3364 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3365
3366 /* Enable UC LPF tune function */
3367 rtl_writephy(tp, 0x1f, 0x0a43);
3368 rtl_writephy(tp, 0x13, 0x8012);
3369 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3370 rtl_writephy(tp, 0x1f, 0x0000);
3371
3372 /* set rg_sel_sdm_rate */
3373 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3374
3375 rtl8168g_disable_aldps(tp);
3376 rtl8168g_config_eee_phy(tp);
3377 rtl_enable_eee(tp);
3378 }
3379
3380 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3381 {
3382 rtl8168g_phy_adjust_10m_aldps(tp);
3383
3384 /* Enable UC LPF tune function */
3385 rtl_writephy(tp, 0x1f, 0x0a43);
3386 rtl_writephy(tp, 0x13, 0x8012);
3387 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3388 rtl_writephy(tp, 0x1f, 0x0000);
3389
3390 /* Set rg_sel_sdm_rate */
3391 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3392
3393 /* Channel estimation parameters */
3394 rtl_writephy(tp, 0x1f, 0x0a43);
3395 rtl_writephy(tp, 0x13, 0x80f3);
3396 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3397 rtl_writephy(tp, 0x13, 0x80f0);
3398 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3399 rtl_writephy(tp, 0x13, 0x80ef);
3400 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3401 rtl_writephy(tp, 0x13, 0x80f6);
3402 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3403 rtl_writephy(tp, 0x13, 0x80ec);
3404 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3405 rtl_writephy(tp, 0x13, 0x80ed);
3406 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3407 rtl_writephy(tp, 0x13, 0x80f2);
3408 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3409 rtl_writephy(tp, 0x13, 0x80f4);
3410 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3411 rtl_writephy(tp, 0x1f, 0x0a43);
3412 rtl_writephy(tp, 0x13, 0x8110);
3413 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3414 rtl_writephy(tp, 0x13, 0x810f);
3415 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3416 rtl_writephy(tp, 0x13, 0x8111);
3417 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3418 rtl_writephy(tp, 0x13, 0x8113);
3419 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3420 rtl_writephy(tp, 0x13, 0x8115);
3421 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3422 rtl_writephy(tp, 0x13, 0x810e);
3423 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3424 rtl_writephy(tp, 0x13, 0x810c);
3425 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3426 rtl_writephy(tp, 0x13, 0x810b);
3427 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3428 rtl_writephy(tp, 0x1f, 0x0a43);
3429 rtl_writephy(tp, 0x13, 0x80d1);
3430 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3431 rtl_writephy(tp, 0x13, 0x80cd);
3432 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3433 rtl_writephy(tp, 0x13, 0x80d3);
3434 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3435 rtl_writephy(tp, 0x13, 0x80d5);
3436 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3437 rtl_writephy(tp, 0x13, 0x80d7);
3438 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3439
3440 /* Force PWM-mode */
3441 rtl_writephy(tp, 0x1f, 0x0bcd);
3442 rtl_writephy(tp, 0x14, 0x5065);
3443 rtl_writephy(tp, 0x14, 0xd065);
3444 rtl_writephy(tp, 0x1f, 0x0bc8);
3445 rtl_writephy(tp, 0x12, 0x00ed);
3446 rtl_writephy(tp, 0x1f, 0x0bcd);
3447 rtl_writephy(tp, 0x14, 0x1065);
3448 rtl_writephy(tp, 0x14, 0x9065);
3449 rtl_writephy(tp, 0x14, 0x1065);
3450 rtl_writephy(tp, 0x1f, 0x0000);
3451
3452 rtl8168g_disable_aldps(tp);
3453 rtl8168g_config_eee_phy(tp);
3454 rtl_enable_eee(tp);
3455 }
3456
3457 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3458 {
3459 static const struct phy_reg phy_reg_init[] = {
3460 { 0x1f, 0x0003 },
3461 { 0x08, 0x441d },
3462 { 0x01, 0x9100 },
3463 { 0x1f, 0x0000 }
3464 };
3465
3466 rtl_writephy(tp, 0x1f, 0x0000);
3467 rtl_patchphy(tp, 0x11, 1 << 12);
3468 rtl_patchphy(tp, 0x19, 1 << 13);
3469 rtl_patchphy(tp, 0x10, 1 << 15);
3470
3471 rtl_writephy_batch(tp, phy_reg_init);
3472 }
3473
3474 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3475 {
3476 static const struct phy_reg phy_reg_init[] = {
3477 { 0x1f, 0x0005 },
3478 { 0x1a, 0x0000 },
3479 { 0x1f, 0x0000 },
3480
3481 { 0x1f, 0x0004 },
3482 { 0x1c, 0x0000 },
3483 { 0x1f, 0x0000 },
3484
3485 { 0x1f, 0x0001 },
3486 { 0x15, 0x7701 },
3487 { 0x1f, 0x0000 }
3488 };
3489
3490 /* Disable ALDPS before ram code */
3491 rtl_writephy(tp, 0x1f, 0x0000);
3492 rtl_writephy(tp, 0x18, 0x0310);
3493 msleep(100);
3494
3495 rtl_apply_firmware(tp);
3496
3497 rtl_writephy_batch(tp, phy_reg_init);
3498 }
3499
3500 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3501 {
3502 /* Disable ALDPS before setting firmware */
3503 rtl_writephy(tp, 0x1f, 0x0000);
3504 rtl_writephy(tp, 0x18, 0x0310);
3505 msleep(20);
3506
3507 rtl_apply_firmware(tp);
3508
3509 /* EEE setting */
3510 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3511 rtl_writephy(tp, 0x1f, 0x0004);
3512 rtl_writephy(tp, 0x10, 0x401f);
3513 rtl_writephy(tp, 0x19, 0x7030);
3514 rtl_writephy(tp, 0x1f, 0x0000);
3515 }
3516
3517 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3518 {
3519 static const struct phy_reg phy_reg_init[] = {
3520 { 0x1f, 0x0004 },
3521 { 0x10, 0xc07f },
3522 { 0x19, 0x7030 },
3523 { 0x1f, 0x0000 }
3524 };
3525
3526 /* Disable ALDPS before ram code */
3527 rtl_writephy(tp, 0x1f, 0x0000);
3528 rtl_writephy(tp, 0x18, 0x0310);
3529 msleep(100);
3530
3531 rtl_apply_firmware(tp);
3532
3533 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3534 rtl_writephy_batch(tp, phy_reg_init);
3535
3536 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3537 }
3538
3539 static void rtl_hw_phy_config(struct net_device *dev)
3540 {
3541 static const rtl_generic_fct phy_configs[] = {
3542 /* PCI devices. */
3543 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
3544 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
3545 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
3546 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
3547 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
3548 /* PCI-E devices. */
3549 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
3550 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
3551 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
3552 [RTL_GIGA_MAC_VER_10] = NULL,
3553 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
3554 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config,
3555 [RTL_GIGA_MAC_VER_13] = NULL,
3556 [RTL_GIGA_MAC_VER_14] = NULL,
3557 [RTL_GIGA_MAC_VER_15] = NULL,
3558 [RTL_GIGA_MAC_VER_16] = NULL,
3559 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
3560 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
3561 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
3562 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
3563 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
3564 [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config,
3565 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
3566 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
3567 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
3568 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
3569 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config,
3570 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
3571 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
3572 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
3573 [RTL_GIGA_MAC_VER_31] = NULL,
3574 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
3575 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
3576 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
3577 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
3578 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
3579 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
3580 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
3581 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
3582 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
3583 [RTL_GIGA_MAC_VER_41] = NULL,
3584 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
3585 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
3586 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
3587 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config,
3588 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
3589 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config,
3590 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
3591 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config,
3592 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config,
3593 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
3594 };
3595 struct rtl8169_private *tp = netdev_priv(dev);
3596
3597 if (phy_configs[tp->mac_version])
3598 phy_configs[tp->mac_version](tp);
3599 }
3600
3601 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3602 {
3603 if (!test_and_set_bit(flag, tp->wk.flags))
3604 schedule_work(&tp->wk.work);
3605 }
3606
3607 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3608 {
3609 rtl_hw_phy_config(dev);
3610
3611 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3612 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3613 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3614 netif_dbg(tp, drv, dev,
3615 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3616 RTL_W8(tp, 0x82, 0x01);
3617 }
3618
3619 /* We may have called phy_speed_down before */
3620 phy_speed_up(tp->phydev);
3621
3622 genphy_soft_reset(tp->phydev);
3623 }
3624
3625 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3626 {
3627 rtl_lock_work(tp);
3628
3629 rtl_unlock_config_regs(tp);
3630
3631 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
3632 RTL_R32(tp, MAC4);
3633
3634 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3635 RTL_R32(tp, MAC0);
3636
3637 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3638 rtl_rar_exgmac_set(tp, addr);
3639
3640 rtl_lock_config_regs(tp);
3641
3642 rtl_unlock_work(tp);
3643 }
3644
3645 static int rtl_set_mac_address(struct net_device *dev, void *p)
3646 {
3647 struct rtl8169_private *tp = netdev_priv(dev);
3648 struct device *d = tp_to_dev(tp);
3649 int ret;
3650
3651 ret = eth_mac_addr(dev, p);
3652 if (ret)
3653 return ret;
3654
3655 pm_runtime_get_noresume(d);
3656
3657 if (pm_runtime_active(d))
3658 rtl_rar_set(tp, dev->dev_addr);
3659
3660 pm_runtime_put_noidle(d);
3661
3662 return 0;
3663 }
3664
3665 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3666 {
3667 struct rtl8169_private *tp = netdev_priv(dev);
3668
3669 if (!netif_running(dev))
3670 return -ENODEV;
3671
3672 return phy_mii_ioctl(tp->phydev, ifr, cmd);
3673 }
3674
3675 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3676 {
3677 switch (tp->mac_version) {
3678 case RTL_GIGA_MAC_VER_25:
3679 case RTL_GIGA_MAC_VER_26:
3680 case RTL_GIGA_MAC_VER_29:
3681 case RTL_GIGA_MAC_VER_30:
3682 case RTL_GIGA_MAC_VER_32:
3683 case RTL_GIGA_MAC_VER_33:
3684 case RTL_GIGA_MAC_VER_34:
3685 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
3686 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
3687 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3688 break;
3689 default:
3690 break;
3691 }
3692 }
3693
3694 static void rtl_pll_power_down(struct rtl8169_private *tp)
3695 {
3696 if (r8168_check_dash(tp))
3697 return;
3698
3699 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3700 tp->mac_version == RTL_GIGA_MAC_VER_33)
3701 rtl_ephy_write(tp, 0x19, 0xff64);
3702
3703 if (device_may_wakeup(tp_to_dev(tp))) {
3704 phy_speed_down(tp->phydev, false);
3705 rtl_wol_suspend_quirk(tp);
3706 return;
3707 }
3708
3709 switch (tp->mac_version) {
3710 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
3711 case RTL_GIGA_MAC_VER_37:
3712 case RTL_GIGA_MAC_VER_39:
3713 case RTL_GIGA_MAC_VER_43:
3714 case RTL_GIGA_MAC_VER_44:
3715 case RTL_GIGA_MAC_VER_45:
3716 case RTL_GIGA_MAC_VER_46:
3717 case RTL_GIGA_MAC_VER_47:
3718 case RTL_GIGA_MAC_VER_48:
3719 case RTL_GIGA_MAC_VER_50:
3720 case RTL_GIGA_MAC_VER_51:
3721 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
3722 break;
3723 case RTL_GIGA_MAC_VER_40:
3724 case RTL_GIGA_MAC_VER_41:
3725 case RTL_GIGA_MAC_VER_49:
3726 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
3727 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
3728 break;
3729 default:
3730 break;
3731 }
3732 }
3733
3734 static void rtl_pll_power_up(struct rtl8169_private *tp)
3735 {
3736 switch (tp->mac_version) {
3737 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
3738 case RTL_GIGA_MAC_VER_37:
3739 case RTL_GIGA_MAC_VER_39:
3740 case RTL_GIGA_MAC_VER_43:
3741 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
3742 break;
3743 case RTL_GIGA_MAC_VER_44:
3744 case RTL_GIGA_MAC_VER_45:
3745 case RTL_GIGA_MAC_VER_46:
3746 case RTL_GIGA_MAC_VER_47:
3747 case RTL_GIGA_MAC_VER_48:
3748 case RTL_GIGA_MAC_VER_50:
3749 case RTL_GIGA_MAC_VER_51:
3750 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
3751 break;
3752 case RTL_GIGA_MAC_VER_40:
3753 case RTL_GIGA_MAC_VER_41:
3754 case RTL_GIGA_MAC_VER_49:
3755 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
3756 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
3757 break;
3758 default:
3759 break;
3760 }
3761
3762 phy_resume(tp->phydev);
3763 /* give MAC/PHY some time to resume */
3764 msleep(20);
3765 }
3766
3767 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3768 {
3769 switch (tp->mac_version) {
3770 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
3771 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
3772 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3773 break;
3774 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
3775 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
3776 case RTL_GIGA_MAC_VER_38:
3777 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3778 break;
3779 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
3780 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
3781 break;
3782 default:
3783 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
3784 break;
3785 }
3786 }
3787
3788 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3789 {
3790 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
3791 }
3792
3793 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3794 {
3795 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3796 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
3797 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
3798 }
3799
3800 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3801 {
3802 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3803 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
3804 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
3805 }
3806
3807 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3808 {
3809 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3810 }
3811
3812 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3813 {
3814 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3815 }
3816
3817 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3818 {
3819 RTL_W8(tp, MaxTxPacketSize, 0x3f);
3820 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3821 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
3822 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
3823 }
3824
3825 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3826 {
3827 RTL_W8(tp, MaxTxPacketSize, 0x0c);
3828 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3829 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
3830 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
3831 }
3832
3833 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3834 {
3835 rtl_tx_performance_tweak(tp,
3836 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
3837 }
3838
3839 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3840 {
3841 rtl_tx_performance_tweak(tp,
3842 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
3843 }
3844
3845 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3846 {
3847 r8168b_0_hw_jumbo_enable(tp);
3848
3849 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
3850 }
3851
3852 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3853 {
3854 r8168b_0_hw_jumbo_disable(tp);
3855
3856 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
3857 }
3858
3859 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3860 {
3861 rtl_unlock_config_regs(tp);
3862 switch (tp->mac_version) {
3863 case RTL_GIGA_MAC_VER_11:
3864 r8168b_0_hw_jumbo_enable(tp);
3865 break;
3866 case RTL_GIGA_MAC_VER_12:
3867 case RTL_GIGA_MAC_VER_17:
3868 r8168b_1_hw_jumbo_enable(tp);
3869 break;
3870 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
3871 r8168c_hw_jumbo_enable(tp);
3872 break;
3873 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
3874 r8168dp_hw_jumbo_enable(tp);
3875 break;
3876 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
3877 r8168e_hw_jumbo_enable(tp);
3878 break;
3879 default:
3880 break;
3881 }
3882 rtl_lock_config_regs(tp);
3883 }
3884
3885 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3886 {
3887 rtl_unlock_config_regs(tp);
3888 switch (tp->mac_version) {
3889 case RTL_GIGA_MAC_VER_11:
3890 r8168b_0_hw_jumbo_disable(tp);
3891 break;
3892 case RTL_GIGA_MAC_VER_12:
3893 case RTL_GIGA_MAC_VER_17:
3894 r8168b_1_hw_jumbo_disable(tp);
3895 break;
3896 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
3897 r8168c_hw_jumbo_disable(tp);
3898 break;
3899 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
3900 r8168dp_hw_jumbo_disable(tp);
3901 break;
3902 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
3903 r8168e_hw_jumbo_disable(tp);
3904 break;
3905 default:
3906 break;
3907 }
3908 rtl_lock_config_regs(tp);
3909 }
3910
3911 DECLARE_RTL_COND(rtl_chipcmd_cond)
3912 {
3913 return RTL_R8(tp, ChipCmd) & CmdReset;
3914 }
3915
3916 static void rtl_hw_reset(struct rtl8169_private *tp)
3917 {
3918 RTL_W8(tp, ChipCmd, CmdReset);
3919
3920 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
3921 }
3922
3923 static void rtl_request_firmware(struct rtl8169_private *tp)
3924 {
3925 struct rtl_fw *rtl_fw;
3926
3927 /* firmware loaded already or no firmware available */
3928 if (tp->rtl_fw || !tp->fw_name)
3929 return;
3930
3931 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3932 if (!rtl_fw) {
3933 netif_warn(tp, ifup, tp->dev, "Unable to load firmware, out of memory\n");
3934 return;
3935 }
3936
3937 rtl_fw->phy_write = rtl_writephy;
3938 rtl_fw->phy_read = rtl_readphy;
3939 rtl_fw->mac_mcu_write = mac_mcu_write;
3940 rtl_fw->mac_mcu_read = mac_mcu_read;
3941 rtl_fw->fw_name = tp->fw_name;
3942 rtl_fw->dev = tp_to_dev(tp);
3943
3944 if (rtl_fw_request_firmware(rtl_fw))
3945 kfree(rtl_fw);
3946 else
3947 tp->rtl_fw = rtl_fw;
3948 }
3949
3950 static void rtl_rx_close(struct rtl8169_private *tp)
3951 {
3952 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
3953 }
3954
3955 DECLARE_RTL_COND(rtl_npq_cond)
3956 {
3957 return RTL_R8(tp, TxPoll) & NPQ;
3958 }
3959
3960 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
3961 {
3962 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
3963 }
3964
3965 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3966 {
3967 /* Disable interrupts */
3968 rtl8169_irq_mask_and_ack(tp);
3969
3970 rtl_rx_close(tp);
3971
3972 switch (tp->mac_version) {
3973 case RTL_GIGA_MAC_VER_27:
3974 case RTL_GIGA_MAC_VER_28:
3975 case RTL_GIGA_MAC_VER_31:
3976 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
3977 break;
3978 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
3979 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
3980 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3981 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
3982 break;
3983 default:
3984 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3985 udelay(100);
3986 break;
3987 }
3988
3989 rtl_hw_reset(tp);
3990 }
3991
3992 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
3993 {
3994 u32 val = TX_DMA_BURST << TxDMAShift |
3995 InterFrameGap << TxInterFrameGapShift;
3996
3997 if (rtl_is_8168evl_up(tp))
3998 val |= TXCFG_AUTO_FIFO;
3999
4000 RTL_W32(tp, TxConfig, val);
4001 }
4002
4003 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4004 {
4005 /* Low hurts. Let's disable the filtering. */
4006 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4007 }
4008
4009 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4010 {
4011 /*
4012 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4013 * register to be written before TxDescAddrLow to work.
4014 * Switching from MMIO to I/O access fixes the issue as well.
4015 */
4016 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4017 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4018 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4019 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4020 }
4021
4022 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4023 {
4024 u32 val;
4025
4026 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4027 val = 0x000fff00;
4028 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4029 val = 0x00ffff00;
4030 else
4031 return;
4032
4033 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4034 val |= 0xff;
4035
4036 RTL_W32(tp, 0x7c, val);
4037 }
4038
4039 static void rtl_set_rx_mode(struct net_device *dev)
4040 {
4041 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
4042 /* Multicast hash filter */
4043 u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
4044 struct rtl8169_private *tp = netdev_priv(dev);
4045 u32 tmp;
4046
4047 if (dev->flags & IFF_PROMISC) {
4048 /* Unconditionally log net taps. */
4049 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4050 rx_mode |= AcceptAllPhys;
4051 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
4052 dev->flags & IFF_ALLMULTI ||
4053 tp->mac_version == RTL_GIGA_MAC_VER_35) {
4054 /* accept all multicasts */
4055 } else if (netdev_mc_empty(dev)) {
4056 rx_mode &= ~AcceptMulticast;
4057 } else {
4058 struct netdev_hw_addr *ha;
4059
4060 mc_filter[1] = mc_filter[0] = 0;
4061 netdev_for_each_mc_addr(ha, dev) {
4062 u32 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4063 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
4064 }
4065
4066 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4067 tmp = mc_filter[0];
4068 mc_filter[0] = swab32(mc_filter[1]);
4069 mc_filter[1] = swab32(tmp);
4070 }
4071 }
4072
4073 if (dev->features & NETIF_F_RXALL)
4074 rx_mode |= (AcceptErr | AcceptRunt);
4075
4076 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4077 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4078
4079 tmp = RTL_R32(tp, RxConfig);
4080 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_MASK) | rx_mode);
4081 }
4082
4083 DECLARE_RTL_COND(rtl_csiar_cond)
4084 {
4085 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4086 }
4087
4088 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4089 {
4090 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4091
4092 RTL_W32(tp, CSIDR, value);
4093 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4094 CSIAR_BYTE_ENABLE | func << 16);
4095
4096 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4097 }
4098
4099 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4100 {
4101 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4102
4103 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4104 CSIAR_BYTE_ENABLE);
4105
4106 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4107 RTL_R32(tp, CSIDR) : ~0;
4108 }
4109
4110 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4111 {
4112 struct pci_dev *pdev = tp->pci_dev;
4113 u32 csi;
4114
4115 /* According to Realtek the value at config space address 0x070f
4116 * controls the L0s/L1 entrance latency. We try standard ECAM access
4117 * first and if it fails fall back to CSI.
4118 */
4119 if (pdev->cfg_size > 0x070f &&
4120 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4121 return;
4122
4123 netdev_notice_once(tp->dev,
4124 "No native access to PCI extended config space, falling back to CSI\n");
4125 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4126 rtl_csi_write(tp, 0x070c, csi | val << 24);
4127 }
4128
4129 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4130 {
4131 rtl_csi_access_enable(tp, 0x27);
4132 }
4133
4134 struct ephy_info {
4135 unsigned int offset;
4136 u16 mask;
4137 u16 bits;
4138 };
4139
4140 static void __rtl_ephy_init(struct rtl8169_private *tp,
4141 const struct ephy_info *e, int len)
4142 {
4143 u16 w;
4144
4145 while (len-- > 0) {
4146 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4147 rtl_ephy_write(tp, e->offset, w);
4148 e++;
4149 }
4150 }
4151
4152 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
4153
4154 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4155 {
4156 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4157 PCI_EXP_LNKCTL_CLKREQ_EN);
4158 }
4159
4160 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4161 {
4162 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4163 PCI_EXP_LNKCTL_CLKREQ_EN);
4164 }
4165
4166 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
4167 {
4168 /* work around an issue when PCI reset occurs during L2/L3 state */
4169 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
4170 }
4171
4172 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4173 {
4174 /* Don't enable ASPM in the chip if OS can't control ASPM */
4175 if (enable && tp->aspm_manageable) {
4176 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4177 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4178 } else {
4179 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4180 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4181 }
4182
4183 udelay(10);
4184 }
4185
4186 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
4187 u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
4188 {
4189 /* Usage of dynamic vs. static FIFO is controlled by bit
4190 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
4191 */
4192 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
4193 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
4194 }
4195
4196 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
4197 u8 low, u8 high)
4198 {
4199 /* FIFO thresholds for pause flow control */
4200 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
4201 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
4202 }
4203
4204 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4205 {
4206 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4207
4208 if (tp->dev->mtu <= ETH_DATA_LEN) {
4209 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4210 PCI_EXP_DEVCTL_NOSNOOP_EN);
4211 }
4212 }
4213
4214 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4215 {
4216 rtl_hw_start_8168bb(tp);
4217
4218 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4219 }
4220
4221 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4222 {
4223 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4224
4225 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4226
4227 if (tp->dev->mtu <= ETH_DATA_LEN)
4228 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4229
4230 rtl_disable_clock_request(tp);
4231 }
4232
4233 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4234 {
4235 static const struct ephy_info e_info_8168cp[] = {
4236 { 0x01, 0, 0x0001 },
4237 { 0x02, 0x0800, 0x1000 },
4238 { 0x03, 0, 0x0042 },
4239 { 0x06, 0x0080, 0x0000 },
4240 { 0x07, 0, 0x2000 }
4241 };
4242
4243 rtl_set_def_aspm_entry_latency(tp);
4244
4245 rtl_ephy_init(tp, e_info_8168cp);
4246
4247 __rtl_hw_start_8168cp(tp);
4248 }
4249
4250 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4251 {
4252 rtl_set_def_aspm_entry_latency(tp);
4253
4254 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4255
4256 if (tp->dev->mtu <= ETH_DATA_LEN)
4257 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4258 }
4259
4260 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4261 {
4262 rtl_set_def_aspm_entry_latency(tp);
4263
4264 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4265
4266 /* Magic. */
4267 RTL_W8(tp, DBG_REG, 0x20);
4268
4269 if (tp->dev->mtu <= ETH_DATA_LEN)
4270 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4271 }
4272
4273 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4274 {
4275 static const struct ephy_info e_info_8168c_1[] = {
4276 { 0x02, 0x0800, 0x1000 },
4277 { 0x03, 0, 0x0002 },
4278 { 0x06, 0x0080, 0x0000 }
4279 };
4280
4281 rtl_set_def_aspm_entry_latency(tp);
4282
4283 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4284
4285 rtl_ephy_init(tp, e_info_8168c_1);
4286
4287 __rtl_hw_start_8168cp(tp);
4288 }
4289
4290 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4291 {
4292 static const struct ephy_info e_info_8168c_2[] = {
4293 { 0x01, 0, 0x0001 },
4294 { 0x03, 0x0400, 0x0020 }
4295 };
4296
4297 rtl_set_def_aspm_entry_latency(tp);
4298
4299 rtl_ephy_init(tp, e_info_8168c_2);
4300
4301 __rtl_hw_start_8168cp(tp);
4302 }
4303
4304 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4305 {
4306 rtl_hw_start_8168c_2(tp);
4307 }
4308
4309 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4310 {
4311 rtl_set_def_aspm_entry_latency(tp);
4312
4313 __rtl_hw_start_8168cp(tp);
4314 }
4315
4316 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4317 {
4318 rtl_set_def_aspm_entry_latency(tp);
4319
4320 rtl_disable_clock_request(tp);
4321
4322 if (tp->dev->mtu <= ETH_DATA_LEN)
4323 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4324 }
4325
4326 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4327 {
4328 rtl_set_def_aspm_entry_latency(tp);
4329
4330 if (tp->dev->mtu <= ETH_DATA_LEN)
4331 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4332
4333 rtl_disable_clock_request(tp);
4334 }
4335
4336 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4337 {
4338 static const struct ephy_info e_info_8168d_4[] = {
4339 { 0x0b, 0x0000, 0x0048 },
4340 { 0x19, 0x0020, 0x0050 },
4341 { 0x0c, 0x0100, 0x0020 },
4342 { 0x10, 0x0004, 0x0000 },
4343 };
4344
4345 rtl_set_def_aspm_entry_latency(tp);
4346
4347 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4348
4349 rtl_ephy_init(tp, e_info_8168d_4);
4350
4351 rtl_enable_clock_request(tp);
4352 }
4353
4354 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4355 {
4356 static const struct ephy_info e_info_8168e_1[] = {
4357 { 0x00, 0x0200, 0x0100 },
4358 { 0x00, 0x0000, 0x0004 },
4359 { 0x06, 0x0002, 0x0001 },
4360 { 0x06, 0x0000, 0x0030 },
4361 { 0x07, 0x0000, 0x2000 },
4362 { 0x00, 0x0000, 0x0020 },
4363 { 0x03, 0x5800, 0x2000 },
4364 { 0x03, 0x0000, 0x0001 },
4365 { 0x01, 0x0800, 0x1000 },
4366 { 0x07, 0x0000, 0x4000 },
4367 { 0x1e, 0x0000, 0x2000 },
4368 { 0x19, 0xffff, 0xfe6c },
4369 { 0x0a, 0x0000, 0x0040 }
4370 };
4371
4372 rtl_set_def_aspm_entry_latency(tp);
4373
4374 rtl_ephy_init(tp, e_info_8168e_1);
4375
4376 if (tp->dev->mtu <= ETH_DATA_LEN)
4377 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4378
4379 rtl_disable_clock_request(tp);
4380
4381 /* Reset tx FIFO pointer */
4382 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4383 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4384
4385 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4386 }
4387
4388 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4389 {
4390 static const struct ephy_info e_info_8168e_2[] = {
4391 { 0x09, 0x0000, 0x0080 },
4392 { 0x19, 0x0000, 0x0224 },
4393 { 0x00, 0x0000, 0x0004 },
4394 { 0x0c, 0x3df0, 0x0200 },
4395 };
4396
4397 rtl_set_def_aspm_entry_latency(tp);
4398
4399 rtl_ephy_init(tp, e_info_8168e_2);
4400
4401 if (tp->dev->mtu <= ETH_DATA_LEN)
4402 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4403
4404 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4405 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4406 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4407 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4408 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
4409 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4410 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4411
4412 rtl_disable_clock_request(tp);
4413
4414 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4415
4416 rtl8168_config_eee_mac(tp);
4417
4418 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4419 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4420 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4421
4422 rtl_hw_aspm_clkreq_enable(tp, true);
4423 }
4424
4425 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
4426 {
4427 rtl_set_def_aspm_entry_latency(tp);
4428
4429 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4430
4431 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4432 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4433 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4434 rtl_reset_packet_filter(tp);
4435 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4436 rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));
4437 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4438 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
4439
4440 rtl_disable_clock_request(tp);
4441
4442 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4443 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4444 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4445 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4446
4447 rtl8168_config_eee_mac(tp);
4448 }
4449
4450 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
4451 {
4452 static const struct ephy_info e_info_8168f_1[] = {
4453 { 0x06, 0x00c0, 0x0020 },
4454 { 0x08, 0x0001, 0x0002 },
4455 { 0x09, 0x0000, 0x0080 },
4456 { 0x19, 0x0000, 0x0224 },
4457 { 0x00, 0x0000, 0x0004 },
4458 { 0x0c, 0x3df0, 0x0200 },
4459 };
4460
4461 rtl_hw_start_8168f(tp);
4462
4463 rtl_ephy_init(tp, e_info_8168f_1);
4464
4465 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4466 }
4467
4468 static void rtl_hw_start_8411(struct rtl8169_private *tp)
4469 {
4470 static const struct ephy_info e_info_8168f_1[] = {
4471 { 0x06, 0x00c0, 0x0020 },
4472 { 0x0f, 0xffff, 0x5200 },
4473 { 0x19, 0x0000, 0x0224 },
4474 { 0x00, 0x0000, 0x0004 },
4475 { 0x0c, 0x3df0, 0x0200 },
4476 };
4477
4478 rtl_hw_start_8168f(tp);
4479 rtl_pcie_state_l2l3_disable(tp);
4480
4481 rtl_ephy_init(tp, e_info_8168f_1);
4482
4483 rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);
4484 }
4485
4486 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
4487 {
4488 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4489 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4490
4491 rtl_set_def_aspm_entry_latency(tp);
4492
4493 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4494
4495 rtl_reset_packet_filter(tp);
4496 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
4497
4498 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4499
4500 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4501 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4502
4503 rtl8168_config_eee_mac(tp);
4504
4505 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
4506 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4507
4508 rtl_pcie_state_l2l3_disable(tp);
4509 }
4510
4511 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
4512 {
4513 static const struct ephy_info e_info_8168g_1[] = {
4514 { 0x00, 0x0008, 0x0000 },
4515 { 0x0c, 0x3ff0, 0x0820 },
4516 { 0x1e, 0x0000, 0x0001 },
4517 { 0x19, 0x8000, 0x0000 }
4518 };
4519
4520 rtl_hw_start_8168g(tp);
4521
4522 /* disable aspm and clock request before access ephy */
4523 rtl_hw_aspm_clkreq_enable(tp, false);
4524 rtl_ephy_init(tp, e_info_8168g_1);
4525 rtl_hw_aspm_clkreq_enable(tp, true);
4526 }
4527
4528 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
4529 {
4530 static const struct ephy_info e_info_8168g_2[] = {
4531 { 0x00, 0x0008, 0x0000 },
4532 { 0x0c, 0x3ff0, 0x0820 },
4533 { 0x19, 0xffff, 0x7c00 },
4534 { 0x1e, 0xffff, 0x20eb },
4535 { 0x0d, 0xffff, 0x1666 },
4536 { 0x00, 0xffff, 0x10a3 },
4537 { 0x06, 0xffff, 0xf050 },
4538 { 0x04, 0x0000, 0x0010 },
4539 { 0x1d, 0x4000, 0x0000 },
4540 };
4541
4542 rtl_hw_start_8168g(tp);
4543
4544 /* disable aspm and clock request before access ephy */
4545 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4546 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4547 rtl_ephy_init(tp, e_info_8168g_2);
4548 }
4549
4550 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
4551 {
4552 static const struct ephy_info e_info_8411_2[] = {
4553 { 0x00, 0x0008, 0x0000 },
4554 { 0x0c, 0x37d0, 0x0820 },
4555 { 0x1e, 0x0000, 0x0001 },
4556 { 0x19, 0x8021, 0x0000 },
4557 { 0x1e, 0x0000, 0x2000 },
4558 { 0x0d, 0x0100, 0x0200 },
4559 { 0x00, 0x0000, 0x0080 },
4560 { 0x06, 0x0000, 0x0010 },
4561 { 0x04, 0x0000, 0x0010 },
4562 { 0x1d, 0x0000, 0x4000 },
4563 };
4564
4565 rtl_hw_start_8168g(tp);
4566
4567 /* disable aspm and clock request before access ephy */
4568 rtl_hw_aspm_clkreq_enable(tp, false);
4569 rtl_ephy_init(tp, e_info_8411_2);
4570
4571 /* The following Realtek-provided magic fixes an issue with the RX unit
4572 * getting confused after the PHY having been powered-down.
4573 */
4574 r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
4575 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
4576 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
4577 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
4578 r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
4579 r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
4580 r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
4581 r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
4582 mdelay(3);
4583 r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
4584
4585 r8168_mac_ocp_write(tp, 0xF800, 0xE008);
4586 r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
4587 r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
4588 r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
4589 r8168_mac_ocp_write(tp, 0xF808, 0xE027);
4590 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
4591 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
4592 r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
4593 r8168_mac_ocp_write(tp, 0xF810, 0xC602);
4594 r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
4595 r8168_mac_ocp_write(tp, 0xF814, 0x0000);
4596 r8168_mac_ocp_write(tp, 0xF816, 0xC502);
4597 r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
4598 r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
4599 r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
4600 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
4601 r8168_mac_ocp_write(tp, 0xF820, 0x080A);
4602 r8168_mac_ocp_write(tp, 0xF822, 0x6420);
4603 r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
4604 r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
4605 r8168_mac_ocp_write(tp, 0xF828, 0xC516);
4606 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
4607 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
4608 r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
4609 r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
4610 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
4611 r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
4612 r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
4613 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
4614 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
4615 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
4616 r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
4617 r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
4618 r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
4619 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
4620 r8168_mac_ocp_write(tp, 0xF846, 0xC404);
4621 r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
4622 r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
4623 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
4624 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
4625 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
4626 r8168_mac_ocp_write(tp, 0xF852, 0xE434);
4627 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
4628 r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
4629 r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
4630 r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
4631 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
4632 r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
4633 r8168_mac_ocp_write(tp, 0xF860, 0xF007);
4634 r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
4635 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
4636 r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
4637 r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
4638 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
4639 r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
4640 r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
4641 r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
4642 r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
4643 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
4644 r8168_mac_ocp_write(tp, 0xF876, 0xC516);
4645 r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
4646 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
4647 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
4648 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
4649 r8168_mac_ocp_write(tp, 0xF880, 0xC512);
4650 r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
4651 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
4652 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
4653 r8168_mac_ocp_write(tp, 0xF888, 0x483F);
4654 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
4655 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
4656 r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
4657 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
4658 r8168_mac_ocp_write(tp, 0xF892, 0xC505);
4659 r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
4660 r8168_mac_ocp_write(tp, 0xF896, 0xC502);
4661 r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
4662 r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
4663 r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
4664 r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
4665 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
4666 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
4667 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
4668 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
4669 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
4670 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
4671 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
4672 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
4673 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
4674 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
4675 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
4676 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
4677 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
4678 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
4679 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
4680 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
4681 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
4682 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
4683 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
4684 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
4685 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
4686 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
4687 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
4688 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
4689 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
4690 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
4691 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
4692 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
4693 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
4694 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
4695 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
4696
4697 r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
4698
4699 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
4700 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
4701 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
4702 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
4703 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
4704 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
4705 r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
4706
4707 rtl_hw_aspm_clkreq_enable(tp, true);
4708 }
4709
4710 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
4711 {
4712 static const struct ephy_info e_info_8168h_1[] = {
4713 { 0x1e, 0x0800, 0x0001 },
4714 { 0x1d, 0x0000, 0x0800 },
4715 { 0x05, 0xffff, 0x2089 },
4716 { 0x06, 0xffff, 0x5881 },
4717 { 0x04, 0xffff, 0x854a },
4718 { 0x01, 0xffff, 0x068b }
4719 };
4720 int rg_saw_cnt;
4721
4722 /* disable aspm and clock request before access ephy */
4723 rtl_hw_aspm_clkreq_enable(tp, false);
4724 rtl_ephy_init(tp, e_info_8168h_1);
4725
4726 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4727 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4728
4729 rtl_set_def_aspm_entry_latency(tp);
4730
4731 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4732
4733 rtl_reset_packet_filter(tp);
4734
4735 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
4736
4737 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);
4738
4739 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
4740
4741 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4742
4743 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4744 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4745
4746 rtl8168_config_eee_mac(tp);
4747
4748 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4749 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4750
4751 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
4752
4753 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4754
4755 rtl_pcie_state_l2l3_disable(tp);
4756
4757 rtl_writephy(tp, 0x1f, 0x0c42);
4758 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
4759 rtl_writephy(tp, 0x1f, 0x0000);
4760 if (rg_saw_cnt > 0) {
4761 u16 sw_cnt_1ms_ini;
4762
4763 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
4764 sw_cnt_1ms_ini &= 0x0fff;
4765 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
4766 }
4767
4768 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
4769 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
4770 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
4771 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
4772
4773 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
4774 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
4775 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
4776 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
4777
4778 rtl_hw_aspm_clkreq_enable(tp, true);
4779 }
4780
4781 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
4782 {
4783 rtl8168ep_stop_cmac(tp);
4784
4785 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4786 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
4787
4788 rtl_set_def_aspm_entry_latency(tp);
4789
4790 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4791
4792 rtl_reset_packet_filter(tp);
4793
4794 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
4795
4796 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
4797
4798 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4799
4800 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4801 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4802
4803 rtl8168_config_eee_mac(tp);
4804
4805 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
4806
4807 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
4808
4809 rtl_pcie_state_l2l3_disable(tp);
4810 }
4811
4812 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
4813 {
4814 static const struct ephy_info e_info_8168ep_1[] = {
4815 { 0x00, 0xffff, 0x10ab },
4816 { 0x06, 0xffff, 0xf030 },
4817 { 0x08, 0xffff, 0x2006 },
4818 { 0x0d, 0xffff, 0x1666 },
4819 { 0x0c, 0x3ff0, 0x0000 }
4820 };
4821
4822 /* disable aspm and clock request before access ephy */
4823 rtl_hw_aspm_clkreq_enable(tp, false);
4824 rtl_ephy_init(tp, e_info_8168ep_1);
4825
4826 rtl_hw_start_8168ep(tp);
4827
4828 rtl_hw_aspm_clkreq_enable(tp, true);
4829 }
4830
4831 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
4832 {
4833 static const struct ephy_info e_info_8168ep_2[] = {
4834 { 0x00, 0xffff, 0x10a3 },
4835 { 0x19, 0xffff, 0xfc00 },
4836 { 0x1e, 0xffff, 0x20ea }
4837 };
4838
4839 /* disable aspm and clock request before access ephy */
4840 rtl_hw_aspm_clkreq_enable(tp, false);
4841 rtl_ephy_init(tp, e_info_8168ep_2);
4842
4843 rtl_hw_start_8168ep(tp);
4844
4845 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4846 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4847
4848 rtl_hw_aspm_clkreq_enable(tp, true);
4849 }
4850
4851 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
4852 {
4853 static const struct ephy_info e_info_8168ep_3[] = {
4854 { 0x00, 0x0000, 0x0080 },
4855 { 0x0d, 0x0100, 0x0200 },
4856 { 0x19, 0x8021, 0x0000 },
4857 { 0x1e, 0x0000, 0x2000 },
4858 };
4859
4860 /* disable aspm and clock request before access ephy */
4861 rtl_hw_aspm_clkreq_enable(tp, false);
4862 rtl_ephy_init(tp, e_info_8168ep_3);
4863
4864 rtl_hw_start_8168ep(tp);
4865
4866 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4867 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4868
4869 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
4870 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
4871 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
4872
4873 rtl_hw_aspm_clkreq_enable(tp, true);
4874 }
4875
4876 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
4877 {
4878 static const struct ephy_info e_info_8102e_1[] = {
4879 { 0x01, 0, 0x6e65 },
4880 { 0x02, 0, 0x091f },
4881 { 0x03, 0, 0xc2f9 },
4882 { 0x06, 0, 0xafb5 },
4883 { 0x07, 0, 0x0e00 },
4884 { 0x19, 0, 0xec80 },
4885 { 0x01, 0, 0x2e65 },
4886 { 0x01, 0, 0x6e65 }
4887 };
4888 u8 cfg1;
4889
4890 rtl_set_def_aspm_entry_latency(tp);
4891
4892 RTL_W8(tp, DBG_REG, FIX_NAK_1);
4893
4894 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4895
4896 RTL_W8(tp, Config1,
4897 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4898 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4899
4900 cfg1 = RTL_R8(tp, Config1);
4901 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4902 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
4903
4904 rtl_ephy_init(tp, e_info_8102e_1);
4905 }
4906
4907 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
4908 {
4909 rtl_set_def_aspm_entry_latency(tp);
4910
4911 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4912
4913 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
4914 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4915 }
4916
4917 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
4918 {
4919 rtl_hw_start_8102e_2(tp);
4920
4921 rtl_ephy_write(tp, 0x03, 0xc2f9);
4922 }
4923
4924 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
4925 {
4926 static const struct ephy_info e_info_8105e_1[] = {
4927 { 0x07, 0, 0x4000 },
4928 { 0x19, 0, 0x0200 },
4929 { 0x19, 0, 0x0020 },
4930 { 0x1e, 0, 0x2000 },
4931 { 0x03, 0, 0x0001 },
4932 { 0x19, 0, 0x0100 },
4933 { 0x19, 0, 0x0004 },
4934 { 0x0a, 0, 0x0020 }
4935 };
4936
4937 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4938 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
4939
4940 /* Disable Early Tally Counter */
4941 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
4942
4943 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
4944 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4945
4946 rtl_ephy_init(tp, e_info_8105e_1);
4947
4948 rtl_pcie_state_l2l3_disable(tp);
4949 }
4950
4951 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
4952 {
4953 rtl_hw_start_8105e_1(tp);
4954 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
4955 }
4956
4957 static void rtl_hw_start_8402(struct rtl8169_private *tp)
4958 {
4959 static const struct ephy_info e_info_8402[] = {
4960 { 0x19, 0xffff, 0xff64 },
4961 { 0x1e, 0, 0x4000 }
4962 };
4963
4964 rtl_set_def_aspm_entry_latency(tp);
4965
4966 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4967 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
4968
4969 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4970
4971 rtl_ephy_init(tp, e_info_8402);
4972
4973 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4974
4975 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
4976 rtl_reset_packet_filter(tp);
4977 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4978 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4979 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
4980
4981 rtl_pcie_state_l2l3_disable(tp);
4982 }
4983
4984 static void rtl_hw_start_8106(struct rtl8169_private *tp)
4985 {
4986 rtl_hw_aspm_clkreq_enable(tp, false);
4987
4988 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4989 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
4990
4991 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
4992 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
4993 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4994
4995 rtl_pcie_state_l2l3_disable(tp);
4996 rtl_hw_aspm_clkreq_enable(tp, true);
4997 }
4998
4999 static void rtl_hw_config(struct rtl8169_private *tp)
5000 {
5001 static const rtl_generic_fct hw_configs[] = {
5002 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
5003 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
5004 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
5005 [RTL_GIGA_MAC_VER_10] = NULL,
5006 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168bb,
5007 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168bef,
5008 [RTL_GIGA_MAC_VER_13] = NULL,
5009 [RTL_GIGA_MAC_VER_14] = NULL,
5010 [RTL_GIGA_MAC_VER_15] = NULL,
5011 [RTL_GIGA_MAC_VER_16] = NULL,
5012 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168bef,
5013 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
5014 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
5015 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
5016 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
5017 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
5018 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
5019 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
5020 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
5021 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
5022 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
5023 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
5024 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
5025 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
5026 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168dp,
5027 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
5028 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
5029 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
5030 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
5031 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
5032 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
5033 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
5034 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
5035 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
5036 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
5037 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
5038 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
5039 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
5040 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
5041 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
5042 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
5043 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
5044 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
5045 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
5046 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
5047 };
5048
5049 if (hw_configs[tp->mac_version])
5050 hw_configs[tp->mac_version](tp);
5051 }
5052
5053 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5054 {
5055 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5056 tp->mac_version == RTL_GIGA_MAC_VER_16)
5057 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5058 PCI_EXP_DEVCTL_NOSNOOP_EN);
5059
5060 if (rtl_is_8168evl_up(tp))
5061 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5062 else
5063 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5064
5065 rtl_hw_config(tp);
5066 }
5067
5068 static void rtl_hw_start_8169(struct rtl8169_private *tp)
5069 {
5070 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5071 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
5072
5073 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
5074
5075 tp->cp_cmd |= PCIMulRW;
5076
5077 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5078 tp->mac_version == RTL_GIGA_MAC_VER_03) {
5079 netif_dbg(tp, drv, tp->dev,
5080 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
5081 tp->cp_cmd |= (1 << 14);
5082 }
5083
5084 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5085
5086 rtl8169_set_magic_reg(tp, tp->mac_version);
5087
5088 RTL_W32(tp, RxMissed, 0);
5089 }
5090
5091 static void rtl_hw_start(struct rtl8169_private *tp)
5092 {
5093 rtl_unlock_config_regs(tp);
5094
5095 tp->cp_cmd &= CPCMD_MASK;
5096 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5097
5098 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5099 rtl_hw_start_8169(tp);
5100 else
5101 rtl_hw_start_8168(tp);
5102
5103 rtl_set_rx_max_size(tp);
5104 rtl_set_rx_tx_desc_registers(tp);
5105 rtl_lock_config_regs(tp);
5106
5107 /* disable interrupt coalescing */
5108 RTL_W16(tp, IntrMitigate, 0x0000);
5109 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5110 RTL_R8(tp, IntrMask);
5111 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
5112 rtl_init_rxcfg(tp);
5113 rtl_set_tx_config_registers(tp);
5114 rtl_set_rx_mode(tp->dev);
5115 rtl_irq_enable(tp);
5116 }
5117
5118 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5119 {
5120 struct rtl8169_private *tp = netdev_priv(dev);
5121
5122 if (new_mtu > ETH_DATA_LEN)
5123 rtl_hw_jumbo_enable(tp);
5124 else
5125 rtl_hw_jumbo_disable(tp);
5126
5127 dev->mtu = new_mtu;
5128 netdev_update_features(dev);
5129
5130 return 0;
5131 }
5132
5133 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5134 {
5135 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5136 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5137 }
5138
5139 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5140 {
5141 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5142
5143 /* Force memory writes to complete before releasing descriptor */
5144 dma_wmb();
5145
5146 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5147 }
5148
5149 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5150 struct RxDesc *desc)
5151 {
5152 struct device *d = tp_to_dev(tp);
5153 int node = dev_to_node(d);
5154 dma_addr_t mapping;
5155 struct page *data;
5156
5157 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
5158 if (!data)
5159 return NULL;
5160
5161 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5162 if (unlikely(dma_mapping_error(d, mapping))) {
5163 if (net_ratelimit())
5164 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5165 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
5166 return NULL;
5167 }
5168
5169 desc->addr = cpu_to_le64(mapping);
5170 rtl8169_mark_to_asic(desc);
5171
5172 return data;
5173 }
5174
5175 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5176 {
5177 unsigned int i;
5178
5179 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
5180 dma_unmap_page(tp_to_dev(tp),
5181 le64_to_cpu(tp->RxDescArray[i].addr),
5182 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5183 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
5184 tp->Rx_databuff[i] = NULL;
5185 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5186 }
5187 }
5188
5189 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5190 {
5191 desc->opts1 |= cpu_to_le32(RingEnd);
5192 }
5193
5194 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5195 {
5196 unsigned int i;
5197
5198 for (i = 0; i < NUM_RX_DESC; i++) {
5199 struct page *data;
5200
5201 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5202 if (!data) {
5203 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5204 goto err_out;
5205 }
5206 tp->Rx_databuff[i] = data;
5207 }
5208
5209 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5210 return 0;
5211
5212 err_out:
5213 rtl8169_rx_clear(tp);
5214 return -ENOMEM;
5215 }
5216
5217 static int rtl8169_init_ring(struct rtl8169_private *tp)
5218 {
5219 rtl8169_init_ring_indexes(tp);
5220
5221 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5222 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5223
5224 return rtl8169_rx_fill(tp);
5225 }
5226
5227 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5228 struct TxDesc *desc)
5229 {
5230 unsigned int len = tx_skb->len;
5231
5232 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5233
5234 desc->opts1 = 0x00;
5235 desc->opts2 = 0x00;
5236 desc->addr = 0x00;
5237 tx_skb->len = 0;
5238 }
5239
5240 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5241 unsigned int n)
5242 {
5243 unsigned int i;
5244
5245 for (i = 0; i < n; i++) {
5246 unsigned int entry = (start + i) % NUM_TX_DESC;
5247 struct ring_info *tx_skb = tp->tx_skb + entry;
5248 unsigned int len = tx_skb->len;
5249
5250 if (len) {
5251 struct sk_buff *skb = tx_skb->skb;
5252
5253 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5254 tp->TxDescArray + entry);
5255 if (skb) {
5256 dev_consume_skb_any(skb);
5257 tx_skb->skb = NULL;
5258 }
5259 }
5260 }
5261 }
5262
5263 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5264 {
5265 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5266 tp->cur_tx = tp->dirty_tx = 0;
5267 netdev_reset_queue(tp->dev);
5268 }
5269
5270 static void rtl_reset_work(struct rtl8169_private *tp)
5271 {
5272 struct net_device *dev = tp->dev;
5273 int i;
5274
5275 napi_disable(&tp->napi);
5276 netif_stop_queue(dev);
5277 synchronize_rcu();
5278
5279 rtl8169_hw_reset(tp);
5280
5281 for (i = 0; i < NUM_RX_DESC; i++)
5282 rtl8169_mark_to_asic(tp->RxDescArray + i);
5283
5284 rtl8169_tx_clear(tp);
5285 rtl8169_init_ring_indexes(tp);
5286
5287 napi_enable(&tp->napi);
5288 rtl_hw_start(tp);
5289 netif_wake_queue(dev);
5290 }
5291
5292 static void rtl8169_tx_timeout(struct net_device *dev)
5293 {
5294 struct rtl8169_private *tp = netdev_priv(dev);
5295
5296 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5297 }
5298
5299 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5300 {
5301 u32 status = opts0 | len;
5302
5303 if (entry == NUM_TX_DESC - 1)
5304 status |= RingEnd;
5305
5306 return cpu_to_le32(status);
5307 }
5308
5309 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5310 u32 *opts)
5311 {
5312 struct skb_shared_info *info = skb_shinfo(skb);
5313 unsigned int cur_frag, entry;
5314 struct TxDesc *uninitialized_var(txd);
5315 struct device *d = tp_to_dev(tp);
5316
5317 entry = tp->cur_tx;
5318 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5319 const skb_frag_t *frag = info->frags + cur_frag;
5320 dma_addr_t mapping;
5321 u32 len;
5322 void *addr;
5323
5324 entry = (entry + 1) % NUM_TX_DESC;
5325
5326 txd = tp->TxDescArray + entry;
5327 len = skb_frag_size(frag);
5328 addr = skb_frag_address(frag);
5329 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5330 if (unlikely(dma_mapping_error(d, mapping))) {
5331 if (net_ratelimit())
5332 netif_err(tp, drv, tp->dev,
5333 "Failed to map TX fragments DMA!\n");
5334 goto err_out;
5335 }
5336
5337 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5338 txd->opts2 = cpu_to_le32(opts[1]);
5339 txd->addr = cpu_to_le64(mapping);
5340
5341 tp->tx_skb[entry].len = len;
5342 }
5343
5344 if (cur_frag) {
5345 tp->tx_skb[entry].skb = skb;
5346 txd->opts1 |= cpu_to_le32(LastFrag);
5347 }
5348
5349 return cur_frag;
5350
5351 err_out:
5352 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5353 return -EIO;
5354 }
5355
5356 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5357 {
5358 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5359 }
5360
5361 /* msdn_giant_send_check()
5362 * According to the document of microsoft, the TCP Pseudo Header excludes the
5363 * packet length for IPv6 TCP large packets.
5364 */
5365 static int msdn_giant_send_check(struct sk_buff *skb)
5366 {
5367 const struct ipv6hdr *ipv6h;
5368 struct tcphdr *th;
5369 int ret;
5370
5371 ret = skb_cow_head(skb, 0);
5372 if (ret)
5373 return ret;
5374
5375 ipv6h = ipv6_hdr(skb);
5376 th = tcp_hdr(skb);
5377
5378 th->check = 0;
5379 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5380
5381 return ret;
5382 }
5383
5384 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
5385 {
5386 u32 mss = skb_shinfo(skb)->gso_size;
5387
5388 if (mss) {
5389 opts[0] |= TD_LSO;
5390 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5391 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5392 const struct iphdr *ip = ip_hdr(skb);
5393
5394 if (ip->protocol == IPPROTO_TCP)
5395 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5396 else if (ip->protocol == IPPROTO_UDP)
5397 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5398 else
5399 WARN_ON_ONCE(1);
5400 }
5401 }
5402
5403 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5404 struct sk_buff *skb, u32 *opts)
5405 {
5406 u32 transport_offset = (u32)skb_transport_offset(skb);
5407 u32 mss = skb_shinfo(skb)->gso_size;
5408
5409 if (mss) {
5410 switch (vlan_get_protocol(skb)) {
5411 case htons(ETH_P_IP):
5412 opts[0] |= TD1_GTSENV4;
5413 break;
5414
5415 case htons(ETH_P_IPV6):
5416 if (msdn_giant_send_check(skb))
5417 return false;
5418
5419 opts[0] |= TD1_GTSENV6;
5420 break;
5421
5422 default:
5423 WARN_ON_ONCE(1);
5424 break;
5425 }
5426
5427 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5428 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
5429 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5430 u8 ip_protocol;
5431
5432 switch (vlan_get_protocol(skb)) {
5433 case htons(ETH_P_IP):
5434 opts[1] |= TD1_IPv4_CS;
5435 ip_protocol = ip_hdr(skb)->protocol;
5436 break;
5437
5438 case htons(ETH_P_IPV6):
5439 opts[1] |= TD1_IPv6_CS;
5440 ip_protocol = ipv6_hdr(skb)->nexthdr;
5441 break;
5442
5443 default:
5444 ip_protocol = IPPROTO_RAW;
5445 break;
5446 }
5447
5448 if (ip_protocol == IPPROTO_TCP)
5449 opts[1] |= TD1_TCP_CS;
5450 else if (ip_protocol == IPPROTO_UDP)
5451 opts[1] |= TD1_UDP_CS;
5452 else
5453 WARN_ON_ONCE(1);
5454
5455 opts[1] |= transport_offset << TCPHO_SHIFT;
5456 } else {
5457 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5458 return !eth_skb_pad(skb);
5459 }
5460
5461 return true;
5462 }
5463
5464 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
5465 unsigned int nr_frags)
5466 {
5467 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
5468
5469 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
5470 return slots_avail > nr_frags;
5471 }
5472
5473 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
5474 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
5475 {
5476 switch (tp->mac_version) {
5477 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5478 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
5479 return false;
5480 default:
5481 return true;
5482 }
5483 }
5484
5485 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5486 struct net_device *dev)
5487 {
5488 struct rtl8169_private *tp = netdev_priv(dev);
5489 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5490 struct TxDesc *txd = tp->TxDescArray + entry;
5491 struct device *d = tp_to_dev(tp);
5492 dma_addr_t mapping;
5493 u32 opts[2], len;
5494 bool stop_queue;
5495 bool door_bell;
5496 int frags;
5497
5498 if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
5499 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5500 goto err_stop_0;
5501 }
5502
5503 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5504 goto err_stop_0;
5505
5506 opts[1] = rtl8169_tx_vlan_tag(skb);
5507 opts[0] = DescOwn;
5508
5509 if (rtl_chip_supports_csum_v2(tp)) {
5510 if (!rtl8169_tso_csum_v2(tp, skb, opts))
5511 goto err_dma_0;
5512 } else {
5513 rtl8169_tso_csum_v1(skb, opts);
5514 }
5515
5516 len = skb_headlen(skb);
5517 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5518 if (unlikely(dma_mapping_error(d, mapping))) {
5519 if (net_ratelimit())
5520 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5521 goto err_dma_0;
5522 }
5523
5524 tp->tx_skb[entry].len = len;
5525 txd->addr = cpu_to_le64(mapping);
5526
5527 frags = rtl8169_xmit_frags(tp, skb, opts);
5528 if (frags < 0)
5529 goto err_dma_1;
5530 else if (frags)
5531 opts[0] |= FirstFrag;
5532 else {
5533 opts[0] |= FirstFrag | LastFrag;
5534 tp->tx_skb[entry].skb = skb;
5535 }
5536
5537 txd->opts2 = cpu_to_le32(opts[1]);
5538
5539 skb_tx_timestamp(skb);
5540
5541 /* Force memory writes to complete before releasing descriptor */
5542 dma_wmb();
5543
5544 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
5545
5546 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5547
5548 /* Force all memory writes to complete before notifying device */
5549 wmb();
5550
5551 tp->cur_tx += frags + 1;
5552
5553 stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS);
5554 if (unlikely(stop_queue)) {
5555 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5556 * not miss a ring update when it notices a stopped queue.
5557 */
5558 smp_wmb();
5559 netif_stop_queue(dev);
5560 door_bell = true;
5561 }
5562
5563 if (door_bell)
5564 RTL_W8(tp, TxPoll, NPQ);
5565
5566 if (unlikely(stop_queue)) {
5567 /* Sync with rtl_tx:
5568 * - publish queue status and cur_tx ring index (write barrier)
5569 * - refresh dirty_tx ring index (read barrier).
5570 * May the current thread have a pessimistic view of the ring
5571 * status and forget to wake up queue, a racing rtl_tx thread
5572 * can't.
5573 */
5574 smp_mb();
5575 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
5576 netif_start_queue(dev);
5577 }
5578
5579 return NETDEV_TX_OK;
5580
5581 err_dma_1:
5582 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5583 err_dma_0:
5584 dev_kfree_skb_any(skb);
5585 dev->stats.tx_dropped++;
5586 return NETDEV_TX_OK;
5587
5588 err_stop_0:
5589 netif_stop_queue(dev);
5590 dev->stats.tx_dropped++;
5591 return NETDEV_TX_BUSY;
5592 }
5593
5594 static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
5595 struct net_device *dev,
5596 netdev_features_t features)
5597 {
5598 int transport_offset = skb_transport_offset(skb);
5599 struct rtl8169_private *tp = netdev_priv(dev);
5600
5601 if (skb_is_gso(skb)) {
5602 if (transport_offset > GTTCPHO_MAX &&
5603 rtl_chip_supports_csum_v2(tp))
5604 features &= ~NETIF_F_ALL_TSO;
5605 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5606 if (skb->len < ETH_ZLEN) {
5607 switch (tp->mac_version) {
5608 case RTL_GIGA_MAC_VER_11:
5609 case RTL_GIGA_MAC_VER_12:
5610 case RTL_GIGA_MAC_VER_17:
5611 case RTL_GIGA_MAC_VER_34:
5612 features &= ~NETIF_F_CSUM_MASK;
5613 break;
5614 default:
5615 break;
5616 }
5617 }
5618
5619 if (transport_offset > TCPHO_MAX &&
5620 rtl_chip_supports_csum_v2(tp))
5621 features &= ~NETIF_F_CSUM_MASK;
5622 }
5623
5624 return vlan_features_check(skb, features);
5625 }
5626
5627 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5628 {
5629 struct rtl8169_private *tp = netdev_priv(dev);
5630 struct pci_dev *pdev = tp->pci_dev;
5631 u16 pci_status, pci_cmd;
5632
5633 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5634 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5635
5636 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5637 pci_cmd, pci_status);
5638
5639 /*
5640 * The recovery sequence below admits a very elaborated explanation:
5641 * - it seems to work;
5642 * - I did not see what else could be done;
5643 * - it makes iop3xx happy.
5644 *
5645 * Feel free to adjust to your needs.
5646 */
5647 if (pdev->broken_parity_status)
5648 pci_cmd &= ~PCI_COMMAND_PARITY;
5649 else
5650 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5651
5652 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5653
5654 pci_write_config_word(pdev, PCI_STATUS,
5655 pci_status & (PCI_STATUS_DETECTED_PARITY |
5656 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5657 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5658
5659 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5660 }
5661
5662 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
5663 int budget)
5664 {
5665 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
5666
5667 dirty_tx = tp->dirty_tx;
5668 smp_rmb();
5669 tx_left = tp->cur_tx - dirty_tx;
5670
5671 while (tx_left > 0) {
5672 unsigned int entry = dirty_tx % NUM_TX_DESC;
5673 struct ring_info *tx_skb = tp->tx_skb + entry;
5674 u32 status;
5675
5676 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5677 if (status & DescOwn)
5678 break;
5679
5680 /* This barrier is needed to keep us from reading
5681 * any other fields out of the Tx descriptor until
5682 * we know the status of DescOwn
5683 */
5684 dma_rmb();
5685
5686 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5687 tp->TxDescArray + entry);
5688 if (status & LastFrag) {
5689 pkts_compl++;
5690 bytes_compl += tx_skb->skb->len;
5691 napi_consume_skb(tx_skb->skb, budget);
5692 tx_skb->skb = NULL;
5693 }
5694 dirty_tx++;
5695 tx_left--;
5696 }
5697
5698 if (tp->dirty_tx != dirty_tx) {
5699 netdev_completed_queue(dev, pkts_compl, bytes_compl);
5700
5701 u64_stats_update_begin(&tp->tx_stats.syncp);
5702 tp->tx_stats.packets += pkts_compl;
5703 tp->tx_stats.bytes += bytes_compl;
5704 u64_stats_update_end(&tp->tx_stats.syncp);
5705
5706 tp->dirty_tx = dirty_tx;
5707 /* Sync with rtl8169_start_xmit:
5708 * - publish dirty_tx ring index (write barrier)
5709 * - refresh cur_tx ring index and queue status (read barrier)
5710 * May the current thread miss the stopped queue condition,
5711 * a racing xmit thread can only have a right view of the
5712 * ring status.
5713 */
5714 smp_mb();
5715 if (netif_queue_stopped(dev) &&
5716 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
5717 netif_wake_queue(dev);
5718 }
5719 /*
5720 * 8168 hack: TxPoll requests are lost when the Tx packets are
5721 * too close. Let's kick an extra TxPoll request when a burst
5722 * of start_xmit activity is detected (if it is not detected,
5723 * it is slow enough). -- FR
5724 */
5725 if (tp->cur_tx != dirty_tx)
5726 RTL_W8(tp, TxPoll, NPQ);
5727 }
5728 }
5729
5730 static inline int rtl8169_fragmented_frame(u32 status)
5731 {
5732 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5733 }
5734
5735 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5736 {
5737 u32 status = opts1 & RxProtoMask;
5738
5739 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5740 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5741 skb->ip_summed = CHECKSUM_UNNECESSARY;
5742 else
5743 skb_checksum_none_assert(skb);
5744 }
5745
5746 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5747 {
5748 unsigned int cur_rx, rx_left;
5749 unsigned int count;
5750
5751 cur_rx = tp->cur_rx;
5752
5753 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
5754 unsigned int entry = cur_rx % NUM_RX_DESC;
5755 const void *rx_buf = page_address(tp->Rx_databuff[entry]);
5756 struct RxDesc *desc = tp->RxDescArray + entry;
5757 u32 status;
5758
5759 status = le32_to_cpu(desc->opts1);
5760 if (status & DescOwn)
5761 break;
5762
5763 /* This barrier is needed to keep us from reading
5764 * any other fields out of the Rx descriptor until
5765 * we know the status of DescOwn
5766 */
5767 dma_rmb();
5768
5769 if (unlikely(status & RxRES)) {
5770 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5771 status);
5772 dev->stats.rx_errors++;
5773 if (status & (RxRWT | RxRUNT))
5774 dev->stats.rx_length_errors++;
5775 if (status & RxCRC)
5776 dev->stats.rx_crc_errors++;
5777 if (status & (RxRUNT | RxCRC) && !(status & RxRWT) &&
5778 dev->features & NETIF_F_RXALL) {
5779 goto process_pkt;
5780 }
5781 } else {
5782 unsigned int pkt_size;
5783 struct sk_buff *skb;
5784
5785 process_pkt:
5786 pkt_size = status & GENMASK(13, 0);
5787 if (likely(!(dev->features & NETIF_F_RXFCS)))
5788 pkt_size -= ETH_FCS_LEN;
5789 /*
5790 * The driver does not support incoming fragmented
5791 * frames. They are seen as a symptom of over-mtu
5792 * sized frames.
5793 */
5794 if (unlikely(rtl8169_fragmented_frame(status))) {
5795 dev->stats.rx_dropped++;
5796 dev->stats.rx_length_errors++;
5797 goto release_descriptor;
5798 }
5799
5800 dma_sync_single_for_cpu(tp_to_dev(tp),
5801 le64_to_cpu(desc->addr),
5802 pkt_size, DMA_FROM_DEVICE);
5803
5804 skb = napi_alloc_skb(&tp->napi, pkt_size);
5805 if (unlikely(!skb)) {
5806 dev->stats.rx_dropped++;
5807 goto release_descriptor;
5808 }
5809
5810 prefetch(rx_buf);
5811 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
5812 skb->tail += pkt_size;
5813 skb->len = pkt_size;
5814
5815 rtl8169_rx_csum(skb, status);
5816 skb->protocol = eth_type_trans(skb, dev);
5817
5818 rtl8169_rx_vlan_tag(desc, skb);
5819
5820 if (skb->pkt_type == PACKET_MULTICAST)
5821 dev->stats.multicast++;
5822
5823 napi_gro_receive(&tp->napi, skb);
5824
5825 u64_stats_update_begin(&tp->rx_stats.syncp);
5826 tp->rx_stats.packets++;
5827 tp->rx_stats.bytes += pkt_size;
5828 u64_stats_update_end(&tp->rx_stats.syncp);
5829 }
5830 release_descriptor:
5831 desc->opts2 = 0;
5832 rtl8169_mark_to_asic(desc);
5833 }
5834
5835 count = cur_rx - tp->cur_rx;
5836 tp->cur_rx = cur_rx;
5837
5838 return count;
5839 }
5840
5841 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5842 {
5843 struct rtl8169_private *tp = dev_instance;
5844 u16 status = RTL_R16(tp, IntrStatus);
5845
5846 if (!tp->irq_enabled || status == 0xffff || !(status & tp->irq_mask))
5847 return IRQ_NONE;
5848
5849 if (unlikely(status & SYSErr)) {
5850 rtl8169_pcierr_interrupt(tp->dev);
5851 goto out;
5852 }
5853
5854 if (status & LinkChg)
5855 phy_mac_interrupt(tp->phydev);
5856
5857 if (unlikely(status & RxFIFOOver &&
5858 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
5859 netif_stop_queue(tp->dev);
5860 /* XXX - Hack alert. See rtl_task(). */
5861 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
5862 }
5863
5864 rtl_irq_disable(tp);
5865 napi_schedule_irqoff(&tp->napi);
5866 out:
5867 rtl_ack_events(tp, status);
5868
5869 return IRQ_HANDLED;
5870 }
5871
5872 static void rtl_task(struct work_struct *work)
5873 {
5874 static const struct {
5875 int bitnr;
5876 void (*action)(struct rtl8169_private *);
5877 } rtl_work[] = {
5878 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
5879 };
5880 struct rtl8169_private *tp =
5881 container_of(work, struct rtl8169_private, wk.work);
5882 struct net_device *dev = tp->dev;
5883 int i;
5884
5885 rtl_lock_work(tp);
5886
5887 if (!netif_running(dev) ||
5888 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
5889 goto out_unlock;
5890
5891 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
5892 bool pending;
5893
5894 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
5895 if (pending)
5896 rtl_work[i].action(tp);
5897 }
5898
5899 out_unlock:
5900 rtl_unlock_work(tp);
5901 }
5902
5903 static int rtl8169_poll(struct napi_struct *napi, int budget)
5904 {
5905 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5906 struct net_device *dev = tp->dev;
5907 int work_done;
5908
5909 work_done = rtl_rx(dev, tp, (u32) budget);
5910
5911 rtl_tx(dev, tp, budget);
5912
5913 if (work_done < budget) {
5914 napi_complete_done(napi, work_done);
5915 rtl_irq_enable(tp);
5916 }
5917
5918 return work_done;
5919 }
5920
5921 static void rtl8169_rx_missed(struct net_device *dev)
5922 {
5923 struct rtl8169_private *tp = netdev_priv(dev);
5924
5925 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5926 return;
5927
5928 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
5929 RTL_W32(tp, RxMissed, 0);
5930 }
5931
5932 static void r8169_phylink_handler(struct net_device *ndev)
5933 {
5934 struct rtl8169_private *tp = netdev_priv(ndev);
5935
5936 if (netif_carrier_ok(ndev)) {
5937 rtl_link_chg_patch(tp);
5938 pm_request_resume(&tp->pci_dev->dev);
5939 } else {
5940 pm_runtime_idle(&tp->pci_dev->dev);
5941 }
5942
5943 if (net_ratelimit())
5944 phy_print_status(tp->phydev);
5945 }
5946
5947 static int r8169_phy_connect(struct rtl8169_private *tp)
5948 {
5949 struct phy_device *phydev = tp->phydev;
5950 phy_interface_t phy_mode;
5951 int ret;
5952
5953 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
5954 PHY_INTERFACE_MODE_MII;
5955
5956 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
5957 phy_mode);
5958 if (ret)
5959 return ret;
5960
5961 if (!tp->supports_gmii)
5962 phy_set_max_speed(phydev, SPEED_100);
5963
5964 phy_support_asym_pause(phydev);
5965
5966 phy_attached_info(phydev);
5967
5968 return 0;
5969 }
5970
5971 static void rtl8169_down(struct net_device *dev)
5972 {
5973 struct rtl8169_private *tp = netdev_priv(dev);
5974
5975 phy_stop(tp->phydev);
5976
5977 napi_disable(&tp->napi);
5978 netif_stop_queue(dev);
5979
5980 rtl8169_hw_reset(tp);
5981 /*
5982 * At this point device interrupts can not be enabled in any function,
5983 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
5984 * and napi is disabled (rtl8169_poll).
5985 */
5986 rtl8169_rx_missed(dev);
5987
5988 /* Give a racing hard_start_xmit a few cycles to complete. */
5989 synchronize_rcu();
5990
5991 rtl8169_tx_clear(tp);
5992
5993 rtl8169_rx_clear(tp);
5994
5995 rtl_pll_power_down(tp);
5996 }
5997
5998 static int rtl8169_close(struct net_device *dev)
5999 {
6000 struct rtl8169_private *tp = netdev_priv(dev);
6001 struct pci_dev *pdev = tp->pci_dev;
6002
6003 pm_runtime_get_sync(&pdev->dev);
6004
6005 /* Update counters before going down */
6006 rtl8169_update_counters(tp);
6007
6008 rtl_lock_work(tp);
6009 /* Clear all task flags */
6010 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6011
6012 rtl8169_down(dev);
6013 rtl_unlock_work(tp);
6014
6015 cancel_work_sync(&tp->wk.work);
6016
6017 phy_disconnect(tp->phydev);
6018
6019 pci_free_irq(pdev, 0, tp);
6020
6021 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6022 tp->RxPhyAddr);
6023 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6024 tp->TxPhyAddr);
6025 tp->TxDescArray = NULL;
6026 tp->RxDescArray = NULL;
6027
6028 pm_runtime_put_sync(&pdev->dev);
6029
6030 return 0;
6031 }
6032
6033 #ifdef CONFIG_NET_POLL_CONTROLLER
6034 static void rtl8169_netpoll(struct net_device *dev)
6035 {
6036 struct rtl8169_private *tp = netdev_priv(dev);
6037
6038 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6039 }
6040 #endif
6041
6042 static int rtl_open(struct net_device *dev)
6043 {
6044 struct rtl8169_private *tp = netdev_priv(dev);
6045 struct pci_dev *pdev = tp->pci_dev;
6046 int retval = -ENOMEM;
6047
6048 pm_runtime_get_sync(&pdev->dev);
6049
6050 /*
6051 * Rx and Tx descriptors needs 256 bytes alignment.
6052 * dma_alloc_coherent provides more.
6053 */
6054 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6055 &tp->TxPhyAddr, GFP_KERNEL);
6056 if (!tp->TxDescArray)
6057 goto err_pm_runtime_put;
6058
6059 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6060 &tp->RxPhyAddr, GFP_KERNEL);
6061 if (!tp->RxDescArray)
6062 goto err_free_tx_0;
6063
6064 retval = rtl8169_init_ring(tp);
6065 if (retval < 0)
6066 goto err_free_rx_1;
6067
6068 rtl_request_firmware(tp);
6069
6070 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6071 dev->name);
6072 if (retval < 0)
6073 goto err_release_fw_2;
6074
6075 retval = r8169_phy_connect(tp);
6076 if (retval)
6077 goto err_free_irq;
6078
6079 rtl_lock_work(tp);
6080
6081 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6082
6083 napi_enable(&tp->napi);
6084
6085 rtl8169_init_phy(dev, tp);
6086
6087 rtl_pll_power_up(tp);
6088
6089 rtl_hw_start(tp);
6090
6091 if (!rtl8169_init_counter_offsets(tp))
6092 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6093
6094 phy_start(tp->phydev);
6095 netif_start_queue(dev);
6096
6097 rtl_unlock_work(tp);
6098
6099 pm_runtime_put_sync(&pdev->dev);
6100 out:
6101 return retval;
6102
6103 err_free_irq:
6104 pci_free_irq(pdev, 0, tp);
6105 err_release_fw_2:
6106 rtl_release_firmware(tp);
6107 rtl8169_rx_clear(tp);
6108 err_free_rx_1:
6109 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6110 tp->RxPhyAddr);
6111 tp->RxDescArray = NULL;
6112 err_free_tx_0:
6113 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6114 tp->TxPhyAddr);
6115 tp->TxDescArray = NULL;
6116 err_pm_runtime_put:
6117 pm_runtime_put_noidle(&pdev->dev);
6118 goto out;
6119 }
6120
6121 static void
6122 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6123 {
6124 struct rtl8169_private *tp = netdev_priv(dev);
6125 struct pci_dev *pdev = tp->pci_dev;
6126 struct rtl8169_counters *counters = tp->counters;
6127 unsigned int start;
6128
6129 pm_runtime_get_noresume(&pdev->dev);
6130
6131 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6132 rtl8169_rx_missed(dev);
6133
6134 do {
6135 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6136 stats->rx_packets = tp->rx_stats.packets;
6137 stats->rx_bytes = tp->rx_stats.bytes;
6138 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6139
6140 do {
6141 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6142 stats->tx_packets = tp->tx_stats.packets;
6143 stats->tx_bytes = tp->tx_stats.bytes;
6144 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6145
6146 stats->rx_dropped = dev->stats.rx_dropped;
6147 stats->tx_dropped = dev->stats.tx_dropped;
6148 stats->rx_length_errors = dev->stats.rx_length_errors;
6149 stats->rx_errors = dev->stats.rx_errors;
6150 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6151 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6152 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6153 stats->multicast = dev->stats.multicast;
6154
6155 /*
6156 * Fetch additional counter values missing in stats collected by driver
6157 * from tally counters.
6158 */
6159 if (pm_runtime_active(&pdev->dev))
6160 rtl8169_update_counters(tp);
6161
6162 /*
6163 * Subtract values fetched during initalization.
6164 * See rtl8169_init_counter_offsets for a description why we do that.
6165 */
6166 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6167 le64_to_cpu(tp->tc_offset.tx_errors);
6168 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6169 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6170 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6171 le16_to_cpu(tp->tc_offset.tx_aborted);
6172
6173 pm_runtime_put_noidle(&pdev->dev);
6174 }
6175
6176 static void rtl8169_net_suspend(struct net_device *dev)
6177 {
6178 struct rtl8169_private *tp = netdev_priv(dev);
6179
6180 if (!netif_running(dev))
6181 return;
6182
6183 phy_stop(tp->phydev);
6184 netif_device_detach(dev);
6185
6186 rtl_lock_work(tp);
6187 napi_disable(&tp->napi);
6188 /* Clear all task flags */
6189 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6190
6191 rtl_unlock_work(tp);
6192
6193 rtl_pll_power_down(tp);
6194 }
6195
6196 #ifdef CONFIG_PM
6197
6198 static int rtl8169_suspend(struct device *device)
6199 {
6200 struct net_device *dev = dev_get_drvdata(device);
6201 struct rtl8169_private *tp = netdev_priv(dev);
6202
6203 rtl8169_net_suspend(dev);
6204 clk_disable_unprepare(tp->clk);
6205
6206 return 0;
6207 }
6208
6209 static void __rtl8169_resume(struct net_device *dev)
6210 {
6211 struct rtl8169_private *tp = netdev_priv(dev);
6212
6213 netif_device_attach(dev);
6214
6215 rtl_pll_power_up(tp);
6216 rtl8169_init_phy(dev, tp);
6217
6218 phy_start(tp->phydev);
6219
6220 rtl_lock_work(tp);
6221 napi_enable(&tp->napi);
6222 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6223 rtl_reset_work(tp);
6224 rtl_unlock_work(tp);
6225 }
6226
6227 static int rtl8169_resume(struct device *device)
6228 {
6229 struct net_device *dev = dev_get_drvdata(device);
6230 struct rtl8169_private *tp = netdev_priv(dev);
6231
6232 rtl_rar_set(tp, dev->dev_addr);
6233
6234 clk_prepare_enable(tp->clk);
6235
6236 if (netif_running(dev))
6237 __rtl8169_resume(dev);
6238
6239 return 0;
6240 }
6241
6242 static int rtl8169_runtime_suspend(struct device *device)
6243 {
6244 struct net_device *dev = dev_get_drvdata(device);
6245 struct rtl8169_private *tp = netdev_priv(dev);
6246
6247 if (!tp->TxDescArray)
6248 return 0;
6249
6250 rtl_lock_work(tp);
6251 __rtl8169_set_wol(tp, WAKE_ANY);
6252 rtl_unlock_work(tp);
6253
6254 rtl8169_net_suspend(dev);
6255
6256 /* Update counters before going runtime suspend */
6257 rtl8169_rx_missed(dev);
6258 rtl8169_update_counters(tp);
6259
6260 return 0;
6261 }
6262
6263 static int rtl8169_runtime_resume(struct device *device)
6264 {
6265 struct net_device *dev = dev_get_drvdata(device);
6266 struct rtl8169_private *tp = netdev_priv(dev);
6267
6268 rtl_rar_set(tp, dev->dev_addr);
6269
6270 if (!tp->TxDescArray)
6271 return 0;
6272
6273 rtl_lock_work(tp);
6274 __rtl8169_set_wol(tp, tp->saved_wolopts);
6275 rtl_unlock_work(tp);
6276
6277 __rtl8169_resume(dev);
6278
6279 return 0;
6280 }
6281
6282 static int rtl8169_runtime_idle(struct device *device)
6283 {
6284 struct net_device *dev = dev_get_drvdata(device);
6285
6286 if (!netif_running(dev) || !netif_carrier_ok(dev))
6287 pm_schedule_suspend(device, 10000);
6288
6289 return -EBUSY;
6290 }
6291
6292 static const struct dev_pm_ops rtl8169_pm_ops = {
6293 .suspend = rtl8169_suspend,
6294 .resume = rtl8169_resume,
6295 .freeze = rtl8169_suspend,
6296 .thaw = rtl8169_resume,
6297 .poweroff = rtl8169_suspend,
6298 .restore = rtl8169_resume,
6299 .runtime_suspend = rtl8169_runtime_suspend,
6300 .runtime_resume = rtl8169_runtime_resume,
6301 .runtime_idle = rtl8169_runtime_idle,
6302 };
6303
6304 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
6305
6306 #else /* !CONFIG_PM */
6307
6308 #define RTL8169_PM_OPS NULL
6309
6310 #endif /* !CONFIG_PM */
6311
6312 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6313 {
6314 /* WoL fails with 8168b when the receiver is disabled. */
6315 switch (tp->mac_version) {
6316 case RTL_GIGA_MAC_VER_11:
6317 case RTL_GIGA_MAC_VER_12:
6318 case RTL_GIGA_MAC_VER_17:
6319 pci_clear_master(tp->pci_dev);
6320
6321 RTL_W8(tp, ChipCmd, CmdRxEnb);
6322 /* PCI commit */
6323 RTL_R8(tp, ChipCmd);
6324 break;
6325 default:
6326 break;
6327 }
6328 }
6329
6330 static void rtl_shutdown(struct pci_dev *pdev)
6331 {
6332 struct net_device *dev = pci_get_drvdata(pdev);
6333 struct rtl8169_private *tp = netdev_priv(dev);
6334
6335 rtl8169_net_suspend(dev);
6336
6337 /* Restore original MAC address */
6338 rtl_rar_set(tp, dev->perm_addr);
6339
6340 rtl8169_hw_reset(tp);
6341
6342 if (system_state == SYSTEM_POWER_OFF) {
6343 if (tp->saved_wolopts) {
6344 rtl_wol_suspend_quirk(tp);
6345 rtl_wol_shutdown_quirk(tp);
6346 }
6347
6348 pci_wake_from_d3(pdev, true);
6349 pci_set_power_state(pdev, PCI_D3hot);
6350 }
6351 }
6352
6353 static void rtl_remove_one(struct pci_dev *pdev)
6354 {
6355 struct net_device *dev = pci_get_drvdata(pdev);
6356 struct rtl8169_private *tp = netdev_priv(dev);
6357
6358 if (r8168_check_dash(tp))
6359 rtl8168_driver_stop(tp);
6360
6361 netif_napi_del(&tp->napi);
6362
6363 unregister_netdev(dev);
6364 mdiobus_unregister(tp->phydev->mdio.bus);
6365
6366 rtl_release_firmware(tp);
6367
6368 if (pci_dev_run_wake(pdev))
6369 pm_runtime_get_noresume(&pdev->dev);
6370
6371 /* restore original MAC address */
6372 rtl_rar_set(tp, dev->perm_addr);
6373 }
6374
6375 static const struct net_device_ops rtl_netdev_ops = {
6376 .ndo_open = rtl_open,
6377 .ndo_stop = rtl8169_close,
6378 .ndo_get_stats64 = rtl8169_get_stats64,
6379 .ndo_start_xmit = rtl8169_start_xmit,
6380 .ndo_features_check = rtl8169_features_check,
6381 .ndo_tx_timeout = rtl8169_tx_timeout,
6382 .ndo_validate_addr = eth_validate_addr,
6383 .ndo_change_mtu = rtl8169_change_mtu,
6384 .ndo_fix_features = rtl8169_fix_features,
6385 .ndo_set_features = rtl8169_set_features,
6386 .ndo_set_mac_address = rtl_set_mac_address,
6387 .ndo_do_ioctl = rtl8169_ioctl,
6388 .ndo_set_rx_mode = rtl_set_rx_mode,
6389 #ifdef CONFIG_NET_POLL_CONTROLLER
6390 .ndo_poll_controller = rtl8169_netpoll,
6391 #endif
6392
6393 };
6394
6395 static void rtl_set_irq_mask(struct rtl8169_private *tp)
6396 {
6397 tp->irq_mask = RTL_EVENT_NAPI | LinkChg;
6398
6399 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6400 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
6401 else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
6402 /* special workaround needed */
6403 tp->irq_mask |= RxFIFOOver;
6404 else
6405 tp->irq_mask |= RxOverflow;
6406 }
6407
6408 static int rtl_alloc_irq(struct rtl8169_private *tp)
6409 {
6410 unsigned int flags;
6411
6412 switch (tp->mac_version) {
6413 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
6414 rtl_unlock_config_regs(tp);
6415 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
6416 rtl_lock_config_regs(tp);
6417 /* fall through */
6418 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_24:
6419 flags = PCI_IRQ_LEGACY;
6420 break;
6421 default:
6422 flags = PCI_IRQ_ALL_TYPES;
6423 break;
6424 }
6425
6426 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
6427 }
6428
6429 static void rtl_read_mac_address(struct rtl8169_private *tp,
6430 u8 mac_addr[ETH_ALEN])
6431 {
6432 /* Get MAC address */
6433 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
6434 u32 value = rtl_eri_read(tp, 0xe0);
6435
6436 mac_addr[0] = (value >> 0) & 0xff;
6437 mac_addr[1] = (value >> 8) & 0xff;
6438 mac_addr[2] = (value >> 16) & 0xff;
6439 mac_addr[3] = (value >> 24) & 0xff;
6440
6441 value = rtl_eri_read(tp, 0xe4);
6442 mac_addr[4] = (value >> 0) & 0xff;
6443 mac_addr[5] = (value >> 8) & 0xff;
6444 }
6445 }
6446
6447 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6448 {
6449 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
6450 }
6451
6452 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6453 {
6454 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6455 }
6456
6457 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
6458 {
6459 struct rtl8169_private *tp = mii_bus->priv;
6460
6461 if (phyaddr > 0)
6462 return -ENODEV;
6463
6464 return rtl_readphy(tp, phyreg);
6465 }
6466
6467 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
6468 int phyreg, u16 val)
6469 {
6470 struct rtl8169_private *tp = mii_bus->priv;
6471
6472 if (phyaddr > 0)
6473 return -ENODEV;
6474
6475 rtl_writephy(tp, phyreg, val);
6476
6477 return 0;
6478 }
6479
6480 static int r8169_mdio_register(struct rtl8169_private *tp)
6481 {
6482 struct pci_dev *pdev = tp->pci_dev;
6483 struct mii_bus *new_bus;
6484 int ret;
6485
6486 new_bus = devm_mdiobus_alloc(&pdev->dev);
6487 if (!new_bus)
6488 return -ENOMEM;
6489
6490 new_bus->name = "r8169";
6491 new_bus->priv = tp;
6492 new_bus->parent = &pdev->dev;
6493 new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
6494 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
6495
6496 new_bus->read = r8169_mdio_read_reg;
6497 new_bus->write = r8169_mdio_write_reg;
6498
6499 ret = mdiobus_register(new_bus);
6500 if (ret)
6501 return ret;
6502
6503 tp->phydev = mdiobus_get_phy(new_bus, 0);
6504 if (!tp->phydev) {
6505 mdiobus_unregister(new_bus);
6506 return -ENODEV;
6507 }
6508
6509 /* PHY will be woken up in rtl_open() */
6510 phy_suspend(tp->phydev);
6511
6512 return 0;
6513 }
6514
6515 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6516 {
6517 tp->ocp_base = OCP_STD_PHY_BASE;
6518
6519 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
6520
6521 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6522 return;
6523
6524 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6525 return;
6526
6527 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6528 msleep(1);
6529 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6530
6531 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
6532
6533 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6534 return;
6535
6536 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
6537
6538 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
6539 }
6540
6541 static void rtl_hw_initialize(struct rtl8169_private *tp)
6542 {
6543 switch (tp->mac_version) {
6544 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
6545 rtl8168ep_stop_cmac(tp);
6546 /* fall through */
6547 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
6548 rtl_hw_init_8168g(tp);
6549 break;
6550 default:
6551 break;
6552 }
6553 }
6554
6555 static int rtl_jumbo_max(struct rtl8169_private *tp)
6556 {
6557 /* Non-GBit versions don't support jumbo frames */
6558 if (!tp->supports_gmii)
6559 return JUMBO_1K;
6560
6561 switch (tp->mac_version) {
6562 /* RTL8169 */
6563 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
6564 return JUMBO_7K;
6565 /* RTL8168b */
6566 case RTL_GIGA_MAC_VER_11:
6567 case RTL_GIGA_MAC_VER_12:
6568 case RTL_GIGA_MAC_VER_17:
6569 return JUMBO_4K;
6570 /* RTL8168c */
6571 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
6572 return JUMBO_6K;
6573 default:
6574 return JUMBO_9K;
6575 }
6576 }
6577
6578 static void rtl_disable_clk(void *data)
6579 {
6580 clk_disable_unprepare(data);
6581 }
6582
6583 static int rtl_get_ether_clk(struct rtl8169_private *tp)
6584 {
6585 struct device *d = tp_to_dev(tp);
6586 struct clk *clk;
6587 int rc;
6588
6589 clk = devm_clk_get(d, "ether_clk");
6590 if (IS_ERR(clk)) {
6591 rc = PTR_ERR(clk);
6592 if (rc == -ENOENT)
6593 /* clk-core allows NULL (for suspend / resume) */
6594 rc = 0;
6595 else if (rc != -EPROBE_DEFER)
6596 dev_err(d, "failed to get clk: %d\n", rc);
6597 } else {
6598 tp->clk = clk;
6599 rc = clk_prepare_enable(clk);
6600 if (rc)
6601 dev_err(d, "failed to enable clk: %d\n", rc);
6602 else
6603 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
6604 }
6605
6606 return rc;
6607 }
6608
6609 static void rtl_init_mac_address(struct rtl8169_private *tp)
6610 {
6611 struct net_device *dev = tp->dev;
6612 u8 *mac_addr = dev->dev_addr;
6613 int rc, i;
6614
6615 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
6616 if (!rc)
6617 goto done;
6618
6619 rtl_read_mac_address(tp, mac_addr);
6620 if (is_valid_ether_addr(mac_addr))
6621 goto done;
6622
6623 for (i = 0; i < ETH_ALEN; i++)
6624 mac_addr[i] = RTL_R8(tp, MAC0 + i);
6625 if (is_valid_ether_addr(mac_addr))
6626 goto done;
6627
6628 eth_hw_addr_random(dev);
6629 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
6630 done:
6631 rtl_rar_set(tp, mac_addr);
6632 }
6633
6634 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6635 {
6636 struct rtl8169_private *tp;
6637 struct net_device *dev;
6638 int chipset, region;
6639 int jumbo_max, rc;
6640
6641 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
6642 if (!dev)
6643 return -ENOMEM;
6644
6645 SET_NETDEV_DEV(dev, &pdev->dev);
6646 dev->netdev_ops = &rtl_netdev_ops;
6647 tp = netdev_priv(dev);
6648 tp->dev = dev;
6649 tp->pci_dev = pdev;
6650 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6651 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
6652
6653 /* Get the *optional* external "ether_clk" used on some boards */
6654 rc = rtl_get_ether_clk(tp);
6655 if (rc)
6656 return rc;
6657
6658 /* Disable ASPM completely as that cause random device stop working
6659 * problems as well as full system hangs for some PCIe devices users.
6660 */
6661 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
6662 PCIE_LINK_STATE_L1);
6663 tp->aspm_manageable = !rc;
6664
6665 /* enable device (incl. PCI PM wakeup and hotplug setup) */
6666 rc = pcim_enable_device(pdev);
6667 if (rc < 0) {
6668 dev_err(&pdev->dev, "enable failure\n");
6669 return rc;
6670 }
6671
6672 if (pcim_set_mwi(pdev) < 0)
6673 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
6674
6675 /* use first MMIO region */
6676 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
6677 if (region < 0) {
6678 dev_err(&pdev->dev, "no MMIO resource found\n");
6679 return -ENODEV;
6680 }
6681
6682 /* check for weird/broken PCI region reporting */
6683 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6684 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
6685 return -ENODEV;
6686 }
6687
6688 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
6689 if (rc < 0) {
6690 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
6691 return rc;
6692 }
6693
6694 tp->mmio_addr = pcim_iomap_table(pdev)[region];
6695
6696 /* Identify chip attached to board */
6697 rtl8169_get_mac_version(tp);
6698 if (tp->mac_version == RTL_GIGA_MAC_NONE)
6699 return -ENODEV;
6700
6701 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
6702
6703 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
6704 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
6705 dev->features |= NETIF_F_HIGHDMA;
6706
6707 rtl_init_rxcfg(tp);
6708
6709 rtl8169_irq_mask_and_ack(tp);
6710
6711 rtl_hw_initialize(tp);
6712
6713 rtl_hw_reset(tp);
6714
6715 pci_set_master(pdev);
6716
6717 chipset = tp->mac_version;
6718
6719 rc = rtl_alloc_irq(tp);
6720 if (rc < 0) {
6721 dev_err(&pdev->dev, "Can't allocate interrupt\n");
6722 return rc;
6723 }
6724
6725 mutex_init(&tp->wk.mutex);
6726 INIT_WORK(&tp->wk.work, rtl_task);
6727 u64_stats_init(&tp->rx_stats.syncp);
6728 u64_stats_init(&tp->tx_stats.syncp);
6729
6730 rtl_init_mac_address(tp);
6731
6732 dev->ethtool_ops = &rtl8169_ethtool_ops;
6733
6734 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
6735
6736 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6737 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
6738 NETIF_F_HW_VLAN_CTAG_RX;
6739 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6740 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
6741 NETIF_F_HW_VLAN_CTAG_RX;
6742 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6743 NETIF_F_HIGHDMA;
6744 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
6745
6746 tp->cp_cmd |= RxChkSum | RxVlan;
6747
6748 /*
6749 * Pretend we are using VLANs; This bypasses a nasty bug where
6750 * Interrupts stop flowing on high load on 8110SCd controllers.
6751 */
6752 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6753 /* Disallow toggling */
6754 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
6755
6756 if (rtl_chip_supports_csum_v2(tp)) {
6757 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
6758 dev->features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
6759 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2;
6760 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2;
6761 } else {
6762 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1;
6763 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1;
6764 }
6765
6766 /* RTL8168e-vl has a HW issue with TSO */
6767 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
6768 dev->vlan_features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG);
6769 dev->hw_features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG);
6770 dev->features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG);
6771 }
6772
6773 dev->hw_features |= NETIF_F_RXALL;
6774 dev->hw_features |= NETIF_F_RXFCS;
6775
6776 /* MTU range: 60 - hw-specific max */
6777 dev->min_mtu = ETH_ZLEN;
6778 jumbo_max = rtl_jumbo_max(tp);
6779 dev->max_mtu = jumbo_max;
6780
6781 rtl_set_irq_mask(tp);
6782
6783 tp->fw_name = rtl_chip_infos[chipset].fw_name;
6784
6785 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
6786 &tp->counters_phys_addr,
6787 GFP_KERNEL);
6788 if (!tp->counters)
6789 return -ENOMEM;
6790
6791 pci_set_drvdata(pdev, dev);
6792
6793 rc = r8169_mdio_register(tp);
6794 if (rc)
6795 return rc;
6796
6797 /* chip gets powered up in rtl_open() */
6798 rtl_pll_power_down(tp);
6799
6800 rc = register_netdev(dev);
6801 if (rc)
6802 goto err_mdio_unregister;
6803
6804 netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
6805 rtl_chip_infos[chipset].name, dev->dev_addr,
6806 (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
6807 pci_irq_vector(pdev, 0));
6808
6809 if (jumbo_max > JUMBO_1K)
6810 netif_info(tp, probe, dev,
6811 "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
6812 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
6813 "ok" : "ko");
6814
6815 if (r8168_check_dash(tp))
6816 rtl8168_driver_start(tp);
6817
6818 if (pci_dev_run_wake(pdev))
6819 pm_runtime_put_sync(&pdev->dev);
6820
6821 return 0;
6822
6823 err_mdio_unregister:
6824 mdiobus_unregister(tp->phydev->mdio.bus);
6825 return rc;
6826 }
6827
6828 static struct pci_driver rtl8169_pci_driver = {
6829 .name = MODULENAME,
6830 .id_table = rtl8169_pci_tbl,
6831 .probe = rtl_init_one,
6832 .remove = rtl_remove_one,
6833 .shutdown = rtl_shutdown,
6834 .driver.pm = RTL8169_PM_OPS,
6835 };
6836
6837 module_pci_driver(rtl8169_pci_driver);
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