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[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / realtek / r8169_main.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 *
5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
7 * Copyright (c) a lot of people too. Please respect their work.
8 *
9 * See MAINTAINERS file for support contact information.
10 */
11
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/pci.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/ethtool.h>
20 #include <linux/phy.h>
21 #include <linux/if_vlan.h>
22 #include <linux/crc32.h>
23 #include <linux/in.h>
24 #include <linux/io.h>
25 #include <linux/ip.h>
26 #include <linux/tcp.h>
27 #include <linux/interrupt.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/prefetch.h>
31 #include <linux/pci-aspm.h>
32 #include <linux/ipv6.h>
33 #include <net/ip6_checksum.h>
34
35 #include "r8169_firmware.h"
36
37 #define MODULENAME "r8169"
38
39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
47 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
48 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
49 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
50 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
51 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
52 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
53 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
54 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
55 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
56 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
57 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
58
59 #define R8169_MSG_DEFAULT \
60 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
61
62 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
63 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
64 static const int multicast_filter_limit = 32;
65
66 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
67 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
68
69 #define R8169_REGS_SIZE 256
70 #define R8169_RX_BUF_SIZE (SZ_16K - 1)
71 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
72 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
73 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
74 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
75
76 #define RTL_CFG_NO_GBIT 1
77
78 /* write/read MMIO register */
79 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
80 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
81 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
82 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
83 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
84 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
85
86 enum mac_version {
87 /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */
88 RTL_GIGA_MAC_VER_02,
89 RTL_GIGA_MAC_VER_03,
90 RTL_GIGA_MAC_VER_04,
91 RTL_GIGA_MAC_VER_05,
92 RTL_GIGA_MAC_VER_06,
93 RTL_GIGA_MAC_VER_07,
94 RTL_GIGA_MAC_VER_08,
95 RTL_GIGA_MAC_VER_09,
96 RTL_GIGA_MAC_VER_10,
97 RTL_GIGA_MAC_VER_11,
98 RTL_GIGA_MAC_VER_12,
99 RTL_GIGA_MAC_VER_13,
100 RTL_GIGA_MAC_VER_14,
101 RTL_GIGA_MAC_VER_15,
102 RTL_GIGA_MAC_VER_16,
103 RTL_GIGA_MAC_VER_17,
104 RTL_GIGA_MAC_VER_18,
105 RTL_GIGA_MAC_VER_19,
106 RTL_GIGA_MAC_VER_20,
107 RTL_GIGA_MAC_VER_21,
108 RTL_GIGA_MAC_VER_22,
109 RTL_GIGA_MAC_VER_23,
110 RTL_GIGA_MAC_VER_24,
111 RTL_GIGA_MAC_VER_25,
112 RTL_GIGA_MAC_VER_26,
113 RTL_GIGA_MAC_VER_27,
114 RTL_GIGA_MAC_VER_28,
115 RTL_GIGA_MAC_VER_29,
116 RTL_GIGA_MAC_VER_30,
117 RTL_GIGA_MAC_VER_31,
118 RTL_GIGA_MAC_VER_32,
119 RTL_GIGA_MAC_VER_33,
120 RTL_GIGA_MAC_VER_34,
121 RTL_GIGA_MAC_VER_35,
122 RTL_GIGA_MAC_VER_36,
123 RTL_GIGA_MAC_VER_37,
124 RTL_GIGA_MAC_VER_38,
125 RTL_GIGA_MAC_VER_39,
126 RTL_GIGA_MAC_VER_40,
127 RTL_GIGA_MAC_VER_41,
128 RTL_GIGA_MAC_VER_42,
129 RTL_GIGA_MAC_VER_43,
130 RTL_GIGA_MAC_VER_44,
131 RTL_GIGA_MAC_VER_45,
132 RTL_GIGA_MAC_VER_46,
133 RTL_GIGA_MAC_VER_47,
134 RTL_GIGA_MAC_VER_48,
135 RTL_GIGA_MAC_VER_49,
136 RTL_GIGA_MAC_VER_50,
137 RTL_GIGA_MAC_VER_51,
138 RTL_GIGA_MAC_NONE
139 };
140
141 #define JUMBO_1K ETH_DATA_LEN
142 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
143 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
144 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
145 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
146
147 static const struct {
148 const char *name;
149 const char *fw_name;
150 } rtl_chip_infos[] = {
151 /* PCI devices. */
152 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
153 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
154 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
155 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
156 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
157 /* PCI-E devices. */
158 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
159 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
160 [RTL_GIGA_MAC_VER_09] = {"RTL8102e" },
161 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
162 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
163 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
164 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" },
165 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" },
166 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" },
167 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
168 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
169 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
170 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
171 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
172 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
173 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
174 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
175 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
176 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
177 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
178 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
179 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
180 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
181 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
182 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
183 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
184 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
185 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
186 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
187 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
188 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
189 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
190 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
191 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
192 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
193 [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g", FIRMWARE_8168G_3},
194 [RTL_GIGA_MAC_VER_43] = {"RTL8106e", FIRMWARE_8106E_2},
195 [RTL_GIGA_MAC_VER_44] = {"RTL8411", FIRMWARE_8411_2 },
196 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
197 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
198 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
199 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
200 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
201 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
202 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
203 };
204
205 static const struct pci_device_id rtl8169_pci_tbl[] = {
206 { PCI_VDEVICE(REALTEK, 0x2502) },
207 { PCI_VDEVICE(REALTEK, 0x2600) },
208 { PCI_VDEVICE(REALTEK, 0x8129) },
209 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
210 { PCI_VDEVICE(REALTEK, 0x8161) },
211 { PCI_VDEVICE(REALTEK, 0x8167) },
212 { PCI_VDEVICE(REALTEK, 0x8168) },
213 { PCI_VDEVICE(NCUBE, 0x8168) },
214 { PCI_VDEVICE(REALTEK, 0x8169) },
215 { PCI_VENDOR_ID_DLINK, 0x4300,
216 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
217 { PCI_VDEVICE(DLINK, 0x4300), },
218 { PCI_VDEVICE(DLINK, 0x4302), },
219 { PCI_VDEVICE(AT, 0xc107), },
220 { PCI_VDEVICE(USR, 0x0116), },
221 { PCI_VENDOR_ID_LINKSYS, 0x1032,
222 PCI_ANY_ID, 0x0024, 0, 0 },
223 { 0x0001, 0x8168,
224 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_NO_GBIT },
225 {}
226 };
227
228 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
229
230 static struct {
231 u32 msg_enable;
232 } debug = { -1 };
233
234 enum rtl_registers {
235 MAC0 = 0, /* Ethernet hardware address. */
236 MAC4 = 4,
237 MAR0 = 8, /* Multicast filter. */
238 CounterAddrLow = 0x10,
239 CounterAddrHigh = 0x14,
240 TxDescStartAddrLow = 0x20,
241 TxDescStartAddrHigh = 0x24,
242 TxHDescStartAddrLow = 0x28,
243 TxHDescStartAddrHigh = 0x2c,
244 FLASH = 0x30,
245 ERSR = 0x36,
246 ChipCmd = 0x37,
247 TxPoll = 0x38,
248 IntrMask = 0x3c,
249 IntrStatus = 0x3e,
250
251 TxConfig = 0x40,
252 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
253 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
254
255 RxConfig = 0x44,
256 #define RX128_INT_EN (1 << 15) /* 8111c and later */
257 #define RX_MULTI_EN (1 << 14) /* 8111c only */
258 #define RXCFG_FIFO_SHIFT 13
259 /* No threshold before first PCI xfer */
260 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
261 #define RX_EARLY_OFF (1 << 11)
262 #define RXCFG_DMA_SHIFT 8
263 /* Unlimited maximum PCI burst. */
264 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
265
266 RxMissed = 0x4c,
267 Cfg9346 = 0x50,
268 Config0 = 0x51,
269 Config1 = 0x52,
270 Config2 = 0x53,
271 #define PME_SIGNAL (1 << 5) /* 8168c and later */
272
273 Config3 = 0x54,
274 Config4 = 0x55,
275 Config5 = 0x56,
276 MultiIntr = 0x5c,
277 PHYAR = 0x60,
278 PHYstatus = 0x6c,
279 RxMaxSize = 0xda,
280 CPlusCmd = 0xe0,
281 IntrMitigate = 0xe2,
282
283 #define RTL_COALESCE_MASK 0x0f
284 #define RTL_COALESCE_SHIFT 4
285 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
286 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
287
288 RxDescAddrLow = 0xe4,
289 RxDescAddrHigh = 0xe8,
290 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
291
292 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
293
294 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
295
296 #define TxPacketMax (8064 >> 7)
297 #define EarlySize 0x27
298
299 FuncEvent = 0xf0,
300 FuncEventMask = 0xf4,
301 FuncPresetState = 0xf8,
302 IBCR0 = 0xf8,
303 IBCR2 = 0xf9,
304 IBIMR0 = 0xfa,
305 IBISR0 = 0xfb,
306 FuncForceEvent = 0xfc,
307 };
308
309 enum rtl8168_8101_registers {
310 CSIDR = 0x64,
311 CSIAR = 0x68,
312 #define CSIAR_FLAG 0x80000000
313 #define CSIAR_WRITE_CMD 0x80000000
314 #define CSIAR_BYTE_ENABLE 0x0000f000
315 #define CSIAR_ADDR_MASK 0x00000fff
316 PMCH = 0x6f,
317 EPHYAR = 0x80,
318 #define EPHYAR_FLAG 0x80000000
319 #define EPHYAR_WRITE_CMD 0x80000000
320 #define EPHYAR_REG_MASK 0x1f
321 #define EPHYAR_REG_SHIFT 16
322 #define EPHYAR_DATA_MASK 0xffff
323 DLLPR = 0xd0,
324 #define PFM_EN (1 << 6)
325 #define TX_10M_PS_EN (1 << 7)
326 DBG_REG = 0xd1,
327 #define FIX_NAK_1 (1 << 4)
328 #define FIX_NAK_2 (1 << 3)
329 TWSI = 0xd2,
330 MCU = 0xd3,
331 #define NOW_IS_OOB (1 << 7)
332 #define TX_EMPTY (1 << 5)
333 #define RX_EMPTY (1 << 4)
334 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
335 #define EN_NDP (1 << 3)
336 #define EN_OOB_RESET (1 << 2)
337 #define LINK_LIST_RDY (1 << 1)
338 EFUSEAR = 0xdc,
339 #define EFUSEAR_FLAG 0x80000000
340 #define EFUSEAR_WRITE_CMD 0x80000000
341 #define EFUSEAR_READ_CMD 0x00000000
342 #define EFUSEAR_REG_MASK 0x03ff
343 #define EFUSEAR_REG_SHIFT 8
344 #define EFUSEAR_DATA_MASK 0xff
345 MISC_1 = 0xf2,
346 #define PFM_D3COLD_EN (1 << 6)
347 };
348
349 enum rtl8168_registers {
350 LED_FREQ = 0x1a,
351 EEE_LED = 0x1b,
352 ERIDR = 0x70,
353 ERIAR = 0x74,
354 #define ERIAR_FLAG 0x80000000
355 #define ERIAR_WRITE_CMD 0x80000000
356 #define ERIAR_READ_CMD 0x00000000
357 #define ERIAR_ADDR_BYTE_ALIGN 4
358 #define ERIAR_TYPE_SHIFT 16
359 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
360 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
361 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
362 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
363 #define ERIAR_MASK_SHIFT 12
364 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
365 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
366 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
367 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
368 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
369 EPHY_RXER_NUM = 0x7c,
370 OCPDR = 0xb0, /* OCP GPHY access */
371 #define OCPDR_WRITE_CMD 0x80000000
372 #define OCPDR_READ_CMD 0x00000000
373 #define OCPDR_REG_MASK 0x7f
374 #define OCPDR_GPHY_REG_SHIFT 16
375 #define OCPDR_DATA_MASK 0xffff
376 OCPAR = 0xb4,
377 #define OCPAR_FLAG 0x80000000
378 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
379 #define OCPAR_GPHY_READ_CMD 0x0000f060
380 GPHY_OCP = 0xb8,
381 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
382 MISC = 0xf0, /* 8168e only. */
383 #define TXPLA_RST (1 << 29)
384 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
385 #define PWM_EN (1 << 22)
386 #define RXDV_GATED_EN (1 << 19)
387 #define EARLY_TALLY_EN (1 << 16)
388 };
389
390 enum rtl_register_content {
391 /* InterruptStatusBits */
392 SYSErr = 0x8000,
393 PCSTimeout = 0x4000,
394 SWInt = 0x0100,
395 TxDescUnavail = 0x0080,
396 RxFIFOOver = 0x0040,
397 LinkChg = 0x0020,
398 RxOverflow = 0x0010,
399 TxErr = 0x0008,
400 TxOK = 0x0004,
401 RxErr = 0x0002,
402 RxOK = 0x0001,
403
404 /* RxStatusDesc */
405 RxRWT = (1 << 22),
406 RxRES = (1 << 21),
407 RxRUNT = (1 << 20),
408 RxCRC = (1 << 19),
409
410 /* ChipCmdBits */
411 StopReq = 0x80,
412 CmdReset = 0x10,
413 CmdRxEnb = 0x08,
414 CmdTxEnb = 0x04,
415 RxBufEmpty = 0x01,
416
417 /* TXPoll register p.5 */
418 HPQ = 0x80, /* Poll cmd on the high prio queue */
419 NPQ = 0x40, /* Poll cmd on the low prio queue */
420 FSWInt = 0x01, /* Forced software interrupt */
421
422 /* Cfg9346Bits */
423 Cfg9346_Lock = 0x00,
424 Cfg9346_Unlock = 0xc0,
425
426 /* rx_mode_bits */
427 AcceptErr = 0x20,
428 AcceptRunt = 0x10,
429 AcceptBroadcast = 0x08,
430 AcceptMulticast = 0x04,
431 AcceptMyPhys = 0x02,
432 AcceptAllPhys = 0x01,
433 #define RX_CONFIG_ACCEPT_MASK 0x3f
434
435 /* TxConfigBits */
436 TxInterFrameGapShift = 24,
437 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
438
439 /* Config1 register p.24 */
440 LEDS1 = (1 << 7),
441 LEDS0 = (1 << 6),
442 Speed_down = (1 << 4),
443 MEMMAP = (1 << 3),
444 IOMAP = (1 << 2),
445 VPD = (1 << 1),
446 PMEnable = (1 << 0), /* Power Management Enable */
447
448 /* Config2 register p. 25 */
449 ClkReqEn = (1 << 7), /* Clock Request Enable */
450 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
451 PCI_Clock_66MHz = 0x01,
452 PCI_Clock_33MHz = 0x00,
453
454 /* Config3 register p.25 */
455 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
456 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
457 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
458 Rdy_to_L23 = (1 << 1), /* L23 Enable */
459 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
460
461 /* Config4 register */
462 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
463
464 /* Config5 register p.27 */
465 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
466 MWF = (1 << 5), /* Accept Multicast wakeup frame */
467 UWF = (1 << 4), /* Accept Unicast wakeup frame */
468 Spi_en = (1 << 3),
469 LanWake = (1 << 1), /* LanWake enable/disable */
470 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
471 ASPM_en = (1 << 0), /* ASPM enable */
472
473 /* CPlusCmd p.31 */
474 EnableBist = (1 << 15), // 8168 8101
475 Mac_dbgo_oe = (1 << 14), // 8168 8101
476 Normal_mode = (1 << 13), // unused
477 Force_half_dup = (1 << 12), // 8168 8101
478 Force_rxflow_en = (1 << 11), // 8168 8101
479 Force_txflow_en = (1 << 10), // 8168 8101
480 Cxpl_dbg_sel = (1 << 9), // 8168 8101
481 ASF = (1 << 8), // 8168 8101
482 PktCntrDisable = (1 << 7), // 8168 8101
483 Mac_dbgo_sel = 0x001c, // 8168
484 RxVlan = (1 << 6),
485 RxChkSum = (1 << 5),
486 PCIDAC = (1 << 4),
487 PCIMulRW = (1 << 3),
488 #define INTT_MASK GENMASK(1, 0)
489 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
490
491 /* rtl8169_PHYstatus */
492 TBI_Enable = 0x80,
493 TxFlowCtrl = 0x40,
494 RxFlowCtrl = 0x20,
495 _1000bpsF = 0x10,
496 _100bps = 0x08,
497 _10bps = 0x04,
498 LinkStatus = 0x02,
499 FullDup = 0x01,
500
501 /* ResetCounterCommand */
502 CounterReset = 0x1,
503
504 /* DumpCounterCommand */
505 CounterDump = 0x8,
506
507 /* magic enable v2 */
508 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
509 };
510
511 enum rtl_desc_bit {
512 /* First doubleword. */
513 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
514 RingEnd = (1 << 30), /* End of descriptor ring */
515 FirstFrag = (1 << 29), /* First segment of a packet */
516 LastFrag = (1 << 28), /* Final segment of a packet */
517 };
518
519 /* Generic case. */
520 enum rtl_tx_desc_bit {
521 /* First doubleword. */
522 TD_LSO = (1 << 27), /* Large Send Offload */
523 #define TD_MSS_MAX 0x07ffu /* MSS value */
524
525 /* Second doubleword. */
526 TxVlanTag = (1 << 17), /* Add VLAN tag */
527 };
528
529 /* 8169, 8168b and 810x except 8102e. */
530 enum rtl_tx_desc_bit_0 {
531 /* First doubleword. */
532 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
533 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
534 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
535 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
536 };
537
538 /* 8102e, 8168c and beyond. */
539 enum rtl_tx_desc_bit_1 {
540 /* First doubleword. */
541 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
542 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
543 #define GTTCPHO_SHIFT 18
544 #define GTTCPHO_MAX 0x7fU
545
546 /* Second doubleword. */
547 #define TCPHO_SHIFT 18
548 #define TCPHO_MAX 0x3ffU
549 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
550 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
551 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
552 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
553 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
554 };
555
556 enum rtl_rx_desc_bit {
557 /* Rx private */
558 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
559 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
560
561 #define RxProtoUDP (PID1)
562 #define RxProtoTCP (PID0)
563 #define RxProtoIP (PID1 | PID0)
564 #define RxProtoMask RxProtoIP
565
566 IPFail = (1 << 16), /* IP checksum failed */
567 UDPFail = (1 << 15), /* UDP/IP checksum failed */
568 TCPFail = (1 << 14), /* TCP/IP checksum failed */
569 RxVlanTag = (1 << 16), /* VLAN tag available */
570 };
571
572 #define RsvdMask 0x3fffc000
573
574 struct TxDesc {
575 __le32 opts1;
576 __le32 opts2;
577 __le64 addr;
578 };
579
580 struct RxDesc {
581 __le32 opts1;
582 __le32 opts2;
583 __le64 addr;
584 };
585
586 struct ring_info {
587 struct sk_buff *skb;
588 u32 len;
589 };
590
591 struct rtl8169_counters {
592 __le64 tx_packets;
593 __le64 rx_packets;
594 __le64 tx_errors;
595 __le32 rx_errors;
596 __le16 rx_missed;
597 __le16 align_errors;
598 __le32 tx_one_collision;
599 __le32 tx_multi_collision;
600 __le64 rx_unicast;
601 __le64 rx_broadcast;
602 __le32 rx_multicast;
603 __le16 tx_aborted;
604 __le16 tx_underun;
605 };
606
607 struct rtl8169_tc_offsets {
608 bool inited;
609 __le64 tx_errors;
610 __le32 tx_multi_collision;
611 __le16 tx_aborted;
612 };
613
614 enum rtl_flag {
615 RTL_FLAG_TASK_ENABLED = 0,
616 RTL_FLAG_TASK_RESET_PENDING,
617 RTL_FLAG_MAX
618 };
619
620 struct rtl8169_stats {
621 u64 packets;
622 u64 bytes;
623 struct u64_stats_sync syncp;
624 };
625
626 struct rtl8169_private {
627 void __iomem *mmio_addr; /* memory map physical address */
628 struct pci_dev *pci_dev;
629 struct net_device *dev;
630 struct phy_device *phydev;
631 struct napi_struct napi;
632 u32 msg_enable;
633 enum mac_version mac_version;
634 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
635 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
636 u32 dirty_tx;
637 struct rtl8169_stats rx_stats;
638 struct rtl8169_stats tx_stats;
639 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
640 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
641 dma_addr_t TxPhyAddr;
642 dma_addr_t RxPhyAddr;
643 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
644 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
645 u16 cp_cmd;
646
647 u16 irq_mask;
648 const struct rtl_coalesce_info *coalesce_info;
649 struct clk *clk;
650
651 struct {
652 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
653 struct mutex mutex;
654 struct work_struct work;
655 } wk;
656
657 unsigned irq_enabled:1;
658 unsigned supports_gmii:1;
659 dma_addr_t counters_phys_addr;
660 struct rtl8169_counters *counters;
661 struct rtl8169_tc_offsets tc_offset;
662 u32 saved_wolopts;
663
664 const char *fw_name;
665 struct rtl_fw *rtl_fw;
666
667 u32 ocp_base;
668 };
669
670 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
671
672 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
673 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
674 module_param_named(debug, debug.msg_enable, int, 0);
675 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
676 MODULE_SOFTDEP("pre: realtek");
677 MODULE_LICENSE("GPL");
678 MODULE_FIRMWARE(FIRMWARE_8168D_1);
679 MODULE_FIRMWARE(FIRMWARE_8168D_2);
680 MODULE_FIRMWARE(FIRMWARE_8168E_1);
681 MODULE_FIRMWARE(FIRMWARE_8168E_2);
682 MODULE_FIRMWARE(FIRMWARE_8168E_3);
683 MODULE_FIRMWARE(FIRMWARE_8105E_1);
684 MODULE_FIRMWARE(FIRMWARE_8168F_1);
685 MODULE_FIRMWARE(FIRMWARE_8168F_2);
686 MODULE_FIRMWARE(FIRMWARE_8402_1);
687 MODULE_FIRMWARE(FIRMWARE_8411_1);
688 MODULE_FIRMWARE(FIRMWARE_8411_2);
689 MODULE_FIRMWARE(FIRMWARE_8106E_1);
690 MODULE_FIRMWARE(FIRMWARE_8106E_2);
691 MODULE_FIRMWARE(FIRMWARE_8168G_2);
692 MODULE_FIRMWARE(FIRMWARE_8168G_3);
693 MODULE_FIRMWARE(FIRMWARE_8168H_1);
694 MODULE_FIRMWARE(FIRMWARE_8168H_2);
695 MODULE_FIRMWARE(FIRMWARE_8107E_1);
696 MODULE_FIRMWARE(FIRMWARE_8107E_2);
697
698 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
699 {
700 return &tp->pci_dev->dev;
701 }
702
703 static void rtl_lock_work(struct rtl8169_private *tp)
704 {
705 mutex_lock(&tp->wk.mutex);
706 }
707
708 static void rtl_unlock_work(struct rtl8169_private *tp)
709 {
710 mutex_unlock(&tp->wk.mutex);
711 }
712
713 static void rtl_lock_config_regs(struct rtl8169_private *tp)
714 {
715 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
716 }
717
718 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
719 {
720 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
721 }
722
723 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
724 {
725 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
726 PCI_EXP_DEVCTL_READRQ, force);
727 }
728
729 struct rtl_cond {
730 bool (*check)(struct rtl8169_private *);
731 const char *msg;
732 };
733
734 static void rtl_udelay(unsigned int d)
735 {
736 udelay(d);
737 }
738
739 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
740 void (*delay)(unsigned int), unsigned int d, int n,
741 bool high)
742 {
743 int i;
744
745 for (i = 0; i < n; i++) {
746 if (c->check(tp) == high)
747 return true;
748 delay(d);
749 }
750 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
751 c->msg, !high, n, d);
752 return false;
753 }
754
755 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
756 const struct rtl_cond *c,
757 unsigned int d, int n)
758 {
759 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
760 }
761
762 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
763 const struct rtl_cond *c,
764 unsigned int d, int n)
765 {
766 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
767 }
768
769 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
770 const struct rtl_cond *c,
771 unsigned int d, int n)
772 {
773 return rtl_loop_wait(tp, c, msleep, d, n, true);
774 }
775
776 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
777 const struct rtl_cond *c,
778 unsigned int d, int n)
779 {
780 return rtl_loop_wait(tp, c, msleep, d, n, false);
781 }
782
783 #define DECLARE_RTL_COND(name) \
784 static bool name ## _check(struct rtl8169_private *); \
785 \
786 static const struct rtl_cond name = { \
787 .check = name ## _check, \
788 .msg = #name \
789 }; \
790 \
791 static bool name ## _check(struct rtl8169_private *tp)
792
793 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
794 {
795 if (reg & 0xffff0001) {
796 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
797 return true;
798 }
799 return false;
800 }
801
802 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
803 {
804 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
805 }
806
807 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
808 {
809 if (rtl_ocp_reg_failure(tp, reg))
810 return;
811
812 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
813
814 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
815 }
816
817 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
818 {
819 if (rtl_ocp_reg_failure(tp, reg))
820 return 0;
821
822 RTL_W32(tp, GPHY_OCP, reg << 15);
823
824 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
825 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
826 }
827
828 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
829 {
830 if (rtl_ocp_reg_failure(tp, reg))
831 return;
832
833 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
834 }
835
836 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
837 {
838 if (rtl_ocp_reg_failure(tp, reg))
839 return 0;
840
841 RTL_W32(tp, OCPDR, reg << 15);
842
843 return RTL_R32(tp, OCPDR);
844 }
845
846 #define OCP_STD_PHY_BASE 0xa400
847
848 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
849 {
850 if (reg == 0x1f) {
851 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
852 return;
853 }
854
855 if (tp->ocp_base != OCP_STD_PHY_BASE)
856 reg -= 0x10;
857
858 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
859 }
860
861 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
862 {
863 if (tp->ocp_base != OCP_STD_PHY_BASE)
864 reg -= 0x10;
865
866 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
867 }
868
869 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
870 {
871 if (reg == 0x1f) {
872 tp->ocp_base = value << 4;
873 return;
874 }
875
876 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
877 }
878
879 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
880 {
881 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
882 }
883
884 DECLARE_RTL_COND(rtl_phyar_cond)
885 {
886 return RTL_R32(tp, PHYAR) & 0x80000000;
887 }
888
889 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
890 {
891 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
892
893 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
894 /*
895 * According to hardware specs a 20us delay is required after write
896 * complete indication, but before sending next command.
897 */
898 udelay(20);
899 }
900
901 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
902 {
903 int value;
904
905 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
906
907 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
908 RTL_R32(tp, PHYAR) & 0xffff : ~0;
909
910 /*
911 * According to hardware specs a 20us delay is required after read
912 * complete indication, but before sending next command.
913 */
914 udelay(20);
915
916 return value;
917 }
918
919 DECLARE_RTL_COND(rtl_ocpar_cond)
920 {
921 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
922 }
923
924 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
925 {
926 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
927 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
928 RTL_W32(tp, EPHY_RXER_NUM, 0);
929
930 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
931 }
932
933 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
934 {
935 r8168dp_1_mdio_access(tp, reg,
936 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
937 }
938
939 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
940 {
941 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
942
943 mdelay(1);
944 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
945 RTL_W32(tp, EPHY_RXER_NUM, 0);
946
947 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
948 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
949 }
950
951 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
952
953 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
954 {
955 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
956 }
957
958 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
959 {
960 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
961 }
962
963 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
964 {
965 r8168dp_2_mdio_start(tp);
966
967 r8169_mdio_write(tp, reg, value);
968
969 r8168dp_2_mdio_stop(tp);
970 }
971
972 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
973 {
974 int value;
975
976 r8168dp_2_mdio_start(tp);
977
978 value = r8169_mdio_read(tp, reg);
979
980 r8168dp_2_mdio_stop(tp);
981
982 return value;
983 }
984
985 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
986 {
987 switch (tp->mac_version) {
988 case RTL_GIGA_MAC_VER_27:
989 r8168dp_1_mdio_write(tp, location, val);
990 break;
991 case RTL_GIGA_MAC_VER_28:
992 case RTL_GIGA_MAC_VER_31:
993 r8168dp_2_mdio_write(tp, location, val);
994 break;
995 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
996 r8168g_mdio_write(tp, location, val);
997 break;
998 default:
999 r8169_mdio_write(tp, location, val);
1000 break;
1001 }
1002 }
1003
1004 static int rtl_readphy(struct rtl8169_private *tp, int location)
1005 {
1006 switch (tp->mac_version) {
1007 case RTL_GIGA_MAC_VER_27:
1008 return r8168dp_1_mdio_read(tp, location);
1009 case RTL_GIGA_MAC_VER_28:
1010 case RTL_GIGA_MAC_VER_31:
1011 return r8168dp_2_mdio_read(tp, location);
1012 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1013 return r8168g_mdio_read(tp, location);
1014 default:
1015 return r8169_mdio_read(tp, location);
1016 }
1017 }
1018
1019 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1020 {
1021 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1022 }
1023
1024 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1025 {
1026 int val;
1027
1028 val = rtl_readphy(tp, reg_addr);
1029 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1030 }
1031
1032 DECLARE_RTL_COND(rtl_ephyar_cond)
1033 {
1034 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1035 }
1036
1037 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1038 {
1039 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1040 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1041
1042 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1043
1044 udelay(10);
1045 }
1046
1047 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1048 {
1049 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1050
1051 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1052 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1053 }
1054
1055 DECLARE_RTL_COND(rtl_eriar_cond)
1056 {
1057 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1058 }
1059
1060 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1061 u32 val, int type)
1062 {
1063 BUG_ON((addr & 3) || (mask == 0));
1064 RTL_W32(tp, ERIDR, val);
1065 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1066
1067 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1068 }
1069
1070 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1071 u32 val)
1072 {
1073 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1074 }
1075
1076 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1077 {
1078 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1079
1080 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1081 RTL_R32(tp, ERIDR) : ~0;
1082 }
1083
1084 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1085 {
1086 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1087 }
1088
1089 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1090 u32 m)
1091 {
1092 u32 val;
1093
1094 val = rtl_eri_read(tp, addr);
1095 rtl_eri_write(tp, addr, mask, (val & ~m) | p);
1096 }
1097
1098 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,
1099 u32 p)
1100 {
1101 rtl_w0w1_eri(tp, addr, mask, p, 0);
1102 }
1103
1104 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
1105 u32 m)
1106 {
1107 rtl_w0w1_eri(tp, addr, mask, 0, m);
1108 }
1109
1110 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1111 {
1112 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1113 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1114 RTL_R32(tp, OCPDR) : ~0;
1115 }
1116
1117 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1118 {
1119 return _rtl_eri_read(tp, reg, ERIAR_OOB);
1120 }
1121
1122 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1123 u32 data)
1124 {
1125 RTL_W32(tp, OCPDR, data);
1126 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1127 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1128 }
1129
1130 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1131 u32 data)
1132 {
1133 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1134 data, ERIAR_OOB);
1135 }
1136
1137 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1138 {
1139 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1140
1141 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1142 }
1143
1144 #define OOB_CMD_RESET 0x00
1145 #define OOB_CMD_DRIVER_START 0x05
1146 #define OOB_CMD_DRIVER_STOP 0x06
1147
1148 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1149 {
1150 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1151 }
1152
1153 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1154 {
1155 u16 reg;
1156
1157 reg = rtl8168_get_ocp_reg(tp);
1158
1159 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1160 }
1161
1162 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1163 {
1164 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1165 }
1166
1167 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1168 {
1169 return RTL_R8(tp, IBISR0) & 0x20;
1170 }
1171
1172 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1173 {
1174 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1175 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1176 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1177 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1178 }
1179
1180 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1181 {
1182 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1183 rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1184 }
1185
1186 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1187 {
1188 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1189 r8168ep_ocp_write(tp, 0x01, 0x30,
1190 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1191 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1192 }
1193
1194 static void rtl8168_driver_start(struct rtl8169_private *tp)
1195 {
1196 switch (tp->mac_version) {
1197 case RTL_GIGA_MAC_VER_27:
1198 case RTL_GIGA_MAC_VER_28:
1199 case RTL_GIGA_MAC_VER_31:
1200 rtl8168dp_driver_start(tp);
1201 break;
1202 case RTL_GIGA_MAC_VER_49:
1203 case RTL_GIGA_MAC_VER_50:
1204 case RTL_GIGA_MAC_VER_51:
1205 rtl8168ep_driver_start(tp);
1206 break;
1207 default:
1208 BUG();
1209 break;
1210 }
1211 }
1212
1213 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1214 {
1215 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1216 rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1217 }
1218
1219 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1220 {
1221 rtl8168ep_stop_cmac(tp);
1222 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1223 r8168ep_ocp_write(tp, 0x01, 0x30,
1224 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1225 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1226 }
1227
1228 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1229 {
1230 switch (tp->mac_version) {
1231 case RTL_GIGA_MAC_VER_27:
1232 case RTL_GIGA_MAC_VER_28:
1233 case RTL_GIGA_MAC_VER_31:
1234 rtl8168dp_driver_stop(tp);
1235 break;
1236 case RTL_GIGA_MAC_VER_49:
1237 case RTL_GIGA_MAC_VER_50:
1238 case RTL_GIGA_MAC_VER_51:
1239 rtl8168ep_driver_stop(tp);
1240 break;
1241 default:
1242 BUG();
1243 break;
1244 }
1245 }
1246
1247 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1248 {
1249 u16 reg = rtl8168_get_ocp_reg(tp);
1250
1251 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1252 }
1253
1254 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1255 {
1256 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1257 }
1258
1259 static bool r8168_check_dash(struct rtl8169_private *tp)
1260 {
1261 switch (tp->mac_version) {
1262 case RTL_GIGA_MAC_VER_27:
1263 case RTL_GIGA_MAC_VER_28:
1264 case RTL_GIGA_MAC_VER_31:
1265 return r8168dp_check_dash(tp);
1266 case RTL_GIGA_MAC_VER_49:
1267 case RTL_GIGA_MAC_VER_50:
1268 case RTL_GIGA_MAC_VER_51:
1269 return r8168ep_check_dash(tp);
1270 default:
1271 return false;
1272 }
1273 }
1274
1275 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1276 {
1277 rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1278 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1279 }
1280
1281 DECLARE_RTL_COND(rtl_efusear_cond)
1282 {
1283 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1284 }
1285
1286 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1287 {
1288 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1289
1290 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1291 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1292 }
1293
1294 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1295 {
1296 RTL_W16(tp, IntrStatus, bits);
1297 }
1298
1299 static void rtl_irq_disable(struct rtl8169_private *tp)
1300 {
1301 RTL_W16(tp, IntrMask, 0);
1302 tp->irq_enabled = 0;
1303 }
1304
1305 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1306 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1307 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1308
1309 static void rtl_irq_enable(struct rtl8169_private *tp)
1310 {
1311 tp->irq_enabled = 1;
1312 RTL_W16(tp, IntrMask, tp->irq_mask);
1313 }
1314
1315 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1316 {
1317 rtl_irq_disable(tp);
1318 rtl_ack_events(tp, 0xffff);
1319 /* PCI commit */
1320 RTL_R8(tp, ChipCmd);
1321 }
1322
1323 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1324 {
1325 struct net_device *dev = tp->dev;
1326 struct phy_device *phydev = tp->phydev;
1327
1328 if (!netif_running(dev))
1329 return;
1330
1331 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1332 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1333 if (phydev->speed == SPEED_1000) {
1334 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1335 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1336 } else if (phydev->speed == SPEED_100) {
1337 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1338 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1339 } else {
1340 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1341 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1342 }
1343 rtl_reset_packet_filter(tp);
1344 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1345 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1346 if (phydev->speed == SPEED_1000) {
1347 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1348 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1349 } else {
1350 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1351 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1352 }
1353 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1354 if (phydev->speed == SPEED_10) {
1355 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1356 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1357 } else {
1358 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1359 }
1360 }
1361 }
1362
1363 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1364
1365 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1366 {
1367 struct rtl8169_private *tp = netdev_priv(dev);
1368
1369 rtl_lock_work(tp);
1370 wol->supported = WAKE_ANY;
1371 wol->wolopts = tp->saved_wolopts;
1372 rtl_unlock_work(tp);
1373 }
1374
1375 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1376 {
1377 unsigned int i, tmp;
1378 static const struct {
1379 u32 opt;
1380 u16 reg;
1381 u8 mask;
1382 } cfg[] = {
1383 { WAKE_PHY, Config3, LinkUp },
1384 { WAKE_UCAST, Config5, UWF },
1385 { WAKE_BCAST, Config5, BWF },
1386 { WAKE_MCAST, Config5, MWF },
1387 { WAKE_ANY, Config5, LanWake },
1388 { WAKE_MAGIC, Config3, MagicPacket }
1389 };
1390 u8 options;
1391
1392 rtl_unlock_config_regs(tp);
1393
1394 switch (tp->mac_version) {
1395 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1396 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1397 tmp = ARRAY_SIZE(cfg) - 1;
1398 if (wolopts & WAKE_MAGIC)
1399 rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
1400 MagicPacket_v2);
1401 else
1402 rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
1403 MagicPacket_v2);
1404 break;
1405 default:
1406 tmp = ARRAY_SIZE(cfg);
1407 break;
1408 }
1409
1410 for (i = 0; i < tmp; i++) {
1411 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1412 if (wolopts & cfg[i].opt)
1413 options |= cfg[i].mask;
1414 RTL_W8(tp, cfg[i].reg, options);
1415 }
1416
1417 switch (tp->mac_version) {
1418 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_17:
1419 options = RTL_R8(tp, Config1) & ~PMEnable;
1420 if (wolopts)
1421 options |= PMEnable;
1422 RTL_W8(tp, Config1, options);
1423 break;
1424 default:
1425 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1426 if (wolopts)
1427 options |= PME_SIGNAL;
1428 RTL_W8(tp, Config2, options);
1429 break;
1430 }
1431
1432 rtl_lock_config_regs(tp);
1433
1434 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1435 }
1436
1437 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1438 {
1439 struct rtl8169_private *tp = netdev_priv(dev);
1440 struct device *d = tp_to_dev(tp);
1441
1442 if (wol->wolopts & ~WAKE_ANY)
1443 return -EINVAL;
1444
1445 pm_runtime_get_noresume(d);
1446
1447 rtl_lock_work(tp);
1448
1449 tp->saved_wolopts = wol->wolopts;
1450
1451 if (pm_runtime_active(d))
1452 __rtl8169_set_wol(tp, tp->saved_wolopts);
1453
1454 rtl_unlock_work(tp);
1455
1456 pm_runtime_put_noidle(d);
1457
1458 return 0;
1459 }
1460
1461 static void rtl8169_get_drvinfo(struct net_device *dev,
1462 struct ethtool_drvinfo *info)
1463 {
1464 struct rtl8169_private *tp = netdev_priv(dev);
1465 struct rtl_fw *rtl_fw = tp->rtl_fw;
1466
1467 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1468 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1469 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1470 if (rtl_fw)
1471 strlcpy(info->fw_version, rtl_fw->version,
1472 sizeof(info->fw_version));
1473 }
1474
1475 static int rtl8169_get_regs_len(struct net_device *dev)
1476 {
1477 return R8169_REGS_SIZE;
1478 }
1479
1480 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1481 netdev_features_t features)
1482 {
1483 struct rtl8169_private *tp = netdev_priv(dev);
1484
1485 if (dev->mtu > TD_MSS_MAX)
1486 features &= ~NETIF_F_ALL_TSO;
1487
1488 if (dev->mtu > JUMBO_1K &&
1489 tp->mac_version > RTL_GIGA_MAC_VER_06)
1490 features &= ~NETIF_F_IP_CSUM;
1491
1492 return features;
1493 }
1494
1495 static int rtl8169_set_features(struct net_device *dev,
1496 netdev_features_t features)
1497 {
1498 struct rtl8169_private *tp = netdev_priv(dev);
1499 u32 rx_config;
1500
1501 rtl_lock_work(tp);
1502
1503 rx_config = RTL_R32(tp, RxConfig);
1504 if (features & NETIF_F_RXALL)
1505 rx_config |= (AcceptErr | AcceptRunt);
1506 else
1507 rx_config &= ~(AcceptErr | AcceptRunt);
1508
1509 RTL_W32(tp, RxConfig, rx_config);
1510
1511 if (features & NETIF_F_RXCSUM)
1512 tp->cp_cmd |= RxChkSum;
1513 else
1514 tp->cp_cmd &= ~RxChkSum;
1515
1516 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1517 tp->cp_cmd |= RxVlan;
1518 else
1519 tp->cp_cmd &= ~RxVlan;
1520
1521 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1522 RTL_R16(tp, CPlusCmd);
1523
1524 rtl_unlock_work(tp);
1525
1526 return 0;
1527 }
1528
1529 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1530 {
1531 return (skb_vlan_tag_present(skb)) ?
1532 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1533 }
1534
1535 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1536 {
1537 u32 opts2 = le32_to_cpu(desc->opts2);
1538
1539 if (opts2 & RxVlanTag)
1540 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1541 }
1542
1543 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1544 void *p)
1545 {
1546 struct rtl8169_private *tp = netdev_priv(dev);
1547 u32 __iomem *data = tp->mmio_addr;
1548 u32 *dw = p;
1549 int i;
1550
1551 rtl_lock_work(tp);
1552 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1553 memcpy_fromio(dw++, data++, 4);
1554 rtl_unlock_work(tp);
1555 }
1556
1557 static u32 rtl8169_get_msglevel(struct net_device *dev)
1558 {
1559 struct rtl8169_private *tp = netdev_priv(dev);
1560
1561 return tp->msg_enable;
1562 }
1563
1564 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1565 {
1566 struct rtl8169_private *tp = netdev_priv(dev);
1567
1568 tp->msg_enable = value;
1569 }
1570
1571 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1572 "tx_packets",
1573 "rx_packets",
1574 "tx_errors",
1575 "rx_errors",
1576 "rx_missed",
1577 "align_errors",
1578 "tx_single_collisions",
1579 "tx_multi_collisions",
1580 "unicast",
1581 "broadcast",
1582 "multicast",
1583 "tx_aborted",
1584 "tx_underrun",
1585 };
1586
1587 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1588 {
1589 switch (sset) {
1590 case ETH_SS_STATS:
1591 return ARRAY_SIZE(rtl8169_gstrings);
1592 default:
1593 return -EOPNOTSUPP;
1594 }
1595 }
1596
1597 DECLARE_RTL_COND(rtl_counters_cond)
1598 {
1599 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1600 }
1601
1602 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1603 {
1604 dma_addr_t paddr = tp->counters_phys_addr;
1605 u32 cmd;
1606
1607 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1608 RTL_R32(tp, CounterAddrHigh);
1609 cmd = (u64)paddr & DMA_BIT_MASK(32);
1610 RTL_W32(tp, CounterAddrLow, cmd);
1611 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1612
1613 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1614 }
1615
1616 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1617 {
1618 /*
1619 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1620 * tally counters.
1621 */
1622 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1623 return true;
1624
1625 return rtl8169_do_counters(tp, CounterReset);
1626 }
1627
1628 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1629 {
1630 u8 val = RTL_R8(tp, ChipCmd);
1631
1632 /*
1633 * Some chips are unable to dump tally counters when the receiver
1634 * is disabled. If 0xff chip may be in a PCI power-save state.
1635 */
1636 if (!(val & CmdRxEnb) || val == 0xff)
1637 return true;
1638
1639 return rtl8169_do_counters(tp, CounterDump);
1640 }
1641
1642 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1643 {
1644 struct rtl8169_counters *counters = tp->counters;
1645 bool ret = false;
1646
1647 /*
1648 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1649 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1650 * reset by a power cycle, while the counter values collected by the
1651 * driver are reset at every driver unload/load cycle.
1652 *
1653 * To make sure the HW values returned by @get_stats64 match the SW
1654 * values, we collect the initial values at first open(*) and use them
1655 * as offsets to normalize the values returned by @get_stats64.
1656 *
1657 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1658 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1659 * set at open time by rtl_hw_start.
1660 */
1661
1662 if (tp->tc_offset.inited)
1663 return true;
1664
1665 /* If both, reset and update fail, propagate to caller. */
1666 if (rtl8169_reset_counters(tp))
1667 ret = true;
1668
1669 if (rtl8169_update_counters(tp))
1670 ret = true;
1671
1672 tp->tc_offset.tx_errors = counters->tx_errors;
1673 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1674 tp->tc_offset.tx_aborted = counters->tx_aborted;
1675 tp->tc_offset.inited = true;
1676
1677 return ret;
1678 }
1679
1680 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1681 struct ethtool_stats *stats, u64 *data)
1682 {
1683 struct rtl8169_private *tp = netdev_priv(dev);
1684 struct device *d = tp_to_dev(tp);
1685 struct rtl8169_counters *counters = tp->counters;
1686
1687 ASSERT_RTNL();
1688
1689 pm_runtime_get_noresume(d);
1690
1691 if (pm_runtime_active(d))
1692 rtl8169_update_counters(tp);
1693
1694 pm_runtime_put_noidle(d);
1695
1696 data[0] = le64_to_cpu(counters->tx_packets);
1697 data[1] = le64_to_cpu(counters->rx_packets);
1698 data[2] = le64_to_cpu(counters->tx_errors);
1699 data[3] = le32_to_cpu(counters->rx_errors);
1700 data[4] = le16_to_cpu(counters->rx_missed);
1701 data[5] = le16_to_cpu(counters->align_errors);
1702 data[6] = le32_to_cpu(counters->tx_one_collision);
1703 data[7] = le32_to_cpu(counters->tx_multi_collision);
1704 data[8] = le64_to_cpu(counters->rx_unicast);
1705 data[9] = le64_to_cpu(counters->rx_broadcast);
1706 data[10] = le32_to_cpu(counters->rx_multicast);
1707 data[11] = le16_to_cpu(counters->tx_aborted);
1708 data[12] = le16_to_cpu(counters->tx_underun);
1709 }
1710
1711 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1712 {
1713 switch(stringset) {
1714 case ETH_SS_STATS:
1715 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1716 break;
1717 }
1718 }
1719
1720 /*
1721 * Interrupt coalescing
1722 *
1723 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1724 * > 8169, 8168 and 810x line of chipsets
1725 *
1726 * 8169, 8168, and 8136(810x) serial chipsets support it.
1727 *
1728 * > 2 - the Tx timer unit at gigabit speed
1729 *
1730 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1731 * (0xe0) bit 1 and bit 0.
1732 *
1733 * For 8169
1734 * bit[1:0] \ speed 1000M 100M 10M
1735 * 0 0 320ns 2.56us 40.96us
1736 * 0 1 2.56us 20.48us 327.7us
1737 * 1 0 5.12us 40.96us 655.4us
1738 * 1 1 10.24us 81.92us 1.31ms
1739 *
1740 * For the other
1741 * bit[1:0] \ speed 1000M 100M 10M
1742 * 0 0 5us 2.56us 40.96us
1743 * 0 1 40us 20.48us 327.7us
1744 * 1 0 80us 40.96us 655.4us
1745 * 1 1 160us 81.92us 1.31ms
1746 */
1747
1748 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1749 struct rtl_coalesce_scale {
1750 /* Rx / Tx */
1751 u32 nsecs[2];
1752 };
1753
1754 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1755 struct rtl_coalesce_info {
1756 u32 speed;
1757 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
1758 };
1759
1760 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1761 #define rxtx_x1822(r, t) { \
1762 {{(r), (t)}}, \
1763 {{(r)*8, (t)*8}}, \
1764 {{(r)*8*2, (t)*8*2}}, \
1765 {{(r)*8*2*2, (t)*8*2*2}}, \
1766 }
1767 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1768 /* speed delays: rx00 tx00 */
1769 { SPEED_10, rxtx_x1822(40960, 40960) },
1770 { SPEED_100, rxtx_x1822( 2560, 2560) },
1771 { SPEED_1000, rxtx_x1822( 320, 320) },
1772 { 0 },
1773 };
1774
1775 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1776 /* speed delays: rx00 tx00 */
1777 { SPEED_10, rxtx_x1822(40960, 40960) },
1778 { SPEED_100, rxtx_x1822( 2560, 2560) },
1779 { SPEED_1000, rxtx_x1822( 5000, 5000) },
1780 { 0 },
1781 };
1782 #undef rxtx_x1822
1783
1784 /* get rx/tx scale vector corresponding to current speed */
1785 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1786 {
1787 struct rtl8169_private *tp = netdev_priv(dev);
1788 struct ethtool_link_ksettings ecmd;
1789 const struct rtl_coalesce_info *ci;
1790 int rc;
1791
1792 rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1793 if (rc < 0)
1794 return ERR_PTR(rc);
1795
1796 for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1797 if (ecmd.base.speed == ci->speed) {
1798 return ci;
1799 }
1800 }
1801
1802 return ERR_PTR(-ELNRNG);
1803 }
1804
1805 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1806 {
1807 struct rtl8169_private *tp = netdev_priv(dev);
1808 const struct rtl_coalesce_info *ci;
1809 const struct rtl_coalesce_scale *scale;
1810 struct {
1811 u32 *max_frames;
1812 u32 *usecs;
1813 } coal_settings [] = {
1814 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1815 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1816 }, *p = coal_settings;
1817 int i;
1818 u16 w;
1819
1820 memset(ec, 0, sizeof(*ec));
1821
1822 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1823 ci = rtl_coalesce_info(dev);
1824 if (IS_ERR(ci))
1825 return PTR_ERR(ci);
1826
1827 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1828
1829 /* read IntrMitigate and adjust according to scale */
1830 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1831 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1832 w >>= RTL_COALESCE_SHIFT;
1833 *p->usecs = w & RTL_COALESCE_MASK;
1834 }
1835
1836 for (i = 0; i < 2; i++) {
1837 p = coal_settings + i;
1838 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1839
1840 /*
1841 * ethtool_coalesce says it is illegal to set both usecs and
1842 * max_frames to 0.
1843 */
1844 if (!*p->usecs && !*p->max_frames)
1845 *p->max_frames = 1;
1846 }
1847
1848 return 0;
1849 }
1850
1851 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1852 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1853 struct net_device *dev, u32 nsec, u16 *cp01)
1854 {
1855 const struct rtl_coalesce_info *ci;
1856 u16 i;
1857
1858 ci = rtl_coalesce_info(dev);
1859 if (IS_ERR(ci))
1860 return ERR_CAST(ci);
1861
1862 for (i = 0; i < 4; i++) {
1863 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1864 ci->scalev[i].nsecs[1]);
1865 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1866 *cp01 = i;
1867 return &ci->scalev[i];
1868 }
1869 }
1870
1871 return ERR_PTR(-EINVAL);
1872 }
1873
1874 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1875 {
1876 struct rtl8169_private *tp = netdev_priv(dev);
1877 const struct rtl_coalesce_scale *scale;
1878 struct {
1879 u32 frames;
1880 u32 usecs;
1881 } coal_settings [] = {
1882 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1883 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1884 }, *p = coal_settings;
1885 u16 w = 0, cp01;
1886 int i;
1887
1888 scale = rtl_coalesce_choose_scale(dev,
1889 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1890 if (IS_ERR(scale))
1891 return PTR_ERR(scale);
1892
1893 for (i = 0; i < 2; i++, p++) {
1894 u32 units;
1895
1896 /*
1897 * accept max_frames=1 we returned in rtl_get_coalesce.
1898 * accept it not only when usecs=0 because of e.g. the following scenario:
1899 *
1900 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1901 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1902 * - then user does `ethtool -C eth0 rx-usecs 100`
1903 *
1904 * since ethtool sends to kernel whole ethtool_coalesce
1905 * settings, if we do not handle rx_usecs=!0, rx_frames=1
1906 * we'll reject it below in `frames % 4 != 0`.
1907 */
1908 if (p->frames == 1) {
1909 p->frames = 0;
1910 }
1911
1912 units = p->usecs * 1000 / scale->nsecs[i];
1913 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
1914 return -EINVAL;
1915
1916 w <<= RTL_COALESCE_SHIFT;
1917 w |= units;
1918 w <<= RTL_COALESCE_SHIFT;
1919 w |= p->frames >> 2;
1920 }
1921
1922 rtl_lock_work(tp);
1923
1924 RTL_W16(tp, IntrMitigate, swab16(w));
1925
1926 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1927 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1928 RTL_R16(tp, CPlusCmd);
1929
1930 rtl_unlock_work(tp);
1931
1932 return 0;
1933 }
1934
1935 static int rtl_get_eee_supp(struct rtl8169_private *tp)
1936 {
1937 struct phy_device *phydev = tp->phydev;
1938 int ret;
1939
1940 switch (tp->mac_version) {
1941 case RTL_GIGA_MAC_VER_34:
1942 case RTL_GIGA_MAC_VER_35:
1943 case RTL_GIGA_MAC_VER_36:
1944 case RTL_GIGA_MAC_VER_38:
1945 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1946 break;
1947 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1948 ret = phy_read_paged(phydev, 0x0a5c, 0x12);
1949 break;
1950 default:
1951 ret = -EPROTONOSUPPORT;
1952 break;
1953 }
1954
1955 return ret;
1956 }
1957
1958 static int rtl_get_eee_lpadv(struct rtl8169_private *tp)
1959 {
1960 struct phy_device *phydev = tp->phydev;
1961 int ret;
1962
1963 switch (tp->mac_version) {
1964 case RTL_GIGA_MAC_VER_34:
1965 case RTL_GIGA_MAC_VER_35:
1966 case RTL_GIGA_MAC_VER_36:
1967 case RTL_GIGA_MAC_VER_38:
1968 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
1969 break;
1970 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1971 ret = phy_read_paged(phydev, 0x0a5d, 0x11);
1972 break;
1973 default:
1974 ret = -EPROTONOSUPPORT;
1975 break;
1976 }
1977
1978 return ret;
1979 }
1980
1981 static int rtl_get_eee_adv(struct rtl8169_private *tp)
1982 {
1983 struct phy_device *phydev = tp->phydev;
1984 int ret;
1985
1986 switch (tp->mac_version) {
1987 case RTL_GIGA_MAC_VER_34:
1988 case RTL_GIGA_MAC_VER_35:
1989 case RTL_GIGA_MAC_VER_36:
1990 case RTL_GIGA_MAC_VER_38:
1991 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
1992 break;
1993 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1994 ret = phy_read_paged(phydev, 0x0a5d, 0x10);
1995 break;
1996 default:
1997 ret = -EPROTONOSUPPORT;
1998 break;
1999 }
2000
2001 return ret;
2002 }
2003
2004 static int rtl_set_eee_adv(struct rtl8169_private *tp, int val)
2005 {
2006 struct phy_device *phydev = tp->phydev;
2007 int ret = 0;
2008
2009 switch (tp->mac_version) {
2010 case RTL_GIGA_MAC_VER_34:
2011 case RTL_GIGA_MAC_VER_35:
2012 case RTL_GIGA_MAC_VER_36:
2013 case RTL_GIGA_MAC_VER_38:
2014 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
2015 break;
2016 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2017 phy_write_paged(phydev, 0x0a5d, 0x10, val);
2018 break;
2019 default:
2020 ret = -EPROTONOSUPPORT;
2021 break;
2022 }
2023
2024 return ret;
2025 }
2026
2027 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
2028 {
2029 struct rtl8169_private *tp = netdev_priv(dev);
2030 struct device *d = tp_to_dev(tp);
2031 int ret;
2032
2033 pm_runtime_get_noresume(d);
2034
2035 if (!pm_runtime_active(d)) {
2036 ret = -EOPNOTSUPP;
2037 goto out;
2038 }
2039
2040 /* Get Supported EEE */
2041 ret = rtl_get_eee_supp(tp);
2042 if (ret < 0)
2043 goto out;
2044 data->supported = mmd_eee_cap_to_ethtool_sup_t(ret);
2045
2046 /* Get advertisement EEE */
2047 ret = rtl_get_eee_adv(tp);
2048 if (ret < 0)
2049 goto out;
2050 data->advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2051 data->eee_enabled = !!data->advertised;
2052
2053 /* Get LP advertisement EEE */
2054 ret = rtl_get_eee_lpadv(tp);
2055 if (ret < 0)
2056 goto out;
2057 data->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2058 data->eee_active = !!(data->advertised & data->lp_advertised);
2059 out:
2060 pm_runtime_put_noidle(d);
2061 return ret < 0 ? ret : 0;
2062 }
2063
2064 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
2065 {
2066 struct rtl8169_private *tp = netdev_priv(dev);
2067 struct device *d = tp_to_dev(tp);
2068 int old_adv, adv = 0, cap, ret;
2069
2070 pm_runtime_get_noresume(d);
2071
2072 if (!dev->phydev || !pm_runtime_active(d)) {
2073 ret = -EOPNOTSUPP;
2074 goto out;
2075 }
2076
2077 if (dev->phydev->autoneg == AUTONEG_DISABLE ||
2078 dev->phydev->duplex != DUPLEX_FULL) {
2079 ret = -EPROTONOSUPPORT;
2080 goto out;
2081 }
2082
2083 /* Get Supported EEE */
2084 ret = rtl_get_eee_supp(tp);
2085 if (ret < 0)
2086 goto out;
2087 cap = ret;
2088
2089 ret = rtl_get_eee_adv(tp);
2090 if (ret < 0)
2091 goto out;
2092 old_adv = ret;
2093
2094 if (data->eee_enabled) {
2095 adv = !data->advertised ? cap :
2096 ethtool_adv_to_mmd_eee_adv_t(data->advertised) & cap;
2097 /* Mask prohibited EEE modes */
2098 adv &= ~dev->phydev->eee_broken_modes;
2099 }
2100
2101 if (old_adv != adv) {
2102 ret = rtl_set_eee_adv(tp, adv);
2103 if (ret < 0)
2104 goto out;
2105
2106 /* Restart autonegotiation so the new modes get sent to the
2107 * link partner.
2108 */
2109 ret = phy_restart_aneg(dev->phydev);
2110 }
2111
2112 out:
2113 pm_runtime_put_noidle(d);
2114 return ret < 0 ? ret : 0;
2115 }
2116
2117 static const struct ethtool_ops rtl8169_ethtool_ops = {
2118 .get_drvinfo = rtl8169_get_drvinfo,
2119 .get_regs_len = rtl8169_get_regs_len,
2120 .get_link = ethtool_op_get_link,
2121 .get_coalesce = rtl_get_coalesce,
2122 .set_coalesce = rtl_set_coalesce,
2123 .get_msglevel = rtl8169_get_msglevel,
2124 .set_msglevel = rtl8169_set_msglevel,
2125 .get_regs = rtl8169_get_regs,
2126 .get_wol = rtl8169_get_wol,
2127 .set_wol = rtl8169_set_wol,
2128 .get_strings = rtl8169_get_strings,
2129 .get_sset_count = rtl8169_get_sset_count,
2130 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2131 .get_ts_info = ethtool_op_get_ts_info,
2132 .nway_reset = phy_ethtool_nway_reset,
2133 .get_eee = rtl8169_get_eee,
2134 .set_eee = rtl8169_set_eee,
2135 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2136 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2137 };
2138
2139 static void rtl_enable_eee(struct rtl8169_private *tp)
2140 {
2141 int supported = rtl_get_eee_supp(tp);
2142
2143 if (supported > 0)
2144 rtl_set_eee_adv(tp, supported);
2145 }
2146
2147 static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2148 {
2149 /*
2150 * The driver currently handles the 8168Bf and the 8168Be identically
2151 * but they can be identified more specifically through the test below
2152 * if needed:
2153 *
2154 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2155 *
2156 * Same thing for the 8101Eb and the 8101Ec:
2157 *
2158 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2159 */
2160 static const struct rtl_mac_info {
2161 u16 mask;
2162 u16 val;
2163 u16 mac_version;
2164 } mac_info[] = {
2165 /* 8168EP family. */
2166 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2167 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2168 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2169
2170 /* 8168H family. */
2171 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2172 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2173
2174 /* 8168G family. */
2175 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2176 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2177 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2178 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2179
2180 /* 8168F family. */
2181 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2182 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2183 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2184
2185 /* 8168E family. */
2186 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2187 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2188 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2189
2190 /* 8168D family. */
2191 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2192 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2193
2194 /* 8168DP family. */
2195 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2196 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2197 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2198
2199 /* 8168C family. */
2200 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2201 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2202 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2203 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2204 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2205 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2206 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2207
2208 /* 8168B family. */
2209 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2210 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2211 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2212
2213 /* 8101 family. */
2214 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2215 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2216 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2217 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2218 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2219 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2220 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2221 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2222 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2223 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2224 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2225 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2226 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2227 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2228 /* FIXME: where did these entries come from ? -- FR */
2229 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2230 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2231
2232 /* 8110 family. */
2233 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2234 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2235 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2236 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2237 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2238
2239 /* Catch-all */
2240 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
2241 };
2242 const struct rtl_mac_info *p = mac_info;
2243 u16 reg = RTL_R32(tp, TxConfig) >> 20;
2244
2245 while ((reg & p->mask) != p->val)
2246 p++;
2247 tp->mac_version = p->mac_version;
2248
2249 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2250 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2251 } else if (!tp->supports_gmii) {
2252 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2253 tp->mac_version = RTL_GIGA_MAC_VER_43;
2254 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2255 tp->mac_version = RTL_GIGA_MAC_VER_47;
2256 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2257 tp->mac_version = RTL_GIGA_MAC_VER_48;
2258 }
2259 }
2260
2261 struct phy_reg {
2262 u16 reg;
2263 u16 val;
2264 };
2265
2266 static void __rtl_writephy_batch(struct rtl8169_private *tp,
2267 const struct phy_reg *regs, int len)
2268 {
2269 while (len-- > 0) {
2270 rtl_writephy(tp, regs->reg, regs->val);
2271 regs++;
2272 }
2273 }
2274
2275 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a))
2276
2277 static void rtl_release_firmware(struct rtl8169_private *tp)
2278 {
2279 if (tp->rtl_fw) {
2280 rtl_fw_release_firmware(tp->rtl_fw);
2281 kfree(tp->rtl_fw);
2282 tp->rtl_fw = NULL;
2283 }
2284 }
2285
2286 static void rtl_apply_firmware(struct rtl8169_private *tp)
2287 {
2288 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2289 if (tp->rtl_fw)
2290 rtl_fw_write_firmware(tp, tp->rtl_fw);
2291 }
2292
2293 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2294 {
2295 if (rtl_readphy(tp, reg) != val)
2296 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2297 else
2298 rtl_apply_firmware(tp);
2299 }
2300
2301 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2302 {
2303 /* Adjust EEE LED frequency */
2304 if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2305 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2306
2307 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);
2308 }
2309
2310 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2311 {
2312 struct phy_device *phydev = tp->phydev;
2313
2314 phy_write(phydev, 0x1f, 0x0007);
2315 phy_write(phydev, 0x1e, 0x0020);
2316 phy_set_bits(phydev, 0x15, BIT(8));
2317
2318 phy_write(phydev, 0x1f, 0x0005);
2319 phy_write(phydev, 0x05, 0x8b85);
2320 phy_set_bits(phydev, 0x06, BIT(13));
2321
2322 phy_write(phydev, 0x1f, 0x0000);
2323 }
2324
2325 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2326 {
2327 phy_modify_paged(tp->phydev, 0x0a43, 0x11, 0, BIT(4));
2328 }
2329
2330 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2331 {
2332 static const struct phy_reg phy_reg_init[] = {
2333 { 0x1f, 0x0001 },
2334 { 0x06, 0x006e },
2335 { 0x08, 0x0708 },
2336 { 0x15, 0x4000 },
2337 { 0x18, 0x65c7 },
2338
2339 { 0x1f, 0x0001 },
2340 { 0x03, 0x00a1 },
2341 { 0x02, 0x0008 },
2342 { 0x01, 0x0120 },
2343 { 0x00, 0x1000 },
2344 { 0x04, 0x0800 },
2345 { 0x04, 0x0000 },
2346
2347 { 0x03, 0xff41 },
2348 { 0x02, 0xdf60 },
2349 { 0x01, 0x0140 },
2350 { 0x00, 0x0077 },
2351 { 0x04, 0x7800 },
2352 { 0x04, 0x7000 },
2353
2354 { 0x03, 0x802f },
2355 { 0x02, 0x4f02 },
2356 { 0x01, 0x0409 },
2357 { 0x00, 0xf0f9 },
2358 { 0x04, 0x9800 },
2359 { 0x04, 0x9000 },
2360
2361 { 0x03, 0xdf01 },
2362 { 0x02, 0xdf20 },
2363 { 0x01, 0xff95 },
2364 { 0x00, 0xba00 },
2365 { 0x04, 0xa800 },
2366 { 0x04, 0xa000 },
2367
2368 { 0x03, 0xff41 },
2369 { 0x02, 0xdf20 },
2370 { 0x01, 0x0140 },
2371 { 0x00, 0x00bb },
2372 { 0x04, 0xb800 },
2373 { 0x04, 0xb000 },
2374
2375 { 0x03, 0xdf41 },
2376 { 0x02, 0xdc60 },
2377 { 0x01, 0x6340 },
2378 { 0x00, 0x007d },
2379 { 0x04, 0xd800 },
2380 { 0x04, 0xd000 },
2381
2382 { 0x03, 0xdf01 },
2383 { 0x02, 0xdf20 },
2384 { 0x01, 0x100a },
2385 { 0x00, 0xa0ff },
2386 { 0x04, 0xf800 },
2387 { 0x04, 0xf000 },
2388
2389 { 0x1f, 0x0000 },
2390 { 0x0b, 0x0000 },
2391 { 0x00, 0x9200 }
2392 };
2393
2394 rtl_writephy_batch(tp, phy_reg_init);
2395 }
2396
2397 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2398 {
2399 static const struct phy_reg phy_reg_init[] = {
2400 { 0x1f, 0x0002 },
2401 { 0x01, 0x90d0 },
2402 { 0x1f, 0x0000 }
2403 };
2404
2405 rtl_writephy_batch(tp, phy_reg_init);
2406 }
2407
2408 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2409 {
2410 struct pci_dev *pdev = tp->pci_dev;
2411
2412 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2413 (pdev->subsystem_device != 0xe000))
2414 return;
2415
2416 rtl_writephy(tp, 0x1f, 0x0001);
2417 rtl_writephy(tp, 0x10, 0xf01b);
2418 rtl_writephy(tp, 0x1f, 0x0000);
2419 }
2420
2421 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2422 {
2423 static const struct phy_reg phy_reg_init[] = {
2424 { 0x1f, 0x0001 },
2425 { 0x04, 0x0000 },
2426 { 0x03, 0x00a1 },
2427 { 0x02, 0x0008 },
2428 { 0x01, 0x0120 },
2429 { 0x00, 0x1000 },
2430 { 0x04, 0x0800 },
2431 { 0x04, 0x9000 },
2432 { 0x03, 0x802f },
2433 { 0x02, 0x4f02 },
2434 { 0x01, 0x0409 },
2435 { 0x00, 0xf099 },
2436 { 0x04, 0x9800 },
2437 { 0x04, 0xa000 },
2438 { 0x03, 0xdf01 },
2439 { 0x02, 0xdf20 },
2440 { 0x01, 0xff95 },
2441 { 0x00, 0xba00 },
2442 { 0x04, 0xa800 },
2443 { 0x04, 0xf000 },
2444 { 0x03, 0xdf01 },
2445 { 0x02, 0xdf20 },
2446 { 0x01, 0x101a },
2447 { 0x00, 0xa0ff },
2448 { 0x04, 0xf800 },
2449 { 0x04, 0x0000 },
2450 { 0x1f, 0x0000 },
2451
2452 { 0x1f, 0x0001 },
2453 { 0x10, 0xf41b },
2454 { 0x14, 0xfb54 },
2455 { 0x18, 0xf5c7 },
2456 { 0x1f, 0x0000 },
2457
2458 { 0x1f, 0x0001 },
2459 { 0x17, 0x0cc0 },
2460 { 0x1f, 0x0000 }
2461 };
2462
2463 rtl_writephy_batch(tp, phy_reg_init);
2464
2465 rtl8169scd_hw_phy_config_quirk(tp);
2466 }
2467
2468 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2469 {
2470 static const struct phy_reg phy_reg_init[] = {
2471 { 0x1f, 0x0001 },
2472 { 0x04, 0x0000 },
2473 { 0x03, 0x00a1 },
2474 { 0x02, 0x0008 },
2475 { 0x01, 0x0120 },
2476 { 0x00, 0x1000 },
2477 { 0x04, 0x0800 },
2478 { 0x04, 0x9000 },
2479 { 0x03, 0x802f },
2480 { 0x02, 0x4f02 },
2481 { 0x01, 0x0409 },
2482 { 0x00, 0xf099 },
2483 { 0x04, 0x9800 },
2484 { 0x04, 0xa000 },
2485 { 0x03, 0xdf01 },
2486 { 0x02, 0xdf20 },
2487 { 0x01, 0xff95 },
2488 { 0x00, 0xba00 },
2489 { 0x04, 0xa800 },
2490 { 0x04, 0xf000 },
2491 { 0x03, 0xdf01 },
2492 { 0x02, 0xdf20 },
2493 { 0x01, 0x101a },
2494 { 0x00, 0xa0ff },
2495 { 0x04, 0xf800 },
2496 { 0x04, 0x0000 },
2497 { 0x1f, 0x0000 },
2498
2499 { 0x1f, 0x0001 },
2500 { 0x0b, 0x8480 },
2501 { 0x1f, 0x0000 },
2502
2503 { 0x1f, 0x0001 },
2504 { 0x18, 0x67c7 },
2505 { 0x04, 0x2000 },
2506 { 0x03, 0x002f },
2507 { 0x02, 0x4360 },
2508 { 0x01, 0x0109 },
2509 { 0x00, 0x3022 },
2510 { 0x04, 0x2800 },
2511 { 0x1f, 0x0000 },
2512
2513 { 0x1f, 0x0001 },
2514 { 0x17, 0x0cc0 },
2515 { 0x1f, 0x0000 }
2516 };
2517
2518 rtl_writephy_batch(tp, phy_reg_init);
2519 }
2520
2521 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2522 {
2523 static const struct phy_reg phy_reg_init[] = {
2524 { 0x10, 0xf41b },
2525 { 0x1f, 0x0000 }
2526 };
2527
2528 rtl_writephy(tp, 0x1f, 0x0001);
2529 rtl_patchphy(tp, 0x16, 1 << 0);
2530
2531 rtl_writephy_batch(tp, phy_reg_init);
2532 }
2533
2534 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2535 {
2536 static const struct phy_reg phy_reg_init[] = {
2537 { 0x1f, 0x0001 },
2538 { 0x10, 0xf41b },
2539 { 0x1f, 0x0000 }
2540 };
2541
2542 rtl_writephy_batch(tp, phy_reg_init);
2543 }
2544
2545 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2546 {
2547 static const struct phy_reg phy_reg_init[] = {
2548 { 0x1f, 0x0000 },
2549 { 0x1d, 0x0f00 },
2550 { 0x1f, 0x0002 },
2551 { 0x0c, 0x1ec8 },
2552 { 0x1f, 0x0000 }
2553 };
2554
2555 rtl_writephy_batch(tp, phy_reg_init);
2556 }
2557
2558 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2559 {
2560 static const struct phy_reg phy_reg_init[] = {
2561 { 0x1f, 0x0001 },
2562 { 0x1d, 0x3d98 },
2563 { 0x1f, 0x0000 }
2564 };
2565
2566 rtl_writephy(tp, 0x1f, 0x0000);
2567 rtl_patchphy(tp, 0x14, 1 << 5);
2568 rtl_patchphy(tp, 0x0d, 1 << 5);
2569
2570 rtl_writephy_batch(tp, phy_reg_init);
2571 }
2572
2573 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2574 {
2575 static const struct phy_reg phy_reg_init[] = {
2576 { 0x1f, 0x0001 },
2577 { 0x12, 0x2300 },
2578 { 0x1f, 0x0002 },
2579 { 0x00, 0x88d4 },
2580 { 0x01, 0x82b1 },
2581 { 0x03, 0x7002 },
2582 { 0x08, 0x9e30 },
2583 { 0x09, 0x01f0 },
2584 { 0x0a, 0x5500 },
2585 { 0x0c, 0x00c8 },
2586 { 0x1f, 0x0003 },
2587 { 0x12, 0xc096 },
2588 { 0x16, 0x000a },
2589 { 0x1f, 0x0000 },
2590 { 0x1f, 0x0000 },
2591 { 0x09, 0x2000 },
2592 { 0x09, 0x0000 }
2593 };
2594
2595 rtl_writephy_batch(tp, phy_reg_init);
2596
2597 rtl_patchphy(tp, 0x14, 1 << 5);
2598 rtl_patchphy(tp, 0x0d, 1 << 5);
2599 rtl_writephy(tp, 0x1f, 0x0000);
2600 }
2601
2602 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2603 {
2604 static const struct phy_reg phy_reg_init[] = {
2605 { 0x1f, 0x0001 },
2606 { 0x12, 0x2300 },
2607 { 0x03, 0x802f },
2608 { 0x02, 0x4f02 },
2609 { 0x01, 0x0409 },
2610 { 0x00, 0xf099 },
2611 { 0x04, 0x9800 },
2612 { 0x04, 0x9000 },
2613 { 0x1d, 0x3d98 },
2614 { 0x1f, 0x0002 },
2615 { 0x0c, 0x7eb8 },
2616 { 0x06, 0x0761 },
2617 { 0x1f, 0x0003 },
2618 { 0x16, 0x0f0a },
2619 { 0x1f, 0x0000 }
2620 };
2621
2622 rtl_writephy_batch(tp, phy_reg_init);
2623
2624 rtl_patchphy(tp, 0x16, 1 << 0);
2625 rtl_patchphy(tp, 0x14, 1 << 5);
2626 rtl_patchphy(tp, 0x0d, 1 << 5);
2627 rtl_writephy(tp, 0x1f, 0x0000);
2628 }
2629
2630 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2631 {
2632 static const struct phy_reg phy_reg_init[] = {
2633 { 0x1f, 0x0001 },
2634 { 0x12, 0x2300 },
2635 { 0x1d, 0x3d98 },
2636 { 0x1f, 0x0002 },
2637 { 0x0c, 0x7eb8 },
2638 { 0x06, 0x5461 },
2639 { 0x1f, 0x0003 },
2640 { 0x16, 0x0f0a },
2641 { 0x1f, 0x0000 }
2642 };
2643
2644 rtl_writephy_batch(tp, phy_reg_init);
2645
2646 rtl_patchphy(tp, 0x16, 1 << 0);
2647 rtl_patchphy(tp, 0x14, 1 << 5);
2648 rtl_patchphy(tp, 0x0d, 1 << 5);
2649 rtl_writephy(tp, 0x1f, 0x0000);
2650 }
2651
2652 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2653 {
2654 rtl8168c_3_hw_phy_config(tp);
2655 }
2656
2657 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
2658 /* Channel Estimation */
2659 { 0x1f, 0x0001 },
2660 { 0x06, 0x4064 },
2661 { 0x07, 0x2863 },
2662 { 0x08, 0x059c },
2663 { 0x09, 0x26b4 },
2664 { 0x0a, 0x6a19 },
2665 { 0x0b, 0xdcc8 },
2666 { 0x10, 0xf06d },
2667 { 0x14, 0x7f68 },
2668 { 0x18, 0x7fd9 },
2669 { 0x1c, 0xf0ff },
2670 { 0x1d, 0x3d9c },
2671 { 0x1f, 0x0003 },
2672 { 0x12, 0xf49f },
2673 { 0x13, 0x070b },
2674 { 0x1a, 0x05ad },
2675 { 0x14, 0x94c0 },
2676
2677 /*
2678 * Tx Error Issue
2679 * Enhance line driver power
2680 */
2681 { 0x1f, 0x0002 },
2682 { 0x06, 0x5561 },
2683 { 0x1f, 0x0005 },
2684 { 0x05, 0x8332 },
2685 { 0x06, 0x5561 },
2686
2687 /*
2688 * Can not link to 1Gbps with bad cable
2689 * Decrease SNR threshold form 21.07dB to 19.04dB
2690 */
2691 { 0x1f, 0x0001 },
2692 { 0x17, 0x0cc0 },
2693
2694 { 0x1f, 0x0000 },
2695 { 0x0d, 0xf880 }
2696 };
2697
2698 static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = {
2699 { 0x1f, 0x0002 },
2700 { 0x05, 0x669a },
2701 { 0x1f, 0x0005 },
2702 { 0x05, 0x8330 },
2703 { 0x06, 0x669a },
2704 { 0x1f, 0x0002 }
2705 };
2706
2707 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2708 {
2709 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2710
2711 /*
2712 * Rx Error Issue
2713 * Fine Tune Switching regulator parameter
2714 */
2715 rtl_writephy(tp, 0x1f, 0x0002);
2716 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2717 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2718
2719 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2720 int val;
2721
2722 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2723
2724 val = rtl_readphy(tp, 0x0d);
2725
2726 if ((val & 0x00ff) != 0x006c) {
2727 static const u32 set[] = {
2728 0x0065, 0x0066, 0x0067, 0x0068,
2729 0x0069, 0x006a, 0x006b, 0x006c
2730 };
2731 int i;
2732
2733 rtl_writephy(tp, 0x1f, 0x0002);
2734
2735 val &= 0xff00;
2736 for (i = 0; i < ARRAY_SIZE(set); i++)
2737 rtl_writephy(tp, 0x0d, val | set[i]);
2738 }
2739 } else {
2740 static const struct phy_reg phy_reg_init[] = {
2741 { 0x1f, 0x0002 },
2742 { 0x05, 0x6662 },
2743 { 0x1f, 0x0005 },
2744 { 0x05, 0x8330 },
2745 { 0x06, 0x6662 }
2746 };
2747
2748 rtl_writephy_batch(tp, phy_reg_init);
2749 }
2750
2751 /* RSET couple improve */
2752 rtl_writephy(tp, 0x1f, 0x0002);
2753 rtl_patchphy(tp, 0x0d, 0x0300);
2754 rtl_patchphy(tp, 0x0f, 0x0010);
2755
2756 /* Fine tune PLL performance */
2757 rtl_writephy(tp, 0x1f, 0x0002);
2758 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2759 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2760
2761 rtl_writephy(tp, 0x1f, 0x0005);
2762 rtl_writephy(tp, 0x05, 0x001b);
2763
2764 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2765
2766 rtl_writephy(tp, 0x1f, 0x0000);
2767 }
2768
2769 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2770 {
2771 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2772
2773 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2774 int val;
2775
2776 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2777
2778 val = rtl_readphy(tp, 0x0d);
2779 if ((val & 0x00ff) != 0x006c) {
2780 static const u32 set[] = {
2781 0x0065, 0x0066, 0x0067, 0x0068,
2782 0x0069, 0x006a, 0x006b, 0x006c
2783 };
2784 int i;
2785
2786 rtl_writephy(tp, 0x1f, 0x0002);
2787
2788 val &= 0xff00;
2789 for (i = 0; i < ARRAY_SIZE(set); i++)
2790 rtl_writephy(tp, 0x0d, val | set[i]);
2791 }
2792 } else {
2793 static const struct phy_reg phy_reg_init[] = {
2794 { 0x1f, 0x0002 },
2795 { 0x05, 0x2642 },
2796 { 0x1f, 0x0005 },
2797 { 0x05, 0x8330 },
2798 { 0x06, 0x2642 }
2799 };
2800
2801 rtl_writephy_batch(tp, phy_reg_init);
2802 }
2803
2804 /* Fine tune PLL performance */
2805 rtl_writephy(tp, 0x1f, 0x0002);
2806 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2807 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2808
2809 /* Switching regulator Slew rate */
2810 rtl_writephy(tp, 0x1f, 0x0002);
2811 rtl_patchphy(tp, 0x0f, 0x0017);
2812
2813 rtl_writephy(tp, 0x1f, 0x0005);
2814 rtl_writephy(tp, 0x05, 0x001b);
2815
2816 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2817
2818 rtl_writephy(tp, 0x1f, 0x0000);
2819 }
2820
2821 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2822 {
2823 static const struct phy_reg phy_reg_init[] = {
2824 { 0x1f, 0x0002 },
2825 { 0x10, 0x0008 },
2826 { 0x0d, 0x006c },
2827
2828 { 0x1f, 0x0000 },
2829 { 0x0d, 0xf880 },
2830
2831 { 0x1f, 0x0001 },
2832 { 0x17, 0x0cc0 },
2833
2834 { 0x1f, 0x0001 },
2835 { 0x0b, 0xa4d8 },
2836 { 0x09, 0x281c },
2837 { 0x07, 0x2883 },
2838 { 0x0a, 0x6b35 },
2839 { 0x1d, 0x3da4 },
2840 { 0x1c, 0xeffd },
2841 { 0x14, 0x7f52 },
2842 { 0x18, 0x7fc6 },
2843 { 0x08, 0x0601 },
2844 { 0x06, 0x4063 },
2845 { 0x10, 0xf074 },
2846 { 0x1f, 0x0003 },
2847 { 0x13, 0x0789 },
2848 { 0x12, 0xf4bd },
2849 { 0x1a, 0x04fd },
2850 { 0x14, 0x84b0 },
2851 { 0x1f, 0x0000 },
2852 { 0x00, 0x9200 },
2853
2854 { 0x1f, 0x0005 },
2855 { 0x01, 0x0340 },
2856 { 0x1f, 0x0001 },
2857 { 0x04, 0x4000 },
2858 { 0x03, 0x1d21 },
2859 { 0x02, 0x0c32 },
2860 { 0x01, 0x0200 },
2861 { 0x00, 0x5554 },
2862 { 0x04, 0x4800 },
2863 { 0x04, 0x4000 },
2864 { 0x04, 0xf000 },
2865 { 0x03, 0xdf01 },
2866 { 0x02, 0xdf20 },
2867 { 0x01, 0x101a },
2868 { 0x00, 0xa0ff },
2869 { 0x04, 0xf800 },
2870 { 0x04, 0xf000 },
2871 { 0x1f, 0x0000 },
2872
2873 { 0x1f, 0x0007 },
2874 { 0x1e, 0x0023 },
2875 { 0x16, 0x0000 },
2876 { 0x1f, 0x0000 }
2877 };
2878
2879 rtl_writephy_batch(tp, phy_reg_init);
2880 }
2881
2882 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2883 {
2884 static const struct phy_reg phy_reg_init[] = {
2885 { 0x1f, 0x0001 },
2886 { 0x17, 0x0cc0 },
2887
2888 { 0x1f, 0x0007 },
2889 { 0x1e, 0x002d },
2890 { 0x18, 0x0040 },
2891 { 0x1f, 0x0000 }
2892 };
2893
2894 rtl_writephy_batch(tp, phy_reg_init);
2895 rtl_patchphy(tp, 0x0d, 1 << 5);
2896 }
2897
2898 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2899 {
2900 static const struct phy_reg phy_reg_init[] = {
2901 /* Enable Delay cap */
2902 { 0x1f, 0x0005 },
2903 { 0x05, 0x8b80 },
2904 { 0x06, 0xc896 },
2905 { 0x1f, 0x0000 },
2906
2907 /* Channel estimation fine tune */
2908 { 0x1f, 0x0001 },
2909 { 0x0b, 0x6c20 },
2910 { 0x07, 0x2872 },
2911 { 0x1c, 0xefff },
2912 { 0x1f, 0x0003 },
2913 { 0x14, 0x6420 },
2914 { 0x1f, 0x0000 },
2915
2916 /* Update PFM & 10M TX idle timer */
2917 { 0x1f, 0x0007 },
2918 { 0x1e, 0x002f },
2919 { 0x15, 0x1919 },
2920 { 0x1f, 0x0000 },
2921
2922 { 0x1f, 0x0007 },
2923 { 0x1e, 0x00ac },
2924 { 0x18, 0x0006 },
2925 { 0x1f, 0x0000 }
2926 };
2927
2928 rtl_apply_firmware(tp);
2929
2930 rtl_writephy_batch(tp, phy_reg_init);
2931
2932 /* DCO enable for 10M IDLE Power */
2933 rtl_writephy(tp, 0x1f, 0x0007);
2934 rtl_writephy(tp, 0x1e, 0x0023);
2935 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
2936 rtl_writephy(tp, 0x1f, 0x0000);
2937
2938 /* For impedance matching */
2939 rtl_writephy(tp, 0x1f, 0x0002);
2940 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
2941 rtl_writephy(tp, 0x1f, 0x0000);
2942
2943 /* PHY auto speed down */
2944 rtl_writephy(tp, 0x1f, 0x0007);
2945 rtl_writephy(tp, 0x1e, 0x002d);
2946 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
2947 rtl_writephy(tp, 0x1f, 0x0000);
2948 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
2949
2950 rtl_writephy(tp, 0x1f, 0x0005);
2951 rtl_writephy(tp, 0x05, 0x8b86);
2952 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
2953 rtl_writephy(tp, 0x1f, 0x0000);
2954
2955 rtl_writephy(tp, 0x1f, 0x0005);
2956 rtl_writephy(tp, 0x05, 0x8b85);
2957 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
2958 rtl_writephy(tp, 0x1f, 0x0007);
2959 rtl_writephy(tp, 0x1e, 0x0020);
2960 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
2961 rtl_writephy(tp, 0x1f, 0x0006);
2962 rtl_writephy(tp, 0x00, 0x5a00);
2963 rtl_writephy(tp, 0x1f, 0x0000);
2964 rtl_writephy(tp, 0x0d, 0x0007);
2965 rtl_writephy(tp, 0x0e, 0x003c);
2966 rtl_writephy(tp, 0x0d, 0x4007);
2967 rtl_writephy(tp, 0x0e, 0x0000);
2968 rtl_writephy(tp, 0x0d, 0x0000);
2969 }
2970
2971 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
2972 {
2973 const u16 w[] = {
2974 addr[0] | (addr[1] << 8),
2975 addr[2] | (addr[3] << 8),
2976 addr[4] | (addr[5] << 8)
2977 };
2978
2979 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
2980 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
2981 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
2982 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
2983 }
2984
2985 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2986 {
2987 static const struct phy_reg phy_reg_init[] = {
2988 /* Enable Delay cap */
2989 { 0x1f, 0x0004 },
2990 { 0x1f, 0x0007 },
2991 { 0x1e, 0x00ac },
2992 { 0x18, 0x0006 },
2993 { 0x1f, 0x0002 },
2994 { 0x1f, 0x0000 },
2995 { 0x1f, 0x0000 },
2996
2997 /* Channel estimation fine tune */
2998 { 0x1f, 0x0003 },
2999 { 0x09, 0xa20f },
3000 { 0x1f, 0x0000 },
3001 { 0x1f, 0x0000 },
3002
3003 /* Green Setting */
3004 { 0x1f, 0x0005 },
3005 { 0x05, 0x8b5b },
3006 { 0x06, 0x9222 },
3007 { 0x05, 0x8b6d },
3008 { 0x06, 0x8000 },
3009 { 0x05, 0x8b76 },
3010 { 0x06, 0x8000 },
3011 { 0x1f, 0x0000 }
3012 };
3013
3014 rtl_apply_firmware(tp);
3015
3016 rtl_writephy_batch(tp, phy_reg_init);
3017
3018 /* For 4-corner performance improve */
3019 rtl_writephy(tp, 0x1f, 0x0005);
3020 rtl_writephy(tp, 0x05, 0x8b80);
3021 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3022 rtl_writephy(tp, 0x1f, 0x0000);
3023
3024 /* PHY auto speed down */
3025 rtl_writephy(tp, 0x1f, 0x0004);
3026 rtl_writephy(tp, 0x1f, 0x0007);
3027 rtl_writephy(tp, 0x1e, 0x002d);
3028 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3029 rtl_writephy(tp, 0x1f, 0x0002);
3030 rtl_writephy(tp, 0x1f, 0x0000);
3031 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3032
3033 /* improve 10M EEE waveform */
3034 rtl_writephy(tp, 0x1f, 0x0005);
3035 rtl_writephy(tp, 0x05, 0x8b86);
3036 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3037 rtl_writephy(tp, 0x1f, 0x0000);
3038
3039 /* Improve 2-pair detection performance */
3040 rtl_writephy(tp, 0x1f, 0x0005);
3041 rtl_writephy(tp, 0x05, 0x8b85);
3042 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3043 rtl_writephy(tp, 0x1f, 0x0000);
3044
3045 rtl8168f_config_eee_phy(tp);
3046 rtl_enable_eee(tp);
3047
3048 /* Green feature */
3049 rtl_writephy(tp, 0x1f, 0x0003);
3050 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3051 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3052 rtl_writephy(tp, 0x1f, 0x0000);
3053 rtl_writephy(tp, 0x1f, 0x0005);
3054 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3055 rtl_writephy(tp, 0x1f, 0x0000);
3056
3057 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3058 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3059 }
3060
3061 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3062 {
3063 /* For 4-corner performance improve */
3064 rtl_writephy(tp, 0x1f, 0x0005);
3065 rtl_writephy(tp, 0x05, 0x8b80);
3066 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3067 rtl_writephy(tp, 0x1f, 0x0000);
3068
3069 /* PHY auto speed down */
3070 rtl_writephy(tp, 0x1f, 0x0007);
3071 rtl_writephy(tp, 0x1e, 0x002d);
3072 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3073 rtl_writephy(tp, 0x1f, 0x0000);
3074 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3075
3076 /* Improve 10M EEE waveform */
3077 rtl_writephy(tp, 0x1f, 0x0005);
3078 rtl_writephy(tp, 0x05, 0x8b86);
3079 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3080 rtl_writephy(tp, 0x1f, 0x0000);
3081
3082 rtl8168f_config_eee_phy(tp);
3083 rtl_enable_eee(tp);
3084 }
3085
3086 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3087 {
3088 static const struct phy_reg phy_reg_init[] = {
3089 /* Channel estimation fine tune */
3090 { 0x1f, 0x0003 },
3091 { 0x09, 0xa20f },
3092 { 0x1f, 0x0000 },
3093
3094 /* Modify green table for giga & fnet */
3095 { 0x1f, 0x0005 },
3096 { 0x05, 0x8b55 },
3097 { 0x06, 0x0000 },
3098 { 0x05, 0x8b5e },
3099 { 0x06, 0x0000 },
3100 { 0x05, 0x8b67 },
3101 { 0x06, 0x0000 },
3102 { 0x05, 0x8b70 },
3103 { 0x06, 0x0000 },
3104 { 0x1f, 0x0000 },
3105 { 0x1f, 0x0007 },
3106 { 0x1e, 0x0078 },
3107 { 0x17, 0x0000 },
3108 { 0x19, 0x00fb },
3109 { 0x1f, 0x0000 },
3110
3111 /* Modify green table for 10M */
3112 { 0x1f, 0x0005 },
3113 { 0x05, 0x8b79 },
3114 { 0x06, 0xaa00 },
3115 { 0x1f, 0x0000 },
3116
3117 /* Disable hiimpedance detection (RTCT) */
3118 { 0x1f, 0x0003 },
3119 { 0x01, 0x328a },
3120 { 0x1f, 0x0000 }
3121 };
3122
3123 rtl_apply_firmware(tp);
3124
3125 rtl_writephy_batch(tp, phy_reg_init);
3126
3127 rtl8168f_hw_phy_config(tp);
3128
3129 /* Improve 2-pair detection performance */
3130 rtl_writephy(tp, 0x1f, 0x0005);
3131 rtl_writephy(tp, 0x05, 0x8b85);
3132 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3133 rtl_writephy(tp, 0x1f, 0x0000);
3134 }
3135
3136 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3137 {
3138 rtl_apply_firmware(tp);
3139
3140 rtl8168f_hw_phy_config(tp);
3141 }
3142
3143 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3144 {
3145 static const struct phy_reg phy_reg_init[] = {
3146 /* Channel estimation fine tune */
3147 { 0x1f, 0x0003 },
3148 { 0x09, 0xa20f },
3149 { 0x1f, 0x0000 },
3150
3151 /* Modify green table for giga & fnet */
3152 { 0x1f, 0x0005 },
3153 { 0x05, 0x8b55 },
3154 { 0x06, 0x0000 },
3155 { 0x05, 0x8b5e },
3156 { 0x06, 0x0000 },
3157 { 0x05, 0x8b67 },
3158 { 0x06, 0x0000 },
3159 { 0x05, 0x8b70 },
3160 { 0x06, 0x0000 },
3161 { 0x1f, 0x0000 },
3162 { 0x1f, 0x0007 },
3163 { 0x1e, 0x0078 },
3164 { 0x17, 0x0000 },
3165 { 0x19, 0x00aa },
3166 { 0x1f, 0x0000 },
3167
3168 /* Modify green table for 10M */
3169 { 0x1f, 0x0005 },
3170 { 0x05, 0x8b79 },
3171 { 0x06, 0xaa00 },
3172 { 0x1f, 0x0000 },
3173
3174 /* Disable hiimpedance detection (RTCT) */
3175 { 0x1f, 0x0003 },
3176 { 0x01, 0x328a },
3177 { 0x1f, 0x0000 }
3178 };
3179
3180
3181 rtl_apply_firmware(tp);
3182
3183 rtl8168f_hw_phy_config(tp);
3184
3185 /* Improve 2-pair detection performance */
3186 rtl_writephy(tp, 0x1f, 0x0005);
3187 rtl_writephy(tp, 0x05, 0x8b85);
3188 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3189 rtl_writephy(tp, 0x1f, 0x0000);
3190
3191 rtl_writephy_batch(tp, phy_reg_init);
3192
3193 /* Modify green table for giga */
3194 rtl_writephy(tp, 0x1f, 0x0005);
3195 rtl_writephy(tp, 0x05, 0x8b54);
3196 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3197 rtl_writephy(tp, 0x05, 0x8b5d);
3198 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3199 rtl_writephy(tp, 0x05, 0x8a7c);
3200 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3201 rtl_writephy(tp, 0x05, 0x8a7f);
3202 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3203 rtl_writephy(tp, 0x05, 0x8a82);
3204 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3205 rtl_writephy(tp, 0x05, 0x8a85);
3206 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3207 rtl_writephy(tp, 0x05, 0x8a88);
3208 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3209 rtl_writephy(tp, 0x1f, 0x0000);
3210
3211 /* uc same-seed solution */
3212 rtl_writephy(tp, 0x1f, 0x0005);
3213 rtl_writephy(tp, 0x05, 0x8b85);
3214 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3215 rtl_writephy(tp, 0x1f, 0x0000);
3216
3217 /* Green feature */
3218 rtl_writephy(tp, 0x1f, 0x0003);
3219 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3220 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3221 rtl_writephy(tp, 0x1f, 0x0000);
3222 }
3223
3224 static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3225 {
3226 phy_modify_paged(tp->phydev, 0x0a43, 0x10, BIT(2), 0);
3227 }
3228
3229 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3230 {
3231 struct phy_device *phydev = tp->phydev;
3232
3233 phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0);
3234 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6));
3235 phy_write(phydev, 0x1f, 0x0a43);
3236 phy_write(phydev, 0x13, 0x8084);
3237 phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13));
3238 phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0));
3239
3240 phy_write(phydev, 0x1f, 0x0000);
3241 }
3242
3243 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3244 {
3245 int ret;
3246
3247 rtl_apply_firmware(tp);
3248
3249 ret = phy_read_paged(tp->phydev, 0x0a46, 0x10);
3250 if (ret & BIT(8))
3251 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, BIT(15), 0);
3252 else
3253 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, 0, BIT(15));
3254
3255 ret = phy_read_paged(tp->phydev, 0x0a46, 0x13);
3256 if (ret & BIT(8))
3257 phy_modify_paged(tp->phydev, 0x0c41, 0x12, 0, BIT(1));
3258 else
3259 phy_modify_paged(tp->phydev, 0x0c41, 0x12, BIT(1), 0);
3260
3261 /* Enable PHY auto speed down */
3262 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3263
3264 rtl8168g_phy_adjust_10m_aldps(tp);
3265
3266 /* EEE auto-fallback function */
3267 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3268
3269 /* Enable UC LPF tune function */
3270 rtl_writephy(tp, 0x1f, 0x0a43);
3271 rtl_writephy(tp, 0x13, 0x8012);
3272 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3273
3274 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3275
3276 /* Improve SWR Efficiency */
3277 rtl_writephy(tp, 0x1f, 0x0bcd);
3278 rtl_writephy(tp, 0x14, 0x5065);
3279 rtl_writephy(tp, 0x14, 0xd065);
3280 rtl_writephy(tp, 0x1f, 0x0bc8);
3281 rtl_writephy(tp, 0x11, 0x5655);
3282 rtl_writephy(tp, 0x1f, 0x0bcd);
3283 rtl_writephy(tp, 0x14, 0x1065);
3284 rtl_writephy(tp, 0x14, 0x9065);
3285 rtl_writephy(tp, 0x14, 0x1065);
3286 rtl_writephy(tp, 0x1f, 0x0000);
3287
3288 rtl8168g_disable_aldps(tp);
3289 rtl8168g_config_eee_phy(tp);
3290 rtl_enable_eee(tp);
3291 }
3292
3293 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3294 {
3295 rtl_apply_firmware(tp);
3296 rtl8168g_config_eee_phy(tp);
3297 rtl_enable_eee(tp);
3298 }
3299
3300 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3301 {
3302 u16 dout_tapbin;
3303 u32 data;
3304
3305 rtl_apply_firmware(tp);
3306
3307 /* CHN EST parameters adjust - giga master */
3308 rtl_writephy(tp, 0x1f, 0x0a43);
3309 rtl_writephy(tp, 0x13, 0x809b);
3310 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3311 rtl_writephy(tp, 0x13, 0x80a2);
3312 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3313 rtl_writephy(tp, 0x13, 0x80a4);
3314 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3315 rtl_writephy(tp, 0x13, 0x809c);
3316 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3317 rtl_writephy(tp, 0x1f, 0x0000);
3318
3319 /* CHN EST parameters adjust - giga slave */
3320 rtl_writephy(tp, 0x1f, 0x0a43);
3321 rtl_writephy(tp, 0x13, 0x80ad);
3322 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3323 rtl_writephy(tp, 0x13, 0x80b4);
3324 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3325 rtl_writephy(tp, 0x13, 0x80ac);
3326 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3327 rtl_writephy(tp, 0x1f, 0x0000);
3328
3329 /* CHN EST parameters adjust - fnet */
3330 rtl_writephy(tp, 0x1f, 0x0a43);
3331 rtl_writephy(tp, 0x13, 0x808e);
3332 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3333 rtl_writephy(tp, 0x13, 0x8090);
3334 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3335 rtl_writephy(tp, 0x13, 0x8092);
3336 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3337 rtl_writephy(tp, 0x1f, 0x0000);
3338
3339 /* enable R-tune & PGA-retune function */
3340 dout_tapbin = 0;
3341 rtl_writephy(tp, 0x1f, 0x0a46);
3342 data = rtl_readphy(tp, 0x13);
3343 data &= 3;
3344 data <<= 2;
3345 dout_tapbin |= data;
3346 data = rtl_readphy(tp, 0x12);
3347 data &= 0xc000;
3348 data >>= 14;
3349 dout_tapbin |= data;
3350 dout_tapbin = ~(dout_tapbin^0x08);
3351 dout_tapbin <<= 12;
3352 dout_tapbin &= 0xf000;
3353 rtl_writephy(tp, 0x1f, 0x0a43);
3354 rtl_writephy(tp, 0x13, 0x827a);
3355 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3356 rtl_writephy(tp, 0x13, 0x827b);
3357 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3358 rtl_writephy(tp, 0x13, 0x827c);
3359 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3360 rtl_writephy(tp, 0x13, 0x827d);
3361 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3362
3363 rtl_writephy(tp, 0x1f, 0x0a43);
3364 rtl_writephy(tp, 0x13, 0x0811);
3365 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3366 rtl_writephy(tp, 0x1f, 0x0a42);
3367 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3368 rtl_writephy(tp, 0x1f, 0x0000);
3369
3370 /* enable GPHY 10M */
3371 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3372
3373 /* SAR ADC performance */
3374 phy_modify_paged(tp->phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14));
3375
3376 rtl_writephy(tp, 0x1f, 0x0a43);
3377 rtl_writephy(tp, 0x13, 0x803f);
3378 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3379 rtl_writephy(tp, 0x13, 0x8047);
3380 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3381 rtl_writephy(tp, 0x13, 0x804f);
3382 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3383 rtl_writephy(tp, 0x13, 0x8057);
3384 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3385 rtl_writephy(tp, 0x13, 0x805f);
3386 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3387 rtl_writephy(tp, 0x13, 0x8067);
3388 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3389 rtl_writephy(tp, 0x13, 0x806f);
3390 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3391 rtl_writephy(tp, 0x1f, 0x0000);
3392
3393 /* disable phy pfm mode */
3394 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3395
3396 rtl8168g_disable_aldps(tp);
3397 rtl8168g_config_eee_phy(tp);
3398 rtl_enable_eee(tp);
3399 }
3400
3401 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3402 {
3403 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3404 u16 rlen;
3405 u32 data;
3406
3407 rtl_apply_firmware(tp);
3408
3409 /* CHIN EST parameter update */
3410 rtl_writephy(tp, 0x1f, 0x0a43);
3411 rtl_writephy(tp, 0x13, 0x808a);
3412 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3413 rtl_writephy(tp, 0x1f, 0x0000);
3414
3415 /* enable R-tune & PGA-retune function */
3416 rtl_writephy(tp, 0x1f, 0x0a43);
3417 rtl_writephy(tp, 0x13, 0x0811);
3418 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3419 rtl_writephy(tp, 0x1f, 0x0a42);
3420 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3421 rtl_writephy(tp, 0x1f, 0x0000);
3422
3423 /* enable GPHY 10M */
3424 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3425
3426 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3427 data = r8168_mac_ocp_read(tp, 0xdd02);
3428 ioffset_p3 = ((data & 0x80)>>7);
3429 ioffset_p3 <<= 3;
3430
3431 data = r8168_mac_ocp_read(tp, 0xdd00);
3432 ioffset_p3 |= ((data & (0xe000))>>13);
3433 ioffset_p2 = ((data & (0x1e00))>>9);
3434 ioffset_p1 = ((data & (0x01e0))>>5);
3435 ioffset_p0 = ((data & 0x0010)>>4);
3436 ioffset_p0 <<= 3;
3437 ioffset_p0 |= (data & (0x07));
3438 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3439
3440 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3441 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3442 rtl_writephy(tp, 0x1f, 0x0bcf);
3443 rtl_writephy(tp, 0x16, data);
3444 rtl_writephy(tp, 0x1f, 0x0000);
3445 }
3446
3447 /* Modify rlen (TX LPF corner frequency) level */
3448 rtl_writephy(tp, 0x1f, 0x0bcd);
3449 data = rtl_readphy(tp, 0x16);
3450 data &= 0x000f;
3451 rlen = 0;
3452 if (data > 3)
3453 rlen = data - 3;
3454 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3455 rtl_writephy(tp, 0x17, data);
3456 rtl_writephy(tp, 0x1f, 0x0bcd);
3457 rtl_writephy(tp, 0x1f, 0x0000);
3458
3459 /* disable phy pfm mode */
3460 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3461
3462 rtl8168g_disable_aldps(tp);
3463 rtl8168g_config_eee_phy(tp);
3464 rtl_enable_eee(tp);
3465 }
3466
3467 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3468 {
3469 /* Enable PHY auto speed down */
3470 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3471
3472 rtl8168g_phy_adjust_10m_aldps(tp);
3473
3474 /* Enable EEE auto-fallback function */
3475 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3476
3477 /* Enable UC LPF tune function */
3478 rtl_writephy(tp, 0x1f, 0x0a43);
3479 rtl_writephy(tp, 0x13, 0x8012);
3480 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3481 rtl_writephy(tp, 0x1f, 0x0000);
3482
3483 /* set rg_sel_sdm_rate */
3484 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3485
3486 rtl8168g_disable_aldps(tp);
3487 rtl8168g_config_eee_phy(tp);
3488 rtl_enable_eee(tp);
3489 }
3490
3491 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3492 {
3493 rtl8168g_phy_adjust_10m_aldps(tp);
3494
3495 /* Enable UC LPF tune function */
3496 rtl_writephy(tp, 0x1f, 0x0a43);
3497 rtl_writephy(tp, 0x13, 0x8012);
3498 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3499 rtl_writephy(tp, 0x1f, 0x0000);
3500
3501 /* Set rg_sel_sdm_rate */
3502 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3503
3504 /* Channel estimation parameters */
3505 rtl_writephy(tp, 0x1f, 0x0a43);
3506 rtl_writephy(tp, 0x13, 0x80f3);
3507 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3508 rtl_writephy(tp, 0x13, 0x80f0);
3509 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3510 rtl_writephy(tp, 0x13, 0x80ef);
3511 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3512 rtl_writephy(tp, 0x13, 0x80f6);
3513 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3514 rtl_writephy(tp, 0x13, 0x80ec);
3515 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3516 rtl_writephy(tp, 0x13, 0x80ed);
3517 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3518 rtl_writephy(tp, 0x13, 0x80f2);
3519 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3520 rtl_writephy(tp, 0x13, 0x80f4);
3521 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3522 rtl_writephy(tp, 0x1f, 0x0a43);
3523 rtl_writephy(tp, 0x13, 0x8110);
3524 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3525 rtl_writephy(tp, 0x13, 0x810f);
3526 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3527 rtl_writephy(tp, 0x13, 0x8111);
3528 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3529 rtl_writephy(tp, 0x13, 0x8113);
3530 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3531 rtl_writephy(tp, 0x13, 0x8115);
3532 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3533 rtl_writephy(tp, 0x13, 0x810e);
3534 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3535 rtl_writephy(tp, 0x13, 0x810c);
3536 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3537 rtl_writephy(tp, 0x13, 0x810b);
3538 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3539 rtl_writephy(tp, 0x1f, 0x0a43);
3540 rtl_writephy(tp, 0x13, 0x80d1);
3541 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3542 rtl_writephy(tp, 0x13, 0x80cd);
3543 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3544 rtl_writephy(tp, 0x13, 0x80d3);
3545 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3546 rtl_writephy(tp, 0x13, 0x80d5);
3547 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3548 rtl_writephy(tp, 0x13, 0x80d7);
3549 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3550
3551 /* Force PWM-mode */
3552 rtl_writephy(tp, 0x1f, 0x0bcd);
3553 rtl_writephy(tp, 0x14, 0x5065);
3554 rtl_writephy(tp, 0x14, 0xd065);
3555 rtl_writephy(tp, 0x1f, 0x0bc8);
3556 rtl_writephy(tp, 0x12, 0x00ed);
3557 rtl_writephy(tp, 0x1f, 0x0bcd);
3558 rtl_writephy(tp, 0x14, 0x1065);
3559 rtl_writephy(tp, 0x14, 0x9065);
3560 rtl_writephy(tp, 0x14, 0x1065);
3561 rtl_writephy(tp, 0x1f, 0x0000);
3562
3563 rtl8168g_disable_aldps(tp);
3564 rtl8168g_config_eee_phy(tp);
3565 rtl_enable_eee(tp);
3566 }
3567
3568 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3569 {
3570 static const struct phy_reg phy_reg_init[] = {
3571 { 0x1f, 0x0003 },
3572 { 0x08, 0x441d },
3573 { 0x01, 0x9100 },
3574 { 0x1f, 0x0000 }
3575 };
3576
3577 rtl_writephy(tp, 0x1f, 0x0000);
3578 rtl_patchphy(tp, 0x11, 1 << 12);
3579 rtl_patchphy(tp, 0x19, 1 << 13);
3580 rtl_patchphy(tp, 0x10, 1 << 15);
3581
3582 rtl_writephy_batch(tp, phy_reg_init);
3583 }
3584
3585 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3586 {
3587 static const struct phy_reg phy_reg_init[] = {
3588 { 0x1f, 0x0005 },
3589 { 0x1a, 0x0000 },
3590 { 0x1f, 0x0000 },
3591
3592 { 0x1f, 0x0004 },
3593 { 0x1c, 0x0000 },
3594 { 0x1f, 0x0000 },
3595
3596 { 0x1f, 0x0001 },
3597 { 0x15, 0x7701 },
3598 { 0x1f, 0x0000 }
3599 };
3600
3601 /* Disable ALDPS before ram code */
3602 rtl_writephy(tp, 0x1f, 0x0000);
3603 rtl_writephy(tp, 0x18, 0x0310);
3604 msleep(100);
3605
3606 rtl_apply_firmware(tp);
3607
3608 rtl_writephy_batch(tp, phy_reg_init);
3609 }
3610
3611 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3612 {
3613 /* Disable ALDPS before setting firmware */
3614 rtl_writephy(tp, 0x1f, 0x0000);
3615 rtl_writephy(tp, 0x18, 0x0310);
3616 msleep(20);
3617
3618 rtl_apply_firmware(tp);
3619
3620 /* EEE setting */
3621 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3622 rtl_writephy(tp, 0x1f, 0x0004);
3623 rtl_writephy(tp, 0x10, 0x401f);
3624 rtl_writephy(tp, 0x19, 0x7030);
3625 rtl_writephy(tp, 0x1f, 0x0000);
3626 }
3627
3628 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3629 {
3630 static const struct phy_reg phy_reg_init[] = {
3631 { 0x1f, 0x0004 },
3632 { 0x10, 0xc07f },
3633 { 0x19, 0x7030 },
3634 { 0x1f, 0x0000 }
3635 };
3636
3637 /* Disable ALDPS before ram code */
3638 rtl_writephy(tp, 0x1f, 0x0000);
3639 rtl_writephy(tp, 0x18, 0x0310);
3640 msleep(100);
3641
3642 rtl_apply_firmware(tp);
3643
3644 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3645 rtl_writephy_batch(tp, phy_reg_init);
3646
3647 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3648 }
3649
3650 static void rtl_hw_phy_config(struct net_device *dev)
3651 {
3652 static const rtl_generic_fct phy_configs[] = {
3653 /* PCI devices. */
3654 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
3655 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
3656 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
3657 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
3658 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
3659 /* PCI-E devices. */
3660 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
3661 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
3662 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
3663 [RTL_GIGA_MAC_VER_10] = NULL,
3664 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
3665 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config,
3666 [RTL_GIGA_MAC_VER_13] = NULL,
3667 [RTL_GIGA_MAC_VER_14] = NULL,
3668 [RTL_GIGA_MAC_VER_15] = NULL,
3669 [RTL_GIGA_MAC_VER_16] = NULL,
3670 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
3671 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
3672 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
3673 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
3674 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
3675 [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config,
3676 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
3677 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
3678 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
3679 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
3680 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config,
3681 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
3682 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
3683 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
3684 [RTL_GIGA_MAC_VER_31] = NULL,
3685 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
3686 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
3687 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
3688 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
3689 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
3690 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
3691 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
3692 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
3693 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
3694 [RTL_GIGA_MAC_VER_41] = NULL,
3695 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
3696 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
3697 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
3698 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config,
3699 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
3700 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config,
3701 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
3702 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config,
3703 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config,
3704 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
3705 };
3706 struct rtl8169_private *tp = netdev_priv(dev);
3707
3708 if (phy_configs[tp->mac_version])
3709 phy_configs[tp->mac_version](tp);
3710 }
3711
3712 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3713 {
3714 if (!test_and_set_bit(flag, tp->wk.flags))
3715 schedule_work(&tp->wk.work);
3716 }
3717
3718 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3719 {
3720 rtl_hw_phy_config(dev);
3721
3722 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3723 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3724 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3725 netif_dbg(tp, drv, dev,
3726 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3727 RTL_W8(tp, 0x82, 0x01);
3728 }
3729
3730 /* We may have called phy_speed_down before */
3731 phy_speed_up(tp->phydev);
3732
3733 genphy_soft_reset(tp->phydev);
3734 }
3735
3736 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3737 {
3738 rtl_lock_work(tp);
3739
3740 rtl_unlock_config_regs(tp);
3741
3742 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
3743 RTL_R32(tp, MAC4);
3744
3745 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3746 RTL_R32(tp, MAC0);
3747
3748 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3749 rtl_rar_exgmac_set(tp, addr);
3750
3751 rtl_lock_config_regs(tp);
3752
3753 rtl_unlock_work(tp);
3754 }
3755
3756 static int rtl_set_mac_address(struct net_device *dev, void *p)
3757 {
3758 struct rtl8169_private *tp = netdev_priv(dev);
3759 struct device *d = tp_to_dev(tp);
3760 int ret;
3761
3762 ret = eth_mac_addr(dev, p);
3763 if (ret)
3764 return ret;
3765
3766 pm_runtime_get_noresume(d);
3767
3768 if (pm_runtime_active(d))
3769 rtl_rar_set(tp, dev->dev_addr);
3770
3771 pm_runtime_put_noidle(d);
3772
3773 return 0;
3774 }
3775
3776 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3777 {
3778 struct rtl8169_private *tp = netdev_priv(dev);
3779
3780 if (!netif_running(dev))
3781 return -ENODEV;
3782
3783 return phy_mii_ioctl(tp->phydev, ifr, cmd);
3784 }
3785
3786 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3787 {
3788 switch (tp->mac_version) {
3789 case RTL_GIGA_MAC_VER_25:
3790 case RTL_GIGA_MAC_VER_26:
3791 case RTL_GIGA_MAC_VER_29:
3792 case RTL_GIGA_MAC_VER_30:
3793 case RTL_GIGA_MAC_VER_32:
3794 case RTL_GIGA_MAC_VER_33:
3795 case RTL_GIGA_MAC_VER_34:
3796 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
3797 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
3798 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3799 break;
3800 default:
3801 break;
3802 }
3803 }
3804
3805 static void rtl_pll_power_down(struct rtl8169_private *tp)
3806 {
3807 if (r8168_check_dash(tp))
3808 return;
3809
3810 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3811 tp->mac_version == RTL_GIGA_MAC_VER_33)
3812 rtl_ephy_write(tp, 0x19, 0xff64);
3813
3814 if (device_may_wakeup(tp_to_dev(tp))) {
3815 phy_speed_down(tp->phydev, false);
3816 rtl_wol_suspend_quirk(tp);
3817 return;
3818 }
3819
3820 switch (tp->mac_version) {
3821 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
3822 case RTL_GIGA_MAC_VER_37:
3823 case RTL_GIGA_MAC_VER_39:
3824 case RTL_GIGA_MAC_VER_43:
3825 case RTL_GIGA_MAC_VER_44:
3826 case RTL_GIGA_MAC_VER_45:
3827 case RTL_GIGA_MAC_VER_46:
3828 case RTL_GIGA_MAC_VER_47:
3829 case RTL_GIGA_MAC_VER_48:
3830 case RTL_GIGA_MAC_VER_50:
3831 case RTL_GIGA_MAC_VER_51:
3832 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
3833 break;
3834 case RTL_GIGA_MAC_VER_40:
3835 case RTL_GIGA_MAC_VER_41:
3836 case RTL_GIGA_MAC_VER_49:
3837 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
3838 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
3839 break;
3840 default:
3841 break;
3842 }
3843 }
3844
3845 static void rtl_pll_power_up(struct rtl8169_private *tp)
3846 {
3847 switch (tp->mac_version) {
3848 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
3849 case RTL_GIGA_MAC_VER_37:
3850 case RTL_GIGA_MAC_VER_39:
3851 case RTL_GIGA_MAC_VER_43:
3852 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
3853 break;
3854 case RTL_GIGA_MAC_VER_44:
3855 case RTL_GIGA_MAC_VER_45:
3856 case RTL_GIGA_MAC_VER_46:
3857 case RTL_GIGA_MAC_VER_47:
3858 case RTL_GIGA_MAC_VER_48:
3859 case RTL_GIGA_MAC_VER_50:
3860 case RTL_GIGA_MAC_VER_51:
3861 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
3862 break;
3863 case RTL_GIGA_MAC_VER_40:
3864 case RTL_GIGA_MAC_VER_41:
3865 case RTL_GIGA_MAC_VER_49:
3866 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
3867 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
3868 break;
3869 default:
3870 break;
3871 }
3872
3873 phy_resume(tp->phydev);
3874 /* give MAC/PHY some time to resume */
3875 msleep(20);
3876 }
3877
3878 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3879 {
3880 switch (tp->mac_version) {
3881 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
3882 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
3883 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3884 break;
3885 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
3886 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
3887 case RTL_GIGA_MAC_VER_38:
3888 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3889 break;
3890 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
3891 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
3892 break;
3893 default:
3894 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
3895 break;
3896 }
3897 }
3898
3899 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3900 {
3901 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
3902 }
3903
3904 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3905 {
3906 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3907 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
3908 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
3909 }
3910
3911 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3912 {
3913 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3914 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
3915 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
3916 }
3917
3918 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3919 {
3920 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3921 }
3922
3923 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3924 {
3925 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3926 }
3927
3928 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3929 {
3930 RTL_W8(tp, MaxTxPacketSize, 0x3f);
3931 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3932 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
3933 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
3934 }
3935
3936 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3937 {
3938 RTL_W8(tp, MaxTxPacketSize, 0x0c);
3939 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3940 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
3941 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
3942 }
3943
3944 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3945 {
3946 rtl_tx_performance_tweak(tp,
3947 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
3948 }
3949
3950 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3951 {
3952 rtl_tx_performance_tweak(tp,
3953 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
3954 }
3955
3956 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3957 {
3958 r8168b_0_hw_jumbo_enable(tp);
3959
3960 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
3961 }
3962
3963 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3964 {
3965 r8168b_0_hw_jumbo_disable(tp);
3966
3967 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
3968 }
3969
3970 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3971 {
3972 rtl_unlock_config_regs(tp);
3973 switch (tp->mac_version) {
3974 case RTL_GIGA_MAC_VER_11:
3975 r8168b_0_hw_jumbo_enable(tp);
3976 break;
3977 case RTL_GIGA_MAC_VER_12:
3978 case RTL_GIGA_MAC_VER_17:
3979 r8168b_1_hw_jumbo_enable(tp);
3980 break;
3981 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
3982 r8168c_hw_jumbo_enable(tp);
3983 break;
3984 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
3985 r8168dp_hw_jumbo_enable(tp);
3986 break;
3987 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
3988 r8168e_hw_jumbo_enable(tp);
3989 break;
3990 default:
3991 break;
3992 }
3993 rtl_lock_config_regs(tp);
3994 }
3995
3996 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3997 {
3998 rtl_unlock_config_regs(tp);
3999 switch (tp->mac_version) {
4000 case RTL_GIGA_MAC_VER_11:
4001 r8168b_0_hw_jumbo_disable(tp);
4002 break;
4003 case RTL_GIGA_MAC_VER_12:
4004 case RTL_GIGA_MAC_VER_17:
4005 r8168b_1_hw_jumbo_disable(tp);
4006 break;
4007 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
4008 r8168c_hw_jumbo_disable(tp);
4009 break;
4010 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
4011 r8168dp_hw_jumbo_disable(tp);
4012 break;
4013 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
4014 r8168e_hw_jumbo_disable(tp);
4015 break;
4016 default:
4017 break;
4018 }
4019 rtl_lock_config_regs(tp);
4020 }
4021
4022 DECLARE_RTL_COND(rtl_chipcmd_cond)
4023 {
4024 return RTL_R8(tp, ChipCmd) & CmdReset;
4025 }
4026
4027 static void rtl_hw_reset(struct rtl8169_private *tp)
4028 {
4029 RTL_W8(tp, ChipCmd, CmdReset);
4030
4031 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4032 }
4033
4034 static void rtl_request_firmware(struct rtl8169_private *tp)
4035 {
4036 struct rtl_fw *rtl_fw;
4037
4038 /* firmware loaded already or no firmware available */
4039 if (tp->rtl_fw || !tp->fw_name)
4040 return;
4041
4042 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4043 if (!rtl_fw) {
4044 netif_warn(tp, ifup, tp->dev, "Unable to load firmware, out of memory\n");
4045 return;
4046 }
4047
4048 rtl_fw->phy_write = rtl_writephy;
4049 rtl_fw->phy_read = rtl_readphy;
4050 rtl_fw->mac_mcu_write = mac_mcu_write;
4051 rtl_fw->mac_mcu_read = mac_mcu_read;
4052 rtl_fw->fw_name = tp->fw_name;
4053 rtl_fw->dev = tp_to_dev(tp);
4054
4055 if (rtl_fw_request_firmware(rtl_fw))
4056 kfree(rtl_fw);
4057 else
4058 tp->rtl_fw = rtl_fw;
4059 }
4060
4061 static void rtl_rx_close(struct rtl8169_private *tp)
4062 {
4063 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4064 }
4065
4066 DECLARE_RTL_COND(rtl_npq_cond)
4067 {
4068 return RTL_R8(tp, TxPoll) & NPQ;
4069 }
4070
4071 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4072 {
4073 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4074 }
4075
4076 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4077 {
4078 /* Disable interrupts */
4079 rtl8169_irq_mask_and_ack(tp);
4080
4081 rtl_rx_close(tp);
4082
4083 switch (tp->mac_version) {
4084 case RTL_GIGA_MAC_VER_27:
4085 case RTL_GIGA_MAC_VER_28:
4086 case RTL_GIGA_MAC_VER_31:
4087 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4088 break;
4089 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4090 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4091 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4092 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4093 break;
4094 default:
4095 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4096 udelay(100);
4097 break;
4098 }
4099
4100 rtl_hw_reset(tp);
4101 }
4102
4103 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4104 {
4105 u32 val = TX_DMA_BURST << TxDMAShift |
4106 InterFrameGap << TxInterFrameGapShift;
4107
4108 if (tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
4109 tp->mac_version != RTL_GIGA_MAC_VER_39)
4110 val |= TXCFG_AUTO_FIFO;
4111
4112 RTL_W32(tp, TxConfig, val);
4113 }
4114
4115 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4116 {
4117 /* Low hurts. Let's disable the filtering. */
4118 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4119 }
4120
4121 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4122 {
4123 /*
4124 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4125 * register to be written before TxDescAddrLow to work.
4126 * Switching from MMIO to I/O access fixes the issue as well.
4127 */
4128 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4129 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4130 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4131 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4132 }
4133
4134 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4135 {
4136 u32 val;
4137
4138 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4139 val = 0x000fff00;
4140 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4141 val = 0x00ffff00;
4142 else
4143 return;
4144
4145 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4146 val |= 0xff;
4147
4148 RTL_W32(tp, 0x7c, val);
4149 }
4150
4151 static void rtl_set_rx_mode(struct net_device *dev)
4152 {
4153 struct rtl8169_private *tp = netdev_priv(dev);
4154 u32 mc_filter[2]; /* Multicast hash filter */
4155 int rx_mode;
4156 u32 tmp = 0;
4157
4158 if (dev->flags & IFF_PROMISC) {
4159 /* Unconditionally log net taps. */
4160 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4161 rx_mode =
4162 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4163 AcceptAllPhys;
4164 mc_filter[1] = mc_filter[0] = 0xffffffff;
4165 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4166 (dev->flags & IFF_ALLMULTI)) {
4167 /* Too many to filter perfectly -- accept all multicasts. */
4168 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4169 mc_filter[1] = mc_filter[0] = 0xffffffff;
4170 } else {
4171 struct netdev_hw_addr *ha;
4172
4173 rx_mode = AcceptBroadcast | AcceptMyPhys;
4174 mc_filter[1] = mc_filter[0] = 0;
4175 netdev_for_each_mc_addr(ha, dev) {
4176 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4177 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4178 rx_mode |= AcceptMulticast;
4179 }
4180 }
4181
4182 if (dev->features & NETIF_F_RXALL)
4183 rx_mode |= (AcceptErr | AcceptRunt);
4184
4185 tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4186
4187 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4188 u32 data = mc_filter[0];
4189
4190 mc_filter[0] = swab32(mc_filter[1]);
4191 mc_filter[1] = swab32(data);
4192 }
4193
4194 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4195 mc_filter[1] = mc_filter[0] = 0xffffffff;
4196
4197 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4198 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4199
4200 RTL_W32(tp, RxConfig, tmp);
4201 }
4202
4203 DECLARE_RTL_COND(rtl_csiar_cond)
4204 {
4205 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4206 }
4207
4208 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4209 {
4210 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4211
4212 RTL_W32(tp, CSIDR, value);
4213 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4214 CSIAR_BYTE_ENABLE | func << 16);
4215
4216 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4217 }
4218
4219 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4220 {
4221 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4222
4223 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4224 CSIAR_BYTE_ENABLE);
4225
4226 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4227 RTL_R32(tp, CSIDR) : ~0;
4228 }
4229
4230 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4231 {
4232 struct pci_dev *pdev = tp->pci_dev;
4233 u32 csi;
4234
4235 /* According to Realtek the value at config space address 0x070f
4236 * controls the L0s/L1 entrance latency. We try standard ECAM access
4237 * first and if it fails fall back to CSI.
4238 */
4239 if (pdev->cfg_size > 0x070f &&
4240 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4241 return;
4242
4243 netdev_notice_once(tp->dev,
4244 "No native access to PCI extended config space, falling back to CSI\n");
4245 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4246 rtl_csi_write(tp, 0x070c, csi | val << 24);
4247 }
4248
4249 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4250 {
4251 rtl_csi_access_enable(tp, 0x27);
4252 }
4253
4254 struct ephy_info {
4255 unsigned int offset;
4256 u16 mask;
4257 u16 bits;
4258 };
4259
4260 static void __rtl_ephy_init(struct rtl8169_private *tp,
4261 const struct ephy_info *e, int len)
4262 {
4263 u16 w;
4264
4265 while (len-- > 0) {
4266 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4267 rtl_ephy_write(tp, e->offset, w);
4268 e++;
4269 }
4270 }
4271
4272 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
4273
4274 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4275 {
4276 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4277 PCI_EXP_LNKCTL_CLKREQ_EN);
4278 }
4279
4280 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4281 {
4282 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4283 PCI_EXP_LNKCTL_CLKREQ_EN);
4284 }
4285
4286 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
4287 {
4288 /* work around an issue when PCI reset occurs during L2/L3 state */
4289 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
4290 }
4291
4292 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4293 {
4294 if (enable) {
4295 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4296 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4297 } else {
4298 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4299 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4300 }
4301
4302 udelay(10);
4303 }
4304
4305 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
4306 u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
4307 {
4308 /* Usage of dynamic vs. static FIFO is controlled by bit
4309 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
4310 */
4311 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
4312 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
4313 }
4314
4315 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
4316 u8 low, u8 high)
4317 {
4318 /* FIFO thresholds for pause flow control */
4319 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
4320 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
4321 }
4322
4323 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4324 {
4325 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4326
4327 if (tp->dev->mtu <= ETH_DATA_LEN) {
4328 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4329 PCI_EXP_DEVCTL_NOSNOOP_EN);
4330 }
4331 }
4332
4333 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4334 {
4335 rtl_hw_start_8168bb(tp);
4336
4337 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4338
4339 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4340 }
4341
4342 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4343 {
4344 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4345
4346 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4347
4348 if (tp->dev->mtu <= ETH_DATA_LEN)
4349 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4350
4351 rtl_disable_clock_request(tp);
4352 }
4353
4354 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4355 {
4356 static const struct ephy_info e_info_8168cp[] = {
4357 { 0x01, 0, 0x0001 },
4358 { 0x02, 0x0800, 0x1000 },
4359 { 0x03, 0, 0x0042 },
4360 { 0x06, 0x0080, 0x0000 },
4361 { 0x07, 0, 0x2000 }
4362 };
4363
4364 rtl_set_def_aspm_entry_latency(tp);
4365
4366 rtl_ephy_init(tp, e_info_8168cp);
4367
4368 __rtl_hw_start_8168cp(tp);
4369 }
4370
4371 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4372 {
4373 rtl_set_def_aspm_entry_latency(tp);
4374
4375 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4376
4377 if (tp->dev->mtu <= ETH_DATA_LEN)
4378 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4379 }
4380
4381 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4382 {
4383 rtl_set_def_aspm_entry_latency(tp);
4384
4385 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4386
4387 /* Magic. */
4388 RTL_W8(tp, DBG_REG, 0x20);
4389
4390 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4391
4392 if (tp->dev->mtu <= ETH_DATA_LEN)
4393 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4394 }
4395
4396 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4397 {
4398 static const struct ephy_info e_info_8168c_1[] = {
4399 { 0x02, 0x0800, 0x1000 },
4400 { 0x03, 0, 0x0002 },
4401 { 0x06, 0x0080, 0x0000 }
4402 };
4403
4404 rtl_set_def_aspm_entry_latency(tp);
4405
4406 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4407
4408 rtl_ephy_init(tp, e_info_8168c_1);
4409
4410 __rtl_hw_start_8168cp(tp);
4411 }
4412
4413 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4414 {
4415 static const struct ephy_info e_info_8168c_2[] = {
4416 { 0x01, 0, 0x0001 },
4417 { 0x03, 0x0400, 0x0220 }
4418 };
4419
4420 rtl_set_def_aspm_entry_latency(tp);
4421
4422 rtl_ephy_init(tp, e_info_8168c_2);
4423
4424 __rtl_hw_start_8168cp(tp);
4425 }
4426
4427 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4428 {
4429 rtl_hw_start_8168c_2(tp);
4430 }
4431
4432 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4433 {
4434 rtl_set_def_aspm_entry_latency(tp);
4435
4436 __rtl_hw_start_8168cp(tp);
4437 }
4438
4439 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4440 {
4441 rtl_set_def_aspm_entry_latency(tp);
4442
4443 rtl_disable_clock_request(tp);
4444
4445 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4446
4447 if (tp->dev->mtu <= ETH_DATA_LEN)
4448 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4449 }
4450
4451 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4452 {
4453 rtl_set_def_aspm_entry_latency(tp);
4454
4455 if (tp->dev->mtu <= ETH_DATA_LEN)
4456 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4457
4458 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4459
4460 rtl_disable_clock_request(tp);
4461 }
4462
4463 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4464 {
4465 static const struct ephy_info e_info_8168d_4[] = {
4466 { 0x0b, 0x0000, 0x0048 },
4467 { 0x19, 0x0020, 0x0050 },
4468 { 0x0c, 0x0100, 0x0020 }
4469 };
4470
4471 rtl_set_def_aspm_entry_latency(tp);
4472
4473 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4474
4475 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4476
4477 rtl_ephy_init(tp, e_info_8168d_4);
4478
4479 rtl_enable_clock_request(tp);
4480 }
4481
4482 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4483 {
4484 static const struct ephy_info e_info_8168e_1[] = {
4485 { 0x00, 0x0200, 0x0100 },
4486 { 0x00, 0x0000, 0x0004 },
4487 { 0x06, 0x0002, 0x0001 },
4488 { 0x06, 0x0000, 0x0030 },
4489 { 0x07, 0x0000, 0x2000 },
4490 { 0x00, 0x0000, 0x0020 },
4491 { 0x03, 0x5800, 0x2000 },
4492 { 0x03, 0x0000, 0x0001 },
4493 { 0x01, 0x0800, 0x1000 },
4494 { 0x07, 0x0000, 0x4000 },
4495 { 0x1e, 0x0000, 0x2000 },
4496 { 0x19, 0xffff, 0xfe6c },
4497 { 0x0a, 0x0000, 0x0040 }
4498 };
4499
4500 rtl_set_def_aspm_entry_latency(tp);
4501
4502 rtl_ephy_init(tp, e_info_8168e_1);
4503
4504 if (tp->dev->mtu <= ETH_DATA_LEN)
4505 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4506
4507 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4508
4509 rtl_disable_clock_request(tp);
4510
4511 /* Reset tx FIFO pointer */
4512 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4513 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4514
4515 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4516 }
4517
4518 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4519 {
4520 static const struct ephy_info e_info_8168e_2[] = {
4521 { 0x09, 0x0000, 0x0080 },
4522 { 0x19, 0x0000, 0x0224 }
4523 };
4524
4525 rtl_set_def_aspm_entry_latency(tp);
4526
4527 rtl_ephy_init(tp, e_info_8168e_2);
4528
4529 if (tp->dev->mtu <= ETH_DATA_LEN)
4530 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4531
4532 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4533 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4534 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4535 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4536 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
4537 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4538 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4539
4540 RTL_W8(tp, MaxTxPacketSize, EarlySize);
4541
4542 rtl_disable_clock_request(tp);
4543
4544 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4545
4546 rtl8168_config_eee_mac(tp);
4547
4548 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4549 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4550 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4551
4552 rtl_hw_aspm_clkreq_enable(tp, true);
4553 }
4554
4555 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
4556 {
4557 rtl_set_def_aspm_entry_latency(tp);
4558
4559 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4560
4561 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4562 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4563 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4564 rtl_reset_packet_filter(tp);
4565 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4566 rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));
4567 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4568 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
4569
4570 RTL_W8(tp, MaxTxPacketSize, EarlySize);
4571
4572 rtl_disable_clock_request(tp);
4573
4574 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4575 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4576 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4577 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4578
4579 rtl8168_config_eee_mac(tp);
4580 }
4581
4582 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
4583 {
4584 static const struct ephy_info e_info_8168f_1[] = {
4585 { 0x06, 0x00c0, 0x0020 },
4586 { 0x08, 0x0001, 0x0002 },
4587 { 0x09, 0x0000, 0x0080 },
4588 { 0x19, 0x0000, 0x0224 }
4589 };
4590
4591 rtl_hw_start_8168f(tp);
4592
4593 rtl_ephy_init(tp, e_info_8168f_1);
4594
4595 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4596 }
4597
4598 static void rtl_hw_start_8411(struct rtl8169_private *tp)
4599 {
4600 static const struct ephy_info e_info_8168f_1[] = {
4601 { 0x06, 0x00c0, 0x0020 },
4602 { 0x0f, 0xffff, 0x5200 },
4603 { 0x1e, 0x0000, 0x4000 },
4604 { 0x19, 0x0000, 0x0224 }
4605 };
4606
4607 rtl_hw_start_8168f(tp);
4608 rtl_pcie_state_l2l3_disable(tp);
4609
4610 rtl_ephy_init(tp, e_info_8168f_1);
4611
4612 rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);
4613 }
4614
4615 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
4616 {
4617 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4618 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4619
4620 rtl_set_def_aspm_entry_latency(tp);
4621
4622 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4623
4624 rtl_reset_packet_filter(tp);
4625 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
4626
4627 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4628 RTL_W8(tp, MaxTxPacketSize, EarlySize);
4629
4630 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4631 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4632
4633 rtl8168_config_eee_mac(tp);
4634
4635 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
4636 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4637
4638 rtl_pcie_state_l2l3_disable(tp);
4639 }
4640
4641 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
4642 {
4643 static const struct ephy_info e_info_8168g_1[] = {
4644 { 0x00, 0x0000, 0x0008 },
4645 { 0x0c, 0x37d0, 0x0820 },
4646 { 0x1e, 0x0000, 0x0001 },
4647 { 0x19, 0x8000, 0x0000 }
4648 };
4649
4650 rtl_hw_start_8168g(tp);
4651
4652 /* disable aspm and clock request before access ephy */
4653 rtl_hw_aspm_clkreq_enable(tp, false);
4654 rtl_ephy_init(tp, e_info_8168g_1);
4655 rtl_hw_aspm_clkreq_enable(tp, true);
4656 }
4657
4658 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
4659 {
4660 static const struct ephy_info e_info_8168g_2[] = {
4661 { 0x00, 0x0000, 0x0008 },
4662 { 0x0c, 0x3df0, 0x0200 },
4663 { 0x19, 0xffff, 0xfc00 },
4664 { 0x1e, 0xffff, 0x20eb }
4665 };
4666
4667 rtl_hw_start_8168g(tp);
4668
4669 /* disable aspm and clock request before access ephy */
4670 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4671 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4672 rtl_ephy_init(tp, e_info_8168g_2);
4673 }
4674
4675 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
4676 {
4677 static const struct ephy_info e_info_8411_2[] = {
4678 { 0x00, 0x0000, 0x0008 },
4679 { 0x0c, 0x3df0, 0x0200 },
4680 { 0x0f, 0xffff, 0x5200 },
4681 { 0x19, 0x0020, 0x0000 },
4682 { 0x1e, 0x0000, 0x2000 }
4683 };
4684
4685 rtl_hw_start_8168g(tp);
4686
4687 /* disable aspm and clock request before access ephy */
4688 rtl_hw_aspm_clkreq_enable(tp, false);
4689 rtl_ephy_init(tp, e_info_8411_2);
4690 rtl_hw_aspm_clkreq_enable(tp, true);
4691 }
4692
4693 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
4694 {
4695 int rg_saw_cnt;
4696 u32 data;
4697 static const struct ephy_info e_info_8168h_1[] = {
4698 { 0x1e, 0x0800, 0x0001 },
4699 { 0x1d, 0x0000, 0x0800 },
4700 { 0x05, 0xffff, 0x2089 },
4701 { 0x06, 0xffff, 0x5881 },
4702 { 0x04, 0xffff, 0x154a },
4703 { 0x01, 0xffff, 0x068b }
4704 };
4705
4706 /* disable aspm and clock request before access ephy */
4707 rtl_hw_aspm_clkreq_enable(tp, false);
4708 rtl_ephy_init(tp, e_info_8168h_1);
4709
4710 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4711 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4712
4713 rtl_set_def_aspm_entry_latency(tp);
4714
4715 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4716
4717 rtl_reset_packet_filter(tp);
4718
4719 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
4720
4721 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);
4722
4723 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
4724
4725 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4726 RTL_W8(tp, MaxTxPacketSize, EarlySize);
4727
4728 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4729 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4730
4731 rtl8168_config_eee_mac(tp);
4732
4733 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4734 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4735
4736 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
4737
4738 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4739
4740 rtl_pcie_state_l2l3_disable(tp);
4741
4742 rtl_writephy(tp, 0x1f, 0x0c42);
4743 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
4744 rtl_writephy(tp, 0x1f, 0x0000);
4745 if (rg_saw_cnt > 0) {
4746 u16 sw_cnt_1ms_ini;
4747
4748 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
4749 sw_cnt_1ms_ini &= 0x0fff;
4750 data = r8168_mac_ocp_read(tp, 0xd412);
4751 data &= ~0x0fff;
4752 data |= sw_cnt_1ms_ini;
4753 r8168_mac_ocp_write(tp, 0xd412, data);
4754 }
4755
4756 data = r8168_mac_ocp_read(tp, 0xe056);
4757 data &= ~0xf0;
4758 data |= 0x70;
4759 r8168_mac_ocp_write(tp, 0xe056, data);
4760
4761 data = r8168_mac_ocp_read(tp, 0xe052);
4762 data &= ~0x6000;
4763 data |= 0x8008;
4764 r8168_mac_ocp_write(tp, 0xe052, data);
4765
4766 data = r8168_mac_ocp_read(tp, 0xe0d6);
4767 data &= ~0x01ff;
4768 data |= 0x017f;
4769 r8168_mac_ocp_write(tp, 0xe0d6, data);
4770
4771 data = r8168_mac_ocp_read(tp, 0xd420);
4772 data &= ~0x0fff;
4773 data |= 0x047f;
4774 r8168_mac_ocp_write(tp, 0xd420, data);
4775
4776 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
4777 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
4778 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
4779 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
4780
4781 rtl_hw_aspm_clkreq_enable(tp, true);
4782 }
4783
4784 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
4785 {
4786 rtl8168ep_stop_cmac(tp);
4787
4788 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4789 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
4790
4791 rtl_set_def_aspm_entry_latency(tp);
4792
4793 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4794
4795 rtl_reset_packet_filter(tp);
4796
4797 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
4798
4799 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
4800
4801 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4802 RTL_W8(tp, MaxTxPacketSize, EarlySize);
4803
4804 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4805 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4806
4807 rtl8168_config_eee_mac(tp);
4808
4809 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
4810
4811 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
4812
4813 rtl_pcie_state_l2l3_disable(tp);
4814 }
4815
4816 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
4817 {
4818 static const struct ephy_info e_info_8168ep_1[] = {
4819 { 0x00, 0xffff, 0x10ab },
4820 { 0x06, 0xffff, 0xf030 },
4821 { 0x08, 0xffff, 0x2006 },
4822 { 0x0d, 0xffff, 0x1666 },
4823 { 0x0c, 0x3ff0, 0x0000 }
4824 };
4825
4826 /* disable aspm and clock request before access ephy */
4827 rtl_hw_aspm_clkreq_enable(tp, false);
4828 rtl_ephy_init(tp, e_info_8168ep_1);
4829
4830 rtl_hw_start_8168ep(tp);
4831
4832 rtl_hw_aspm_clkreq_enable(tp, true);
4833 }
4834
4835 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
4836 {
4837 static const struct ephy_info e_info_8168ep_2[] = {
4838 { 0x00, 0xffff, 0x10a3 },
4839 { 0x19, 0xffff, 0xfc00 },
4840 { 0x1e, 0xffff, 0x20ea }
4841 };
4842
4843 /* disable aspm and clock request before access ephy */
4844 rtl_hw_aspm_clkreq_enable(tp, false);
4845 rtl_ephy_init(tp, e_info_8168ep_2);
4846
4847 rtl_hw_start_8168ep(tp);
4848
4849 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4850 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4851
4852 rtl_hw_aspm_clkreq_enable(tp, true);
4853 }
4854
4855 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
4856 {
4857 u32 data;
4858 static const struct ephy_info e_info_8168ep_3[] = {
4859 { 0x00, 0xffff, 0x10a3 },
4860 { 0x19, 0xffff, 0x7c00 },
4861 { 0x1e, 0xffff, 0x20eb },
4862 { 0x0d, 0xffff, 0x1666 }
4863 };
4864
4865 /* disable aspm and clock request before access ephy */
4866 rtl_hw_aspm_clkreq_enable(tp, false);
4867 rtl_ephy_init(tp, e_info_8168ep_3);
4868
4869 rtl_hw_start_8168ep(tp);
4870
4871 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4872 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4873
4874 data = r8168_mac_ocp_read(tp, 0xd3e2);
4875 data &= 0xf000;
4876 data |= 0x0271;
4877 r8168_mac_ocp_write(tp, 0xd3e2, data);
4878
4879 data = r8168_mac_ocp_read(tp, 0xd3e4);
4880 data &= 0xff00;
4881 r8168_mac_ocp_write(tp, 0xd3e4, data);
4882
4883 data = r8168_mac_ocp_read(tp, 0xe860);
4884 data |= 0x0080;
4885 r8168_mac_ocp_write(tp, 0xe860, data);
4886
4887 rtl_hw_aspm_clkreq_enable(tp, true);
4888 }
4889
4890 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
4891 {
4892 static const struct ephy_info e_info_8102e_1[] = {
4893 { 0x01, 0, 0x6e65 },
4894 { 0x02, 0, 0x091f },
4895 { 0x03, 0, 0xc2f9 },
4896 { 0x06, 0, 0xafb5 },
4897 { 0x07, 0, 0x0e00 },
4898 { 0x19, 0, 0xec80 },
4899 { 0x01, 0, 0x2e65 },
4900 { 0x01, 0, 0x6e65 }
4901 };
4902 u8 cfg1;
4903
4904 rtl_set_def_aspm_entry_latency(tp);
4905
4906 RTL_W8(tp, DBG_REG, FIX_NAK_1);
4907
4908 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4909
4910 RTL_W8(tp, Config1,
4911 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4912 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4913
4914 cfg1 = RTL_R8(tp, Config1);
4915 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4916 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
4917
4918 rtl_ephy_init(tp, e_info_8102e_1);
4919 }
4920
4921 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
4922 {
4923 rtl_set_def_aspm_entry_latency(tp);
4924
4925 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4926
4927 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
4928 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4929 }
4930
4931 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
4932 {
4933 rtl_hw_start_8102e_2(tp);
4934
4935 rtl_ephy_write(tp, 0x03, 0xc2f9);
4936 }
4937
4938 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
4939 {
4940 static const struct ephy_info e_info_8105e_1[] = {
4941 { 0x07, 0, 0x4000 },
4942 { 0x19, 0, 0x0200 },
4943 { 0x19, 0, 0x0020 },
4944 { 0x1e, 0, 0x2000 },
4945 { 0x03, 0, 0x0001 },
4946 { 0x19, 0, 0x0100 },
4947 { 0x19, 0, 0x0004 },
4948 { 0x0a, 0, 0x0020 }
4949 };
4950
4951 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4952 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
4953
4954 /* Disable Early Tally Counter */
4955 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
4956
4957 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
4958 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4959
4960 rtl_ephy_init(tp, e_info_8105e_1);
4961
4962 rtl_pcie_state_l2l3_disable(tp);
4963 }
4964
4965 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
4966 {
4967 rtl_hw_start_8105e_1(tp);
4968 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
4969 }
4970
4971 static void rtl_hw_start_8402(struct rtl8169_private *tp)
4972 {
4973 static const struct ephy_info e_info_8402[] = {
4974 { 0x19, 0xffff, 0xff64 },
4975 { 0x1e, 0, 0x4000 }
4976 };
4977
4978 rtl_set_def_aspm_entry_latency(tp);
4979
4980 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4981 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
4982
4983 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4984
4985 rtl_ephy_init(tp, e_info_8402);
4986
4987 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4988
4989 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
4990 rtl_reset_packet_filter(tp);
4991 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4992 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4993 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
4994
4995 rtl_pcie_state_l2l3_disable(tp);
4996 }
4997
4998 static void rtl_hw_start_8106(struct rtl8169_private *tp)
4999 {
5000 rtl_hw_aspm_clkreq_enable(tp, false);
5001
5002 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5003 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5004
5005 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5006 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5007 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5008
5009 rtl_pcie_state_l2l3_disable(tp);
5010 rtl_hw_aspm_clkreq_enable(tp, true);
5011 }
5012
5013 static void rtl_hw_config(struct rtl8169_private *tp)
5014 {
5015 static const rtl_generic_fct hw_configs[] = {
5016 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
5017 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
5018 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
5019 [RTL_GIGA_MAC_VER_10] = NULL,
5020 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168bb,
5021 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168bef,
5022 [RTL_GIGA_MAC_VER_13] = NULL,
5023 [RTL_GIGA_MAC_VER_14] = NULL,
5024 [RTL_GIGA_MAC_VER_15] = NULL,
5025 [RTL_GIGA_MAC_VER_16] = NULL,
5026 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168bef,
5027 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
5028 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
5029 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
5030 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
5031 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
5032 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
5033 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
5034 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
5035 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
5036 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
5037 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
5038 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
5039 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
5040 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168dp,
5041 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
5042 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
5043 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
5044 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
5045 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
5046 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
5047 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
5048 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
5049 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
5050 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
5051 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
5052 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
5053 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
5054 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
5055 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
5056 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
5057 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
5058 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
5059 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
5060 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
5061 };
5062
5063 if (hw_configs[tp->mac_version])
5064 hw_configs[tp->mac_version](tp);
5065 }
5066
5067 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5068 {
5069 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5070 tp->mac_version == RTL_GIGA_MAC_VER_16)
5071 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5072 PCI_EXP_DEVCTL_NOSNOOP_EN);
5073
5074 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5075
5076 rtl_hw_config(tp);
5077 }
5078
5079 static void rtl_hw_start_8169(struct rtl8169_private *tp)
5080 {
5081 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5082 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
5083
5084 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
5085
5086 tp->cp_cmd |= PCIMulRW;
5087
5088 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5089 tp->mac_version == RTL_GIGA_MAC_VER_03) {
5090 netif_dbg(tp, drv, tp->dev,
5091 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
5092 tp->cp_cmd |= (1 << 14);
5093 }
5094
5095 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5096
5097 rtl8169_set_magic_reg(tp, tp->mac_version);
5098
5099 RTL_W32(tp, RxMissed, 0);
5100 }
5101
5102 static void rtl_hw_start(struct rtl8169_private *tp)
5103 {
5104 rtl_unlock_config_regs(tp);
5105
5106 tp->cp_cmd &= CPCMD_MASK;
5107 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5108
5109 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5110 rtl_hw_start_8169(tp);
5111 else
5112 rtl_hw_start_8168(tp);
5113
5114 rtl_set_rx_max_size(tp);
5115 rtl_set_rx_tx_desc_registers(tp);
5116 rtl_lock_config_regs(tp);
5117
5118 /* disable interrupt coalescing */
5119 RTL_W16(tp, IntrMitigate, 0x0000);
5120 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5121 RTL_R8(tp, IntrMask);
5122 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
5123 rtl_init_rxcfg(tp);
5124 rtl_set_tx_config_registers(tp);
5125
5126 rtl_set_rx_mode(tp->dev);
5127 /* no early-rx interrupts */
5128 RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
5129 rtl_irq_enable(tp);
5130 }
5131
5132 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5133 {
5134 struct rtl8169_private *tp = netdev_priv(dev);
5135
5136 if (new_mtu > ETH_DATA_LEN)
5137 rtl_hw_jumbo_enable(tp);
5138 else
5139 rtl_hw_jumbo_disable(tp);
5140
5141 dev->mtu = new_mtu;
5142 netdev_update_features(dev);
5143
5144 return 0;
5145 }
5146
5147 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5148 {
5149 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5150 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5151 }
5152
5153 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5154 void **data_buff, struct RxDesc *desc)
5155 {
5156 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5157 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5158
5159 kfree(*data_buff);
5160 *data_buff = NULL;
5161 rtl8169_make_unusable_by_asic(desc);
5162 }
5163
5164 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5165 {
5166 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5167
5168 /* Force memory writes to complete before releasing descriptor */
5169 dma_wmb();
5170
5171 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5172 }
5173
5174 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5175 struct RxDesc *desc)
5176 {
5177 void *data;
5178 dma_addr_t mapping;
5179 struct device *d = tp_to_dev(tp);
5180 int node = dev_to_node(d);
5181
5182 data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5183 if (!data)
5184 return NULL;
5185
5186 /* Memory should be properly aligned, but better check. */
5187 if (!IS_ALIGNED((unsigned long)data, 8)) {
5188 netdev_err_once(tp->dev, "RX buffer not 8-byte-aligned\n");
5189 goto err_out;
5190 }
5191
5192 mapping = dma_map_single(d, data, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5193 if (unlikely(dma_mapping_error(d, mapping))) {
5194 if (net_ratelimit())
5195 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5196 goto err_out;
5197 }
5198
5199 desc->addr = cpu_to_le64(mapping);
5200 rtl8169_mark_to_asic(desc);
5201 return data;
5202
5203 err_out:
5204 kfree(data);
5205 return NULL;
5206 }
5207
5208 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5209 {
5210 unsigned int i;
5211
5212 for (i = 0; i < NUM_RX_DESC; i++) {
5213 if (tp->Rx_databuff[i]) {
5214 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5215 tp->RxDescArray + i);
5216 }
5217 }
5218 }
5219
5220 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5221 {
5222 desc->opts1 |= cpu_to_le32(RingEnd);
5223 }
5224
5225 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5226 {
5227 unsigned int i;
5228
5229 for (i = 0; i < NUM_RX_DESC; i++) {
5230 void *data;
5231
5232 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5233 if (!data) {
5234 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5235 goto err_out;
5236 }
5237 tp->Rx_databuff[i] = data;
5238 }
5239
5240 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5241 return 0;
5242
5243 err_out:
5244 rtl8169_rx_clear(tp);
5245 return -ENOMEM;
5246 }
5247
5248 static int rtl8169_init_ring(struct rtl8169_private *tp)
5249 {
5250 rtl8169_init_ring_indexes(tp);
5251
5252 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5253 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5254
5255 return rtl8169_rx_fill(tp);
5256 }
5257
5258 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5259 struct TxDesc *desc)
5260 {
5261 unsigned int len = tx_skb->len;
5262
5263 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5264
5265 desc->opts1 = 0x00;
5266 desc->opts2 = 0x00;
5267 desc->addr = 0x00;
5268 tx_skb->len = 0;
5269 }
5270
5271 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5272 unsigned int n)
5273 {
5274 unsigned int i;
5275
5276 for (i = 0; i < n; i++) {
5277 unsigned int entry = (start + i) % NUM_TX_DESC;
5278 struct ring_info *tx_skb = tp->tx_skb + entry;
5279 unsigned int len = tx_skb->len;
5280
5281 if (len) {
5282 struct sk_buff *skb = tx_skb->skb;
5283
5284 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5285 tp->TxDescArray + entry);
5286 if (skb) {
5287 dev_consume_skb_any(skb);
5288 tx_skb->skb = NULL;
5289 }
5290 }
5291 }
5292 }
5293
5294 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5295 {
5296 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5297 tp->cur_tx = tp->dirty_tx = 0;
5298 netdev_reset_queue(tp->dev);
5299 }
5300
5301 static void rtl_reset_work(struct rtl8169_private *tp)
5302 {
5303 struct net_device *dev = tp->dev;
5304 int i;
5305
5306 napi_disable(&tp->napi);
5307 netif_stop_queue(dev);
5308 synchronize_rcu();
5309
5310 rtl8169_hw_reset(tp);
5311
5312 for (i = 0; i < NUM_RX_DESC; i++)
5313 rtl8169_mark_to_asic(tp->RxDescArray + i);
5314
5315 rtl8169_tx_clear(tp);
5316 rtl8169_init_ring_indexes(tp);
5317
5318 napi_enable(&tp->napi);
5319 rtl_hw_start(tp);
5320 netif_wake_queue(dev);
5321 }
5322
5323 static void rtl8169_tx_timeout(struct net_device *dev)
5324 {
5325 struct rtl8169_private *tp = netdev_priv(dev);
5326
5327 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5328 }
5329
5330 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5331 {
5332 u32 status = opts0 | len;
5333
5334 if (entry == NUM_TX_DESC - 1)
5335 status |= RingEnd;
5336
5337 return cpu_to_le32(status);
5338 }
5339
5340 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5341 u32 *opts)
5342 {
5343 struct skb_shared_info *info = skb_shinfo(skb);
5344 unsigned int cur_frag, entry;
5345 struct TxDesc *uninitialized_var(txd);
5346 struct device *d = tp_to_dev(tp);
5347
5348 entry = tp->cur_tx;
5349 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5350 const skb_frag_t *frag = info->frags + cur_frag;
5351 dma_addr_t mapping;
5352 u32 len;
5353 void *addr;
5354
5355 entry = (entry + 1) % NUM_TX_DESC;
5356
5357 txd = tp->TxDescArray + entry;
5358 len = skb_frag_size(frag);
5359 addr = skb_frag_address(frag);
5360 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5361 if (unlikely(dma_mapping_error(d, mapping))) {
5362 if (net_ratelimit())
5363 netif_err(tp, drv, tp->dev,
5364 "Failed to map TX fragments DMA!\n");
5365 goto err_out;
5366 }
5367
5368 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5369 txd->opts2 = cpu_to_le32(opts[1]);
5370 txd->addr = cpu_to_le64(mapping);
5371
5372 tp->tx_skb[entry].len = len;
5373 }
5374
5375 if (cur_frag) {
5376 tp->tx_skb[entry].skb = skb;
5377 txd->opts1 |= cpu_to_le32(LastFrag);
5378 }
5379
5380 return cur_frag;
5381
5382 err_out:
5383 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5384 return -EIO;
5385 }
5386
5387 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5388 {
5389 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5390 }
5391
5392 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5393 struct net_device *dev);
5394 /* r8169_csum_workaround()
5395 * The hw limites the value the transport offset. When the offset is out of the
5396 * range, calculate the checksum by sw.
5397 */
5398 static void r8169_csum_workaround(struct rtl8169_private *tp,
5399 struct sk_buff *skb)
5400 {
5401 if (skb_is_gso(skb)) {
5402 netdev_features_t features = tp->dev->features;
5403 struct sk_buff *segs, *nskb;
5404
5405 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5406 segs = skb_gso_segment(skb, features);
5407 if (IS_ERR(segs) || !segs)
5408 goto drop;
5409
5410 do {
5411 nskb = segs;
5412 segs = segs->next;
5413 nskb->next = NULL;
5414 rtl8169_start_xmit(nskb, tp->dev);
5415 } while (segs);
5416
5417 dev_consume_skb_any(skb);
5418 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5419 if (skb_checksum_help(skb) < 0)
5420 goto drop;
5421
5422 rtl8169_start_xmit(skb, tp->dev);
5423 } else {
5424 drop:
5425 tp->dev->stats.tx_dropped++;
5426 dev_kfree_skb_any(skb);
5427 }
5428 }
5429
5430 /* msdn_giant_send_check()
5431 * According to the document of microsoft, the TCP Pseudo Header excludes the
5432 * packet length for IPv6 TCP large packets.
5433 */
5434 static int msdn_giant_send_check(struct sk_buff *skb)
5435 {
5436 const struct ipv6hdr *ipv6h;
5437 struct tcphdr *th;
5438 int ret;
5439
5440 ret = skb_cow_head(skb, 0);
5441 if (ret)
5442 return ret;
5443
5444 ipv6h = ipv6_hdr(skb);
5445 th = tcp_hdr(skb);
5446
5447 th->check = 0;
5448 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5449
5450 return ret;
5451 }
5452
5453 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
5454 {
5455 u32 mss = skb_shinfo(skb)->gso_size;
5456
5457 if (mss) {
5458 opts[0] |= TD_LSO;
5459 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5460 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5461 const struct iphdr *ip = ip_hdr(skb);
5462
5463 if (ip->protocol == IPPROTO_TCP)
5464 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5465 else if (ip->protocol == IPPROTO_UDP)
5466 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5467 else
5468 WARN_ON_ONCE(1);
5469 }
5470 }
5471
5472 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5473 struct sk_buff *skb, u32 *opts)
5474 {
5475 u32 transport_offset = (u32)skb_transport_offset(skb);
5476 u32 mss = skb_shinfo(skb)->gso_size;
5477
5478 if (mss) {
5479 if (transport_offset > GTTCPHO_MAX) {
5480 netif_warn(tp, tx_err, tp->dev,
5481 "Invalid transport offset 0x%x for TSO\n",
5482 transport_offset);
5483 return false;
5484 }
5485
5486 switch (vlan_get_protocol(skb)) {
5487 case htons(ETH_P_IP):
5488 opts[0] |= TD1_GTSENV4;
5489 break;
5490
5491 case htons(ETH_P_IPV6):
5492 if (msdn_giant_send_check(skb))
5493 return false;
5494
5495 opts[0] |= TD1_GTSENV6;
5496 break;
5497
5498 default:
5499 WARN_ON_ONCE(1);
5500 break;
5501 }
5502
5503 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5504 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
5505 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5506 u8 ip_protocol;
5507
5508 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5509 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
5510
5511 if (transport_offset > TCPHO_MAX) {
5512 netif_warn(tp, tx_err, tp->dev,
5513 "Invalid transport offset 0x%x\n",
5514 transport_offset);
5515 return false;
5516 }
5517
5518 switch (vlan_get_protocol(skb)) {
5519 case htons(ETH_P_IP):
5520 opts[1] |= TD1_IPv4_CS;
5521 ip_protocol = ip_hdr(skb)->protocol;
5522 break;
5523
5524 case htons(ETH_P_IPV6):
5525 opts[1] |= TD1_IPv6_CS;
5526 ip_protocol = ipv6_hdr(skb)->nexthdr;
5527 break;
5528
5529 default:
5530 ip_protocol = IPPROTO_RAW;
5531 break;
5532 }
5533
5534 if (ip_protocol == IPPROTO_TCP)
5535 opts[1] |= TD1_TCP_CS;
5536 else if (ip_protocol == IPPROTO_UDP)
5537 opts[1] |= TD1_UDP_CS;
5538 else
5539 WARN_ON_ONCE(1);
5540
5541 opts[1] |= transport_offset << TCPHO_SHIFT;
5542 } else {
5543 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5544 return !eth_skb_pad(skb);
5545 }
5546
5547 return true;
5548 }
5549
5550 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
5551 unsigned int nr_frags)
5552 {
5553 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
5554
5555 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
5556 return slots_avail > nr_frags;
5557 }
5558
5559 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
5560 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
5561 {
5562 switch (tp->mac_version) {
5563 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5564 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
5565 return false;
5566 default:
5567 return true;
5568 }
5569 }
5570
5571 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5572 struct net_device *dev)
5573 {
5574 struct rtl8169_private *tp = netdev_priv(dev);
5575 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5576 struct TxDesc *txd = tp->TxDescArray + entry;
5577 struct device *d = tp_to_dev(tp);
5578 dma_addr_t mapping;
5579 u32 opts[2], len;
5580 int frags;
5581
5582 if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
5583 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5584 goto err_stop_0;
5585 }
5586
5587 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5588 goto err_stop_0;
5589
5590 opts[1] = rtl8169_tx_vlan_tag(skb);
5591 opts[0] = DescOwn;
5592
5593 if (rtl_chip_supports_csum_v2(tp)) {
5594 if (!rtl8169_tso_csum_v2(tp, skb, opts)) {
5595 r8169_csum_workaround(tp, skb);
5596 return NETDEV_TX_OK;
5597 }
5598 } else {
5599 rtl8169_tso_csum_v1(skb, opts);
5600 }
5601
5602 len = skb_headlen(skb);
5603 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5604 if (unlikely(dma_mapping_error(d, mapping))) {
5605 if (net_ratelimit())
5606 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5607 goto err_dma_0;
5608 }
5609
5610 tp->tx_skb[entry].len = len;
5611 txd->addr = cpu_to_le64(mapping);
5612
5613 frags = rtl8169_xmit_frags(tp, skb, opts);
5614 if (frags < 0)
5615 goto err_dma_1;
5616 else if (frags)
5617 opts[0] |= FirstFrag;
5618 else {
5619 opts[0] |= FirstFrag | LastFrag;
5620 tp->tx_skb[entry].skb = skb;
5621 }
5622
5623 txd->opts2 = cpu_to_le32(opts[1]);
5624
5625 netdev_sent_queue(dev, skb->len);
5626
5627 skb_tx_timestamp(skb);
5628
5629 /* Force memory writes to complete before releasing descriptor */
5630 dma_wmb();
5631
5632 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5633
5634 /* Force all memory writes to complete before notifying device */
5635 wmb();
5636
5637 tp->cur_tx += frags + 1;
5638
5639 RTL_W8(tp, TxPoll, NPQ);
5640
5641 if (!rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
5642 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5643 * not miss a ring update when it notices a stopped queue.
5644 */
5645 smp_wmb();
5646 netif_stop_queue(dev);
5647 /* Sync with rtl_tx:
5648 * - publish queue status and cur_tx ring index (write barrier)
5649 * - refresh dirty_tx ring index (read barrier).
5650 * May the current thread have a pessimistic view of the ring
5651 * status and forget to wake up queue, a racing rtl_tx thread
5652 * can't.
5653 */
5654 smp_mb();
5655 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
5656 netif_start_queue(dev);
5657 }
5658
5659 return NETDEV_TX_OK;
5660
5661 err_dma_1:
5662 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5663 err_dma_0:
5664 dev_kfree_skb_any(skb);
5665 dev->stats.tx_dropped++;
5666 return NETDEV_TX_OK;
5667
5668 err_stop_0:
5669 netif_stop_queue(dev);
5670 dev->stats.tx_dropped++;
5671 return NETDEV_TX_BUSY;
5672 }
5673
5674 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5675 {
5676 struct rtl8169_private *tp = netdev_priv(dev);
5677 struct pci_dev *pdev = tp->pci_dev;
5678 u16 pci_status, pci_cmd;
5679
5680 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5681 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5682
5683 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5684 pci_cmd, pci_status);
5685
5686 /*
5687 * The recovery sequence below admits a very elaborated explanation:
5688 * - it seems to work;
5689 * - I did not see what else could be done;
5690 * - it makes iop3xx happy.
5691 *
5692 * Feel free to adjust to your needs.
5693 */
5694 if (pdev->broken_parity_status)
5695 pci_cmd &= ~PCI_COMMAND_PARITY;
5696 else
5697 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5698
5699 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5700
5701 pci_write_config_word(pdev, PCI_STATUS,
5702 pci_status & (PCI_STATUS_DETECTED_PARITY |
5703 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5704 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5705
5706 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5707 }
5708
5709 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
5710 int budget)
5711 {
5712 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
5713
5714 dirty_tx = tp->dirty_tx;
5715 smp_rmb();
5716 tx_left = tp->cur_tx - dirty_tx;
5717
5718 while (tx_left > 0) {
5719 unsigned int entry = dirty_tx % NUM_TX_DESC;
5720 struct ring_info *tx_skb = tp->tx_skb + entry;
5721 u32 status;
5722
5723 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5724 if (status & DescOwn)
5725 break;
5726
5727 /* This barrier is needed to keep us from reading
5728 * any other fields out of the Tx descriptor until
5729 * we know the status of DescOwn
5730 */
5731 dma_rmb();
5732
5733 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5734 tp->TxDescArray + entry);
5735 if (status & LastFrag) {
5736 pkts_compl++;
5737 bytes_compl += tx_skb->skb->len;
5738 napi_consume_skb(tx_skb->skb, budget);
5739 tx_skb->skb = NULL;
5740 }
5741 dirty_tx++;
5742 tx_left--;
5743 }
5744
5745 if (tp->dirty_tx != dirty_tx) {
5746 netdev_completed_queue(dev, pkts_compl, bytes_compl);
5747
5748 u64_stats_update_begin(&tp->tx_stats.syncp);
5749 tp->tx_stats.packets += pkts_compl;
5750 tp->tx_stats.bytes += bytes_compl;
5751 u64_stats_update_end(&tp->tx_stats.syncp);
5752
5753 tp->dirty_tx = dirty_tx;
5754 /* Sync with rtl8169_start_xmit:
5755 * - publish dirty_tx ring index (write barrier)
5756 * - refresh cur_tx ring index and queue status (read barrier)
5757 * May the current thread miss the stopped queue condition,
5758 * a racing xmit thread can only have a right view of the
5759 * ring status.
5760 */
5761 smp_mb();
5762 if (netif_queue_stopped(dev) &&
5763 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
5764 netif_wake_queue(dev);
5765 }
5766 /*
5767 * 8168 hack: TxPoll requests are lost when the Tx packets are
5768 * too close. Let's kick an extra TxPoll request when a burst
5769 * of start_xmit activity is detected (if it is not detected,
5770 * it is slow enough). -- FR
5771 */
5772 if (tp->cur_tx != dirty_tx)
5773 RTL_W8(tp, TxPoll, NPQ);
5774 }
5775 }
5776
5777 static inline int rtl8169_fragmented_frame(u32 status)
5778 {
5779 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5780 }
5781
5782 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5783 {
5784 u32 status = opts1 & RxProtoMask;
5785
5786 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5787 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5788 skb->ip_summed = CHECKSUM_UNNECESSARY;
5789 else
5790 skb_checksum_none_assert(skb);
5791 }
5792
5793 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5794 struct rtl8169_private *tp,
5795 int pkt_size,
5796 dma_addr_t addr)
5797 {
5798 struct sk_buff *skb;
5799 struct device *d = tp_to_dev(tp);
5800
5801 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5802 prefetch(data);
5803 skb = napi_alloc_skb(&tp->napi, pkt_size);
5804 if (skb)
5805 skb_copy_to_linear_data(skb, data, pkt_size);
5806 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5807
5808 return skb;
5809 }
5810
5811 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5812 {
5813 unsigned int cur_rx, rx_left;
5814 unsigned int count;
5815
5816 cur_rx = tp->cur_rx;
5817
5818 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
5819 unsigned int entry = cur_rx % NUM_RX_DESC;
5820 struct RxDesc *desc = tp->RxDescArray + entry;
5821 u32 status;
5822
5823 status = le32_to_cpu(desc->opts1);
5824 if (status & DescOwn)
5825 break;
5826
5827 /* This barrier is needed to keep us from reading
5828 * any other fields out of the Rx descriptor until
5829 * we know the status of DescOwn
5830 */
5831 dma_rmb();
5832
5833 if (unlikely(status & RxRES)) {
5834 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5835 status);
5836 dev->stats.rx_errors++;
5837 if (status & (RxRWT | RxRUNT))
5838 dev->stats.rx_length_errors++;
5839 if (status & RxCRC)
5840 dev->stats.rx_crc_errors++;
5841 if (status & (RxRUNT | RxCRC) && !(status & RxRWT) &&
5842 dev->features & NETIF_F_RXALL) {
5843 goto process_pkt;
5844 }
5845 } else {
5846 struct sk_buff *skb;
5847 dma_addr_t addr;
5848 int pkt_size;
5849
5850 process_pkt:
5851 addr = le64_to_cpu(desc->addr);
5852 if (likely(!(dev->features & NETIF_F_RXFCS)))
5853 pkt_size = (status & 0x00003fff) - 4;
5854 else
5855 pkt_size = status & 0x00003fff;
5856
5857 /*
5858 * The driver does not support incoming fragmented
5859 * frames. They are seen as a symptom of over-mtu
5860 * sized frames.
5861 */
5862 if (unlikely(rtl8169_fragmented_frame(status))) {
5863 dev->stats.rx_dropped++;
5864 dev->stats.rx_length_errors++;
5865 goto release_descriptor;
5866 }
5867
5868 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5869 tp, pkt_size, addr);
5870 if (!skb) {
5871 dev->stats.rx_dropped++;
5872 goto release_descriptor;
5873 }
5874
5875 rtl8169_rx_csum(skb, status);
5876 skb_put(skb, pkt_size);
5877 skb->protocol = eth_type_trans(skb, dev);
5878
5879 rtl8169_rx_vlan_tag(desc, skb);
5880
5881 if (skb->pkt_type == PACKET_MULTICAST)
5882 dev->stats.multicast++;
5883
5884 napi_gro_receive(&tp->napi, skb);
5885
5886 u64_stats_update_begin(&tp->rx_stats.syncp);
5887 tp->rx_stats.packets++;
5888 tp->rx_stats.bytes += pkt_size;
5889 u64_stats_update_end(&tp->rx_stats.syncp);
5890 }
5891 release_descriptor:
5892 desc->opts2 = 0;
5893 rtl8169_mark_to_asic(desc);
5894 }
5895
5896 count = cur_rx - tp->cur_rx;
5897 tp->cur_rx = cur_rx;
5898
5899 return count;
5900 }
5901
5902 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5903 {
5904 struct rtl8169_private *tp = dev_instance;
5905 u16 status = RTL_R16(tp, IntrStatus);
5906
5907 if (!tp->irq_enabled || status == 0xffff || !(status & tp->irq_mask))
5908 return IRQ_NONE;
5909
5910 if (unlikely(status & SYSErr)) {
5911 rtl8169_pcierr_interrupt(tp->dev);
5912 goto out;
5913 }
5914
5915 if (status & LinkChg)
5916 phy_mac_interrupt(tp->phydev);
5917
5918 if (unlikely(status & RxFIFOOver &&
5919 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
5920 netif_stop_queue(tp->dev);
5921 /* XXX - Hack alert. See rtl_task(). */
5922 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
5923 }
5924
5925 rtl_irq_disable(tp);
5926 napi_schedule_irqoff(&tp->napi);
5927 out:
5928 rtl_ack_events(tp, status);
5929
5930 return IRQ_HANDLED;
5931 }
5932
5933 static void rtl_task(struct work_struct *work)
5934 {
5935 static const struct {
5936 int bitnr;
5937 void (*action)(struct rtl8169_private *);
5938 } rtl_work[] = {
5939 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
5940 };
5941 struct rtl8169_private *tp =
5942 container_of(work, struct rtl8169_private, wk.work);
5943 struct net_device *dev = tp->dev;
5944 int i;
5945
5946 rtl_lock_work(tp);
5947
5948 if (!netif_running(dev) ||
5949 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
5950 goto out_unlock;
5951
5952 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
5953 bool pending;
5954
5955 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
5956 if (pending)
5957 rtl_work[i].action(tp);
5958 }
5959
5960 out_unlock:
5961 rtl_unlock_work(tp);
5962 }
5963
5964 static int rtl8169_poll(struct napi_struct *napi, int budget)
5965 {
5966 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5967 struct net_device *dev = tp->dev;
5968 int work_done;
5969
5970 work_done = rtl_rx(dev, tp, (u32) budget);
5971
5972 rtl_tx(dev, tp, budget);
5973
5974 if (work_done < budget) {
5975 napi_complete_done(napi, work_done);
5976 rtl_irq_enable(tp);
5977 }
5978
5979 return work_done;
5980 }
5981
5982 static void rtl8169_rx_missed(struct net_device *dev)
5983 {
5984 struct rtl8169_private *tp = netdev_priv(dev);
5985
5986 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5987 return;
5988
5989 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
5990 RTL_W32(tp, RxMissed, 0);
5991 }
5992
5993 static void r8169_phylink_handler(struct net_device *ndev)
5994 {
5995 struct rtl8169_private *tp = netdev_priv(ndev);
5996
5997 if (netif_carrier_ok(ndev)) {
5998 rtl_link_chg_patch(tp);
5999 pm_request_resume(&tp->pci_dev->dev);
6000 } else {
6001 pm_runtime_idle(&tp->pci_dev->dev);
6002 }
6003
6004 if (net_ratelimit())
6005 phy_print_status(tp->phydev);
6006 }
6007
6008 static int r8169_phy_connect(struct rtl8169_private *tp)
6009 {
6010 struct phy_device *phydev = tp->phydev;
6011 phy_interface_t phy_mode;
6012 int ret;
6013
6014 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6015 PHY_INTERFACE_MODE_MII;
6016
6017 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6018 phy_mode);
6019 if (ret)
6020 return ret;
6021
6022 if (tp->supports_gmii)
6023 phy_remove_link_mode(phydev,
6024 ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
6025 else
6026 phy_set_max_speed(phydev, SPEED_100);
6027
6028 phy_support_asym_pause(phydev);
6029
6030 phy_attached_info(phydev);
6031
6032 return 0;
6033 }
6034
6035 static void rtl8169_down(struct net_device *dev)
6036 {
6037 struct rtl8169_private *tp = netdev_priv(dev);
6038
6039 phy_stop(tp->phydev);
6040
6041 napi_disable(&tp->napi);
6042 netif_stop_queue(dev);
6043
6044 rtl8169_hw_reset(tp);
6045 /*
6046 * At this point device interrupts can not be enabled in any function,
6047 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6048 * and napi is disabled (rtl8169_poll).
6049 */
6050 rtl8169_rx_missed(dev);
6051
6052 /* Give a racing hard_start_xmit a few cycles to complete. */
6053 synchronize_rcu();
6054
6055 rtl8169_tx_clear(tp);
6056
6057 rtl8169_rx_clear(tp);
6058
6059 rtl_pll_power_down(tp);
6060 }
6061
6062 static int rtl8169_close(struct net_device *dev)
6063 {
6064 struct rtl8169_private *tp = netdev_priv(dev);
6065 struct pci_dev *pdev = tp->pci_dev;
6066
6067 pm_runtime_get_sync(&pdev->dev);
6068
6069 /* Update counters before going down */
6070 rtl8169_update_counters(tp);
6071
6072 rtl_lock_work(tp);
6073 /* Clear all task flags */
6074 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6075
6076 rtl8169_down(dev);
6077 rtl_unlock_work(tp);
6078
6079 cancel_work_sync(&tp->wk.work);
6080
6081 phy_disconnect(tp->phydev);
6082
6083 pci_free_irq(pdev, 0, tp);
6084
6085 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6086 tp->RxPhyAddr);
6087 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6088 tp->TxPhyAddr);
6089 tp->TxDescArray = NULL;
6090 tp->RxDescArray = NULL;
6091
6092 pm_runtime_put_sync(&pdev->dev);
6093
6094 return 0;
6095 }
6096
6097 #ifdef CONFIG_NET_POLL_CONTROLLER
6098 static void rtl8169_netpoll(struct net_device *dev)
6099 {
6100 struct rtl8169_private *tp = netdev_priv(dev);
6101
6102 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6103 }
6104 #endif
6105
6106 static int rtl_open(struct net_device *dev)
6107 {
6108 struct rtl8169_private *tp = netdev_priv(dev);
6109 struct pci_dev *pdev = tp->pci_dev;
6110 int retval = -ENOMEM;
6111
6112 pm_runtime_get_sync(&pdev->dev);
6113
6114 /*
6115 * Rx and Tx descriptors needs 256 bytes alignment.
6116 * dma_alloc_coherent provides more.
6117 */
6118 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6119 &tp->TxPhyAddr, GFP_KERNEL);
6120 if (!tp->TxDescArray)
6121 goto err_pm_runtime_put;
6122
6123 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6124 &tp->RxPhyAddr, GFP_KERNEL);
6125 if (!tp->RxDescArray)
6126 goto err_free_tx_0;
6127
6128 retval = rtl8169_init_ring(tp);
6129 if (retval < 0)
6130 goto err_free_rx_1;
6131
6132 rtl_request_firmware(tp);
6133
6134 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6135 dev->name);
6136 if (retval < 0)
6137 goto err_release_fw_2;
6138
6139 retval = r8169_phy_connect(tp);
6140 if (retval)
6141 goto err_free_irq;
6142
6143 rtl_lock_work(tp);
6144
6145 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6146
6147 napi_enable(&tp->napi);
6148
6149 rtl8169_init_phy(dev, tp);
6150
6151 rtl_pll_power_up(tp);
6152
6153 rtl_hw_start(tp);
6154
6155 if (!rtl8169_init_counter_offsets(tp))
6156 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6157
6158 phy_start(tp->phydev);
6159 netif_start_queue(dev);
6160
6161 rtl_unlock_work(tp);
6162
6163 pm_runtime_put_sync(&pdev->dev);
6164 out:
6165 return retval;
6166
6167 err_free_irq:
6168 pci_free_irq(pdev, 0, tp);
6169 err_release_fw_2:
6170 rtl_release_firmware(tp);
6171 rtl8169_rx_clear(tp);
6172 err_free_rx_1:
6173 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6174 tp->RxPhyAddr);
6175 tp->RxDescArray = NULL;
6176 err_free_tx_0:
6177 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6178 tp->TxPhyAddr);
6179 tp->TxDescArray = NULL;
6180 err_pm_runtime_put:
6181 pm_runtime_put_noidle(&pdev->dev);
6182 goto out;
6183 }
6184
6185 static void
6186 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6187 {
6188 struct rtl8169_private *tp = netdev_priv(dev);
6189 struct pci_dev *pdev = tp->pci_dev;
6190 struct rtl8169_counters *counters = tp->counters;
6191 unsigned int start;
6192
6193 pm_runtime_get_noresume(&pdev->dev);
6194
6195 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6196 rtl8169_rx_missed(dev);
6197
6198 do {
6199 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6200 stats->rx_packets = tp->rx_stats.packets;
6201 stats->rx_bytes = tp->rx_stats.bytes;
6202 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6203
6204 do {
6205 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6206 stats->tx_packets = tp->tx_stats.packets;
6207 stats->tx_bytes = tp->tx_stats.bytes;
6208 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6209
6210 stats->rx_dropped = dev->stats.rx_dropped;
6211 stats->tx_dropped = dev->stats.tx_dropped;
6212 stats->rx_length_errors = dev->stats.rx_length_errors;
6213 stats->rx_errors = dev->stats.rx_errors;
6214 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6215 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6216 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6217 stats->multicast = dev->stats.multicast;
6218
6219 /*
6220 * Fetch additonal counter values missing in stats collected by driver
6221 * from tally counters.
6222 */
6223 if (pm_runtime_active(&pdev->dev))
6224 rtl8169_update_counters(tp);
6225
6226 /*
6227 * Subtract values fetched during initalization.
6228 * See rtl8169_init_counter_offsets for a description why we do that.
6229 */
6230 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6231 le64_to_cpu(tp->tc_offset.tx_errors);
6232 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6233 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6234 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6235 le16_to_cpu(tp->tc_offset.tx_aborted);
6236
6237 pm_runtime_put_noidle(&pdev->dev);
6238 }
6239
6240 static void rtl8169_net_suspend(struct net_device *dev)
6241 {
6242 struct rtl8169_private *tp = netdev_priv(dev);
6243
6244 if (!netif_running(dev))
6245 return;
6246
6247 phy_stop(tp->phydev);
6248 netif_device_detach(dev);
6249
6250 rtl_lock_work(tp);
6251 napi_disable(&tp->napi);
6252 /* Clear all task flags */
6253 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6254
6255 rtl_unlock_work(tp);
6256
6257 rtl_pll_power_down(tp);
6258 }
6259
6260 #ifdef CONFIG_PM
6261
6262 static int rtl8169_suspend(struct device *device)
6263 {
6264 struct net_device *dev = dev_get_drvdata(device);
6265 struct rtl8169_private *tp = netdev_priv(dev);
6266
6267 rtl8169_net_suspend(dev);
6268 clk_disable_unprepare(tp->clk);
6269
6270 return 0;
6271 }
6272
6273 static void __rtl8169_resume(struct net_device *dev)
6274 {
6275 struct rtl8169_private *tp = netdev_priv(dev);
6276
6277 netif_device_attach(dev);
6278
6279 rtl_pll_power_up(tp);
6280 rtl8169_init_phy(dev, tp);
6281
6282 phy_start(tp->phydev);
6283
6284 rtl_lock_work(tp);
6285 napi_enable(&tp->napi);
6286 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6287 rtl_reset_work(tp);
6288 rtl_unlock_work(tp);
6289 }
6290
6291 static int rtl8169_resume(struct device *device)
6292 {
6293 struct net_device *dev = dev_get_drvdata(device);
6294 struct rtl8169_private *tp = netdev_priv(dev);
6295
6296 rtl_rar_set(tp, dev->dev_addr);
6297
6298 clk_prepare_enable(tp->clk);
6299
6300 if (netif_running(dev))
6301 __rtl8169_resume(dev);
6302
6303 return 0;
6304 }
6305
6306 static int rtl8169_runtime_suspend(struct device *device)
6307 {
6308 struct net_device *dev = dev_get_drvdata(device);
6309 struct rtl8169_private *tp = netdev_priv(dev);
6310
6311 if (!tp->TxDescArray)
6312 return 0;
6313
6314 rtl_lock_work(tp);
6315 __rtl8169_set_wol(tp, WAKE_ANY);
6316 rtl_unlock_work(tp);
6317
6318 rtl8169_net_suspend(dev);
6319
6320 /* Update counters before going runtime suspend */
6321 rtl8169_rx_missed(dev);
6322 rtl8169_update_counters(tp);
6323
6324 return 0;
6325 }
6326
6327 static int rtl8169_runtime_resume(struct device *device)
6328 {
6329 struct net_device *dev = dev_get_drvdata(device);
6330 struct rtl8169_private *tp = netdev_priv(dev);
6331
6332 rtl_rar_set(tp, dev->dev_addr);
6333
6334 if (!tp->TxDescArray)
6335 return 0;
6336
6337 rtl_lock_work(tp);
6338 __rtl8169_set_wol(tp, tp->saved_wolopts);
6339 rtl_unlock_work(tp);
6340
6341 __rtl8169_resume(dev);
6342
6343 return 0;
6344 }
6345
6346 static int rtl8169_runtime_idle(struct device *device)
6347 {
6348 struct net_device *dev = dev_get_drvdata(device);
6349
6350 if (!netif_running(dev) || !netif_carrier_ok(dev))
6351 pm_schedule_suspend(device, 10000);
6352
6353 return -EBUSY;
6354 }
6355
6356 static const struct dev_pm_ops rtl8169_pm_ops = {
6357 .suspend = rtl8169_suspend,
6358 .resume = rtl8169_resume,
6359 .freeze = rtl8169_suspend,
6360 .thaw = rtl8169_resume,
6361 .poweroff = rtl8169_suspend,
6362 .restore = rtl8169_resume,
6363 .runtime_suspend = rtl8169_runtime_suspend,
6364 .runtime_resume = rtl8169_runtime_resume,
6365 .runtime_idle = rtl8169_runtime_idle,
6366 };
6367
6368 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
6369
6370 #else /* !CONFIG_PM */
6371
6372 #define RTL8169_PM_OPS NULL
6373
6374 #endif /* !CONFIG_PM */
6375
6376 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6377 {
6378 /* WoL fails with 8168b when the receiver is disabled. */
6379 switch (tp->mac_version) {
6380 case RTL_GIGA_MAC_VER_11:
6381 case RTL_GIGA_MAC_VER_12:
6382 case RTL_GIGA_MAC_VER_17:
6383 pci_clear_master(tp->pci_dev);
6384
6385 RTL_W8(tp, ChipCmd, CmdRxEnb);
6386 /* PCI commit */
6387 RTL_R8(tp, ChipCmd);
6388 break;
6389 default:
6390 break;
6391 }
6392 }
6393
6394 static void rtl_shutdown(struct pci_dev *pdev)
6395 {
6396 struct net_device *dev = pci_get_drvdata(pdev);
6397 struct rtl8169_private *tp = netdev_priv(dev);
6398
6399 rtl8169_net_suspend(dev);
6400
6401 /* Restore original MAC address */
6402 rtl_rar_set(tp, dev->perm_addr);
6403
6404 rtl8169_hw_reset(tp);
6405
6406 if (system_state == SYSTEM_POWER_OFF) {
6407 if (tp->saved_wolopts) {
6408 rtl_wol_suspend_quirk(tp);
6409 rtl_wol_shutdown_quirk(tp);
6410 }
6411
6412 pci_wake_from_d3(pdev, true);
6413 pci_set_power_state(pdev, PCI_D3hot);
6414 }
6415 }
6416
6417 static void rtl_remove_one(struct pci_dev *pdev)
6418 {
6419 struct net_device *dev = pci_get_drvdata(pdev);
6420 struct rtl8169_private *tp = netdev_priv(dev);
6421
6422 if (r8168_check_dash(tp))
6423 rtl8168_driver_stop(tp);
6424
6425 netif_napi_del(&tp->napi);
6426
6427 unregister_netdev(dev);
6428 mdiobus_unregister(tp->phydev->mdio.bus);
6429
6430 rtl_release_firmware(tp);
6431
6432 if (pci_dev_run_wake(pdev))
6433 pm_runtime_get_noresume(&pdev->dev);
6434
6435 /* restore original MAC address */
6436 rtl_rar_set(tp, dev->perm_addr);
6437 }
6438
6439 static const struct net_device_ops rtl_netdev_ops = {
6440 .ndo_open = rtl_open,
6441 .ndo_stop = rtl8169_close,
6442 .ndo_get_stats64 = rtl8169_get_stats64,
6443 .ndo_start_xmit = rtl8169_start_xmit,
6444 .ndo_tx_timeout = rtl8169_tx_timeout,
6445 .ndo_validate_addr = eth_validate_addr,
6446 .ndo_change_mtu = rtl8169_change_mtu,
6447 .ndo_fix_features = rtl8169_fix_features,
6448 .ndo_set_features = rtl8169_set_features,
6449 .ndo_set_mac_address = rtl_set_mac_address,
6450 .ndo_do_ioctl = rtl8169_ioctl,
6451 .ndo_set_rx_mode = rtl_set_rx_mode,
6452 #ifdef CONFIG_NET_POLL_CONTROLLER
6453 .ndo_poll_controller = rtl8169_netpoll,
6454 #endif
6455
6456 };
6457
6458 static void rtl_set_irq_mask(struct rtl8169_private *tp)
6459 {
6460 tp->irq_mask = RTL_EVENT_NAPI | LinkChg;
6461
6462 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6463 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
6464 else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
6465 /* special workaround needed */
6466 tp->irq_mask |= RxFIFOOver;
6467 else
6468 tp->irq_mask |= RxOverflow;
6469 }
6470
6471 static int rtl_alloc_irq(struct rtl8169_private *tp)
6472 {
6473 unsigned int flags;
6474
6475 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
6476 rtl_unlock_config_regs(tp);
6477 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
6478 rtl_lock_config_regs(tp);
6479 flags = PCI_IRQ_LEGACY;
6480 } else {
6481 flags = PCI_IRQ_ALL_TYPES;
6482 }
6483
6484 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
6485 }
6486
6487 static void rtl_read_mac_address(struct rtl8169_private *tp,
6488 u8 mac_addr[ETH_ALEN])
6489 {
6490 u32 value;
6491
6492 /* Get MAC address */
6493 switch (tp->mac_version) {
6494 case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
6495 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
6496 value = rtl_eri_read(tp, 0xe0);
6497 mac_addr[0] = (value >> 0) & 0xff;
6498 mac_addr[1] = (value >> 8) & 0xff;
6499 mac_addr[2] = (value >> 16) & 0xff;
6500 mac_addr[3] = (value >> 24) & 0xff;
6501
6502 value = rtl_eri_read(tp, 0xe4);
6503 mac_addr[4] = (value >> 0) & 0xff;
6504 mac_addr[5] = (value >> 8) & 0xff;
6505 break;
6506 default:
6507 break;
6508 }
6509 }
6510
6511 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6512 {
6513 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
6514 }
6515
6516 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6517 {
6518 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6519 }
6520
6521 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
6522 {
6523 struct rtl8169_private *tp = mii_bus->priv;
6524
6525 if (phyaddr > 0)
6526 return -ENODEV;
6527
6528 return rtl_readphy(tp, phyreg);
6529 }
6530
6531 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
6532 int phyreg, u16 val)
6533 {
6534 struct rtl8169_private *tp = mii_bus->priv;
6535
6536 if (phyaddr > 0)
6537 return -ENODEV;
6538
6539 rtl_writephy(tp, phyreg, val);
6540
6541 return 0;
6542 }
6543
6544 static int r8169_mdio_register(struct rtl8169_private *tp)
6545 {
6546 struct pci_dev *pdev = tp->pci_dev;
6547 struct mii_bus *new_bus;
6548 int ret;
6549
6550 new_bus = devm_mdiobus_alloc(&pdev->dev);
6551 if (!new_bus)
6552 return -ENOMEM;
6553
6554 new_bus->name = "r8169";
6555 new_bus->priv = tp;
6556 new_bus->parent = &pdev->dev;
6557 new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
6558 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
6559
6560 new_bus->read = r8169_mdio_read_reg;
6561 new_bus->write = r8169_mdio_write_reg;
6562
6563 ret = mdiobus_register(new_bus);
6564 if (ret)
6565 return ret;
6566
6567 tp->phydev = mdiobus_get_phy(new_bus, 0);
6568 if (!tp->phydev) {
6569 mdiobus_unregister(new_bus);
6570 return -ENODEV;
6571 }
6572
6573 /* PHY will be woken up in rtl_open() */
6574 phy_suspend(tp->phydev);
6575
6576 return 0;
6577 }
6578
6579 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6580 {
6581 u32 data;
6582
6583 tp->ocp_base = OCP_STD_PHY_BASE;
6584
6585 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
6586
6587 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6588 return;
6589
6590 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6591 return;
6592
6593 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6594 msleep(1);
6595 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6596
6597 data = r8168_mac_ocp_read(tp, 0xe8de);
6598 data &= ~(1 << 14);
6599 r8168_mac_ocp_write(tp, 0xe8de, data);
6600
6601 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6602 return;
6603
6604 data = r8168_mac_ocp_read(tp, 0xe8de);
6605 data |= (1 << 15);
6606 r8168_mac_ocp_write(tp, 0xe8de, data);
6607
6608 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
6609 }
6610
6611 static void rtl_hw_initialize(struct rtl8169_private *tp)
6612 {
6613 switch (tp->mac_version) {
6614 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
6615 rtl8168ep_stop_cmac(tp);
6616 /* fall through */
6617 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
6618 rtl_hw_init_8168g(tp);
6619 break;
6620 default:
6621 break;
6622 }
6623 }
6624
6625 static int rtl_jumbo_max(struct rtl8169_private *tp)
6626 {
6627 /* Non-GBit versions don't support jumbo frames */
6628 if (!tp->supports_gmii)
6629 return JUMBO_1K;
6630
6631 switch (tp->mac_version) {
6632 /* RTL8169 */
6633 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
6634 return JUMBO_7K;
6635 /* RTL8168b */
6636 case RTL_GIGA_MAC_VER_11:
6637 case RTL_GIGA_MAC_VER_12:
6638 case RTL_GIGA_MAC_VER_17:
6639 return JUMBO_4K;
6640 /* RTL8168c */
6641 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
6642 return JUMBO_6K;
6643 default:
6644 return JUMBO_9K;
6645 }
6646 }
6647
6648 static void rtl_disable_clk(void *data)
6649 {
6650 clk_disable_unprepare(data);
6651 }
6652
6653 static int rtl_get_ether_clk(struct rtl8169_private *tp)
6654 {
6655 struct device *d = tp_to_dev(tp);
6656 struct clk *clk;
6657 int rc;
6658
6659 clk = devm_clk_get(d, "ether_clk");
6660 if (IS_ERR(clk)) {
6661 rc = PTR_ERR(clk);
6662 if (rc == -ENOENT)
6663 /* clk-core allows NULL (for suspend / resume) */
6664 rc = 0;
6665 else if (rc != -EPROBE_DEFER)
6666 dev_err(d, "failed to get clk: %d\n", rc);
6667 } else {
6668 tp->clk = clk;
6669 rc = clk_prepare_enable(clk);
6670 if (rc)
6671 dev_err(d, "failed to enable clk: %d\n", rc);
6672 else
6673 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
6674 }
6675
6676 return rc;
6677 }
6678
6679 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6680 {
6681 /* align to u16 for is_valid_ether_addr() */
6682 u8 mac_addr[ETH_ALEN] __aligned(2) = {};
6683 struct rtl8169_private *tp;
6684 struct net_device *dev;
6685 int chipset, region, i;
6686 int jumbo_max, rc;
6687
6688 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
6689 if (!dev)
6690 return -ENOMEM;
6691
6692 SET_NETDEV_DEV(dev, &pdev->dev);
6693 dev->netdev_ops = &rtl_netdev_ops;
6694 tp = netdev_priv(dev);
6695 tp->dev = dev;
6696 tp->pci_dev = pdev;
6697 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6698 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
6699
6700 /* Get the *optional* external "ether_clk" used on some boards */
6701 rc = rtl_get_ether_clk(tp);
6702 if (rc)
6703 return rc;
6704
6705 /* Disable ASPM completely as that cause random device stop working
6706 * problems as well as full system hangs for some PCIe devices users.
6707 */
6708 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
6709
6710 /* enable device (incl. PCI PM wakeup and hotplug setup) */
6711 rc = pcim_enable_device(pdev);
6712 if (rc < 0) {
6713 dev_err(&pdev->dev, "enable failure\n");
6714 return rc;
6715 }
6716
6717 if (pcim_set_mwi(pdev) < 0)
6718 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
6719
6720 /* use first MMIO region */
6721 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
6722 if (region < 0) {
6723 dev_err(&pdev->dev, "no MMIO resource found\n");
6724 return -ENODEV;
6725 }
6726
6727 /* check for weird/broken PCI region reporting */
6728 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6729 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
6730 return -ENODEV;
6731 }
6732
6733 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
6734 if (rc < 0) {
6735 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
6736 return rc;
6737 }
6738
6739 tp->mmio_addr = pcim_iomap_table(pdev)[region];
6740
6741 /* Identify chip attached to board */
6742 rtl8169_get_mac_version(tp);
6743 if (tp->mac_version == RTL_GIGA_MAC_NONE)
6744 return -ENODEV;
6745
6746 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
6747
6748 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
6749 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
6750 dev->features |= NETIF_F_HIGHDMA;
6751 } else {
6752 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6753 if (rc < 0) {
6754 dev_err(&pdev->dev, "DMA configuration failed\n");
6755 return rc;
6756 }
6757 }
6758
6759 rtl_init_rxcfg(tp);
6760
6761 rtl8169_irq_mask_and_ack(tp);
6762
6763 rtl_hw_initialize(tp);
6764
6765 rtl_hw_reset(tp);
6766
6767 pci_set_master(pdev);
6768
6769 chipset = tp->mac_version;
6770
6771 rc = rtl_alloc_irq(tp);
6772 if (rc < 0) {
6773 dev_err(&pdev->dev, "Can't allocate interrupt\n");
6774 return rc;
6775 }
6776
6777 mutex_init(&tp->wk.mutex);
6778 INIT_WORK(&tp->wk.work, rtl_task);
6779 u64_stats_init(&tp->rx_stats.syncp);
6780 u64_stats_init(&tp->tx_stats.syncp);
6781
6782 /* get MAC address */
6783 rc = eth_platform_get_mac_address(&pdev->dev, mac_addr);
6784 if (rc)
6785 rtl_read_mac_address(tp, mac_addr);
6786
6787 if (is_valid_ether_addr(mac_addr))
6788 rtl_rar_set(tp, mac_addr);
6789
6790 for (i = 0; i < ETH_ALEN; i++)
6791 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
6792
6793 dev->ethtool_ops = &rtl8169_ethtool_ops;
6794
6795 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
6796
6797 /* don't enable SG, IP_CSUM and TSO by default - it might not work
6798 * properly for all devices */
6799 dev->features |= NETIF_F_RXCSUM |
6800 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
6801
6802 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6803 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
6804 NETIF_F_HW_VLAN_CTAG_RX;
6805 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6806 NETIF_F_HIGHDMA;
6807 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
6808
6809 tp->cp_cmd |= RxChkSum | RxVlan;
6810
6811 /*
6812 * Pretend we are using VLANs; This bypasses a nasty bug where
6813 * Interrupts stop flowing on high load on 8110SCd controllers.
6814 */
6815 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6816 /* Disallow toggling */
6817 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
6818
6819 if (rtl_chip_supports_csum_v2(tp))
6820 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
6821
6822 dev->hw_features |= NETIF_F_RXALL;
6823 dev->hw_features |= NETIF_F_RXFCS;
6824
6825 /* MTU range: 60 - hw-specific max */
6826 dev->min_mtu = ETH_ZLEN;
6827 jumbo_max = rtl_jumbo_max(tp);
6828 dev->max_mtu = jumbo_max;
6829
6830 rtl_set_irq_mask(tp);
6831
6832 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6833 tp->coalesce_info = rtl_coalesce_info_8169;
6834 else
6835 tp->coalesce_info = rtl_coalesce_info_8168_8136;
6836
6837 tp->fw_name = rtl_chip_infos[chipset].fw_name;
6838
6839 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
6840 &tp->counters_phys_addr,
6841 GFP_KERNEL);
6842 if (!tp->counters)
6843 return -ENOMEM;
6844
6845 pci_set_drvdata(pdev, dev);
6846
6847 rc = r8169_mdio_register(tp);
6848 if (rc)
6849 return rc;
6850
6851 /* chip gets powered up in rtl_open() */
6852 rtl_pll_power_down(tp);
6853
6854 rc = register_netdev(dev);
6855 if (rc)
6856 goto err_mdio_unregister;
6857
6858 netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
6859 rtl_chip_infos[chipset].name, dev->dev_addr,
6860 (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
6861 pci_irq_vector(pdev, 0));
6862
6863 if (jumbo_max > JUMBO_1K)
6864 netif_info(tp, probe, dev,
6865 "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
6866 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
6867 "ok" : "ko");
6868
6869 if (r8168_check_dash(tp))
6870 rtl8168_driver_start(tp);
6871
6872 if (pci_dev_run_wake(pdev))
6873 pm_runtime_put_sync(&pdev->dev);
6874
6875 return 0;
6876
6877 err_mdio_unregister:
6878 mdiobus_unregister(tp->phydev->mdio.bus);
6879 return rc;
6880 }
6881
6882 static struct pci_driver rtl8169_pci_driver = {
6883 .name = MODULENAME,
6884 .id_table = rtl8169_pci_tbl,
6885 .probe = rtl_init_one,
6886 .remove = rtl_remove_one,
6887 .shutdown = rtl_shutdown,
6888 .driver.pm = RTL8169_PM_OPS,
6889 };
6890
6891 module_pci_driver(rtl8169_pci_driver);
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