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r8169: don't use MSI before RTL8168d
[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / realtek / r8169_main.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 *
5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
7 * Copyright (c) a lot of people too. Please respect their work.
8 *
9 * See MAINTAINERS file for support contact information.
10 */
11
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/pci.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/ethtool.h>
20 #include <linux/phy.h>
21 #include <linux/if_vlan.h>
22 #include <linux/crc32.h>
23 #include <linux/in.h>
24 #include <linux/io.h>
25 #include <linux/ip.h>
26 #include <linux/tcp.h>
27 #include <linux/interrupt.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/prefetch.h>
31 #include <linux/pci-aspm.h>
32 #include <linux/ipv6.h>
33 #include <net/ip6_checksum.h>
34
35 #include "r8169_firmware.h"
36
37 #define MODULENAME "r8169"
38
39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
47 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
48 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
49 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
50 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
51 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
52 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
53 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
54 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
55 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
56 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
57 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
58
59 #define R8169_MSG_DEFAULT \
60 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
61
62 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
63 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
64 static const int multicast_filter_limit = 32;
65
66 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
67 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
68
69 #define R8169_REGS_SIZE 256
70 #define R8169_RX_BUF_SIZE (SZ_16K - 1)
71 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
72 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
73 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
74 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
75
76 #define RTL_CFG_NO_GBIT 1
77
78 /* write/read MMIO register */
79 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
80 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
81 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
82 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
83 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
84 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
85
86 enum mac_version {
87 /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */
88 RTL_GIGA_MAC_VER_02,
89 RTL_GIGA_MAC_VER_03,
90 RTL_GIGA_MAC_VER_04,
91 RTL_GIGA_MAC_VER_05,
92 RTL_GIGA_MAC_VER_06,
93 RTL_GIGA_MAC_VER_07,
94 RTL_GIGA_MAC_VER_08,
95 RTL_GIGA_MAC_VER_09,
96 RTL_GIGA_MAC_VER_10,
97 RTL_GIGA_MAC_VER_11,
98 RTL_GIGA_MAC_VER_12,
99 RTL_GIGA_MAC_VER_13,
100 RTL_GIGA_MAC_VER_14,
101 RTL_GIGA_MAC_VER_15,
102 RTL_GIGA_MAC_VER_16,
103 RTL_GIGA_MAC_VER_17,
104 RTL_GIGA_MAC_VER_18,
105 RTL_GIGA_MAC_VER_19,
106 RTL_GIGA_MAC_VER_20,
107 RTL_GIGA_MAC_VER_21,
108 RTL_GIGA_MAC_VER_22,
109 RTL_GIGA_MAC_VER_23,
110 RTL_GIGA_MAC_VER_24,
111 RTL_GIGA_MAC_VER_25,
112 RTL_GIGA_MAC_VER_26,
113 RTL_GIGA_MAC_VER_27,
114 RTL_GIGA_MAC_VER_28,
115 RTL_GIGA_MAC_VER_29,
116 RTL_GIGA_MAC_VER_30,
117 RTL_GIGA_MAC_VER_31,
118 RTL_GIGA_MAC_VER_32,
119 RTL_GIGA_MAC_VER_33,
120 RTL_GIGA_MAC_VER_34,
121 RTL_GIGA_MAC_VER_35,
122 RTL_GIGA_MAC_VER_36,
123 RTL_GIGA_MAC_VER_37,
124 RTL_GIGA_MAC_VER_38,
125 RTL_GIGA_MAC_VER_39,
126 RTL_GIGA_MAC_VER_40,
127 RTL_GIGA_MAC_VER_41,
128 RTL_GIGA_MAC_VER_42,
129 RTL_GIGA_MAC_VER_43,
130 RTL_GIGA_MAC_VER_44,
131 RTL_GIGA_MAC_VER_45,
132 RTL_GIGA_MAC_VER_46,
133 RTL_GIGA_MAC_VER_47,
134 RTL_GIGA_MAC_VER_48,
135 RTL_GIGA_MAC_VER_49,
136 RTL_GIGA_MAC_VER_50,
137 RTL_GIGA_MAC_VER_51,
138 RTL_GIGA_MAC_NONE
139 };
140
141 #define JUMBO_1K ETH_DATA_LEN
142 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
143 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
144 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
145 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
146
147 static const struct {
148 const char *name;
149 const char *fw_name;
150 } rtl_chip_infos[] = {
151 /* PCI devices. */
152 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
153 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
154 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
155 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
156 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
157 /* PCI-E devices. */
158 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
159 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
160 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" },
161 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
162 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
163 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
164 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" },
165 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" },
166 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" },
167 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
168 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
169 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
170 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
171 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
172 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
173 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
174 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
175 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
176 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
177 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
178 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
179 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
180 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
181 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
182 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
183 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
184 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
185 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
186 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
187 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
188 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
189 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
190 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
191 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
192 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
193 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3},
194 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2},
195 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 },
196 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
197 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
198 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
199 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
200 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
201 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
202 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
203 };
204
205 static const struct pci_device_id rtl8169_pci_tbl[] = {
206 { PCI_VDEVICE(REALTEK, 0x2502) },
207 { PCI_VDEVICE(REALTEK, 0x2600) },
208 { PCI_VDEVICE(REALTEK, 0x8129) },
209 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
210 { PCI_VDEVICE(REALTEK, 0x8161) },
211 { PCI_VDEVICE(REALTEK, 0x8167) },
212 { PCI_VDEVICE(REALTEK, 0x8168) },
213 { PCI_VDEVICE(NCUBE, 0x8168) },
214 { PCI_VDEVICE(REALTEK, 0x8169) },
215 { PCI_VENDOR_ID_DLINK, 0x4300,
216 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
217 { PCI_VDEVICE(DLINK, 0x4300) },
218 { PCI_VDEVICE(DLINK, 0x4302) },
219 { PCI_VDEVICE(AT, 0xc107) },
220 { PCI_VDEVICE(USR, 0x0116) },
221 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
222 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
223 {}
224 };
225
226 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
227
228 static struct {
229 u32 msg_enable;
230 } debug = { -1 };
231
232 enum rtl_registers {
233 MAC0 = 0, /* Ethernet hardware address. */
234 MAC4 = 4,
235 MAR0 = 8, /* Multicast filter. */
236 CounterAddrLow = 0x10,
237 CounterAddrHigh = 0x14,
238 TxDescStartAddrLow = 0x20,
239 TxDescStartAddrHigh = 0x24,
240 TxHDescStartAddrLow = 0x28,
241 TxHDescStartAddrHigh = 0x2c,
242 FLASH = 0x30,
243 ERSR = 0x36,
244 ChipCmd = 0x37,
245 TxPoll = 0x38,
246 IntrMask = 0x3c,
247 IntrStatus = 0x3e,
248
249 TxConfig = 0x40,
250 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
251 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
252
253 RxConfig = 0x44,
254 #define RX128_INT_EN (1 << 15) /* 8111c and later */
255 #define RX_MULTI_EN (1 << 14) /* 8111c only */
256 #define RXCFG_FIFO_SHIFT 13
257 /* No threshold before first PCI xfer */
258 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
259 #define RX_EARLY_OFF (1 << 11)
260 #define RXCFG_DMA_SHIFT 8
261 /* Unlimited maximum PCI burst. */
262 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
263
264 RxMissed = 0x4c,
265 Cfg9346 = 0x50,
266 Config0 = 0x51,
267 Config1 = 0x52,
268 Config2 = 0x53,
269 #define PME_SIGNAL (1 << 5) /* 8168c and later */
270
271 Config3 = 0x54,
272 Config4 = 0x55,
273 Config5 = 0x56,
274 MultiIntr = 0x5c,
275 PHYAR = 0x60,
276 PHYstatus = 0x6c,
277 RxMaxSize = 0xda,
278 CPlusCmd = 0xe0,
279 IntrMitigate = 0xe2,
280
281 #define RTL_COALESCE_MASK 0x0f
282 #define RTL_COALESCE_SHIFT 4
283 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
284 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
285
286 RxDescAddrLow = 0xe4,
287 RxDescAddrHigh = 0xe8,
288 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
289
290 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
291
292 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
293
294 #define TxPacketMax (8064 >> 7)
295 #define EarlySize 0x27
296
297 FuncEvent = 0xf0,
298 FuncEventMask = 0xf4,
299 FuncPresetState = 0xf8,
300 IBCR0 = 0xf8,
301 IBCR2 = 0xf9,
302 IBIMR0 = 0xfa,
303 IBISR0 = 0xfb,
304 FuncForceEvent = 0xfc,
305 };
306
307 enum rtl8168_8101_registers {
308 CSIDR = 0x64,
309 CSIAR = 0x68,
310 #define CSIAR_FLAG 0x80000000
311 #define CSIAR_WRITE_CMD 0x80000000
312 #define CSIAR_BYTE_ENABLE 0x0000f000
313 #define CSIAR_ADDR_MASK 0x00000fff
314 PMCH = 0x6f,
315 EPHYAR = 0x80,
316 #define EPHYAR_FLAG 0x80000000
317 #define EPHYAR_WRITE_CMD 0x80000000
318 #define EPHYAR_REG_MASK 0x1f
319 #define EPHYAR_REG_SHIFT 16
320 #define EPHYAR_DATA_MASK 0xffff
321 DLLPR = 0xd0,
322 #define PFM_EN (1 << 6)
323 #define TX_10M_PS_EN (1 << 7)
324 DBG_REG = 0xd1,
325 #define FIX_NAK_1 (1 << 4)
326 #define FIX_NAK_2 (1 << 3)
327 TWSI = 0xd2,
328 MCU = 0xd3,
329 #define NOW_IS_OOB (1 << 7)
330 #define TX_EMPTY (1 << 5)
331 #define RX_EMPTY (1 << 4)
332 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
333 #define EN_NDP (1 << 3)
334 #define EN_OOB_RESET (1 << 2)
335 #define LINK_LIST_RDY (1 << 1)
336 EFUSEAR = 0xdc,
337 #define EFUSEAR_FLAG 0x80000000
338 #define EFUSEAR_WRITE_CMD 0x80000000
339 #define EFUSEAR_READ_CMD 0x00000000
340 #define EFUSEAR_REG_MASK 0x03ff
341 #define EFUSEAR_REG_SHIFT 8
342 #define EFUSEAR_DATA_MASK 0xff
343 MISC_1 = 0xf2,
344 #define PFM_D3COLD_EN (1 << 6)
345 };
346
347 enum rtl8168_registers {
348 LED_FREQ = 0x1a,
349 EEE_LED = 0x1b,
350 ERIDR = 0x70,
351 ERIAR = 0x74,
352 #define ERIAR_FLAG 0x80000000
353 #define ERIAR_WRITE_CMD 0x80000000
354 #define ERIAR_READ_CMD 0x00000000
355 #define ERIAR_ADDR_BYTE_ALIGN 4
356 #define ERIAR_TYPE_SHIFT 16
357 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
358 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
359 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
360 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
361 #define ERIAR_MASK_SHIFT 12
362 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
363 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
364 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
365 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
366 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
367 EPHY_RXER_NUM = 0x7c,
368 OCPDR = 0xb0, /* OCP GPHY access */
369 #define OCPDR_WRITE_CMD 0x80000000
370 #define OCPDR_READ_CMD 0x00000000
371 #define OCPDR_REG_MASK 0x7f
372 #define OCPDR_GPHY_REG_SHIFT 16
373 #define OCPDR_DATA_MASK 0xffff
374 OCPAR = 0xb4,
375 #define OCPAR_FLAG 0x80000000
376 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
377 #define OCPAR_GPHY_READ_CMD 0x0000f060
378 GPHY_OCP = 0xb8,
379 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
380 MISC = 0xf0, /* 8168e only. */
381 #define TXPLA_RST (1 << 29)
382 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
383 #define PWM_EN (1 << 22)
384 #define RXDV_GATED_EN (1 << 19)
385 #define EARLY_TALLY_EN (1 << 16)
386 };
387
388 enum rtl_register_content {
389 /* InterruptStatusBits */
390 SYSErr = 0x8000,
391 PCSTimeout = 0x4000,
392 SWInt = 0x0100,
393 TxDescUnavail = 0x0080,
394 RxFIFOOver = 0x0040,
395 LinkChg = 0x0020,
396 RxOverflow = 0x0010,
397 TxErr = 0x0008,
398 TxOK = 0x0004,
399 RxErr = 0x0002,
400 RxOK = 0x0001,
401
402 /* RxStatusDesc */
403 RxRWT = (1 << 22),
404 RxRES = (1 << 21),
405 RxRUNT = (1 << 20),
406 RxCRC = (1 << 19),
407
408 /* ChipCmdBits */
409 StopReq = 0x80,
410 CmdReset = 0x10,
411 CmdRxEnb = 0x08,
412 CmdTxEnb = 0x04,
413 RxBufEmpty = 0x01,
414
415 /* TXPoll register p.5 */
416 HPQ = 0x80, /* Poll cmd on the high prio queue */
417 NPQ = 0x40, /* Poll cmd on the low prio queue */
418 FSWInt = 0x01, /* Forced software interrupt */
419
420 /* Cfg9346Bits */
421 Cfg9346_Lock = 0x00,
422 Cfg9346_Unlock = 0xc0,
423
424 /* rx_mode_bits */
425 AcceptErr = 0x20,
426 AcceptRunt = 0x10,
427 AcceptBroadcast = 0x08,
428 AcceptMulticast = 0x04,
429 AcceptMyPhys = 0x02,
430 AcceptAllPhys = 0x01,
431 #define RX_CONFIG_ACCEPT_MASK 0x3f
432
433 /* TxConfigBits */
434 TxInterFrameGapShift = 24,
435 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
436
437 /* Config1 register p.24 */
438 LEDS1 = (1 << 7),
439 LEDS0 = (1 << 6),
440 Speed_down = (1 << 4),
441 MEMMAP = (1 << 3),
442 IOMAP = (1 << 2),
443 VPD = (1 << 1),
444 PMEnable = (1 << 0), /* Power Management Enable */
445
446 /* Config2 register p. 25 */
447 ClkReqEn = (1 << 7), /* Clock Request Enable */
448 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
449 PCI_Clock_66MHz = 0x01,
450 PCI_Clock_33MHz = 0x00,
451
452 /* Config3 register p.25 */
453 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
454 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
455 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
456 Rdy_to_L23 = (1 << 1), /* L23 Enable */
457 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
458
459 /* Config4 register */
460 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
461
462 /* Config5 register p.27 */
463 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
464 MWF = (1 << 5), /* Accept Multicast wakeup frame */
465 UWF = (1 << 4), /* Accept Unicast wakeup frame */
466 Spi_en = (1 << 3),
467 LanWake = (1 << 1), /* LanWake enable/disable */
468 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
469 ASPM_en = (1 << 0), /* ASPM enable */
470
471 /* CPlusCmd p.31 */
472 EnableBist = (1 << 15), // 8168 8101
473 Mac_dbgo_oe = (1 << 14), // 8168 8101
474 Normal_mode = (1 << 13), // unused
475 Force_half_dup = (1 << 12), // 8168 8101
476 Force_rxflow_en = (1 << 11), // 8168 8101
477 Force_txflow_en = (1 << 10), // 8168 8101
478 Cxpl_dbg_sel = (1 << 9), // 8168 8101
479 ASF = (1 << 8), // 8168 8101
480 PktCntrDisable = (1 << 7), // 8168 8101
481 Mac_dbgo_sel = 0x001c, // 8168
482 RxVlan = (1 << 6),
483 RxChkSum = (1 << 5),
484 PCIDAC = (1 << 4),
485 PCIMulRW = (1 << 3),
486 #define INTT_MASK GENMASK(1, 0)
487 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
488
489 /* rtl8169_PHYstatus */
490 TBI_Enable = 0x80,
491 TxFlowCtrl = 0x40,
492 RxFlowCtrl = 0x20,
493 _1000bpsF = 0x10,
494 _100bps = 0x08,
495 _10bps = 0x04,
496 LinkStatus = 0x02,
497 FullDup = 0x01,
498
499 /* ResetCounterCommand */
500 CounterReset = 0x1,
501
502 /* DumpCounterCommand */
503 CounterDump = 0x8,
504
505 /* magic enable v2 */
506 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
507 };
508
509 enum rtl_desc_bit {
510 /* First doubleword. */
511 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
512 RingEnd = (1 << 30), /* End of descriptor ring */
513 FirstFrag = (1 << 29), /* First segment of a packet */
514 LastFrag = (1 << 28), /* Final segment of a packet */
515 };
516
517 /* Generic case. */
518 enum rtl_tx_desc_bit {
519 /* First doubleword. */
520 TD_LSO = (1 << 27), /* Large Send Offload */
521 #define TD_MSS_MAX 0x07ffu /* MSS value */
522
523 /* Second doubleword. */
524 TxVlanTag = (1 << 17), /* Add VLAN tag */
525 };
526
527 /* 8169, 8168b and 810x except 8102e. */
528 enum rtl_tx_desc_bit_0 {
529 /* First doubleword. */
530 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
531 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
532 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
533 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
534 };
535
536 /* 8102e, 8168c and beyond. */
537 enum rtl_tx_desc_bit_1 {
538 /* First doubleword. */
539 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
540 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
541 #define GTTCPHO_SHIFT 18
542 #define GTTCPHO_MAX 0x7fU
543
544 /* Second doubleword. */
545 #define TCPHO_SHIFT 18
546 #define TCPHO_MAX 0x3ffU
547 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
548 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
549 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
550 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
551 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
552 };
553
554 enum rtl_rx_desc_bit {
555 /* Rx private */
556 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
557 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
558
559 #define RxProtoUDP (PID1)
560 #define RxProtoTCP (PID0)
561 #define RxProtoIP (PID1 | PID0)
562 #define RxProtoMask RxProtoIP
563
564 IPFail = (1 << 16), /* IP checksum failed */
565 UDPFail = (1 << 15), /* UDP/IP checksum failed */
566 TCPFail = (1 << 14), /* TCP/IP checksum failed */
567 RxVlanTag = (1 << 16), /* VLAN tag available */
568 };
569
570 #define RsvdMask 0x3fffc000
571
572 struct TxDesc {
573 __le32 opts1;
574 __le32 opts2;
575 __le64 addr;
576 };
577
578 struct RxDesc {
579 __le32 opts1;
580 __le32 opts2;
581 __le64 addr;
582 };
583
584 struct ring_info {
585 struct sk_buff *skb;
586 u32 len;
587 };
588
589 struct rtl8169_counters {
590 __le64 tx_packets;
591 __le64 rx_packets;
592 __le64 tx_errors;
593 __le32 rx_errors;
594 __le16 rx_missed;
595 __le16 align_errors;
596 __le32 tx_one_collision;
597 __le32 tx_multi_collision;
598 __le64 rx_unicast;
599 __le64 rx_broadcast;
600 __le32 rx_multicast;
601 __le16 tx_aborted;
602 __le16 tx_underun;
603 };
604
605 struct rtl8169_tc_offsets {
606 bool inited;
607 __le64 tx_errors;
608 __le32 tx_multi_collision;
609 __le16 tx_aborted;
610 };
611
612 enum rtl_flag {
613 RTL_FLAG_TASK_ENABLED = 0,
614 RTL_FLAG_TASK_RESET_PENDING,
615 RTL_FLAG_MAX
616 };
617
618 struct rtl8169_stats {
619 u64 packets;
620 u64 bytes;
621 struct u64_stats_sync syncp;
622 };
623
624 struct rtl8169_private {
625 void __iomem *mmio_addr; /* memory map physical address */
626 struct pci_dev *pci_dev;
627 struct net_device *dev;
628 struct phy_device *phydev;
629 struct napi_struct napi;
630 u32 msg_enable;
631 enum mac_version mac_version;
632 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
633 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
634 u32 dirty_tx;
635 struct rtl8169_stats rx_stats;
636 struct rtl8169_stats tx_stats;
637 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
638 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
639 dma_addr_t TxPhyAddr;
640 dma_addr_t RxPhyAddr;
641 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
642 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
643 u16 cp_cmd;
644 u16 irq_mask;
645 struct clk *clk;
646
647 struct {
648 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
649 struct mutex mutex;
650 struct work_struct work;
651 } wk;
652
653 unsigned irq_enabled:1;
654 unsigned supports_gmii:1;
655 unsigned aspm_manageable:1;
656 dma_addr_t counters_phys_addr;
657 struct rtl8169_counters *counters;
658 struct rtl8169_tc_offsets tc_offset;
659 u32 saved_wolopts;
660
661 const char *fw_name;
662 struct rtl_fw *rtl_fw;
663
664 u32 ocp_base;
665 };
666
667 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
668
669 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
670 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
671 module_param_named(debug, debug.msg_enable, int, 0);
672 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
673 MODULE_SOFTDEP("pre: realtek");
674 MODULE_LICENSE("GPL");
675 MODULE_FIRMWARE(FIRMWARE_8168D_1);
676 MODULE_FIRMWARE(FIRMWARE_8168D_2);
677 MODULE_FIRMWARE(FIRMWARE_8168E_1);
678 MODULE_FIRMWARE(FIRMWARE_8168E_2);
679 MODULE_FIRMWARE(FIRMWARE_8168E_3);
680 MODULE_FIRMWARE(FIRMWARE_8105E_1);
681 MODULE_FIRMWARE(FIRMWARE_8168F_1);
682 MODULE_FIRMWARE(FIRMWARE_8168F_2);
683 MODULE_FIRMWARE(FIRMWARE_8402_1);
684 MODULE_FIRMWARE(FIRMWARE_8411_1);
685 MODULE_FIRMWARE(FIRMWARE_8411_2);
686 MODULE_FIRMWARE(FIRMWARE_8106E_1);
687 MODULE_FIRMWARE(FIRMWARE_8106E_2);
688 MODULE_FIRMWARE(FIRMWARE_8168G_2);
689 MODULE_FIRMWARE(FIRMWARE_8168G_3);
690 MODULE_FIRMWARE(FIRMWARE_8168H_1);
691 MODULE_FIRMWARE(FIRMWARE_8168H_2);
692 MODULE_FIRMWARE(FIRMWARE_8107E_1);
693 MODULE_FIRMWARE(FIRMWARE_8107E_2);
694
695 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
696 {
697 return &tp->pci_dev->dev;
698 }
699
700 static void rtl_lock_work(struct rtl8169_private *tp)
701 {
702 mutex_lock(&tp->wk.mutex);
703 }
704
705 static void rtl_unlock_work(struct rtl8169_private *tp)
706 {
707 mutex_unlock(&tp->wk.mutex);
708 }
709
710 static void rtl_lock_config_regs(struct rtl8169_private *tp)
711 {
712 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
713 }
714
715 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
716 {
717 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
718 }
719
720 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
721 {
722 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
723 PCI_EXP_DEVCTL_READRQ, force);
724 }
725
726 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
727 {
728 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
729 tp->mac_version != RTL_GIGA_MAC_VER_39;
730 }
731
732 struct rtl_cond {
733 bool (*check)(struct rtl8169_private *);
734 const char *msg;
735 };
736
737 static void rtl_udelay(unsigned int d)
738 {
739 udelay(d);
740 }
741
742 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
743 void (*delay)(unsigned int), unsigned int d, int n,
744 bool high)
745 {
746 int i;
747
748 for (i = 0; i < n; i++) {
749 if (c->check(tp) == high)
750 return true;
751 delay(d);
752 }
753 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
754 c->msg, !high, n, d);
755 return false;
756 }
757
758 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
759 const struct rtl_cond *c,
760 unsigned int d, int n)
761 {
762 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
763 }
764
765 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
766 const struct rtl_cond *c,
767 unsigned int d, int n)
768 {
769 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
770 }
771
772 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
773 const struct rtl_cond *c,
774 unsigned int d, int n)
775 {
776 return rtl_loop_wait(tp, c, msleep, d, n, true);
777 }
778
779 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
780 const struct rtl_cond *c,
781 unsigned int d, int n)
782 {
783 return rtl_loop_wait(tp, c, msleep, d, n, false);
784 }
785
786 #define DECLARE_RTL_COND(name) \
787 static bool name ## _check(struct rtl8169_private *); \
788 \
789 static const struct rtl_cond name = { \
790 .check = name ## _check, \
791 .msg = #name \
792 }; \
793 \
794 static bool name ## _check(struct rtl8169_private *tp)
795
796 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
797 {
798 if (reg & 0xffff0001) {
799 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
800 return true;
801 }
802 return false;
803 }
804
805 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
806 {
807 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
808 }
809
810 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
811 {
812 if (rtl_ocp_reg_failure(tp, reg))
813 return;
814
815 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
816
817 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
818 }
819
820 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
821 {
822 if (rtl_ocp_reg_failure(tp, reg))
823 return 0;
824
825 RTL_W32(tp, GPHY_OCP, reg << 15);
826
827 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
828 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
829 }
830
831 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
832 {
833 if (rtl_ocp_reg_failure(tp, reg))
834 return;
835
836 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
837 }
838
839 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
840 {
841 if (rtl_ocp_reg_failure(tp, reg))
842 return 0;
843
844 RTL_W32(tp, OCPDR, reg << 15);
845
846 return RTL_R32(tp, OCPDR);
847 }
848
849 #define OCP_STD_PHY_BASE 0xa400
850
851 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
852 {
853 if (reg == 0x1f) {
854 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
855 return;
856 }
857
858 if (tp->ocp_base != OCP_STD_PHY_BASE)
859 reg -= 0x10;
860
861 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
862 }
863
864 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
865 {
866 if (tp->ocp_base != OCP_STD_PHY_BASE)
867 reg -= 0x10;
868
869 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
870 }
871
872 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
873 {
874 if (reg == 0x1f) {
875 tp->ocp_base = value << 4;
876 return;
877 }
878
879 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
880 }
881
882 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
883 {
884 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
885 }
886
887 DECLARE_RTL_COND(rtl_phyar_cond)
888 {
889 return RTL_R32(tp, PHYAR) & 0x80000000;
890 }
891
892 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
893 {
894 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
895
896 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
897 /*
898 * According to hardware specs a 20us delay is required after write
899 * complete indication, but before sending next command.
900 */
901 udelay(20);
902 }
903
904 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
905 {
906 int value;
907
908 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
909
910 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
911 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
912
913 /*
914 * According to hardware specs a 20us delay is required after read
915 * complete indication, but before sending next command.
916 */
917 udelay(20);
918
919 return value;
920 }
921
922 DECLARE_RTL_COND(rtl_ocpar_cond)
923 {
924 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
925 }
926
927 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
928 {
929 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
930 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
931 RTL_W32(tp, EPHY_RXER_NUM, 0);
932
933 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
934 }
935
936 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
937 {
938 r8168dp_1_mdio_access(tp, reg,
939 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
940 }
941
942 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
943 {
944 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
945
946 mdelay(1);
947 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
948 RTL_W32(tp, EPHY_RXER_NUM, 0);
949
950 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
951 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
952 }
953
954 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
955
956 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
957 {
958 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
959 }
960
961 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
962 {
963 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
964 }
965
966 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
967 {
968 r8168dp_2_mdio_start(tp);
969
970 r8169_mdio_write(tp, reg, value);
971
972 r8168dp_2_mdio_stop(tp);
973 }
974
975 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
976 {
977 int value;
978
979 r8168dp_2_mdio_start(tp);
980
981 value = r8169_mdio_read(tp, reg);
982
983 r8168dp_2_mdio_stop(tp);
984
985 return value;
986 }
987
988 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
989 {
990 switch (tp->mac_version) {
991 case RTL_GIGA_MAC_VER_27:
992 r8168dp_1_mdio_write(tp, location, val);
993 break;
994 case RTL_GIGA_MAC_VER_28:
995 case RTL_GIGA_MAC_VER_31:
996 r8168dp_2_mdio_write(tp, location, val);
997 break;
998 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
999 r8168g_mdio_write(tp, location, val);
1000 break;
1001 default:
1002 r8169_mdio_write(tp, location, val);
1003 break;
1004 }
1005 }
1006
1007 static int rtl_readphy(struct rtl8169_private *tp, int location)
1008 {
1009 switch (tp->mac_version) {
1010 case RTL_GIGA_MAC_VER_27:
1011 return r8168dp_1_mdio_read(tp, location);
1012 case RTL_GIGA_MAC_VER_28:
1013 case RTL_GIGA_MAC_VER_31:
1014 return r8168dp_2_mdio_read(tp, location);
1015 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1016 return r8168g_mdio_read(tp, location);
1017 default:
1018 return r8169_mdio_read(tp, location);
1019 }
1020 }
1021
1022 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1023 {
1024 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1025 }
1026
1027 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1028 {
1029 int val;
1030
1031 val = rtl_readphy(tp, reg_addr);
1032 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1033 }
1034
1035 DECLARE_RTL_COND(rtl_ephyar_cond)
1036 {
1037 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1038 }
1039
1040 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1041 {
1042 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1043 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1044
1045 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1046
1047 udelay(10);
1048 }
1049
1050 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1051 {
1052 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1053
1054 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1055 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1056 }
1057
1058 DECLARE_RTL_COND(rtl_eriar_cond)
1059 {
1060 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1061 }
1062
1063 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1064 u32 val, int type)
1065 {
1066 BUG_ON((addr & 3) || (mask == 0));
1067 RTL_W32(tp, ERIDR, val);
1068 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1069
1070 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1071 }
1072
1073 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1074 u32 val)
1075 {
1076 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1077 }
1078
1079 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1080 {
1081 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1082
1083 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1084 RTL_R32(tp, ERIDR) : ~0;
1085 }
1086
1087 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1088 {
1089 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1090 }
1091
1092 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1093 u32 m)
1094 {
1095 u32 val;
1096
1097 val = rtl_eri_read(tp, addr);
1098 rtl_eri_write(tp, addr, mask, (val & ~m) | p);
1099 }
1100
1101 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,
1102 u32 p)
1103 {
1104 rtl_w0w1_eri(tp, addr, mask, p, 0);
1105 }
1106
1107 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
1108 u32 m)
1109 {
1110 rtl_w0w1_eri(tp, addr, mask, 0, m);
1111 }
1112
1113 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1114 {
1115 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1116 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1117 RTL_R32(tp, OCPDR) : ~0;
1118 }
1119
1120 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1121 {
1122 return _rtl_eri_read(tp, reg, ERIAR_OOB);
1123 }
1124
1125 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1126 u32 data)
1127 {
1128 RTL_W32(tp, OCPDR, data);
1129 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1130 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1131 }
1132
1133 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1134 u32 data)
1135 {
1136 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1137 data, ERIAR_OOB);
1138 }
1139
1140 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1141 {
1142 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1143
1144 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1145 }
1146
1147 #define OOB_CMD_RESET 0x00
1148 #define OOB_CMD_DRIVER_START 0x05
1149 #define OOB_CMD_DRIVER_STOP 0x06
1150
1151 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1152 {
1153 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1154 }
1155
1156 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1157 {
1158 u16 reg;
1159
1160 reg = rtl8168_get_ocp_reg(tp);
1161
1162 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1163 }
1164
1165 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1166 {
1167 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1168 }
1169
1170 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1171 {
1172 return RTL_R8(tp, IBISR0) & 0x20;
1173 }
1174
1175 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1176 {
1177 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1178 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1179 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1180 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1181 }
1182
1183 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1184 {
1185 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1186 rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1187 }
1188
1189 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1190 {
1191 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1192 r8168ep_ocp_write(tp, 0x01, 0x30,
1193 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1194 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1195 }
1196
1197 static void rtl8168_driver_start(struct rtl8169_private *tp)
1198 {
1199 switch (tp->mac_version) {
1200 case RTL_GIGA_MAC_VER_27:
1201 case RTL_GIGA_MAC_VER_28:
1202 case RTL_GIGA_MAC_VER_31:
1203 rtl8168dp_driver_start(tp);
1204 break;
1205 case RTL_GIGA_MAC_VER_49:
1206 case RTL_GIGA_MAC_VER_50:
1207 case RTL_GIGA_MAC_VER_51:
1208 rtl8168ep_driver_start(tp);
1209 break;
1210 default:
1211 BUG();
1212 break;
1213 }
1214 }
1215
1216 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1217 {
1218 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1219 rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1220 }
1221
1222 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1223 {
1224 rtl8168ep_stop_cmac(tp);
1225 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1226 r8168ep_ocp_write(tp, 0x01, 0x30,
1227 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1228 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1229 }
1230
1231 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1232 {
1233 switch (tp->mac_version) {
1234 case RTL_GIGA_MAC_VER_27:
1235 case RTL_GIGA_MAC_VER_28:
1236 case RTL_GIGA_MAC_VER_31:
1237 rtl8168dp_driver_stop(tp);
1238 break;
1239 case RTL_GIGA_MAC_VER_49:
1240 case RTL_GIGA_MAC_VER_50:
1241 case RTL_GIGA_MAC_VER_51:
1242 rtl8168ep_driver_stop(tp);
1243 break;
1244 default:
1245 BUG();
1246 break;
1247 }
1248 }
1249
1250 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1251 {
1252 u16 reg = rtl8168_get_ocp_reg(tp);
1253
1254 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1255 }
1256
1257 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1258 {
1259 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1260 }
1261
1262 static bool r8168_check_dash(struct rtl8169_private *tp)
1263 {
1264 switch (tp->mac_version) {
1265 case RTL_GIGA_MAC_VER_27:
1266 case RTL_GIGA_MAC_VER_28:
1267 case RTL_GIGA_MAC_VER_31:
1268 return r8168dp_check_dash(tp);
1269 case RTL_GIGA_MAC_VER_49:
1270 case RTL_GIGA_MAC_VER_50:
1271 case RTL_GIGA_MAC_VER_51:
1272 return r8168ep_check_dash(tp);
1273 default:
1274 return false;
1275 }
1276 }
1277
1278 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1279 {
1280 rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1281 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1282 }
1283
1284 DECLARE_RTL_COND(rtl_efusear_cond)
1285 {
1286 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1287 }
1288
1289 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1290 {
1291 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1292
1293 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1294 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1295 }
1296
1297 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1298 {
1299 RTL_W16(tp, IntrStatus, bits);
1300 }
1301
1302 static void rtl_irq_disable(struct rtl8169_private *tp)
1303 {
1304 RTL_W16(tp, IntrMask, 0);
1305 tp->irq_enabled = 0;
1306 }
1307
1308 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1309 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1310 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1311
1312 static void rtl_irq_enable(struct rtl8169_private *tp)
1313 {
1314 tp->irq_enabled = 1;
1315 RTL_W16(tp, IntrMask, tp->irq_mask);
1316 }
1317
1318 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1319 {
1320 rtl_irq_disable(tp);
1321 rtl_ack_events(tp, 0xffff);
1322 /* PCI commit */
1323 RTL_R8(tp, ChipCmd);
1324 }
1325
1326 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1327 {
1328 struct net_device *dev = tp->dev;
1329 struct phy_device *phydev = tp->phydev;
1330
1331 if (!netif_running(dev))
1332 return;
1333
1334 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1335 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1336 if (phydev->speed == SPEED_1000) {
1337 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1338 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1339 } else if (phydev->speed == SPEED_100) {
1340 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1341 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1342 } else {
1343 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1344 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1345 }
1346 rtl_reset_packet_filter(tp);
1347 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1348 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1349 if (phydev->speed == SPEED_1000) {
1350 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1351 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1352 } else {
1353 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1354 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1355 }
1356 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1357 if (phydev->speed == SPEED_10) {
1358 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1359 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1360 } else {
1361 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1362 }
1363 }
1364 }
1365
1366 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1367
1368 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1369 {
1370 struct rtl8169_private *tp = netdev_priv(dev);
1371
1372 rtl_lock_work(tp);
1373 wol->supported = WAKE_ANY;
1374 wol->wolopts = tp->saved_wolopts;
1375 rtl_unlock_work(tp);
1376 }
1377
1378 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1379 {
1380 unsigned int i, tmp;
1381 static const struct {
1382 u32 opt;
1383 u16 reg;
1384 u8 mask;
1385 } cfg[] = {
1386 { WAKE_PHY, Config3, LinkUp },
1387 { WAKE_UCAST, Config5, UWF },
1388 { WAKE_BCAST, Config5, BWF },
1389 { WAKE_MCAST, Config5, MWF },
1390 { WAKE_ANY, Config5, LanWake },
1391 { WAKE_MAGIC, Config3, MagicPacket }
1392 };
1393 u8 options;
1394
1395 rtl_unlock_config_regs(tp);
1396
1397 if (rtl_is_8168evl_up(tp)) {
1398 tmp = ARRAY_SIZE(cfg) - 1;
1399 if (wolopts & WAKE_MAGIC)
1400 rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
1401 MagicPacket_v2);
1402 else
1403 rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
1404 MagicPacket_v2);
1405 } else {
1406 tmp = ARRAY_SIZE(cfg);
1407 }
1408
1409 for (i = 0; i < tmp; i++) {
1410 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1411 if (wolopts & cfg[i].opt)
1412 options |= cfg[i].mask;
1413 RTL_W8(tp, cfg[i].reg, options);
1414 }
1415
1416 switch (tp->mac_version) {
1417 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_17:
1418 options = RTL_R8(tp, Config1) & ~PMEnable;
1419 if (wolopts)
1420 options |= PMEnable;
1421 RTL_W8(tp, Config1, options);
1422 break;
1423 default:
1424 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1425 if (wolopts)
1426 options |= PME_SIGNAL;
1427 RTL_W8(tp, Config2, options);
1428 break;
1429 }
1430
1431 rtl_lock_config_regs(tp);
1432
1433 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1434 }
1435
1436 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1437 {
1438 struct rtl8169_private *tp = netdev_priv(dev);
1439 struct device *d = tp_to_dev(tp);
1440
1441 if (wol->wolopts & ~WAKE_ANY)
1442 return -EINVAL;
1443
1444 pm_runtime_get_noresume(d);
1445
1446 rtl_lock_work(tp);
1447
1448 tp->saved_wolopts = wol->wolopts;
1449
1450 if (pm_runtime_active(d))
1451 __rtl8169_set_wol(tp, tp->saved_wolopts);
1452
1453 rtl_unlock_work(tp);
1454
1455 pm_runtime_put_noidle(d);
1456
1457 return 0;
1458 }
1459
1460 static void rtl8169_get_drvinfo(struct net_device *dev,
1461 struct ethtool_drvinfo *info)
1462 {
1463 struct rtl8169_private *tp = netdev_priv(dev);
1464 struct rtl_fw *rtl_fw = tp->rtl_fw;
1465
1466 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1467 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1468 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1469 if (rtl_fw)
1470 strlcpy(info->fw_version, rtl_fw->version,
1471 sizeof(info->fw_version));
1472 }
1473
1474 static int rtl8169_get_regs_len(struct net_device *dev)
1475 {
1476 return R8169_REGS_SIZE;
1477 }
1478
1479 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1480 netdev_features_t features)
1481 {
1482 struct rtl8169_private *tp = netdev_priv(dev);
1483
1484 if (dev->mtu > TD_MSS_MAX)
1485 features &= ~NETIF_F_ALL_TSO;
1486
1487 if (dev->mtu > JUMBO_1K &&
1488 tp->mac_version > RTL_GIGA_MAC_VER_06)
1489 features &= ~NETIF_F_IP_CSUM;
1490
1491 return features;
1492 }
1493
1494 static int rtl8169_set_features(struct net_device *dev,
1495 netdev_features_t features)
1496 {
1497 struct rtl8169_private *tp = netdev_priv(dev);
1498 u32 rx_config;
1499
1500 rtl_lock_work(tp);
1501
1502 rx_config = RTL_R32(tp, RxConfig);
1503 if (features & NETIF_F_RXALL)
1504 rx_config |= (AcceptErr | AcceptRunt);
1505 else
1506 rx_config &= ~(AcceptErr | AcceptRunt);
1507
1508 RTL_W32(tp, RxConfig, rx_config);
1509
1510 if (features & NETIF_F_RXCSUM)
1511 tp->cp_cmd |= RxChkSum;
1512 else
1513 tp->cp_cmd &= ~RxChkSum;
1514
1515 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1516 tp->cp_cmd |= RxVlan;
1517 else
1518 tp->cp_cmd &= ~RxVlan;
1519
1520 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1521 RTL_R16(tp, CPlusCmd);
1522
1523 rtl_unlock_work(tp);
1524
1525 return 0;
1526 }
1527
1528 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1529 {
1530 return (skb_vlan_tag_present(skb)) ?
1531 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1532 }
1533
1534 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1535 {
1536 u32 opts2 = le32_to_cpu(desc->opts2);
1537
1538 if (opts2 & RxVlanTag)
1539 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1540 }
1541
1542 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1543 void *p)
1544 {
1545 struct rtl8169_private *tp = netdev_priv(dev);
1546 u32 __iomem *data = tp->mmio_addr;
1547 u32 *dw = p;
1548 int i;
1549
1550 rtl_lock_work(tp);
1551 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1552 memcpy_fromio(dw++, data++, 4);
1553 rtl_unlock_work(tp);
1554 }
1555
1556 static u32 rtl8169_get_msglevel(struct net_device *dev)
1557 {
1558 struct rtl8169_private *tp = netdev_priv(dev);
1559
1560 return tp->msg_enable;
1561 }
1562
1563 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1564 {
1565 struct rtl8169_private *tp = netdev_priv(dev);
1566
1567 tp->msg_enable = value;
1568 }
1569
1570 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1571 "tx_packets",
1572 "rx_packets",
1573 "tx_errors",
1574 "rx_errors",
1575 "rx_missed",
1576 "align_errors",
1577 "tx_single_collisions",
1578 "tx_multi_collisions",
1579 "unicast",
1580 "broadcast",
1581 "multicast",
1582 "tx_aborted",
1583 "tx_underrun",
1584 };
1585
1586 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1587 {
1588 switch (sset) {
1589 case ETH_SS_STATS:
1590 return ARRAY_SIZE(rtl8169_gstrings);
1591 default:
1592 return -EOPNOTSUPP;
1593 }
1594 }
1595
1596 DECLARE_RTL_COND(rtl_counters_cond)
1597 {
1598 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1599 }
1600
1601 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1602 {
1603 dma_addr_t paddr = tp->counters_phys_addr;
1604 u32 cmd;
1605
1606 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1607 RTL_R32(tp, CounterAddrHigh);
1608 cmd = (u64)paddr & DMA_BIT_MASK(32);
1609 RTL_W32(tp, CounterAddrLow, cmd);
1610 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1611
1612 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1613 }
1614
1615 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1616 {
1617 /*
1618 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1619 * tally counters.
1620 */
1621 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1622 return true;
1623
1624 return rtl8169_do_counters(tp, CounterReset);
1625 }
1626
1627 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1628 {
1629 u8 val = RTL_R8(tp, ChipCmd);
1630
1631 /*
1632 * Some chips are unable to dump tally counters when the receiver
1633 * is disabled. If 0xff chip may be in a PCI power-save state.
1634 */
1635 if (!(val & CmdRxEnb) || val == 0xff)
1636 return true;
1637
1638 return rtl8169_do_counters(tp, CounterDump);
1639 }
1640
1641 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1642 {
1643 struct rtl8169_counters *counters = tp->counters;
1644 bool ret = false;
1645
1646 /*
1647 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1648 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1649 * reset by a power cycle, while the counter values collected by the
1650 * driver are reset at every driver unload/load cycle.
1651 *
1652 * To make sure the HW values returned by @get_stats64 match the SW
1653 * values, we collect the initial values at first open(*) and use them
1654 * as offsets to normalize the values returned by @get_stats64.
1655 *
1656 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1657 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1658 * set at open time by rtl_hw_start.
1659 */
1660
1661 if (tp->tc_offset.inited)
1662 return true;
1663
1664 /* If both, reset and update fail, propagate to caller. */
1665 if (rtl8169_reset_counters(tp))
1666 ret = true;
1667
1668 if (rtl8169_update_counters(tp))
1669 ret = true;
1670
1671 tp->tc_offset.tx_errors = counters->tx_errors;
1672 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1673 tp->tc_offset.tx_aborted = counters->tx_aborted;
1674 tp->tc_offset.inited = true;
1675
1676 return ret;
1677 }
1678
1679 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1680 struct ethtool_stats *stats, u64 *data)
1681 {
1682 struct rtl8169_private *tp = netdev_priv(dev);
1683 struct device *d = tp_to_dev(tp);
1684 struct rtl8169_counters *counters = tp->counters;
1685
1686 ASSERT_RTNL();
1687
1688 pm_runtime_get_noresume(d);
1689
1690 if (pm_runtime_active(d))
1691 rtl8169_update_counters(tp);
1692
1693 pm_runtime_put_noidle(d);
1694
1695 data[0] = le64_to_cpu(counters->tx_packets);
1696 data[1] = le64_to_cpu(counters->rx_packets);
1697 data[2] = le64_to_cpu(counters->tx_errors);
1698 data[3] = le32_to_cpu(counters->rx_errors);
1699 data[4] = le16_to_cpu(counters->rx_missed);
1700 data[5] = le16_to_cpu(counters->align_errors);
1701 data[6] = le32_to_cpu(counters->tx_one_collision);
1702 data[7] = le32_to_cpu(counters->tx_multi_collision);
1703 data[8] = le64_to_cpu(counters->rx_unicast);
1704 data[9] = le64_to_cpu(counters->rx_broadcast);
1705 data[10] = le32_to_cpu(counters->rx_multicast);
1706 data[11] = le16_to_cpu(counters->tx_aborted);
1707 data[12] = le16_to_cpu(counters->tx_underun);
1708 }
1709
1710 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1711 {
1712 switch(stringset) {
1713 case ETH_SS_STATS:
1714 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1715 break;
1716 }
1717 }
1718
1719 /*
1720 * Interrupt coalescing
1721 *
1722 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1723 * > 8169, 8168 and 810x line of chipsets
1724 *
1725 * 8169, 8168, and 8136(810x) serial chipsets support it.
1726 *
1727 * > 2 - the Tx timer unit at gigabit speed
1728 *
1729 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1730 * (0xe0) bit 1 and bit 0.
1731 *
1732 * For 8169
1733 * bit[1:0] \ speed 1000M 100M 10M
1734 * 0 0 320ns 2.56us 40.96us
1735 * 0 1 2.56us 20.48us 327.7us
1736 * 1 0 5.12us 40.96us 655.4us
1737 * 1 1 10.24us 81.92us 1.31ms
1738 *
1739 * For the other
1740 * bit[1:0] \ speed 1000M 100M 10M
1741 * 0 0 5us 2.56us 40.96us
1742 * 0 1 40us 20.48us 327.7us
1743 * 1 0 80us 40.96us 655.4us
1744 * 1 1 160us 81.92us 1.31ms
1745 */
1746
1747 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1748 struct rtl_coalesce_scale {
1749 /* Rx / Tx */
1750 u32 nsecs[2];
1751 };
1752
1753 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1754 struct rtl_coalesce_info {
1755 u32 speed;
1756 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
1757 };
1758
1759 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1760 #define rxtx_x1822(r, t) { \
1761 {{(r), (t)}}, \
1762 {{(r)*8, (t)*8}}, \
1763 {{(r)*8*2, (t)*8*2}}, \
1764 {{(r)*8*2*2, (t)*8*2*2}}, \
1765 }
1766 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1767 /* speed delays: rx00 tx00 */
1768 { SPEED_10, rxtx_x1822(40960, 40960) },
1769 { SPEED_100, rxtx_x1822( 2560, 2560) },
1770 { SPEED_1000, rxtx_x1822( 320, 320) },
1771 { 0 },
1772 };
1773
1774 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1775 /* speed delays: rx00 tx00 */
1776 { SPEED_10, rxtx_x1822(40960, 40960) },
1777 { SPEED_100, rxtx_x1822( 2560, 2560) },
1778 { SPEED_1000, rxtx_x1822( 5000, 5000) },
1779 { 0 },
1780 };
1781 #undef rxtx_x1822
1782
1783 /* get rx/tx scale vector corresponding to current speed */
1784 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1785 {
1786 struct rtl8169_private *tp = netdev_priv(dev);
1787 const struct rtl_coalesce_info *ci;
1788
1789 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1790 ci = rtl_coalesce_info_8169;
1791 else
1792 ci = rtl_coalesce_info_8168_8136;
1793
1794 for (; ci->speed; ci++) {
1795 if (tp->phydev->speed == ci->speed)
1796 return ci;
1797 }
1798
1799 return ERR_PTR(-ELNRNG);
1800 }
1801
1802 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1803 {
1804 struct rtl8169_private *tp = netdev_priv(dev);
1805 const struct rtl_coalesce_info *ci;
1806 const struct rtl_coalesce_scale *scale;
1807 struct {
1808 u32 *max_frames;
1809 u32 *usecs;
1810 } coal_settings [] = {
1811 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1812 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1813 }, *p = coal_settings;
1814 int i;
1815 u16 w;
1816
1817 memset(ec, 0, sizeof(*ec));
1818
1819 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1820 ci = rtl_coalesce_info(dev);
1821 if (IS_ERR(ci))
1822 return PTR_ERR(ci);
1823
1824 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1825
1826 /* read IntrMitigate and adjust according to scale */
1827 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1828 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1829 w >>= RTL_COALESCE_SHIFT;
1830 *p->usecs = w & RTL_COALESCE_MASK;
1831 }
1832
1833 for (i = 0; i < 2; i++) {
1834 p = coal_settings + i;
1835 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1836
1837 /*
1838 * ethtool_coalesce says it is illegal to set both usecs and
1839 * max_frames to 0.
1840 */
1841 if (!*p->usecs && !*p->max_frames)
1842 *p->max_frames = 1;
1843 }
1844
1845 return 0;
1846 }
1847
1848 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1849 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1850 struct net_device *dev, u32 nsec, u16 *cp01)
1851 {
1852 const struct rtl_coalesce_info *ci;
1853 u16 i;
1854
1855 ci = rtl_coalesce_info(dev);
1856 if (IS_ERR(ci))
1857 return ERR_CAST(ci);
1858
1859 for (i = 0; i < 4; i++) {
1860 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1861 ci->scalev[i].nsecs[1]);
1862 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1863 *cp01 = i;
1864 return &ci->scalev[i];
1865 }
1866 }
1867
1868 return ERR_PTR(-EINVAL);
1869 }
1870
1871 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1872 {
1873 struct rtl8169_private *tp = netdev_priv(dev);
1874 const struct rtl_coalesce_scale *scale;
1875 struct {
1876 u32 frames;
1877 u32 usecs;
1878 } coal_settings [] = {
1879 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1880 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1881 }, *p = coal_settings;
1882 u16 w = 0, cp01;
1883 int i;
1884
1885 scale = rtl_coalesce_choose_scale(dev,
1886 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1887 if (IS_ERR(scale))
1888 return PTR_ERR(scale);
1889
1890 for (i = 0; i < 2; i++, p++) {
1891 u32 units;
1892
1893 /*
1894 * accept max_frames=1 we returned in rtl_get_coalesce.
1895 * accept it not only when usecs=0 because of e.g. the following scenario:
1896 *
1897 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1898 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1899 * - then user does `ethtool -C eth0 rx-usecs 100`
1900 *
1901 * since ethtool sends to kernel whole ethtool_coalesce
1902 * settings, if we do not handle rx_usecs=!0, rx_frames=1
1903 * we'll reject it below in `frames % 4 != 0`.
1904 */
1905 if (p->frames == 1) {
1906 p->frames = 0;
1907 }
1908
1909 units = p->usecs * 1000 / scale->nsecs[i];
1910 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
1911 return -EINVAL;
1912
1913 w <<= RTL_COALESCE_SHIFT;
1914 w |= units;
1915 w <<= RTL_COALESCE_SHIFT;
1916 w |= p->frames >> 2;
1917 }
1918
1919 rtl_lock_work(tp);
1920
1921 RTL_W16(tp, IntrMitigate, swab16(w));
1922
1923 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1924 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1925 RTL_R16(tp, CPlusCmd);
1926
1927 rtl_unlock_work(tp);
1928
1929 return 0;
1930 }
1931
1932 static int rtl_get_eee_supp(struct rtl8169_private *tp)
1933 {
1934 struct phy_device *phydev = tp->phydev;
1935 int ret;
1936
1937 switch (tp->mac_version) {
1938 case RTL_GIGA_MAC_VER_34:
1939 case RTL_GIGA_MAC_VER_35:
1940 case RTL_GIGA_MAC_VER_36:
1941 case RTL_GIGA_MAC_VER_38:
1942 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1943 break;
1944 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1945 ret = phy_read_paged(phydev, 0x0a5c, 0x12);
1946 break;
1947 default:
1948 ret = -EPROTONOSUPPORT;
1949 break;
1950 }
1951
1952 return ret;
1953 }
1954
1955 static int rtl_get_eee_lpadv(struct rtl8169_private *tp)
1956 {
1957 struct phy_device *phydev = tp->phydev;
1958 int ret;
1959
1960 switch (tp->mac_version) {
1961 case RTL_GIGA_MAC_VER_34:
1962 case RTL_GIGA_MAC_VER_35:
1963 case RTL_GIGA_MAC_VER_36:
1964 case RTL_GIGA_MAC_VER_38:
1965 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
1966 break;
1967 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1968 ret = phy_read_paged(phydev, 0x0a5d, 0x11);
1969 break;
1970 default:
1971 ret = -EPROTONOSUPPORT;
1972 break;
1973 }
1974
1975 return ret;
1976 }
1977
1978 static int rtl_get_eee_adv(struct rtl8169_private *tp)
1979 {
1980 struct phy_device *phydev = tp->phydev;
1981 int ret;
1982
1983 switch (tp->mac_version) {
1984 case RTL_GIGA_MAC_VER_34:
1985 case RTL_GIGA_MAC_VER_35:
1986 case RTL_GIGA_MAC_VER_36:
1987 case RTL_GIGA_MAC_VER_38:
1988 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
1989 break;
1990 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1991 ret = phy_read_paged(phydev, 0x0a5d, 0x10);
1992 break;
1993 default:
1994 ret = -EPROTONOSUPPORT;
1995 break;
1996 }
1997
1998 return ret;
1999 }
2000
2001 static int rtl_set_eee_adv(struct rtl8169_private *tp, int val)
2002 {
2003 struct phy_device *phydev = tp->phydev;
2004 int ret = 0;
2005
2006 switch (tp->mac_version) {
2007 case RTL_GIGA_MAC_VER_34:
2008 case RTL_GIGA_MAC_VER_35:
2009 case RTL_GIGA_MAC_VER_36:
2010 case RTL_GIGA_MAC_VER_38:
2011 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
2012 break;
2013 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2014 phy_write_paged(phydev, 0x0a5d, 0x10, val);
2015 break;
2016 default:
2017 ret = -EPROTONOSUPPORT;
2018 break;
2019 }
2020
2021 return ret;
2022 }
2023
2024 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
2025 {
2026 struct rtl8169_private *tp = netdev_priv(dev);
2027 struct device *d = tp_to_dev(tp);
2028 int ret;
2029
2030 pm_runtime_get_noresume(d);
2031
2032 if (!pm_runtime_active(d)) {
2033 ret = -EOPNOTSUPP;
2034 goto out;
2035 }
2036
2037 /* Get Supported EEE */
2038 ret = rtl_get_eee_supp(tp);
2039 if (ret < 0)
2040 goto out;
2041 data->supported = mmd_eee_cap_to_ethtool_sup_t(ret);
2042
2043 /* Get advertisement EEE */
2044 ret = rtl_get_eee_adv(tp);
2045 if (ret < 0)
2046 goto out;
2047 data->advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2048 data->eee_enabled = !!data->advertised;
2049
2050 /* Get LP advertisement EEE */
2051 ret = rtl_get_eee_lpadv(tp);
2052 if (ret < 0)
2053 goto out;
2054 data->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2055 data->eee_active = !!(data->advertised & data->lp_advertised);
2056 out:
2057 pm_runtime_put_noidle(d);
2058 return ret < 0 ? ret : 0;
2059 }
2060
2061 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
2062 {
2063 struct rtl8169_private *tp = netdev_priv(dev);
2064 struct device *d = tp_to_dev(tp);
2065 int old_adv, adv = 0, cap, ret;
2066
2067 pm_runtime_get_noresume(d);
2068
2069 if (!dev->phydev || !pm_runtime_active(d)) {
2070 ret = -EOPNOTSUPP;
2071 goto out;
2072 }
2073
2074 if (dev->phydev->autoneg == AUTONEG_DISABLE ||
2075 dev->phydev->duplex != DUPLEX_FULL) {
2076 ret = -EPROTONOSUPPORT;
2077 goto out;
2078 }
2079
2080 /* Get Supported EEE */
2081 ret = rtl_get_eee_supp(tp);
2082 if (ret < 0)
2083 goto out;
2084 cap = ret;
2085
2086 ret = rtl_get_eee_adv(tp);
2087 if (ret < 0)
2088 goto out;
2089 old_adv = ret;
2090
2091 if (data->eee_enabled) {
2092 adv = !data->advertised ? cap :
2093 ethtool_adv_to_mmd_eee_adv_t(data->advertised) & cap;
2094 /* Mask prohibited EEE modes */
2095 adv &= ~dev->phydev->eee_broken_modes;
2096 }
2097
2098 if (old_adv != adv) {
2099 ret = rtl_set_eee_adv(tp, adv);
2100 if (ret < 0)
2101 goto out;
2102
2103 /* Restart autonegotiation so the new modes get sent to the
2104 * link partner.
2105 */
2106 ret = phy_restart_aneg(dev->phydev);
2107 }
2108
2109 out:
2110 pm_runtime_put_noidle(d);
2111 return ret < 0 ? ret : 0;
2112 }
2113
2114 static const struct ethtool_ops rtl8169_ethtool_ops = {
2115 .get_drvinfo = rtl8169_get_drvinfo,
2116 .get_regs_len = rtl8169_get_regs_len,
2117 .get_link = ethtool_op_get_link,
2118 .get_coalesce = rtl_get_coalesce,
2119 .set_coalesce = rtl_set_coalesce,
2120 .get_msglevel = rtl8169_get_msglevel,
2121 .set_msglevel = rtl8169_set_msglevel,
2122 .get_regs = rtl8169_get_regs,
2123 .get_wol = rtl8169_get_wol,
2124 .set_wol = rtl8169_set_wol,
2125 .get_strings = rtl8169_get_strings,
2126 .get_sset_count = rtl8169_get_sset_count,
2127 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2128 .get_ts_info = ethtool_op_get_ts_info,
2129 .nway_reset = phy_ethtool_nway_reset,
2130 .get_eee = rtl8169_get_eee,
2131 .set_eee = rtl8169_set_eee,
2132 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2133 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2134 };
2135
2136 static void rtl_enable_eee(struct rtl8169_private *tp)
2137 {
2138 int supported = rtl_get_eee_supp(tp);
2139
2140 if (supported > 0)
2141 rtl_set_eee_adv(tp, supported);
2142 }
2143
2144 static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2145 {
2146 /*
2147 * The driver currently handles the 8168Bf and the 8168Be identically
2148 * but they can be identified more specifically through the test below
2149 * if needed:
2150 *
2151 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2152 *
2153 * Same thing for the 8101Eb and the 8101Ec:
2154 *
2155 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2156 */
2157 static const struct rtl_mac_info {
2158 u16 mask;
2159 u16 val;
2160 u16 mac_version;
2161 } mac_info[] = {
2162 /* 8168EP family. */
2163 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2164 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2165 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2166
2167 /* 8168H family. */
2168 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2169 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2170
2171 /* 8168G family. */
2172 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2173 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2174 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2175 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2176
2177 /* 8168F family. */
2178 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2179 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2180 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2181
2182 /* 8168E family. */
2183 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2184 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2185 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2186
2187 /* 8168D family. */
2188 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2189 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2190
2191 /* 8168DP family. */
2192 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2193 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2194 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2195
2196 /* 8168C family. */
2197 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2198 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2199 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2200 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2201 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2202 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2203 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2204
2205 /* 8168B family. */
2206 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2207 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2208 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2209
2210 /* 8101 family. */
2211 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2212 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2213 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2214 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2215 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2216 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2217 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2218 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2219 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2220 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2221 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2222 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2223 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2224 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2225 /* FIXME: where did these entries come from ? -- FR */
2226 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2227 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2228
2229 /* 8110 family. */
2230 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2231 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2232 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2233 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2234 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2235
2236 /* Catch-all */
2237 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
2238 };
2239 const struct rtl_mac_info *p = mac_info;
2240 u16 reg = RTL_R32(tp, TxConfig) >> 20;
2241
2242 while ((reg & p->mask) != p->val)
2243 p++;
2244 tp->mac_version = p->mac_version;
2245
2246 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2247 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2248 } else if (!tp->supports_gmii) {
2249 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2250 tp->mac_version = RTL_GIGA_MAC_VER_43;
2251 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2252 tp->mac_version = RTL_GIGA_MAC_VER_47;
2253 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2254 tp->mac_version = RTL_GIGA_MAC_VER_48;
2255 }
2256 }
2257
2258 struct phy_reg {
2259 u16 reg;
2260 u16 val;
2261 };
2262
2263 static void __rtl_writephy_batch(struct rtl8169_private *tp,
2264 const struct phy_reg *regs, int len)
2265 {
2266 while (len-- > 0) {
2267 rtl_writephy(tp, regs->reg, regs->val);
2268 regs++;
2269 }
2270 }
2271
2272 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a))
2273
2274 static void rtl_release_firmware(struct rtl8169_private *tp)
2275 {
2276 if (tp->rtl_fw) {
2277 rtl_fw_release_firmware(tp->rtl_fw);
2278 kfree(tp->rtl_fw);
2279 tp->rtl_fw = NULL;
2280 }
2281 }
2282
2283 static void rtl_apply_firmware(struct rtl8169_private *tp)
2284 {
2285 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2286 if (tp->rtl_fw)
2287 rtl_fw_write_firmware(tp, tp->rtl_fw);
2288 }
2289
2290 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2291 {
2292 if (rtl_readphy(tp, reg) != val)
2293 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2294 else
2295 rtl_apply_firmware(tp);
2296 }
2297
2298 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2299 {
2300 /* Adjust EEE LED frequency */
2301 if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2302 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2303
2304 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);
2305 }
2306
2307 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2308 {
2309 struct phy_device *phydev = tp->phydev;
2310
2311 phy_write(phydev, 0x1f, 0x0007);
2312 phy_write(phydev, 0x1e, 0x0020);
2313 phy_set_bits(phydev, 0x15, BIT(8));
2314
2315 phy_write(phydev, 0x1f, 0x0005);
2316 phy_write(phydev, 0x05, 0x8b85);
2317 phy_set_bits(phydev, 0x06, BIT(13));
2318
2319 phy_write(phydev, 0x1f, 0x0000);
2320 }
2321
2322 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2323 {
2324 phy_modify_paged(tp->phydev, 0x0a43, 0x11, 0, BIT(4));
2325 }
2326
2327 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2328 {
2329 static const struct phy_reg phy_reg_init[] = {
2330 { 0x1f, 0x0001 },
2331 { 0x06, 0x006e },
2332 { 0x08, 0x0708 },
2333 { 0x15, 0x4000 },
2334 { 0x18, 0x65c7 },
2335
2336 { 0x1f, 0x0001 },
2337 { 0x03, 0x00a1 },
2338 { 0x02, 0x0008 },
2339 { 0x01, 0x0120 },
2340 { 0x00, 0x1000 },
2341 { 0x04, 0x0800 },
2342 { 0x04, 0x0000 },
2343
2344 { 0x03, 0xff41 },
2345 { 0x02, 0xdf60 },
2346 { 0x01, 0x0140 },
2347 { 0x00, 0x0077 },
2348 { 0x04, 0x7800 },
2349 { 0x04, 0x7000 },
2350
2351 { 0x03, 0x802f },
2352 { 0x02, 0x4f02 },
2353 { 0x01, 0x0409 },
2354 { 0x00, 0xf0f9 },
2355 { 0x04, 0x9800 },
2356 { 0x04, 0x9000 },
2357
2358 { 0x03, 0xdf01 },
2359 { 0x02, 0xdf20 },
2360 { 0x01, 0xff95 },
2361 { 0x00, 0xba00 },
2362 { 0x04, 0xa800 },
2363 { 0x04, 0xa000 },
2364
2365 { 0x03, 0xff41 },
2366 { 0x02, 0xdf20 },
2367 { 0x01, 0x0140 },
2368 { 0x00, 0x00bb },
2369 { 0x04, 0xb800 },
2370 { 0x04, 0xb000 },
2371
2372 { 0x03, 0xdf41 },
2373 { 0x02, 0xdc60 },
2374 { 0x01, 0x6340 },
2375 { 0x00, 0x007d },
2376 { 0x04, 0xd800 },
2377 { 0x04, 0xd000 },
2378
2379 { 0x03, 0xdf01 },
2380 { 0x02, 0xdf20 },
2381 { 0x01, 0x100a },
2382 { 0x00, 0xa0ff },
2383 { 0x04, 0xf800 },
2384 { 0x04, 0xf000 },
2385
2386 { 0x1f, 0x0000 },
2387 { 0x0b, 0x0000 },
2388 { 0x00, 0x9200 }
2389 };
2390
2391 rtl_writephy_batch(tp, phy_reg_init);
2392 }
2393
2394 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2395 {
2396 static const struct phy_reg phy_reg_init[] = {
2397 { 0x1f, 0x0002 },
2398 { 0x01, 0x90d0 },
2399 { 0x1f, 0x0000 }
2400 };
2401
2402 rtl_writephy_batch(tp, phy_reg_init);
2403 }
2404
2405 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2406 {
2407 struct pci_dev *pdev = tp->pci_dev;
2408
2409 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2410 (pdev->subsystem_device != 0xe000))
2411 return;
2412
2413 rtl_writephy(tp, 0x1f, 0x0001);
2414 rtl_writephy(tp, 0x10, 0xf01b);
2415 rtl_writephy(tp, 0x1f, 0x0000);
2416 }
2417
2418 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2419 {
2420 static const struct phy_reg phy_reg_init[] = {
2421 { 0x1f, 0x0001 },
2422 { 0x04, 0x0000 },
2423 { 0x03, 0x00a1 },
2424 { 0x02, 0x0008 },
2425 { 0x01, 0x0120 },
2426 { 0x00, 0x1000 },
2427 { 0x04, 0x0800 },
2428 { 0x04, 0x9000 },
2429 { 0x03, 0x802f },
2430 { 0x02, 0x4f02 },
2431 { 0x01, 0x0409 },
2432 { 0x00, 0xf099 },
2433 { 0x04, 0x9800 },
2434 { 0x04, 0xa000 },
2435 { 0x03, 0xdf01 },
2436 { 0x02, 0xdf20 },
2437 { 0x01, 0xff95 },
2438 { 0x00, 0xba00 },
2439 { 0x04, 0xa800 },
2440 { 0x04, 0xf000 },
2441 { 0x03, 0xdf01 },
2442 { 0x02, 0xdf20 },
2443 { 0x01, 0x101a },
2444 { 0x00, 0xa0ff },
2445 { 0x04, 0xf800 },
2446 { 0x04, 0x0000 },
2447 { 0x1f, 0x0000 },
2448
2449 { 0x1f, 0x0001 },
2450 { 0x10, 0xf41b },
2451 { 0x14, 0xfb54 },
2452 { 0x18, 0xf5c7 },
2453 { 0x1f, 0x0000 },
2454
2455 { 0x1f, 0x0001 },
2456 { 0x17, 0x0cc0 },
2457 { 0x1f, 0x0000 }
2458 };
2459
2460 rtl_writephy_batch(tp, phy_reg_init);
2461
2462 rtl8169scd_hw_phy_config_quirk(tp);
2463 }
2464
2465 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2466 {
2467 static const struct phy_reg phy_reg_init[] = {
2468 { 0x1f, 0x0001 },
2469 { 0x04, 0x0000 },
2470 { 0x03, 0x00a1 },
2471 { 0x02, 0x0008 },
2472 { 0x01, 0x0120 },
2473 { 0x00, 0x1000 },
2474 { 0x04, 0x0800 },
2475 { 0x04, 0x9000 },
2476 { 0x03, 0x802f },
2477 { 0x02, 0x4f02 },
2478 { 0x01, 0x0409 },
2479 { 0x00, 0xf099 },
2480 { 0x04, 0x9800 },
2481 { 0x04, 0xa000 },
2482 { 0x03, 0xdf01 },
2483 { 0x02, 0xdf20 },
2484 { 0x01, 0xff95 },
2485 { 0x00, 0xba00 },
2486 { 0x04, 0xa800 },
2487 { 0x04, 0xf000 },
2488 { 0x03, 0xdf01 },
2489 { 0x02, 0xdf20 },
2490 { 0x01, 0x101a },
2491 { 0x00, 0xa0ff },
2492 { 0x04, 0xf800 },
2493 { 0x04, 0x0000 },
2494 { 0x1f, 0x0000 },
2495
2496 { 0x1f, 0x0001 },
2497 { 0x0b, 0x8480 },
2498 { 0x1f, 0x0000 },
2499
2500 { 0x1f, 0x0001 },
2501 { 0x18, 0x67c7 },
2502 { 0x04, 0x2000 },
2503 { 0x03, 0x002f },
2504 { 0x02, 0x4360 },
2505 { 0x01, 0x0109 },
2506 { 0x00, 0x3022 },
2507 { 0x04, 0x2800 },
2508 { 0x1f, 0x0000 },
2509
2510 { 0x1f, 0x0001 },
2511 { 0x17, 0x0cc0 },
2512 { 0x1f, 0x0000 }
2513 };
2514
2515 rtl_writephy_batch(tp, phy_reg_init);
2516 }
2517
2518 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2519 {
2520 static const struct phy_reg phy_reg_init[] = {
2521 { 0x10, 0xf41b },
2522 { 0x1f, 0x0000 }
2523 };
2524
2525 rtl_writephy(tp, 0x1f, 0x0001);
2526 rtl_patchphy(tp, 0x16, 1 << 0);
2527
2528 rtl_writephy_batch(tp, phy_reg_init);
2529 }
2530
2531 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2532 {
2533 static const struct phy_reg phy_reg_init[] = {
2534 { 0x1f, 0x0001 },
2535 { 0x10, 0xf41b },
2536 { 0x1f, 0x0000 }
2537 };
2538
2539 rtl_writephy_batch(tp, phy_reg_init);
2540 }
2541
2542 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2543 {
2544 static const struct phy_reg phy_reg_init[] = {
2545 { 0x1f, 0x0000 },
2546 { 0x1d, 0x0f00 },
2547 { 0x1f, 0x0002 },
2548 { 0x0c, 0x1ec8 },
2549 { 0x1f, 0x0000 }
2550 };
2551
2552 rtl_writephy_batch(tp, phy_reg_init);
2553 }
2554
2555 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2556 {
2557 static const struct phy_reg phy_reg_init[] = {
2558 { 0x1f, 0x0001 },
2559 { 0x1d, 0x3d98 },
2560 { 0x1f, 0x0000 }
2561 };
2562
2563 rtl_writephy(tp, 0x1f, 0x0000);
2564 rtl_patchphy(tp, 0x14, 1 << 5);
2565 rtl_patchphy(tp, 0x0d, 1 << 5);
2566
2567 rtl_writephy_batch(tp, phy_reg_init);
2568 }
2569
2570 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2571 {
2572 static const struct phy_reg phy_reg_init[] = {
2573 { 0x1f, 0x0001 },
2574 { 0x12, 0x2300 },
2575 { 0x1f, 0x0002 },
2576 { 0x00, 0x88d4 },
2577 { 0x01, 0x82b1 },
2578 { 0x03, 0x7002 },
2579 { 0x08, 0x9e30 },
2580 { 0x09, 0x01f0 },
2581 { 0x0a, 0x5500 },
2582 { 0x0c, 0x00c8 },
2583 { 0x1f, 0x0003 },
2584 { 0x12, 0xc096 },
2585 { 0x16, 0x000a },
2586 { 0x1f, 0x0000 },
2587 { 0x1f, 0x0000 },
2588 { 0x09, 0x2000 },
2589 { 0x09, 0x0000 }
2590 };
2591
2592 rtl_writephy_batch(tp, phy_reg_init);
2593
2594 rtl_patchphy(tp, 0x14, 1 << 5);
2595 rtl_patchphy(tp, 0x0d, 1 << 5);
2596 rtl_writephy(tp, 0x1f, 0x0000);
2597 }
2598
2599 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2600 {
2601 static const struct phy_reg phy_reg_init[] = {
2602 { 0x1f, 0x0001 },
2603 { 0x12, 0x2300 },
2604 { 0x03, 0x802f },
2605 { 0x02, 0x4f02 },
2606 { 0x01, 0x0409 },
2607 { 0x00, 0xf099 },
2608 { 0x04, 0x9800 },
2609 { 0x04, 0x9000 },
2610 { 0x1d, 0x3d98 },
2611 { 0x1f, 0x0002 },
2612 { 0x0c, 0x7eb8 },
2613 { 0x06, 0x0761 },
2614 { 0x1f, 0x0003 },
2615 { 0x16, 0x0f0a },
2616 { 0x1f, 0x0000 }
2617 };
2618
2619 rtl_writephy_batch(tp, phy_reg_init);
2620
2621 rtl_patchphy(tp, 0x16, 1 << 0);
2622 rtl_patchphy(tp, 0x14, 1 << 5);
2623 rtl_patchphy(tp, 0x0d, 1 << 5);
2624 rtl_writephy(tp, 0x1f, 0x0000);
2625 }
2626
2627 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2628 {
2629 static const struct phy_reg phy_reg_init[] = {
2630 { 0x1f, 0x0001 },
2631 { 0x12, 0x2300 },
2632 { 0x1d, 0x3d98 },
2633 { 0x1f, 0x0002 },
2634 { 0x0c, 0x7eb8 },
2635 { 0x06, 0x5461 },
2636 { 0x1f, 0x0003 },
2637 { 0x16, 0x0f0a },
2638 { 0x1f, 0x0000 }
2639 };
2640
2641 rtl_writephy_batch(tp, phy_reg_init);
2642
2643 rtl_patchphy(tp, 0x16, 1 << 0);
2644 rtl_patchphy(tp, 0x14, 1 << 5);
2645 rtl_patchphy(tp, 0x0d, 1 << 5);
2646 rtl_writephy(tp, 0x1f, 0x0000);
2647 }
2648
2649 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2650 {
2651 rtl8168c_3_hw_phy_config(tp);
2652 }
2653
2654 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
2655 /* Channel Estimation */
2656 { 0x1f, 0x0001 },
2657 { 0x06, 0x4064 },
2658 { 0x07, 0x2863 },
2659 { 0x08, 0x059c },
2660 { 0x09, 0x26b4 },
2661 { 0x0a, 0x6a19 },
2662 { 0x0b, 0xdcc8 },
2663 { 0x10, 0xf06d },
2664 { 0x14, 0x7f68 },
2665 { 0x18, 0x7fd9 },
2666 { 0x1c, 0xf0ff },
2667 { 0x1d, 0x3d9c },
2668 { 0x1f, 0x0003 },
2669 { 0x12, 0xf49f },
2670 { 0x13, 0x070b },
2671 { 0x1a, 0x05ad },
2672 { 0x14, 0x94c0 },
2673
2674 /*
2675 * Tx Error Issue
2676 * Enhance line driver power
2677 */
2678 { 0x1f, 0x0002 },
2679 { 0x06, 0x5561 },
2680 { 0x1f, 0x0005 },
2681 { 0x05, 0x8332 },
2682 { 0x06, 0x5561 },
2683
2684 /*
2685 * Can not link to 1Gbps with bad cable
2686 * Decrease SNR threshold form 21.07dB to 19.04dB
2687 */
2688 { 0x1f, 0x0001 },
2689 { 0x17, 0x0cc0 },
2690
2691 { 0x1f, 0x0000 },
2692 { 0x0d, 0xf880 }
2693 };
2694
2695 static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = {
2696 { 0x1f, 0x0002 },
2697 { 0x05, 0x669a },
2698 { 0x1f, 0x0005 },
2699 { 0x05, 0x8330 },
2700 { 0x06, 0x669a },
2701 { 0x1f, 0x0002 }
2702 };
2703
2704 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2705 {
2706 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2707
2708 /*
2709 * Rx Error Issue
2710 * Fine Tune Switching regulator parameter
2711 */
2712 rtl_writephy(tp, 0x1f, 0x0002);
2713 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2714 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2715
2716 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2717 int val;
2718
2719 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2720
2721 val = rtl_readphy(tp, 0x0d);
2722
2723 if ((val & 0x00ff) != 0x006c) {
2724 static const u32 set[] = {
2725 0x0065, 0x0066, 0x0067, 0x0068,
2726 0x0069, 0x006a, 0x006b, 0x006c
2727 };
2728 int i;
2729
2730 rtl_writephy(tp, 0x1f, 0x0002);
2731
2732 val &= 0xff00;
2733 for (i = 0; i < ARRAY_SIZE(set); i++)
2734 rtl_writephy(tp, 0x0d, val | set[i]);
2735 }
2736 } else {
2737 static const struct phy_reg phy_reg_init[] = {
2738 { 0x1f, 0x0002 },
2739 { 0x05, 0x6662 },
2740 { 0x1f, 0x0005 },
2741 { 0x05, 0x8330 },
2742 { 0x06, 0x6662 }
2743 };
2744
2745 rtl_writephy_batch(tp, phy_reg_init);
2746 }
2747
2748 /* RSET couple improve */
2749 rtl_writephy(tp, 0x1f, 0x0002);
2750 rtl_patchphy(tp, 0x0d, 0x0300);
2751 rtl_patchphy(tp, 0x0f, 0x0010);
2752
2753 /* Fine tune PLL performance */
2754 rtl_writephy(tp, 0x1f, 0x0002);
2755 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2756 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2757
2758 rtl_writephy(tp, 0x1f, 0x0005);
2759 rtl_writephy(tp, 0x05, 0x001b);
2760
2761 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2762
2763 rtl_writephy(tp, 0x1f, 0x0000);
2764 }
2765
2766 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2767 {
2768 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2769
2770 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2771 int val;
2772
2773 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2774
2775 val = rtl_readphy(tp, 0x0d);
2776 if ((val & 0x00ff) != 0x006c) {
2777 static const u32 set[] = {
2778 0x0065, 0x0066, 0x0067, 0x0068,
2779 0x0069, 0x006a, 0x006b, 0x006c
2780 };
2781 int i;
2782
2783 rtl_writephy(tp, 0x1f, 0x0002);
2784
2785 val &= 0xff00;
2786 for (i = 0; i < ARRAY_SIZE(set); i++)
2787 rtl_writephy(tp, 0x0d, val | set[i]);
2788 }
2789 } else {
2790 static const struct phy_reg phy_reg_init[] = {
2791 { 0x1f, 0x0002 },
2792 { 0x05, 0x2642 },
2793 { 0x1f, 0x0005 },
2794 { 0x05, 0x8330 },
2795 { 0x06, 0x2642 }
2796 };
2797
2798 rtl_writephy_batch(tp, phy_reg_init);
2799 }
2800
2801 /* Fine tune PLL performance */
2802 rtl_writephy(tp, 0x1f, 0x0002);
2803 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2804 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2805
2806 /* Switching regulator Slew rate */
2807 rtl_writephy(tp, 0x1f, 0x0002);
2808 rtl_patchphy(tp, 0x0f, 0x0017);
2809
2810 rtl_writephy(tp, 0x1f, 0x0005);
2811 rtl_writephy(tp, 0x05, 0x001b);
2812
2813 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2814
2815 rtl_writephy(tp, 0x1f, 0x0000);
2816 }
2817
2818 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2819 {
2820 static const struct phy_reg phy_reg_init[] = {
2821 { 0x1f, 0x0002 },
2822 { 0x10, 0x0008 },
2823 { 0x0d, 0x006c },
2824
2825 { 0x1f, 0x0000 },
2826 { 0x0d, 0xf880 },
2827
2828 { 0x1f, 0x0001 },
2829 { 0x17, 0x0cc0 },
2830
2831 { 0x1f, 0x0001 },
2832 { 0x0b, 0xa4d8 },
2833 { 0x09, 0x281c },
2834 { 0x07, 0x2883 },
2835 { 0x0a, 0x6b35 },
2836 { 0x1d, 0x3da4 },
2837 { 0x1c, 0xeffd },
2838 { 0x14, 0x7f52 },
2839 { 0x18, 0x7fc6 },
2840 { 0x08, 0x0601 },
2841 { 0x06, 0x4063 },
2842 { 0x10, 0xf074 },
2843 { 0x1f, 0x0003 },
2844 { 0x13, 0x0789 },
2845 { 0x12, 0xf4bd },
2846 { 0x1a, 0x04fd },
2847 { 0x14, 0x84b0 },
2848 { 0x1f, 0x0000 },
2849 { 0x00, 0x9200 },
2850
2851 { 0x1f, 0x0005 },
2852 { 0x01, 0x0340 },
2853 { 0x1f, 0x0001 },
2854 { 0x04, 0x4000 },
2855 { 0x03, 0x1d21 },
2856 { 0x02, 0x0c32 },
2857 { 0x01, 0x0200 },
2858 { 0x00, 0x5554 },
2859 { 0x04, 0x4800 },
2860 { 0x04, 0x4000 },
2861 { 0x04, 0xf000 },
2862 { 0x03, 0xdf01 },
2863 { 0x02, 0xdf20 },
2864 { 0x01, 0x101a },
2865 { 0x00, 0xa0ff },
2866 { 0x04, 0xf800 },
2867 { 0x04, 0xf000 },
2868 { 0x1f, 0x0000 },
2869
2870 { 0x1f, 0x0007 },
2871 { 0x1e, 0x0023 },
2872 { 0x16, 0x0000 },
2873 { 0x1f, 0x0000 }
2874 };
2875
2876 rtl_writephy_batch(tp, phy_reg_init);
2877 }
2878
2879 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2880 {
2881 static const struct phy_reg phy_reg_init[] = {
2882 { 0x1f, 0x0001 },
2883 { 0x17, 0x0cc0 },
2884
2885 { 0x1f, 0x0007 },
2886 { 0x1e, 0x002d },
2887 { 0x18, 0x0040 },
2888 { 0x1f, 0x0000 }
2889 };
2890
2891 rtl_writephy_batch(tp, phy_reg_init);
2892 rtl_patchphy(tp, 0x0d, 1 << 5);
2893 }
2894
2895 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2896 {
2897 static const struct phy_reg phy_reg_init[] = {
2898 /* Enable Delay cap */
2899 { 0x1f, 0x0005 },
2900 { 0x05, 0x8b80 },
2901 { 0x06, 0xc896 },
2902 { 0x1f, 0x0000 },
2903
2904 /* Channel estimation fine tune */
2905 { 0x1f, 0x0001 },
2906 { 0x0b, 0x6c20 },
2907 { 0x07, 0x2872 },
2908 { 0x1c, 0xefff },
2909 { 0x1f, 0x0003 },
2910 { 0x14, 0x6420 },
2911 { 0x1f, 0x0000 },
2912
2913 /* Update PFM & 10M TX idle timer */
2914 { 0x1f, 0x0007 },
2915 { 0x1e, 0x002f },
2916 { 0x15, 0x1919 },
2917 { 0x1f, 0x0000 },
2918
2919 { 0x1f, 0x0007 },
2920 { 0x1e, 0x00ac },
2921 { 0x18, 0x0006 },
2922 { 0x1f, 0x0000 }
2923 };
2924
2925 rtl_apply_firmware(tp);
2926
2927 rtl_writephy_batch(tp, phy_reg_init);
2928
2929 /* DCO enable for 10M IDLE Power */
2930 rtl_writephy(tp, 0x1f, 0x0007);
2931 rtl_writephy(tp, 0x1e, 0x0023);
2932 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
2933 rtl_writephy(tp, 0x1f, 0x0000);
2934
2935 /* For impedance matching */
2936 rtl_writephy(tp, 0x1f, 0x0002);
2937 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
2938 rtl_writephy(tp, 0x1f, 0x0000);
2939
2940 /* PHY auto speed down */
2941 rtl_writephy(tp, 0x1f, 0x0007);
2942 rtl_writephy(tp, 0x1e, 0x002d);
2943 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
2944 rtl_writephy(tp, 0x1f, 0x0000);
2945 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
2946
2947 rtl_writephy(tp, 0x1f, 0x0005);
2948 rtl_writephy(tp, 0x05, 0x8b86);
2949 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
2950 rtl_writephy(tp, 0x1f, 0x0000);
2951
2952 rtl_writephy(tp, 0x1f, 0x0005);
2953 rtl_writephy(tp, 0x05, 0x8b85);
2954 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
2955 rtl_writephy(tp, 0x1f, 0x0007);
2956 rtl_writephy(tp, 0x1e, 0x0020);
2957 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
2958 rtl_writephy(tp, 0x1f, 0x0006);
2959 rtl_writephy(tp, 0x00, 0x5a00);
2960 rtl_writephy(tp, 0x1f, 0x0000);
2961 rtl_writephy(tp, 0x0d, 0x0007);
2962 rtl_writephy(tp, 0x0e, 0x003c);
2963 rtl_writephy(tp, 0x0d, 0x4007);
2964 rtl_writephy(tp, 0x0e, 0x0000);
2965 rtl_writephy(tp, 0x0d, 0x0000);
2966 }
2967
2968 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
2969 {
2970 const u16 w[] = {
2971 addr[0] | (addr[1] << 8),
2972 addr[2] | (addr[3] << 8),
2973 addr[4] | (addr[5] << 8)
2974 };
2975
2976 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
2977 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
2978 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
2979 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
2980 }
2981
2982 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2983 {
2984 static const struct phy_reg phy_reg_init[] = {
2985 /* Enable Delay cap */
2986 { 0x1f, 0x0004 },
2987 { 0x1f, 0x0007 },
2988 { 0x1e, 0x00ac },
2989 { 0x18, 0x0006 },
2990 { 0x1f, 0x0002 },
2991 { 0x1f, 0x0000 },
2992 { 0x1f, 0x0000 },
2993
2994 /* Channel estimation fine tune */
2995 { 0x1f, 0x0003 },
2996 { 0x09, 0xa20f },
2997 { 0x1f, 0x0000 },
2998 { 0x1f, 0x0000 },
2999
3000 /* Green Setting */
3001 { 0x1f, 0x0005 },
3002 { 0x05, 0x8b5b },
3003 { 0x06, 0x9222 },
3004 { 0x05, 0x8b6d },
3005 { 0x06, 0x8000 },
3006 { 0x05, 0x8b76 },
3007 { 0x06, 0x8000 },
3008 { 0x1f, 0x0000 }
3009 };
3010
3011 rtl_apply_firmware(tp);
3012
3013 rtl_writephy_batch(tp, phy_reg_init);
3014
3015 /* For 4-corner performance improve */
3016 rtl_writephy(tp, 0x1f, 0x0005);
3017 rtl_writephy(tp, 0x05, 0x8b80);
3018 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3019 rtl_writephy(tp, 0x1f, 0x0000);
3020
3021 /* PHY auto speed down */
3022 rtl_writephy(tp, 0x1f, 0x0004);
3023 rtl_writephy(tp, 0x1f, 0x0007);
3024 rtl_writephy(tp, 0x1e, 0x002d);
3025 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3026 rtl_writephy(tp, 0x1f, 0x0002);
3027 rtl_writephy(tp, 0x1f, 0x0000);
3028 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3029
3030 /* improve 10M EEE waveform */
3031 rtl_writephy(tp, 0x1f, 0x0005);
3032 rtl_writephy(tp, 0x05, 0x8b86);
3033 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3034 rtl_writephy(tp, 0x1f, 0x0000);
3035
3036 /* Improve 2-pair detection performance */
3037 rtl_writephy(tp, 0x1f, 0x0005);
3038 rtl_writephy(tp, 0x05, 0x8b85);
3039 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3040 rtl_writephy(tp, 0x1f, 0x0000);
3041
3042 rtl8168f_config_eee_phy(tp);
3043 rtl_enable_eee(tp);
3044
3045 /* Green feature */
3046 rtl_writephy(tp, 0x1f, 0x0003);
3047 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3048 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3049 rtl_writephy(tp, 0x1f, 0x0000);
3050 rtl_writephy(tp, 0x1f, 0x0005);
3051 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3052 rtl_writephy(tp, 0x1f, 0x0000);
3053
3054 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3055 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3056 }
3057
3058 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3059 {
3060 /* For 4-corner performance improve */
3061 rtl_writephy(tp, 0x1f, 0x0005);
3062 rtl_writephy(tp, 0x05, 0x8b80);
3063 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3064 rtl_writephy(tp, 0x1f, 0x0000);
3065
3066 /* PHY auto speed down */
3067 rtl_writephy(tp, 0x1f, 0x0007);
3068 rtl_writephy(tp, 0x1e, 0x002d);
3069 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3070 rtl_writephy(tp, 0x1f, 0x0000);
3071 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3072
3073 /* Improve 10M EEE waveform */
3074 rtl_writephy(tp, 0x1f, 0x0005);
3075 rtl_writephy(tp, 0x05, 0x8b86);
3076 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3077 rtl_writephy(tp, 0x1f, 0x0000);
3078
3079 rtl8168f_config_eee_phy(tp);
3080 rtl_enable_eee(tp);
3081 }
3082
3083 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3084 {
3085 static const struct phy_reg phy_reg_init[] = {
3086 /* Channel estimation fine tune */
3087 { 0x1f, 0x0003 },
3088 { 0x09, 0xa20f },
3089 { 0x1f, 0x0000 },
3090
3091 /* Modify green table for giga & fnet */
3092 { 0x1f, 0x0005 },
3093 { 0x05, 0x8b55 },
3094 { 0x06, 0x0000 },
3095 { 0x05, 0x8b5e },
3096 { 0x06, 0x0000 },
3097 { 0x05, 0x8b67 },
3098 { 0x06, 0x0000 },
3099 { 0x05, 0x8b70 },
3100 { 0x06, 0x0000 },
3101 { 0x1f, 0x0000 },
3102 { 0x1f, 0x0007 },
3103 { 0x1e, 0x0078 },
3104 { 0x17, 0x0000 },
3105 { 0x19, 0x00fb },
3106 { 0x1f, 0x0000 },
3107
3108 /* Modify green table for 10M */
3109 { 0x1f, 0x0005 },
3110 { 0x05, 0x8b79 },
3111 { 0x06, 0xaa00 },
3112 { 0x1f, 0x0000 },
3113
3114 /* Disable hiimpedance detection (RTCT) */
3115 { 0x1f, 0x0003 },
3116 { 0x01, 0x328a },
3117 { 0x1f, 0x0000 }
3118 };
3119
3120 rtl_apply_firmware(tp);
3121
3122 rtl_writephy_batch(tp, phy_reg_init);
3123
3124 rtl8168f_hw_phy_config(tp);
3125
3126 /* Improve 2-pair detection performance */
3127 rtl_writephy(tp, 0x1f, 0x0005);
3128 rtl_writephy(tp, 0x05, 0x8b85);
3129 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3130 rtl_writephy(tp, 0x1f, 0x0000);
3131 }
3132
3133 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3134 {
3135 rtl_apply_firmware(tp);
3136
3137 rtl8168f_hw_phy_config(tp);
3138 }
3139
3140 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3141 {
3142 static const struct phy_reg phy_reg_init[] = {
3143 /* Channel estimation fine tune */
3144 { 0x1f, 0x0003 },
3145 { 0x09, 0xa20f },
3146 { 0x1f, 0x0000 },
3147
3148 /* Modify green table for giga & fnet */
3149 { 0x1f, 0x0005 },
3150 { 0x05, 0x8b55 },
3151 { 0x06, 0x0000 },
3152 { 0x05, 0x8b5e },
3153 { 0x06, 0x0000 },
3154 { 0x05, 0x8b67 },
3155 { 0x06, 0x0000 },
3156 { 0x05, 0x8b70 },
3157 { 0x06, 0x0000 },
3158 { 0x1f, 0x0000 },
3159 { 0x1f, 0x0007 },
3160 { 0x1e, 0x0078 },
3161 { 0x17, 0x0000 },
3162 { 0x19, 0x00aa },
3163 { 0x1f, 0x0000 },
3164
3165 /* Modify green table for 10M */
3166 { 0x1f, 0x0005 },
3167 { 0x05, 0x8b79 },
3168 { 0x06, 0xaa00 },
3169 { 0x1f, 0x0000 },
3170
3171 /* Disable hiimpedance detection (RTCT) */
3172 { 0x1f, 0x0003 },
3173 { 0x01, 0x328a },
3174 { 0x1f, 0x0000 }
3175 };
3176
3177
3178 rtl_apply_firmware(tp);
3179
3180 rtl8168f_hw_phy_config(tp);
3181
3182 /* Improve 2-pair detection performance */
3183 rtl_writephy(tp, 0x1f, 0x0005);
3184 rtl_writephy(tp, 0x05, 0x8b85);
3185 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3186 rtl_writephy(tp, 0x1f, 0x0000);
3187
3188 rtl_writephy_batch(tp, phy_reg_init);
3189
3190 /* Modify green table for giga */
3191 rtl_writephy(tp, 0x1f, 0x0005);
3192 rtl_writephy(tp, 0x05, 0x8b54);
3193 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3194 rtl_writephy(tp, 0x05, 0x8b5d);
3195 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3196 rtl_writephy(tp, 0x05, 0x8a7c);
3197 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3198 rtl_writephy(tp, 0x05, 0x8a7f);
3199 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3200 rtl_writephy(tp, 0x05, 0x8a82);
3201 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3202 rtl_writephy(tp, 0x05, 0x8a85);
3203 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3204 rtl_writephy(tp, 0x05, 0x8a88);
3205 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3206 rtl_writephy(tp, 0x1f, 0x0000);
3207
3208 /* uc same-seed solution */
3209 rtl_writephy(tp, 0x1f, 0x0005);
3210 rtl_writephy(tp, 0x05, 0x8b85);
3211 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3212 rtl_writephy(tp, 0x1f, 0x0000);
3213
3214 /* Green feature */
3215 rtl_writephy(tp, 0x1f, 0x0003);
3216 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3217 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3218 rtl_writephy(tp, 0x1f, 0x0000);
3219 }
3220
3221 static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3222 {
3223 phy_modify_paged(tp->phydev, 0x0a43, 0x10, BIT(2), 0);
3224 }
3225
3226 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3227 {
3228 struct phy_device *phydev = tp->phydev;
3229
3230 phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0);
3231 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6));
3232 phy_write(phydev, 0x1f, 0x0a43);
3233 phy_write(phydev, 0x13, 0x8084);
3234 phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13));
3235 phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0));
3236
3237 phy_write(phydev, 0x1f, 0x0000);
3238 }
3239
3240 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3241 {
3242 int ret;
3243
3244 rtl_apply_firmware(tp);
3245
3246 ret = phy_read_paged(tp->phydev, 0x0a46, 0x10);
3247 if (ret & BIT(8))
3248 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, BIT(15), 0);
3249 else
3250 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, 0, BIT(15));
3251
3252 ret = phy_read_paged(tp->phydev, 0x0a46, 0x13);
3253 if (ret & BIT(8))
3254 phy_modify_paged(tp->phydev, 0x0c41, 0x15, 0, BIT(1));
3255 else
3256 phy_modify_paged(tp->phydev, 0x0c41, 0x15, BIT(1), 0);
3257
3258 /* Enable PHY auto speed down */
3259 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3260
3261 rtl8168g_phy_adjust_10m_aldps(tp);
3262
3263 /* EEE auto-fallback function */
3264 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3265
3266 /* Enable UC LPF tune function */
3267 rtl_writephy(tp, 0x1f, 0x0a43);
3268 rtl_writephy(tp, 0x13, 0x8012);
3269 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3270
3271 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3272
3273 /* Improve SWR Efficiency */
3274 rtl_writephy(tp, 0x1f, 0x0bcd);
3275 rtl_writephy(tp, 0x14, 0x5065);
3276 rtl_writephy(tp, 0x14, 0xd065);
3277 rtl_writephy(tp, 0x1f, 0x0bc8);
3278 rtl_writephy(tp, 0x11, 0x5655);
3279 rtl_writephy(tp, 0x1f, 0x0bcd);
3280 rtl_writephy(tp, 0x14, 0x1065);
3281 rtl_writephy(tp, 0x14, 0x9065);
3282 rtl_writephy(tp, 0x14, 0x1065);
3283 rtl_writephy(tp, 0x1f, 0x0000);
3284
3285 rtl8168g_disable_aldps(tp);
3286 rtl8168g_config_eee_phy(tp);
3287 rtl_enable_eee(tp);
3288 }
3289
3290 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3291 {
3292 rtl_apply_firmware(tp);
3293 rtl8168g_config_eee_phy(tp);
3294 rtl_enable_eee(tp);
3295 }
3296
3297 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3298 {
3299 u16 dout_tapbin;
3300 u32 data;
3301
3302 rtl_apply_firmware(tp);
3303
3304 /* CHN EST parameters adjust - giga master */
3305 rtl_writephy(tp, 0x1f, 0x0a43);
3306 rtl_writephy(tp, 0x13, 0x809b);
3307 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3308 rtl_writephy(tp, 0x13, 0x80a2);
3309 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3310 rtl_writephy(tp, 0x13, 0x80a4);
3311 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3312 rtl_writephy(tp, 0x13, 0x809c);
3313 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3314 rtl_writephy(tp, 0x1f, 0x0000);
3315
3316 /* CHN EST parameters adjust - giga slave */
3317 rtl_writephy(tp, 0x1f, 0x0a43);
3318 rtl_writephy(tp, 0x13, 0x80ad);
3319 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3320 rtl_writephy(tp, 0x13, 0x80b4);
3321 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3322 rtl_writephy(tp, 0x13, 0x80ac);
3323 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3324 rtl_writephy(tp, 0x1f, 0x0000);
3325
3326 /* CHN EST parameters adjust - fnet */
3327 rtl_writephy(tp, 0x1f, 0x0a43);
3328 rtl_writephy(tp, 0x13, 0x808e);
3329 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3330 rtl_writephy(tp, 0x13, 0x8090);
3331 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3332 rtl_writephy(tp, 0x13, 0x8092);
3333 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3334 rtl_writephy(tp, 0x1f, 0x0000);
3335
3336 /* enable R-tune & PGA-retune function */
3337 dout_tapbin = 0;
3338 rtl_writephy(tp, 0x1f, 0x0a46);
3339 data = rtl_readphy(tp, 0x13);
3340 data &= 3;
3341 data <<= 2;
3342 dout_tapbin |= data;
3343 data = rtl_readphy(tp, 0x12);
3344 data &= 0xc000;
3345 data >>= 14;
3346 dout_tapbin |= data;
3347 dout_tapbin = ~(dout_tapbin^0x08);
3348 dout_tapbin <<= 12;
3349 dout_tapbin &= 0xf000;
3350 rtl_writephy(tp, 0x1f, 0x0a43);
3351 rtl_writephy(tp, 0x13, 0x827a);
3352 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3353 rtl_writephy(tp, 0x13, 0x827b);
3354 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3355 rtl_writephy(tp, 0x13, 0x827c);
3356 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3357 rtl_writephy(tp, 0x13, 0x827d);
3358 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3359
3360 rtl_writephy(tp, 0x1f, 0x0a43);
3361 rtl_writephy(tp, 0x13, 0x0811);
3362 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3363 rtl_writephy(tp, 0x1f, 0x0a42);
3364 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3365 rtl_writephy(tp, 0x1f, 0x0000);
3366
3367 /* enable GPHY 10M */
3368 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3369
3370 /* SAR ADC performance */
3371 phy_modify_paged(tp->phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14));
3372
3373 rtl_writephy(tp, 0x1f, 0x0a43);
3374 rtl_writephy(tp, 0x13, 0x803f);
3375 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3376 rtl_writephy(tp, 0x13, 0x8047);
3377 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3378 rtl_writephy(tp, 0x13, 0x804f);
3379 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3380 rtl_writephy(tp, 0x13, 0x8057);
3381 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3382 rtl_writephy(tp, 0x13, 0x805f);
3383 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3384 rtl_writephy(tp, 0x13, 0x8067);
3385 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3386 rtl_writephy(tp, 0x13, 0x806f);
3387 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3388 rtl_writephy(tp, 0x1f, 0x0000);
3389
3390 /* disable phy pfm mode */
3391 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3392
3393 rtl8168g_disable_aldps(tp);
3394 rtl8168g_config_eee_phy(tp);
3395 rtl_enable_eee(tp);
3396 }
3397
3398 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3399 {
3400 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3401 u16 rlen;
3402 u32 data;
3403
3404 rtl_apply_firmware(tp);
3405
3406 /* CHIN EST parameter update */
3407 rtl_writephy(tp, 0x1f, 0x0a43);
3408 rtl_writephy(tp, 0x13, 0x808a);
3409 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3410 rtl_writephy(tp, 0x1f, 0x0000);
3411
3412 /* enable R-tune & PGA-retune function */
3413 rtl_writephy(tp, 0x1f, 0x0a43);
3414 rtl_writephy(tp, 0x13, 0x0811);
3415 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3416 rtl_writephy(tp, 0x1f, 0x0a42);
3417 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3418 rtl_writephy(tp, 0x1f, 0x0000);
3419
3420 /* enable GPHY 10M */
3421 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3422
3423 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3424 data = r8168_mac_ocp_read(tp, 0xdd02);
3425 ioffset_p3 = ((data & 0x80)>>7);
3426 ioffset_p3 <<= 3;
3427
3428 data = r8168_mac_ocp_read(tp, 0xdd00);
3429 ioffset_p3 |= ((data & (0xe000))>>13);
3430 ioffset_p2 = ((data & (0x1e00))>>9);
3431 ioffset_p1 = ((data & (0x01e0))>>5);
3432 ioffset_p0 = ((data & 0x0010)>>4);
3433 ioffset_p0 <<= 3;
3434 ioffset_p0 |= (data & (0x07));
3435 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3436
3437 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3438 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3439 rtl_writephy(tp, 0x1f, 0x0bcf);
3440 rtl_writephy(tp, 0x16, data);
3441 rtl_writephy(tp, 0x1f, 0x0000);
3442 }
3443
3444 /* Modify rlen (TX LPF corner frequency) level */
3445 rtl_writephy(tp, 0x1f, 0x0bcd);
3446 data = rtl_readphy(tp, 0x16);
3447 data &= 0x000f;
3448 rlen = 0;
3449 if (data > 3)
3450 rlen = data - 3;
3451 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3452 rtl_writephy(tp, 0x17, data);
3453 rtl_writephy(tp, 0x1f, 0x0bcd);
3454 rtl_writephy(tp, 0x1f, 0x0000);
3455
3456 /* disable phy pfm mode */
3457 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3458
3459 rtl8168g_disable_aldps(tp);
3460 rtl8168g_config_eee_phy(tp);
3461 rtl_enable_eee(tp);
3462 }
3463
3464 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3465 {
3466 /* Enable PHY auto speed down */
3467 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3468
3469 rtl8168g_phy_adjust_10m_aldps(tp);
3470
3471 /* Enable EEE auto-fallback function */
3472 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3473
3474 /* Enable UC LPF tune function */
3475 rtl_writephy(tp, 0x1f, 0x0a43);
3476 rtl_writephy(tp, 0x13, 0x8012);
3477 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3478 rtl_writephy(tp, 0x1f, 0x0000);
3479
3480 /* set rg_sel_sdm_rate */
3481 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3482
3483 rtl8168g_disable_aldps(tp);
3484 rtl8168g_config_eee_phy(tp);
3485 rtl_enable_eee(tp);
3486 }
3487
3488 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3489 {
3490 rtl8168g_phy_adjust_10m_aldps(tp);
3491
3492 /* Enable UC LPF tune function */
3493 rtl_writephy(tp, 0x1f, 0x0a43);
3494 rtl_writephy(tp, 0x13, 0x8012);
3495 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3496 rtl_writephy(tp, 0x1f, 0x0000);
3497
3498 /* Set rg_sel_sdm_rate */
3499 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3500
3501 /* Channel estimation parameters */
3502 rtl_writephy(tp, 0x1f, 0x0a43);
3503 rtl_writephy(tp, 0x13, 0x80f3);
3504 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3505 rtl_writephy(tp, 0x13, 0x80f0);
3506 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3507 rtl_writephy(tp, 0x13, 0x80ef);
3508 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3509 rtl_writephy(tp, 0x13, 0x80f6);
3510 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3511 rtl_writephy(tp, 0x13, 0x80ec);
3512 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3513 rtl_writephy(tp, 0x13, 0x80ed);
3514 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3515 rtl_writephy(tp, 0x13, 0x80f2);
3516 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3517 rtl_writephy(tp, 0x13, 0x80f4);
3518 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3519 rtl_writephy(tp, 0x1f, 0x0a43);
3520 rtl_writephy(tp, 0x13, 0x8110);
3521 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3522 rtl_writephy(tp, 0x13, 0x810f);
3523 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3524 rtl_writephy(tp, 0x13, 0x8111);
3525 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3526 rtl_writephy(tp, 0x13, 0x8113);
3527 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3528 rtl_writephy(tp, 0x13, 0x8115);
3529 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3530 rtl_writephy(tp, 0x13, 0x810e);
3531 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3532 rtl_writephy(tp, 0x13, 0x810c);
3533 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3534 rtl_writephy(tp, 0x13, 0x810b);
3535 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3536 rtl_writephy(tp, 0x1f, 0x0a43);
3537 rtl_writephy(tp, 0x13, 0x80d1);
3538 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3539 rtl_writephy(tp, 0x13, 0x80cd);
3540 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3541 rtl_writephy(tp, 0x13, 0x80d3);
3542 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3543 rtl_writephy(tp, 0x13, 0x80d5);
3544 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3545 rtl_writephy(tp, 0x13, 0x80d7);
3546 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3547
3548 /* Force PWM-mode */
3549 rtl_writephy(tp, 0x1f, 0x0bcd);
3550 rtl_writephy(tp, 0x14, 0x5065);
3551 rtl_writephy(tp, 0x14, 0xd065);
3552 rtl_writephy(tp, 0x1f, 0x0bc8);
3553 rtl_writephy(tp, 0x12, 0x00ed);
3554 rtl_writephy(tp, 0x1f, 0x0bcd);
3555 rtl_writephy(tp, 0x14, 0x1065);
3556 rtl_writephy(tp, 0x14, 0x9065);
3557 rtl_writephy(tp, 0x14, 0x1065);
3558 rtl_writephy(tp, 0x1f, 0x0000);
3559
3560 rtl8168g_disable_aldps(tp);
3561 rtl8168g_config_eee_phy(tp);
3562 rtl_enable_eee(tp);
3563 }
3564
3565 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3566 {
3567 static const struct phy_reg phy_reg_init[] = {
3568 { 0x1f, 0x0003 },
3569 { 0x08, 0x441d },
3570 { 0x01, 0x9100 },
3571 { 0x1f, 0x0000 }
3572 };
3573
3574 rtl_writephy(tp, 0x1f, 0x0000);
3575 rtl_patchphy(tp, 0x11, 1 << 12);
3576 rtl_patchphy(tp, 0x19, 1 << 13);
3577 rtl_patchphy(tp, 0x10, 1 << 15);
3578
3579 rtl_writephy_batch(tp, phy_reg_init);
3580 }
3581
3582 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3583 {
3584 static const struct phy_reg phy_reg_init[] = {
3585 { 0x1f, 0x0005 },
3586 { 0x1a, 0x0000 },
3587 { 0x1f, 0x0000 },
3588
3589 { 0x1f, 0x0004 },
3590 { 0x1c, 0x0000 },
3591 { 0x1f, 0x0000 },
3592
3593 { 0x1f, 0x0001 },
3594 { 0x15, 0x7701 },
3595 { 0x1f, 0x0000 }
3596 };
3597
3598 /* Disable ALDPS before ram code */
3599 rtl_writephy(tp, 0x1f, 0x0000);
3600 rtl_writephy(tp, 0x18, 0x0310);
3601 msleep(100);
3602
3603 rtl_apply_firmware(tp);
3604
3605 rtl_writephy_batch(tp, phy_reg_init);
3606 }
3607
3608 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3609 {
3610 /* Disable ALDPS before setting firmware */
3611 rtl_writephy(tp, 0x1f, 0x0000);
3612 rtl_writephy(tp, 0x18, 0x0310);
3613 msleep(20);
3614
3615 rtl_apply_firmware(tp);
3616
3617 /* EEE setting */
3618 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3619 rtl_writephy(tp, 0x1f, 0x0004);
3620 rtl_writephy(tp, 0x10, 0x401f);
3621 rtl_writephy(tp, 0x19, 0x7030);
3622 rtl_writephy(tp, 0x1f, 0x0000);
3623 }
3624
3625 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3626 {
3627 static const struct phy_reg phy_reg_init[] = {
3628 { 0x1f, 0x0004 },
3629 { 0x10, 0xc07f },
3630 { 0x19, 0x7030 },
3631 { 0x1f, 0x0000 }
3632 };
3633
3634 /* Disable ALDPS before ram code */
3635 rtl_writephy(tp, 0x1f, 0x0000);
3636 rtl_writephy(tp, 0x18, 0x0310);
3637 msleep(100);
3638
3639 rtl_apply_firmware(tp);
3640
3641 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3642 rtl_writephy_batch(tp, phy_reg_init);
3643
3644 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3645 }
3646
3647 static void rtl_hw_phy_config(struct net_device *dev)
3648 {
3649 static const rtl_generic_fct phy_configs[] = {
3650 /* PCI devices. */
3651 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
3652 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
3653 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
3654 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
3655 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
3656 /* PCI-E devices. */
3657 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
3658 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
3659 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
3660 [RTL_GIGA_MAC_VER_10] = NULL,
3661 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
3662 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config,
3663 [RTL_GIGA_MAC_VER_13] = NULL,
3664 [RTL_GIGA_MAC_VER_14] = NULL,
3665 [RTL_GIGA_MAC_VER_15] = NULL,
3666 [RTL_GIGA_MAC_VER_16] = NULL,
3667 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
3668 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
3669 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
3670 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
3671 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
3672 [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config,
3673 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
3674 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
3675 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
3676 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
3677 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config,
3678 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
3679 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
3680 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
3681 [RTL_GIGA_MAC_VER_31] = NULL,
3682 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
3683 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
3684 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
3685 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
3686 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
3687 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
3688 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
3689 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
3690 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
3691 [RTL_GIGA_MAC_VER_41] = NULL,
3692 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
3693 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
3694 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
3695 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config,
3696 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
3697 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config,
3698 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
3699 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config,
3700 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config,
3701 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
3702 };
3703 struct rtl8169_private *tp = netdev_priv(dev);
3704
3705 if (phy_configs[tp->mac_version])
3706 phy_configs[tp->mac_version](tp);
3707 }
3708
3709 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3710 {
3711 if (!test_and_set_bit(flag, tp->wk.flags))
3712 schedule_work(&tp->wk.work);
3713 }
3714
3715 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3716 {
3717 rtl_hw_phy_config(dev);
3718
3719 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3720 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3721 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3722 netif_dbg(tp, drv, dev,
3723 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3724 RTL_W8(tp, 0x82, 0x01);
3725 }
3726
3727 /* We may have called phy_speed_down before */
3728 phy_speed_up(tp->phydev);
3729
3730 genphy_soft_reset(tp->phydev);
3731 }
3732
3733 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3734 {
3735 rtl_lock_work(tp);
3736
3737 rtl_unlock_config_regs(tp);
3738
3739 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
3740 RTL_R32(tp, MAC4);
3741
3742 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3743 RTL_R32(tp, MAC0);
3744
3745 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3746 rtl_rar_exgmac_set(tp, addr);
3747
3748 rtl_lock_config_regs(tp);
3749
3750 rtl_unlock_work(tp);
3751 }
3752
3753 static int rtl_set_mac_address(struct net_device *dev, void *p)
3754 {
3755 struct rtl8169_private *tp = netdev_priv(dev);
3756 struct device *d = tp_to_dev(tp);
3757 int ret;
3758
3759 ret = eth_mac_addr(dev, p);
3760 if (ret)
3761 return ret;
3762
3763 pm_runtime_get_noresume(d);
3764
3765 if (pm_runtime_active(d))
3766 rtl_rar_set(tp, dev->dev_addr);
3767
3768 pm_runtime_put_noidle(d);
3769
3770 return 0;
3771 }
3772
3773 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3774 {
3775 struct rtl8169_private *tp = netdev_priv(dev);
3776
3777 if (!netif_running(dev))
3778 return -ENODEV;
3779
3780 return phy_mii_ioctl(tp->phydev, ifr, cmd);
3781 }
3782
3783 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3784 {
3785 switch (tp->mac_version) {
3786 case RTL_GIGA_MAC_VER_25:
3787 case RTL_GIGA_MAC_VER_26:
3788 case RTL_GIGA_MAC_VER_29:
3789 case RTL_GIGA_MAC_VER_30:
3790 case RTL_GIGA_MAC_VER_32:
3791 case RTL_GIGA_MAC_VER_33:
3792 case RTL_GIGA_MAC_VER_34:
3793 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
3794 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
3795 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3796 break;
3797 default:
3798 break;
3799 }
3800 }
3801
3802 static void rtl_pll_power_down(struct rtl8169_private *tp)
3803 {
3804 if (r8168_check_dash(tp))
3805 return;
3806
3807 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3808 tp->mac_version == RTL_GIGA_MAC_VER_33)
3809 rtl_ephy_write(tp, 0x19, 0xff64);
3810
3811 if (device_may_wakeup(tp_to_dev(tp))) {
3812 phy_speed_down(tp->phydev, false);
3813 rtl_wol_suspend_quirk(tp);
3814 return;
3815 }
3816
3817 switch (tp->mac_version) {
3818 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
3819 case RTL_GIGA_MAC_VER_37:
3820 case RTL_GIGA_MAC_VER_39:
3821 case RTL_GIGA_MAC_VER_43:
3822 case RTL_GIGA_MAC_VER_44:
3823 case RTL_GIGA_MAC_VER_45:
3824 case RTL_GIGA_MAC_VER_46:
3825 case RTL_GIGA_MAC_VER_47:
3826 case RTL_GIGA_MAC_VER_48:
3827 case RTL_GIGA_MAC_VER_50:
3828 case RTL_GIGA_MAC_VER_51:
3829 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
3830 break;
3831 case RTL_GIGA_MAC_VER_40:
3832 case RTL_GIGA_MAC_VER_41:
3833 case RTL_GIGA_MAC_VER_49:
3834 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
3835 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
3836 break;
3837 default:
3838 break;
3839 }
3840 }
3841
3842 static void rtl_pll_power_up(struct rtl8169_private *tp)
3843 {
3844 switch (tp->mac_version) {
3845 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
3846 case RTL_GIGA_MAC_VER_37:
3847 case RTL_GIGA_MAC_VER_39:
3848 case RTL_GIGA_MAC_VER_43:
3849 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
3850 break;
3851 case RTL_GIGA_MAC_VER_44:
3852 case RTL_GIGA_MAC_VER_45:
3853 case RTL_GIGA_MAC_VER_46:
3854 case RTL_GIGA_MAC_VER_47:
3855 case RTL_GIGA_MAC_VER_48:
3856 case RTL_GIGA_MAC_VER_50:
3857 case RTL_GIGA_MAC_VER_51:
3858 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
3859 break;
3860 case RTL_GIGA_MAC_VER_40:
3861 case RTL_GIGA_MAC_VER_41:
3862 case RTL_GIGA_MAC_VER_49:
3863 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
3864 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
3865 break;
3866 default:
3867 break;
3868 }
3869
3870 phy_resume(tp->phydev);
3871 /* give MAC/PHY some time to resume */
3872 msleep(20);
3873 }
3874
3875 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3876 {
3877 switch (tp->mac_version) {
3878 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
3879 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
3880 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3881 break;
3882 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
3883 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
3884 case RTL_GIGA_MAC_VER_38:
3885 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3886 break;
3887 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
3888 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
3889 break;
3890 default:
3891 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
3892 break;
3893 }
3894 }
3895
3896 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3897 {
3898 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
3899 }
3900
3901 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3902 {
3903 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3904 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
3905 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
3906 }
3907
3908 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3909 {
3910 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3911 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
3912 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
3913 }
3914
3915 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3916 {
3917 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3918 }
3919
3920 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3921 {
3922 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3923 }
3924
3925 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3926 {
3927 RTL_W8(tp, MaxTxPacketSize, 0x3f);
3928 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3929 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
3930 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
3931 }
3932
3933 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3934 {
3935 RTL_W8(tp, MaxTxPacketSize, 0x0c);
3936 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3937 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
3938 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
3939 }
3940
3941 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3942 {
3943 rtl_tx_performance_tweak(tp,
3944 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
3945 }
3946
3947 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3948 {
3949 rtl_tx_performance_tweak(tp,
3950 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
3951 }
3952
3953 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3954 {
3955 r8168b_0_hw_jumbo_enable(tp);
3956
3957 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
3958 }
3959
3960 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3961 {
3962 r8168b_0_hw_jumbo_disable(tp);
3963
3964 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
3965 }
3966
3967 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3968 {
3969 rtl_unlock_config_regs(tp);
3970 switch (tp->mac_version) {
3971 case RTL_GIGA_MAC_VER_11:
3972 r8168b_0_hw_jumbo_enable(tp);
3973 break;
3974 case RTL_GIGA_MAC_VER_12:
3975 case RTL_GIGA_MAC_VER_17:
3976 r8168b_1_hw_jumbo_enable(tp);
3977 break;
3978 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
3979 r8168c_hw_jumbo_enable(tp);
3980 break;
3981 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
3982 r8168dp_hw_jumbo_enable(tp);
3983 break;
3984 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
3985 r8168e_hw_jumbo_enable(tp);
3986 break;
3987 default:
3988 break;
3989 }
3990 rtl_lock_config_regs(tp);
3991 }
3992
3993 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3994 {
3995 rtl_unlock_config_regs(tp);
3996 switch (tp->mac_version) {
3997 case RTL_GIGA_MAC_VER_11:
3998 r8168b_0_hw_jumbo_disable(tp);
3999 break;
4000 case RTL_GIGA_MAC_VER_12:
4001 case RTL_GIGA_MAC_VER_17:
4002 r8168b_1_hw_jumbo_disable(tp);
4003 break;
4004 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
4005 r8168c_hw_jumbo_disable(tp);
4006 break;
4007 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
4008 r8168dp_hw_jumbo_disable(tp);
4009 break;
4010 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
4011 r8168e_hw_jumbo_disable(tp);
4012 break;
4013 default:
4014 break;
4015 }
4016 rtl_lock_config_regs(tp);
4017 }
4018
4019 DECLARE_RTL_COND(rtl_chipcmd_cond)
4020 {
4021 return RTL_R8(tp, ChipCmd) & CmdReset;
4022 }
4023
4024 static void rtl_hw_reset(struct rtl8169_private *tp)
4025 {
4026 RTL_W8(tp, ChipCmd, CmdReset);
4027
4028 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4029 }
4030
4031 static void rtl_request_firmware(struct rtl8169_private *tp)
4032 {
4033 struct rtl_fw *rtl_fw;
4034
4035 /* firmware loaded already or no firmware available */
4036 if (tp->rtl_fw || !tp->fw_name)
4037 return;
4038
4039 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4040 if (!rtl_fw) {
4041 netif_warn(tp, ifup, tp->dev, "Unable to load firmware, out of memory\n");
4042 return;
4043 }
4044
4045 rtl_fw->phy_write = rtl_writephy;
4046 rtl_fw->phy_read = rtl_readphy;
4047 rtl_fw->mac_mcu_write = mac_mcu_write;
4048 rtl_fw->mac_mcu_read = mac_mcu_read;
4049 rtl_fw->fw_name = tp->fw_name;
4050 rtl_fw->dev = tp_to_dev(tp);
4051
4052 if (rtl_fw_request_firmware(rtl_fw))
4053 kfree(rtl_fw);
4054 else
4055 tp->rtl_fw = rtl_fw;
4056 }
4057
4058 static void rtl_rx_close(struct rtl8169_private *tp)
4059 {
4060 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4061 }
4062
4063 DECLARE_RTL_COND(rtl_npq_cond)
4064 {
4065 return RTL_R8(tp, TxPoll) & NPQ;
4066 }
4067
4068 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4069 {
4070 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4071 }
4072
4073 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4074 {
4075 /* Disable interrupts */
4076 rtl8169_irq_mask_and_ack(tp);
4077
4078 rtl_rx_close(tp);
4079
4080 switch (tp->mac_version) {
4081 case RTL_GIGA_MAC_VER_27:
4082 case RTL_GIGA_MAC_VER_28:
4083 case RTL_GIGA_MAC_VER_31:
4084 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4085 break;
4086 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4087 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4088 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4089 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4090 break;
4091 default:
4092 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4093 udelay(100);
4094 break;
4095 }
4096
4097 rtl_hw_reset(tp);
4098 }
4099
4100 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4101 {
4102 u32 val = TX_DMA_BURST << TxDMAShift |
4103 InterFrameGap << TxInterFrameGapShift;
4104
4105 if (rtl_is_8168evl_up(tp))
4106 val |= TXCFG_AUTO_FIFO;
4107
4108 RTL_W32(tp, TxConfig, val);
4109 }
4110
4111 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4112 {
4113 /* Low hurts. Let's disable the filtering. */
4114 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4115 }
4116
4117 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4118 {
4119 /*
4120 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4121 * register to be written before TxDescAddrLow to work.
4122 * Switching from MMIO to I/O access fixes the issue as well.
4123 */
4124 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4125 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4126 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4127 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4128 }
4129
4130 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4131 {
4132 u32 val;
4133
4134 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4135 val = 0x000fff00;
4136 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4137 val = 0x00ffff00;
4138 else
4139 return;
4140
4141 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4142 val |= 0xff;
4143
4144 RTL_W32(tp, 0x7c, val);
4145 }
4146
4147 static void rtl_set_rx_mode(struct net_device *dev)
4148 {
4149 struct rtl8169_private *tp = netdev_priv(dev);
4150 u32 mc_filter[2]; /* Multicast hash filter */
4151 int rx_mode;
4152 u32 tmp = 0;
4153
4154 if (dev->flags & IFF_PROMISC) {
4155 /* Unconditionally log net taps. */
4156 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4157 rx_mode =
4158 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4159 AcceptAllPhys;
4160 mc_filter[1] = mc_filter[0] = 0xffffffff;
4161 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4162 (dev->flags & IFF_ALLMULTI)) {
4163 /* Too many to filter perfectly -- accept all multicasts. */
4164 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4165 mc_filter[1] = mc_filter[0] = 0xffffffff;
4166 } else {
4167 struct netdev_hw_addr *ha;
4168
4169 rx_mode = AcceptBroadcast | AcceptMyPhys;
4170 mc_filter[1] = mc_filter[0] = 0;
4171 netdev_for_each_mc_addr(ha, dev) {
4172 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4173 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4174 rx_mode |= AcceptMulticast;
4175 }
4176 }
4177
4178 if (dev->features & NETIF_F_RXALL)
4179 rx_mode |= (AcceptErr | AcceptRunt);
4180
4181 tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4182
4183 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4184 u32 data = mc_filter[0];
4185
4186 mc_filter[0] = swab32(mc_filter[1]);
4187 mc_filter[1] = swab32(data);
4188 }
4189
4190 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4191 mc_filter[1] = mc_filter[0] = 0xffffffff;
4192
4193 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4194 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4195
4196 RTL_W32(tp, RxConfig, tmp);
4197 }
4198
4199 DECLARE_RTL_COND(rtl_csiar_cond)
4200 {
4201 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4202 }
4203
4204 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4205 {
4206 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4207
4208 RTL_W32(tp, CSIDR, value);
4209 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4210 CSIAR_BYTE_ENABLE | func << 16);
4211
4212 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4213 }
4214
4215 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4216 {
4217 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4218
4219 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4220 CSIAR_BYTE_ENABLE);
4221
4222 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4223 RTL_R32(tp, CSIDR) : ~0;
4224 }
4225
4226 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4227 {
4228 struct pci_dev *pdev = tp->pci_dev;
4229 u32 csi;
4230
4231 /* According to Realtek the value at config space address 0x070f
4232 * controls the L0s/L1 entrance latency. We try standard ECAM access
4233 * first and if it fails fall back to CSI.
4234 */
4235 if (pdev->cfg_size > 0x070f &&
4236 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4237 return;
4238
4239 netdev_notice_once(tp->dev,
4240 "No native access to PCI extended config space, falling back to CSI\n");
4241 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4242 rtl_csi_write(tp, 0x070c, csi | val << 24);
4243 }
4244
4245 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4246 {
4247 rtl_csi_access_enable(tp, 0x27);
4248 }
4249
4250 struct ephy_info {
4251 unsigned int offset;
4252 u16 mask;
4253 u16 bits;
4254 };
4255
4256 static void __rtl_ephy_init(struct rtl8169_private *tp,
4257 const struct ephy_info *e, int len)
4258 {
4259 u16 w;
4260
4261 while (len-- > 0) {
4262 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4263 rtl_ephy_write(tp, e->offset, w);
4264 e++;
4265 }
4266 }
4267
4268 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
4269
4270 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4271 {
4272 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4273 PCI_EXP_LNKCTL_CLKREQ_EN);
4274 }
4275
4276 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4277 {
4278 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4279 PCI_EXP_LNKCTL_CLKREQ_EN);
4280 }
4281
4282 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
4283 {
4284 /* work around an issue when PCI reset occurs during L2/L3 state */
4285 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
4286 }
4287
4288 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4289 {
4290 /* Don't enable ASPM in the chip if OS can't control ASPM */
4291 if (enable && tp->aspm_manageable) {
4292 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4293 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4294 } else {
4295 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4296 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4297 }
4298
4299 udelay(10);
4300 }
4301
4302 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
4303 u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
4304 {
4305 /* Usage of dynamic vs. static FIFO is controlled by bit
4306 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
4307 */
4308 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
4309 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
4310 }
4311
4312 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
4313 u8 low, u8 high)
4314 {
4315 /* FIFO thresholds for pause flow control */
4316 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
4317 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
4318 }
4319
4320 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4321 {
4322 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4323
4324 if (tp->dev->mtu <= ETH_DATA_LEN) {
4325 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4326 PCI_EXP_DEVCTL_NOSNOOP_EN);
4327 }
4328 }
4329
4330 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4331 {
4332 rtl_hw_start_8168bb(tp);
4333
4334 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4335 }
4336
4337 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4338 {
4339 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4340
4341 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4342
4343 if (tp->dev->mtu <= ETH_DATA_LEN)
4344 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4345
4346 rtl_disable_clock_request(tp);
4347 }
4348
4349 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4350 {
4351 static const struct ephy_info e_info_8168cp[] = {
4352 { 0x01, 0, 0x0001 },
4353 { 0x02, 0x0800, 0x1000 },
4354 { 0x03, 0, 0x0042 },
4355 { 0x06, 0x0080, 0x0000 },
4356 { 0x07, 0, 0x2000 }
4357 };
4358
4359 rtl_set_def_aspm_entry_latency(tp);
4360
4361 rtl_ephy_init(tp, e_info_8168cp);
4362
4363 __rtl_hw_start_8168cp(tp);
4364 }
4365
4366 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4367 {
4368 rtl_set_def_aspm_entry_latency(tp);
4369
4370 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4371
4372 if (tp->dev->mtu <= ETH_DATA_LEN)
4373 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4374 }
4375
4376 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4377 {
4378 rtl_set_def_aspm_entry_latency(tp);
4379
4380 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4381
4382 /* Magic. */
4383 RTL_W8(tp, DBG_REG, 0x20);
4384
4385 if (tp->dev->mtu <= ETH_DATA_LEN)
4386 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4387 }
4388
4389 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4390 {
4391 static const struct ephy_info e_info_8168c_1[] = {
4392 { 0x02, 0x0800, 0x1000 },
4393 { 0x03, 0, 0x0002 },
4394 { 0x06, 0x0080, 0x0000 }
4395 };
4396
4397 rtl_set_def_aspm_entry_latency(tp);
4398
4399 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4400
4401 rtl_ephy_init(tp, e_info_8168c_1);
4402
4403 __rtl_hw_start_8168cp(tp);
4404 }
4405
4406 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4407 {
4408 static const struct ephy_info e_info_8168c_2[] = {
4409 { 0x01, 0, 0x0001 },
4410 { 0x03, 0x0400, 0x0220 }
4411 };
4412
4413 rtl_set_def_aspm_entry_latency(tp);
4414
4415 rtl_ephy_init(tp, e_info_8168c_2);
4416
4417 __rtl_hw_start_8168cp(tp);
4418 }
4419
4420 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4421 {
4422 rtl_hw_start_8168c_2(tp);
4423 }
4424
4425 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4426 {
4427 rtl_set_def_aspm_entry_latency(tp);
4428
4429 __rtl_hw_start_8168cp(tp);
4430 }
4431
4432 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4433 {
4434 rtl_set_def_aspm_entry_latency(tp);
4435
4436 rtl_disable_clock_request(tp);
4437
4438 if (tp->dev->mtu <= ETH_DATA_LEN)
4439 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4440 }
4441
4442 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4443 {
4444 rtl_set_def_aspm_entry_latency(tp);
4445
4446 if (tp->dev->mtu <= ETH_DATA_LEN)
4447 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4448
4449 rtl_disable_clock_request(tp);
4450 }
4451
4452 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4453 {
4454 static const struct ephy_info e_info_8168d_4[] = {
4455 { 0x0b, 0x0000, 0x0048 },
4456 { 0x19, 0x0020, 0x0050 },
4457 { 0x0c, 0x0100, 0x0020 }
4458 };
4459
4460 rtl_set_def_aspm_entry_latency(tp);
4461
4462 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4463
4464 rtl_ephy_init(tp, e_info_8168d_4);
4465
4466 rtl_enable_clock_request(tp);
4467 }
4468
4469 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4470 {
4471 static const struct ephy_info e_info_8168e_1[] = {
4472 { 0x00, 0x0200, 0x0100 },
4473 { 0x00, 0x0000, 0x0004 },
4474 { 0x06, 0x0002, 0x0001 },
4475 { 0x06, 0x0000, 0x0030 },
4476 { 0x07, 0x0000, 0x2000 },
4477 { 0x00, 0x0000, 0x0020 },
4478 { 0x03, 0x5800, 0x2000 },
4479 { 0x03, 0x0000, 0x0001 },
4480 { 0x01, 0x0800, 0x1000 },
4481 { 0x07, 0x0000, 0x4000 },
4482 { 0x1e, 0x0000, 0x2000 },
4483 { 0x19, 0xffff, 0xfe6c },
4484 { 0x0a, 0x0000, 0x0040 }
4485 };
4486
4487 rtl_set_def_aspm_entry_latency(tp);
4488
4489 rtl_ephy_init(tp, e_info_8168e_1);
4490
4491 if (tp->dev->mtu <= ETH_DATA_LEN)
4492 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4493
4494 rtl_disable_clock_request(tp);
4495
4496 /* Reset tx FIFO pointer */
4497 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4498 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4499
4500 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4501 }
4502
4503 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4504 {
4505 static const struct ephy_info e_info_8168e_2[] = {
4506 { 0x09, 0x0000, 0x0080 },
4507 { 0x19, 0x0000, 0x0224 }
4508 };
4509
4510 rtl_set_def_aspm_entry_latency(tp);
4511
4512 rtl_ephy_init(tp, e_info_8168e_2);
4513
4514 if (tp->dev->mtu <= ETH_DATA_LEN)
4515 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4516
4517 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4518 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4519 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4520 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4521 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
4522 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4523 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4524
4525 rtl_disable_clock_request(tp);
4526
4527 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4528
4529 rtl8168_config_eee_mac(tp);
4530
4531 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4532 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4533 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4534
4535 rtl_hw_aspm_clkreq_enable(tp, true);
4536 }
4537
4538 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
4539 {
4540 rtl_set_def_aspm_entry_latency(tp);
4541
4542 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4543
4544 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4545 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4546 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4547 rtl_reset_packet_filter(tp);
4548 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4549 rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));
4550 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4551 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
4552
4553 rtl_disable_clock_request(tp);
4554
4555 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4556 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4557 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4558 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4559
4560 rtl8168_config_eee_mac(tp);
4561 }
4562
4563 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
4564 {
4565 static const struct ephy_info e_info_8168f_1[] = {
4566 { 0x06, 0x00c0, 0x0020 },
4567 { 0x08, 0x0001, 0x0002 },
4568 { 0x09, 0x0000, 0x0080 },
4569 { 0x19, 0x0000, 0x0224 }
4570 };
4571
4572 rtl_hw_start_8168f(tp);
4573
4574 rtl_ephy_init(tp, e_info_8168f_1);
4575
4576 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4577 }
4578
4579 static void rtl_hw_start_8411(struct rtl8169_private *tp)
4580 {
4581 static const struct ephy_info e_info_8168f_1[] = {
4582 { 0x06, 0x00c0, 0x0020 },
4583 { 0x0f, 0xffff, 0x5200 },
4584 { 0x1e, 0x0000, 0x4000 },
4585 { 0x19, 0x0000, 0x0224 }
4586 };
4587
4588 rtl_hw_start_8168f(tp);
4589 rtl_pcie_state_l2l3_disable(tp);
4590
4591 rtl_ephy_init(tp, e_info_8168f_1);
4592
4593 rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);
4594 }
4595
4596 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
4597 {
4598 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4599 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4600
4601 rtl_set_def_aspm_entry_latency(tp);
4602
4603 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4604
4605 rtl_reset_packet_filter(tp);
4606 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
4607
4608 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4609
4610 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4611 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4612
4613 rtl8168_config_eee_mac(tp);
4614
4615 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
4616 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4617
4618 rtl_pcie_state_l2l3_disable(tp);
4619 }
4620
4621 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
4622 {
4623 static const struct ephy_info e_info_8168g_1[] = {
4624 { 0x00, 0x0000, 0x0008 },
4625 { 0x0c, 0x37d0, 0x0820 },
4626 { 0x1e, 0x0000, 0x0001 },
4627 { 0x19, 0x8000, 0x0000 }
4628 };
4629
4630 rtl_hw_start_8168g(tp);
4631
4632 /* disable aspm and clock request before access ephy */
4633 rtl_hw_aspm_clkreq_enable(tp, false);
4634 rtl_ephy_init(tp, e_info_8168g_1);
4635 rtl_hw_aspm_clkreq_enable(tp, true);
4636 }
4637
4638 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
4639 {
4640 static const struct ephy_info e_info_8168g_2[] = {
4641 { 0x00, 0x0000, 0x0008 },
4642 { 0x0c, 0x3df0, 0x0200 },
4643 { 0x19, 0xffff, 0xfc00 },
4644 { 0x1e, 0xffff, 0x20eb }
4645 };
4646
4647 rtl_hw_start_8168g(tp);
4648
4649 /* disable aspm and clock request before access ephy */
4650 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4651 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4652 rtl_ephy_init(tp, e_info_8168g_2);
4653 }
4654
4655 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
4656 {
4657 static const struct ephy_info e_info_8411_2[] = {
4658 { 0x00, 0x0000, 0x0008 },
4659 { 0x0c, 0x3df0, 0x0200 },
4660 { 0x0f, 0xffff, 0x5200 },
4661 { 0x19, 0x0020, 0x0000 },
4662 { 0x1e, 0x0000, 0x2000 }
4663 };
4664
4665 rtl_hw_start_8168g(tp);
4666
4667 /* disable aspm and clock request before access ephy */
4668 rtl_hw_aspm_clkreq_enable(tp, false);
4669 rtl_ephy_init(tp, e_info_8411_2);
4670
4671 /* The following Realtek-provided magic fixes an issue with the RX unit
4672 * getting confused after the PHY having been powered-down.
4673 */
4674 r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
4675 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
4676 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
4677 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
4678 r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
4679 r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
4680 r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
4681 r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
4682 mdelay(3);
4683 r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
4684
4685 r8168_mac_ocp_write(tp, 0xF800, 0xE008);
4686 r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
4687 r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
4688 r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
4689 r8168_mac_ocp_write(tp, 0xF808, 0xE027);
4690 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
4691 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
4692 r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
4693 r8168_mac_ocp_write(tp, 0xF810, 0xC602);
4694 r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
4695 r8168_mac_ocp_write(tp, 0xF814, 0x0000);
4696 r8168_mac_ocp_write(tp, 0xF816, 0xC502);
4697 r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
4698 r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
4699 r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
4700 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
4701 r8168_mac_ocp_write(tp, 0xF820, 0x080A);
4702 r8168_mac_ocp_write(tp, 0xF822, 0x6420);
4703 r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
4704 r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
4705 r8168_mac_ocp_write(tp, 0xF828, 0xC516);
4706 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
4707 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
4708 r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
4709 r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
4710 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
4711 r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
4712 r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
4713 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
4714 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
4715 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
4716 r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
4717 r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
4718 r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
4719 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
4720 r8168_mac_ocp_write(tp, 0xF846, 0xC404);
4721 r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
4722 r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
4723 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
4724 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
4725 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
4726 r8168_mac_ocp_write(tp, 0xF852, 0xE434);
4727 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
4728 r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
4729 r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
4730 r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
4731 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
4732 r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
4733 r8168_mac_ocp_write(tp, 0xF860, 0xF007);
4734 r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
4735 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
4736 r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
4737 r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
4738 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
4739 r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
4740 r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
4741 r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
4742 r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
4743 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
4744 r8168_mac_ocp_write(tp, 0xF876, 0xC516);
4745 r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
4746 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
4747 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
4748 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
4749 r8168_mac_ocp_write(tp, 0xF880, 0xC512);
4750 r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
4751 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
4752 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
4753 r8168_mac_ocp_write(tp, 0xF888, 0x483F);
4754 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
4755 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
4756 r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
4757 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
4758 r8168_mac_ocp_write(tp, 0xF892, 0xC505);
4759 r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
4760 r8168_mac_ocp_write(tp, 0xF896, 0xC502);
4761 r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
4762 r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
4763 r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
4764 r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
4765 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
4766 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
4767 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
4768 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
4769 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
4770 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
4771 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
4772 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
4773 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
4774 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
4775 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
4776 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
4777 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
4778 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
4779 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
4780 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
4781 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
4782 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
4783 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
4784 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
4785 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
4786 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
4787 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
4788 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
4789 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
4790 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
4791 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
4792 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
4793 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
4794 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
4795 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
4796
4797 r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
4798
4799 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
4800 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
4801 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
4802 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
4803 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
4804 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
4805 r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
4806
4807 rtl_hw_aspm_clkreq_enable(tp, true);
4808 }
4809
4810 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
4811 {
4812 int rg_saw_cnt;
4813 u32 data;
4814 static const struct ephy_info e_info_8168h_1[] = {
4815 { 0x1e, 0x0800, 0x0001 },
4816 { 0x1d, 0x0000, 0x0800 },
4817 { 0x05, 0xffff, 0x2089 },
4818 { 0x06, 0xffff, 0x5881 },
4819 { 0x04, 0xffff, 0x154a },
4820 { 0x01, 0xffff, 0x068b }
4821 };
4822
4823 /* disable aspm and clock request before access ephy */
4824 rtl_hw_aspm_clkreq_enable(tp, false);
4825 rtl_ephy_init(tp, e_info_8168h_1);
4826
4827 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4828 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4829
4830 rtl_set_def_aspm_entry_latency(tp);
4831
4832 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4833
4834 rtl_reset_packet_filter(tp);
4835
4836 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
4837
4838 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);
4839
4840 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
4841
4842 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4843
4844 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4845 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4846
4847 rtl8168_config_eee_mac(tp);
4848
4849 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4850 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4851
4852 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
4853
4854 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4855
4856 rtl_pcie_state_l2l3_disable(tp);
4857
4858 rtl_writephy(tp, 0x1f, 0x0c42);
4859 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
4860 rtl_writephy(tp, 0x1f, 0x0000);
4861 if (rg_saw_cnt > 0) {
4862 u16 sw_cnt_1ms_ini;
4863
4864 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
4865 sw_cnt_1ms_ini &= 0x0fff;
4866 data = r8168_mac_ocp_read(tp, 0xd412);
4867 data &= ~0x0fff;
4868 data |= sw_cnt_1ms_ini;
4869 r8168_mac_ocp_write(tp, 0xd412, data);
4870 }
4871
4872 data = r8168_mac_ocp_read(tp, 0xe056);
4873 data &= ~0xf0;
4874 data |= 0x70;
4875 r8168_mac_ocp_write(tp, 0xe056, data);
4876
4877 data = r8168_mac_ocp_read(tp, 0xe052);
4878 data &= ~0x6000;
4879 data |= 0x8008;
4880 r8168_mac_ocp_write(tp, 0xe052, data);
4881
4882 data = r8168_mac_ocp_read(tp, 0xe0d6);
4883 data &= ~0x01ff;
4884 data |= 0x017f;
4885 r8168_mac_ocp_write(tp, 0xe0d6, data);
4886
4887 data = r8168_mac_ocp_read(tp, 0xd420);
4888 data &= ~0x0fff;
4889 data |= 0x047f;
4890 r8168_mac_ocp_write(tp, 0xd420, data);
4891
4892 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
4893 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
4894 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
4895 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
4896
4897 rtl_hw_aspm_clkreq_enable(tp, true);
4898 }
4899
4900 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
4901 {
4902 rtl8168ep_stop_cmac(tp);
4903
4904 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4905 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
4906
4907 rtl_set_def_aspm_entry_latency(tp);
4908
4909 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4910
4911 rtl_reset_packet_filter(tp);
4912
4913 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
4914
4915 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
4916
4917 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4918
4919 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4920 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4921
4922 rtl8168_config_eee_mac(tp);
4923
4924 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
4925
4926 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
4927
4928 rtl_pcie_state_l2l3_disable(tp);
4929 }
4930
4931 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
4932 {
4933 static const struct ephy_info e_info_8168ep_1[] = {
4934 { 0x00, 0xffff, 0x10ab },
4935 { 0x06, 0xffff, 0xf030 },
4936 { 0x08, 0xffff, 0x2006 },
4937 { 0x0d, 0xffff, 0x1666 },
4938 { 0x0c, 0x3ff0, 0x0000 }
4939 };
4940
4941 /* disable aspm and clock request before access ephy */
4942 rtl_hw_aspm_clkreq_enable(tp, false);
4943 rtl_ephy_init(tp, e_info_8168ep_1);
4944
4945 rtl_hw_start_8168ep(tp);
4946
4947 rtl_hw_aspm_clkreq_enable(tp, true);
4948 }
4949
4950 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
4951 {
4952 static const struct ephy_info e_info_8168ep_2[] = {
4953 { 0x00, 0xffff, 0x10a3 },
4954 { 0x19, 0xffff, 0xfc00 },
4955 { 0x1e, 0xffff, 0x20ea }
4956 };
4957
4958 /* disable aspm and clock request before access ephy */
4959 rtl_hw_aspm_clkreq_enable(tp, false);
4960 rtl_ephy_init(tp, e_info_8168ep_2);
4961
4962 rtl_hw_start_8168ep(tp);
4963
4964 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4965 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4966
4967 rtl_hw_aspm_clkreq_enable(tp, true);
4968 }
4969
4970 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
4971 {
4972 u32 data;
4973 static const struct ephy_info e_info_8168ep_3[] = {
4974 { 0x00, 0xffff, 0x10a3 },
4975 { 0x19, 0xffff, 0x7c00 },
4976 { 0x1e, 0xffff, 0x20eb },
4977 { 0x0d, 0xffff, 0x1666 }
4978 };
4979
4980 /* disable aspm and clock request before access ephy */
4981 rtl_hw_aspm_clkreq_enable(tp, false);
4982 rtl_ephy_init(tp, e_info_8168ep_3);
4983
4984 rtl_hw_start_8168ep(tp);
4985
4986 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4987 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4988
4989 data = r8168_mac_ocp_read(tp, 0xd3e2);
4990 data &= 0xf000;
4991 data |= 0x0271;
4992 r8168_mac_ocp_write(tp, 0xd3e2, data);
4993
4994 data = r8168_mac_ocp_read(tp, 0xd3e4);
4995 data &= 0xff00;
4996 r8168_mac_ocp_write(tp, 0xd3e4, data);
4997
4998 data = r8168_mac_ocp_read(tp, 0xe860);
4999 data |= 0x0080;
5000 r8168_mac_ocp_write(tp, 0xe860, data);
5001
5002 rtl_hw_aspm_clkreq_enable(tp, true);
5003 }
5004
5005 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5006 {
5007 static const struct ephy_info e_info_8102e_1[] = {
5008 { 0x01, 0, 0x6e65 },
5009 { 0x02, 0, 0x091f },
5010 { 0x03, 0, 0xc2f9 },
5011 { 0x06, 0, 0xafb5 },
5012 { 0x07, 0, 0x0e00 },
5013 { 0x19, 0, 0xec80 },
5014 { 0x01, 0, 0x2e65 },
5015 { 0x01, 0, 0x6e65 }
5016 };
5017 u8 cfg1;
5018
5019 rtl_set_def_aspm_entry_latency(tp);
5020
5021 RTL_W8(tp, DBG_REG, FIX_NAK_1);
5022
5023 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5024
5025 RTL_W8(tp, Config1,
5026 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5027 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5028
5029 cfg1 = RTL_R8(tp, Config1);
5030 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5031 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5032
5033 rtl_ephy_init(tp, e_info_8102e_1);
5034 }
5035
5036 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5037 {
5038 rtl_set_def_aspm_entry_latency(tp);
5039
5040 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5041
5042 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5043 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5044 }
5045
5046 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5047 {
5048 rtl_hw_start_8102e_2(tp);
5049
5050 rtl_ephy_write(tp, 0x03, 0xc2f9);
5051 }
5052
5053 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5054 {
5055 static const struct ephy_info e_info_8105e_1[] = {
5056 { 0x07, 0, 0x4000 },
5057 { 0x19, 0, 0x0200 },
5058 { 0x19, 0, 0x0020 },
5059 { 0x1e, 0, 0x2000 },
5060 { 0x03, 0, 0x0001 },
5061 { 0x19, 0, 0x0100 },
5062 { 0x19, 0, 0x0004 },
5063 { 0x0a, 0, 0x0020 }
5064 };
5065
5066 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5067 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5068
5069 /* Disable Early Tally Counter */
5070 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5071
5072 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5073 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5074
5075 rtl_ephy_init(tp, e_info_8105e_1);
5076
5077 rtl_pcie_state_l2l3_disable(tp);
5078 }
5079
5080 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5081 {
5082 rtl_hw_start_8105e_1(tp);
5083 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5084 }
5085
5086 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5087 {
5088 static const struct ephy_info e_info_8402[] = {
5089 { 0x19, 0xffff, 0xff64 },
5090 { 0x1e, 0, 0x4000 }
5091 };
5092
5093 rtl_set_def_aspm_entry_latency(tp);
5094
5095 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5096 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5097
5098 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5099
5100 rtl_ephy_init(tp, e_info_8402);
5101
5102 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5103
5104 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
5105 rtl_reset_packet_filter(tp);
5106 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5107 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5108 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
5109
5110 rtl_pcie_state_l2l3_disable(tp);
5111 }
5112
5113 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5114 {
5115 rtl_hw_aspm_clkreq_enable(tp, false);
5116
5117 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5118 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5119
5120 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5121 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5122 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5123
5124 rtl_pcie_state_l2l3_disable(tp);
5125 rtl_hw_aspm_clkreq_enable(tp, true);
5126 }
5127
5128 static void rtl_hw_config(struct rtl8169_private *tp)
5129 {
5130 static const rtl_generic_fct hw_configs[] = {
5131 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
5132 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
5133 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
5134 [RTL_GIGA_MAC_VER_10] = NULL,
5135 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168bb,
5136 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168bef,
5137 [RTL_GIGA_MAC_VER_13] = NULL,
5138 [RTL_GIGA_MAC_VER_14] = NULL,
5139 [RTL_GIGA_MAC_VER_15] = NULL,
5140 [RTL_GIGA_MAC_VER_16] = NULL,
5141 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168bef,
5142 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
5143 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
5144 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
5145 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
5146 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
5147 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
5148 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
5149 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
5150 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
5151 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
5152 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
5153 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
5154 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
5155 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168dp,
5156 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
5157 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
5158 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
5159 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
5160 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
5161 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
5162 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
5163 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
5164 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
5165 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
5166 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
5167 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
5168 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
5169 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
5170 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
5171 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
5172 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
5173 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
5174 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
5175 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
5176 };
5177
5178 if (hw_configs[tp->mac_version])
5179 hw_configs[tp->mac_version](tp);
5180 }
5181
5182 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5183 {
5184 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5185 tp->mac_version == RTL_GIGA_MAC_VER_16)
5186 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5187 PCI_EXP_DEVCTL_NOSNOOP_EN);
5188
5189 if (rtl_is_8168evl_up(tp))
5190 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5191 else
5192 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5193
5194 rtl_hw_config(tp);
5195 }
5196
5197 static void rtl_hw_start_8169(struct rtl8169_private *tp)
5198 {
5199 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5200 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
5201
5202 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
5203
5204 tp->cp_cmd |= PCIMulRW;
5205
5206 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5207 tp->mac_version == RTL_GIGA_MAC_VER_03) {
5208 netif_dbg(tp, drv, tp->dev,
5209 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
5210 tp->cp_cmd |= (1 << 14);
5211 }
5212
5213 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5214
5215 rtl8169_set_magic_reg(tp, tp->mac_version);
5216
5217 RTL_W32(tp, RxMissed, 0);
5218 }
5219
5220 static void rtl_hw_start(struct rtl8169_private *tp)
5221 {
5222 rtl_unlock_config_regs(tp);
5223
5224 tp->cp_cmd &= CPCMD_MASK;
5225 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5226
5227 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5228 rtl_hw_start_8169(tp);
5229 else
5230 rtl_hw_start_8168(tp);
5231
5232 rtl_set_rx_max_size(tp);
5233 rtl_set_rx_tx_desc_registers(tp);
5234 rtl_lock_config_regs(tp);
5235
5236 /* disable interrupt coalescing */
5237 RTL_W16(tp, IntrMitigate, 0x0000);
5238 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5239 RTL_R8(tp, IntrMask);
5240 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
5241 rtl_init_rxcfg(tp);
5242 rtl_set_tx_config_registers(tp);
5243
5244 rtl_set_rx_mode(tp->dev);
5245 /* no early-rx interrupts */
5246 RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
5247 rtl_irq_enable(tp);
5248 }
5249
5250 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5251 {
5252 struct rtl8169_private *tp = netdev_priv(dev);
5253
5254 if (new_mtu > ETH_DATA_LEN)
5255 rtl_hw_jumbo_enable(tp);
5256 else
5257 rtl_hw_jumbo_disable(tp);
5258
5259 dev->mtu = new_mtu;
5260 netdev_update_features(dev);
5261
5262 return 0;
5263 }
5264
5265 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5266 {
5267 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5268 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5269 }
5270
5271 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5272 void **data_buff, struct RxDesc *desc)
5273 {
5274 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5275 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5276
5277 kfree(*data_buff);
5278 *data_buff = NULL;
5279 rtl8169_make_unusable_by_asic(desc);
5280 }
5281
5282 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5283 {
5284 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5285
5286 /* Force memory writes to complete before releasing descriptor */
5287 dma_wmb();
5288
5289 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5290 }
5291
5292 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5293 struct RxDesc *desc)
5294 {
5295 void *data;
5296 dma_addr_t mapping;
5297 struct device *d = tp_to_dev(tp);
5298 int node = dev_to_node(d);
5299
5300 data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5301 if (!data)
5302 return NULL;
5303
5304 /* Memory should be properly aligned, but better check. */
5305 if (!IS_ALIGNED((unsigned long)data, 8)) {
5306 netdev_err_once(tp->dev, "RX buffer not 8-byte-aligned\n");
5307 goto err_out;
5308 }
5309
5310 mapping = dma_map_single(d, data, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5311 if (unlikely(dma_mapping_error(d, mapping))) {
5312 if (net_ratelimit())
5313 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5314 goto err_out;
5315 }
5316
5317 desc->addr = cpu_to_le64(mapping);
5318 rtl8169_mark_to_asic(desc);
5319 return data;
5320
5321 err_out:
5322 kfree(data);
5323 return NULL;
5324 }
5325
5326 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5327 {
5328 unsigned int i;
5329
5330 for (i = 0; i < NUM_RX_DESC; i++) {
5331 if (tp->Rx_databuff[i]) {
5332 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5333 tp->RxDescArray + i);
5334 }
5335 }
5336 }
5337
5338 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5339 {
5340 desc->opts1 |= cpu_to_le32(RingEnd);
5341 }
5342
5343 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5344 {
5345 unsigned int i;
5346
5347 for (i = 0; i < NUM_RX_DESC; i++) {
5348 void *data;
5349
5350 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5351 if (!data) {
5352 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5353 goto err_out;
5354 }
5355 tp->Rx_databuff[i] = data;
5356 }
5357
5358 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5359 return 0;
5360
5361 err_out:
5362 rtl8169_rx_clear(tp);
5363 return -ENOMEM;
5364 }
5365
5366 static int rtl8169_init_ring(struct rtl8169_private *tp)
5367 {
5368 rtl8169_init_ring_indexes(tp);
5369
5370 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5371 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5372
5373 return rtl8169_rx_fill(tp);
5374 }
5375
5376 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5377 struct TxDesc *desc)
5378 {
5379 unsigned int len = tx_skb->len;
5380
5381 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5382
5383 desc->opts1 = 0x00;
5384 desc->opts2 = 0x00;
5385 desc->addr = 0x00;
5386 tx_skb->len = 0;
5387 }
5388
5389 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5390 unsigned int n)
5391 {
5392 unsigned int i;
5393
5394 for (i = 0; i < n; i++) {
5395 unsigned int entry = (start + i) % NUM_TX_DESC;
5396 struct ring_info *tx_skb = tp->tx_skb + entry;
5397 unsigned int len = tx_skb->len;
5398
5399 if (len) {
5400 struct sk_buff *skb = tx_skb->skb;
5401
5402 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5403 tp->TxDescArray + entry);
5404 if (skb) {
5405 dev_consume_skb_any(skb);
5406 tx_skb->skb = NULL;
5407 }
5408 }
5409 }
5410 }
5411
5412 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5413 {
5414 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5415 tp->cur_tx = tp->dirty_tx = 0;
5416 netdev_reset_queue(tp->dev);
5417 }
5418
5419 static void rtl_reset_work(struct rtl8169_private *tp)
5420 {
5421 struct net_device *dev = tp->dev;
5422 int i;
5423
5424 napi_disable(&tp->napi);
5425 netif_stop_queue(dev);
5426 synchronize_rcu();
5427
5428 rtl8169_hw_reset(tp);
5429
5430 for (i = 0; i < NUM_RX_DESC; i++)
5431 rtl8169_mark_to_asic(tp->RxDescArray + i);
5432
5433 rtl8169_tx_clear(tp);
5434 rtl8169_init_ring_indexes(tp);
5435
5436 napi_enable(&tp->napi);
5437 rtl_hw_start(tp);
5438 netif_wake_queue(dev);
5439 }
5440
5441 static void rtl8169_tx_timeout(struct net_device *dev)
5442 {
5443 struct rtl8169_private *tp = netdev_priv(dev);
5444
5445 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5446 }
5447
5448 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5449 {
5450 u32 status = opts0 | len;
5451
5452 if (entry == NUM_TX_DESC - 1)
5453 status |= RingEnd;
5454
5455 return cpu_to_le32(status);
5456 }
5457
5458 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5459 u32 *opts)
5460 {
5461 struct skb_shared_info *info = skb_shinfo(skb);
5462 unsigned int cur_frag, entry;
5463 struct TxDesc *uninitialized_var(txd);
5464 struct device *d = tp_to_dev(tp);
5465
5466 entry = tp->cur_tx;
5467 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5468 const skb_frag_t *frag = info->frags + cur_frag;
5469 dma_addr_t mapping;
5470 u32 len;
5471 void *addr;
5472
5473 entry = (entry + 1) % NUM_TX_DESC;
5474
5475 txd = tp->TxDescArray + entry;
5476 len = skb_frag_size(frag);
5477 addr = skb_frag_address(frag);
5478 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5479 if (unlikely(dma_mapping_error(d, mapping))) {
5480 if (net_ratelimit())
5481 netif_err(tp, drv, tp->dev,
5482 "Failed to map TX fragments DMA!\n");
5483 goto err_out;
5484 }
5485
5486 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5487 txd->opts2 = cpu_to_le32(opts[1]);
5488 txd->addr = cpu_to_le64(mapping);
5489
5490 tp->tx_skb[entry].len = len;
5491 }
5492
5493 if (cur_frag) {
5494 tp->tx_skb[entry].skb = skb;
5495 txd->opts1 |= cpu_to_le32(LastFrag);
5496 }
5497
5498 return cur_frag;
5499
5500 err_out:
5501 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5502 return -EIO;
5503 }
5504
5505 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5506 {
5507 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5508 }
5509
5510 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5511 struct net_device *dev);
5512 /* r8169_csum_workaround()
5513 * The hw limites the value the transport offset. When the offset is out of the
5514 * range, calculate the checksum by sw.
5515 */
5516 static void r8169_csum_workaround(struct rtl8169_private *tp,
5517 struct sk_buff *skb)
5518 {
5519 if (skb_is_gso(skb)) {
5520 netdev_features_t features = tp->dev->features;
5521 struct sk_buff *segs, *nskb;
5522
5523 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5524 segs = skb_gso_segment(skb, features);
5525 if (IS_ERR(segs) || !segs)
5526 goto drop;
5527
5528 do {
5529 nskb = segs;
5530 segs = segs->next;
5531 nskb->next = NULL;
5532 rtl8169_start_xmit(nskb, tp->dev);
5533 } while (segs);
5534
5535 dev_consume_skb_any(skb);
5536 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5537 if (skb_checksum_help(skb) < 0)
5538 goto drop;
5539
5540 rtl8169_start_xmit(skb, tp->dev);
5541 } else {
5542 drop:
5543 tp->dev->stats.tx_dropped++;
5544 dev_kfree_skb_any(skb);
5545 }
5546 }
5547
5548 /* msdn_giant_send_check()
5549 * According to the document of microsoft, the TCP Pseudo Header excludes the
5550 * packet length for IPv6 TCP large packets.
5551 */
5552 static int msdn_giant_send_check(struct sk_buff *skb)
5553 {
5554 const struct ipv6hdr *ipv6h;
5555 struct tcphdr *th;
5556 int ret;
5557
5558 ret = skb_cow_head(skb, 0);
5559 if (ret)
5560 return ret;
5561
5562 ipv6h = ipv6_hdr(skb);
5563 th = tcp_hdr(skb);
5564
5565 th->check = 0;
5566 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5567
5568 return ret;
5569 }
5570
5571 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
5572 {
5573 u32 mss = skb_shinfo(skb)->gso_size;
5574
5575 if (mss) {
5576 opts[0] |= TD_LSO;
5577 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5578 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5579 const struct iphdr *ip = ip_hdr(skb);
5580
5581 if (ip->protocol == IPPROTO_TCP)
5582 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5583 else if (ip->protocol == IPPROTO_UDP)
5584 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5585 else
5586 WARN_ON_ONCE(1);
5587 }
5588 }
5589
5590 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5591 struct sk_buff *skb, u32 *opts)
5592 {
5593 u32 transport_offset = (u32)skb_transport_offset(skb);
5594 u32 mss = skb_shinfo(skb)->gso_size;
5595
5596 if (mss) {
5597 if (transport_offset > GTTCPHO_MAX) {
5598 netif_warn(tp, tx_err, tp->dev,
5599 "Invalid transport offset 0x%x for TSO\n",
5600 transport_offset);
5601 return false;
5602 }
5603
5604 switch (vlan_get_protocol(skb)) {
5605 case htons(ETH_P_IP):
5606 opts[0] |= TD1_GTSENV4;
5607 break;
5608
5609 case htons(ETH_P_IPV6):
5610 if (msdn_giant_send_check(skb))
5611 return false;
5612
5613 opts[0] |= TD1_GTSENV6;
5614 break;
5615
5616 default:
5617 WARN_ON_ONCE(1);
5618 break;
5619 }
5620
5621 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5622 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
5623 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5624 u8 ip_protocol;
5625
5626 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5627 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
5628
5629 if (transport_offset > TCPHO_MAX) {
5630 netif_warn(tp, tx_err, tp->dev,
5631 "Invalid transport offset 0x%x\n",
5632 transport_offset);
5633 return false;
5634 }
5635
5636 switch (vlan_get_protocol(skb)) {
5637 case htons(ETH_P_IP):
5638 opts[1] |= TD1_IPv4_CS;
5639 ip_protocol = ip_hdr(skb)->protocol;
5640 break;
5641
5642 case htons(ETH_P_IPV6):
5643 opts[1] |= TD1_IPv6_CS;
5644 ip_protocol = ipv6_hdr(skb)->nexthdr;
5645 break;
5646
5647 default:
5648 ip_protocol = IPPROTO_RAW;
5649 break;
5650 }
5651
5652 if (ip_protocol == IPPROTO_TCP)
5653 opts[1] |= TD1_TCP_CS;
5654 else if (ip_protocol == IPPROTO_UDP)
5655 opts[1] |= TD1_UDP_CS;
5656 else
5657 WARN_ON_ONCE(1);
5658
5659 opts[1] |= transport_offset << TCPHO_SHIFT;
5660 } else {
5661 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5662 return !eth_skb_pad(skb);
5663 }
5664
5665 return true;
5666 }
5667
5668 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
5669 unsigned int nr_frags)
5670 {
5671 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
5672
5673 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
5674 return slots_avail > nr_frags;
5675 }
5676
5677 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
5678 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
5679 {
5680 switch (tp->mac_version) {
5681 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5682 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
5683 return false;
5684 default:
5685 return true;
5686 }
5687 }
5688
5689 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5690 struct net_device *dev)
5691 {
5692 struct rtl8169_private *tp = netdev_priv(dev);
5693 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5694 struct TxDesc *txd = tp->TxDescArray + entry;
5695 struct device *d = tp_to_dev(tp);
5696 dma_addr_t mapping;
5697 u32 opts[2], len;
5698 int frags;
5699
5700 if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
5701 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5702 goto err_stop_0;
5703 }
5704
5705 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5706 goto err_stop_0;
5707
5708 opts[1] = rtl8169_tx_vlan_tag(skb);
5709 opts[0] = DescOwn;
5710
5711 if (rtl_chip_supports_csum_v2(tp)) {
5712 if (!rtl8169_tso_csum_v2(tp, skb, opts)) {
5713 r8169_csum_workaround(tp, skb);
5714 return NETDEV_TX_OK;
5715 }
5716 } else {
5717 rtl8169_tso_csum_v1(skb, opts);
5718 }
5719
5720 len = skb_headlen(skb);
5721 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5722 if (unlikely(dma_mapping_error(d, mapping))) {
5723 if (net_ratelimit())
5724 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5725 goto err_dma_0;
5726 }
5727
5728 tp->tx_skb[entry].len = len;
5729 txd->addr = cpu_to_le64(mapping);
5730
5731 frags = rtl8169_xmit_frags(tp, skb, opts);
5732 if (frags < 0)
5733 goto err_dma_1;
5734 else if (frags)
5735 opts[0] |= FirstFrag;
5736 else {
5737 opts[0] |= FirstFrag | LastFrag;
5738 tp->tx_skb[entry].skb = skb;
5739 }
5740
5741 txd->opts2 = cpu_to_le32(opts[1]);
5742
5743 netdev_sent_queue(dev, skb->len);
5744
5745 skb_tx_timestamp(skb);
5746
5747 /* Force memory writes to complete before releasing descriptor */
5748 dma_wmb();
5749
5750 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5751
5752 /* Force all memory writes to complete before notifying device */
5753 wmb();
5754
5755 tp->cur_tx += frags + 1;
5756
5757 RTL_W8(tp, TxPoll, NPQ);
5758
5759 if (!rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
5760 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5761 * not miss a ring update when it notices a stopped queue.
5762 */
5763 smp_wmb();
5764 netif_stop_queue(dev);
5765 /* Sync with rtl_tx:
5766 * - publish queue status and cur_tx ring index (write barrier)
5767 * - refresh dirty_tx ring index (read barrier).
5768 * May the current thread have a pessimistic view of the ring
5769 * status and forget to wake up queue, a racing rtl_tx thread
5770 * can't.
5771 */
5772 smp_mb();
5773 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
5774 netif_start_queue(dev);
5775 }
5776
5777 return NETDEV_TX_OK;
5778
5779 err_dma_1:
5780 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5781 err_dma_0:
5782 dev_kfree_skb_any(skb);
5783 dev->stats.tx_dropped++;
5784 return NETDEV_TX_OK;
5785
5786 err_stop_0:
5787 netif_stop_queue(dev);
5788 dev->stats.tx_dropped++;
5789 return NETDEV_TX_BUSY;
5790 }
5791
5792 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5793 {
5794 struct rtl8169_private *tp = netdev_priv(dev);
5795 struct pci_dev *pdev = tp->pci_dev;
5796 u16 pci_status, pci_cmd;
5797
5798 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5799 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5800
5801 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5802 pci_cmd, pci_status);
5803
5804 /*
5805 * The recovery sequence below admits a very elaborated explanation:
5806 * - it seems to work;
5807 * - I did not see what else could be done;
5808 * - it makes iop3xx happy.
5809 *
5810 * Feel free to adjust to your needs.
5811 */
5812 if (pdev->broken_parity_status)
5813 pci_cmd &= ~PCI_COMMAND_PARITY;
5814 else
5815 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5816
5817 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5818
5819 pci_write_config_word(pdev, PCI_STATUS,
5820 pci_status & (PCI_STATUS_DETECTED_PARITY |
5821 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5822 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5823
5824 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5825 }
5826
5827 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
5828 int budget)
5829 {
5830 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
5831
5832 dirty_tx = tp->dirty_tx;
5833 smp_rmb();
5834 tx_left = tp->cur_tx - dirty_tx;
5835
5836 while (tx_left > 0) {
5837 unsigned int entry = dirty_tx % NUM_TX_DESC;
5838 struct ring_info *tx_skb = tp->tx_skb + entry;
5839 u32 status;
5840
5841 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5842 if (status & DescOwn)
5843 break;
5844
5845 /* This barrier is needed to keep us from reading
5846 * any other fields out of the Tx descriptor until
5847 * we know the status of DescOwn
5848 */
5849 dma_rmb();
5850
5851 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5852 tp->TxDescArray + entry);
5853 if (status & LastFrag) {
5854 pkts_compl++;
5855 bytes_compl += tx_skb->skb->len;
5856 napi_consume_skb(tx_skb->skb, budget);
5857 tx_skb->skb = NULL;
5858 }
5859 dirty_tx++;
5860 tx_left--;
5861 }
5862
5863 if (tp->dirty_tx != dirty_tx) {
5864 netdev_completed_queue(dev, pkts_compl, bytes_compl);
5865
5866 u64_stats_update_begin(&tp->tx_stats.syncp);
5867 tp->tx_stats.packets += pkts_compl;
5868 tp->tx_stats.bytes += bytes_compl;
5869 u64_stats_update_end(&tp->tx_stats.syncp);
5870
5871 tp->dirty_tx = dirty_tx;
5872 /* Sync with rtl8169_start_xmit:
5873 * - publish dirty_tx ring index (write barrier)
5874 * - refresh cur_tx ring index and queue status (read barrier)
5875 * May the current thread miss the stopped queue condition,
5876 * a racing xmit thread can only have a right view of the
5877 * ring status.
5878 */
5879 smp_mb();
5880 if (netif_queue_stopped(dev) &&
5881 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
5882 netif_wake_queue(dev);
5883 }
5884 /*
5885 * 8168 hack: TxPoll requests are lost when the Tx packets are
5886 * too close. Let's kick an extra TxPoll request when a burst
5887 * of start_xmit activity is detected (if it is not detected,
5888 * it is slow enough). -- FR
5889 */
5890 if (tp->cur_tx != dirty_tx)
5891 RTL_W8(tp, TxPoll, NPQ);
5892 }
5893 }
5894
5895 static inline int rtl8169_fragmented_frame(u32 status)
5896 {
5897 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5898 }
5899
5900 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5901 {
5902 u32 status = opts1 & RxProtoMask;
5903
5904 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5905 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5906 skb->ip_summed = CHECKSUM_UNNECESSARY;
5907 else
5908 skb_checksum_none_assert(skb);
5909 }
5910
5911 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5912 struct rtl8169_private *tp,
5913 int pkt_size,
5914 dma_addr_t addr)
5915 {
5916 struct sk_buff *skb;
5917 struct device *d = tp_to_dev(tp);
5918
5919 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5920 prefetch(data);
5921 skb = napi_alloc_skb(&tp->napi, pkt_size);
5922 if (skb)
5923 skb_copy_to_linear_data(skb, data, pkt_size);
5924
5925 return skb;
5926 }
5927
5928 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5929 {
5930 unsigned int cur_rx, rx_left;
5931 unsigned int count;
5932
5933 cur_rx = tp->cur_rx;
5934
5935 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
5936 unsigned int entry = cur_rx % NUM_RX_DESC;
5937 struct RxDesc *desc = tp->RxDescArray + entry;
5938 u32 status;
5939
5940 status = le32_to_cpu(desc->opts1);
5941 if (status & DescOwn)
5942 break;
5943
5944 /* This barrier is needed to keep us from reading
5945 * any other fields out of the Rx descriptor until
5946 * we know the status of DescOwn
5947 */
5948 dma_rmb();
5949
5950 if (unlikely(status & RxRES)) {
5951 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5952 status);
5953 dev->stats.rx_errors++;
5954 if (status & (RxRWT | RxRUNT))
5955 dev->stats.rx_length_errors++;
5956 if (status & RxCRC)
5957 dev->stats.rx_crc_errors++;
5958 if (status & (RxRUNT | RxCRC) && !(status & RxRWT) &&
5959 dev->features & NETIF_F_RXALL) {
5960 goto process_pkt;
5961 }
5962 } else {
5963 struct sk_buff *skb;
5964 dma_addr_t addr;
5965 int pkt_size;
5966
5967 process_pkt:
5968 addr = le64_to_cpu(desc->addr);
5969 if (likely(!(dev->features & NETIF_F_RXFCS)))
5970 pkt_size = (status & 0x00003fff) - 4;
5971 else
5972 pkt_size = status & 0x00003fff;
5973
5974 /*
5975 * The driver does not support incoming fragmented
5976 * frames. They are seen as a symptom of over-mtu
5977 * sized frames.
5978 */
5979 if (unlikely(rtl8169_fragmented_frame(status))) {
5980 dev->stats.rx_dropped++;
5981 dev->stats.rx_length_errors++;
5982 goto release_descriptor;
5983 }
5984
5985 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5986 tp, pkt_size, addr);
5987 if (!skb) {
5988 dev->stats.rx_dropped++;
5989 goto release_descriptor;
5990 }
5991
5992 rtl8169_rx_csum(skb, status);
5993 skb_put(skb, pkt_size);
5994 skb->protocol = eth_type_trans(skb, dev);
5995
5996 rtl8169_rx_vlan_tag(desc, skb);
5997
5998 if (skb->pkt_type == PACKET_MULTICAST)
5999 dev->stats.multicast++;
6000
6001 napi_gro_receive(&tp->napi, skb);
6002
6003 u64_stats_update_begin(&tp->rx_stats.syncp);
6004 tp->rx_stats.packets++;
6005 tp->rx_stats.bytes += pkt_size;
6006 u64_stats_update_end(&tp->rx_stats.syncp);
6007 }
6008 release_descriptor:
6009 desc->opts2 = 0;
6010 rtl8169_mark_to_asic(desc);
6011 }
6012
6013 count = cur_rx - tp->cur_rx;
6014 tp->cur_rx = cur_rx;
6015
6016 return count;
6017 }
6018
6019 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6020 {
6021 struct rtl8169_private *tp = dev_instance;
6022 u16 status = RTL_R16(tp, IntrStatus);
6023
6024 if (!tp->irq_enabled || status == 0xffff || !(status & tp->irq_mask))
6025 return IRQ_NONE;
6026
6027 if (unlikely(status & SYSErr)) {
6028 rtl8169_pcierr_interrupt(tp->dev);
6029 goto out;
6030 }
6031
6032 if (status & LinkChg)
6033 phy_mac_interrupt(tp->phydev);
6034
6035 if (unlikely(status & RxFIFOOver &&
6036 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6037 netif_stop_queue(tp->dev);
6038 /* XXX - Hack alert. See rtl_task(). */
6039 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6040 }
6041
6042 rtl_irq_disable(tp);
6043 napi_schedule_irqoff(&tp->napi);
6044 out:
6045 rtl_ack_events(tp, status);
6046
6047 return IRQ_HANDLED;
6048 }
6049
6050 static void rtl_task(struct work_struct *work)
6051 {
6052 static const struct {
6053 int bitnr;
6054 void (*action)(struct rtl8169_private *);
6055 } rtl_work[] = {
6056 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6057 };
6058 struct rtl8169_private *tp =
6059 container_of(work, struct rtl8169_private, wk.work);
6060 struct net_device *dev = tp->dev;
6061 int i;
6062
6063 rtl_lock_work(tp);
6064
6065 if (!netif_running(dev) ||
6066 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6067 goto out_unlock;
6068
6069 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6070 bool pending;
6071
6072 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6073 if (pending)
6074 rtl_work[i].action(tp);
6075 }
6076
6077 out_unlock:
6078 rtl_unlock_work(tp);
6079 }
6080
6081 static int rtl8169_poll(struct napi_struct *napi, int budget)
6082 {
6083 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6084 struct net_device *dev = tp->dev;
6085 int work_done;
6086
6087 work_done = rtl_rx(dev, tp, (u32) budget);
6088
6089 rtl_tx(dev, tp, budget);
6090
6091 if (work_done < budget) {
6092 napi_complete_done(napi, work_done);
6093 rtl_irq_enable(tp);
6094 }
6095
6096 return work_done;
6097 }
6098
6099 static void rtl8169_rx_missed(struct net_device *dev)
6100 {
6101 struct rtl8169_private *tp = netdev_priv(dev);
6102
6103 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6104 return;
6105
6106 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6107 RTL_W32(tp, RxMissed, 0);
6108 }
6109
6110 static void r8169_phylink_handler(struct net_device *ndev)
6111 {
6112 struct rtl8169_private *tp = netdev_priv(ndev);
6113
6114 if (netif_carrier_ok(ndev)) {
6115 rtl_link_chg_patch(tp);
6116 pm_request_resume(&tp->pci_dev->dev);
6117 } else {
6118 pm_runtime_idle(&tp->pci_dev->dev);
6119 }
6120
6121 if (net_ratelimit())
6122 phy_print_status(tp->phydev);
6123 }
6124
6125 static int r8169_phy_connect(struct rtl8169_private *tp)
6126 {
6127 struct phy_device *phydev = tp->phydev;
6128 phy_interface_t phy_mode;
6129 int ret;
6130
6131 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6132 PHY_INTERFACE_MODE_MII;
6133
6134 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6135 phy_mode);
6136 if (ret)
6137 return ret;
6138
6139 if (!tp->supports_gmii)
6140 phy_set_max_speed(phydev, SPEED_100);
6141
6142 phy_support_asym_pause(phydev);
6143
6144 phy_attached_info(phydev);
6145
6146 return 0;
6147 }
6148
6149 static void rtl8169_down(struct net_device *dev)
6150 {
6151 struct rtl8169_private *tp = netdev_priv(dev);
6152
6153 phy_stop(tp->phydev);
6154
6155 napi_disable(&tp->napi);
6156 netif_stop_queue(dev);
6157
6158 rtl8169_hw_reset(tp);
6159 /*
6160 * At this point device interrupts can not be enabled in any function,
6161 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6162 * and napi is disabled (rtl8169_poll).
6163 */
6164 rtl8169_rx_missed(dev);
6165
6166 /* Give a racing hard_start_xmit a few cycles to complete. */
6167 synchronize_rcu();
6168
6169 rtl8169_tx_clear(tp);
6170
6171 rtl8169_rx_clear(tp);
6172
6173 rtl_pll_power_down(tp);
6174 }
6175
6176 static int rtl8169_close(struct net_device *dev)
6177 {
6178 struct rtl8169_private *tp = netdev_priv(dev);
6179 struct pci_dev *pdev = tp->pci_dev;
6180
6181 pm_runtime_get_sync(&pdev->dev);
6182
6183 /* Update counters before going down */
6184 rtl8169_update_counters(tp);
6185
6186 rtl_lock_work(tp);
6187 /* Clear all task flags */
6188 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6189
6190 rtl8169_down(dev);
6191 rtl_unlock_work(tp);
6192
6193 cancel_work_sync(&tp->wk.work);
6194
6195 phy_disconnect(tp->phydev);
6196
6197 pci_free_irq(pdev, 0, tp);
6198
6199 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6200 tp->RxPhyAddr);
6201 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6202 tp->TxPhyAddr);
6203 tp->TxDescArray = NULL;
6204 tp->RxDescArray = NULL;
6205
6206 pm_runtime_put_sync(&pdev->dev);
6207
6208 return 0;
6209 }
6210
6211 #ifdef CONFIG_NET_POLL_CONTROLLER
6212 static void rtl8169_netpoll(struct net_device *dev)
6213 {
6214 struct rtl8169_private *tp = netdev_priv(dev);
6215
6216 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6217 }
6218 #endif
6219
6220 static int rtl_open(struct net_device *dev)
6221 {
6222 struct rtl8169_private *tp = netdev_priv(dev);
6223 struct pci_dev *pdev = tp->pci_dev;
6224 int retval = -ENOMEM;
6225
6226 pm_runtime_get_sync(&pdev->dev);
6227
6228 /*
6229 * Rx and Tx descriptors needs 256 bytes alignment.
6230 * dma_alloc_coherent provides more.
6231 */
6232 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6233 &tp->TxPhyAddr, GFP_KERNEL);
6234 if (!tp->TxDescArray)
6235 goto err_pm_runtime_put;
6236
6237 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6238 &tp->RxPhyAddr, GFP_KERNEL);
6239 if (!tp->RxDescArray)
6240 goto err_free_tx_0;
6241
6242 retval = rtl8169_init_ring(tp);
6243 if (retval < 0)
6244 goto err_free_rx_1;
6245
6246 rtl_request_firmware(tp);
6247
6248 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6249 dev->name);
6250 if (retval < 0)
6251 goto err_release_fw_2;
6252
6253 retval = r8169_phy_connect(tp);
6254 if (retval)
6255 goto err_free_irq;
6256
6257 rtl_lock_work(tp);
6258
6259 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6260
6261 napi_enable(&tp->napi);
6262
6263 rtl8169_init_phy(dev, tp);
6264
6265 rtl_pll_power_up(tp);
6266
6267 rtl_hw_start(tp);
6268
6269 if (!rtl8169_init_counter_offsets(tp))
6270 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6271
6272 phy_start(tp->phydev);
6273 netif_start_queue(dev);
6274
6275 rtl_unlock_work(tp);
6276
6277 pm_runtime_put_sync(&pdev->dev);
6278 out:
6279 return retval;
6280
6281 err_free_irq:
6282 pci_free_irq(pdev, 0, tp);
6283 err_release_fw_2:
6284 rtl_release_firmware(tp);
6285 rtl8169_rx_clear(tp);
6286 err_free_rx_1:
6287 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6288 tp->RxPhyAddr);
6289 tp->RxDescArray = NULL;
6290 err_free_tx_0:
6291 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6292 tp->TxPhyAddr);
6293 tp->TxDescArray = NULL;
6294 err_pm_runtime_put:
6295 pm_runtime_put_noidle(&pdev->dev);
6296 goto out;
6297 }
6298
6299 static void
6300 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6301 {
6302 struct rtl8169_private *tp = netdev_priv(dev);
6303 struct pci_dev *pdev = tp->pci_dev;
6304 struct rtl8169_counters *counters = tp->counters;
6305 unsigned int start;
6306
6307 pm_runtime_get_noresume(&pdev->dev);
6308
6309 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6310 rtl8169_rx_missed(dev);
6311
6312 do {
6313 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6314 stats->rx_packets = tp->rx_stats.packets;
6315 stats->rx_bytes = tp->rx_stats.bytes;
6316 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6317
6318 do {
6319 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6320 stats->tx_packets = tp->tx_stats.packets;
6321 stats->tx_bytes = tp->tx_stats.bytes;
6322 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6323
6324 stats->rx_dropped = dev->stats.rx_dropped;
6325 stats->tx_dropped = dev->stats.tx_dropped;
6326 stats->rx_length_errors = dev->stats.rx_length_errors;
6327 stats->rx_errors = dev->stats.rx_errors;
6328 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6329 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6330 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6331 stats->multicast = dev->stats.multicast;
6332
6333 /*
6334 * Fetch additonal counter values missing in stats collected by driver
6335 * from tally counters.
6336 */
6337 if (pm_runtime_active(&pdev->dev))
6338 rtl8169_update_counters(tp);
6339
6340 /*
6341 * Subtract values fetched during initalization.
6342 * See rtl8169_init_counter_offsets for a description why we do that.
6343 */
6344 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6345 le64_to_cpu(tp->tc_offset.tx_errors);
6346 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6347 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6348 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6349 le16_to_cpu(tp->tc_offset.tx_aborted);
6350
6351 pm_runtime_put_noidle(&pdev->dev);
6352 }
6353
6354 static void rtl8169_net_suspend(struct net_device *dev)
6355 {
6356 struct rtl8169_private *tp = netdev_priv(dev);
6357
6358 if (!netif_running(dev))
6359 return;
6360
6361 phy_stop(tp->phydev);
6362 netif_device_detach(dev);
6363
6364 rtl_lock_work(tp);
6365 napi_disable(&tp->napi);
6366 /* Clear all task flags */
6367 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6368
6369 rtl_unlock_work(tp);
6370
6371 rtl_pll_power_down(tp);
6372 }
6373
6374 #ifdef CONFIG_PM
6375
6376 static int rtl8169_suspend(struct device *device)
6377 {
6378 struct net_device *dev = dev_get_drvdata(device);
6379 struct rtl8169_private *tp = netdev_priv(dev);
6380
6381 rtl8169_net_suspend(dev);
6382 clk_disable_unprepare(tp->clk);
6383
6384 return 0;
6385 }
6386
6387 static void __rtl8169_resume(struct net_device *dev)
6388 {
6389 struct rtl8169_private *tp = netdev_priv(dev);
6390
6391 netif_device_attach(dev);
6392
6393 rtl_pll_power_up(tp);
6394 rtl8169_init_phy(dev, tp);
6395
6396 phy_start(tp->phydev);
6397
6398 rtl_lock_work(tp);
6399 napi_enable(&tp->napi);
6400 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6401 rtl_reset_work(tp);
6402 rtl_unlock_work(tp);
6403 }
6404
6405 static int rtl8169_resume(struct device *device)
6406 {
6407 struct net_device *dev = dev_get_drvdata(device);
6408 struct rtl8169_private *tp = netdev_priv(dev);
6409
6410 rtl_rar_set(tp, dev->dev_addr);
6411
6412 clk_prepare_enable(tp->clk);
6413
6414 if (netif_running(dev))
6415 __rtl8169_resume(dev);
6416
6417 return 0;
6418 }
6419
6420 static int rtl8169_runtime_suspend(struct device *device)
6421 {
6422 struct net_device *dev = dev_get_drvdata(device);
6423 struct rtl8169_private *tp = netdev_priv(dev);
6424
6425 if (!tp->TxDescArray)
6426 return 0;
6427
6428 rtl_lock_work(tp);
6429 __rtl8169_set_wol(tp, WAKE_ANY);
6430 rtl_unlock_work(tp);
6431
6432 rtl8169_net_suspend(dev);
6433
6434 /* Update counters before going runtime suspend */
6435 rtl8169_rx_missed(dev);
6436 rtl8169_update_counters(tp);
6437
6438 return 0;
6439 }
6440
6441 static int rtl8169_runtime_resume(struct device *device)
6442 {
6443 struct net_device *dev = dev_get_drvdata(device);
6444 struct rtl8169_private *tp = netdev_priv(dev);
6445
6446 rtl_rar_set(tp, dev->dev_addr);
6447
6448 if (!tp->TxDescArray)
6449 return 0;
6450
6451 rtl_lock_work(tp);
6452 __rtl8169_set_wol(tp, tp->saved_wolopts);
6453 rtl_unlock_work(tp);
6454
6455 __rtl8169_resume(dev);
6456
6457 return 0;
6458 }
6459
6460 static int rtl8169_runtime_idle(struct device *device)
6461 {
6462 struct net_device *dev = dev_get_drvdata(device);
6463
6464 if (!netif_running(dev) || !netif_carrier_ok(dev))
6465 pm_schedule_suspend(device, 10000);
6466
6467 return -EBUSY;
6468 }
6469
6470 static const struct dev_pm_ops rtl8169_pm_ops = {
6471 .suspend = rtl8169_suspend,
6472 .resume = rtl8169_resume,
6473 .freeze = rtl8169_suspend,
6474 .thaw = rtl8169_resume,
6475 .poweroff = rtl8169_suspend,
6476 .restore = rtl8169_resume,
6477 .runtime_suspend = rtl8169_runtime_suspend,
6478 .runtime_resume = rtl8169_runtime_resume,
6479 .runtime_idle = rtl8169_runtime_idle,
6480 };
6481
6482 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
6483
6484 #else /* !CONFIG_PM */
6485
6486 #define RTL8169_PM_OPS NULL
6487
6488 #endif /* !CONFIG_PM */
6489
6490 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6491 {
6492 /* WoL fails with 8168b when the receiver is disabled. */
6493 switch (tp->mac_version) {
6494 case RTL_GIGA_MAC_VER_11:
6495 case RTL_GIGA_MAC_VER_12:
6496 case RTL_GIGA_MAC_VER_17:
6497 pci_clear_master(tp->pci_dev);
6498
6499 RTL_W8(tp, ChipCmd, CmdRxEnb);
6500 /* PCI commit */
6501 RTL_R8(tp, ChipCmd);
6502 break;
6503 default:
6504 break;
6505 }
6506 }
6507
6508 static void rtl_shutdown(struct pci_dev *pdev)
6509 {
6510 struct net_device *dev = pci_get_drvdata(pdev);
6511 struct rtl8169_private *tp = netdev_priv(dev);
6512
6513 rtl8169_net_suspend(dev);
6514
6515 /* Restore original MAC address */
6516 rtl_rar_set(tp, dev->perm_addr);
6517
6518 rtl8169_hw_reset(tp);
6519
6520 if (system_state == SYSTEM_POWER_OFF) {
6521 if (tp->saved_wolopts) {
6522 rtl_wol_suspend_quirk(tp);
6523 rtl_wol_shutdown_quirk(tp);
6524 }
6525
6526 pci_wake_from_d3(pdev, true);
6527 pci_set_power_state(pdev, PCI_D3hot);
6528 }
6529 }
6530
6531 static void rtl_remove_one(struct pci_dev *pdev)
6532 {
6533 struct net_device *dev = pci_get_drvdata(pdev);
6534 struct rtl8169_private *tp = netdev_priv(dev);
6535
6536 if (r8168_check_dash(tp))
6537 rtl8168_driver_stop(tp);
6538
6539 netif_napi_del(&tp->napi);
6540
6541 unregister_netdev(dev);
6542 mdiobus_unregister(tp->phydev->mdio.bus);
6543
6544 rtl_release_firmware(tp);
6545
6546 if (pci_dev_run_wake(pdev))
6547 pm_runtime_get_noresume(&pdev->dev);
6548
6549 /* restore original MAC address */
6550 rtl_rar_set(tp, dev->perm_addr);
6551 }
6552
6553 static const struct net_device_ops rtl_netdev_ops = {
6554 .ndo_open = rtl_open,
6555 .ndo_stop = rtl8169_close,
6556 .ndo_get_stats64 = rtl8169_get_stats64,
6557 .ndo_start_xmit = rtl8169_start_xmit,
6558 .ndo_tx_timeout = rtl8169_tx_timeout,
6559 .ndo_validate_addr = eth_validate_addr,
6560 .ndo_change_mtu = rtl8169_change_mtu,
6561 .ndo_fix_features = rtl8169_fix_features,
6562 .ndo_set_features = rtl8169_set_features,
6563 .ndo_set_mac_address = rtl_set_mac_address,
6564 .ndo_do_ioctl = rtl8169_ioctl,
6565 .ndo_set_rx_mode = rtl_set_rx_mode,
6566 #ifdef CONFIG_NET_POLL_CONTROLLER
6567 .ndo_poll_controller = rtl8169_netpoll,
6568 #endif
6569
6570 };
6571
6572 static void rtl_set_irq_mask(struct rtl8169_private *tp)
6573 {
6574 tp->irq_mask = RTL_EVENT_NAPI | LinkChg;
6575
6576 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6577 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
6578 else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
6579 /* special workaround needed */
6580 tp->irq_mask |= RxFIFOOver;
6581 else
6582 tp->irq_mask |= RxOverflow;
6583 }
6584
6585 static int rtl_alloc_irq(struct rtl8169_private *tp)
6586 {
6587 unsigned int flags;
6588
6589 switch (tp->mac_version) {
6590 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
6591 rtl_unlock_config_regs(tp);
6592 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
6593 rtl_lock_config_regs(tp);
6594 /* fall through */
6595 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_24:
6596 flags = PCI_IRQ_LEGACY;
6597 break;
6598 default:
6599 flags = PCI_IRQ_ALL_TYPES;
6600 break;
6601 }
6602
6603 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
6604 }
6605
6606 static void rtl_read_mac_address(struct rtl8169_private *tp,
6607 u8 mac_addr[ETH_ALEN])
6608 {
6609 /* Get MAC address */
6610 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
6611 u32 value = rtl_eri_read(tp, 0xe0);
6612
6613 mac_addr[0] = (value >> 0) & 0xff;
6614 mac_addr[1] = (value >> 8) & 0xff;
6615 mac_addr[2] = (value >> 16) & 0xff;
6616 mac_addr[3] = (value >> 24) & 0xff;
6617
6618 value = rtl_eri_read(tp, 0xe4);
6619 mac_addr[4] = (value >> 0) & 0xff;
6620 mac_addr[5] = (value >> 8) & 0xff;
6621 }
6622 }
6623
6624 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6625 {
6626 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
6627 }
6628
6629 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6630 {
6631 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6632 }
6633
6634 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
6635 {
6636 struct rtl8169_private *tp = mii_bus->priv;
6637
6638 if (phyaddr > 0)
6639 return -ENODEV;
6640
6641 return rtl_readphy(tp, phyreg);
6642 }
6643
6644 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
6645 int phyreg, u16 val)
6646 {
6647 struct rtl8169_private *tp = mii_bus->priv;
6648
6649 if (phyaddr > 0)
6650 return -ENODEV;
6651
6652 rtl_writephy(tp, phyreg, val);
6653
6654 return 0;
6655 }
6656
6657 static int r8169_mdio_register(struct rtl8169_private *tp)
6658 {
6659 struct pci_dev *pdev = tp->pci_dev;
6660 struct mii_bus *new_bus;
6661 int ret;
6662
6663 new_bus = devm_mdiobus_alloc(&pdev->dev);
6664 if (!new_bus)
6665 return -ENOMEM;
6666
6667 new_bus->name = "r8169";
6668 new_bus->priv = tp;
6669 new_bus->parent = &pdev->dev;
6670 new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
6671 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
6672
6673 new_bus->read = r8169_mdio_read_reg;
6674 new_bus->write = r8169_mdio_write_reg;
6675
6676 ret = mdiobus_register(new_bus);
6677 if (ret)
6678 return ret;
6679
6680 tp->phydev = mdiobus_get_phy(new_bus, 0);
6681 if (!tp->phydev) {
6682 mdiobus_unregister(new_bus);
6683 return -ENODEV;
6684 }
6685
6686 /* PHY will be woken up in rtl_open() */
6687 phy_suspend(tp->phydev);
6688
6689 return 0;
6690 }
6691
6692 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6693 {
6694 u32 data;
6695
6696 tp->ocp_base = OCP_STD_PHY_BASE;
6697
6698 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
6699
6700 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6701 return;
6702
6703 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6704 return;
6705
6706 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6707 msleep(1);
6708 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6709
6710 data = r8168_mac_ocp_read(tp, 0xe8de);
6711 data &= ~(1 << 14);
6712 r8168_mac_ocp_write(tp, 0xe8de, data);
6713
6714 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6715 return;
6716
6717 data = r8168_mac_ocp_read(tp, 0xe8de);
6718 data |= (1 << 15);
6719 r8168_mac_ocp_write(tp, 0xe8de, data);
6720
6721 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
6722 }
6723
6724 static void rtl_hw_initialize(struct rtl8169_private *tp)
6725 {
6726 switch (tp->mac_version) {
6727 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
6728 rtl8168ep_stop_cmac(tp);
6729 /* fall through */
6730 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
6731 rtl_hw_init_8168g(tp);
6732 break;
6733 default:
6734 break;
6735 }
6736 }
6737
6738 static int rtl_jumbo_max(struct rtl8169_private *tp)
6739 {
6740 /* Non-GBit versions don't support jumbo frames */
6741 if (!tp->supports_gmii)
6742 return JUMBO_1K;
6743
6744 switch (tp->mac_version) {
6745 /* RTL8169 */
6746 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
6747 return JUMBO_7K;
6748 /* RTL8168b */
6749 case RTL_GIGA_MAC_VER_11:
6750 case RTL_GIGA_MAC_VER_12:
6751 case RTL_GIGA_MAC_VER_17:
6752 return JUMBO_4K;
6753 /* RTL8168c */
6754 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
6755 return JUMBO_6K;
6756 default:
6757 return JUMBO_9K;
6758 }
6759 }
6760
6761 static void rtl_disable_clk(void *data)
6762 {
6763 clk_disable_unprepare(data);
6764 }
6765
6766 static int rtl_get_ether_clk(struct rtl8169_private *tp)
6767 {
6768 struct device *d = tp_to_dev(tp);
6769 struct clk *clk;
6770 int rc;
6771
6772 clk = devm_clk_get(d, "ether_clk");
6773 if (IS_ERR(clk)) {
6774 rc = PTR_ERR(clk);
6775 if (rc == -ENOENT)
6776 /* clk-core allows NULL (for suspend / resume) */
6777 rc = 0;
6778 else if (rc != -EPROBE_DEFER)
6779 dev_err(d, "failed to get clk: %d\n", rc);
6780 } else {
6781 tp->clk = clk;
6782 rc = clk_prepare_enable(clk);
6783 if (rc)
6784 dev_err(d, "failed to enable clk: %d\n", rc);
6785 else
6786 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
6787 }
6788
6789 return rc;
6790 }
6791
6792 static void rtl_init_mac_address(struct rtl8169_private *tp)
6793 {
6794 struct net_device *dev = tp->dev;
6795 u8 *mac_addr = dev->dev_addr;
6796 int rc, i;
6797
6798 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
6799 if (!rc)
6800 goto done;
6801
6802 rtl_read_mac_address(tp, mac_addr);
6803 if (is_valid_ether_addr(mac_addr))
6804 goto done;
6805
6806 for (i = 0; i < ETH_ALEN; i++)
6807 mac_addr[i] = RTL_R8(tp, MAC0 + i);
6808 if (is_valid_ether_addr(mac_addr))
6809 goto done;
6810
6811 eth_hw_addr_random(dev);
6812 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
6813 done:
6814 rtl_rar_set(tp, mac_addr);
6815 }
6816
6817 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6818 {
6819 struct rtl8169_private *tp;
6820 struct net_device *dev;
6821 int chipset, region;
6822 int jumbo_max, rc;
6823
6824 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
6825 if (!dev)
6826 return -ENOMEM;
6827
6828 SET_NETDEV_DEV(dev, &pdev->dev);
6829 dev->netdev_ops = &rtl_netdev_ops;
6830 tp = netdev_priv(dev);
6831 tp->dev = dev;
6832 tp->pci_dev = pdev;
6833 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6834 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
6835
6836 /* Get the *optional* external "ether_clk" used on some boards */
6837 rc = rtl_get_ether_clk(tp);
6838 if (rc)
6839 return rc;
6840
6841 /* Disable ASPM completely as that cause random device stop working
6842 * problems as well as full system hangs for some PCIe devices users.
6843 */
6844 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
6845 PCIE_LINK_STATE_L1);
6846 tp->aspm_manageable = !rc;
6847
6848 /* enable device (incl. PCI PM wakeup and hotplug setup) */
6849 rc = pcim_enable_device(pdev);
6850 if (rc < 0) {
6851 dev_err(&pdev->dev, "enable failure\n");
6852 return rc;
6853 }
6854
6855 if (pcim_set_mwi(pdev) < 0)
6856 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
6857
6858 /* use first MMIO region */
6859 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
6860 if (region < 0) {
6861 dev_err(&pdev->dev, "no MMIO resource found\n");
6862 return -ENODEV;
6863 }
6864
6865 /* check for weird/broken PCI region reporting */
6866 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6867 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
6868 return -ENODEV;
6869 }
6870
6871 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
6872 if (rc < 0) {
6873 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
6874 return rc;
6875 }
6876
6877 tp->mmio_addr = pcim_iomap_table(pdev)[region];
6878
6879 /* Identify chip attached to board */
6880 rtl8169_get_mac_version(tp);
6881 if (tp->mac_version == RTL_GIGA_MAC_NONE)
6882 return -ENODEV;
6883
6884 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
6885
6886 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
6887 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
6888 dev->features |= NETIF_F_HIGHDMA;
6889
6890 rtl_init_rxcfg(tp);
6891
6892 rtl8169_irq_mask_and_ack(tp);
6893
6894 rtl_hw_initialize(tp);
6895
6896 rtl_hw_reset(tp);
6897
6898 pci_set_master(pdev);
6899
6900 chipset = tp->mac_version;
6901
6902 rc = rtl_alloc_irq(tp);
6903 if (rc < 0) {
6904 dev_err(&pdev->dev, "Can't allocate interrupt\n");
6905 return rc;
6906 }
6907
6908 mutex_init(&tp->wk.mutex);
6909 INIT_WORK(&tp->wk.work, rtl_task);
6910 u64_stats_init(&tp->rx_stats.syncp);
6911 u64_stats_init(&tp->tx_stats.syncp);
6912
6913 rtl_init_mac_address(tp);
6914
6915 dev->ethtool_ops = &rtl8169_ethtool_ops;
6916
6917 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
6918
6919 /* don't enable SG, IP_CSUM and TSO by default - it might not work
6920 * properly for all devices */
6921 dev->features |= NETIF_F_RXCSUM |
6922 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
6923
6924 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6925 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
6926 NETIF_F_HW_VLAN_CTAG_RX;
6927 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6928 NETIF_F_HIGHDMA;
6929 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
6930
6931 tp->cp_cmd |= RxChkSum | RxVlan;
6932
6933 /*
6934 * Pretend we are using VLANs; This bypasses a nasty bug where
6935 * Interrupts stop flowing on high load on 8110SCd controllers.
6936 */
6937 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6938 /* Disallow toggling */
6939 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
6940
6941 if (rtl_chip_supports_csum_v2(tp))
6942 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
6943
6944 dev->hw_features |= NETIF_F_RXALL;
6945 dev->hw_features |= NETIF_F_RXFCS;
6946
6947 /* MTU range: 60 - hw-specific max */
6948 dev->min_mtu = ETH_ZLEN;
6949 jumbo_max = rtl_jumbo_max(tp);
6950 dev->max_mtu = jumbo_max;
6951
6952 rtl_set_irq_mask(tp);
6953
6954 tp->fw_name = rtl_chip_infos[chipset].fw_name;
6955
6956 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
6957 &tp->counters_phys_addr,
6958 GFP_KERNEL);
6959 if (!tp->counters)
6960 return -ENOMEM;
6961
6962 pci_set_drvdata(pdev, dev);
6963
6964 rc = r8169_mdio_register(tp);
6965 if (rc)
6966 return rc;
6967
6968 /* chip gets powered up in rtl_open() */
6969 rtl_pll_power_down(tp);
6970
6971 rc = register_netdev(dev);
6972 if (rc)
6973 goto err_mdio_unregister;
6974
6975 netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
6976 rtl_chip_infos[chipset].name, dev->dev_addr,
6977 (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
6978 pci_irq_vector(pdev, 0));
6979
6980 if (jumbo_max > JUMBO_1K)
6981 netif_info(tp, probe, dev,
6982 "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
6983 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
6984 "ok" : "ko");
6985
6986 if (r8168_check_dash(tp))
6987 rtl8168_driver_start(tp);
6988
6989 if (pci_dev_run_wake(pdev))
6990 pm_runtime_put_sync(&pdev->dev);
6991
6992 return 0;
6993
6994 err_mdio_unregister:
6995 mdiobus_unregister(tp->phydev->mdio.bus);
6996 return rc;
6997 }
6998
6999 static struct pci_driver rtl8169_pci_driver = {
7000 .name = MODULENAME,
7001 .id_table = rtl8169_pci_tbl,
7002 .probe = rtl_init_one,
7003 .remove = rtl_remove_one,
7004 .shutdown = rtl_shutdown,
7005 .driver.pm = RTL8169_PM_OPS,
7006 };
7007
7008 module_pci_driver(rtl8169_pci_driver);
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