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[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / realtek / r8169_main.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 *
5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
7 * Copyright (c) a lot of people too. Please respect their work.
8 *
9 * See MAINTAINERS file for support contact information.
10 */
11
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/pci.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/ethtool.h>
20 #include <linux/phy.h>
21 #include <linux/if_vlan.h>
22 #include <linux/crc32.h>
23 #include <linux/in.h>
24 #include <linux/io.h>
25 #include <linux/ip.h>
26 #include <linux/tcp.h>
27 #include <linux/interrupt.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/prefetch.h>
31 #include <linux/pci-aspm.h>
32 #include <linux/ipv6.h>
33 #include <net/ip6_checksum.h>
34
35 #include "r8169_firmware.h"
36
37 #define MODULENAME "r8169"
38
39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
47 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
48 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
49 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
50 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
51 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
52 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
53 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
54 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
55 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
56 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
57 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
58
59 #define R8169_MSG_DEFAULT \
60 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
61
62 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
63 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
64 static const int multicast_filter_limit = 32;
65
66 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
67 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
68
69 #define R8169_REGS_SIZE 256
70 #define R8169_RX_BUF_SIZE (SZ_16K - 1)
71 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
72 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
73 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
74 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
75
76 #define RTL_CFG_NO_GBIT 1
77
78 /* write/read MMIO register */
79 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
80 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
81 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
82 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
83 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
84 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
85
86 enum mac_version {
87 /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */
88 RTL_GIGA_MAC_VER_02,
89 RTL_GIGA_MAC_VER_03,
90 RTL_GIGA_MAC_VER_04,
91 RTL_GIGA_MAC_VER_05,
92 RTL_GIGA_MAC_VER_06,
93 RTL_GIGA_MAC_VER_07,
94 RTL_GIGA_MAC_VER_08,
95 RTL_GIGA_MAC_VER_09,
96 RTL_GIGA_MAC_VER_10,
97 RTL_GIGA_MAC_VER_11,
98 RTL_GIGA_MAC_VER_12,
99 RTL_GIGA_MAC_VER_13,
100 RTL_GIGA_MAC_VER_14,
101 RTL_GIGA_MAC_VER_15,
102 RTL_GIGA_MAC_VER_16,
103 RTL_GIGA_MAC_VER_17,
104 RTL_GIGA_MAC_VER_18,
105 RTL_GIGA_MAC_VER_19,
106 RTL_GIGA_MAC_VER_20,
107 RTL_GIGA_MAC_VER_21,
108 RTL_GIGA_MAC_VER_22,
109 RTL_GIGA_MAC_VER_23,
110 RTL_GIGA_MAC_VER_24,
111 RTL_GIGA_MAC_VER_25,
112 RTL_GIGA_MAC_VER_26,
113 RTL_GIGA_MAC_VER_27,
114 RTL_GIGA_MAC_VER_28,
115 RTL_GIGA_MAC_VER_29,
116 RTL_GIGA_MAC_VER_30,
117 RTL_GIGA_MAC_VER_31,
118 RTL_GIGA_MAC_VER_32,
119 RTL_GIGA_MAC_VER_33,
120 RTL_GIGA_MAC_VER_34,
121 RTL_GIGA_MAC_VER_35,
122 RTL_GIGA_MAC_VER_36,
123 RTL_GIGA_MAC_VER_37,
124 RTL_GIGA_MAC_VER_38,
125 RTL_GIGA_MAC_VER_39,
126 RTL_GIGA_MAC_VER_40,
127 RTL_GIGA_MAC_VER_41,
128 RTL_GIGA_MAC_VER_42,
129 RTL_GIGA_MAC_VER_43,
130 RTL_GIGA_MAC_VER_44,
131 RTL_GIGA_MAC_VER_45,
132 RTL_GIGA_MAC_VER_46,
133 RTL_GIGA_MAC_VER_47,
134 RTL_GIGA_MAC_VER_48,
135 RTL_GIGA_MAC_VER_49,
136 RTL_GIGA_MAC_VER_50,
137 RTL_GIGA_MAC_VER_51,
138 RTL_GIGA_MAC_NONE
139 };
140
141 #define JUMBO_1K ETH_DATA_LEN
142 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
143 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
144 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
145 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
146
147 static const struct {
148 const char *name;
149 const char *fw_name;
150 } rtl_chip_infos[] = {
151 /* PCI devices. */
152 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
153 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
154 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
155 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
156 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
157 /* PCI-E devices. */
158 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
159 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
160 [RTL_GIGA_MAC_VER_09] = {"RTL8102e" },
161 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
162 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
163 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
164 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" },
165 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" },
166 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" },
167 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
168 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
169 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
170 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
171 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
172 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
173 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
174 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
175 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
176 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
177 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
178 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
179 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
180 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
181 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
182 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
183 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
184 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
185 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
186 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
187 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
188 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
189 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
190 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
191 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
192 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
193 [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g", FIRMWARE_8168G_3},
194 [RTL_GIGA_MAC_VER_43] = {"RTL8106e", FIRMWARE_8106E_2},
195 [RTL_GIGA_MAC_VER_44] = {"RTL8411", FIRMWARE_8411_2 },
196 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
197 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
198 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
199 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
200 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
201 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
202 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
203 };
204
205 static const struct pci_device_id rtl8169_pci_tbl[] = {
206 { PCI_VDEVICE(REALTEK, 0x2502) },
207 { PCI_VDEVICE(REALTEK, 0x2600) },
208 { PCI_VDEVICE(REALTEK, 0x8129) },
209 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
210 { PCI_VDEVICE(REALTEK, 0x8161) },
211 { PCI_VDEVICE(REALTEK, 0x8167) },
212 { PCI_VDEVICE(REALTEK, 0x8168) },
213 { PCI_VDEVICE(NCUBE, 0x8168) },
214 { PCI_VDEVICE(REALTEK, 0x8169) },
215 { PCI_VENDOR_ID_DLINK, 0x4300,
216 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
217 { PCI_VDEVICE(DLINK, 0x4300), },
218 { PCI_VDEVICE(DLINK, 0x4302), },
219 { PCI_VDEVICE(AT, 0xc107), },
220 { PCI_VDEVICE(USR, 0x0116), },
221 { PCI_VENDOR_ID_LINKSYS, 0x1032,
222 PCI_ANY_ID, 0x0024, 0, 0 },
223 { 0x0001, 0x8168,
224 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_NO_GBIT },
225 {}
226 };
227
228 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
229
230 static struct {
231 u32 msg_enable;
232 } debug = { -1 };
233
234 enum rtl_registers {
235 MAC0 = 0, /* Ethernet hardware address. */
236 MAC4 = 4,
237 MAR0 = 8, /* Multicast filter. */
238 CounterAddrLow = 0x10,
239 CounterAddrHigh = 0x14,
240 TxDescStartAddrLow = 0x20,
241 TxDescStartAddrHigh = 0x24,
242 TxHDescStartAddrLow = 0x28,
243 TxHDescStartAddrHigh = 0x2c,
244 FLASH = 0x30,
245 ERSR = 0x36,
246 ChipCmd = 0x37,
247 TxPoll = 0x38,
248 IntrMask = 0x3c,
249 IntrStatus = 0x3e,
250
251 TxConfig = 0x40,
252 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
253 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
254
255 RxConfig = 0x44,
256 #define RX128_INT_EN (1 << 15) /* 8111c and later */
257 #define RX_MULTI_EN (1 << 14) /* 8111c only */
258 #define RXCFG_FIFO_SHIFT 13
259 /* No threshold before first PCI xfer */
260 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
261 #define RX_EARLY_OFF (1 << 11)
262 #define RXCFG_DMA_SHIFT 8
263 /* Unlimited maximum PCI burst. */
264 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
265
266 RxMissed = 0x4c,
267 Cfg9346 = 0x50,
268 Config0 = 0x51,
269 Config1 = 0x52,
270 Config2 = 0x53,
271 #define PME_SIGNAL (1 << 5) /* 8168c and later */
272
273 Config3 = 0x54,
274 Config4 = 0x55,
275 Config5 = 0x56,
276 MultiIntr = 0x5c,
277 PHYAR = 0x60,
278 PHYstatus = 0x6c,
279 RxMaxSize = 0xda,
280 CPlusCmd = 0xe0,
281 IntrMitigate = 0xe2,
282
283 #define RTL_COALESCE_MASK 0x0f
284 #define RTL_COALESCE_SHIFT 4
285 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
286 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
287
288 RxDescAddrLow = 0xe4,
289 RxDescAddrHigh = 0xe8,
290 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
291
292 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
293
294 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
295
296 #define TxPacketMax (8064 >> 7)
297 #define EarlySize 0x27
298
299 FuncEvent = 0xf0,
300 FuncEventMask = 0xf4,
301 FuncPresetState = 0xf8,
302 IBCR0 = 0xf8,
303 IBCR2 = 0xf9,
304 IBIMR0 = 0xfa,
305 IBISR0 = 0xfb,
306 FuncForceEvent = 0xfc,
307 };
308
309 enum rtl8168_8101_registers {
310 CSIDR = 0x64,
311 CSIAR = 0x68,
312 #define CSIAR_FLAG 0x80000000
313 #define CSIAR_WRITE_CMD 0x80000000
314 #define CSIAR_BYTE_ENABLE 0x0000f000
315 #define CSIAR_ADDR_MASK 0x00000fff
316 PMCH = 0x6f,
317 EPHYAR = 0x80,
318 #define EPHYAR_FLAG 0x80000000
319 #define EPHYAR_WRITE_CMD 0x80000000
320 #define EPHYAR_REG_MASK 0x1f
321 #define EPHYAR_REG_SHIFT 16
322 #define EPHYAR_DATA_MASK 0xffff
323 DLLPR = 0xd0,
324 #define PFM_EN (1 << 6)
325 #define TX_10M_PS_EN (1 << 7)
326 DBG_REG = 0xd1,
327 #define FIX_NAK_1 (1 << 4)
328 #define FIX_NAK_2 (1 << 3)
329 TWSI = 0xd2,
330 MCU = 0xd3,
331 #define NOW_IS_OOB (1 << 7)
332 #define TX_EMPTY (1 << 5)
333 #define RX_EMPTY (1 << 4)
334 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
335 #define EN_NDP (1 << 3)
336 #define EN_OOB_RESET (1 << 2)
337 #define LINK_LIST_RDY (1 << 1)
338 EFUSEAR = 0xdc,
339 #define EFUSEAR_FLAG 0x80000000
340 #define EFUSEAR_WRITE_CMD 0x80000000
341 #define EFUSEAR_READ_CMD 0x00000000
342 #define EFUSEAR_REG_MASK 0x03ff
343 #define EFUSEAR_REG_SHIFT 8
344 #define EFUSEAR_DATA_MASK 0xff
345 MISC_1 = 0xf2,
346 #define PFM_D3COLD_EN (1 << 6)
347 };
348
349 enum rtl8168_registers {
350 LED_FREQ = 0x1a,
351 EEE_LED = 0x1b,
352 ERIDR = 0x70,
353 ERIAR = 0x74,
354 #define ERIAR_FLAG 0x80000000
355 #define ERIAR_WRITE_CMD 0x80000000
356 #define ERIAR_READ_CMD 0x00000000
357 #define ERIAR_ADDR_BYTE_ALIGN 4
358 #define ERIAR_TYPE_SHIFT 16
359 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
360 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
361 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
362 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
363 #define ERIAR_MASK_SHIFT 12
364 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
365 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
366 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
367 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
368 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
369 EPHY_RXER_NUM = 0x7c,
370 OCPDR = 0xb0, /* OCP GPHY access */
371 #define OCPDR_WRITE_CMD 0x80000000
372 #define OCPDR_READ_CMD 0x00000000
373 #define OCPDR_REG_MASK 0x7f
374 #define OCPDR_GPHY_REG_SHIFT 16
375 #define OCPDR_DATA_MASK 0xffff
376 OCPAR = 0xb4,
377 #define OCPAR_FLAG 0x80000000
378 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
379 #define OCPAR_GPHY_READ_CMD 0x0000f060
380 GPHY_OCP = 0xb8,
381 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
382 MISC = 0xf0, /* 8168e only. */
383 #define TXPLA_RST (1 << 29)
384 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
385 #define PWM_EN (1 << 22)
386 #define RXDV_GATED_EN (1 << 19)
387 #define EARLY_TALLY_EN (1 << 16)
388 };
389
390 enum rtl_register_content {
391 /* InterruptStatusBits */
392 SYSErr = 0x8000,
393 PCSTimeout = 0x4000,
394 SWInt = 0x0100,
395 TxDescUnavail = 0x0080,
396 RxFIFOOver = 0x0040,
397 LinkChg = 0x0020,
398 RxOverflow = 0x0010,
399 TxErr = 0x0008,
400 TxOK = 0x0004,
401 RxErr = 0x0002,
402 RxOK = 0x0001,
403
404 /* RxStatusDesc */
405 RxRWT = (1 << 22),
406 RxRES = (1 << 21),
407 RxRUNT = (1 << 20),
408 RxCRC = (1 << 19),
409
410 /* ChipCmdBits */
411 StopReq = 0x80,
412 CmdReset = 0x10,
413 CmdRxEnb = 0x08,
414 CmdTxEnb = 0x04,
415 RxBufEmpty = 0x01,
416
417 /* TXPoll register p.5 */
418 HPQ = 0x80, /* Poll cmd on the high prio queue */
419 NPQ = 0x40, /* Poll cmd on the low prio queue */
420 FSWInt = 0x01, /* Forced software interrupt */
421
422 /* Cfg9346Bits */
423 Cfg9346_Lock = 0x00,
424 Cfg9346_Unlock = 0xc0,
425
426 /* rx_mode_bits */
427 AcceptErr = 0x20,
428 AcceptRunt = 0x10,
429 AcceptBroadcast = 0x08,
430 AcceptMulticast = 0x04,
431 AcceptMyPhys = 0x02,
432 AcceptAllPhys = 0x01,
433 #define RX_CONFIG_ACCEPT_MASK 0x3f
434
435 /* TxConfigBits */
436 TxInterFrameGapShift = 24,
437 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
438
439 /* Config1 register p.24 */
440 LEDS1 = (1 << 7),
441 LEDS0 = (1 << 6),
442 Speed_down = (1 << 4),
443 MEMMAP = (1 << 3),
444 IOMAP = (1 << 2),
445 VPD = (1 << 1),
446 PMEnable = (1 << 0), /* Power Management Enable */
447
448 /* Config2 register p. 25 */
449 ClkReqEn = (1 << 7), /* Clock Request Enable */
450 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
451 PCI_Clock_66MHz = 0x01,
452 PCI_Clock_33MHz = 0x00,
453
454 /* Config3 register p.25 */
455 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
456 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
457 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
458 Rdy_to_L23 = (1 << 1), /* L23 Enable */
459 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
460
461 /* Config4 register */
462 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
463
464 /* Config5 register p.27 */
465 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
466 MWF = (1 << 5), /* Accept Multicast wakeup frame */
467 UWF = (1 << 4), /* Accept Unicast wakeup frame */
468 Spi_en = (1 << 3),
469 LanWake = (1 << 1), /* LanWake enable/disable */
470 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
471 ASPM_en = (1 << 0), /* ASPM enable */
472
473 /* CPlusCmd p.31 */
474 EnableBist = (1 << 15), // 8168 8101
475 Mac_dbgo_oe = (1 << 14), // 8168 8101
476 Normal_mode = (1 << 13), // unused
477 Force_half_dup = (1 << 12), // 8168 8101
478 Force_rxflow_en = (1 << 11), // 8168 8101
479 Force_txflow_en = (1 << 10), // 8168 8101
480 Cxpl_dbg_sel = (1 << 9), // 8168 8101
481 ASF = (1 << 8), // 8168 8101
482 PktCntrDisable = (1 << 7), // 8168 8101
483 Mac_dbgo_sel = 0x001c, // 8168
484 RxVlan = (1 << 6),
485 RxChkSum = (1 << 5),
486 PCIDAC = (1 << 4),
487 PCIMulRW = (1 << 3),
488 #define INTT_MASK GENMASK(1, 0)
489 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
490
491 /* rtl8169_PHYstatus */
492 TBI_Enable = 0x80,
493 TxFlowCtrl = 0x40,
494 RxFlowCtrl = 0x20,
495 _1000bpsF = 0x10,
496 _100bps = 0x08,
497 _10bps = 0x04,
498 LinkStatus = 0x02,
499 FullDup = 0x01,
500
501 /* ResetCounterCommand */
502 CounterReset = 0x1,
503
504 /* DumpCounterCommand */
505 CounterDump = 0x8,
506
507 /* magic enable v2 */
508 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
509 };
510
511 enum rtl_desc_bit {
512 /* First doubleword. */
513 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
514 RingEnd = (1 << 30), /* End of descriptor ring */
515 FirstFrag = (1 << 29), /* First segment of a packet */
516 LastFrag = (1 << 28), /* Final segment of a packet */
517 };
518
519 /* Generic case. */
520 enum rtl_tx_desc_bit {
521 /* First doubleword. */
522 TD_LSO = (1 << 27), /* Large Send Offload */
523 #define TD_MSS_MAX 0x07ffu /* MSS value */
524
525 /* Second doubleword. */
526 TxVlanTag = (1 << 17), /* Add VLAN tag */
527 };
528
529 /* 8169, 8168b and 810x except 8102e. */
530 enum rtl_tx_desc_bit_0 {
531 /* First doubleword. */
532 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
533 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
534 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
535 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
536 };
537
538 /* 8102e, 8168c and beyond. */
539 enum rtl_tx_desc_bit_1 {
540 /* First doubleword. */
541 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
542 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
543 #define GTTCPHO_SHIFT 18
544 #define GTTCPHO_MAX 0x7fU
545
546 /* Second doubleword. */
547 #define TCPHO_SHIFT 18
548 #define TCPHO_MAX 0x3ffU
549 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
550 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
551 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
552 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
553 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
554 };
555
556 enum rtl_rx_desc_bit {
557 /* Rx private */
558 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
559 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
560
561 #define RxProtoUDP (PID1)
562 #define RxProtoTCP (PID0)
563 #define RxProtoIP (PID1 | PID0)
564 #define RxProtoMask RxProtoIP
565
566 IPFail = (1 << 16), /* IP checksum failed */
567 UDPFail = (1 << 15), /* UDP/IP checksum failed */
568 TCPFail = (1 << 14), /* TCP/IP checksum failed */
569 RxVlanTag = (1 << 16), /* VLAN tag available */
570 };
571
572 #define RsvdMask 0x3fffc000
573
574 struct TxDesc {
575 __le32 opts1;
576 __le32 opts2;
577 __le64 addr;
578 };
579
580 struct RxDesc {
581 __le32 opts1;
582 __le32 opts2;
583 __le64 addr;
584 };
585
586 struct ring_info {
587 struct sk_buff *skb;
588 u32 len;
589 };
590
591 struct rtl8169_counters {
592 __le64 tx_packets;
593 __le64 rx_packets;
594 __le64 tx_errors;
595 __le32 rx_errors;
596 __le16 rx_missed;
597 __le16 align_errors;
598 __le32 tx_one_collision;
599 __le32 tx_multi_collision;
600 __le64 rx_unicast;
601 __le64 rx_broadcast;
602 __le32 rx_multicast;
603 __le16 tx_aborted;
604 __le16 tx_underun;
605 };
606
607 struct rtl8169_tc_offsets {
608 bool inited;
609 __le64 tx_errors;
610 __le32 tx_multi_collision;
611 __le16 tx_aborted;
612 };
613
614 enum rtl_flag {
615 RTL_FLAG_TASK_ENABLED = 0,
616 RTL_FLAG_TASK_RESET_PENDING,
617 RTL_FLAG_MAX
618 };
619
620 struct rtl8169_stats {
621 u64 packets;
622 u64 bytes;
623 struct u64_stats_sync syncp;
624 };
625
626 struct rtl8169_private {
627 void __iomem *mmio_addr; /* memory map physical address */
628 struct pci_dev *pci_dev;
629 struct net_device *dev;
630 struct phy_device *phydev;
631 struct napi_struct napi;
632 u32 msg_enable;
633 enum mac_version mac_version;
634 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
635 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
636 u32 dirty_tx;
637 struct rtl8169_stats rx_stats;
638 struct rtl8169_stats tx_stats;
639 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
640 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
641 dma_addr_t TxPhyAddr;
642 dma_addr_t RxPhyAddr;
643 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
644 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
645 u16 cp_cmd;
646 u16 irq_mask;
647 struct clk *clk;
648
649 struct {
650 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
651 struct mutex mutex;
652 struct work_struct work;
653 } wk;
654
655 unsigned irq_enabled:1;
656 unsigned supports_gmii:1;
657 dma_addr_t counters_phys_addr;
658 struct rtl8169_counters *counters;
659 struct rtl8169_tc_offsets tc_offset;
660 u32 saved_wolopts;
661
662 const char *fw_name;
663 struct rtl_fw *rtl_fw;
664
665 u32 ocp_base;
666 };
667
668 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
669
670 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
671 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
672 module_param_named(debug, debug.msg_enable, int, 0);
673 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
674 MODULE_SOFTDEP("pre: realtek");
675 MODULE_LICENSE("GPL");
676 MODULE_FIRMWARE(FIRMWARE_8168D_1);
677 MODULE_FIRMWARE(FIRMWARE_8168D_2);
678 MODULE_FIRMWARE(FIRMWARE_8168E_1);
679 MODULE_FIRMWARE(FIRMWARE_8168E_2);
680 MODULE_FIRMWARE(FIRMWARE_8168E_3);
681 MODULE_FIRMWARE(FIRMWARE_8105E_1);
682 MODULE_FIRMWARE(FIRMWARE_8168F_1);
683 MODULE_FIRMWARE(FIRMWARE_8168F_2);
684 MODULE_FIRMWARE(FIRMWARE_8402_1);
685 MODULE_FIRMWARE(FIRMWARE_8411_1);
686 MODULE_FIRMWARE(FIRMWARE_8411_2);
687 MODULE_FIRMWARE(FIRMWARE_8106E_1);
688 MODULE_FIRMWARE(FIRMWARE_8106E_2);
689 MODULE_FIRMWARE(FIRMWARE_8168G_2);
690 MODULE_FIRMWARE(FIRMWARE_8168G_3);
691 MODULE_FIRMWARE(FIRMWARE_8168H_1);
692 MODULE_FIRMWARE(FIRMWARE_8168H_2);
693 MODULE_FIRMWARE(FIRMWARE_8107E_1);
694 MODULE_FIRMWARE(FIRMWARE_8107E_2);
695
696 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
697 {
698 return &tp->pci_dev->dev;
699 }
700
701 static void rtl_lock_work(struct rtl8169_private *tp)
702 {
703 mutex_lock(&tp->wk.mutex);
704 }
705
706 static void rtl_unlock_work(struct rtl8169_private *tp)
707 {
708 mutex_unlock(&tp->wk.mutex);
709 }
710
711 static void rtl_lock_config_regs(struct rtl8169_private *tp)
712 {
713 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
714 }
715
716 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
717 {
718 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
719 }
720
721 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
722 {
723 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
724 PCI_EXP_DEVCTL_READRQ, force);
725 }
726
727 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
728 {
729 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
730 tp->mac_version != RTL_GIGA_MAC_VER_39;
731 }
732
733 struct rtl_cond {
734 bool (*check)(struct rtl8169_private *);
735 const char *msg;
736 };
737
738 static void rtl_udelay(unsigned int d)
739 {
740 udelay(d);
741 }
742
743 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
744 void (*delay)(unsigned int), unsigned int d, int n,
745 bool high)
746 {
747 int i;
748
749 for (i = 0; i < n; i++) {
750 if (c->check(tp) == high)
751 return true;
752 delay(d);
753 }
754 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
755 c->msg, !high, n, d);
756 return false;
757 }
758
759 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
760 const struct rtl_cond *c,
761 unsigned int d, int n)
762 {
763 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
764 }
765
766 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
767 const struct rtl_cond *c,
768 unsigned int d, int n)
769 {
770 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
771 }
772
773 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
774 const struct rtl_cond *c,
775 unsigned int d, int n)
776 {
777 return rtl_loop_wait(tp, c, msleep, d, n, true);
778 }
779
780 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
781 const struct rtl_cond *c,
782 unsigned int d, int n)
783 {
784 return rtl_loop_wait(tp, c, msleep, d, n, false);
785 }
786
787 #define DECLARE_RTL_COND(name) \
788 static bool name ## _check(struct rtl8169_private *); \
789 \
790 static const struct rtl_cond name = { \
791 .check = name ## _check, \
792 .msg = #name \
793 }; \
794 \
795 static bool name ## _check(struct rtl8169_private *tp)
796
797 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
798 {
799 if (reg & 0xffff0001) {
800 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
801 return true;
802 }
803 return false;
804 }
805
806 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
807 {
808 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
809 }
810
811 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
812 {
813 if (rtl_ocp_reg_failure(tp, reg))
814 return;
815
816 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
817
818 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
819 }
820
821 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
822 {
823 if (rtl_ocp_reg_failure(tp, reg))
824 return 0;
825
826 RTL_W32(tp, GPHY_OCP, reg << 15);
827
828 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
829 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
830 }
831
832 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
833 {
834 if (rtl_ocp_reg_failure(tp, reg))
835 return;
836
837 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
838 }
839
840 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
841 {
842 if (rtl_ocp_reg_failure(tp, reg))
843 return 0;
844
845 RTL_W32(tp, OCPDR, reg << 15);
846
847 return RTL_R32(tp, OCPDR);
848 }
849
850 #define OCP_STD_PHY_BASE 0xa400
851
852 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
853 {
854 if (reg == 0x1f) {
855 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
856 return;
857 }
858
859 if (tp->ocp_base != OCP_STD_PHY_BASE)
860 reg -= 0x10;
861
862 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
863 }
864
865 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
866 {
867 if (tp->ocp_base != OCP_STD_PHY_BASE)
868 reg -= 0x10;
869
870 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
871 }
872
873 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
874 {
875 if (reg == 0x1f) {
876 tp->ocp_base = value << 4;
877 return;
878 }
879
880 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
881 }
882
883 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
884 {
885 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
886 }
887
888 DECLARE_RTL_COND(rtl_phyar_cond)
889 {
890 return RTL_R32(tp, PHYAR) & 0x80000000;
891 }
892
893 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
894 {
895 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
896
897 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
898 /*
899 * According to hardware specs a 20us delay is required after write
900 * complete indication, but before sending next command.
901 */
902 udelay(20);
903 }
904
905 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
906 {
907 int value;
908
909 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
910
911 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
912 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
913
914 /*
915 * According to hardware specs a 20us delay is required after read
916 * complete indication, but before sending next command.
917 */
918 udelay(20);
919
920 return value;
921 }
922
923 DECLARE_RTL_COND(rtl_ocpar_cond)
924 {
925 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
926 }
927
928 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
929 {
930 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
931 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
932 RTL_W32(tp, EPHY_RXER_NUM, 0);
933
934 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
935 }
936
937 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
938 {
939 r8168dp_1_mdio_access(tp, reg,
940 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
941 }
942
943 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
944 {
945 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
946
947 mdelay(1);
948 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
949 RTL_W32(tp, EPHY_RXER_NUM, 0);
950
951 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
952 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
953 }
954
955 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
956
957 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
958 {
959 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
960 }
961
962 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
963 {
964 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
965 }
966
967 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
968 {
969 r8168dp_2_mdio_start(tp);
970
971 r8169_mdio_write(tp, reg, value);
972
973 r8168dp_2_mdio_stop(tp);
974 }
975
976 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
977 {
978 int value;
979
980 r8168dp_2_mdio_start(tp);
981
982 value = r8169_mdio_read(tp, reg);
983
984 r8168dp_2_mdio_stop(tp);
985
986 return value;
987 }
988
989 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
990 {
991 switch (tp->mac_version) {
992 case RTL_GIGA_MAC_VER_27:
993 r8168dp_1_mdio_write(tp, location, val);
994 break;
995 case RTL_GIGA_MAC_VER_28:
996 case RTL_GIGA_MAC_VER_31:
997 r8168dp_2_mdio_write(tp, location, val);
998 break;
999 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1000 r8168g_mdio_write(tp, location, val);
1001 break;
1002 default:
1003 r8169_mdio_write(tp, location, val);
1004 break;
1005 }
1006 }
1007
1008 static int rtl_readphy(struct rtl8169_private *tp, int location)
1009 {
1010 switch (tp->mac_version) {
1011 case RTL_GIGA_MAC_VER_27:
1012 return r8168dp_1_mdio_read(tp, location);
1013 case RTL_GIGA_MAC_VER_28:
1014 case RTL_GIGA_MAC_VER_31:
1015 return r8168dp_2_mdio_read(tp, location);
1016 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1017 return r8168g_mdio_read(tp, location);
1018 default:
1019 return r8169_mdio_read(tp, location);
1020 }
1021 }
1022
1023 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1024 {
1025 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1026 }
1027
1028 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1029 {
1030 int val;
1031
1032 val = rtl_readphy(tp, reg_addr);
1033 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1034 }
1035
1036 DECLARE_RTL_COND(rtl_ephyar_cond)
1037 {
1038 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1039 }
1040
1041 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1042 {
1043 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1044 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1045
1046 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1047
1048 udelay(10);
1049 }
1050
1051 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1052 {
1053 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1054
1055 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1056 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1057 }
1058
1059 DECLARE_RTL_COND(rtl_eriar_cond)
1060 {
1061 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1062 }
1063
1064 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1065 u32 val, int type)
1066 {
1067 BUG_ON((addr & 3) || (mask == 0));
1068 RTL_W32(tp, ERIDR, val);
1069 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1070
1071 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1072 }
1073
1074 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1075 u32 val)
1076 {
1077 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1078 }
1079
1080 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1081 {
1082 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1083
1084 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1085 RTL_R32(tp, ERIDR) : ~0;
1086 }
1087
1088 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1089 {
1090 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1091 }
1092
1093 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1094 u32 m)
1095 {
1096 u32 val;
1097
1098 val = rtl_eri_read(tp, addr);
1099 rtl_eri_write(tp, addr, mask, (val & ~m) | p);
1100 }
1101
1102 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,
1103 u32 p)
1104 {
1105 rtl_w0w1_eri(tp, addr, mask, p, 0);
1106 }
1107
1108 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
1109 u32 m)
1110 {
1111 rtl_w0w1_eri(tp, addr, mask, 0, m);
1112 }
1113
1114 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1115 {
1116 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1117 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1118 RTL_R32(tp, OCPDR) : ~0;
1119 }
1120
1121 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1122 {
1123 return _rtl_eri_read(tp, reg, ERIAR_OOB);
1124 }
1125
1126 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1127 u32 data)
1128 {
1129 RTL_W32(tp, OCPDR, data);
1130 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1131 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1132 }
1133
1134 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1135 u32 data)
1136 {
1137 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1138 data, ERIAR_OOB);
1139 }
1140
1141 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1142 {
1143 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1144
1145 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1146 }
1147
1148 #define OOB_CMD_RESET 0x00
1149 #define OOB_CMD_DRIVER_START 0x05
1150 #define OOB_CMD_DRIVER_STOP 0x06
1151
1152 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1153 {
1154 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1155 }
1156
1157 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1158 {
1159 u16 reg;
1160
1161 reg = rtl8168_get_ocp_reg(tp);
1162
1163 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1164 }
1165
1166 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1167 {
1168 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1169 }
1170
1171 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1172 {
1173 return RTL_R8(tp, IBISR0) & 0x20;
1174 }
1175
1176 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1177 {
1178 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1179 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1180 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1181 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1182 }
1183
1184 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1185 {
1186 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1187 rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1188 }
1189
1190 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1191 {
1192 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1193 r8168ep_ocp_write(tp, 0x01, 0x30,
1194 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1195 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1196 }
1197
1198 static void rtl8168_driver_start(struct rtl8169_private *tp)
1199 {
1200 switch (tp->mac_version) {
1201 case RTL_GIGA_MAC_VER_27:
1202 case RTL_GIGA_MAC_VER_28:
1203 case RTL_GIGA_MAC_VER_31:
1204 rtl8168dp_driver_start(tp);
1205 break;
1206 case RTL_GIGA_MAC_VER_49:
1207 case RTL_GIGA_MAC_VER_50:
1208 case RTL_GIGA_MAC_VER_51:
1209 rtl8168ep_driver_start(tp);
1210 break;
1211 default:
1212 BUG();
1213 break;
1214 }
1215 }
1216
1217 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1218 {
1219 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1220 rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1221 }
1222
1223 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1224 {
1225 rtl8168ep_stop_cmac(tp);
1226 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1227 r8168ep_ocp_write(tp, 0x01, 0x30,
1228 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1229 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1230 }
1231
1232 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1233 {
1234 switch (tp->mac_version) {
1235 case RTL_GIGA_MAC_VER_27:
1236 case RTL_GIGA_MAC_VER_28:
1237 case RTL_GIGA_MAC_VER_31:
1238 rtl8168dp_driver_stop(tp);
1239 break;
1240 case RTL_GIGA_MAC_VER_49:
1241 case RTL_GIGA_MAC_VER_50:
1242 case RTL_GIGA_MAC_VER_51:
1243 rtl8168ep_driver_stop(tp);
1244 break;
1245 default:
1246 BUG();
1247 break;
1248 }
1249 }
1250
1251 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1252 {
1253 u16 reg = rtl8168_get_ocp_reg(tp);
1254
1255 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1256 }
1257
1258 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1259 {
1260 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1261 }
1262
1263 static bool r8168_check_dash(struct rtl8169_private *tp)
1264 {
1265 switch (tp->mac_version) {
1266 case RTL_GIGA_MAC_VER_27:
1267 case RTL_GIGA_MAC_VER_28:
1268 case RTL_GIGA_MAC_VER_31:
1269 return r8168dp_check_dash(tp);
1270 case RTL_GIGA_MAC_VER_49:
1271 case RTL_GIGA_MAC_VER_50:
1272 case RTL_GIGA_MAC_VER_51:
1273 return r8168ep_check_dash(tp);
1274 default:
1275 return false;
1276 }
1277 }
1278
1279 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1280 {
1281 rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1282 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1283 }
1284
1285 DECLARE_RTL_COND(rtl_efusear_cond)
1286 {
1287 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1288 }
1289
1290 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1291 {
1292 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1293
1294 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1295 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1296 }
1297
1298 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1299 {
1300 RTL_W16(tp, IntrStatus, bits);
1301 }
1302
1303 static void rtl_irq_disable(struct rtl8169_private *tp)
1304 {
1305 RTL_W16(tp, IntrMask, 0);
1306 tp->irq_enabled = 0;
1307 }
1308
1309 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1310 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1311 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1312
1313 static void rtl_irq_enable(struct rtl8169_private *tp)
1314 {
1315 tp->irq_enabled = 1;
1316 RTL_W16(tp, IntrMask, tp->irq_mask);
1317 }
1318
1319 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1320 {
1321 rtl_irq_disable(tp);
1322 rtl_ack_events(tp, 0xffff);
1323 /* PCI commit */
1324 RTL_R8(tp, ChipCmd);
1325 }
1326
1327 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1328 {
1329 struct net_device *dev = tp->dev;
1330 struct phy_device *phydev = tp->phydev;
1331
1332 if (!netif_running(dev))
1333 return;
1334
1335 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1336 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1337 if (phydev->speed == SPEED_1000) {
1338 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1339 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1340 } else if (phydev->speed == SPEED_100) {
1341 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1342 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1343 } else {
1344 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1345 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1346 }
1347 rtl_reset_packet_filter(tp);
1348 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1349 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1350 if (phydev->speed == SPEED_1000) {
1351 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1352 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1353 } else {
1354 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1355 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1356 }
1357 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1358 if (phydev->speed == SPEED_10) {
1359 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1360 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1361 } else {
1362 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1363 }
1364 }
1365 }
1366
1367 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1368
1369 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1370 {
1371 struct rtl8169_private *tp = netdev_priv(dev);
1372
1373 rtl_lock_work(tp);
1374 wol->supported = WAKE_ANY;
1375 wol->wolopts = tp->saved_wolopts;
1376 rtl_unlock_work(tp);
1377 }
1378
1379 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1380 {
1381 unsigned int i, tmp;
1382 static const struct {
1383 u32 opt;
1384 u16 reg;
1385 u8 mask;
1386 } cfg[] = {
1387 { WAKE_PHY, Config3, LinkUp },
1388 { WAKE_UCAST, Config5, UWF },
1389 { WAKE_BCAST, Config5, BWF },
1390 { WAKE_MCAST, Config5, MWF },
1391 { WAKE_ANY, Config5, LanWake },
1392 { WAKE_MAGIC, Config3, MagicPacket }
1393 };
1394 u8 options;
1395
1396 rtl_unlock_config_regs(tp);
1397
1398 if (rtl_is_8168evl_up(tp)) {
1399 tmp = ARRAY_SIZE(cfg) - 1;
1400 if (wolopts & WAKE_MAGIC)
1401 rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
1402 MagicPacket_v2);
1403 else
1404 rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
1405 MagicPacket_v2);
1406 } else {
1407 tmp = ARRAY_SIZE(cfg);
1408 }
1409
1410 for (i = 0; i < tmp; i++) {
1411 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1412 if (wolopts & cfg[i].opt)
1413 options |= cfg[i].mask;
1414 RTL_W8(tp, cfg[i].reg, options);
1415 }
1416
1417 switch (tp->mac_version) {
1418 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_17:
1419 options = RTL_R8(tp, Config1) & ~PMEnable;
1420 if (wolopts)
1421 options |= PMEnable;
1422 RTL_W8(tp, Config1, options);
1423 break;
1424 default:
1425 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1426 if (wolopts)
1427 options |= PME_SIGNAL;
1428 RTL_W8(tp, Config2, options);
1429 break;
1430 }
1431
1432 rtl_lock_config_regs(tp);
1433
1434 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1435 }
1436
1437 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1438 {
1439 struct rtl8169_private *tp = netdev_priv(dev);
1440 struct device *d = tp_to_dev(tp);
1441
1442 if (wol->wolopts & ~WAKE_ANY)
1443 return -EINVAL;
1444
1445 pm_runtime_get_noresume(d);
1446
1447 rtl_lock_work(tp);
1448
1449 tp->saved_wolopts = wol->wolopts;
1450
1451 if (pm_runtime_active(d))
1452 __rtl8169_set_wol(tp, tp->saved_wolopts);
1453
1454 rtl_unlock_work(tp);
1455
1456 pm_runtime_put_noidle(d);
1457
1458 return 0;
1459 }
1460
1461 static void rtl8169_get_drvinfo(struct net_device *dev,
1462 struct ethtool_drvinfo *info)
1463 {
1464 struct rtl8169_private *tp = netdev_priv(dev);
1465 struct rtl_fw *rtl_fw = tp->rtl_fw;
1466
1467 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1468 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1469 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1470 if (rtl_fw)
1471 strlcpy(info->fw_version, rtl_fw->version,
1472 sizeof(info->fw_version));
1473 }
1474
1475 static int rtl8169_get_regs_len(struct net_device *dev)
1476 {
1477 return R8169_REGS_SIZE;
1478 }
1479
1480 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1481 netdev_features_t features)
1482 {
1483 struct rtl8169_private *tp = netdev_priv(dev);
1484
1485 if (dev->mtu > TD_MSS_MAX)
1486 features &= ~NETIF_F_ALL_TSO;
1487
1488 if (dev->mtu > JUMBO_1K &&
1489 tp->mac_version > RTL_GIGA_MAC_VER_06)
1490 features &= ~NETIF_F_IP_CSUM;
1491
1492 return features;
1493 }
1494
1495 static int rtl8169_set_features(struct net_device *dev,
1496 netdev_features_t features)
1497 {
1498 struct rtl8169_private *tp = netdev_priv(dev);
1499 u32 rx_config;
1500
1501 rtl_lock_work(tp);
1502
1503 rx_config = RTL_R32(tp, RxConfig);
1504 if (features & NETIF_F_RXALL)
1505 rx_config |= (AcceptErr | AcceptRunt);
1506 else
1507 rx_config &= ~(AcceptErr | AcceptRunt);
1508
1509 RTL_W32(tp, RxConfig, rx_config);
1510
1511 if (features & NETIF_F_RXCSUM)
1512 tp->cp_cmd |= RxChkSum;
1513 else
1514 tp->cp_cmd &= ~RxChkSum;
1515
1516 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1517 tp->cp_cmd |= RxVlan;
1518 else
1519 tp->cp_cmd &= ~RxVlan;
1520
1521 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1522 RTL_R16(tp, CPlusCmd);
1523
1524 rtl_unlock_work(tp);
1525
1526 return 0;
1527 }
1528
1529 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1530 {
1531 return (skb_vlan_tag_present(skb)) ?
1532 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1533 }
1534
1535 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1536 {
1537 u32 opts2 = le32_to_cpu(desc->opts2);
1538
1539 if (opts2 & RxVlanTag)
1540 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1541 }
1542
1543 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1544 void *p)
1545 {
1546 struct rtl8169_private *tp = netdev_priv(dev);
1547 u32 __iomem *data = tp->mmio_addr;
1548 u32 *dw = p;
1549 int i;
1550
1551 rtl_lock_work(tp);
1552 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1553 memcpy_fromio(dw++, data++, 4);
1554 rtl_unlock_work(tp);
1555 }
1556
1557 static u32 rtl8169_get_msglevel(struct net_device *dev)
1558 {
1559 struct rtl8169_private *tp = netdev_priv(dev);
1560
1561 return tp->msg_enable;
1562 }
1563
1564 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1565 {
1566 struct rtl8169_private *tp = netdev_priv(dev);
1567
1568 tp->msg_enable = value;
1569 }
1570
1571 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1572 "tx_packets",
1573 "rx_packets",
1574 "tx_errors",
1575 "rx_errors",
1576 "rx_missed",
1577 "align_errors",
1578 "tx_single_collisions",
1579 "tx_multi_collisions",
1580 "unicast",
1581 "broadcast",
1582 "multicast",
1583 "tx_aborted",
1584 "tx_underrun",
1585 };
1586
1587 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1588 {
1589 switch (sset) {
1590 case ETH_SS_STATS:
1591 return ARRAY_SIZE(rtl8169_gstrings);
1592 default:
1593 return -EOPNOTSUPP;
1594 }
1595 }
1596
1597 DECLARE_RTL_COND(rtl_counters_cond)
1598 {
1599 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1600 }
1601
1602 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1603 {
1604 dma_addr_t paddr = tp->counters_phys_addr;
1605 u32 cmd;
1606
1607 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1608 RTL_R32(tp, CounterAddrHigh);
1609 cmd = (u64)paddr & DMA_BIT_MASK(32);
1610 RTL_W32(tp, CounterAddrLow, cmd);
1611 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1612
1613 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1614 }
1615
1616 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1617 {
1618 /*
1619 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1620 * tally counters.
1621 */
1622 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1623 return true;
1624
1625 return rtl8169_do_counters(tp, CounterReset);
1626 }
1627
1628 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1629 {
1630 u8 val = RTL_R8(tp, ChipCmd);
1631
1632 /*
1633 * Some chips are unable to dump tally counters when the receiver
1634 * is disabled. If 0xff chip may be in a PCI power-save state.
1635 */
1636 if (!(val & CmdRxEnb) || val == 0xff)
1637 return true;
1638
1639 return rtl8169_do_counters(tp, CounterDump);
1640 }
1641
1642 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1643 {
1644 struct rtl8169_counters *counters = tp->counters;
1645 bool ret = false;
1646
1647 /*
1648 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1649 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1650 * reset by a power cycle, while the counter values collected by the
1651 * driver are reset at every driver unload/load cycle.
1652 *
1653 * To make sure the HW values returned by @get_stats64 match the SW
1654 * values, we collect the initial values at first open(*) and use them
1655 * as offsets to normalize the values returned by @get_stats64.
1656 *
1657 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1658 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1659 * set at open time by rtl_hw_start.
1660 */
1661
1662 if (tp->tc_offset.inited)
1663 return true;
1664
1665 /* If both, reset and update fail, propagate to caller. */
1666 if (rtl8169_reset_counters(tp))
1667 ret = true;
1668
1669 if (rtl8169_update_counters(tp))
1670 ret = true;
1671
1672 tp->tc_offset.tx_errors = counters->tx_errors;
1673 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1674 tp->tc_offset.tx_aborted = counters->tx_aborted;
1675 tp->tc_offset.inited = true;
1676
1677 return ret;
1678 }
1679
1680 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1681 struct ethtool_stats *stats, u64 *data)
1682 {
1683 struct rtl8169_private *tp = netdev_priv(dev);
1684 struct device *d = tp_to_dev(tp);
1685 struct rtl8169_counters *counters = tp->counters;
1686
1687 ASSERT_RTNL();
1688
1689 pm_runtime_get_noresume(d);
1690
1691 if (pm_runtime_active(d))
1692 rtl8169_update_counters(tp);
1693
1694 pm_runtime_put_noidle(d);
1695
1696 data[0] = le64_to_cpu(counters->tx_packets);
1697 data[1] = le64_to_cpu(counters->rx_packets);
1698 data[2] = le64_to_cpu(counters->tx_errors);
1699 data[3] = le32_to_cpu(counters->rx_errors);
1700 data[4] = le16_to_cpu(counters->rx_missed);
1701 data[5] = le16_to_cpu(counters->align_errors);
1702 data[6] = le32_to_cpu(counters->tx_one_collision);
1703 data[7] = le32_to_cpu(counters->tx_multi_collision);
1704 data[8] = le64_to_cpu(counters->rx_unicast);
1705 data[9] = le64_to_cpu(counters->rx_broadcast);
1706 data[10] = le32_to_cpu(counters->rx_multicast);
1707 data[11] = le16_to_cpu(counters->tx_aborted);
1708 data[12] = le16_to_cpu(counters->tx_underun);
1709 }
1710
1711 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1712 {
1713 switch(stringset) {
1714 case ETH_SS_STATS:
1715 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1716 break;
1717 }
1718 }
1719
1720 /*
1721 * Interrupt coalescing
1722 *
1723 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1724 * > 8169, 8168 and 810x line of chipsets
1725 *
1726 * 8169, 8168, and 8136(810x) serial chipsets support it.
1727 *
1728 * > 2 - the Tx timer unit at gigabit speed
1729 *
1730 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1731 * (0xe0) bit 1 and bit 0.
1732 *
1733 * For 8169
1734 * bit[1:0] \ speed 1000M 100M 10M
1735 * 0 0 320ns 2.56us 40.96us
1736 * 0 1 2.56us 20.48us 327.7us
1737 * 1 0 5.12us 40.96us 655.4us
1738 * 1 1 10.24us 81.92us 1.31ms
1739 *
1740 * For the other
1741 * bit[1:0] \ speed 1000M 100M 10M
1742 * 0 0 5us 2.56us 40.96us
1743 * 0 1 40us 20.48us 327.7us
1744 * 1 0 80us 40.96us 655.4us
1745 * 1 1 160us 81.92us 1.31ms
1746 */
1747
1748 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1749 struct rtl_coalesce_scale {
1750 /* Rx / Tx */
1751 u32 nsecs[2];
1752 };
1753
1754 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1755 struct rtl_coalesce_info {
1756 u32 speed;
1757 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
1758 };
1759
1760 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1761 #define rxtx_x1822(r, t) { \
1762 {{(r), (t)}}, \
1763 {{(r)*8, (t)*8}}, \
1764 {{(r)*8*2, (t)*8*2}}, \
1765 {{(r)*8*2*2, (t)*8*2*2}}, \
1766 }
1767 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1768 /* speed delays: rx00 tx00 */
1769 { SPEED_10, rxtx_x1822(40960, 40960) },
1770 { SPEED_100, rxtx_x1822( 2560, 2560) },
1771 { SPEED_1000, rxtx_x1822( 320, 320) },
1772 { 0 },
1773 };
1774
1775 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1776 /* speed delays: rx00 tx00 */
1777 { SPEED_10, rxtx_x1822(40960, 40960) },
1778 { SPEED_100, rxtx_x1822( 2560, 2560) },
1779 { SPEED_1000, rxtx_x1822( 5000, 5000) },
1780 { 0 },
1781 };
1782 #undef rxtx_x1822
1783
1784 /* get rx/tx scale vector corresponding to current speed */
1785 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1786 {
1787 struct rtl8169_private *tp = netdev_priv(dev);
1788 const struct rtl_coalesce_info *ci;
1789
1790 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1791 ci = rtl_coalesce_info_8169;
1792 else
1793 ci = rtl_coalesce_info_8168_8136;
1794
1795 for (; ci->speed; ci++) {
1796 if (tp->phydev->speed == ci->speed)
1797 return ci;
1798 }
1799
1800 return ERR_PTR(-ELNRNG);
1801 }
1802
1803 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1804 {
1805 struct rtl8169_private *tp = netdev_priv(dev);
1806 const struct rtl_coalesce_info *ci;
1807 const struct rtl_coalesce_scale *scale;
1808 struct {
1809 u32 *max_frames;
1810 u32 *usecs;
1811 } coal_settings [] = {
1812 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1813 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1814 }, *p = coal_settings;
1815 int i;
1816 u16 w;
1817
1818 memset(ec, 0, sizeof(*ec));
1819
1820 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1821 ci = rtl_coalesce_info(dev);
1822 if (IS_ERR(ci))
1823 return PTR_ERR(ci);
1824
1825 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1826
1827 /* read IntrMitigate and adjust according to scale */
1828 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1829 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1830 w >>= RTL_COALESCE_SHIFT;
1831 *p->usecs = w & RTL_COALESCE_MASK;
1832 }
1833
1834 for (i = 0; i < 2; i++) {
1835 p = coal_settings + i;
1836 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1837
1838 /*
1839 * ethtool_coalesce says it is illegal to set both usecs and
1840 * max_frames to 0.
1841 */
1842 if (!*p->usecs && !*p->max_frames)
1843 *p->max_frames = 1;
1844 }
1845
1846 return 0;
1847 }
1848
1849 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1850 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1851 struct net_device *dev, u32 nsec, u16 *cp01)
1852 {
1853 const struct rtl_coalesce_info *ci;
1854 u16 i;
1855
1856 ci = rtl_coalesce_info(dev);
1857 if (IS_ERR(ci))
1858 return ERR_CAST(ci);
1859
1860 for (i = 0; i < 4; i++) {
1861 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1862 ci->scalev[i].nsecs[1]);
1863 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1864 *cp01 = i;
1865 return &ci->scalev[i];
1866 }
1867 }
1868
1869 return ERR_PTR(-EINVAL);
1870 }
1871
1872 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1873 {
1874 struct rtl8169_private *tp = netdev_priv(dev);
1875 const struct rtl_coalesce_scale *scale;
1876 struct {
1877 u32 frames;
1878 u32 usecs;
1879 } coal_settings [] = {
1880 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1881 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1882 }, *p = coal_settings;
1883 u16 w = 0, cp01;
1884 int i;
1885
1886 scale = rtl_coalesce_choose_scale(dev,
1887 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1888 if (IS_ERR(scale))
1889 return PTR_ERR(scale);
1890
1891 for (i = 0; i < 2; i++, p++) {
1892 u32 units;
1893
1894 /*
1895 * accept max_frames=1 we returned in rtl_get_coalesce.
1896 * accept it not only when usecs=0 because of e.g. the following scenario:
1897 *
1898 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1899 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1900 * - then user does `ethtool -C eth0 rx-usecs 100`
1901 *
1902 * since ethtool sends to kernel whole ethtool_coalesce
1903 * settings, if we do not handle rx_usecs=!0, rx_frames=1
1904 * we'll reject it below in `frames % 4 != 0`.
1905 */
1906 if (p->frames == 1) {
1907 p->frames = 0;
1908 }
1909
1910 units = p->usecs * 1000 / scale->nsecs[i];
1911 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
1912 return -EINVAL;
1913
1914 w <<= RTL_COALESCE_SHIFT;
1915 w |= units;
1916 w <<= RTL_COALESCE_SHIFT;
1917 w |= p->frames >> 2;
1918 }
1919
1920 rtl_lock_work(tp);
1921
1922 RTL_W16(tp, IntrMitigate, swab16(w));
1923
1924 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1925 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1926 RTL_R16(tp, CPlusCmd);
1927
1928 rtl_unlock_work(tp);
1929
1930 return 0;
1931 }
1932
1933 static int rtl_get_eee_supp(struct rtl8169_private *tp)
1934 {
1935 struct phy_device *phydev = tp->phydev;
1936 int ret;
1937
1938 switch (tp->mac_version) {
1939 case RTL_GIGA_MAC_VER_34:
1940 case RTL_GIGA_MAC_VER_35:
1941 case RTL_GIGA_MAC_VER_36:
1942 case RTL_GIGA_MAC_VER_38:
1943 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1944 break;
1945 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1946 ret = phy_read_paged(phydev, 0x0a5c, 0x12);
1947 break;
1948 default:
1949 ret = -EPROTONOSUPPORT;
1950 break;
1951 }
1952
1953 return ret;
1954 }
1955
1956 static int rtl_get_eee_lpadv(struct rtl8169_private *tp)
1957 {
1958 struct phy_device *phydev = tp->phydev;
1959 int ret;
1960
1961 switch (tp->mac_version) {
1962 case RTL_GIGA_MAC_VER_34:
1963 case RTL_GIGA_MAC_VER_35:
1964 case RTL_GIGA_MAC_VER_36:
1965 case RTL_GIGA_MAC_VER_38:
1966 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
1967 break;
1968 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1969 ret = phy_read_paged(phydev, 0x0a5d, 0x11);
1970 break;
1971 default:
1972 ret = -EPROTONOSUPPORT;
1973 break;
1974 }
1975
1976 return ret;
1977 }
1978
1979 static int rtl_get_eee_adv(struct rtl8169_private *tp)
1980 {
1981 struct phy_device *phydev = tp->phydev;
1982 int ret;
1983
1984 switch (tp->mac_version) {
1985 case RTL_GIGA_MAC_VER_34:
1986 case RTL_GIGA_MAC_VER_35:
1987 case RTL_GIGA_MAC_VER_36:
1988 case RTL_GIGA_MAC_VER_38:
1989 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
1990 break;
1991 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1992 ret = phy_read_paged(phydev, 0x0a5d, 0x10);
1993 break;
1994 default:
1995 ret = -EPROTONOSUPPORT;
1996 break;
1997 }
1998
1999 return ret;
2000 }
2001
2002 static int rtl_set_eee_adv(struct rtl8169_private *tp, int val)
2003 {
2004 struct phy_device *phydev = tp->phydev;
2005 int ret = 0;
2006
2007 switch (tp->mac_version) {
2008 case RTL_GIGA_MAC_VER_34:
2009 case RTL_GIGA_MAC_VER_35:
2010 case RTL_GIGA_MAC_VER_36:
2011 case RTL_GIGA_MAC_VER_38:
2012 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
2013 break;
2014 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2015 phy_write_paged(phydev, 0x0a5d, 0x10, val);
2016 break;
2017 default:
2018 ret = -EPROTONOSUPPORT;
2019 break;
2020 }
2021
2022 return ret;
2023 }
2024
2025 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
2026 {
2027 struct rtl8169_private *tp = netdev_priv(dev);
2028 struct device *d = tp_to_dev(tp);
2029 int ret;
2030
2031 pm_runtime_get_noresume(d);
2032
2033 if (!pm_runtime_active(d)) {
2034 ret = -EOPNOTSUPP;
2035 goto out;
2036 }
2037
2038 /* Get Supported EEE */
2039 ret = rtl_get_eee_supp(tp);
2040 if (ret < 0)
2041 goto out;
2042 data->supported = mmd_eee_cap_to_ethtool_sup_t(ret);
2043
2044 /* Get advertisement EEE */
2045 ret = rtl_get_eee_adv(tp);
2046 if (ret < 0)
2047 goto out;
2048 data->advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2049 data->eee_enabled = !!data->advertised;
2050
2051 /* Get LP advertisement EEE */
2052 ret = rtl_get_eee_lpadv(tp);
2053 if (ret < 0)
2054 goto out;
2055 data->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2056 data->eee_active = !!(data->advertised & data->lp_advertised);
2057 out:
2058 pm_runtime_put_noidle(d);
2059 return ret < 0 ? ret : 0;
2060 }
2061
2062 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
2063 {
2064 struct rtl8169_private *tp = netdev_priv(dev);
2065 struct device *d = tp_to_dev(tp);
2066 int old_adv, adv = 0, cap, ret;
2067
2068 pm_runtime_get_noresume(d);
2069
2070 if (!dev->phydev || !pm_runtime_active(d)) {
2071 ret = -EOPNOTSUPP;
2072 goto out;
2073 }
2074
2075 if (dev->phydev->autoneg == AUTONEG_DISABLE ||
2076 dev->phydev->duplex != DUPLEX_FULL) {
2077 ret = -EPROTONOSUPPORT;
2078 goto out;
2079 }
2080
2081 /* Get Supported EEE */
2082 ret = rtl_get_eee_supp(tp);
2083 if (ret < 0)
2084 goto out;
2085 cap = ret;
2086
2087 ret = rtl_get_eee_adv(tp);
2088 if (ret < 0)
2089 goto out;
2090 old_adv = ret;
2091
2092 if (data->eee_enabled) {
2093 adv = !data->advertised ? cap :
2094 ethtool_adv_to_mmd_eee_adv_t(data->advertised) & cap;
2095 /* Mask prohibited EEE modes */
2096 adv &= ~dev->phydev->eee_broken_modes;
2097 }
2098
2099 if (old_adv != adv) {
2100 ret = rtl_set_eee_adv(tp, adv);
2101 if (ret < 0)
2102 goto out;
2103
2104 /* Restart autonegotiation so the new modes get sent to the
2105 * link partner.
2106 */
2107 ret = phy_restart_aneg(dev->phydev);
2108 }
2109
2110 out:
2111 pm_runtime_put_noidle(d);
2112 return ret < 0 ? ret : 0;
2113 }
2114
2115 static const struct ethtool_ops rtl8169_ethtool_ops = {
2116 .get_drvinfo = rtl8169_get_drvinfo,
2117 .get_regs_len = rtl8169_get_regs_len,
2118 .get_link = ethtool_op_get_link,
2119 .get_coalesce = rtl_get_coalesce,
2120 .set_coalesce = rtl_set_coalesce,
2121 .get_msglevel = rtl8169_get_msglevel,
2122 .set_msglevel = rtl8169_set_msglevel,
2123 .get_regs = rtl8169_get_regs,
2124 .get_wol = rtl8169_get_wol,
2125 .set_wol = rtl8169_set_wol,
2126 .get_strings = rtl8169_get_strings,
2127 .get_sset_count = rtl8169_get_sset_count,
2128 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2129 .get_ts_info = ethtool_op_get_ts_info,
2130 .nway_reset = phy_ethtool_nway_reset,
2131 .get_eee = rtl8169_get_eee,
2132 .set_eee = rtl8169_set_eee,
2133 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2134 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2135 };
2136
2137 static void rtl_enable_eee(struct rtl8169_private *tp)
2138 {
2139 int supported = rtl_get_eee_supp(tp);
2140
2141 if (supported > 0)
2142 rtl_set_eee_adv(tp, supported);
2143 }
2144
2145 static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2146 {
2147 /*
2148 * The driver currently handles the 8168Bf and the 8168Be identically
2149 * but they can be identified more specifically through the test below
2150 * if needed:
2151 *
2152 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2153 *
2154 * Same thing for the 8101Eb and the 8101Ec:
2155 *
2156 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2157 */
2158 static const struct rtl_mac_info {
2159 u16 mask;
2160 u16 val;
2161 u16 mac_version;
2162 } mac_info[] = {
2163 /* 8168EP family. */
2164 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2165 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2166 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2167
2168 /* 8168H family. */
2169 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2170 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2171
2172 /* 8168G family. */
2173 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2174 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2175 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2176 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2177
2178 /* 8168F family. */
2179 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2180 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2181 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2182
2183 /* 8168E family. */
2184 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2185 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2186 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2187
2188 /* 8168D family. */
2189 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2190 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2191
2192 /* 8168DP family. */
2193 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2194 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2195 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2196
2197 /* 8168C family. */
2198 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2199 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2200 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2201 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2202 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2203 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2204 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2205
2206 /* 8168B family. */
2207 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2208 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2209 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2210
2211 /* 8101 family. */
2212 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2213 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2214 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2215 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2216 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2217 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2218 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2219 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2220 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2221 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2222 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2223 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2224 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2225 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2226 /* FIXME: where did these entries come from ? -- FR */
2227 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2228 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2229
2230 /* 8110 family. */
2231 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2232 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2233 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2234 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2235 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2236
2237 /* Catch-all */
2238 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
2239 };
2240 const struct rtl_mac_info *p = mac_info;
2241 u16 reg = RTL_R32(tp, TxConfig) >> 20;
2242
2243 while ((reg & p->mask) != p->val)
2244 p++;
2245 tp->mac_version = p->mac_version;
2246
2247 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2248 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2249 } else if (!tp->supports_gmii) {
2250 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2251 tp->mac_version = RTL_GIGA_MAC_VER_43;
2252 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2253 tp->mac_version = RTL_GIGA_MAC_VER_47;
2254 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2255 tp->mac_version = RTL_GIGA_MAC_VER_48;
2256 }
2257 }
2258
2259 struct phy_reg {
2260 u16 reg;
2261 u16 val;
2262 };
2263
2264 static void __rtl_writephy_batch(struct rtl8169_private *tp,
2265 const struct phy_reg *regs, int len)
2266 {
2267 while (len-- > 0) {
2268 rtl_writephy(tp, regs->reg, regs->val);
2269 regs++;
2270 }
2271 }
2272
2273 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a))
2274
2275 static void rtl_release_firmware(struct rtl8169_private *tp)
2276 {
2277 if (tp->rtl_fw) {
2278 rtl_fw_release_firmware(tp->rtl_fw);
2279 kfree(tp->rtl_fw);
2280 tp->rtl_fw = NULL;
2281 }
2282 }
2283
2284 static void rtl_apply_firmware(struct rtl8169_private *tp)
2285 {
2286 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2287 if (tp->rtl_fw)
2288 rtl_fw_write_firmware(tp, tp->rtl_fw);
2289 }
2290
2291 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2292 {
2293 if (rtl_readphy(tp, reg) != val)
2294 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2295 else
2296 rtl_apply_firmware(tp);
2297 }
2298
2299 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2300 {
2301 /* Adjust EEE LED frequency */
2302 if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2303 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2304
2305 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);
2306 }
2307
2308 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2309 {
2310 struct phy_device *phydev = tp->phydev;
2311
2312 phy_write(phydev, 0x1f, 0x0007);
2313 phy_write(phydev, 0x1e, 0x0020);
2314 phy_set_bits(phydev, 0x15, BIT(8));
2315
2316 phy_write(phydev, 0x1f, 0x0005);
2317 phy_write(phydev, 0x05, 0x8b85);
2318 phy_set_bits(phydev, 0x06, BIT(13));
2319
2320 phy_write(phydev, 0x1f, 0x0000);
2321 }
2322
2323 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2324 {
2325 phy_modify_paged(tp->phydev, 0x0a43, 0x11, 0, BIT(4));
2326 }
2327
2328 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2329 {
2330 static const struct phy_reg phy_reg_init[] = {
2331 { 0x1f, 0x0001 },
2332 { 0x06, 0x006e },
2333 { 0x08, 0x0708 },
2334 { 0x15, 0x4000 },
2335 { 0x18, 0x65c7 },
2336
2337 { 0x1f, 0x0001 },
2338 { 0x03, 0x00a1 },
2339 { 0x02, 0x0008 },
2340 { 0x01, 0x0120 },
2341 { 0x00, 0x1000 },
2342 { 0x04, 0x0800 },
2343 { 0x04, 0x0000 },
2344
2345 { 0x03, 0xff41 },
2346 { 0x02, 0xdf60 },
2347 { 0x01, 0x0140 },
2348 { 0x00, 0x0077 },
2349 { 0x04, 0x7800 },
2350 { 0x04, 0x7000 },
2351
2352 { 0x03, 0x802f },
2353 { 0x02, 0x4f02 },
2354 { 0x01, 0x0409 },
2355 { 0x00, 0xf0f9 },
2356 { 0x04, 0x9800 },
2357 { 0x04, 0x9000 },
2358
2359 { 0x03, 0xdf01 },
2360 { 0x02, 0xdf20 },
2361 { 0x01, 0xff95 },
2362 { 0x00, 0xba00 },
2363 { 0x04, 0xa800 },
2364 { 0x04, 0xa000 },
2365
2366 { 0x03, 0xff41 },
2367 { 0x02, 0xdf20 },
2368 { 0x01, 0x0140 },
2369 { 0x00, 0x00bb },
2370 { 0x04, 0xb800 },
2371 { 0x04, 0xb000 },
2372
2373 { 0x03, 0xdf41 },
2374 { 0x02, 0xdc60 },
2375 { 0x01, 0x6340 },
2376 { 0x00, 0x007d },
2377 { 0x04, 0xd800 },
2378 { 0x04, 0xd000 },
2379
2380 { 0x03, 0xdf01 },
2381 { 0x02, 0xdf20 },
2382 { 0x01, 0x100a },
2383 { 0x00, 0xa0ff },
2384 { 0x04, 0xf800 },
2385 { 0x04, 0xf000 },
2386
2387 { 0x1f, 0x0000 },
2388 { 0x0b, 0x0000 },
2389 { 0x00, 0x9200 }
2390 };
2391
2392 rtl_writephy_batch(tp, phy_reg_init);
2393 }
2394
2395 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2396 {
2397 static const struct phy_reg phy_reg_init[] = {
2398 { 0x1f, 0x0002 },
2399 { 0x01, 0x90d0 },
2400 { 0x1f, 0x0000 }
2401 };
2402
2403 rtl_writephy_batch(tp, phy_reg_init);
2404 }
2405
2406 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2407 {
2408 struct pci_dev *pdev = tp->pci_dev;
2409
2410 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2411 (pdev->subsystem_device != 0xe000))
2412 return;
2413
2414 rtl_writephy(tp, 0x1f, 0x0001);
2415 rtl_writephy(tp, 0x10, 0xf01b);
2416 rtl_writephy(tp, 0x1f, 0x0000);
2417 }
2418
2419 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2420 {
2421 static const struct phy_reg phy_reg_init[] = {
2422 { 0x1f, 0x0001 },
2423 { 0x04, 0x0000 },
2424 { 0x03, 0x00a1 },
2425 { 0x02, 0x0008 },
2426 { 0x01, 0x0120 },
2427 { 0x00, 0x1000 },
2428 { 0x04, 0x0800 },
2429 { 0x04, 0x9000 },
2430 { 0x03, 0x802f },
2431 { 0x02, 0x4f02 },
2432 { 0x01, 0x0409 },
2433 { 0x00, 0xf099 },
2434 { 0x04, 0x9800 },
2435 { 0x04, 0xa000 },
2436 { 0x03, 0xdf01 },
2437 { 0x02, 0xdf20 },
2438 { 0x01, 0xff95 },
2439 { 0x00, 0xba00 },
2440 { 0x04, 0xa800 },
2441 { 0x04, 0xf000 },
2442 { 0x03, 0xdf01 },
2443 { 0x02, 0xdf20 },
2444 { 0x01, 0x101a },
2445 { 0x00, 0xa0ff },
2446 { 0x04, 0xf800 },
2447 { 0x04, 0x0000 },
2448 { 0x1f, 0x0000 },
2449
2450 { 0x1f, 0x0001 },
2451 { 0x10, 0xf41b },
2452 { 0x14, 0xfb54 },
2453 { 0x18, 0xf5c7 },
2454 { 0x1f, 0x0000 },
2455
2456 { 0x1f, 0x0001 },
2457 { 0x17, 0x0cc0 },
2458 { 0x1f, 0x0000 }
2459 };
2460
2461 rtl_writephy_batch(tp, phy_reg_init);
2462
2463 rtl8169scd_hw_phy_config_quirk(tp);
2464 }
2465
2466 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2467 {
2468 static const struct phy_reg phy_reg_init[] = {
2469 { 0x1f, 0x0001 },
2470 { 0x04, 0x0000 },
2471 { 0x03, 0x00a1 },
2472 { 0x02, 0x0008 },
2473 { 0x01, 0x0120 },
2474 { 0x00, 0x1000 },
2475 { 0x04, 0x0800 },
2476 { 0x04, 0x9000 },
2477 { 0x03, 0x802f },
2478 { 0x02, 0x4f02 },
2479 { 0x01, 0x0409 },
2480 { 0x00, 0xf099 },
2481 { 0x04, 0x9800 },
2482 { 0x04, 0xa000 },
2483 { 0x03, 0xdf01 },
2484 { 0x02, 0xdf20 },
2485 { 0x01, 0xff95 },
2486 { 0x00, 0xba00 },
2487 { 0x04, 0xa800 },
2488 { 0x04, 0xf000 },
2489 { 0x03, 0xdf01 },
2490 { 0x02, 0xdf20 },
2491 { 0x01, 0x101a },
2492 { 0x00, 0xa0ff },
2493 { 0x04, 0xf800 },
2494 { 0x04, 0x0000 },
2495 { 0x1f, 0x0000 },
2496
2497 { 0x1f, 0x0001 },
2498 { 0x0b, 0x8480 },
2499 { 0x1f, 0x0000 },
2500
2501 { 0x1f, 0x0001 },
2502 { 0x18, 0x67c7 },
2503 { 0x04, 0x2000 },
2504 { 0x03, 0x002f },
2505 { 0x02, 0x4360 },
2506 { 0x01, 0x0109 },
2507 { 0x00, 0x3022 },
2508 { 0x04, 0x2800 },
2509 { 0x1f, 0x0000 },
2510
2511 { 0x1f, 0x0001 },
2512 { 0x17, 0x0cc0 },
2513 { 0x1f, 0x0000 }
2514 };
2515
2516 rtl_writephy_batch(tp, phy_reg_init);
2517 }
2518
2519 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2520 {
2521 static const struct phy_reg phy_reg_init[] = {
2522 { 0x10, 0xf41b },
2523 { 0x1f, 0x0000 }
2524 };
2525
2526 rtl_writephy(tp, 0x1f, 0x0001);
2527 rtl_patchphy(tp, 0x16, 1 << 0);
2528
2529 rtl_writephy_batch(tp, phy_reg_init);
2530 }
2531
2532 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2533 {
2534 static const struct phy_reg phy_reg_init[] = {
2535 { 0x1f, 0x0001 },
2536 { 0x10, 0xf41b },
2537 { 0x1f, 0x0000 }
2538 };
2539
2540 rtl_writephy_batch(tp, phy_reg_init);
2541 }
2542
2543 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2544 {
2545 static const struct phy_reg phy_reg_init[] = {
2546 { 0x1f, 0x0000 },
2547 { 0x1d, 0x0f00 },
2548 { 0x1f, 0x0002 },
2549 { 0x0c, 0x1ec8 },
2550 { 0x1f, 0x0000 }
2551 };
2552
2553 rtl_writephy_batch(tp, phy_reg_init);
2554 }
2555
2556 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2557 {
2558 static const struct phy_reg phy_reg_init[] = {
2559 { 0x1f, 0x0001 },
2560 { 0x1d, 0x3d98 },
2561 { 0x1f, 0x0000 }
2562 };
2563
2564 rtl_writephy(tp, 0x1f, 0x0000);
2565 rtl_patchphy(tp, 0x14, 1 << 5);
2566 rtl_patchphy(tp, 0x0d, 1 << 5);
2567
2568 rtl_writephy_batch(tp, phy_reg_init);
2569 }
2570
2571 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2572 {
2573 static const struct phy_reg phy_reg_init[] = {
2574 { 0x1f, 0x0001 },
2575 { 0x12, 0x2300 },
2576 { 0x1f, 0x0002 },
2577 { 0x00, 0x88d4 },
2578 { 0x01, 0x82b1 },
2579 { 0x03, 0x7002 },
2580 { 0x08, 0x9e30 },
2581 { 0x09, 0x01f0 },
2582 { 0x0a, 0x5500 },
2583 { 0x0c, 0x00c8 },
2584 { 0x1f, 0x0003 },
2585 { 0x12, 0xc096 },
2586 { 0x16, 0x000a },
2587 { 0x1f, 0x0000 },
2588 { 0x1f, 0x0000 },
2589 { 0x09, 0x2000 },
2590 { 0x09, 0x0000 }
2591 };
2592
2593 rtl_writephy_batch(tp, phy_reg_init);
2594
2595 rtl_patchphy(tp, 0x14, 1 << 5);
2596 rtl_patchphy(tp, 0x0d, 1 << 5);
2597 rtl_writephy(tp, 0x1f, 0x0000);
2598 }
2599
2600 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2601 {
2602 static const struct phy_reg phy_reg_init[] = {
2603 { 0x1f, 0x0001 },
2604 { 0x12, 0x2300 },
2605 { 0x03, 0x802f },
2606 { 0x02, 0x4f02 },
2607 { 0x01, 0x0409 },
2608 { 0x00, 0xf099 },
2609 { 0x04, 0x9800 },
2610 { 0x04, 0x9000 },
2611 { 0x1d, 0x3d98 },
2612 { 0x1f, 0x0002 },
2613 { 0x0c, 0x7eb8 },
2614 { 0x06, 0x0761 },
2615 { 0x1f, 0x0003 },
2616 { 0x16, 0x0f0a },
2617 { 0x1f, 0x0000 }
2618 };
2619
2620 rtl_writephy_batch(tp, phy_reg_init);
2621
2622 rtl_patchphy(tp, 0x16, 1 << 0);
2623 rtl_patchphy(tp, 0x14, 1 << 5);
2624 rtl_patchphy(tp, 0x0d, 1 << 5);
2625 rtl_writephy(tp, 0x1f, 0x0000);
2626 }
2627
2628 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2629 {
2630 static const struct phy_reg phy_reg_init[] = {
2631 { 0x1f, 0x0001 },
2632 { 0x12, 0x2300 },
2633 { 0x1d, 0x3d98 },
2634 { 0x1f, 0x0002 },
2635 { 0x0c, 0x7eb8 },
2636 { 0x06, 0x5461 },
2637 { 0x1f, 0x0003 },
2638 { 0x16, 0x0f0a },
2639 { 0x1f, 0x0000 }
2640 };
2641
2642 rtl_writephy_batch(tp, phy_reg_init);
2643
2644 rtl_patchphy(tp, 0x16, 1 << 0);
2645 rtl_patchphy(tp, 0x14, 1 << 5);
2646 rtl_patchphy(tp, 0x0d, 1 << 5);
2647 rtl_writephy(tp, 0x1f, 0x0000);
2648 }
2649
2650 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2651 {
2652 rtl8168c_3_hw_phy_config(tp);
2653 }
2654
2655 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
2656 /* Channel Estimation */
2657 { 0x1f, 0x0001 },
2658 { 0x06, 0x4064 },
2659 { 0x07, 0x2863 },
2660 { 0x08, 0x059c },
2661 { 0x09, 0x26b4 },
2662 { 0x0a, 0x6a19 },
2663 { 0x0b, 0xdcc8 },
2664 { 0x10, 0xf06d },
2665 { 0x14, 0x7f68 },
2666 { 0x18, 0x7fd9 },
2667 { 0x1c, 0xf0ff },
2668 { 0x1d, 0x3d9c },
2669 { 0x1f, 0x0003 },
2670 { 0x12, 0xf49f },
2671 { 0x13, 0x070b },
2672 { 0x1a, 0x05ad },
2673 { 0x14, 0x94c0 },
2674
2675 /*
2676 * Tx Error Issue
2677 * Enhance line driver power
2678 */
2679 { 0x1f, 0x0002 },
2680 { 0x06, 0x5561 },
2681 { 0x1f, 0x0005 },
2682 { 0x05, 0x8332 },
2683 { 0x06, 0x5561 },
2684
2685 /*
2686 * Can not link to 1Gbps with bad cable
2687 * Decrease SNR threshold form 21.07dB to 19.04dB
2688 */
2689 { 0x1f, 0x0001 },
2690 { 0x17, 0x0cc0 },
2691
2692 { 0x1f, 0x0000 },
2693 { 0x0d, 0xf880 }
2694 };
2695
2696 static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = {
2697 { 0x1f, 0x0002 },
2698 { 0x05, 0x669a },
2699 { 0x1f, 0x0005 },
2700 { 0x05, 0x8330 },
2701 { 0x06, 0x669a },
2702 { 0x1f, 0x0002 }
2703 };
2704
2705 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2706 {
2707 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2708
2709 /*
2710 * Rx Error Issue
2711 * Fine Tune Switching regulator parameter
2712 */
2713 rtl_writephy(tp, 0x1f, 0x0002);
2714 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2715 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2716
2717 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2718 int val;
2719
2720 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2721
2722 val = rtl_readphy(tp, 0x0d);
2723
2724 if ((val & 0x00ff) != 0x006c) {
2725 static const u32 set[] = {
2726 0x0065, 0x0066, 0x0067, 0x0068,
2727 0x0069, 0x006a, 0x006b, 0x006c
2728 };
2729 int i;
2730
2731 rtl_writephy(tp, 0x1f, 0x0002);
2732
2733 val &= 0xff00;
2734 for (i = 0; i < ARRAY_SIZE(set); i++)
2735 rtl_writephy(tp, 0x0d, val | set[i]);
2736 }
2737 } else {
2738 static const struct phy_reg phy_reg_init[] = {
2739 { 0x1f, 0x0002 },
2740 { 0x05, 0x6662 },
2741 { 0x1f, 0x0005 },
2742 { 0x05, 0x8330 },
2743 { 0x06, 0x6662 }
2744 };
2745
2746 rtl_writephy_batch(tp, phy_reg_init);
2747 }
2748
2749 /* RSET couple improve */
2750 rtl_writephy(tp, 0x1f, 0x0002);
2751 rtl_patchphy(tp, 0x0d, 0x0300);
2752 rtl_patchphy(tp, 0x0f, 0x0010);
2753
2754 /* Fine tune PLL performance */
2755 rtl_writephy(tp, 0x1f, 0x0002);
2756 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2757 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2758
2759 rtl_writephy(tp, 0x1f, 0x0005);
2760 rtl_writephy(tp, 0x05, 0x001b);
2761
2762 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2763
2764 rtl_writephy(tp, 0x1f, 0x0000);
2765 }
2766
2767 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2768 {
2769 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2770
2771 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2772 int val;
2773
2774 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2775
2776 val = rtl_readphy(tp, 0x0d);
2777 if ((val & 0x00ff) != 0x006c) {
2778 static const u32 set[] = {
2779 0x0065, 0x0066, 0x0067, 0x0068,
2780 0x0069, 0x006a, 0x006b, 0x006c
2781 };
2782 int i;
2783
2784 rtl_writephy(tp, 0x1f, 0x0002);
2785
2786 val &= 0xff00;
2787 for (i = 0; i < ARRAY_SIZE(set); i++)
2788 rtl_writephy(tp, 0x0d, val | set[i]);
2789 }
2790 } else {
2791 static const struct phy_reg phy_reg_init[] = {
2792 { 0x1f, 0x0002 },
2793 { 0x05, 0x2642 },
2794 { 0x1f, 0x0005 },
2795 { 0x05, 0x8330 },
2796 { 0x06, 0x2642 }
2797 };
2798
2799 rtl_writephy_batch(tp, phy_reg_init);
2800 }
2801
2802 /* Fine tune PLL performance */
2803 rtl_writephy(tp, 0x1f, 0x0002);
2804 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2805 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2806
2807 /* Switching regulator Slew rate */
2808 rtl_writephy(tp, 0x1f, 0x0002);
2809 rtl_patchphy(tp, 0x0f, 0x0017);
2810
2811 rtl_writephy(tp, 0x1f, 0x0005);
2812 rtl_writephy(tp, 0x05, 0x001b);
2813
2814 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2815
2816 rtl_writephy(tp, 0x1f, 0x0000);
2817 }
2818
2819 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2820 {
2821 static const struct phy_reg phy_reg_init[] = {
2822 { 0x1f, 0x0002 },
2823 { 0x10, 0x0008 },
2824 { 0x0d, 0x006c },
2825
2826 { 0x1f, 0x0000 },
2827 { 0x0d, 0xf880 },
2828
2829 { 0x1f, 0x0001 },
2830 { 0x17, 0x0cc0 },
2831
2832 { 0x1f, 0x0001 },
2833 { 0x0b, 0xa4d8 },
2834 { 0x09, 0x281c },
2835 { 0x07, 0x2883 },
2836 { 0x0a, 0x6b35 },
2837 { 0x1d, 0x3da4 },
2838 { 0x1c, 0xeffd },
2839 { 0x14, 0x7f52 },
2840 { 0x18, 0x7fc6 },
2841 { 0x08, 0x0601 },
2842 { 0x06, 0x4063 },
2843 { 0x10, 0xf074 },
2844 { 0x1f, 0x0003 },
2845 { 0x13, 0x0789 },
2846 { 0x12, 0xf4bd },
2847 { 0x1a, 0x04fd },
2848 { 0x14, 0x84b0 },
2849 { 0x1f, 0x0000 },
2850 { 0x00, 0x9200 },
2851
2852 { 0x1f, 0x0005 },
2853 { 0x01, 0x0340 },
2854 { 0x1f, 0x0001 },
2855 { 0x04, 0x4000 },
2856 { 0x03, 0x1d21 },
2857 { 0x02, 0x0c32 },
2858 { 0x01, 0x0200 },
2859 { 0x00, 0x5554 },
2860 { 0x04, 0x4800 },
2861 { 0x04, 0x4000 },
2862 { 0x04, 0xf000 },
2863 { 0x03, 0xdf01 },
2864 { 0x02, 0xdf20 },
2865 { 0x01, 0x101a },
2866 { 0x00, 0xa0ff },
2867 { 0x04, 0xf800 },
2868 { 0x04, 0xf000 },
2869 { 0x1f, 0x0000 },
2870
2871 { 0x1f, 0x0007 },
2872 { 0x1e, 0x0023 },
2873 { 0x16, 0x0000 },
2874 { 0x1f, 0x0000 }
2875 };
2876
2877 rtl_writephy_batch(tp, phy_reg_init);
2878 }
2879
2880 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2881 {
2882 static const struct phy_reg phy_reg_init[] = {
2883 { 0x1f, 0x0001 },
2884 { 0x17, 0x0cc0 },
2885
2886 { 0x1f, 0x0007 },
2887 { 0x1e, 0x002d },
2888 { 0x18, 0x0040 },
2889 { 0x1f, 0x0000 }
2890 };
2891
2892 rtl_writephy_batch(tp, phy_reg_init);
2893 rtl_patchphy(tp, 0x0d, 1 << 5);
2894 }
2895
2896 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2897 {
2898 static const struct phy_reg phy_reg_init[] = {
2899 /* Enable Delay cap */
2900 { 0x1f, 0x0005 },
2901 { 0x05, 0x8b80 },
2902 { 0x06, 0xc896 },
2903 { 0x1f, 0x0000 },
2904
2905 /* Channel estimation fine tune */
2906 { 0x1f, 0x0001 },
2907 { 0x0b, 0x6c20 },
2908 { 0x07, 0x2872 },
2909 { 0x1c, 0xefff },
2910 { 0x1f, 0x0003 },
2911 { 0x14, 0x6420 },
2912 { 0x1f, 0x0000 },
2913
2914 /* Update PFM & 10M TX idle timer */
2915 { 0x1f, 0x0007 },
2916 { 0x1e, 0x002f },
2917 { 0x15, 0x1919 },
2918 { 0x1f, 0x0000 },
2919
2920 { 0x1f, 0x0007 },
2921 { 0x1e, 0x00ac },
2922 { 0x18, 0x0006 },
2923 { 0x1f, 0x0000 }
2924 };
2925
2926 rtl_apply_firmware(tp);
2927
2928 rtl_writephy_batch(tp, phy_reg_init);
2929
2930 /* DCO enable for 10M IDLE Power */
2931 rtl_writephy(tp, 0x1f, 0x0007);
2932 rtl_writephy(tp, 0x1e, 0x0023);
2933 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
2934 rtl_writephy(tp, 0x1f, 0x0000);
2935
2936 /* For impedance matching */
2937 rtl_writephy(tp, 0x1f, 0x0002);
2938 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
2939 rtl_writephy(tp, 0x1f, 0x0000);
2940
2941 /* PHY auto speed down */
2942 rtl_writephy(tp, 0x1f, 0x0007);
2943 rtl_writephy(tp, 0x1e, 0x002d);
2944 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
2945 rtl_writephy(tp, 0x1f, 0x0000);
2946 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
2947
2948 rtl_writephy(tp, 0x1f, 0x0005);
2949 rtl_writephy(tp, 0x05, 0x8b86);
2950 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
2951 rtl_writephy(tp, 0x1f, 0x0000);
2952
2953 rtl_writephy(tp, 0x1f, 0x0005);
2954 rtl_writephy(tp, 0x05, 0x8b85);
2955 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
2956 rtl_writephy(tp, 0x1f, 0x0007);
2957 rtl_writephy(tp, 0x1e, 0x0020);
2958 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
2959 rtl_writephy(tp, 0x1f, 0x0006);
2960 rtl_writephy(tp, 0x00, 0x5a00);
2961 rtl_writephy(tp, 0x1f, 0x0000);
2962 rtl_writephy(tp, 0x0d, 0x0007);
2963 rtl_writephy(tp, 0x0e, 0x003c);
2964 rtl_writephy(tp, 0x0d, 0x4007);
2965 rtl_writephy(tp, 0x0e, 0x0000);
2966 rtl_writephy(tp, 0x0d, 0x0000);
2967 }
2968
2969 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
2970 {
2971 const u16 w[] = {
2972 addr[0] | (addr[1] << 8),
2973 addr[2] | (addr[3] << 8),
2974 addr[4] | (addr[5] << 8)
2975 };
2976
2977 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
2978 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
2979 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
2980 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
2981 }
2982
2983 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2984 {
2985 static const struct phy_reg phy_reg_init[] = {
2986 /* Enable Delay cap */
2987 { 0x1f, 0x0004 },
2988 { 0x1f, 0x0007 },
2989 { 0x1e, 0x00ac },
2990 { 0x18, 0x0006 },
2991 { 0x1f, 0x0002 },
2992 { 0x1f, 0x0000 },
2993 { 0x1f, 0x0000 },
2994
2995 /* Channel estimation fine tune */
2996 { 0x1f, 0x0003 },
2997 { 0x09, 0xa20f },
2998 { 0x1f, 0x0000 },
2999 { 0x1f, 0x0000 },
3000
3001 /* Green Setting */
3002 { 0x1f, 0x0005 },
3003 { 0x05, 0x8b5b },
3004 { 0x06, 0x9222 },
3005 { 0x05, 0x8b6d },
3006 { 0x06, 0x8000 },
3007 { 0x05, 0x8b76 },
3008 { 0x06, 0x8000 },
3009 { 0x1f, 0x0000 }
3010 };
3011
3012 rtl_apply_firmware(tp);
3013
3014 rtl_writephy_batch(tp, phy_reg_init);
3015
3016 /* For 4-corner performance improve */
3017 rtl_writephy(tp, 0x1f, 0x0005);
3018 rtl_writephy(tp, 0x05, 0x8b80);
3019 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3020 rtl_writephy(tp, 0x1f, 0x0000);
3021
3022 /* PHY auto speed down */
3023 rtl_writephy(tp, 0x1f, 0x0004);
3024 rtl_writephy(tp, 0x1f, 0x0007);
3025 rtl_writephy(tp, 0x1e, 0x002d);
3026 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3027 rtl_writephy(tp, 0x1f, 0x0002);
3028 rtl_writephy(tp, 0x1f, 0x0000);
3029 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3030
3031 /* improve 10M EEE waveform */
3032 rtl_writephy(tp, 0x1f, 0x0005);
3033 rtl_writephy(tp, 0x05, 0x8b86);
3034 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3035 rtl_writephy(tp, 0x1f, 0x0000);
3036
3037 /* Improve 2-pair detection performance */
3038 rtl_writephy(tp, 0x1f, 0x0005);
3039 rtl_writephy(tp, 0x05, 0x8b85);
3040 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3041 rtl_writephy(tp, 0x1f, 0x0000);
3042
3043 rtl8168f_config_eee_phy(tp);
3044 rtl_enable_eee(tp);
3045
3046 /* Green feature */
3047 rtl_writephy(tp, 0x1f, 0x0003);
3048 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3049 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3050 rtl_writephy(tp, 0x1f, 0x0000);
3051 rtl_writephy(tp, 0x1f, 0x0005);
3052 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3053 rtl_writephy(tp, 0x1f, 0x0000);
3054
3055 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3056 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3057 }
3058
3059 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3060 {
3061 /* For 4-corner performance improve */
3062 rtl_writephy(tp, 0x1f, 0x0005);
3063 rtl_writephy(tp, 0x05, 0x8b80);
3064 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3065 rtl_writephy(tp, 0x1f, 0x0000);
3066
3067 /* PHY auto speed down */
3068 rtl_writephy(tp, 0x1f, 0x0007);
3069 rtl_writephy(tp, 0x1e, 0x002d);
3070 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3071 rtl_writephy(tp, 0x1f, 0x0000);
3072 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3073
3074 /* Improve 10M EEE waveform */
3075 rtl_writephy(tp, 0x1f, 0x0005);
3076 rtl_writephy(tp, 0x05, 0x8b86);
3077 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3078 rtl_writephy(tp, 0x1f, 0x0000);
3079
3080 rtl8168f_config_eee_phy(tp);
3081 rtl_enable_eee(tp);
3082 }
3083
3084 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3085 {
3086 static const struct phy_reg phy_reg_init[] = {
3087 /* Channel estimation fine tune */
3088 { 0x1f, 0x0003 },
3089 { 0x09, 0xa20f },
3090 { 0x1f, 0x0000 },
3091
3092 /* Modify green table for giga & fnet */
3093 { 0x1f, 0x0005 },
3094 { 0x05, 0x8b55 },
3095 { 0x06, 0x0000 },
3096 { 0x05, 0x8b5e },
3097 { 0x06, 0x0000 },
3098 { 0x05, 0x8b67 },
3099 { 0x06, 0x0000 },
3100 { 0x05, 0x8b70 },
3101 { 0x06, 0x0000 },
3102 { 0x1f, 0x0000 },
3103 { 0x1f, 0x0007 },
3104 { 0x1e, 0x0078 },
3105 { 0x17, 0x0000 },
3106 { 0x19, 0x00fb },
3107 { 0x1f, 0x0000 },
3108
3109 /* Modify green table for 10M */
3110 { 0x1f, 0x0005 },
3111 { 0x05, 0x8b79 },
3112 { 0x06, 0xaa00 },
3113 { 0x1f, 0x0000 },
3114
3115 /* Disable hiimpedance detection (RTCT) */
3116 { 0x1f, 0x0003 },
3117 { 0x01, 0x328a },
3118 { 0x1f, 0x0000 }
3119 };
3120
3121 rtl_apply_firmware(tp);
3122
3123 rtl_writephy_batch(tp, phy_reg_init);
3124
3125 rtl8168f_hw_phy_config(tp);
3126
3127 /* Improve 2-pair detection performance */
3128 rtl_writephy(tp, 0x1f, 0x0005);
3129 rtl_writephy(tp, 0x05, 0x8b85);
3130 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3131 rtl_writephy(tp, 0x1f, 0x0000);
3132 }
3133
3134 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3135 {
3136 rtl_apply_firmware(tp);
3137
3138 rtl8168f_hw_phy_config(tp);
3139 }
3140
3141 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3142 {
3143 static const struct phy_reg phy_reg_init[] = {
3144 /* Channel estimation fine tune */
3145 { 0x1f, 0x0003 },
3146 { 0x09, 0xa20f },
3147 { 0x1f, 0x0000 },
3148
3149 /* Modify green table for giga & fnet */
3150 { 0x1f, 0x0005 },
3151 { 0x05, 0x8b55 },
3152 { 0x06, 0x0000 },
3153 { 0x05, 0x8b5e },
3154 { 0x06, 0x0000 },
3155 { 0x05, 0x8b67 },
3156 { 0x06, 0x0000 },
3157 { 0x05, 0x8b70 },
3158 { 0x06, 0x0000 },
3159 { 0x1f, 0x0000 },
3160 { 0x1f, 0x0007 },
3161 { 0x1e, 0x0078 },
3162 { 0x17, 0x0000 },
3163 { 0x19, 0x00aa },
3164 { 0x1f, 0x0000 },
3165
3166 /* Modify green table for 10M */
3167 { 0x1f, 0x0005 },
3168 { 0x05, 0x8b79 },
3169 { 0x06, 0xaa00 },
3170 { 0x1f, 0x0000 },
3171
3172 /* Disable hiimpedance detection (RTCT) */
3173 { 0x1f, 0x0003 },
3174 { 0x01, 0x328a },
3175 { 0x1f, 0x0000 }
3176 };
3177
3178
3179 rtl_apply_firmware(tp);
3180
3181 rtl8168f_hw_phy_config(tp);
3182
3183 /* Improve 2-pair detection performance */
3184 rtl_writephy(tp, 0x1f, 0x0005);
3185 rtl_writephy(tp, 0x05, 0x8b85);
3186 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3187 rtl_writephy(tp, 0x1f, 0x0000);
3188
3189 rtl_writephy_batch(tp, phy_reg_init);
3190
3191 /* Modify green table for giga */
3192 rtl_writephy(tp, 0x1f, 0x0005);
3193 rtl_writephy(tp, 0x05, 0x8b54);
3194 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3195 rtl_writephy(tp, 0x05, 0x8b5d);
3196 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3197 rtl_writephy(tp, 0x05, 0x8a7c);
3198 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3199 rtl_writephy(tp, 0x05, 0x8a7f);
3200 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3201 rtl_writephy(tp, 0x05, 0x8a82);
3202 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3203 rtl_writephy(tp, 0x05, 0x8a85);
3204 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3205 rtl_writephy(tp, 0x05, 0x8a88);
3206 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3207 rtl_writephy(tp, 0x1f, 0x0000);
3208
3209 /* uc same-seed solution */
3210 rtl_writephy(tp, 0x1f, 0x0005);
3211 rtl_writephy(tp, 0x05, 0x8b85);
3212 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3213 rtl_writephy(tp, 0x1f, 0x0000);
3214
3215 /* Green feature */
3216 rtl_writephy(tp, 0x1f, 0x0003);
3217 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3218 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3219 rtl_writephy(tp, 0x1f, 0x0000);
3220 }
3221
3222 static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3223 {
3224 phy_modify_paged(tp->phydev, 0x0a43, 0x10, BIT(2), 0);
3225 }
3226
3227 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3228 {
3229 struct phy_device *phydev = tp->phydev;
3230
3231 phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0);
3232 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6));
3233 phy_write(phydev, 0x1f, 0x0a43);
3234 phy_write(phydev, 0x13, 0x8084);
3235 phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13));
3236 phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0));
3237
3238 phy_write(phydev, 0x1f, 0x0000);
3239 }
3240
3241 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3242 {
3243 int ret;
3244
3245 rtl_apply_firmware(tp);
3246
3247 ret = phy_read_paged(tp->phydev, 0x0a46, 0x10);
3248 if (ret & BIT(8))
3249 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, BIT(15), 0);
3250 else
3251 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, 0, BIT(15));
3252
3253 ret = phy_read_paged(tp->phydev, 0x0a46, 0x13);
3254 if (ret & BIT(8))
3255 phy_modify_paged(tp->phydev, 0x0c41, 0x12, 0, BIT(1));
3256 else
3257 phy_modify_paged(tp->phydev, 0x0c41, 0x12, BIT(1), 0);
3258
3259 /* Enable PHY auto speed down */
3260 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3261
3262 rtl8168g_phy_adjust_10m_aldps(tp);
3263
3264 /* EEE auto-fallback function */
3265 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3266
3267 /* Enable UC LPF tune function */
3268 rtl_writephy(tp, 0x1f, 0x0a43);
3269 rtl_writephy(tp, 0x13, 0x8012);
3270 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3271
3272 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3273
3274 /* Improve SWR Efficiency */
3275 rtl_writephy(tp, 0x1f, 0x0bcd);
3276 rtl_writephy(tp, 0x14, 0x5065);
3277 rtl_writephy(tp, 0x14, 0xd065);
3278 rtl_writephy(tp, 0x1f, 0x0bc8);
3279 rtl_writephy(tp, 0x11, 0x5655);
3280 rtl_writephy(tp, 0x1f, 0x0bcd);
3281 rtl_writephy(tp, 0x14, 0x1065);
3282 rtl_writephy(tp, 0x14, 0x9065);
3283 rtl_writephy(tp, 0x14, 0x1065);
3284 rtl_writephy(tp, 0x1f, 0x0000);
3285
3286 rtl8168g_disable_aldps(tp);
3287 rtl8168g_config_eee_phy(tp);
3288 rtl_enable_eee(tp);
3289 }
3290
3291 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3292 {
3293 rtl_apply_firmware(tp);
3294 rtl8168g_config_eee_phy(tp);
3295 rtl_enable_eee(tp);
3296 }
3297
3298 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3299 {
3300 u16 dout_tapbin;
3301 u32 data;
3302
3303 rtl_apply_firmware(tp);
3304
3305 /* CHN EST parameters adjust - giga master */
3306 rtl_writephy(tp, 0x1f, 0x0a43);
3307 rtl_writephy(tp, 0x13, 0x809b);
3308 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3309 rtl_writephy(tp, 0x13, 0x80a2);
3310 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3311 rtl_writephy(tp, 0x13, 0x80a4);
3312 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3313 rtl_writephy(tp, 0x13, 0x809c);
3314 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3315 rtl_writephy(tp, 0x1f, 0x0000);
3316
3317 /* CHN EST parameters adjust - giga slave */
3318 rtl_writephy(tp, 0x1f, 0x0a43);
3319 rtl_writephy(tp, 0x13, 0x80ad);
3320 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3321 rtl_writephy(tp, 0x13, 0x80b4);
3322 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3323 rtl_writephy(tp, 0x13, 0x80ac);
3324 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3325 rtl_writephy(tp, 0x1f, 0x0000);
3326
3327 /* CHN EST parameters adjust - fnet */
3328 rtl_writephy(tp, 0x1f, 0x0a43);
3329 rtl_writephy(tp, 0x13, 0x808e);
3330 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3331 rtl_writephy(tp, 0x13, 0x8090);
3332 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3333 rtl_writephy(tp, 0x13, 0x8092);
3334 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3335 rtl_writephy(tp, 0x1f, 0x0000);
3336
3337 /* enable R-tune & PGA-retune function */
3338 dout_tapbin = 0;
3339 rtl_writephy(tp, 0x1f, 0x0a46);
3340 data = rtl_readphy(tp, 0x13);
3341 data &= 3;
3342 data <<= 2;
3343 dout_tapbin |= data;
3344 data = rtl_readphy(tp, 0x12);
3345 data &= 0xc000;
3346 data >>= 14;
3347 dout_tapbin |= data;
3348 dout_tapbin = ~(dout_tapbin^0x08);
3349 dout_tapbin <<= 12;
3350 dout_tapbin &= 0xf000;
3351 rtl_writephy(tp, 0x1f, 0x0a43);
3352 rtl_writephy(tp, 0x13, 0x827a);
3353 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3354 rtl_writephy(tp, 0x13, 0x827b);
3355 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3356 rtl_writephy(tp, 0x13, 0x827c);
3357 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3358 rtl_writephy(tp, 0x13, 0x827d);
3359 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3360
3361 rtl_writephy(tp, 0x1f, 0x0a43);
3362 rtl_writephy(tp, 0x13, 0x0811);
3363 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3364 rtl_writephy(tp, 0x1f, 0x0a42);
3365 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3366 rtl_writephy(tp, 0x1f, 0x0000);
3367
3368 /* enable GPHY 10M */
3369 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3370
3371 /* SAR ADC performance */
3372 phy_modify_paged(tp->phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14));
3373
3374 rtl_writephy(tp, 0x1f, 0x0a43);
3375 rtl_writephy(tp, 0x13, 0x803f);
3376 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3377 rtl_writephy(tp, 0x13, 0x8047);
3378 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3379 rtl_writephy(tp, 0x13, 0x804f);
3380 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3381 rtl_writephy(tp, 0x13, 0x8057);
3382 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3383 rtl_writephy(tp, 0x13, 0x805f);
3384 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3385 rtl_writephy(tp, 0x13, 0x8067);
3386 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3387 rtl_writephy(tp, 0x13, 0x806f);
3388 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3389 rtl_writephy(tp, 0x1f, 0x0000);
3390
3391 /* disable phy pfm mode */
3392 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3393
3394 rtl8168g_disable_aldps(tp);
3395 rtl8168g_config_eee_phy(tp);
3396 rtl_enable_eee(tp);
3397 }
3398
3399 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3400 {
3401 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3402 u16 rlen;
3403 u32 data;
3404
3405 rtl_apply_firmware(tp);
3406
3407 /* CHIN EST parameter update */
3408 rtl_writephy(tp, 0x1f, 0x0a43);
3409 rtl_writephy(tp, 0x13, 0x808a);
3410 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3411 rtl_writephy(tp, 0x1f, 0x0000);
3412
3413 /* enable R-tune & PGA-retune function */
3414 rtl_writephy(tp, 0x1f, 0x0a43);
3415 rtl_writephy(tp, 0x13, 0x0811);
3416 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3417 rtl_writephy(tp, 0x1f, 0x0a42);
3418 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3419 rtl_writephy(tp, 0x1f, 0x0000);
3420
3421 /* enable GPHY 10M */
3422 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3423
3424 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3425 data = r8168_mac_ocp_read(tp, 0xdd02);
3426 ioffset_p3 = ((data & 0x80)>>7);
3427 ioffset_p3 <<= 3;
3428
3429 data = r8168_mac_ocp_read(tp, 0xdd00);
3430 ioffset_p3 |= ((data & (0xe000))>>13);
3431 ioffset_p2 = ((data & (0x1e00))>>9);
3432 ioffset_p1 = ((data & (0x01e0))>>5);
3433 ioffset_p0 = ((data & 0x0010)>>4);
3434 ioffset_p0 <<= 3;
3435 ioffset_p0 |= (data & (0x07));
3436 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3437
3438 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3439 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3440 rtl_writephy(tp, 0x1f, 0x0bcf);
3441 rtl_writephy(tp, 0x16, data);
3442 rtl_writephy(tp, 0x1f, 0x0000);
3443 }
3444
3445 /* Modify rlen (TX LPF corner frequency) level */
3446 rtl_writephy(tp, 0x1f, 0x0bcd);
3447 data = rtl_readphy(tp, 0x16);
3448 data &= 0x000f;
3449 rlen = 0;
3450 if (data > 3)
3451 rlen = data - 3;
3452 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3453 rtl_writephy(tp, 0x17, data);
3454 rtl_writephy(tp, 0x1f, 0x0bcd);
3455 rtl_writephy(tp, 0x1f, 0x0000);
3456
3457 /* disable phy pfm mode */
3458 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3459
3460 rtl8168g_disable_aldps(tp);
3461 rtl8168g_config_eee_phy(tp);
3462 rtl_enable_eee(tp);
3463 }
3464
3465 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3466 {
3467 /* Enable PHY auto speed down */
3468 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3469
3470 rtl8168g_phy_adjust_10m_aldps(tp);
3471
3472 /* Enable EEE auto-fallback function */
3473 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3474
3475 /* Enable UC LPF tune function */
3476 rtl_writephy(tp, 0x1f, 0x0a43);
3477 rtl_writephy(tp, 0x13, 0x8012);
3478 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3479 rtl_writephy(tp, 0x1f, 0x0000);
3480
3481 /* set rg_sel_sdm_rate */
3482 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3483
3484 rtl8168g_disable_aldps(tp);
3485 rtl8168g_config_eee_phy(tp);
3486 rtl_enable_eee(tp);
3487 }
3488
3489 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3490 {
3491 rtl8168g_phy_adjust_10m_aldps(tp);
3492
3493 /* Enable UC LPF tune function */
3494 rtl_writephy(tp, 0x1f, 0x0a43);
3495 rtl_writephy(tp, 0x13, 0x8012);
3496 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3497 rtl_writephy(tp, 0x1f, 0x0000);
3498
3499 /* Set rg_sel_sdm_rate */
3500 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3501
3502 /* Channel estimation parameters */
3503 rtl_writephy(tp, 0x1f, 0x0a43);
3504 rtl_writephy(tp, 0x13, 0x80f3);
3505 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3506 rtl_writephy(tp, 0x13, 0x80f0);
3507 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3508 rtl_writephy(tp, 0x13, 0x80ef);
3509 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3510 rtl_writephy(tp, 0x13, 0x80f6);
3511 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3512 rtl_writephy(tp, 0x13, 0x80ec);
3513 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3514 rtl_writephy(tp, 0x13, 0x80ed);
3515 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3516 rtl_writephy(tp, 0x13, 0x80f2);
3517 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3518 rtl_writephy(tp, 0x13, 0x80f4);
3519 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3520 rtl_writephy(tp, 0x1f, 0x0a43);
3521 rtl_writephy(tp, 0x13, 0x8110);
3522 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3523 rtl_writephy(tp, 0x13, 0x810f);
3524 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3525 rtl_writephy(tp, 0x13, 0x8111);
3526 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3527 rtl_writephy(tp, 0x13, 0x8113);
3528 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3529 rtl_writephy(tp, 0x13, 0x8115);
3530 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3531 rtl_writephy(tp, 0x13, 0x810e);
3532 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3533 rtl_writephy(tp, 0x13, 0x810c);
3534 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3535 rtl_writephy(tp, 0x13, 0x810b);
3536 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3537 rtl_writephy(tp, 0x1f, 0x0a43);
3538 rtl_writephy(tp, 0x13, 0x80d1);
3539 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3540 rtl_writephy(tp, 0x13, 0x80cd);
3541 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3542 rtl_writephy(tp, 0x13, 0x80d3);
3543 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3544 rtl_writephy(tp, 0x13, 0x80d5);
3545 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3546 rtl_writephy(tp, 0x13, 0x80d7);
3547 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3548
3549 /* Force PWM-mode */
3550 rtl_writephy(tp, 0x1f, 0x0bcd);
3551 rtl_writephy(tp, 0x14, 0x5065);
3552 rtl_writephy(tp, 0x14, 0xd065);
3553 rtl_writephy(tp, 0x1f, 0x0bc8);
3554 rtl_writephy(tp, 0x12, 0x00ed);
3555 rtl_writephy(tp, 0x1f, 0x0bcd);
3556 rtl_writephy(tp, 0x14, 0x1065);
3557 rtl_writephy(tp, 0x14, 0x9065);
3558 rtl_writephy(tp, 0x14, 0x1065);
3559 rtl_writephy(tp, 0x1f, 0x0000);
3560
3561 rtl8168g_disable_aldps(tp);
3562 rtl8168g_config_eee_phy(tp);
3563 rtl_enable_eee(tp);
3564 }
3565
3566 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3567 {
3568 static const struct phy_reg phy_reg_init[] = {
3569 { 0x1f, 0x0003 },
3570 { 0x08, 0x441d },
3571 { 0x01, 0x9100 },
3572 { 0x1f, 0x0000 }
3573 };
3574
3575 rtl_writephy(tp, 0x1f, 0x0000);
3576 rtl_patchphy(tp, 0x11, 1 << 12);
3577 rtl_patchphy(tp, 0x19, 1 << 13);
3578 rtl_patchphy(tp, 0x10, 1 << 15);
3579
3580 rtl_writephy_batch(tp, phy_reg_init);
3581 }
3582
3583 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3584 {
3585 static const struct phy_reg phy_reg_init[] = {
3586 { 0x1f, 0x0005 },
3587 { 0x1a, 0x0000 },
3588 { 0x1f, 0x0000 },
3589
3590 { 0x1f, 0x0004 },
3591 { 0x1c, 0x0000 },
3592 { 0x1f, 0x0000 },
3593
3594 { 0x1f, 0x0001 },
3595 { 0x15, 0x7701 },
3596 { 0x1f, 0x0000 }
3597 };
3598
3599 /* Disable ALDPS before ram code */
3600 rtl_writephy(tp, 0x1f, 0x0000);
3601 rtl_writephy(tp, 0x18, 0x0310);
3602 msleep(100);
3603
3604 rtl_apply_firmware(tp);
3605
3606 rtl_writephy_batch(tp, phy_reg_init);
3607 }
3608
3609 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3610 {
3611 /* Disable ALDPS before setting firmware */
3612 rtl_writephy(tp, 0x1f, 0x0000);
3613 rtl_writephy(tp, 0x18, 0x0310);
3614 msleep(20);
3615
3616 rtl_apply_firmware(tp);
3617
3618 /* EEE setting */
3619 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3620 rtl_writephy(tp, 0x1f, 0x0004);
3621 rtl_writephy(tp, 0x10, 0x401f);
3622 rtl_writephy(tp, 0x19, 0x7030);
3623 rtl_writephy(tp, 0x1f, 0x0000);
3624 }
3625
3626 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3627 {
3628 static const struct phy_reg phy_reg_init[] = {
3629 { 0x1f, 0x0004 },
3630 { 0x10, 0xc07f },
3631 { 0x19, 0x7030 },
3632 { 0x1f, 0x0000 }
3633 };
3634
3635 /* Disable ALDPS before ram code */
3636 rtl_writephy(tp, 0x1f, 0x0000);
3637 rtl_writephy(tp, 0x18, 0x0310);
3638 msleep(100);
3639
3640 rtl_apply_firmware(tp);
3641
3642 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3643 rtl_writephy_batch(tp, phy_reg_init);
3644
3645 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3646 }
3647
3648 static void rtl_hw_phy_config(struct net_device *dev)
3649 {
3650 static const rtl_generic_fct phy_configs[] = {
3651 /* PCI devices. */
3652 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
3653 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
3654 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
3655 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
3656 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
3657 /* PCI-E devices. */
3658 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
3659 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
3660 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
3661 [RTL_GIGA_MAC_VER_10] = NULL,
3662 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
3663 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config,
3664 [RTL_GIGA_MAC_VER_13] = NULL,
3665 [RTL_GIGA_MAC_VER_14] = NULL,
3666 [RTL_GIGA_MAC_VER_15] = NULL,
3667 [RTL_GIGA_MAC_VER_16] = NULL,
3668 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
3669 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
3670 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
3671 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
3672 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
3673 [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config,
3674 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
3675 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
3676 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
3677 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
3678 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config,
3679 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
3680 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
3681 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
3682 [RTL_GIGA_MAC_VER_31] = NULL,
3683 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
3684 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
3685 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
3686 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
3687 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
3688 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
3689 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
3690 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
3691 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
3692 [RTL_GIGA_MAC_VER_41] = NULL,
3693 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
3694 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
3695 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
3696 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config,
3697 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
3698 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config,
3699 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
3700 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config,
3701 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config,
3702 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
3703 };
3704 struct rtl8169_private *tp = netdev_priv(dev);
3705
3706 if (phy_configs[tp->mac_version])
3707 phy_configs[tp->mac_version](tp);
3708 }
3709
3710 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3711 {
3712 if (!test_and_set_bit(flag, tp->wk.flags))
3713 schedule_work(&tp->wk.work);
3714 }
3715
3716 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3717 {
3718 rtl_hw_phy_config(dev);
3719
3720 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3721 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3722 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3723 netif_dbg(tp, drv, dev,
3724 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3725 RTL_W8(tp, 0x82, 0x01);
3726 }
3727
3728 /* We may have called phy_speed_down before */
3729 phy_speed_up(tp->phydev);
3730
3731 genphy_soft_reset(tp->phydev);
3732 }
3733
3734 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3735 {
3736 rtl_lock_work(tp);
3737
3738 rtl_unlock_config_regs(tp);
3739
3740 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
3741 RTL_R32(tp, MAC4);
3742
3743 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3744 RTL_R32(tp, MAC0);
3745
3746 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3747 rtl_rar_exgmac_set(tp, addr);
3748
3749 rtl_lock_config_regs(tp);
3750
3751 rtl_unlock_work(tp);
3752 }
3753
3754 static int rtl_set_mac_address(struct net_device *dev, void *p)
3755 {
3756 struct rtl8169_private *tp = netdev_priv(dev);
3757 struct device *d = tp_to_dev(tp);
3758 int ret;
3759
3760 ret = eth_mac_addr(dev, p);
3761 if (ret)
3762 return ret;
3763
3764 pm_runtime_get_noresume(d);
3765
3766 if (pm_runtime_active(d))
3767 rtl_rar_set(tp, dev->dev_addr);
3768
3769 pm_runtime_put_noidle(d);
3770
3771 return 0;
3772 }
3773
3774 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3775 {
3776 struct rtl8169_private *tp = netdev_priv(dev);
3777
3778 if (!netif_running(dev))
3779 return -ENODEV;
3780
3781 return phy_mii_ioctl(tp->phydev, ifr, cmd);
3782 }
3783
3784 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3785 {
3786 switch (tp->mac_version) {
3787 case RTL_GIGA_MAC_VER_25:
3788 case RTL_GIGA_MAC_VER_26:
3789 case RTL_GIGA_MAC_VER_29:
3790 case RTL_GIGA_MAC_VER_30:
3791 case RTL_GIGA_MAC_VER_32:
3792 case RTL_GIGA_MAC_VER_33:
3793 case RTL_GIGA_MAC_VER_34:
3794 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
3795 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
3796 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3797 break;
3798 default:
3799 break;
3800 }
3801 }
3802
3803 static void rtl_pll_power_down(struct rtl8169_private *tp)
3804 {
3805 if (r8168_check_dash(tp))
3806 return;
3807
3808 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3809 tp->mac_version == RTL_GIGA_MAC_VER_33)
3810 rtl_ephy_write(tp, 0x19, 0xff64);
3811
3812 if (device_may_wakeup(tp_to_dev(tp))) {
3813 phy_speed_down(tp->phydev, false);
3814 rtl_wol_suspend_quirk(tp);
3815 return;
3816 }
3817
3818 switch (tp->mac_version) {
3819 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
3820 case RTL_GIGA_MAC_VER_37:
3821 case RTL_GIGA_MAC_VER_39:
3822 case RTL_GIGA_MAC_VER_43:
3823 case RTL_GIGA_MAC_VER_44:
3824 case RTL_GIGA_MAC_VER_45:
3825 case RTL_GIGA_MAC_VER_46:
3826 case RTL_GIGA_MAC_VER_47:
3827 case RTL_GIGA_MAC_VER_48:
3828 case RTL_GIGA_MAC_VER_50:
3829 case RTL_GIGA_MAC_VER_51:
3830 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
3831 break;
3832 case RTL_GIGA_MAC_VER_40:
3833 case RTL_GIGA_MAC_VER_41:
3834 case RTL_GIGA_MAC_VER_49:
3835 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
3836 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
3837 break;
3838 default:
3839 break;
3840 }
3841 }
3842
3843 static void rtl_pll_power_up(struct rtl8169_private *tp)
3844 {
3845 switch (tp->mac_version) {
3846 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
3847 case RTL_GIGA_MAC_VER_37:
3848 case RTL_GIGA_MAC_VER_39:
3849 case RTL_GIGA_MAC_VER_43:
3850 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
3851 break;
3852 case RTL_GIGA_MAC_VER_44:
3853 case RTL_GIGA_MAC_VER_45:
3854 case RTL_GIGA_MAC_VER_46:
3855 case RTL_GIGA_MAC_VER_47:
3856 case RTL_GIGA_MAC_VER_48:
3857 case RTL_GIGA_MAC_VER_50:
3858 case RTL_GIGA_MAC_VER_51:
3859 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
3860 break;
3861 case RTL_GIGA_MAC_VER_40:
3862 case RTL_GIGA_MAC_VER_41:
3863 case RTL_GIGA_MAC_VER_49:
3864 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
3865 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
3866 break;
3867 default:
3868 break;
3869 }
3870
3871 phy_resume(tp->phydev);
3872 /* give MAC/PHY some time to resume */
3873 msleep(20);
3874 }
3875
3876 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3877 {
3878 switch (tp->mac_version) {
3879 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
3880 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
3881 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3882 break;
3883 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
3884 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
3885 case RTL_GIGA_MAC_VER_38:
3886 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3887 break;
3888 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
3889 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
3890 break;
3891 default:
3892 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
3893 break;
3894 }
3895 }
3896
3897 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3898 {
3899 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
3900 }
3901
3902 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3903 {
3904 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3905 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
3906 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
3907 }
3908
3909 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3910 {
3911 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3912 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
3913 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
3914 }
3915
3916 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3917 {
3918 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3919 }
3920
3921 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3922 {
3923 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3924 }
3925
3926 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3927 {
3928 RTL_W8(tp, MaxTxPacketSize, 0x3f);
3929 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3930 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
3931 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
3932 }
3933
3934 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3935 {
3936 RTL_W8(tp, MaxTxPacketSize, 0x0c);
3937 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3938 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
3939 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
3940 }
3941
3942 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3943 {
3944 rtl_tx_performance_tweak(tp,
3945 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
3946 }
3947
3948 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3949 {
3950 rtl_tx_performance_tweak(tp,
3951 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
3952 }
3953
3954 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3955 {
3956 r8168b_0_hw_jumbo_enable(tp);
3957
3958 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
3959 }
3960
3961 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3962 {
3963 r8168b_0_hw_jumbo_disable(tp);
3964
3965 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
3966 }
3967
3968 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3969 {
3970 rtl_unlock_config_regs(tp);
3971 switch (tp->mac_version) {
3972 case RTL_GIGA_MAC_VER_11:
3973 r8168b_0_hw_jumbo_enable(tp);
3974 break;
3975 case RTL_GIGA_MAC_VER_12:
3976 case RTL_GIGA_MAC_VER_17:
3977 r8168b_1_hw_jumbo_enable(tp);
3978 break;
3979 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
3980 r8168c_hw_jumbo_enable(tp);
3981 break;
3982 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
3983 r8168dp_hw_jumbo_enable(tp);
3984 break;
3985 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
3986 r8168e_hw_jumbo_enable(tp);
3987 break;
3988 default:
3989 break;
3990 }
3991 rtl_lock_config_regs(tp);
3992 }
3993
3994 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3995 {
3996 rtl_unlock_config_regs(tp);
3997 switch (tp->mac_version) {
3998 case RTL_GIGA_MAC_VER_11:
3999 r8168b_0_hw_jumbo_disable(tp);
4000 break;
4001 case RTL_GIGA_MAC_VER_12:
4002 case RTL_GIGA_MAC_VER_17:
4003 r8168b_1_hw_jumbo_disable(tp);
4004 break;
4005 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
4006 r8168c_hw_jumbo_disable(tp);
4007 break;
4008 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
4009 r8168dp_hw_jumbo_disable(tp);
4010 break;
4011 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
4012 r8168e_hw_jumbo_disable(tp);
4013 break;
4014 default:
4015 break;
4016 }
4017 rtl_lock_config_regs(tp);
4018 }
4019
4020 DECLARE_RTL_COND(rtl_chipcmd_cond)
4021 {
4022 return RTL_R8(tp, ChipCmd) & CmdReset;
4023 }
4024
4025 static void rtl_hw_reset(struct rtl8169_private *tp)
4026 {
4027 RTL_W8(tp, ChipCmd, CmdReset);
4028
4029 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4030 }
4031
4032 static void rtl_request_firmware(struct rtl8169_private *tp)
4033 {
4034 struct rtl_fw *rtl_fw;
4035
4036 /* firmware loaded already or no firmware available */
4037 if (tp->rtl_fw || !tp->fw_name)
4038 return;
4039
4040 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4041 if (!rtl_fw) {
4042 netif_warn(tp, ifup, tp->dev, "Unable to load firmware, out of memory\n");
4043 return;
4044 }
4045
4046 rtl_fw->phy_write = rtl_writephy;
4047 rtl_fw->phy_read = rtl_readphy;
4048 rtl_fw->mac_mcu_write = mac_mcu_write;
4049 rtl_fw->mac_mcu_read = mac_mcu_read;
4050 rtl_fw->fw_name = tp->fw_name;
4051 rtl_fw->dev = tp_to_dev(tp);
4052
4053 if (rtl_fw_request_firmware(rtl_fw))
4054 kfree(rtl_fw);
4055 else
4056 tp->rtl_fw = rtl_fw;
4057 }
4058
4059 static void rtl_rx_close(struct rtl8169_private *tp)
4060 {
4061 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4062 }
4063
4064 DECLARE_RTL_COND(rtl_npq_cond)
4065 {
4066 return RTL_R8(tp, TxPoll) & NPQ;
4067 }
4068
4069 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4070 {
4071 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4072 }
4073
4074 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4075 {
4076 /* Disable interrupts */
4077 rtl8169_irq_mask_and_ack(tp);
4078
4079 rtl_rx_close(tp);
4080
4081 switch (tp->mac_version) {
4082 case RTL_GIGA_MAC_VER_27:
4083 case RTL_GIGA_MAC_VER_28:
4084 case RTL_GIGA_MAC_VER_31:
4085 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4086 break;
4087 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4088 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4089 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4090 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4091 break;
4092 default:
4093 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4094 udelay(100);
4095 break;
4096 }
4097
4098 rtl_hw_reset(tp);
4099 }
4100
4101 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4102 {
4103 u32 val = TX_DMA_BURST << TxDMAShift |
4104 InterFrameGap << TxInterFrameGapShift;
4105
4106 if (rtl_is_8168evl_up(tp))
4107 val |= TXCFG_AUTO_FIFO;
4108
4109 RTL_W32(tp, TxConfig, val);
4110 }
4111
4112 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4113 {
4114 /* Low hurts. Let's disable the filtering. */
4115 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4116 }
4117
4118 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4119 {
4120 /*
4121 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4122 * register to be written before TxDescAddrLow to work.
4123 * Switching from MMIO to I/O access fixes the issue as well.
4124 */
4125 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4126 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4127 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4128 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4129 }
4130
4131 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4132 {
4133 u32 val;
4134
4135 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4136 val = 0x000fff00;
4137 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4138 val = 0x00ffff00;
4139 else
4140 return;
4141
4142 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4143 val |= 0xff;
4144
4145 RTL_W32(tp, 0x7c, val);
4146 }
4147
4148 static void rtl_set_rx_mode(struct net_device *dev)
4149 {
4150 struct rtl8169_private *tp = netdev_priv(dev);
4151 u32 mc_filter[2]; /* Multicast hash filter */
4152 int rx_mode;
4153 u32 tmp = 0;
4154
4155 if (dev->flags & IFF_PROMISC) {
4156 /* Unconditionally log net taps. */
4157 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4158 rx_mode =
4159 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4160 AcceptAllPhys;
4161 mc_filter[1] = mc_filter[0] = 0xffffffff;
4162 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4163 (dev->flags & IFF_ALLMULTI)) {
4164 /* Too many to filter perfectly -- accept all multicasts. */
4165 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4166 mc_filter[1] = mc_filter[0] = 0xffffffff;
4167 } else {
4168 struct netdev_hw_addr *ha;
4169
4170 rx_mode = AcceptBroadcast | AcceptMyPhys;
4171 mc_filter[1] = mc_filter[0] = 0;
4172 netdev_for_each_mc_addr(ha, dev) {
4173 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4174 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4175 rx_mode |= AcceptMulticast;
4176 }
4177 }
4178
4179 if (dev->features & NETIF_F_RXALL)
4180 rx_mode |= (AcceptErr | AcceptRunt);
4181
4182 tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4183
4184 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4185 u32 data = mc_filter[0];
4186
4187 mc_filter[0] = swab32(mc_filter[1]);
4188 mc_filter[1] = swab32(data);
4189 }
4190
4191 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4192 mc_filter[1] = mc_filter[0] = 0xffffffff;
4193
4194 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4195 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4196
4197 RTL_W32(tp, RxConfig, tmp);
4198 }
4199
4200 DECLARE_RTL_COND(rtl_csiar_cond)
4201 {
4202 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4203 }
4204
4205 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4206 {
4207 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4208
4209 RTL_W32(tp, CSIDR, value);
4210 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4211 CSIAR_BYTE_ENABLE | func << 16);
4212
4213 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4214 }
4215
4216 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4217 {
4218 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4219
4220 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4221 CSIAR_BYTE_ENABLE);
4222
4223 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4224 RTL_R32(tp, CSIDR) : ~0;
4225 }
4226
4227 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4228 {
4229 struct pci_dev *pdev = tp->pci_dev;
4230 u32 csi;
4231
4232 /* According to Realtek the value at config space address 0x070f
4233 * controls the L0s/L1 entrance latency. We try standard ECAM access
4234 * first and if it fails fall back to CSI.
4235 */
4236 if (pdev->cfg_size > 0x070f &&
4237 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4238 return;
4239
4240 netdev_notice_once(tp->dev,
4241 "No native access to PCI extended config space, falling back to CSI\n");
4242 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4243 rtl_csi_write(tp, 0x070c, csi | val << 24);
4244 }
4245
4246 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4247 {
4248 rtl_csi_access_enable(tp, 0x27);
4249 }
4250
4251 struct ephy_info {
4252 unsigned int offset;
4253 u16 mask;
4254 u16 bits;
4255 };
4256
4257 static void __rtl_ephy_init(struct rtl8169_private *tp,
4258 const struct ephy_info *e, int len)
4259 {
4260 u16 w;
4261
4262 while (len-- > 0) {
4263 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4264 rtl_ephy_write(tp, e->offset, w);
4265 e++;
4266 }
4267 }
4268
4269 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
4270
4271 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4272 {
4273 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4274 PCI_EXP_LNKCTL_CLKREQ_EN);
4275 }
4276
4277 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4278 {
4279 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4280 PCI_EXP_LNKCTL_CLKREQ_EN);
4281 }
4282
4283 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
4284 {
4285 /* work around an issue when PCI reset occurs during L2/L3 state */
4286 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
4287 }
4288
4289 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4290 {
4291 if (enable) {
4292 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4293 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4294 } else {
4295 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4296 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4297 }
4298
4299 udelay(10);
4300 }
4301
4302 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
4303 u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
4304 {
4305 /* Usage of dynamic vs. static FIFO is controlled by bit
4306 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
4307 */
4308 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
4309 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
4310 }
4311
4312 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
4313 u8 low, u8 high)
4314 {
4315 /* FIFO thresholds for pause flow control */
4316 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
4317 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
4318 }
4319
4320 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4321 {
4322 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4323
4324 if (tp->dev->mtu <= ETH_DATA_LEN) {
4325 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4326 PCI_EXP_DEVCTL_NOSNOOP_EN);
4327 }
4328 }
4329
4330 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4331 {
4332 rtl_hw_start_8168bb(tp);
4333
4334 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4335 }
4336
4337 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4338 {
4339 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4340
4341 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4342
4343 if (tp->dev->mtu <= ETH_DATA_LEN)
4344 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4345
4346 rtl_disable_clock_request(tp);
4347 }
4348
4349 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4350 {
4351 static const struct ephy_info e_info_8168cp[] = {
4352 { 0x01, 0, 0x0001 },
4353 { 0x02, 0x0800, 0x1000 },
4354 { 0x03, 0, 0x0042 },
4355 { 0x06, 0x0080, 0x0000 },
4356 { 0x07, 0, 0x2000 }
4357 };
4358
4359 rtl_set_def_aspm_entry_latency(tp);
4360
4361 rtl_ephy_init(tp, e_info_8168cp);
4362
4363 __rtl_hw_start_8168cp(tp);
4364 }
4365
4366 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4367 {
4368 rtl_set_def_aspm_entry_latency(tp);
4369
4370 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4371
4372 if (tp->dev->mtu <= ETH_DATA_LEN)
4373 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4374 }
4375
4376 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4377 {
4378 rtl_set_def_aspm_entry_latency(tp);
4379
4380 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4381
4382 /* Magic. */
4383 RTL_W8(tp, DBG_REG, 0x20);
4384
4385 if (tp->dev->mtu <= ETH_DATA_LEN)
4386 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4387 }
4388
4389 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4390 {
4391 static const struct ephy_info e_info_8168c_1[] = {
4392 { 0x02, 0x0800, 0x1000 },
4393 { 0x03, 0, 0x0002 },
4394 { 0x06, 0x0080, 0x0000 }
4395 };
4396
4397 rtl_set_def_aspm_entry_latency(tp);
4398
4399 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4400
4401 rtl_ephy_init(tp, e_info_8168c_1);
4402
4403 __rtl_hw_start_8168cp(tp);
4404 }
4405
4406 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4407 {
4408 static const struct ephy_info e_info_8168c_2[] = {
4409 { 0x01, 0, 0x0001 },
4410 { 0x03, 0x0400, 0x0220 }
4411 };
4412
4413 rtl_set_def_aspm_entry_latency(tp);
4414
4415 rtl_ephy_init(tp, e_info_8168c_2);
4416
4417 __rtl_hw_start_8168cp(tp);
4418 }
4419
4420 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4421 {
4422 rtl_hw_start_8168c_2(tp);
4423 }
4424
4425 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4426 {
4427 rtl_set_def_aspm_entry_latency(tp);
4428
4429 __rtl_hw_start_8168cp(tp);
4430 }
4431
4432 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4433 {
4434 rtl_set_def_aspm_entry_latency(tp);
4435
4436 rtl_disable_clock_request(tp);
4437
4438 if (tp->dev->mtu <= ETH_DATA_LEN)
4439 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4440 }
4441
4442 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4443 {
4444 rtl_set_def_aspm_entry_latency(tp);
4445
4446 if (tp->dev->mtu <= ETH_DATA_LEN)
4447 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4448
4449 rtl_disable_clock_request(tp);
4450 }
4451
4452 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4453 {
4454 static const struct ephy_info e_info_8168d_4[] = {
4455 { 0x0b, 0x0000, 0x0048 },
4456 { 0x19, 0x0020, 0x0050 },
4457 { 0x0c, 0x0100, 0x0020 }
4458 };
4459
4460 rtl_set_def_aspm_entry_latency(tp);
4461
4462 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4463
4464 rtl_ephy_init(tp, e_info_8168d_4);
4465
4466 rtl_enable_clock_request(tp);
4467 }
4468
4469 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4470 {
4471 static const struct ephy_info e_info_8168e_1[] = {
4472 { 0x00, 0x0200, 0x0100 },
4473 { 0x00, 0x0000, 0x0004 },
4474 { 0x06, 0x0002, 0x0001 },
4475 { 0x06, 0x0000, 0x0030 },
4476 { 0x07, 0x0000, 0x2000 },
4477 { 0x00, 0x0000, 0x0020 },
4478 { 0x03, 0x5800, 0x2000 },
4479 { 0x03, 0x0000, 0x0001 },
4480 { 0x01, 0x0800, 0x1000 },
4481 { 0x07, 0x0000, 0x4000 },
4482 { 0x1e, 0x0000, 0x2000 },
4483 { 0x19, 0xffff, 0xfe6c },
4484 { 0x0a, 0x0000, 0x0040 }
4485 };
4486
4487 rtl_set_def_aspm_entry_latency(tp);
4488
4489 rtl_ephy_init(tp, e_info_8168e_1);
4490
4491 if (tp->dev->mtu <= ETH_DATA_LEN)
4492 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4493
4494 rtl_disable_clock_request(tp);
4495
4496 /* Reset tx FIFO pointer */
4497 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4498 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4499
4500 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4501 }
4502
4503 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4504 {
4505 static const struct ephy_info e_info_8168e_2[] = {
4506 { 0x09, 0x0000, 0x0080 },
4507 { 0x19, 0x0000, 0x0224 }
4508 };
4509
4510 rtl_set_def_aspm_entry_latency(tp);
4511
4512 rtl_ephy_init(tp, e_info_8168e_2);
4513
4514 if (tp->dev->mtu <= ETH_DATA_LEN)
4515 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4516
4517 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4518 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4519 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4520 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4521 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
4522 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4523 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4524
4525 rtl_disable_clock_request(tp);
4526
4527 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4528
4529 rtl8168_config_eee_mac(tp);
4530
4531 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4532 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4533 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4534
4535 rtl_hw_aspm_clkreq_enable(tp, true);
4536 }
4537
4538 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
4539 {
4540 rtl_set_def_aspm_entry_latency(tp);
4541
4542 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4543
4544 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4545 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4546 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4547 rtl_reset_packet_filter(tp);
4548 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4549 rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));
4550 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4551 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
4552
4553 rtl_disable_clock_request(tp);
4554
4555 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4556 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4557 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4558 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4559
4560 rtl8168_config_eee_mac(tp);
4561 }
4562
4563 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
4564 {
4565 static const struct ephy_info e_info_8168f_1[] = {
4566 { 0x06, 0x00c0, 0x0020 },
4567 { 0x08, 0x0001, 0x0002 },
4568 { 0x09, 0x0000, 0x0080 },
4569 { 0x19, 0x0000, 0x0224 }
4570 };
4571
4572 rtl_hw_start_8168f(tp);
4573
4574 rtl_ephy_init(tp, e_info_8168f_1);
4575
4576 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4577 }
4578
4579 static void rtl_hw_start_8411(struct rtl8169_private *tp)
4580 {
4581 static const struct ephy_info e_info_8168f_1[] = {
4582 { 0x06, 0x00c0, 0x0020 },
4583 { 0x0f, 0xffff, 0x5200 },
4584 { 0x1e, 0x0000, 0x4000 },
4585 { 0x19, 0x0000, 0x0224 }
4586 };
4587
4588 rtl_hw_start_8168f(tp);
4589 rtl_pcie_state_l2l3_disable(tp);
4590
4591 rtl_ephy_init(tp, e_info_8168f_1);
4592
4593 rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);
4594 }
4595
4596 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
4597 {
4598 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4599 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4600
4601 rtl_set_def_aspm_entry_latency(tp);
4602
4603 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4604
4605 rtl_reset_packet_filter(tp);
4606 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
4607
4608 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4609
4610 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4611 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4612
4613 rtl8168_config_eee_mac(tp);
4614
4615 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
4616 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4617
4618 rtl_pcie_state_l2l3_disable(tp);
4619 }
4620
4621 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
4622 {
4623 static const struct ephy_info e_info_8168g_1[] = {
4624 { 0x00, 0x0000, 0x0008 },
4625 { 0x0c, 0x37d0, 0x0820 },
4626 { 0x1e, 0x0000, 0x0001 },
4627 { 0x19, 0x8000, 0x0000 }
4628 };
4629
4630 rtl_hw_start_8168g(tp);
4631
4632 /* disable aspm and clock request before access ephy */
4633 rtl_hw_aspm_clkreq_enable(tp, false);
4634 rtl_ephy_init(tp, e_info_8168g_1);
4635 rtl_hw_aspm_clkreq_enable(tp, true);
4636 }
4637
4638 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
4639 {
4640 static const struct ephy_info e_info_8168g_2[] = {
4641 { 0x00, 0x0000, 0x0008 },
4642 { 0x0c, 0x3df0, 0x0200 },
4643 { 0x19, 0xffff, 0xfc00 },
4644 { 0x1e, 0xffff, 0x20eb }
4645 };
4646
4647 rtl_hw_start_8168g(tp);
4648
4649 /* disable aspm and clock request before access ephy */
4650 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4651 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4652 rtl_ephy_init(tp, e_info_8168g_2);
4653 }
4654
4655 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
4656 {
4657 static const struct ephy_info e_info_8411_2[] = {
4658 { 0x00, 0x0000, 0x0008 },
4659 { 0x0c, 0x3df0, 0x0200 },
4660 { 0x0f, 0xffff, 0x5200 },
4661 { 0x19, 0x0020, 0x0000 },
4662 { 0x1e, 0x0000, 0x2000 }
4663 };
4664
4665 rtl_hw_start_8168g(tp);
4666
4667 /* disable aspm and clock request before access ephy */
4668 rtl_hw_aspm_clkreq_enable(tp, false);
4669 rtl_ephy_init(tp, e_info_8411_2);
4670 rtl_hw_aspm_clkreq_enable(tp, true);
4671 }
4672
4673 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
4674 {
4675 int rg_saw_cnt;
4676 u32 data;
4677 static const struct ephy_info e_info_8168h_1[] = {
4678 { 0x1e, 0x0800, 0x0001 },
4679 { 0x1d, 0x0000, 0x0800 },
4680 { 0x05, 0xffff, 0x2089 },
4681 { 0x06, 0xffff, 0x5881 },
4682 { 0x04, 0xffff, 0x154a },
4683 { 0x01, 0xffff, 0x068b }
4684 };
4685
4686 /* disable aspm and clock request before access ephy */
4687 rtl_hw_aspm_clkreq_enable(tp, false);
4688 rtl_ephy_init(tp, e_info_8168h_1);
4689
4690 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4691 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4692
4693 rtl_set_def_aspm_entry_latency(tp);
4694
4695 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4696
4697 rtl_reset_packet_filter(tp);
4698
4699 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
4700
4701 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);
4702
4703 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
4704
4705 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4706
4707 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4708 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4709
4710 rtl8168_config_eee_mac(tp);
4711
4712 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4713 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4714
4715 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
4716
4717 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4718
4719 rtl_pcie_state_l2l3_disable(tp);
4720
4721 rtl_writephy(tp, 0x1f, 0x0c42);
4722 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
4723 rtl_writephy(tp, 0x1f, 0x0000);
4724 if (rg_saw_cnt > 0) {
4725 u16 sw_cnt_1ms_ini;
4726
4727 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
4728 sw_cnt_1ms_ini &= 0x0fff;
4729 data = r8168_mac_ocp_read(tp, 0xd412);
4730 data &= ~0x0fff;
4731 data |= sw_cnt_1ms_ini;
4732 r8168_mac_ocp_write(tp, 0xd412, data);
4733 }
4734
4735 data = r8168_mac_ocp_read(tp, 0xe056);
4736 data &= ~0xf0;
4737 data |= 0x70;
4738 r8168_mac_ocp_write(tp, 0xe056, data);
4739
4740 data = r8168_mac_ocp_read(tp, 0xe052);
4741 data &= ~0x6000;
4742 data |= 0x8008;
4743 r8168_mac_ocp_write(tp, 0xe052, data);
4744
4745 data = r8168_mac_ocp_read(tp, 0xe0d6);
4746 data &= ~0x01ff;
4747 data |= 0x017f;
4748 r8168_mac_ocp_write(tp, 0xe0d6, data);
4749
4750 data = r8168_mac_ocp_read(tp, 0xd420);
4751 data &= ~0x0fff;
4752 data |= 0x047f;
4753 r8168_mac_ocp_write(tp, 0xd420, data);
4754
4755 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
4756 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
4757 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
4758 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
4759
4760 rtl_hw_aspm_clkreq_enable(tp, true);
4761 }
4762
4763 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
4764 {
4765 rtl8168ep_stop_cmac(tp);
4766
4767 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4768 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
4769
4770 rtl_set_def_aspm_entry_latency(tp);
4771
4772 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4773
4774 rtl_reset_packet_filter(tp);
4775
4776 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
4777
4778 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
4779
4780 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4781
4782 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4783 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4784
4785 rtl8168_config_eee_mac(tp);
4786
4787 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
4788
4789 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
4790
4791 rtl_pcie_state_l2l3_disable(tp);
4792 }
4793
4794 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
4795 {
4796 static const struct ephy_info e_info_8168ep_1[] = {
4797 { 0x00, 0xffff, 0x10ab },
4798 { 0x06, 0xffff, 0xf030 },
4799 { 0x08, 0xffff, 0x2006 },
4800 { 0x0d, 0xffff, 0x1666 },
4801 { 0x0c, 0x3ff0, 0x0000 }
4802 };
4803
4804 /* disable aspm and clock request before access ephy */
4805 rtl_hw_aspm_clkreq_enable(tp, false);
4806 rtl_ephy_init(tp, e_info_8168ep_1);
4807
4808 rtl_hw_start_8168ep(tp);
4809
4810 rtl_hw_aspm_clkreq_enable(tp, true);
4811 }
4812
4813 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
4814 {
4815 static const struct ephy_info e_info_8168ep_2[] = {
4816 { 0x00, 0xffff, 0x10a3 },
4817 { 0x19, 0xffff, 0xfc00 },
4818 { 0x1e, 0xffff, 0x20ea }
4819 };
4820
4821 /* disable aspm and clock request before access ephy */
4822 rtl_hw_aspm_clkreq_enable(tp, false);
4823 rtl_ephy_init(tp, e_info_8168ep_2);
4824
4825 rtl_hw_start_8168ep(tp);
4826
4827 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4828 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4829
4830 rtl_hw_aspm_clkreq_enable(tp, true);
4831 }
4832
4833 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
4834 {
4835 u32 data;
4836 static const struct ephy_info e_info_8168ep_3[] = {
4837 { 0x00, 0xffff, 0x10a3 },
4838 { 0x19, 0xffff, 0x7c00 },
4839 { 0x1e, 0xffff, 0x20eb },
4840 { 0x0d, 0xffff, 0x1666 }
4841 };
4842
4843 /* disable aspm and clock request before access ephy */
4844 rtl_hw_aspm_clkreq_enable(tp, false);
4845 rtl_ephy_init(tp, e_info_8168ep_3);
4846
4847 rtl_hw_start_8168ep(tp);
4848
4849 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4850 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4851
4852 data = r8168_mac_ocp_read(tp, 0xd3e2);
4853 data &= 0xf000;
4854 data |= 0x0271;
4855 r8168_mac_ocp_write(tp, 0xd3e2, data);
4856
4857 data = r8168_mac_ocp_read(tp, 0xd3e4);
4858 data &= 0xff00;
4859 r8168_mac_ocp_write(tp, 0xd3e4, data);
4860
4861 data = r8168_mac_ocp_read(tp, 0xe860);
4862 data |= 0x0080;
4863 r8168_mac_ocp_write(tp, 0xe860, data);
4864
4865 rtl_hw_aspm_clkreq_enable(tp, true);
4866 }
4867
4868 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
4869 {
4870 static const struct ephy_info e_info_8102e_1[] = {
4871 { 0x01, 0, 0x6e65 },
4872 { 0x02, 0, 0x091f },
4873 { 0x03, 0, 0xc2f9 },
4874 { 0x06, 0, 0xafb5 },
4875 { 0x07, 0, 0x0e00 },
4876 { 0x19, 0, 0xec80 },
4877 { 0x01, 0, 0x2e65 },
4878 { 0x01, 0, 0x6e65 }
4879 };
4880 u8 cfg1;
4881
4882 rtl_set_def_aspm_entry_latency(tp);
4883
4884 RTL_W8(tp, DBG_REG, FIX_NAK_1);
4885
4886 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4887
4888 RTL_W8(tp, Config1,
4889 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4890 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4891
4892 cfg1 = RTL_R8(tp, Config1);
4893 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4894 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
4895
4896 rtl_ephy_init(tp, e_info_8102e_1);
4897 }
4898
4899 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
4900 {
4901 rtl_set_def_aspm_entry_latency(tp);
4902
4903 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4904
4905 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
4906 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4907 }
4908
4909 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
4910 {
4911 rtl_hw_start_8102e_2(tp);
4912
4913 rtl_ephy_write(tp, 0x03, 0xc2f9);
4914 }
4915
4916 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
4917 {
4918 static const struct ephy_info e_info_8105e_1[] = {
4919 { 0x07, 0, 0x4000 },
4920 { 0x19, 0, 0x0200 },
4921 { 0x19, 0, 0x0020 },
4922 { 0x1e, 0, 0x2000 },
4923 { 0x03, 0, 0x0001 },
4924 { 0x19, 0, 0x0100 },
4925 { 0x19, 0, 0x0004 },
4926 { 0x0a, 0, 0x0020 }
4927 };
4928
4929 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4930 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
4931
4932 /* Disable Early Tally Counter */
4933 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
4934
4935 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
4936 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4937
4938 rtl_ephy_init(tp, e_info_8105e_1);
4939
4940 rtl_pcie_state_l2l3_disable(tp);
4941 }
4942
4943 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
4944 {
4945 rtl_hw_start_8105e_1(tp);
4946 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
4947 }
4948
4949 static void rtl_hw_start_8402(struct rtl8169_private *tp)
4950 {
4951 static const struct ephy_info e_info_8402[] = {
4952 { 0x19, 0xffff, 0xff64 },
4953 { 0x1e, 0, 0x4000 }
4954 };
4955
4956 rtl_set_def_aspm_entry_latency(tp);
4957
4958 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4959 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
4960
4961 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4962
4963 rtl_ephy_init(tp, e_info_8402);
4964
4965 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4966
4967 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
4968 rtl_reset_packet_filter(tp);
4969 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4970 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4971 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
4972
4973 rtl_pcie_state_l2l3_disable(tp);
4974 }
4975
4976 static void rtl_hw_start_8106(struct rtl8169_private *tp)
4977 {
4978 rtl_hw_aspm_clkreq_enable(tp, false);
4979
4980 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4981 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
4982
4983 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
4984 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
4985 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4986
4987 rtl_pcie_state_l2l3_disable(tp);
4988 rtl_hw_aspm_clkreq_enable(tp, true);
4989 }
4990
4991 static void rtl_hw_config(struct rtl8169_private *tp)
4992 {
4993 static const rtl_generic_fct hw_configs[] = {
4994 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
4995 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
4996 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
4997 [RTL_GIGA_MAC_VER_10] = NULL,
4998 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168bb,
4999 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168bef,
5000 [RTL_GIGA_MAC_VER_13] = NULL,
5001 [RTL_GIGA_MAC_VER_14] = NULL,
5002 [RTL_GIGA_MAC_VER_15] = NULL,
5003 [RTL_GIGA_MAC_VER_16] = NULL,
5004 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168bef,
5005 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
5006 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
5007 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
5008 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
5009 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
5010 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
5011 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
5012 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
5013 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
5014 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
5015 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
5016 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
5017 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
5018 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168dp,
5019 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
5020 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
5021 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
5022 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
5023 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
5024 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
5025 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
5026 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
5027 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
5028 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
5029 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
5030 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
5031 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
5032 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
5033 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
5034 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
5035 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
5036 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
5037 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
5038 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
5039 };
5040
5041 if (hw_configs[tp->mac_version])
5042 hw_configs[tp->mac_version](tp);
5043 }
5044
5045 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5046 {
5047 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5048 tp->mac_version == RTL_GIGA_MAC_VER_16)
5049 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5050 PCI_EXP_DEVCTL_NOSNOOP_EN);
5051
5052 if (rtl_is_8168evl_up(tp))
5053 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5054 else
5055 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5056
5057 rtl_hw_config(tp);
5058 }
5059
5060 static void rtl_hw_start_8169(struct rtl8169_private *tp)
5061 {
5062 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5063 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
5064
5065 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
5066
5067 tp->cp_cmd |= PCIMulRW;
5068
5069 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5070 tp->mac_version == RTL_GIGA_MAC_VER_03) {
5071 netif_dbg(tp, drv, tp->dev,
5072 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
5073 tp->cp_cmd |= (1 << 14);
5074 }
5075
5076 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5077
5078 rtl8169_set_magic_reg(tp, tp->mac_version);
5079
5080 RTL_W32(tp, RxMissed, 0);
5081 }
5082
5083 static void rtl_hw_start(struct rtl8169_private *tp)
5084 {
5085 rtl_unlock_config_regs(tp);
5086
5087 tp->cp_cmd &= CPCMD_MASK;
5088 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5089
5090 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5091 rtl_hw_start_8169(tp);
5092 else
5093 rtl_hw_start_8168(tp);
5094
5095 rtl_set_rx_max_size(tp);
5096 rtl_set_rx_tx_desc_registers(tp);
5097 rtl_lock_config_regs(tp);
5098
5099 /* disable interrupt coalescing */
5100 RTL_W16(tp, IntrMitigate, 0x0000);
5101 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5102 RTL_R8(tp, IntrMask);
5103 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
5104 rtl_init_rxcfg(tp);
5105 rtl_set_tx_config_registers(tp);
5106
5107 rtl_set_rx_mode(tp->dev);
5108 /* no early-rx interrupts */
5109 RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
5110 rtl_irq_enable(tp);
5111 }
5112
5113 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5114 {
5115 struct rtl8169_private *tp = netdev_priv(dev);
5116
5117 if (new_mtu > ETH_DATA_LEN)
5118 rtl_hw_jumbo_enable(tp);
5119 else
5120 rtl_hw_jumbo_disable(tp);
5121
5122 dev->mtu = new_mtu;
5123 netdev_update_features(dev);
5124
5125 return 0;
5126 }
5127
5128 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5129 {
5130 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5131 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5132 }
5133
5134 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5135 void **data_buff, struct RxDesc *desc)
5136 {
5137 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5138 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5139
5140 kfree(*data_buff);
5141 *data_buff = NULL;
5142 rtl8169_make_unusable_by_asic(desc);
5143 }
5144
5145 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5146 {
5147 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5148
5149 /* Force memory writes to complete before releasing descriptor */
5150 dma_wmb();
5151
5152 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5153 }
5154
5155 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5156 struct RxDesc *desc)
5157 {
5158 void *data;
5159 dma_addr_t mapping;
5160 struct device *d = tp_to_dev(tp);
5161 int node = dev_to_node(d);
5162
5163 data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5164 if (!data)
5165 return NULL;
5166
5167 /* Memory should be properly aligned, but better check. */
5168 if (!IS_ALIGNED((unsigned long)data, 8)) {
5169 netdev_err_once(tp->dev, "RX buffer not 8-byte-aligned\n");
5170 goto err_out;
5171 }
5172
5173 mapping = dma_map_single(d, data, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5174 if (unlikely(dma_mapping_error(d, mapping))) {
5175 if (net_ratelimit())
5176 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5177 goto err_out;
5178 }
5179
5180 desc->addr = cpu_to_le64(mapping);
5181 rtl8169_mark_to_asic(desc);
5182 return data;
5183
5184 err_out:
5185 kfree(data);
5186 return NULL;
5187 }
5188
5189 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5190 {
5191 unsigned int i;
5192
5193 for (i = 0; i < NUM_RX_DESC; i++) {
5194 if (tp->Rx_databuff[i]) {
5195 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5196 tp->RxDescArray + i);
5197 }
5198 }
5199 }
5200
5201 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5202 {
5203 desc->opts1 |= cpu_to_le32(RingEnd);
5204 }
5205
5206 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5207 {
5208 unsigned int i;
5209
5210 for (i = 0; i < NUM_RX_DESC; i++) {
5211 void *data;
5212
5213 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5214 if (!data) {
5215 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5216 goto err_out;
5217 }
5218 tp->Rx_databuff[i] = data;
5219 }
5220
5221 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5222 return 0;
5223
5224 err_out:
5225 rtl8169_rx_clear(tp);
5226 return -ENOMEM;
5227 }
5228
5229 static int rtl8169_init_ring(struct rtl8169_private *tp)
5230 {
5231 rtl8169_init_ring_indexes(tp);
5232
5233 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5234 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5235
5236 return rtl8169_rx_fill(tp);
5237 }
5238
5239 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5240 struct TxDesc *desc)
5241 {
5242 unsigned int len = tx_skb->len;
5243
5244 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5245
5246 desc->opts1 = 0x00;
5247 desc->opts2 = 0x00;
5248 desc->addr = 0x00;
5249 tx_skb->len = 0;
5250 }
5251
5252 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5253 unsigned int n)
5254 {
5255 unsigned int i;
5256
5257 for (i = 0; i < n; i++) {
5258 unsigned int entry = (start + i) % NUM_TX_DESC;
5259 struct ring_info *tx_skb = tp->tx_skb + entry;
5260 unsigned int len = tx_skb->len;
5261
5262 if (len) {
5263 struct sk_buff *skb = tx_skb->skb;
5264
5265 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5266 tp->TxDescArray + entry);
5267 if (skb) {
5268 dev_consume_skb_any(skb);
5269 tx_skb->skb = NULL;
5270 }
5271 }
5272 }
5273 }
5274
5275 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5276 {
5277 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5278 tp->cur_tx = tp->dirty_tx = 0;
5279 netdev_reset_queue(tp->dev);
5280 }
5281
5282 static void rtl_reset_work(struct rtl8169_private *tp)
5283 {
5284 struct net_device *dev = tp->dev;
5285 int i;
5286
5287 napi_disable(&tp->napi);
5288 netif_stop_queue(dev);
5289 synchronize_rcu();
5290
5291 rtl8169_hw_reset(tp);
5292
5293 for (i = 0; i < NUM_RX_DESC; i++)
5294 rtl8169_mark_to_asic(tp->RxDescArray + i);
5295
5296 rtl8169_tx_clear(tp);
5297 rtl8169_init_ring_indexes(tp);
5298
5299 napi_enable(&tp->napi);
5300 rtl_hw_start(tp);
5301 netif_wake_queue(dev);
5302 }
5303
5304 static void rtl8169_tx_timeout(struct net_device *dev)
5305 {
5306 struct rtl8169_private *tp = netdev_priv(dev);
5307
5308 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5309 }
5310
5311 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5312 {
5313 u32 status = opts0 | len;
5314
5315 if (entry == NUM_TX_DESC - 1)
5316 status |= RingEnd;
5317
5318 return cpu_to_le32(status);
5319 }
5320
5321 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5322 u32 *opts)
5323 {
5324 struct skb_shared_info *info = skb_shinfo(skb);
5325 unsigned int cur_frag, entry;
5326 struct TxDesc *uninitialized_var(txd);
5327 struct device *d = tp_to_dev(tp);
5328
5329 entry = tp->cur_tx;
5330 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5331 const skb_frag_t *frag = info->frags + cur_frag;
5332 dma_addr_t mapping;
5333 u32 len;
5334 void *addr;
5335
5336 entry = (entry + 1) % NUM_TX_DESC;
5337
5338 txd = tp->TxDescArray + entry;
5339 len = skb_frag_size(frag);
5340 addr = skb_frag_address(frag);
5341 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5342 if (unlikely(dma_mapping_error(d, mapping))) {
5343 if (net_ratelimit())
5344 netif_err(tp, drv, tp->dev,
5345 "Failed to map TX fragments DMA!\n");
5346 goto err_out;
5347 }
5348
5349 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5350 txd->opts2 = cpu_to_le32(opts[1]);
5351 txd->addr = cpu_to_le64(mapping);
5352
5353 tp->tx_skb[entry].len = len;
5354 }
5355
5356 if (cur_frag) {
5357 tp->tx_skb[entry].skb = skb;
5358 txd->opts1 |= cpu_to_le32(LastFrag);
5359 }
5360
5361 return cur_frag;
5362
5363 err_out:
5364 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5365 return -EIO;
5366 }
5367
5368 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5369 {
5370 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5371 }
5372
5373 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5374 struct net_device *dev);
5375 /* r8169_csum_workaround()
5376 * The hw limites the value the transport offset. When the offset is out of the
5377 * range, calculate the checksum by sw.
5378 */
5379 static void r8169_csum_workaround(struct rtl8169_private *tp,
5380 struct sk_buff *skb)
5381 {
5382 if (skb_is_gso(skb)) {
5383 netdev_features_t features = tp->dev->features;
5384 struct sk_buff *segs, *nskb;
5385
5386 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5387 segs = skb_gso_segment(skb, features);
5388 if (IS_ERR(segs) || !segs)
5389 goto drop;
5390
5391 do {
5392 nskb = segs;
5393 segs = segs->next;
5394 nskb->next = NULL;
5395 rtl8169_start_xmit(nskb, tp->dev);
5396 } while (segs);
5397
5398 dev_consume_skb_any(skb);
5399 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5400 if (skb_checksum_help(skb) < 0)
5401 goto drop;
5402
5403 rtl8169_start_xmit(skb, tp->dev);
5404 } else {
5405 drop:
5406 tp->dev->stats.tx_dropped++;
5407 dev_kfree_skb_any(skb);
5408 }
5409 }
5410
5411 /* msdn_giant_send_check()
5412 * According to the document of microsoft, the TCP Pseudo Header excludes the
5413 * packet length for IPv6 TCP large packets.
5414 */
5415 static int msdn_giant_send_check(struct sk_buff *skb)
5416 {
5417 const struct ipv6hdr *ipv6h;
5418 struct tcphdr *th;
5419 int ret;
5420
5421 ret = skb_cow_head(skb, 0);
5422 if (ret)
5423 return ret;
5424
5425 ipv6h = ipv6_hdr(skb);
5426 th = tcp_hdr(skb);
5427
5428 th->check = 0;
5429 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5430
5431 return ret;
5432 }
5433
5434 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
5435 {
5436 u32 mss = skb_shinfo(skb)->gso_size;
5437
5438 if (mss) {
5439 opts[0] |= TD_LSO;
5440 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5441 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5442 const struct iphdr *ip = ip_hdr(skb);
5443
5444 if (ip->protocol == IPPROTO_TCP)
5445 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5446 else if (ip->protocol == IPPROTO_UDP)
5447 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5448 else
5449 WARN_ON_ONCE(1);
5450 }
5451 }
5452
5453 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5454 struct sk_buff *skb, u32 *opts)
5455 {
5456 u32 transport_offset = (u32)skb_transport_offset(skb);
5457 u32 mss = skb_shinfo(skb)->gso_size;
5458
5459 if (mss) {
5460 if (transport_offset > GTTCPHO_MAX) {
5461 netif_warn(tp, tx_err, tp->dev,
5462 "Invalid transport offset 0x%x for TSO\n",
5463 transport_offset);
5464 return false;
5465 }
5466
5467 switch (vlan_get_protocol(skb)) {
5468 case htons(ETH_P_IP):
5469 opts[0] |= TD1_GTSENV4;
5470 break;
5471
5472 case htons(ETH_P_IPV6):
5473 if (msdn_giant_send_check(skb))
5474 return false;
5475
5476 opts[0] |= TD1_GTSENV6;
5477 break;
5478
5479 default:
5480 WARN_ON_ONCE(1);
5481 break;
5482 }
5483
5484 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5485 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
5486 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5487 u8 ip_protocol;
5488
5489 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5490 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
5491
5492 if (transport_offset > TCPHO_MAX) {
5493 netif_warn(tp, tx_err, tp->dev,
5494 "Invalid transport offset 0x%x\n",
5495 transport_offset);
5496 return false;
5497 }
5498
5499 switch (vlan_get_protocol(skb)) {
5500 case htons(ETH_P_IP):
5501 opts[1] |= TD1_IPv4_CS;
5502 ip_protocol = ip_hdr(skb)->protocol;
5503 break;
5504
5505 case htons(ETH_P_IPV6):
5506 opts[1] |= TD1_IPv6_CS;
5507 ip_protocol = ipv6_hdr(skb)->nexthdr;
5508 break;
5509
5510 default:
5511 ip_protocol = IPPROTO_RAW;
5512 break;
5513 }
5514
5515 if (ip_protocol == IPPROTO_TCP)
5516 opts[1] |= TD1_TCP_CS;
5517 else if (ip_protocol == IPPROTO_UDP)
5518 opts[1] |= TD1_UDP_CS;
5519 else
5520 WARN_ON_ONCE(1);
5521
5522 opts[1] |= transport_offset << TCPHO_SHIFT;
5523 } else {
5524 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5525 return !eth_skb_pad(skb);
5526 }
5527
5528 return true;
5529 }
5530
5531 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
5532 unsigned int nr_frags)
5533 {
5534 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
5535
5536 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
5537 return slots_avail > nr_frags;
5538 }
5539
5540 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
5541 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
5542 {
5543 switch (tp->mac_version) {
5544 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5545 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
5546 return false;
5547 default:
5548 return true;
5549 }
5550 }
5551
5552 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5553 struct net_device *dev)
5554 {
5555 struct rtl8169_private *tp = netdev_priv(dev);
5556 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5557 struct TxDesc *txd = tp->TxDescArray + entry;
5558 struct device *d = tp_to_dev(tp);
5559 dma_addr_t mapping;
5560 u32 opts[2], len;
5561 int frags;
5562
5563 if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
5564 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5565 goto err_stop_0;
5566 }
5567
5568 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5569 goto err_stop_0;
5570
5571 opts[1] = rtl8169_tx_vlan_tag(skb);
5572 opts[0] = DescOwn;
5573
5574 if (rtl_chip_supports_csum_v2(tp)) {
5575 if (!rtl8169_tso_csum_v2(tp, skb, opts)) {
5576 r8169_csum_workaround(tp, skb);
5577 return NETDEV_TX_OK;
5578 }
5579 } else {
5580 rtl8169_tso_csum_v1(skb, opts);
5581 }
5582
5583 len = skb_headlen(skb);
5584 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5585 if (unlikely(dma_mapping_error(d, mapping))) {
5586 if (net_ratelimit())
5587 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5588 goto err_dma_0;
5589 }
5590
5591 tp->tx_skb[entry].len = len;
5592 txd->addr = cpu_to_le64(mapping);
5593
5594 frags = rtl8169_xmit_frags(tp, skb, opts);
5595 if (frags < 0)
5596 goto err_dma_1;
5597 else if (frags)
5598 opts[0] |= FirstFrag;
5599 else {
5600 opts[0] |= FirstFrag | LastFrag;
5601 tp->tx_skb[entry].skb = skb;
5602 }
5603
5604 txd->opts2 = cpu_to_le32(opts[1]);
5605
5606 netdev_sent_queue(dev, skb->len);
5607
5608 skb_tx_timestamp(skb);
5609
5610 /* Force memory writes to complete before releasing descriptor */
5611 dma_wmb();
5612
5613 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5614
5615 /* Force all memory writes to complete before notifying device */
5616 wmb();
5617
5618 tp->cur_tx += frags + 1;
5619
5620 RTL_W8(tp, TxPoll, NPQ);
5621
5622 if (!rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
5623 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5624 * not miss a ring update when it notices a stopped queue.
5625 */
5626 smp_wmb();
5627 netif_stop_queue(dev);
5628 /* Sync with rtl_tx:
5629 * - publish queue status and cur_tx ring index (write barrier)
5630 * - refresh dirty_tx ring index (read barrier).
5631 * May the current thread have a pessimistic view of the ring
5632 * status and forget to wake up queue, a racing rtl_tx thread
5633 * can't.
5634 */
5635 smp_mb();
5636 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
5637 netif_start_queue(dev);
5638 }
5639
5640 return NETDEV_TX_OK;
5641
5642 err_dma_1:
5643 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5644 err_dma_0:
5645 dev_kfree_skb_any(skb);
5646 dev->stats.tx_dropped++;
5647 return NETDEV_TX_OK;
5648
5649 err_stop_0:
5650 netif_stop_queue(dev);
5651 dev->stats.tx_dropped++;
5652 return NETDEV_TX_BUSY;
5653 }
5654
5655 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5656 {
5657 struct rtl8169_private *tp = netdev_priv(dev);
5658 struct pci_dev *pdev = tp->pci_dev;
5659 u16 pci_status, pci_cmd;
5660
5661 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5662 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5663
5664 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5665 pci_cmd, pci_status);
5666
5667 /*
5668 * The recovery sequence below admits a very elaborated explanation:
5669 * - it seems to work;
5670 * - I did not see what else could be done;
5671 * - it makes iop3xx happy.
5672 *
5673 * Feel free to adjust to your needs.
5674 */
5675 if (pdev->broken_parity_status)
5676 pci_cmd &= ~PCI_COMMAND_PARITY;
5677 else
5678 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5679
5680 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5681
5682 pci_write_config_word(pdev, PCI_STATUS,
5683 pci_status & (PCI_STATUS_DETECTED_PARITY |
5684 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5685 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5686
5687 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5688 }
5689
5690 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
5691 int budget)
5692 {
5693 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
5694
5695 dirty_tx = tp->dirty_tx;
5696 smp_rmb();
5697 tx_left = tp->cur_tx - dirty_tx;
5698
5699 while (tx_left > 0) {
5700 unsigned int entry = dirty_tx % NUM_TX_DESC;
5701 struct ring_info *tx_skb = tp->tx_skb + entry;
5702 u32 status;
5703
5704 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5705 if (status & DescOwn)
5706 break;
5707
5708 /* This barrier is needed to keep us from reading
5709 * any other fields out of the Tx descriptor until
5710 * we know the status of DescOwn
5711 */
5712 dma_rmb();
5713
5714 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5715 tp->TxDescArray + entry);
5716 if (status & LastFrag) {
5717 pkts_compl++;
5718 bytes_compl += tx_skb->skb->len;
5719 napi_consume_skb(tx_skb->skb, budget);
5720 tx_skb->skb = NULL;
5721 }
5722 dirty_tx++;
5723 tx_left--;
5724 }
5725
5726 if (tp->dirty_tx != dirty_tx) {
5727 netdev_completed_queue(dev, pkts_compl, bytes_compl);
5728
5729 u64_stats_update_begin(&tp->tx_stats.syncp);
5730 tp->tx_stats.packets += pkts_compl;
5731 tp->tx_stats.bytes += bytes_compl;
5732 u64_stats_update_end(&tp->tx_stats.syncp);
5733
5734 tp->dirty_tx = dirty_tx;
5735 /* Sync with rtl8169_start_xmit:
5736 * - publish dirty_tx ring index (write barrier)
5737 * - refresh cur_tx ring index and queue status (read barrier)
5738 * May the current thread miss the stopped queue condition,
5739 * a racing xmit thread can only have a right view of the
5740 * ring status.
5741 */
5742 smp_mb();
5743 if (netif_queue_stopped(dev) &&
5744 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
5745 netif_wake_queue(dev);
5746 }
5747 /*
5748 * 8168 hack: TxPoll requests are lost when the Tx packets are
5749 * too close. Let's kick an extra TxPoll request when a burst
5750 * of start_xmit activity is detected (if it is not detected,
5751 * it is slow enough). -- FR
5752 */
5753 if (tp->cur_tx != dirty_tx)
5754 RTL_W8(tp, TxPoll, NPQ);
5755 }
5756 }
5757
5758 static inline int rtl8169_fragmented_frame(u32 status)
5759 {
5760 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5761 }
5762
5763 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5764 {
5765 u32 status = opts1 & RxProtoMask;
5766
5767 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5768 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5769 skb->ip_summed = CHECKSUM_UNNECESSARY;
5770 else
5771 skb_checksum_none_assert(skb);
5772 }
5773
5774 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5775 struct rtl8169_private *tp,
5776 int pkt_size,
5777 dma_addr_t addr)
5778 {
5779 struct sk_buff *skb;
5780 struct device *d = tp_to_dev(tp);
5781
5782 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5783 prefetch(data);
5784 skb = napi_alloc_skb(&tp->napi, pkt_size);
5785 if (skb)
5786 skb_copy_to_linear_data(skb, data, pkt_size);
5787 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5788
5789 return skb;
5790 }
5791
5792 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5793 {
5794 unsigned int cur_rx, rx_left;
5795 unsigned int count;
5796
5797 cur_rx = tp->cur_rx;
5798
5799 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
5800 unsigned int entry = cur_rx % NUM_RX_DESC;
5801 struct RxDesc *desc = tp->RxDescArray + entry;
5802 u32 status;
5803
5804 status = le32_to_cpu(desc->opts1);
5805 if (status & DescOwn)
5806 break;
5807
5808 /* This barrier is needed to keep us from reading
5809 * any other fields out of the Rx descriptor until
5810 * we know the status of DescOwn
5811 */
5812 dma_rmb();
5813
5814 if (unlikely(status & RxRES)) {
5815 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5816 status);
5817 dev->stats.rx_errors++;
5818 if (status & (RxRWT | RxRUNT))
5819 dev->stats.rx_length_errors++;
5820 if (status & RxCRC)
5821 dev->stats.rx_crc_errors++;
5822 if (status & (RxRUNT | RxCRC) && !(status & RxRWT) &&
5823 dev->features & NETIF_F_RXALL) {
5824 goto process_pkt;
5825 }
5826 } else {
5827 struct sk_buff *skb;
5828 dma_addr_t addr;
5829 int pkt_size;
5830
5831 process_pkt:
5832 addr = le64_to_cpu(desc->addr);
5833 if (likely(!(dev->features & NETIF_F_RXFCS)))
5834 pkt_size = (status & 0x00003fff) - 4;
5835 else
5836 pkt_size = status & 0x00003fff;
5837
5838 /*
5839 * The driver does not support incoming fragmented
5840 * frames. They are seen as a symptom of over-mtu
5841 * sized frames.
5842 */
5843 if (unlikely(rtl8169_fragmented_frame(status))) {
5844 dev->stats.rx_dropped++;
5845 dev->stats.rx_length_errors++;
5846 goto release_descriptor;
5847 }
5848
5849 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5850 tp, pkt_size, addr);
5851 if (!skb) {
5852 dev->stats.rx_dropped++;
5853 goto release_descriptor;
5854 }
5855
5856 rtl8169_rx_csum(skb, status);
5857 skb_put(skb, pkt_size);
5858 skb->protocol = eth_type_trans(skb, dev);
5859
5860 rtl8169_rx_vlan_tag(desc, skb);
5861
5862 if (skb->pkt_type == PACKET_MULTICAST)
5863 dev->stats.multicast++;
5864
5865 napi_gro_receive(&tp->napi, skb);
5866
5867 u64_stats_update_begin(&tp->rx_stats.syncp);
5868 tp->rx_stats.packets++;
5869 tp->rx_stats.bytes += pkt_size;
5870 u64_stats_update_end(&tp->rx_stats.syncp);
5871 }
5872 release_descriptor:
5873 desc->opts2 = 0;
5874 rtl8169_mark_to_asic(desc);
5875 }
5876
5877 count = cur_rx - tp->cur_rx;
5878 tp->cur_rx = cur_rx;
5879
5880 return count;
5881 }
5882
5883 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5884 {
5885 struct rtl8169_private *tp = dev_instance;
5886 u16 status = RTL_R16(tp, IntrStatus);
5887
5888 if (!tp->irq_enabled || status == 0xffff || !(status & tp->irq_mask))
5889 return IRQ_NONE;
5890
5891 if (unlikely(status & SYSErr)) {
5892 rtl8169_pcierr_interrupt(tp->dev);
5893 goto out;
5894 }
5895
5896 if (status & LinkChg)
5897 phy_mac_interrupt(tp->phydev);
5898
5899 if (unlikely(status & RxFIFOOver &&
5900 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
5901 netif_stop_queue(tp->dev);
5902 /* XXX - Hack alert. See rtl_task(). */
5903 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
5904 }
5905
5906 rtl_irq_disable(tp);
5907 napi_schedule_irqoff(&tp->napi);
5908 out:
5909 rtl_ack_events(tp, status);
5910
5911 return IRQ_HANDLED;
5912 }
5913
5914 static void rtl_task(struct work_struct *work)
5915 {
5916 static const struct {
5917 int bitnr;
5918 void (*action)(struct rtl8169_private *);
5919 } rtl_work[] = {
5920 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
5921 };
5922 struct rtl8169_private *tp =
5923 container_of(work, struct rtl8169_private, wk.work);
5924 struct net_device *dev = tp->dev;
5925 int i;
5926
5927 rtl_lock_work(tp);
5928
5929 if (!netif_running(dev) ||
5930 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
5931 goto out_unlock;
5932
5933 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
5934 bool pending;
5935
5936 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
5937 if (pending)
5938 rtl_work[i].action(tp);
5939 }
5940
5941 out_unlock:
5942 rtl_unlock_work(tp);
5943 }
5944
5945 static int rtl8169_poll(struct napi_struct *napi, int budget)
5946 {
5947 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5948 struct net_device *dev = tp->dev;
5949 int work_done;
5950
5951 work_done = rtl_rx(dev, tp, (u32) budget);
5952
5953 rtl_tx(dev, tp, budget);
5954
5955 if (work_done < budget) {
5956 napi_complete_done(napi, work_done);
5957 rtl_irq_enable(tp);
5958 }
5959
5960 return work_done;
5961 }
5962
5963 static void rtl8169_rx_missed(struct net_device *dev)
5964 {
5965 struct rtl8169_private *tp = netdev_priv(dev);
5966
5967 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5968 return;
5969
5970 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
5971 RTL_W32(tp, RxMissed, 0);
5972 }
5973
5974 static void r8169_phylink_handler(struct net_device *ndev)
5975 {
5976 struct rtl8169_private *tp = netdev_priv(ndev);
5977
5978 if (netif_carrier_ok(ndev)) {
5979 rtl_link_chg_patch(tp);
5980 pm_request_resume(&tp->pci_dev->dev);
5981 } else {
5982 pm_runtime_idle(&tp->pci_dev->dev);
5983 }
5984
5985 if (net_ratelimit())
5986 phy_print_status(tp->phydev);
5987 }
5988
5989 static int r8169_phy_connect(struct rtl8169_private *tp)
5990 {
5991 struct phy_device *phydev = tp->phydev;
5992 phy_interface_t phy_mode;
5993 int ret;
5994
5995 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
5996 PHY_INTERFACE_MODE_MII;
5997
5998 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
5999 phy_mode);
6000 if (ret)
6001 return ret;
6002
6003 if (tp->supports_gmii)
6004 phy_remove_link_mode(phydev,
6005 ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
6006 else
6007 phy_set_max_speed(phydev, SPEED_100);
6008
6009 phy_support_asym_pause(phydev);
6010
6011 phy_attached_info(phydev);
6012
6013 return 0;
6014 }
6015
6016 static void rtl8169_down(struct net_device *dev)
6017 {
6018 struct rtl8169_private *tp = netdev_priv(dev);
6019
6020 phy_stop(tp->phydev);
6021
6022 napi_disable(&tp->napi);
6023 netif_stop_queue(dev);
6024
6025 rtl8169_hw_reset(tp);
6026 /*
6027 * At this point device interrupts can not be enabled in any function,
6028 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6029 * and napi is disabled (rtl8169_poll).
6030 */
6031 rtl8169_rx_missed(dev);
6032
6033 /* Give a racing hard_start_xmit a few cycles to complete. */
6034 synchronize_rcu();
6035
6036 rtl8169_tx_clear(tp);
6037
6038 rtl8169_rx_clear(tp);
6039
6040 rtl_pll_power_down(tp);
6041 }
6042
6043 static int rtl8169_close(struct net_device *dev)
6044 {
6045 struct rtl8169_private *tp = netdev_priv(dev);
6046 struct pci_dev *pdev = tp->pci_dev;
6047
6048 pm_runtime_get_sync(&pdev->dev);
6049
6050 /* Update counters before going down */
6051 rtl8169_update_counters(tp);
6052
6053 rtl_lock_work(tp);
6054 /* Clear all task flags */
6055 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6056
6057 rtl8169_down(dev);
6058 rtl_unlock_work(tp);
6059
6060 cancel_work_sync(&tp->wk.work);
6061
6062 phy_disconnect(tp->phydev);
6063
6064 pci_free_irq(pdev, 0, tp);
6065
6066 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6067 tp->RxPhyAddr);
6068 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6069 tp->TxPhyAddr);
6070 tp->TxDescArray = NULL;
6071 tp->RxDescArray = NULL;
6072
6073 pm_runtime_put_sync(&pdev->dev);
6074
6075 return 0;
6076 }
6077
6078 #ifdef CONFIG_NET_POLL_CONTROLLER
6079 static void rtl8169_netpoll(struct net_device *dev)
6080 {
6081 struct rtl8169_private *tp = netdev_priv(dev);
6082
6083 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6084 }
6085 #endif
6086
6087 static int rtl_open(struct net_device *dev)
6088 {
6089 struct rtl8169_private *tp = netdev_priv(dev);
6090 struct pci_dev *pdev = tp->pci_dev;
6091 int retval = -ENOMEM;
6092
6093 pm_runtime_get_sync(&pdev->dev);
6094
6095 /*
6096 * Rx and Tx descriptors needs 256 bytes alignment.
6097 * dma_alloc_coherent provides more.
6098 */
6099 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6100 &tp->TxPhyAddr, GFP_KERNEL);
6101 if (!tp->TxDescArray)
6102 goto err_pm_runtime_put;
6103
6104 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6105 &tp->RxPhyAddr, GFP_KERNEL);
6106 if (!tp->RxDescArray)
6107 goto err_free_tx_0;
6108
6109 retval = rtl8169_init_ring(tp);
6110 if (retval < 0)
6111 goto err_free_rx_1;
6112
6113 rtl_request_firmware(tp);
6114
6115 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6116 dev->name);
6117 if (retval < 0)
6118 goto err_release_fw_2;
6119
6120 retval = r8169_phy_connect(tp);
6121 if (retval)
6122 goto err_free_irq;
6123
6124 rtl_lock_work(tp);
6125
6126 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6127
6128 napi_enable(&tp->napi);
6129
6130 rtl8169_init_phy(dev, tp);
6131
6132 rtl_pll_power_up(tp);
6133
6134 rtl_hw_start(tp);
6135
6136 if (!rtl8169_init_counter_offsets(tp))
6137 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6138
6139 phy_start(tp->phydev);
6140 netif_start_queue(dev);
6141
6142 rtl_unlock_work(tp);
6143
6144 pm_runtime_put_sync(&pdev->dev);
6145 out:
6146 return retval;
6147
6148 err_free_irq:
6149 pci_free_irq(pdev, 0, tp);
6150 err_release_fw_2:
6151 rtl_release_firmware(tp);
6152 rtl8169_rx_clear(tp);
6153 err_free_rx_1:
6154 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6155 tp->RxPhyAddr);
6156 tp->RxDescArray = NULL;
6157 err_free_tx_0:
6158 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6159 tp->TxPhyAddr);
6160 tp->TxDescArray = NULL;
6161 err_pm_runtime_put:
6162 pm_runtime_put_noidle(&pdev->dev);
6163 goto out;
6164 }
6165
6166 static void
6167 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6168 {
6169 struct rtl8169_private *tp = netdev_priv(dev);
6170 struct pci_dev *pdev = tp->pci_dev;
6171 struct rtl8169_counters *counters = tp->counters;
6172 unsigned int start;
6173
6174 pm_runtime_get_noresume(&pdev->dev);
6175
6176 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6177 rtl8169_rx_missed(dev);
6178
6179 do {
6180 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6181 stats->rx_packets = tp->rx_stats.packets;
6182 stats->rx_bytes = tp->rx_stats.bytes;
6183 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6184
6185 do {
6186 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6187 stats->tx_packets = tp->tx_stats.packets;
6188 stats->tx_bytes = tp->tx_stats.bytes;
6189 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6190
6191 stats->rx_dropped = dev->stats.rx_dropped;
6192 stats->tx_dropped = dev->stats.tx_dropped;
6193 stats->rx_length_errors = dev->stats.rx_length_errors;
6194 stats->rx_errors = dev->stats.rx_errors;
6195 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6196 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6197 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6198 stats->multicast = dev->stats.multicast;
6199
6200 /*
6201 * Fetch additonal counter values missing in stats collected by driver
6202 * from tally counters.
6203 */
6204 if (pm_runtime_active(&pdev->dev))
6205 rtl8169_update_counters(tp);
6206
6207 /*
6208 * Subtract values fetched during initalization.
6209 * See rtl8169_init_counter_offsets for a description why we do that.
6210 */
6211 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6212 le64_to_cpu(tp->tc_offset.tx_errors);
6213 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6214 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6215 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6216 le16_to_cpu(tp->tc_offset.tx_aborted);
6217
6218 pm_runtime_put_noidle(&pdev->dev);
6219 }
6220
6221 static void rtl8169_net_suspend(struct net_device *dev)
6222 {
6223 struct rtl8169_private *tp = netdev_priv(dev);
6224
6225 if (!netif_running(dev))
6226 return;
6227
6228 phy_stop(tp->phydev);
6229 netif_device_detach(dev);
6230
6231 rtl_lock_work(tp);
6232 napi_disable(&tp->napi);
6233 /* Clear all task flags */
6234 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6235
6236 rtl_unlock_work(tp);
6237
6238 rtl_pll_power_down(tp);
6239 }
6240
6241 #ifdef CONFIG_PM
6242
6243 static int rtl8169_suspend(struct device *device)
6244 {
6245 struct net_device *dev = dev_get_drvdata(device);
6246 struct rtl8169_private *tp = netdev_priv(dev);
6247
6248 rtl8169_net_suspend(dev);
6249 clk_disable_unprepare(tp->clk);
6250
6251 return 0;
6252 }
6253
6254 static void __rtl8169_resume(struct net_device *dev)
6255 {
6256 struct rtl8169_private *tp = netdev_priv(dev);
6257
6258 netif_device_attach(dev);
6259
6260 rtl_pll_power_up(tp);
6261 rtl8169_init_phy(dev, tp);
6262
6263 phy_start(tp->phydev);
6264
6265 rtl_lock_work(tp);
6266 napi_enable(&tp->napi);
6267 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6268 rtl_reset_work(tp);
6269 rtl_unlock_work(tp);
6270 }
6271
6272 static int rtl8169_resume(struct device *device)
6273 {
6274 struct net_device *dev = dev_get_drvdata(device);
6275 struct rtl8169_private *tp = netdev_priv(dev);
6276
6277 rtl_rar_set(tp, dev->dev_addr);
6278
6279 clk_prepare_enable(tp->clk);
6280
6281 if (netif_running(dev))
6282 __rtl8169_resume(dev);
6283
6284 return 0;
6285 }
6286
6287 static int rtl8169_runtime_suspend(struct device *device)
6288 {
6289 struct net_device *dev = dev_get_drvdata(device);
6290 struct rtl8169_private *tp = netdev_priv(dev);
6291
6292 if (!tp->TxDescArray)
6293 return 0;
6294
6295 rtl_lock_work(tp);
6296 __rtl8169_set_wol(tp, WAKE_ANY);
6297 rtl_unlock_work(tp);
6298
6299 rtl8169_net_suspend(dev);
6300
6301 /* Update counters before going runtime suspend */
6302 rtl8169_rx_missed(dev);
6303 rtl8169_update_counters(tp);
6304
6305 return 0;
6306 }
6307
6308 static int rtl8169_runtime_resume(struct device *device)
6309 {
6310 struct net_device *dev = dev_get_drvdata(device);
6311 struct rtl8169_private *tp = netdev_priv(dev);
6312
6313 rtl_rar_set(tp, dev->dev_addr);
6314
6315 if (!tp->TxDescArray)
6316 return 0;
6317
6318 rtl_lock_work(tp);
6319 __rtl8169_set_wol(tp, tp->saved_wolopts);
6320 rtl_unlock_work(tp);
6321
6322 __rtl8169_resume(dev);
6323
6324 return 0;
6325 }
6326
6327 static int rtl8169_runtime_idle(struct device *device)
6328 {
6329 struct net_device *dev = dev_get_drvdata(device);
6330
6331 if (!netif_running(dev) || !netif_carrier_ok(dev))
6332 pm_schedule_suspend(device, 10000);
6333
6334 return -EBUSY;
6335 }
6336
6337 static const struct dev_pm_ops rtl8169_pm_ops = {
6338 .suspend = rtl8169_suspend,
6339 .resume = rtl8169_resume,
6340 .freeze = rtl8169_suspend,
6341 .thaw = rtl8169_resume,
6342 .poweroff = rtl8169_suspend,
6343 .restore = rtl8169_resume,
6344 .runtime_suspend = rtl8169_runtime_suspend,
6345 .runtime_resume = rtl8169_runtime_resume,
6346 .runtime_idle = rtl8169_runtime_idle,
6347 };
6348
6349 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
6350
6351 #else /* !CONFIG_PM */
6352
6353 #define RTL8169_PM_OPS NULL
6354
6355 #endif /* !CONFIG_PM */
6356
6357 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6358 {
6359 /* WoL fails with 8168b when the receiver is disabled. */
6360 switch (tp->mac_version) {
6361 case RTL_GIGA_MAC_VER_11:
6362 case RTL_GIGA_MAC_VER_12:
6363 case RTL_GIGA_MAC_VER_17:
6364 pci_clear_master(tp->pci_dev);
6365
6366 RTL_W8(tp, ChipCmd, CmdRxEnb);
6367 /* PCI commit */
6368 RTL_R8(tp, ChipCmd);
6369 break;
6370 default:
6371 break;
6372 }
6373 }
6374
6375 static void rtl_shutdown(struct pci_dev *pdev)
6376 {
6377 struct net_device *dev = pci_get_drvdata(pdev);
6378 struct rtl8169_private *tp = netdev_priv(dev);
6379
6380 rtl8169_net_suspend(dev);
6381
6382 /* Restore original MAC address */
6383 rtl_rar_set(tp, dev->perm_addr);
6384
6385 rtl8169_hw_reset(tp);
6386
6387 if (system_state == SYSTEM_POWER_OFF) {
6388 if (tp->saved_wolopts) {
6389 rtl_wol_suspend_quirk(tp);
6390 rtl_wol_shutdown_quirk(tp);
6391 }
6392
6393 pci_wake_from_d3(pdev, true);
6394 pci_set_power_state(pdev, PCI_D3hot);
6395 }
6396 }
6397
6398 static void rtl_remove_one(struct pci_dev *pdev)
6399 {
6400 struct net_device *dev = pci_get_drvdata(pdev);
6401 struct rtl8169_private *tp = netdev_priv(dev);
6402
6403 if (r8168_check_dash(tp))
6404 rtl8168_driver_stop(tp);
6405
6406 netif_napi_del(&tp->napi);
6407
6408 unregister_netdev(dev);
6409 mdiobus_unregister(tp->phydev->mdio.bus);
6410
6411 rtl_release_firmware(tp);
6412
6413 if (pci_dev_run_wake(pdev))
6414 pm_runtime_get_noresume(&pdev->dev);
6415
6416 /* restore original MAC address */
6417 rtl_rar_set(tp, dev->perm_addr);
6418 }
6419
6420 static const struct net_device_ops rtl_netdev_ops = {
6421 .ndo_open = rtl_open,
6422 .ndo_stop = rtl8169_close,
6423 .ndo_get_stats64 = rtl8169_get_stats64,
6424 .ndo_start_xmit = rtl8169_start_xmit,
6425 .ndo_tx_timeout = rtl8169_tx_timeout,
6426 .ndo_validate_addr = eth_validate_addr,
6427 .ndo_change_mtu = rtl8169_change_mtu,
6428 .ndo_fix_features = rtl8169_fix_features,
6429 .ndo_set_features = rtl8169_set_features,
6430 .ndo_set_mac_address = rtl_set_mac_address,
6431 .ndo_do_ioctl = rtl8169_ioctl,
6432 .ndo_set_rx_mode = rtl_set_rx_mode,
6433 #ifdef CONFIG_NET_POLL_CONTROLLER
6434 .ndo_poll_controller = rtl8169_netpoll,
6435 #endif
6436
6437 };
6438
6439 static void rtl_set_irq_mask(struct rtl8169_private *tp)
6440 {
6441 tp->irq_mask = RTL_EVENT_NAPI | LinkChg;
6442
6443 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6444 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
6445 else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
6446 /* special workaround needed */
6447 tp->irq_mask |= RxFIFOOver;
6448 else
6449 tp->irq_mask |= RxOverflow;
6450 }
6451
6452 static int rtl_alloc_irq(struct rtl8169_private *tp)
6453 {
6454 unsigned int flags;
6455
6456 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
6457 rtl_unlock_config_regs(tp);
6458 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
6459 rtl_lock_config_regs(tp);
6460 flags = PCI_IRQ_LEGACY;
6461 } else {
6462 flags = PCI_IRQ_ALL_TYPES;
6463 }
6464
6465 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
6466 }
6467
6468 static void rtl_read_mac_address(struct rtl8169_private *tp,
6469 u8 mac_addr[ETH_ALEN])
6470 {
6471 /* Get MAC address */
6472 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
6473 u32 value = rtl_eri_read(tp, 0xe0);
6474
6475 mac_addr[0] = (value >> 0) & 0xff;
6476 mac_addr[1] = (value >> 8) & 0xff;
6477 mac_addr[2] = (value >> 16) & 0xff;
6478 mac_addr[3] = (value >> 24) & 0xff;
6479
6480 value = rtl_eri_read(tp, 0xe4);
6481 mac_addr[4] = (value >> 0) & 0xff;
6482 mac_addr[5] = (value >> 8) & 0xff;
6483 }
6484 }
6485
6486 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6487 {
6488 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
6489 }
6490
6491 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6492 {
6493 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6494 }
6495
6496 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
6497 {
6498 struct rtl8169_private *tp = mii_bus->priv;
6499
6500 if (phyaddr > 0)
6501 return -ENODEV;
6502
6503 return rtl_readphy(tp, phyreg);
6504 }
6505
6506 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
6507 int phyreg, u16 val)
6508 {
6509 struct rtl8169_private *tp = mii_bus->priv;
6510
6511 if (phyaddr > 0)
6512 return -ENODEV;
6513
6514 rtl_writephy(tp, phyreg, val);
6515
6516 return 0;
6517 }
6518
6519 static int r8169_mdio_register(struct rtl8169_private *tp)
6520 {
6521 struct pci_dev *pdev = tp->pci_dev;
6522 struct mii_bus *new_bus;
6523 int ret;
6524
6525 new_bus = devm_mdiobus_alloc(&pdev->dev);
6526 if (!new_bus)
6527 return -ENOMEM;
6528
6529 new_bus->name = "r8169";
6530 new_bus->priv = tp;
6531 new_bus->parent = &pdev->dev;
6532 new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
6533 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
6534
6535 new_bus->read = r8169_mdio_read_reg;
6536 new_bus->write = r8169_mdio_write_reg;
6537
6538 ret = mdiobus_register(new_bus);
6539 if (ret)
6540 return ret;
6541
6542 tp->phydev = mdiobus_get_phy(new_bus, 0);
6543 if (!tp->phydev) {
6544 mdiobus_unregister(new_bus);
6545 return -ENODEV;
6546 }
6547
6548 /* PHY will be woken up in rtl_open() */
6549 phy_suspend(tp->phydev);
6550
6551 return 0;
6552 }
6553
6554 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6555 {
6556 u32 data;
6557
6558 tp->ocp_base = OCP_STD_PHY_BASE;
6559
6560 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
6561
6562 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6563 return;
6564
6565 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6566 return;
6567
6568 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6569 msleep(1);
6570 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6571
6572 data = r8168_mac_ocp_read(tp, 0xe8de);
6573 data &= ~(1 << 14);
6574 r8168_mac_ocp_write(tp, 0xe8de, data);
6575
6576 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6577 return;
6578
6579 data = r8168_mac_ocp_read(tp, 0xe8de);
6580 data |= (1 << 15);
6581 r8168_mac_ocp_write(tp, 0xe8de, data);
6582
6583 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
6584 }
6585
6586 static void rtl_hw_initialize(struct rtl8169_private *tp)
6587 {
6588 switch (tp->mac_version) {
6589 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
6590 rtl8168ep_stop_cmac(tp);
6591 /* fall through */
6592 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
6593 rtl_hw_init_8168g(tp);
6594 break;
6595 default:
6596 break;
6597 }
6598 }
6599
6600 static int rtl_jumbo_max(struct rtl8169_private *tp)
6601 {
6602 /* Non-GBit versions don't support jumbo frames */
6603 if (!tp->supports_gmii)
6604 return JUMBO_1K;
6605
6606 switch (tp->mac_version) {
6607 /* RTL8169 */
6608 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
6609 return JUMBO_7K;
6610 /* RTL8168b */
6611 case RTL_GIGA_MAC_VER_11:
6612 case RTL_GIGA_MAC_VER_12:
6613 case RTL_GIGA_MAC_VER_17:
6614 return JUMBO_4K;
6615 /* RTL8168c */
6616 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
6617 return JUMBO_6K;
6618 default:
6619 return JUMBO_9K;
6620 }
6621 }
6622
6623 static void rtl_disable_clk(void *data)
6624 {
6625 clk_disable_unprepare(data);
6626 }
6627
6628 static int rtl_get_ether_clk(struct rtl8169_private *tp)
6629 {
6630 struct device *d = tp_to_dev(tp);
6631 struct clk *clk;
6632 int rc;
6633
6634 clk = devm_clk_get(d, "ether_clk");
6635 if (IS_ERR(clk)) {
6636 rc = PTR_ERR(clk);
6637 if (rc == -ENOENT)
6638 /* clk-core allows NULL (for suspend / resume) */
6639 rc = 0;
6640 else if (rc != -EPROBE_DEFER)
6641 dev_err(d, "failed to get clk: %d\n", rc);
6642 } else {
6643 tp->clk = clk;
6644 rc = clk_prepare_enable(clk);
6645 if (rc)
6646 dev_err(d, "failed to enable clk: %d\n", rc);
6647 else
6648 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
6649 }
6650
6651 return rc;
6652 }
6653
6654 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6655 {
6656 /* align to u16 for is_valid_ether_addr() */
6657 u8 mac_addr[ETH_ALEN] __aligned(2) = {};
6658 struct rtl8169_private *tp;
6659 struct net_device *dev;
6660 int chipset, region, i;
6661 int jumbo_max, rc;
6662
6663 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
6664 if (!dev)
6665 return -ENOMEM;
6666
6667 SET_NETDEV_DEV(dev, &pdev->dev);
6668 dev->netdev_ops = &rtl_netdev_ops;
6669 tp = netdev_priv(dev);
6670 tp->dev = dev;
6671 tp->pci_dev = pdev;
6672 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6673 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
6674
6675 /* Get the *optional* external "ether_clk" used on some boards */
6676 rc = rtl_get_ether_clk(tp);
6677 if (rc)
6678 return rc;
6679
6680 /* Disable ASPM completely as that cause random device stop working
6681 * problems as well as full system hangs for some PCIe devices users.
6682 */
6683 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
6684
6685 /* enable device (incl. PCI PM wakeup and hotplug setup) */
6686 rc = pcim_enable_device(pdev);
6687 if (rc < 0) {
6688 dev_err(&pdev->dev, "enable failure\n");
6689 return rc;
6690 }
6691
6692 if (pcim_set_mwi(pdev) < 0)
6693 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
6694
6695 /* use first MMIO region */
6696 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
6697 if (region < 0) {
6698 dev_err(&pdev->dev, "no MMIO resource found\n");
6699 return -ENODEV;
6700 }
6701
6702 /* check for weird/broken PCI region reporting */
6703 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6704 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
6705 return -ENODEV;
6706 }
6707
6708 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
6709 if (rc < 0) {
6710 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
6711 return rc;
6712 }
6713
6714 tp->mmio_addr = pcim_iomap_table(pdev)[region];
6715
6716 /* Identify chip attached to board */
6717 rtl8169_get_mac_version(tp);
6718 if (tp->mac_version == RTL_GIGA_MAC_NONE)
6719 return -ENODEV;
6720
6721 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
6722
6723 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
6724 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
6725 dev->features |= NETIF_F_HIGHDMA;
6726 } else {
6727 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6728 if (rc < 0) {
6729 dev_err(&pdev->dev, "DMA configuration failed\n");
6730 return rc;
6731 }
6732 }
6733
6734 rtl_init_rxcfg(tp);
6735
6736 rtl8169_irq_mask_and_ack(tp);
6737
6738 rtl_hw_initialize(tp);
6739
6740 rtl_hw_reset(tp);
6741
6742 pci_set_master(pdev);
6743
6744 chipset = tp->mac_version;
6745
6746 rc = rtl_alloc_irq(tp);
6747 if (rc < 0) {
6748 dev_err(&pdev->dev, "Can't allocate interrupt\n");
6749 return rc;
6750 }
6751
6752 mutex_init(&tp->wk.mutex);
6753 INIT_WORK(&tp->wk.work, rtl_task);
6754 u64_stats_init(&tp->rx_stats.syncp);
6755 u64_stats_init(&tp->tx_stats.syncp);
6756
6757 /* get MAC address */
6758 rc = eth_platform_get_mac_address(&pdev->dev, mac_addr);
6759 if (rc)
6760 rtl_read_mac_address(tp, mac_addr);
6761
6762 if (is_valid_ether_addr(mac_addr))
6763 rtl_rar_set(tp, mac_addr);
6764
6765 for (i = 0; i < ETH_ALEN; i++)
6766 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
6767
6768 dev->ethtool_ops = &rtl8169_ethtool_ops;
6769
6770 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
6771
6772 /* don't enable SG, IP_CSUM and TSO by default - it might not work
6773 * properly for all devices */
6774 dev->features |= NETIF_F_RXCSUM |
6775 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
6776
6777 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6778 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
6779 NETIF_F_HW_VLAN_CTAG_RX;
6780 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6781 NETIF_F_HIGHDMA;
6782 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
6783
6784 tp->cp_cmd |= RxChkSum | RxVlan;
6785
6786 /*
6787 * Pretend we are using VLANs; This bypasses a nasty bug where
6788 * Interrupts stop flowing on high load on 8110SCd controllers.
6789 */
6790 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6791 /* Disallow toggling */
6792 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
6793
6794 if (rtl_chip_supports_csum_v2(tp))
6795 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
6796
6797 dev->hw_features |= NETIF_F_RXALL;
6798 dev->hw_features |= NETIF_F_RXFCS;
6799
6800 /* MTU range: 60 - hw-specific max */
6801 dev->min_mtu = ETH_ZLEN;
6802 jumbo_max = rtl_jumbo_max(tp);
6803 dev->max_mtu = jumbo_max;
6804
6805 rtl_set_irq_mask(tp);
6806
6807 tp->fw_name = rtl_chip_infos[chipset].fw_name;
6808
6809 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
6810 &tp->counters_phys_addr,
6811 GFP_KERNEL);
6812 if (!tp->counters)
6813 return -ENOMEM;
6814
6815 pci_set_drvdata(pdev, dev);
6816
6817 rc = r8169_mdio_register(tp);
6818 if (rc)
6819 return rc;
6820
6821 /* chip gets powered up in rtl_open() */
6822 rtl_pll_power_down(tp);
6823
6824 rc = register_netdev(dev);
6825 if (rc)
6826 goto err_mdio_unregister;
6827
6828 netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
6829 rtl_chip_infos[chipset].name, dev->dev_addr,
6830 (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
6831 pci_irq_vector(pdev, 0));
6832
6833 if (jumbo_max > JUMBO_1K)
6834 netif_info(tp, probe, dev,
6835 "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
6836 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
6837 "ok" : "ko");
6838
6839 if (r8168_check_dash(tp))
6840 rtl8168_driver_start(tp);
6841
6842 if (pci_dev_run_wake(pdev))
6843 pm_runtime_put_sync(&pdev->dev);
6844
6845 return 0;
6846
6847 err_mdio_unregister:
6848 mdiobus_unregister(tp->phydev->mdio.bus);
6849 return rc;
6850 }
6851
6852 static struct pci_driver rtl8169_pci_driver = {
6853 .name = MODULENAME,
6854 .id_table = rtl8169_pci_tbl,
6855 .probe = rtl_init_one,
6856 .remove = rtl_remove_one,
6857 .shutdown = rtl_shutdown,
6858 .driver.pm = RTL8169_PM_OPS,
6859 };
6860
6861 module_pci_driver(rtl8169_pci_driver);
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