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r8169: improve DMA handling in rtl_rx
[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / realtek / r8169_main.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 *
5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
7 * Copyright (c) a lot of people too. Please respect their work.
8 *
9 * See MAINTAINERS file for support contact information.
10 */
11
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/pci.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/ethtool.h>
20 #include <linux/phy.h>
21 #include <linux/if_vlan.h>
22 #include <linux/crc32.h>
23 #include <linux/in.h>
24 #include <linux/io.h>
25 #include <linux/ip.h>
26 #include <linux/tcp.h>
27 #include <linux/interrupt.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/prefetch.h>
31 #include <linux/pci-aspm.h>
32 #include <linux/ipv6.h>
33 #include <net/ip6_checksum.h>
34
35 #include "r8169_firmware.h"
36
37 #define MODULENAME "r8169"
38
39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
47 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
48 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
49 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
50 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
51 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
52 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
53 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
54 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
55 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
56 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
57 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
58
59 #define R8169_MSG_DEFAULT \
60 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
61
62 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
63 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
64 #define MC_FILTER_LIMIT 32
65
66 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
67 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
68
69 #define R8169_REGS_SIZE 256
70 #define R8169_RX_BUF_SIZE (SZ_16K - 1)
71 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
72 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
73 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
74 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
75
76 #define RTL_CFG_NO_GBIT 1
77
78 /* write/read MMIO register */
79 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
80 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
81 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
82 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
83 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
84 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
85
86 enum mac_version {
87 /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */
88 RTL_GIGA_MAC_VER_02,
89 RTL_GIGA_MAC_VER_03,
90 RTL_GIGA_MAC_VER_04,
91 RTL_GIGA_MAC_VER_05,
92 RTL_GIGA_MAC_VER_06,
93 RTL_GIGA_MAC_VER_07,
94 RTL_GIGA_MAC_VER_08,
95 RTL_GIGA_MAC_VER_09,
96 RTL_GIGA_MAC_VER_10,
97 RTL_GIGA_MAC_VER_11,
98 RTL_GIGA_MAC_VER_12,
99 RTL_GIGA_MAC_VER_13,
100 RTL_GIGA_MAC_VER_14,
101 RTL_GIGA_MAC_VER_15,
102 RTL_GIGA_MAC_VER_16,
103 RTL_GIGA_MAC_VER_17,
104 RTL_GIGA_MAC_VER_18,
105 RTL_GIGA_MAC_VER_19,
106 RTL_GIGA_MAC_VER_20,
107 RTL_GIGA_MAC_VER_21,
108 RTL_GIGA_MAC_VER_22,
109 RTL_GIGA_MAC_VER_23,
110 RTL_GIGA_MAC_VER_24,
111 RTL_GIGA_MAC_VER_25,
112 RTL_GIGA_MAC_VER_26,
113 RTL_GIGA_MAC_VER_27,
114 RTL_GIGA_MAC_VER_28,
115 RTL_GIGA_MAC_VER_29,
116 RTL_GIGA_MAC_VER_30,
117 RTL_GIGA_MAC_VER_31,
118 RTL_GIGA_MAC_VER_32,
119 RTL_GIGA_MAC_VER_33,
120 RTL_GIGA_MAC_VER_34,
121 RTL_GIGA_MAC_VER_35,
122 RTL_GIGA_MAC_VER_36,
123 RTL_GIGA_MAC_VER_37,
124 RTL_GIGA_MAC_VER_38,
125 RTL_GIGA_MAC_VER_39,
126 RTL_GIGA_MAC_VER_40,
127 RTL_GIGA_MAC_VER_41,
128 RTL_GIGA_MAC_VER_42,
129 RTL_GIGA_MAC_VER_43,
130 RTL_GIGA_MAC_VER_44,
131 RTL_GIGA_MAC_VER_45,
132 RTL_GIGA_MAC_VER_46,
133 RTL_GIGA_MAC_VER_47,
134 RTL_GIGA_MAC_VER_48,
135 RTL_GIGA_MAC_VER_49,
136 RTL_GIGA_MAC_VER_50,
137 RTL_GIGA_MAC_VER_51,
138 RTL_GIGA_MAC_NONE
139 };
140
141 #define JUMBO_1K ETH_DATA_LEN
142 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
143 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
144 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
145 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
146
147 static const struct {
148 const char *name;
149 const char *fw_name;
150 } rtl_chip_infos[] = {
151 /* PCI devices. */
152 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
153 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
154 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
155 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
156 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
157 /* PCI-E devices. */
158 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
159 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
160 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" },
161 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
162 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
163 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
164 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" },
165 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" },
166 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" },
167 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
168 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
169 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
170 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
171 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
172 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
173 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
174 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
175 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
176 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
177 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
178 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
179 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
180 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
181 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
182 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
183 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
184 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
185 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
186 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
187 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
188 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
189 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
190 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
191 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
192 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
193 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3},
194 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2},
195 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 },
196 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
197 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
198 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
199 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
200 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
201 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
202 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
203 };
204
205 static const struct pci_device_id rtl8169_pci_tbl[] = {
206 { PCI_VDEVICE(REALTEK, 0x2502) },
207 { PCI_VDEVICE(REALTEK, 0x2600) },
208 { PCI_VDEVICE(REALTEK, 0x8129) },
209 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
210 { PCI_VDEVICE(REALTEK, 0x8161) },
211 { PCI_VDEVICE(REALTEK, 0x8167) },
212 { PCI_VDEVICE(REALTEK, 0x8168) },
213 { PCI_VDEVICE(NCUBE, 0x8168) },
214 { PCI_VDEVICE(REALTEK, 0x8169) },
215 { PCI_VENDOR_ID_DLINK, 0x4300,
216 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
217 { PCI_VDEVICE(DLINK, 0x4300) },
218 { PCI_VDEVICE(DLINK, 0x4302) },
219 { PCI_VDEVICE(AT, 0xc107) },
220 { PCI_VDEVICE(USR, 0x0116) },
221 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
222 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
223 {}
224 };
225
226 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
227
228 static struct {
229 u32 msg_enable;
230 } debug = { -1 };
231
232 enum rtl_registers {
233 MAC0 = 0, /* Ethernet hardware address. */
234 MAC4 = 4,
235 MAR0 = 8, /* Multicast filter. */
236 CounterAddrLow = 0x10,
237 CounterAddrHigh = 0x14,
238 TxDescStartAddrLow = 0x20,
239 TxDescStartAddrHigh = 0x24,
240 TxHDescStartAddrLow = 0x28,
241 TxHDescStartAddrHigh = 0x2c,
242 FLASH = 0x30,
243 ERSR = 0x36,
244 ChipCmd = 0x37,
245 TxPoll = 0x38,
246 IntrMask = 0x3c,
247 IntrStatus = 0x3e,
248
249 TxConfig = 0x40,
250 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
251 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
252
253 RxConfig = 0x44,
254 #define RX128_INT_EN (1 << 15) /* 8111c and later */
255 #define RX_MULTI_EN (1 << 14) /* 8111c only */
256 #define RXCFG_FIFO_SHIFT 13
257 /* No threshold before first PCI xfer */
258 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
259 #define RX_EARLY_OFF (1 << 11)
260 #define RXCFG_DMA_SHIFT 8
261 /* Unlimited maximum PCI burst. */
262 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
263
264 RxMissed = 0x4c,
265 Cfg9346 = 0x50,
266 Config0 = 0x51,
267 Config1 = 0x52,
268 Config2 = 0x53,
269 #define PME_SIGNAL (1 << 5) /* 8168c and later */
270
271 Config3 = 0x54,
272 Config4 = 0x55,
273 Config5 = 0x56,
274 PHYAR = 0x60,
275 PHYstatus = 0x6c,
276 RxMaxSize = 0xda,
277 CPlusCmd = 0xe0,
278 IntrMitigate = 0xe2,
279
280 #define RTL_COALESCE_MASK 0x0f
281 #define RTL_COALESCE_SHIFT 4
282 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
283 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
284
285 RxDescAddrLow = 0xe4,
286 RxDescAddrHigh = 0xe8,
287 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
288
289 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
290
291 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
292
293 #define TxPacketMax (8064 >> 7)
294 #define EarlySize 0x27
295
296 FuncEvent = 0xf0,
297 FuncEventMask = 0xf4,
298 FuncPresetState = 0xf8,
299 IBCR0 = 0xf8,
300 IBCR2 = 0xf9,
301 IBIMR0 = 0xfa,
302 IBISR0 = 0xfb,
303 FuncForceEvent = 0xfc,
304 };
305
306 enum rtl8168_8101_registers {
307 CSIDR = 0x64,
308 CSIAR = 0x68,
309 #define CSIAR_FLAG 0x80000000
310 #define CSIAR_WRITE_CMD 0x80000000
311 #define CSIAR_BYTE_ENABLE 0x0000f000
312 #define CSIAR_ADDR_MASK 0x00000fff
313 PMCH = 0x6f,
314 EPHYAR = 0x80,
315 #define EPHYAR_FLAG 0x80000000
316 #define EPHYAR_WRITE_CMD 0x80000000
317 #define EPHYAR_REG_MASK 0x1f
318 #define EPHYAR_REG_SHIFT 16
319 #define EPHYAR_DATA_MASK 0xffff
320 DLLPR = 0xd0,
321 #define PFM_EN (1 << 6)
322 #define TX_10M_PS_EN (1 << 7)
323 DBG_REG = 0xd1,
324 #define FIX_NAK_1 (1 << 4)
325 #define FIX_NAK_2 (1 << 3)
326 TWSI = 0xd2,
327 MCU = 0xd3,
328 #define NOW_IS_OOB (1 << 7)
329 #define TX_EMPTY (1 << 5)
330 #define RX_EMPTY (1 << 4)
331 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
332 #define EN_NDP (1 << 3)
333 #define EN_OOB_RESET (1 << 2)
334 #define LINK_LIST_RDY (1 << 1)
335 EFUSEAR = 0xdc,
336 #define EFUSEAR_FLAG 0x80000000
337 #define EFUSEAR_WRITE_CMD 0x80000000
338 #define EFUSEAR_READ_CMD 0x00000000
339 #define EFUSEAR_REG_MASK 0x03ff
340 #define EFUSEAR_REG_SHIFT 8
341 #define EFUSEAR_DATA_MASK 0xff
342 MISC_1 = 0xf2,
343 #define PFM_D3COLD_EN (1 << 6)
344 };
345
346 enum rtl8168_registers {
347 LED_FREQ = 0x1a,
348 EEE_LED = 0x1b,
349 ERIDR = 0x70,
350 ERIAR = 0x74,
351 #define ERIAR_FLAG 0x80000000
352 #define ERIAR_WRITE_CMD 0x80000000
353 #define ERIAR_READ_CMD 0x00000000
354 #define ERIAR_ADDR_BYTE_ALIGN 4
355 #define ERIAR_TYPE_SHIFT 16
356 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
357 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
358 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
359 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
360 #define ERIAR_MASK_SHIFT 12
361 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
362 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
363 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
364 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
365 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
366 EPHY_RXER_NUM = 0x7c,
367 OCPDR = 0xb0, /* OCP GPHY access */
368 #define OCPDR_WRITE_CMD 0x80000000
369 #define OCPDR_READ_CMD 0x00000000
370 #define OCPDR_REG_MASK 0x7f
371 #define OCPDR_GPHY_REG_SHIFT 16
372 #define OCPDR_DATA_MASK 0xffff
373 OCPAR = 0xb4,
374 #define OCPAR_FLAG 0x80000000
375 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
376 #define OCPAR_GPHY_READ_CMD 0x0000f060
377 GPHY_OCP = 0xb8,
378 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
379 MISC = 0xf0, /* 8168e only. */
380 #define TXPLA_RST (1 << 29)
381 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
382 #define PWM_EN (1 << 22)
383 #define RXDV_GATED_EN (1 << 19)
384 #define EARLY_TALLY_EN (1 << 16)
385 };
386
387 enum rtl_register_content {
388 /* InterruptStatusBits */
389 SYSErr = 0x8000,
390 PCSTimeout = 0x4000,
391 SWInt = 0x0100,
392 TxDescUnavail = 0x0080,
393 RxFIFOOver = 0x0040,
394 LinkChg = 0x0020,
395 RxOverflow = 0x0010,
396 TxErr = 0x0008,
397 TxOK = 0x0004,
398 RxErr = 0x0002,
399 RxOK = 0x0001,
400
401 /* RxStatusDesc */
402 RxRWT = (1 << 22),
403 RxRES = (1 << 21),
404 RxRUNT = (1 << 20),
405 RxCRC = (1 << 19),
406
407 /* ChipCmdBits */
408 StopReq = 0x80,
409 CmdReset = 0x10,
410 CmdRxEnb = 0x08,
411 CmdTxEnb = 0x04,
412 RxBufEmpty = 0x01,
413
414 /* TXPoll register p.5 */
415 HPQ = 0x80, /* Poll cmd on the high prio queue */
416 NPQ = 0x40, /* Poll cmd on the low prio queue */
417 FSWInt = 0x01, /* Forced software interrupt */
418
419 /* Cfg9346Bits */
420 Cfg9346_Lock = 0x00,
421 Cfg9346_Unlock = 0xc0,
422
423 /* rx_mode_bits */
424 AcceptErr = 0x20,
425 AcceptRunt = 0x10,
426 AcceptBroadcast = 0x08,
427 AcceptMulticast = 0x04,
428 AcceptMyPhys = 0x02,
429 AcceptAllPhys = 0x01,
430 #define RX_CONFIG_ACCEPT_MASK 0x3f
431
432 /* TxConfigBits */
433 TxInterFrameGapShift = 24,
434 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
435
436 /* Config1 register p.24 */
437 LEDS1 = (1 << 7),
438 LEDS0 = (1 << 6),
439 Speed_down = (1 << 4),
440 MEMMAP = (1 << 3),
441 IOMAP = (1 << 2),
442 VPD = (1 << 1),
443 PMEnable = (1 << 0), /* Power Management Enable */
444
445 /* Config2 register p. 25 */
446 ClkReqEn = (1 << 7), /* Clock Request Enable */
447 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
448 PCI_Clock_66MHz = 0x01,
449 PCI_Clock_33MHz = 0x00,
450
451 /* Config3 register p.25 */
452 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
453 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
454 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
455 Rdy_to_L23 = (1 << 1), /* L23 Enable */
456 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
457
458 /* Config4 register */
459 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
460
461 /* Config5 register p.27 */
462 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
463 MWF = (1 << 5), /* Accept Multicast wakeup frame */
464 UWF = (1 << 4), /* Accept Unicast wakeup frame */
465 Spi_en = (1 << 3),
466 LanWake = (1 << 1), /* LanWake enable/disable */
467 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
468 ASPM_en = (1 << 0), /* ASPM enable */
469
470 /* CPlusCmd p.31 */
471 EnableBist = (1 << 15), // 8168 8101
472 Mac_dbgo_oe = (1 << 14), // 8168 8101
473 Normal_mode = (1 << 13), // unused
474 Force_half_dup = (1 << 12), // 8168 8101
475 Force_rxflow_en = (1 << 11), // 8168 8101
476 Force_txflow_en = (1 << 10), // 8168 8101
477 Cxpl_dbg_sel = (1 << 9), // 8168 8101
478 ASF = (1 << 8), // 8168 8101
479 PktCntrDisable = (1 << 7), // 8168 8101
480 Mac_dbgo_sel = 0x001c, // 8168
481 RxVlan = (1 << 6),
482 RxChkSum = (1 << 5),
483 PCIDAC = (1 << 4),
484 PCIMulRW = (1 << 3),
485 #define INTT_MASK GENMASK(1, 0)
486 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
487
488 /* rtl8169_PHYstatus */
489 TBI_Enable = 0x80,
490 TxFlowCtrl = 0x40,
491 RxFlowCtrl = 0x20,
492 _1000bpsF = 0x10,
493 _100bps = 0x08,
494 _10bps = 0x04,
495 LinkStatus = 0x02,
496 FullDup = 0x01,
497
498 /* ResetCounterCommand */
499 CounterReset = 0x1,
500
501 /* DumpCounterCommand */
502 CounterDump = 0x8,
503
504 /* magic enable v2 */
505 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
506 };
507
508 enum rtl_desc_bit {
509 /* First doubleword. */
510 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
511 RingEnd = (1 << 30), /* End of descriptor ring */
512 FirstFrag = (1 << 29), /* First segment of a packet */
513 LastFrag = (1 << 28), /* Final segment of a packet */
514 };
515
516 /* Generic case. */
517 enum rtl_tx_desc_bit {
518 /* First doubleword. */
519 TD_LSO = (1 << 27), /* Large Send Offload */
520 #define TD_MSS_MAX 0x07ffu /* MSS value */
521
522 /* Second doubleword. */
523 TxVlanTag = (1 << 17), /* Add VLAN tag */
524 };
525
526 /* 8169, 8168b and 810x except 8102e. */
527 enum rtl_tx_desc_bit_0 {
528 /* First doubleword. */
529 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
530 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
531 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
532 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
533 };
534
535 /* 8102e, 8168c and beyond. */
536 enum rtl_tx_desc_bit_1 {
537 /* First doubleword. */
538 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
539 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
540 #define GTTCPHO_SHIFT 18
541 #define GTTCPHO_MAX 0x7f
542
543 /* Second doubleword. */
544 #define TCPHO_SHIFT 18
545 #define TCPHO_MAX 0x3ff
546 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
547 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
548 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
549 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
550 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
551 };
552
553 enum rtl_rx_desc_bit {
554 /* Rx private */
555 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
556 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
557
558 #define RxProtoUDP (PID1)
559 #define RxProtoTCP (PID0)
560 #define RxProtoIP (PID1 | PID0)
561 #define RxProtoMask RxProtoIP
562
563 IPFail = (1 << 16), /* IP checksum failed */
564 UDPFail = (1 << 15), /* UDP/IP checksum failed */
565 TCPFail = (1 << 14), /* TCP/IP checksum failed */
566 RxVlanTag = (1 << 16), /* VLAN tag available */
567 };
568
569 #define RsvdMask 0x3fffc000
570
571 #define RTL_GSO_MAX_SIZE_V1 32000
572 #define RTL_GSO_MAX_SEGS_V1 24
573 #define RTL_GSO_MAX_SIZE_V2 64000
574 #define RTL_GSO_MAX_SEGS_V2 64
575
576 struct TxDesc {
577 __le32 opts1;
578 __le32 opts2;
579 __le64 addr;
580 };
581
582 struct RxDesc {
583 __le32 opts1;
584 __le32 opts2;
585 __le64 addr;
586 };
587
588 struct ring_info {
589 struct sk_buff *skb;
590 u32 len;
591 };
592
593 struct rtl8169_counters {
594 __le64 tx_packets;
595 __le64 rx_packets;
596 __le64 tx_errors;
597 __le32 rx_errors;
598 __le16 rx_missed;
599 __le16 align_errors;
600 __le32 tx_one_collision;
601 __le32 tx_multi_collision;
602 __le64 rx_unicast;
603 __le64 rx_broadcast;
604 __le32 rx_multicast;
605 __le16 tx_aborted;
606 __le16 tx_underun;
607 };
608
609 struct rtl8169_tc_offsets {
610 bool inited;
611 __le64 tx_errors;
612 __le32 tx_multi_collision;
613 __le16 tx_aborted;
614 };
615
616 enum rtl_flag {
617 RTL_FLAG_TASK_ENABLED = 0,
618 RTL_FLAG_TASK_RESET_PENDING,
619 RTL_FLAG_MAX
620 };
621
622 struct rtl8169_stats {
623 u64 packets;
624 u64 bytes;
625 struct u64_stats_sync syncp;
626 };
627
628 struct rtl8169_private {
629 void __iomem *mmio_addr; /* memory map physical address */
630 struct pci_dev *pci_dev;
631 struct net_device *dev;
632 struct phy_device *phydev;
633 struct napi_struct napi;
634 u32 msg_enable;
635 enum mac_version mac_version;
636 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
637 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
638 u32 dirty_tx;
639 struct rtl8169_stats rx_stats;
640 struct rtl8169_stats tx_stats;
641 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
642 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
643 dma_addr_t TxPhyAddr;
644 dma_addr_t RxPhyAddr;
645 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
646 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
647 u16 cp_cmd;
648 u16 irq_mask;
649 struct clk *clk;
650
651 struct {
652 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
653 struct mutex mutex;
654 struct work_struct work;
655 } wk;
656
657 unsigned irq_enabled:1;
658 unsigned supports_gmii:1;
659 unsigned aspm_manageable:1;
660 dma_addr_t counters_phys_addr;
661 struct rtl8169_counters *counters;
662 struct rtl8169_tc_offsets tc_offset;
663 u32 saved_wolopts;
664
665 const char *fw_name;
666 struct rtl_fw *rtl_fw;
667
668 u32 ocp_base;
669 };
670
671 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
672
673 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
674 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
675 module_param_named(debug, debug.msg_enable, int, 0);
676 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
677 MODULE_SOFTDEP("pre: realtek");
678 MODULE_LICENSE("GPL");
679 MODULE_FIRMWARE(FIRMWARE_8168D_1);
680 MODULE_FIRMWARE(FIRMWARE_8168D_2);
681 MODULE_FIRMWARE(FIRMWARE_8168E_1);
682 MODULE_FIRMWARE(FIRMWARE_8168E_2);
683 MODULE_FIRMWARE(FIRMWARE_8168E_3);
684 MODULE_FIRMWARE(FIRMWARE_8105E_1);
685 MODULE_FIRMWARE(FIRMWARE_8168F_1);
686 MODULE_FIRMWARE(FIRMWARE_8168F_2);
687 MODULE_FIRMWARE(FIRMWARE_8402_1);
688 MODULE_FIRMWARE(FIRMWARE_8411_1);
689 MODULE_FIRMWARE(FIRMWARE_8411_2);
690 MODULE_FIRMWARE(FIRMWARE_8106E_1);
691 MODULE_FIRMWARE(FIRMWARE_8106E_2);
692 MODULE_FIRMWARE(FIRMWARE_8168G_2);
693 MODULE_FIRMWARE(FIRMWARE_8168G_3);
694 MODULE_FIRMWARE(FIRMWARE_8168H_1);
695 MODULE_FIRMWARE(FIRMWARE_8168H_2);
696 MODULE_FIRMWARE(FIRMWARE_8107E_1);
697 MODULE_FIRMWARE(FIRMWARE_8107E_2);
698
699 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
700 {
701 return &tp->pci_dev->dev;
702 }
703
704 static void rtl_lock_work(struct rtl8169_private *tp)
705 {
706 mutex_lock(&tp->wk.mutex);
707 }
708
709 static void rtl_unlock_work(struct rtl8169_private *tp)
710 {
711 mutex_unlock(&tp->wk.mutex);
712 }
713
714 static void rtl_lock_config_regs(struct rtl8169_private *tp)
715 {
716 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
717 }
718
719 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
720 {
721 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
722 }
723
724 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
725 {
726 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
727 PCI_EXP_DEVCTL_READRQ, force);
728 }
729
730 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
731 {
732 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
733 tp->mac_version != RTL_GIGA_MAC_VER_39;
734 }
735
736 static bool rtl_supports_eee(struct rtl8169_private *tp)
737 {
738 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
739 tp->mac_version != RTL_GIGA_MAC_VER_37 &&
740 tp->mac_version != RTL_GIGA_MAC_VER_39;
741 }
742
743 struct rtl_cond {
744 bool (*check)(struct rtl8169_private *);
745 const char *msg;
746 };
747
748 static void rtl_udelay(unsigned int d)
749 {
750 udelay(d);
751 }
752
753 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
754 void (*delay)(unsigned int), unsigned int d, int n,
755 bool high)
756 {
757 int i;
758
759 for (i = 0; i < n; i++) {
760 if (c->check(tp) == high)
761 return true;
762 delay(d);
763 }
764 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
765 c->msg, !high, n, d);
766 return false;
767 }
768
769 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
770 const struct rtl_cond *c,
771 unsigned int d, int n)
772 {
773 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
774 }
775
776 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
777 const struct rtl_cond *c,
778 unsigned int d, int n)
779 {
780 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
781 }
782
783 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
784 const struct rtl_cond *c,
785 unsigned int d, int n)
786 {
787 return rtl_loop_wait(tp, c, msleep, d, n, true);
788 }
789
790 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
791 const struct rtl_cond *c,
792 unsigned int d, int n)
793 {
794 return rtl_loop_wait(tp, c, msleep, d, n, false);
795 }
796
797 #define DECLARE_RTL_COND(name) \
798 static bool name ## _check(struct rtl8169_private *); \
799 \
800 static const struct rtl_cond name = { \
801 .check = name ## _check, \
802 .msg = #name \
803 }; \
804 \
805 static bool name ## _check(struct rtl8169_private *tp)
806
807 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
808 {
809 if (reg & 0xffff0001) {
810 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
811 return true;
812 }
813 return false;
814 }
815
816 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
817 {
818 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
819 }
820
821 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
822 {
823 if (rtl_ocp_reg_failure(tp, reg))
824 return;
825
826 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
827
828 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
829 }
830
831 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
832 {
833 if (rtl_ocp_reg_failure(tp, reg))
834 return 0;
835
836 RTL_W32(tp, GPHY_OCP, reg << 15);
837
838 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
839 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
840 }
841
842 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
843 {
844 if (rtl_ocp_reg_failure(tp, reg))
845 return;
846
847 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
848 }
849
850 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
851 {
852 if (rtl_ocp_reg_failure(tp, reg))
853 return 0;
854
855 RTL_W32(tp, OCPDR, reg << 15);
856
857 return RTL_R32(tp, OCPDR);
858 }
859
860 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
861 u16 set)
862 {
863 u16 data = r8168_mac_ocp_read(tp, reg);
864
865 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
866 }
867
868 #define OCP_STD_PHY_BASE 0xa400
869
870 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
871 {
872 if (reg == 0x1f) {
873 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
874 return;
875 }
876
877 if (tp->ocp_base != OCP_STD_PHY_BASE)
878 reg -= 0x10;
879
880 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
881 }
882
883 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
884 {
885 if (tp->ocp_base != OCP_STD_PHY_BASE)
886 reg -= 0x10;
887
888 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
889 }
890
891 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
892 {
893 if (reg == 0x1f) {
894 tp->ocp_base = value << 4;
895 return;
896 }
897
898 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
899 }
900
901 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
902 {
903 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
904 }
905
906 DECLARE_RTL_COND(rtl_phyar_cond)
907 {
908 return RTL_R32(tp, PHYAR) & 0x80000000;
909 }
910
911 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
912 {
913 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
914
915 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
916 /*
917 * According to hardware specs a 20us delay is required after write
918 * complete indication, but before sending next command.
919 */
920 udelay(20);
921 }
922
923 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
924 {
925 int value;
926
927 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
928
929 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
930 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
931
932 /*
933 * According to hardware specs a 20us delay is required after read
934 * complete indication, but before sending next command.
935 */
936 udelay(20);
937
938 return value;
939 }
940
941 DECLARE_RTL_COND(rtl_ocpar_cond)
942 {
943 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
944 }
945
946 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
947 {
948 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
949 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
950 RTL_W32(tp, EPHY_RXER_NUM, 0);
951
952 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
953 }
954
955 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
956 {
957 r8168dp_1_mdio_access(tp, reg,
958 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
959 }
960
961 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
962 {
963 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
964
965 mdelay(1);
966 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
967 RTL_W32(tp, EPHY_RXER_NUM, 0);
968
969 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
970 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
971 }
972
973 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
974
975 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
976 {
977 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
978 }
979
980 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
981 {
982 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
983 }
984
985 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
986 {
987 r8168dp_2_mdio_start(tp);
988
989 r8169_mdio_write(tp, reg, value);
990
991 r8168dp_2_mdio_stop(tp);
992 }
993
994 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
995 {
996 int value;
997
998 r8168dp_2_mdio_start(tp);
999
1000 value = r8169_mdio_read(tp, reg);
1001
1002 r8168dp_2_mdio_stop(tp);
1003
1004 return value;
1005 }
1006
1007 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1008 {
1009 switch (tp->mac_version) {
1010 case RTL_GIGA_MAC_VER_27:
1011 r8168dp_1_mdio_write(tp, location, val);
1012 break;
1013 case RTL_GIGA_MAC_VER_28:
1014 case RTL_GIGA_MAC_VER_31:
1015 r8168dp_2_mdio_write(tp, location, val);
1016 break;
1017 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1018 r8168g_mdio_write(tp, location, val);
1019 break;
1020 default:
1021 r8169_mdio_write(tp, location, val);
1022 break;
1023 }
1024 }
1025
1026 static int rtl_readphy(struct rtl8169_private *tp, int location)
1027 {
1028 switch (tp->mac_version) {
1029 case RTL_GIGA_MAC_VER_27:
1030 return r8168dp_1_mdio_read(tp, location);
1031 case RTL_GIGA_MAC_VER_28:
1032 case RTL_GIGA_MAC_VER_31:
1033 return r8168dp_2_mdio_read(tp, location);
1034 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1035 return r8168g_mdio_read(tp, location);
1036 default:
1037 return r8169_mdio_read(tp, location);
1038 }
1039 }
1040
1041 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1042 {
1043 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1044 }
1045
1046 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1047 {
1048 int val;
1049
1050 val = rtl_readphy(tp, reg_addr);
1051 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1052 }
1053
1054 DECLARE_RTL_COND(rtl_ephyar_cond)
1055 {
1056 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1057 }
1058
1059 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1060 {
1061 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1062 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1063
1064 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1065
1066 udelay(10);
1067 }
1068
1069 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1070 {
1071 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1072
1073 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1074 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1075 }
1076
1077 DECLARE_RTL_COND(rtl_eriar_cond)
1078 {
1079 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1080 }
1081
1082 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1083 u32 val, int type)
1084 {
1085 BUG_ON((addr & 3) || (mask == 0));
1086 RTL_W32(tp, ERIDR, val);
1087 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1088
1089 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1090 }
1091
1092 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1093 u32 val)
1094 {
1095 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1096 }
1097
1098 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1099 {
1100 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1101
1102 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1103 RTL_R32(tp, ERIDR) : ~0;
1104 }
1105
1106 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1107 {
1108 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1109 }
1110
1111 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1112 u32 m)
1113 {
1114 u32 val;
1115
1116 val = rtl_eri_read(tp, addr);
1117 rtl_eri_write(tp, addr, mask, (val & ~m) | p);
1118 }
1119
1120 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,
1121 u32 p)
1122 {
1123 rtl_w0w1_eri(tp, addr, mask, p, 0);
1124 }
1125
1126 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
1127 u32 m)
1128 {
1129 rtl_w0w1_eri(tp, addr, mask, 0, m);
1130 }
1131
1132 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1133 {
1134 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1135 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1136 RTL_R32(tp, OCPDR) : ~0;
1137 }
1138
1139 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1140 {
1141 return _rtl_eri_read(tp, reg, ERIAR_OOB);
1142 }
1143
1144 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1145 u32 data)
1146 {
1147 RTL_W32(tp, OCPDR, data);
1148 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1149 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1150 }
1151
1152 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1153 u32 data)
1154 {
1155 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1156 data, ERIAR_OOB);
1157 }
1158
1159 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1160 {
1161 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1162
1163 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1164 }
1165
1166 #define OOB_CMD_RESET 0x00
1167 #define OOB_CMD_DRIVER_START 0x05
1168 #define OOB_CMD_DRIVER_STOP 0x06
1169
1170 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1171 {
1172 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1173 }
1174
1175 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1176 {
1177 u16 reg;
1178
1179 reg = rtl8168_get_ocp_reg(tp);
1180
1181 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1182 }
1183
1184 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1185 {
1186 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1187 }
1188
1189 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1190 {
1191 return RTL_R8(tp, IBISR0) & 0x20;
1192 }
1193
1194 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1195 {
1196 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1197 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1198 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1199 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1200 }
1201
1202 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1203 {
1204 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1205 rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1206 }
1207
1208 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1209 {
1210 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1211 r8168ep_ocp_write(tp, 0x01, 0x30,
1212 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1213 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1214 }
1215
1216 static void rtl8168_driver_start(struct rtl8169_private *tp)
1217 {
1218 switch (tp->mac_version) {
1219 case RTL_GIGA_MAC_VER_27:
1220 case RTL_GIGA_MAC_VER_28:
1221 case RTL_GIGA_MAC_VER_31:
1222 rtl8168dp_driver_start(tp);
1223 break;
1224 case RTL_GIGA_MAC_VER_49:
1225 case RTL_GIGA_MAC_VER_50:
1226 case RTL_GIGA_MAC_VER_51:
1227 rtl8168ep_driver_start(tp);
1228 break;
1229 default:
1230 BUG();
1231 break;
1232 }
1233 }
1234
1235 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1236 {
1237 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1238 rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1239 }
1240
1241 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1242 {
1243 rtl8168ep_stop_cmac(tp);
1244 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1245 r8168ep_ocp_write(tp, 0x01, 0x30,
1246 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1247 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1248 }
1249
1250 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1251 {
1252 switch (tp->mac_version) {
1253 case RTL_GIGA_MAC_VER_27:
1254 case RTL_GIGA_MAC_VER_28:
1255 case RTL_GIGA_MAC_VER_31:
1256 rtl8168dp_driver_stop(tp);
1257 break;
1258 case RTL_GIGA_MAC_VER_49:
1259 case RTL_GIGA_MAC_VER_50:
1260 case RTL_GIGA_MAC_VER_51:
1261 rtl8168ep_driver_stop(tp);
1262 break;
1263 default:
1264 BUG();
1265 break;
1266 }
1267 }
1268
1269 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1270 {
1271 u16 reg = rtl8168_get_ocp_reg(tp);
1272
1273 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1274 }
1275
1276 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1277 {
1278 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1279 }
1280
1281 static bool r8168_check_dash(struct rtl8169_private *tp)
1282 {
1283 switch (tp->mac_version) {
1284 case RTL_GIGA_MAC_VER_27:
1285 case RTL_GIGA_MAC_VER_28:
1286 case RTL_GIGA_MAC_VER_31:
1287 return r8168dp_check_dash(tp);
1288 case RTL_GIGA_MAC_VER_49:
1289 case RTL_GIGA_MAC_VER_50:
1290 case RTL_GIGA_MAC_VER_51:
1291 return r8168ep_check_dash(tp);
1292 default:
1293 return false;
1294 }
1295 }
1296
1297 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1298 {
1299 rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1300 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1301 }
1302
1303 DECLARE_RTL_COND(rtl_efusear_cond)
1304 {
1305 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1306 }
1307
1308 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1309 {
1310 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1311
1312 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1313 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1314 }
1315
1316 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1317 {
1318 RTL_W16(tp, IntrStatus, bits);
1319 }
1320
1321 static void rtl_irq_disable(struct rtl8169_private *tp)
1322 {
1323 RTL_W16(tp, IntrMask, 0);
1324 tp->irq_enabled = 0;
1325 }
1326
1327 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1328 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1329 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1330
1331 static void rtl_irq_enable(struct rtl8169_private *tp)
1332 {
1333 tp->irq_enabled = 1;
1334 RTL_W16(tp, IntrMask, tp->irq_mask);
1335 }
1336
1337 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1338 {
1339 rtl_irq_disable(tp);
1340 rtl_ack_events(tp, 0xffff);
1341 /* PCI commit */
1342 RTL_R8(tp, ChipCmd);
1343 }
1344
1345 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1346 {
1347 struct net_device *dev = tp->dev;
1348 struct phy_device *phydev = tp->phydev;
1349
1350 if (!netif_running(dev))
1351 return;
1352
1353 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1354 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1355 if (phydev->speed == SPEED_1000) {
1356 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1357 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1358 } else if (phydev->speed == SPEED_100) {
1359 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1360 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1361 } else {
1362 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1363 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1364 }
1365 rtl_reset_packet_filter(tp);
1366 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1367 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1368 if (phydev->speed == SPEED_1000) {
1369 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1370 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1371 } else {
1372 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1373 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1374 }
1375 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1376 if (phydev->speed == SPEED_10) {
1377 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1378 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1379 } else {
1380 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1381 }
1382 }
1383 }
1384
1385 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1386
1387 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1388 {
1389 struct rtl8169_private *tp = netdev_priv(dev);
1390
1391 rtl_lock_work(tp);
1392 wol->supported = WAKE_ANY;
1393 wol->wolopts = tp->saved_wolopts;
1394 rtl_unlock_work(tp);
1395 }
1396
1397 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1398 {
1399 unsigned int i, tmp;
1400 static const struct {
1401 u32 opt;
1402 u16 reg;
1403 u8 mask;
1404 } cfg[] = {
1405 { WAKE_PHY, Config3, LinkUp },
1406 { WAKE_UCAST, Config5, UWF },
1407 { WAKE_BCAST, Config5, BWF },
1408 { WAKE_MCAST, Config5, MWF },
1409 { WAKE_ANY, Config5, LanWake },
1410 { WAKE_MAGIC, Config3, MagicPacket }
1411 };
1412 u8 options;
1413
1414 rtl_unlock_config_regs(tp);
1415
1416 if (rtl_is_8168evl_up(tp)) {
1417 tmp = ARRAY_SIZE(cfg) - 1;
1418 if (wolopts & WAKE_MAGIC)
1419 rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
1420 MagicPacket_v2);
1421 else
1422 rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
1423 MagicPacket_v2);
1424 } else {
1425 tmp = ARRAY_SIZE(cfg);
1426 }
1427
1428 for (i = 0; i < tmp; i++) {
1429 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1430 if (wolopts & cfg[i].opt)
1431 options |= cfg[i].mask;
1432 RTL_W8(tp, cfg[i].reg, options);
1433 }
1434
1435 switch (tp->mac_version) {
1436 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1437 options = RTL_R8(tp, Config1) & ~PMEnable;
1438 if (wolopts)
1439 options |= PMEnable;
1440 RTL_W8(tp, Config1, options);
1441 break;
1442 case RTL_GIGA_MAC_VER_34:
1443 case RTL_GIGA_MAC_VER_37:
1444 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_51:
1445 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1446 if (wolopts)
1447 options |= PME_SIGNAL;
1448 RTL_W8(tp, Config2, options);
1449 break;
1450 default:
1451 break;
1452 }
1453
1454 rtl_lock_config_regs(tp);
1455
1456 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1457 }
1458
1459 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1460 {
1461 struct rtl8169_private *tp = netdev_priv(dev);
1462 struct device *d = tp_to_dev(tp);
1463
1464 if (wol->wolopts & ~WAKE_ANY)
1465 return -EINVAL;
1466
1467 pm_runtime_get_noresume(d);
1468
1469 rtl_lock_work(tp);
1470
1471 tp->saved_wolopts = wol->wolopts;
1472
1473 if (pm_runtime_active(d))
1474 __rtl8169_set_wol(tp, tp->saved_wolopts);
1475
1476 rtl_unlock_work(tp);
1477
1478 pm_runtime_put_noidle(d);
1479
1480 return 0;
1481 }
1482
1483 static void rtl8169_get_drvinfo(struct net_device *dev,
1484 struct ethtool_drvinfo *info)
1485 {
1486 struct rtl8169_private *tp = netdev_priv(dev);
1487 struct rtl_fw *rtl_fw = tp->rtl_fw;
1488
1489 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1490 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1491 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1492 if (rtl_fw)
1493 strlcpy(info->fw_version, rtl_fw->version,
1494 sizeof(info->fw_version));
1495 }
1496
1497 static int rtl8169_get_regs_len(struct net_device *dev)
1498 {
1499 return R8169_REGS_SIZE;
1500 }
1501
1502 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1503 netdev_features_t features)
1504 {
1505 struct rtl8169_private *tp = netdev_priv(dev);
1506
1507 if (dev->mtu > TD_MSS_MAX)
1508 features &= ~NETIF_F_ALL_TSO;
1509
1510 if (dev->mtu > JUMBO_1K &&
1511 tp->mac_version > RTL_GIGA_MAC_VER_06)
1512 features &= ~NETIF_F_IP_CSUM;
1513
1514 return features;
1515 }
1516
1517 static int rtl8169_set_features(struct net_device *dev,
1518 netdev_features_t features)
1519 {
1520 struct rtl8169_private *tp = netdev_priv(dev);
1521 u32 rx_config;
1522
1523 rtl_lock_work(tp);
1524
1525 rx_config = RTL_R32(tp, RxConfig);
1526 if (features & NETIF_F_RXALL)
1527 rx_config |= (AcceptErr | AcceptRunt);
1528 else
1529 rx_config &= ~(AcceptErr | AcceptRunt);
1530
1531 RTL_W32(tp, RxConfig, rx_config);
1532
1533 if (features & NETIF_F_RXCSUM)
1534 tp->cp_cmd |= RxChkSum;
1535 else
1536 tp->cp_cmd &= ~RxChkSum;
1537
1538 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1539 tp->cp_cmd |= RxVlan;
1540 else
1541 tp->cp_cmd &= ~RxVlan;
1542
1543 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1544 RTL_R16(tp, CPlusCmd);
1545
1546 rtl_unlock_work(tp);
1547
1548 return 0;
1549 }
1550
1551 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1552 {
1553 return (skb_vlan_tag_present(skb)) ?
1554 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1555 }
1556
1557 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1558 {
1559 u32 opts2 = le32_to_cpu(desc->opts2);
1560
1561 if (opts2 & RxVlanTag)
1562 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1563 }
1564
1565 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1566 void *p)
1567 {
1568 struct rtl8169_private *tp = netdev_priv(dev);
1569 u32 __iomem *data = tp->mmio_addr;
1570 u32 *dw = p;
1571 int i;
1572
1573 rtl_lock_work(tp);
1574 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1575 memcpy_fromio(dw++, data++, 4);
1576 rtl_unlock_work(tp);
1577 }
1578
1579 static u32 rtl8169_get_msglevel(struct net_device *dev)
1580 {
1581 struct rtl8169_private *tp = netdev_priv(dev);
1582
1583 return tp->msg_enable;
1584 }
1585
1586 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1587 {
1588 struct rtl8169_private *tp = netdev_priv(dev);
1589
1590 tp->msg_enable = value;
1591 }
1592
1593 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1594 "tx_packets",
1595 "rx_packets",
1596 "tx_errors",
1597 "rx_errors",
1598 "rx_missed",
1599 "align_errors",
1600 "tx_single_collisions",
1601 "tx_multi_collisions",
1602 "unicast",
1603 "broadcast",
1604 "multicast",
1605 "tx_aborted",
1606 "tx_underrun",
1607 };
1608
1609 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1610 {
1611 switch (sset) {
1612 case ETH_SS_STATS:
1613 return ARRAY_SIZE(rtl8169_gstrings);
1614 default:
1615 return -EOPNOTSUPP;
1616 }
1617 }
1618
1619 DECLARE_RTL_COND(rtl_counters_cond)
1620 {
1621 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1622 }
1623
1624 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1625 {
1626 dma_addr_t paddr = tp->counters_phys_addr;
1627 u32 cmd;
1628
1629 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1630 RTL_R32(tp, CounterAddrHigh);
1631 cmd = (u64)paddr & DMA_BIT_MASK(32);
1632 RTL_W32(tp, CounterAddrLow, cmd);
1633 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1634
1635 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1636 }
1637
1638 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1639 {
1640 /*
1641 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1642 * tally counters.
1643 */
1644 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1645 return true;
1646
1647 return rtl8169_do_counters(tp, CounterReset);
1648 }
1649
1650 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1651 {
1652 u8 val = RTL_R8(tp, ChipCmd);
1653
1654 /*
1655 * Some chips are unable to dump tally counters when the receiver
1656 * is disabled. If 0xff chip may be in a PCI power-save state.
1657 */
1658 if (!(val & CmdRxEnb) || val == 0xff)
1659 return true;
1660
1661 return rtl8169_do_counters(tp, CounterDump);
1662 }
1663
1664 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1665 {
1666 struct rtl8169_counters *counters = tp->counters;
1667 bool ret = false;
1668
1669 /*
1670 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1671 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1672 * reset by a power cycle, while the counter values collected by the
1673 * driver are reset at every driver unload/load cycle.
1674 *
1675 * To make sure the HW values returned by @get_stats64 match the SW
1676 * values, we collect the initial values at first open(*) and use them
1677 * as offsets to normalize the values returned by @get_stats64.
1678 *
1679 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1680 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1681 * set at open time by rtl_hw_start.
1682 */
1683
1684 if (tp->tc_offset.inited)
1685 return true;
1686
1687 /* If both, reset and update fail, propagate to caller. */
1688 if (rtl8169_reset_counters(tp))
1689 ret = true;
1690
1691 if (rtl8169_update_counters(tp))
1692 ret = true;
1693
1694 tp->tc_offset.tx_errors = counters->tx_errors;
1695 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1696 tp->tc_offset.tx_aborted = counters->tx_aborted;
1697 tp->tc_offset.inited = true;
1698
1699 return ret;
1700 }
1701
1702 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1703 struct ethtool_stats *stats, u64 *data)
1704 {
1705 struct rtl8169_private *tp = netdev_priv(dev);
1706 struct device *d = tp_to_dev(tp);
1707 struct rtl8169_counters *counters = tp->counters;
1708
1709 ASSERT_RTNL();
1710
1711 pm_runtime_get_noresume(d);
1712
1713 if (pm_runtime_active(d))
1714 rtl8169_update_counters(tp);
1715
1716 pm_runtime_put_noidle(d);
1717
1718 data[0] = le64_to_cpu(counters->tx_packets);
1719 data[1] = le64_to_cpu(counters->rx_packets);
1720 data[2] = le64_to_cpu(counters->tx_errors);
1721 data[3] = le32_to_cpu(counters->rx_errors);
1722 data[4] = le16_to_cpu(counters->rx_missed);
1723 data[5] = le16_to_cpu(counters->align_errors);
1724 data[6] = le32_to_cpu(counters->tx_one_collision);
1725 data[7] = le32_to_cpu(counters->tx_multi_collision);
1726 data[8] = le64_to_cpu(counters->rx_unicast);
1727 data[9] = le64_to_cpu(counters->rx_broadcast);
1728 data[10] = le32_to_cpu(counters->rx_multicast);
1729 data[11] = le16_to_cpu(counters->tx_aborted);
1730 data[12] = le16_to_cpu(counters->tx_underun);
1731 }
1732
1733 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1734 {
1735 switch(stringset) {
1736 case ETH_SS_STATS:
1737 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1738 break;
1739 }
1740 }
1741
1742 /*
1743 * Interrupt coalescing
1744 *
1745 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1746 * > 8169, 8168 and 810x line of chipsets
1747 *
1748 * 8169, 8168, and 8136(810x) serial chipsets support it.
1749 *
1750 * > 2 - the Tx timer unit at gigabit speed
1751 *
1752 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1753 * (0xe0) bit 1 and bit 0.
1754 *
1755 * For 8169
1756 * bit[1:0] \ speed 1000M 100M 10M
1757 * 0 0 320ns 2.56us 40.96us
1758 * 0 1 2.56us 20.48us 327.7us
1759 * 1 0 5.12us 40.96us 655.4us
1760 * 1 1 10.24us 81.92us 1.31ms
1761 *
1762 * For the other
1763 * bit[1:0] \ speed 1000M 100M 10M
1764 * 0 0 5us 2.56us 40.96us
1765 * 0 1 40us 20.48us 327.7us
1766 * 1 0 80us 40.96us 655.4us
1767 * 1 1 160us 81.92us 1.31ms
1768 */
1769
1770 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1771 struct rtl_coalesce_scale {
1772 /* Rx / Tx */
1773 u32 nsecs[2];
1774 };
1775
1776 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1777 struct rtl_coalesce_info {
1778 u32 speed;
1779 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
1780 };
1781
1782 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1783 #define rxtx_x1822(r, t) { \
1784 {{(r), (t)}}, \
1785 {{(r)*8, (t)*8}}, \
1786 {{(r)*8*2, (t)*8*2}}, \
1787 {{(r)*8*2*2, (t)*8*2*2}}, \
1788 }
1789 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1790 /* speed delays: rx00 tx00 */
1791 { SPEED_10, rxtx_x1822(40960, 40960) },
1792 { SPEED_100, rxtx_x1822( 2560, 2560) },
1793 { SPEED_1000, rxtx_x1822( 320, 320) },
1794 { 0 },
1795 };
1796
1797 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1798 /* speed delays: rx00 tx00 */
1799 { SPEED_10, rxtx_x1822(40960, 40960) },
1800 { SPEED_100, rxtx_x1822( 2560, 2560) },
1801 { SPEED_1000, rxtx_x1822( 5000, 5000) },
1802 { 0 },
1803 };
1804 #undef rxtx_x1822
1805
1806 /* get rx/tx scale vector corresponding to current speed */
1807 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1808 {
1809 struct rtl8169_private *tp = netdev_priv(dev);
1810 const struct rtl_coalesce_info *ci;
1811
1812 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1813 ci = rtl_coalesce_info_8169;
1814 else
1815 ci = rtl_coalesce_info_8168_8136;
1816
1817 for (; ci->speed; ci++) {
1818 if (tp->phydev->speed == ci->speed)
1819 return ci;
1820 }
1821
1822 return ERR_PTR(-ELNRNG);
1823 }
1824
1825 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1826 {
1827 struct rtl8169_private *tp = netdev_priv(dev);
1828 const struct rtl_coalesce_info *ci;
1829 const struct rtl_coalesce_scale *scale;
1830 struct {
1831 u32 *max_frames;
1832 u32 *usecs;
1833 } coal_settings [] = {
1834 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1835 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1836 }, *p = coal_settings;
1837 int i;
1838 u16 w;
1839
1840 memset(ec, 0, sizeof(*ec));
1841
1842 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1843 ci = rtl_coalesce_info(dev);
1844 if (IS_ERR(ci))
1845 return PTR_ERR(ci);
1846
1847 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1848
1849 /* read IntrMitigate and adjust according to scale */
1850 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1851 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1852 w >>= RTL_COALESCE_SHIFT;
1853 *p->usecs = w & RTL_COALESCE_MASK;
1854 }
1855
1856 for (i = 0; i < 2; i++) {
1857 p = coal_settings + i;
1858 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1859
1860 /*
1861 * ethtool_coalesce says it is illegal to set both usecs and
1862 * max_frames to 0.
1863 */
1864 if (!*p->usecs && !*p->max_frames)
1865 *p->max_frames = 1;
1866 }
1867
1868 return 0;
1869 }
1870
1871 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1872 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1873 struct net_device *dev, u32 nsec, u16 *cp01)
1874 {
1875 const struct rtl_coalesce_info *ci;
1876 u16 i;
1877
1878 ci = rtl_coalesce_info(dev);
1879 if (IS_ERR(ci))
1880 return ERR_CAST(ci);
1881
1882 for (i = 0; i < 4; i++) {
1883 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1884 ci->scalev[i].nsecs[1]);
1885 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1886 *cp01 = i;
1887 return &ci->scalev[i];
1888 }
1889 }
1890
1891 return ERR_PTR(-EINVAL);
1892 }
1893
1894 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1895 {
1896 struct rtl8169_private *tp = netdev_priv(dev);
1897 const struct rtl_coalesce_scale *scale;
1898 struct {
1899 u32 frames;
1900 u32 usecs;
1901 } coal_settings [] = {
1902 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1903 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1904 }, *p = coal_settings;
1905 u16 w = 0, cp01;
1906 int i;
1907
1908 scale = rtl_coalesce_choose_scale(dev,
1909 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1910 if (IS_ERR(scale))
1911 return PTR_ERR(scale);
1912
1913 for (i = 0; i < 2; i++, p++) {
1914 u32 units;
1915
1916 /*
1917 * accept max_frames=1 we returned in rtl_get_coalesce.
1918 * accept it not only when usecs=0 because of e.g. the following scenario:
1919 *
1920 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1921 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1922 * - then user does `ethtool -C eth0 rx-usecs 100`
1923 *
1924 * since ethtool sends to kernel whole ethtool_coalesce
1925 * settings, if we do not handle rx_usecs=!0, rx_frames=1
1926 * we'll reject it below in `frames % 4 != 0`.
1927 */
1928 if (p->frames == 1) {
1929 p->frames = 0;
1930 }
1931
1932 units = p->usecs * 1000 / scale->nsecs[i];
1933 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
1934 return -EINVAL;
1935
1936 w <<= RTL_COALESCE_SHIFT;
1937 w |= units;
1938 w <<= RTL_COALESCE_SHIFT;
1939 w |= p->frames >> 2;
1940 }
1941
1942 rtl_lock_work(tp);
1943
1944 RTL_W16(tp, IntrMitigate, swab16(w));
1945
1946 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1947 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1948 RTL_R16(tp, CPlusCmd);
1949
1950 rtl_unlock_work(tp);
1951
1952 return 0;
1953 }
1954
1955 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
1956 {
1957 struct rtl8169_private *tp = netdev_priv(dev);
1958 struct device *d = tp_to_dev(tp);
1959 int ret;
1960
1961 if (!rtl_supports_eee(tp))
1962 return -EOPNOTSUPP;
1963
1964 pm_runtime_get_noresume(d);
1965
1966 if (!pm_runtime_active(d)) {
1967 ret = -EOPNOTSUPP;
1968 } else {
1969 ret = phy_ethtool_get_eee(tp->phydev, data);
1970 }
1971
1972 pm_runtime_put_noidle(d);
1973
1974 return ret;
1975 }
1976
1977 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
1978 {
1979 struct rtl8169_private *tp = netdev_priv(dev);
1980 struct device *d = tp_to_dev(tp);
1981 int ret;
1982
1983 if (!rtl_supports_eee(tp))
1984 return -EOPNOTSUPP;
1985
1986 pm_runtime_get_noresume(d);
1987
1988 if (!pm_runtime_active(d)) {
1989 ret = -EOPNOTSUPP;
1990 goto out;
1991 }
1992
1993 if (dev->phydev->autoneg == AUTONEG_DISABLE ||
1994 dev->phydev->duplex != DUPLEX_FULL) {
1995 ret = -EPROTONOSUPPORT;
1996 goto out;
1997 }
1998
1999 ret = phy_ethtool_set_eee(tp->phydev, data);
2000 out:
2001 pm_runtime_put_noidle(d);
2002 return ret;
2003 }
2004
2005 static const struct ethtool_ops rtl8169_ethtool_ops = {
2006 .get_drvinfo = rtl8169_get_drvinfo,
2007 .get_regs_len = rtl8169_get_regs_len,
2008 .get_link = ethtool_op_get_link,
2009 .get_coalesce = rtl_get_coalesce,
2010 .set_coalesce = rtl_set_coalesce,
2011 .get_msglevel = rtl8169_get_msglevel,
2012 .set_msglevel = rtl8169_set_msglevel,
2013 .get_regs = rtl8169_get_regs,
2014 .get_wol = rtl8169_get_wol,
2015 .set_wol = rtl8169_set_wol,
2016 .get_strings = rtl8169_get_strings,
2017 .get_sset_count = rtl8169_get_sset_count,
2018 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2019 .get_ts_info = ethtool_op_get_ts_info,
2020 .nway_reset = phy_ethtool_nway_reset,
2021 .get_eee = rtl8169_get_eee,
2022 .set_eee = rtl8169_set_eee,
2023 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2024 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2025 };
2026
2027 static void rtl_enable_eee(struct rtl8169_private *tp)
2028 {
2029 struct phy_device *phydev = tp->phydev;
2030 int supported = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
2031
2032 if (supported > 0)
2033 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, supported);
2034 }
2035
2036 static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2037 {
2038 /*
2039 * The driver currently handles the 8168Bf and the 8168Be identically
2040 * but they can be identified more specifically through the test below
2041 * if needed:
2042 *
2043 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2044 *
2045 * Same thing for the 8101Eb and the 8101Ec:
2046 *
2047 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2048 */
2049 static const struct rtl_mac_info {
2050 u16 mask;
2051 u16 val;
2052 u16 mac_version;
2053 } mac_info[] = {
2054 /* 8168EP family. */
2055 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2056 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2057 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2058
2059 /* 8168H family. */
2060 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2061 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2062
2063 /* 8168G family. */
2064 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2065 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2066 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2067 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2068
2069 /* 8168F family. */
2070 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2071 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2072 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2073
2074 /* 8168E family. */
2075 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2076 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2077 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2078
2079 /* 8168D family. */
2080 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2081 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2082
2083 /* 8168DP family. */
2084 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2085 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2086 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2087
2088 /* 8168C family. */
2089 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2090 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2091 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2092 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2093 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2094 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2095 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2096
2097 /* 8168B family. */
2098 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2099 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2100 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2101
2102 /* 8101 family. */
2103 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2104 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2105 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2106 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2107 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2108 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2109 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2110 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2111 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2112 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2113 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2114 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2115 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2116 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2117 /* FIXME: where did these entries come from ? -- FR */
2118 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2119 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2120
2121 /* 8110 family. */
2122 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2123 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2124 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2125 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2126 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2127
2128 /* Catch-all */
2129 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
2130 };
2131 const struct rtl_mac_info *p = mac_info;
2132 u16 reg = RTL_R32(tp, TxConfig) >> 20;
2133
2134 while ((reg & p->mask) != p->val)
2135 p++;
2136 tp->mac_version = p->mac_version;
2137
2138 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2139 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2140 } else if (!tp->supports_gmii) {
2141 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2142 tp->mac_version = RTL_GIGA_MAC_VER_43;
2143 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2144 tp->mac_version = RTL_GIGA_MAC_VER_47;
2145 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2146 tp->mac_version = RTL_GIGA_MAC_VER_48;
2147 }
2148 }
2149
2150 struct phy_reg {
2151 u16 reg;
2152 u16 val;
2153 };
2154
2155 static void __rtl_writephy_batch(struct rtl8169_private *tp,
2156 const struct phy_reg *regs, int len)
2157 {
2158 while (len-- > 0) {
2159 rtl_writephy(tp, regs->reg, regs->val);
2160 regs++;
2161 }
2162 }
2163
2164 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a))
2165
2166 static void rtl_release_firmware(struct rtl8169_private *tp)
2167 {
2168 if (tp->rtl_fw) {
2169 rtl_fw_release_firmware(tp->rtl_fw);
2170 kfree(tp->rtl_fw);
2171 tp->rtl_fw = NULL;
2172 }
2173 }
2174
2175 static void rtl_apply_firmware(struct rtl8169_private *tp)
2176 {
2177 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2178 if (tp->rtl_fw)
2179 rtl_fw_write_firmware(tp, tp->rtl_fw);
2180 }
2181
2182 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2183 {
2184 if (rtl_readphy(tp, reg) != val)
2185 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2186 else
2187 rtl_apply_firmware(tp);
2188 }
2189
2190 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2191 {
2192 /* Adjust EEE LED frequency */
2193 if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2194 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2195
2196 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);
2197 }
2198
2199 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2200 {
2201 struct phy_device *phydev = tp->phydev;
2202
2203 phy_write(phydev, 0x1f, 0x0007);
2204 phy_write(phydev, 0x1e, 0x0020);
2205 phy_set_bits(phydev, 0x15, BIT(8));
2206
2207 phy_write(phydev, 0x1f, 0x0005);
2208 phy_write(phydev, 0x05, 0x8b85);
2209 phy_set_bits(phydev, 0x06, BIT(13));
2210
2211 phy_write(phydev, 0x1f, 0x0000);
2212 }
2213
2214 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2215 {
2216 phy_modify_paged(tp->phydev, 0x0a43, 0x11, 0, BIT(4));
2217 }
2218
2219 static void rtl8168h_config_eee_phy(struct rtl8169_private *tp)
2220 {
2221 struct phy_device *phydev = tp->phydev;
2222
2223 rtl8168g_config_eee_phy(tp);
2224
2225 phy_modify_paged(phydev, 0xa4a, 0x11, 0x0000, 0x0200);
2226 phy_modify_paged(phydev, 0xa42, 0x14, 0x0000, 0x0080);
2227 }
2228
2229 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2230 {
2231 static const struct phy_reg phy_reg_init[] = {
2232 { 0x1f, 0x0001 },
2233 { 0x06, 0x006e },
2234 { 0x08, 0x0708 },
2235 { 0x15, 0x4000 },
2236 { 0x18, 0x65c7 },
2237
2238 { 0x1f, 0x0001 },
2239 { 0x03, 0x00a1 },
2240 { 0x02, 0x0008 },
2241 { 0x01, 0x0120 },
2242 { 0x00, 0x1000 },
2243 { 0x04, 0x0800 },
2244 { 0x04, 0x0000 },
2245
2246 { 0x03, 0xff41 },
2247 { 0x02, 0xdf60 },
2248 { 0x01, 0x0140 },
2249 { 0x00, 0x0077 },
2250 { 0x04, 0x7800 },
2251 { 0x04, 0x7000 },
2252
2253 { 0x03, 0x802f },
2254 { 0x02, 0x4f02 },
2255 { 0x01, 0x0409 },
2256 { 0x00, 0xf0f9 },
2257 { 0x04, 0x9800 },
2258 { 0x04, 0x9000 },
2259
2260 { 0x03, 0xdf01 },
2261 { 0x02, 0xdf20 },
2262 { 0x01, 0xff95 },
2263 { 0x00, 0xba00 },
2264 { 0x04, 0xa800 },
2265 { 0x04, 0xa000 },
2266
2267 { 0x03, 0xff41 },
2268 { 0x02, 0xdf20 },
2269 { 0x01, 0x0140 },
2270 { 0x00, 0x00bb },
2271 { 0x04, 0xb800 },
2272 { 0x04, 0xb000 },
2273
2274 { 0x03, 0xdf41 },
2275 { 0x02, 0xdc60 },
2276 { 0x01, 0x6340 },
2277 { 0x00, 0x007d },
2278 { 0x04, 0xd800 },
2279 { 0x04, 0xd000 },
2280
2281 { 0x03, 0xdf01 },
2282 { 0x02, 0xdf20 },
2283 { 0x01, 0x100a },
2284 { 0x00, 0xa0ff },
2285 { 0x04, 0xf800 },
2286 { 0x04, 0xf000 },
2287
2288 { 0x1f, 0x0000 },
2289 { 0x0b, 0x0000 },
2290 { 0x00, 0x9200 }
2291 };
2292
2293 rtl_writephy_batch(tp, phy_reg_init);
2294 }
2295
2296 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2297 {
2298 static const struct phy_reg phy_reg_init[] = {
2299 { 0x1f, 0x0002 },
2300 { 0x01, 0x90d0 },
2301 { 0x1f, 0x0000 }
2302 };
2303
2304 rtl_writephy_batch(tp, phy_reg_init);
2305 }
2306
2307 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2308 {
2309 struct pci_dev *pdev = tp->pci_dev;
2310
2311 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2312 (pdev->subsystem_device != 0xe000))
2313 return;
2314
2315 rtl_writephy(tp, 0x1f, 0x0001);
2316 rtl_writephy(tp, 0x10, 0xf01b);
2317 rtl_writephy(tp, 0x1f, 0x0000);
2318 }
2319
2320 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2321 {
2322 static const struct phy_reg phy_reg_init[] = {
2323 { 0x1f, 0x0001 },
2324 { 0x04, 0x0000 },
2325 { 0x03, 0x00a1 },
2326 { 0x02, 0x0008 },
2327 { 0x01, 0x0120 },
2328 { 0x00, 0x1000 },
2329 { 0x04, 0x0800 },
2330 { 0x04, 0x9000 },
2331 { 0x03, 0x802f },
2332 { 0x02, 0x4f02 },
2333 { 0x01, 0x0409 },
2334 { 0x00, 0xf099 },
2335 { 0x04, 0x9800 },
2336 { 0x04, 0xa000 },
2337 { 0x03, 0xdf01 },
2338 { 0x02, 0xdf20 },
2339 { 0x01, 0xff95 },
2340 { 0x00, 0xba00 },
2341 { 0x04, 0xa800 },
2342 { 0x04, 0xf000 },
2343 { 0x03, 0xdf01 },
2344 { 0x02, 0xdf20 },
2345 { 0x01, 0x101a },
2346 { 0x00, 0xa0ff },
2347 { 0x04, 0xf800 },
2348 { 0x04, 0x0000 },
2349 { 0x1f, 0x0000 },
2350
2351 { 0x1f, 0x0001 },
2352 { 0x10, 0xf41b },
2353 { 0x14, 0xfb54 },
2354 { 0x18, 0xf5c7 },
2355 { 0x1f, 0x0000 },
2356
2357 { 0x1f, 0x0001 },
2358 { 0x17, 0x0cc0 },
2359 { 0x1f, 0x0000 }
2360 };
2361
2362 rtl_writephy_batch(tp, phy_reg_init);
2363
2364 rtl8169scd_hw_phy_config_quirk(tp);
2365 }
2366
2367 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2368 {
2369 static const struct phy_reg phy_reg_init[] = {
2370 { 0x1f, 0x0001 },
2371 { 0x04, 0x0000 },
2372 { 0x03, 0x00a1 },
2373 { 0x02, 0x0008 },
2374 { 0x01, 0x0120 },
2375 { 0x00, 0x1000 },
2376 { 0x04, 0x0800 },
2377 { 0x04, 0x9000 },
2378 { 0x03, 0x802f },
2379 { 0x02, 0x4f02 },
2380 { 0x01, 0x0409 },
2381 { 0x00, 0xf099 },
2382 { 0x04, 0x9800 },
2383 { 0x04, 0xa000 },
2384 { 0x03, 0xdf01 },
2385 { 0x02, 0xdf20 },
2386 { 0x01, 0xff95 },
2387 { 0x00, 0xba00 },
2388 { 0x04, 0xa800 },
2389 { 0x04, 0xf000 },
2390 { 0x03, 0xdf01 },
2391 { 0x02, 0xdf20 },
2392 { 0x01, 0x101a },
2393 { 0x00, 0xa0ff },
2394 { 0x04, 0xf800 },
2395 { 0x04, 0x0000 },
2396 { 0x1f, 0x0000 },
2397
2398 { 0x1f, 0x0001 },
2399 { 0x0b, 0x8480 },
2400 { 0x1f, 0x0000 },
2401
2402 { 0x1f, 0x0001 },
2403 { 0x18, 0x67c7 },
2404 { 0x04, 0x2000 },
2405 { 0x03, 0x002f },
2406 { 0x02, 0x4360 },
2407 { 0x01, 0x0109 },
2408 { 0x00, 0x3022 },
2409 { 0x04, 0x2800 },
2410 { 0x1f, 0x0000 },
2411
2412 { 0x1f, 0x0001 },
2413 { 0x17, 0x0cc0 },
2414 { 0x1f, 0x0000 }
2415 };
2416
2417 rtl_writephy_batch(tp, phy_reg_init);
2418 }
2419
2420 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2421 {
2422 static const struct phy_reg phy_reg_init[] = {
2423 { 0x10, 0xf41b },
2424 { 0x1f, 0x0000 }
2425 };
2426
2427 rtl_writephy(tp, 0x1f, 0x0001);
2428 rtl_patchphy(tp, 0x16, 1 << 0);
2429
2430 rtl_writephy_batch(tp, phy_reg_init);
2431 }
2432
2433 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2434 {
2435 static const struct phy_reg phy_reg_init[] = {
2436 { 0x1f, 0x0001 },
2437 { 0x10, 0xf41b },
2438 { 0x1f, 0x0000 }
2439 };
2440
2441 rtl_writephy_batch(tp, phy_reg_init);
2442 }
2443
2444 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2445 {
2446 static const struct phy_reg phy_reg_init[] = {
2447 { 0x1f, 0x0000 },
2448 { 0x1d, 0x0f00 },
2449 { 0x1f, 0x0002 },
2450 { 0x0c, 0x1ec8 },
2451 { 0x1f, 0x0000 }
2452 };
2453
2454 rtl_writephy_batch(tp, phy_reg_init);
2455 }
2456
2457 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2458 {
2459 static const struct phy_reg phy_reg_init[] = {
2460 { 0x1f, 0x0001 },
2461 { 0x1d, 0x3d98 },
2462 { 0x1f, 0x0000 }
2463 };
2464
2465 rtl_writephy(tp, 0x1f, 0x0000);
2466 rtl_patchphy(tp, 0x14, 1 << 5);
2467 rtl_patchphy(tp, 0x0d, 1 << 5);
2468
2469 rtl_writephy_batch(tp, phy_reg_init);
2470 }
2471
2472 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2473 {
2474 static const struct phy_reg phy_reg_init[] = {
2475 { 0x1f, 0x0001 },
2476 { 0x12, 0x2300 },
2477 { 0x1f, 0x0002 },
2478 { 0x00, 0x88d4 },
2479 { 0x01, 0x82b1 },
2480 { 0x03, 0x7002 },
2481 { 0x08, 0x9e30 },
2482 { 0x09, 0x01f0 },
2483 { 0x0a, 0x5500 },
2484 { 0x0c, 0x00c8 },
2485 { 0x1f, 0x0003 },
2486 { 0x12, 0xc096 },
2487 { 0x16, 0x000a },
2488 { 0x1f, 0x0000 },
2489 { 0x1f, 0x0000 },
2490 { 0x09, 0x2000 },
2491 { 0x09, 0x0000 }
2492 };
2493
2494 rtl_writephy_batch(tp, phy_reg_init);
2495
2496 rtl_patchphy(tp, 0x14, 1 << 5);
2497 rtl_patchphy(tp, 0x0d, 1 << 5);
2498 rtl_writephy(tp, 0x1f, 0x0000);
2499 }
2500
2501 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2502 {
2503 static const struct phy_reg phy_reg_init[] = {
2504 { 0x1f, 0x0001 },
2505 { 0x12, 0x2300 },
2506 { 0x03, 0x802f },
2507 { 0x02, 0x4f02 },
2508 { 0x01, 0x0409 },
2509 { 0x00, 0xf099 },
2510 { 0x04, 0x9800 },
2511 { 0x04, 0x9000 },
2512 { 0x1d, 0x3d98 },
2513 { 0x1f, 0x0002 },
2514 { 0x0c, 0x7eb8 },
2515 { 0x06, 0x0761 },
2516 { 0x1f, 0x0003 },
2517 { 0x16, 0x0f0a },
2518 { 0x1f, 0x0000 }
2519 };
2520
2521 rtl_writephy_batch(tp, phy_reg_init);
2522
2523 rtl_patchphy(tp, 0x16, 1 << 0);
2524 rtl_patchphy(tp, 0x14, 1 << 5);
2525 rtl_patchphy(tp, 0x0d, 1 << 5);
2526 rtl_writephy(tp, 0x1f, 0x0000);
2527 }
2528
2529 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2530 {
2531 static const struct phy_reg phy_reg_init[] = {
2532 { 0x1f, 0x0001 },
2533 { 0x12, 0x2300 },
2534 { 0x1d, 0x3d98 },
2535 { 0x1f, 0x0002 },
2536 { 0x0c, 0x7eb8 },
2537 { 0x06, 0x5461 },
2538 { 0x1f, 0x0003 },
2539 { 0x16, 0x0f0a },
2540 { 0x1f, 0x0000 }
2541 };
2542
2543 rtl_writephy_batch(tp, phy_reg_init);
2544
2545 rtl_patchphy(tp, 0x16, 1 << 0);
2546 rtl_patchphy(tp, 0x14, 1 << 5);
2547 rtl_patchphy(tp, 0x0d, 1 << 5);
2548 rtl_writephy(tp, 0x1f, 0x0000);
2549 }
2550
2551 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2552 {
2553 rtl8168c_3_hw_phy_config(tp);
2554 }
2555
2556 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
2557 /* Channel Estimation */
2558 { 0x1f, 0x0001 },
2559 { 0x06, 0x4064 },
2560 { 0x07, 0x2863 },
2561 { 0x08, 0x059c },
2562 { 0x09, 0x26b4 },
2563 { 0x0a, 0x6a19 },
2564 { 0x0b, 0xdcc8 },
2565 { 0x10, 0xf06d },
2566 { 0x14, 0x7f68 },
2567 { 0x18, 0x7fd9 },
2568 { 0x1c, 0xf0ff },
2569 { 0x1d, 0x3d9c },
2570 { 0x1f, 0x0003 },
2571 { 0x12, 0xf49f },
2572 { 0x13, 0x070b },
2573 { 0x1a, 0x05ad },
2574 { 0x14, 0x94c0 },
2575
2576 /*
2577 * Tx Error Issue
2578 * Enhance line driver power
2579 */
2580 { 0x1f, 0x0002 },
2581 { 0x06, 0x5561 },
2582 { 0x1f, 0x0005 },
2583 { 0x05, 0x8332 },
2584 { 0x06, 0x5561 },
2585
2586 /*
2587 * Can not link to 1Gbps with bad cable
2588 * Decrease SNR threshold form 21.07dB to 19.04dB
2589 */
2590 { 0x1f, 0x0001 },
2591 { 0x17, 0x0cc0 },
2592
2593 { 0x1f, 0x0000 },
2594 { 0x0d, 0xf880 }
2595 };
2596
2597 static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = {
2598 { 0x1f, 0x0002 },
2599 { 0x05, 0x669a },
2600 { 0x1f, 0x0005 },
2601 { 0x05, 0x8330 },
2602 { 0x06, 0x669a },
2603 { 0x1f, 0x0002 }
2604 };
2605
2606 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2607 {
2608 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2609
2610 /*
2611 * Rx Error Issue
2612 * Fine Tune Switching regulator parameter
2613 */
2614 rtl_writephy(tp, 0x1f, 0x0002);
2615 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2616 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2617
2618 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2619 int val;
2620
2621 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2622
2623 val = rtl_readphy(tp, 0x0d);
2624
2625 if ((val & 0x00ff) != 0x006c) {
2626 static const u32 set[] = {
2627 0x0065, 0x0066, 0x0067, 0x0068,
2628 0x0069, 0x006a, 0x006b, 0x006c
2629 };
2630 int i;
2631
2632 rtl_writephy(tp, 0x1f, 0x0002);
2633
2634 val &= 0xff00;
2635 for (i = 0; i < ARRAY_SIZE(set); i++)
2636 rtl_writephy(tp, 0x0d, val | set[i]);
2637 }
2638 } else {
2639 static const struct phy_reg phy_reg_init[] = {
2640 { 0x1f, 0x0002 },
2641 { 0x05, 0x6662 },
2642 { 0x1f, 0x0005 },
2643 { 0x05, 0x8330 },
2644 { 0x06, 0x6662 }
2645 };
2646
2647 rtl_writephy_batch(tp, phy_reg_init);
2648 }
2649
2650 /* RSET couple improve */
2651 rtl_writephy(tp, 0x1f, 0x0002);
2652 rtl_patchphy(tp, 0x0d, 0x0300);
2653 rtl_patchphy(tp, 0x0f, 0x0010);
2654
2655 /* Fine tune PLL performance */
2656 rtl_writephy(tp, 0x1f, 0x0002);
2657 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2658 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2659
2660 rtl_writephy(tp, 0x1f, 0x0005);
2661 rtl_writephy(tp, 0x05, 0x001b);
2662
2663 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2664
2665 rtl_writephy(tp, 0x1f, 0x0000);
2666 }
2667
2668 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2669 {
2670 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2671
2672 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2673 int val;
2674
2675 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2676
2677 val = rtl_readphy(tp, 0x0d);
2678 if ((val & 0x00ff) != 0x006c) {
2679 static const u32 set[] = {
2680 0x0065, 0x0066, 0x0067, 0x0068,
2681 0x0069, 0x006a, 0x006b, 0x006c
2682 };
2683 int i;
2684
2685 rtl_writephy(tp, 0x1f, 0x0002);
2686
2687 val &= 0xff00;
2688 for (i = 0; i < ARRAY_SIZE(set); i++)
2689 rtl_writephy(tp, 0x0d, val | set[i]);
2690 }
2691 } else {
2692 static const struct phy_reg phy_reg_init[] = {
2693 { 0x1f, 0x0002 },
2694 { 0x05, 0x2642 },
2695 { 0x1f, 0x0005 },
2696 { 0x05, 0x8330 },
2697 { 0x06, 0x2642 }
2698 };
2699
2700 rtl_writephy_batch(tp, phy_reg_init);
2701 }
2702
2703 /* Fine tune PLL performance */
2704 rtl_writephy(tp, 0x1f, 0x0002);
2705 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2706 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2707
2708 /* Switching regulator Slew rate */
2709 rtl_writephy(tp, 0x1f, 0x0002);
2710 rtl_patchphy(tp, 0x0f, 0x0017);
2711
2712 rtl_writephy(tp, 0x1f, 0x0005);
2713 rtl_writephy(tp, 0x05, 0x001b);
2714
2715 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2716
2717 rtl_writephy(tp, 0x1f, 0x0000);
2718 }
2719
2720 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2721 {
2722 static const struct phy_reg phy_reg_init[] = {
2723 { 0x1f, 0x0002 },
2724 { 0x10, 0x0008 },
2725 { 0x0d, 0x006c },
2726
2727 { 0x1f, 0x0000 },
2728 { 0x0d, 0xf880 },
2729
2730 { 0x1f, 0x0001 },
2731 { 0x17, 0x0cc0 },
2732
2733 { 0x1f, 0x0001 },
2734 { 0x0b, 0xa4d8 },
2735 { 0x09, 0x281c },
2736 { 0x07, 0x2883 },
2737 { 0x0a, 0x6b35 },
2738 { 0x1d, 0x3da4 },
2739 { 0x1c, 0xeffd },
2740 { 0x14, 0x7f52 },
2741 { 0x18, 0x7fc6 },
2742 { 0x08, 0x0601 },
2743 { 0x06, 0x4063 },
2744 { 0x10, 0xf074 },
2745 { 0x1f, 0x0003 },
2746 { 0x13, 0x0789 },
2747 { 0x12, 0xf4bd },
2748 { 0x1a, 0x04fd },
2749 { 0x14, 0x84b0 },
2750 { 0x1f, 0x0000 },
2751 { 0x00, 0x9200 },
2752
2753 { 0x1f, 0x0005 },
2754 { 0x01, 0x0340 },
2755 { 0x1f, 0x0001 },
2756 { 0x04, 0x4000 },
2757 { 0x03, 0x1d21 },
2758 { 0x02, 0x0c32 },
2759 { 0x01, 0x0200 },
2760 { 0x00, 0x5554 },
2761 { 0x04, 0x4800 },
2762 { 0x04, 0x4000 },
2763 { 0x04, 0xf000 },
2764 { 0x03, 0xdf01 },
2765 { 0x02, 0xdf20 },
2766 { 0x01, 0x101a },
2767 { 0x00, 0xa0ff },
2768 { 0x04, 0xf800 },
2769 { 0x04, 0xf000 },
2770 { 0x1f, 0x0000 },
2771
2772 { 0x1f, 0x0007 },
2773 { 0x1e, 0x0023 },
2774 { 0x16, 0x0000 },
2775 { 0x1f, 0x0000 }
2776 };
2777
2778 rtl_writephy_batch(tp, phy_reg_init);
2779 }
2780
2781 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2782 {
2783 static const struct phy_reg phy_reg_init[] = {
2784 { 0x1f, 0x0001 },
2785 { 0x17, 0x0cc0 },
2786
2787 { 0x1f, 0x0007 },
2788 { 0x1e, 0x002d },
2789 { 0x18, 0x0040 },
2790 { 0x1f, 0x0000 }
2791 };
2792
2793 rtl_writephy_batch(tp, phy_reg_init);
2794 rtl_patchphy(tp, 0x0d, 1 << 5);
2795 }
2796
2797 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2798 {
2799 static const struct phy_reg phy_reg_init[] = {
2800 /* Enable Delay cap */
2801 { 0x1f, 0x0005 },
2802 { 0x05, 0x8b80 },
2803 { 0x06, 0xc896 },
2804 { 0x1f, 0x0000 },
2805
2806 /* Channel estimation fine tune */
2807 { 0x1f, 0x0001 },
2808 { 0x0b, 0x6c20 },
2809 { 0x07, 0x2872 },
2810 { 0x1c, 0xefff },
2811 { 0x1f, 0x0003 },
2812 { 0x14, 0x6420 },
2813 { 0x1f, 0x0000 },
2814
2815 /* Update PFM & 10M TX idle timer */
2816 { 0x1f, 0x0007 },
2817 { 0x1e, 0x002f },
2818 { 0x15, 0x1919 },
2819 { 0x1f, 0x0000 },
2820
2821 { 0x1f, 0x0007 },
2822 { 0x1e, 0x00ac },
2823 { 0x18, 0x0006 },
2824 { 0x1f, 0x0000 }
2825 };
2826
2827 rtl_apply_firmware(tp);
2828
2829 rtl_writephy_batch(tp, phy_reg_init);
2830
2831 /* DCO enable for 10M IDLE Power */
2832 rtl_writephy(tp, 0x1f, 0x0007);
2833 rtl_writephy(tp, 0x1e, 0x0023);
2834 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
2835 rtl_writephy(tp, 0x1f, 0x0000);
2836
2837 /* For impedance matching */
2838 rtl_writephy(tp, 0x1f, 0x0002);
2839 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
2840 rtl_writephy(tp, 0x1f, 0x0000);
2841
2842 /* PHY auto speed down */
2843 rtl_writephy(tp, 0x1f, 0x0007);
2844 rtl_writephy(tp, 0x1e, 0x002d);
2845 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
2846 rtl_writephy(tp, 0x1f, 0x0000);
2847 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
2848
2849 rtl_writephy(tp, 0x1f, 0x0005);
2850 rtl_writephy(tp, 0x05, 0x8b86);
2851 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
2852 rtl_writephy(tp, 0x1f, 0x0000);
2853
2854 rtl_writephy(tp, 0x1f, 0x0005);
2855 rtl_writephy(tp, 0x05, 0x8b85);
2856 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
2857 rtl_writephy(tp, 0x1f, 0x0007);
2858 rtl_writephy(tp, 0x1e, 0x0020);
2859 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
2860 rtl_writephy(tp, 0x1f, 0x0006);
2861 rtl_writephy(tp, 0x00, 0x5a00);
2862 rtl_writephy(tp, 0x1f, 0x0000);
2863 rtl_writephy(tp, 0x0d, 0x0007);
2864 rtl_writephy(tp, 0x0e, 0x003c);
2865 rtl_writephy(tp, 0x0d, 0x4007);
2866 rtl_writephy(tp, 0x0e, 0x0000);
2867 rtl_writephy(tp, 0x0d, 0x0000);
2868 }
2869
2870 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
2871 {
2872 const u16 w[] = {
2873 addr[0] | (addr[1] << 8),
2874 addr[2] | (addr[3] << 8),
2875 addr[4] | (addr[5] << 8)
2876 };
2877
2878 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
2879 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
2880 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
2881 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
2882 }
2883
2884 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2885 {
2886 static const struct phy_reg phy_reg_init[] = {
2887 /* Enable Delay cap */
2888 { 0x1f, 0x0004 },
2889 { 0x1f, 0x0007 },
2890 { 0x1e, 0x00ac },
2891 { 0x18, 0x0006 },
2892 { 0x1f, 0x0002 },
2893 { 0x1f, 0x0000 },
2894 { 0x1f, 0x0000 },
2895
2896 /* Channel estimation fine tune */
2897 { 0x1f, 0x0003 },
2898 { 0x09, 0xa20f },
2899 { 0x1f, 0x0000 },
2900 { 0x1f, 0x0000 },
2901
2902 /* Green Setting */
2903 { 0x1f, 0x0005 },
2904 { 0x05, 0x8b5b },
2905 { 0x06, 0x9222 },
2906 { 0x05, 0x8b6d },
2907 { 0x06, 0x8000 },
2908 { 0x05, 0x8b76 },
2909 { 0x06, 0x8000 },
2910 { 0x1f, 0x0000 }
2911 };
2912
2913 rtl_apply_firmware(tp);
2914
2915 rtl_writephy_batch(tp, phy_reg_init);
2916
2917 /* For 4-corner performance improve */
2918 rtl_writephy(tp, 0x1f, 0x0005);
2919 rtl_writephy(tp, 0x05, 0x8b80);
2920 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
2921 rtl_writephy(tp, 0x1f, 0x0000);
2922
2923 /* PHY auto speed down */
2924 rtl_writephy(tp, 0x1f, 0x0004);
2925 rtl_writephy(tp, 0x1f, 0x0007);
2926 rtl_writephy(tp, 0x1e, 0x002d);
2927 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
2928 rtl_writephy(tp, 0x1f, 0x0002);
2929 rtl_writephy(tp, 0x1f, 0x0000);
2930 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
2931
2932 /* improve 10M EEE waveform */
2933 rtl_writephy(tp, 0x1f, 0x0005);
2934 rtl_writephy(tp, 0x05, 0x8b86);
2935 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
2936 rtl_writephy(tp, 0x1f, 0x0000);
2937
2938 /* Improve 2-pair detection performance */
2939 rtl_writephy(tp, 0x1f, 0x0005);
2940 rtl_writephy(tp, 0x05, 0x8b85);
2941 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
2942 rtl_writephy(tp, 0x1f, 0x0000);
2943
2944 rtl8168f_config_eee_phy(tp);
2945 rtl_enable_eee(tp);
2946
2947 /* Green feature */
2948 rtl_writephy(tp, 0x1f, 0x0003);
2949 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
2950 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
2951 rtl_writephy(tp, 0x1f, 0x0000);
2952 rtl_writephy(tp, 0x1f, 0x0005);
2953 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
2954 rtl_writephy(tp, 0x1f, 0x0000);
2955
2956 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
2957 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
2958 }
2959
2960 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
2961 {
2962 /* For 4-corner performance improve */
2963 rtl_writephy(tp, 0x1f, 0x0005);
2964 rtl_writephy(tp, 0x05, 0x8b80);
2965 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
2966 rtl_writephy(tp, 0x1f, 0x0000);
2967
2968 /* PHY auto speed down */
2969 rtl_writephy(tp, 0x1f, 0x0007);
2970 rtl_writephy(tp, 0x1e, 0x002d);
2971 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
2972 rtl_writephy(tp, 0x1f, 0x0000);
2973 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
2974
2975 /* Improve 10M EEE waveform */
2976 rtl_writephy(tp, 0x1f, 0x0005);
2977 rtl_writephy(tp, 0x05, 0x8b86);
2978 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
2979 rtl_writephy(tp, 0x1f, 0x0000);
2980
2981 rtl8168f_config_eee_phy(tp);
2982 rtl_enable_eee(tp);
2983 }
2984
2985 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
2986 {
2987 static const struct phy_reg phy_reg_init[] = {
2988 /* Channel estimation fine tune */
2989 { 0x1f, 0x0003 },
2990 { 0x09, 0xa20f },
2991 { 0x1f, 0x0000 },
2992
2993 /* Modify green table for giga & fnet */
2994 { 0x1f, 0x0005 },
2995 { 0x05, 0x8b55 },
2996 { 0x06, 0x0000 },
2997 { 0x05, 0x8b5e },
2998 { 0x06, 0x0000 },
2999 { 0x05, 0x8b67 },
3000 { 0x06, 0x0000 },
3001 { 0x05, 0x8b70 },
3002 { 0x06, 0x0000 },
3003 { 0x1f, 0x0000 },
3004 { 0x1f, 0x0007 },
3005 { 0x1e, 0x0078 },
3006 { 0x17, 0x0000 },
3007 { 0x19, 0x00fb },
3008 { 0x1f, 0x0000 },
3009
3010 /* Modify green table for 10M */
3011 { 0x1f, 0x0005 },
3012 { 0x05, 0x8b79 },
3013 { 0x06, 0xaa00 },
3014 { 0x1f, 0x0000 },
3015
3016 /* Disable hiimpedance detection (RTCT) */
3017 { 0x1f, 0x0003 },
3018 { 0x01, 0x328a },
3019 { 0x1f, 0x0000 }
3020 };
3021
3022 rtl_apply_firmware(tp);
3023
3024 rtl_writephy_batch(tp, phy_reg_init);
3025
3026 rtl8168f_hw_phy_config(tp);
3027
3028 /* Improve 2-pair detection performance */
3029 rtl_writephy(tp, 0x1f, 0x0005);
3030 rtl_writephy(tp, 0x05, 0x8b85);
3031 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3032 rtl_writephy(tp, 0x1f, 0x0000);
3033 }
3034
3035 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3036 {
3037 rtl_apply_firmware(tp);
3038
3039 rtl8168f_hw_phy_config(tp);
3040 }
3041
3042 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3043 {
3044 static const struct phy_reg phy_reg_init[] = {
3045 /* Channel estimation fine tune */
3046 { 0x1f, 0x0003 },
3047 { 0x09, 0xa20f },
3048 { 0x1f, 0x0000 },
3049
3050 /* Modify green table for giga & fnet */
3051 { 0x1f, 0x0005 },
3052 { 0x05, 0x8b55 },
3053 { 0x06, 0x0000 },
3054 { 0x05, 0x8b5e },
3055 { 0x06, 0x0000 },
3056 { 0x05, 0x8b67 },
3057 { 0x06, 0x0000 },
3058 { 0x05, 0x8b70 },
3059 { 0x06, 0x0000 },
3060 { 0x1f, 0x0000 },
3061 { 0x1f, 0x0007 },
3062 { 0x1e, 0x0078 },
3063 { 0x17, 0x0000 },
3064 { 0x19, 0x00aa },
3065 { 0x1f, 0x0000 },
3066
3067 /* Modify green table for 10M */
3068 { 0x1f, 0x0005 },
3069 { 0x05, 0x8b79 },
3070 { 0x06, 0xaa00 },
3071 { 0x1f, 0x0000 },
3072
3073 /* Disable hiimpedance detection (RTCT) */
3074 { 0x1f, 0x0003 },
3075 { 0x01, 0x328a },
3076 { 0x1f, 0x0000 }
3077 };
3078
3079
3080 rtl_apply_firmware(tp);
3081
3082 rtl8168f_hw_phy_config(tp);
3083
3084 /* Improve 2-pair detection performance */
3085 rtl_writephy(tp, 0x1f, 0x0005);
3086 rtl_writephy(tp, 0x05, 0x8b85);
3087 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3088 rtl_writephy(tp, 0x1f, 0x0000);
3089
3090 rtl_writephy_batch(tp, phy_reg_init);
3091
3092 /* Modify green table for giga */
3093 rtl_writephy(tp, 0x1f, 0x0005);
3094 rtl_writephy(tp, 0x05, 0x8b54);
3095 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3096 rtl_writephy(tp, 0x05, 0x8b5d);
3097 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3098 rtl_writephy(tp, 0x05, 0x8a7c);
3099 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3100 rtl_writephy(tp, 0x05, 0x8a7f);
3101 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3102 rtl_writephy(tp, 0x05, 0x8a82);
3103 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3104 rtl_writephy(tp, 0x05, 0x8a85);
3105 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3106 rtl_writephy(tp, 0x05, 0x8a88);
3107 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3108 rtl_writephy(tp, 0x1f, 0x0000);
3109
3110 /* uc same-seed solution */
3111 rtl_writephy(tp, 0x1f, 0x0005);
3112 rtl_writephy(tp, 0x05, 0x8b85);
3113 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3114 rtl_writephy(tp, 0x1f, 0x0000);
3115
3116 /* Green feature */
3117 rtl_writephy(tp, 0x1f, 0x0003);
3118 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3119 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3120 rtl_writephy(tp, 0x1f, 0x0000);
3121 }
3122
3123 static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3124 {
3125 phy_modify_paged(tp->phydev, 0x0a43, 0x10, BIT(2), 0);
3126 }
3127
3128 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3129 {
3130 struct phy_device *phydev = tp->phydev;
3131
3132 phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0);
3133 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6));
3134 phy_write(phydev, 0x1f, 0x0a43);
3135 phy_write(phydev, 0x13, 0x8084);
3136 phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13));
3137 phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0));
3138
3139 phy_write(phydev, 0x1f, 0x0000);
3140 }
3141
3142 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3143 {
3144 int ret;
3145
3146 rtl_apply_firmware(tp);
3147
3148 ret = phy_read_paged(tp->phydev, 0x0a46, 0x10);
3149 if (ret & BIT(8))
3150 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, BIT(15), 0);
3151 else
3152 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, 0, BIT(15));
3153
3154 ret = phy_read_paged(tp->phydev, 0x0a46, 0x13);
3155 if (ret & BIT(8))
3156 phy_modify_paged(tp->phydev, 0x0c41, 0x15, 0, BIT(1));
3157 else
3158 phy_modify_paged(tp->phydev, 0x0c41, 0x15, BIT(1), 0);
3159
3160 /* Enable PHY auto speed down */
3161 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3162
3163 rtl8168g_phy_adjust_10m_aldps(tp);
3164
3165 /* EEE auto-fallback function */
3166 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3167
3168 /* Enable UC LPF tune function */
3169 rtl_writephy(tp, 0x1f, 0x0a43);
3170 rtl_writephy(tp, 0x13, 0x8012);
3171 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3172
3173 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3174
3175 /* Improve SWR Efficiency */
3176 rtl_writephy(tp, 0x1f, 0x0bcd);
3177 rtl_writephy(tp, 0x14, 0x5065);
3178 rtl_writephy(tp, 0x14, 0xd065);
3179 rtl_writephy(tp, 0x1f, 0x0bc8);
3180 rtl_writephy(tp, 0x11, 0x5655);
3181 rtl_writephy(tp, 0x1f, 0x0bcd);
3182 rtl_writephy(tp, 0x14, 0x1065);
3183 rtl_writephy(tp, 0x14, 0x9065);
3184 rtl_writephy(tp, 0x14, 0x1065);
3185 rtl_writephy(tp, 0x1f, 0x0000);
3186
3187 rtl8168g_disable_aldps(tp);
3188 rtl8168g_config_eee_phy(tp);
3189 rtl_enable_eee(tp);
3190 }
3191
3192 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3193 {
3194 rtl_apply_firmware(tp);
3195 rtl8168g_config_eee_phy(tp);
3196 rtl_enable_eee(tp);
3197 }
3198
3199 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3200 {
3201 u16 dout_tapbin;
3202 u32 data;
3203
3204 rtl_apply_firmware(tp);
3205
3206 /* CHN EST parameters adjust - giga master */
3207 rtl_writephy(tp, 0x1f, 0x0a43);
3208 rtl_writephy(tp, 0x13, 0x809b);
3209 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3210 rtl_writephy(tp, 0x13, 0x80a2);
3211 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3212 rtl_writephy(tp, 0x13, 0x80a4);
3213 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3214 rtl_writephy(tp, 0x13, 0x809c);
3215 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3216 rtl_writephy(tp, 0x1f, 0x0000);
3217
3218 /* CHN EST parameters adjust - giga slave */
3219 rtl_writephy(tp, 0x1f, 0x0a43);
3220 rtl_writephy(tp, 0x13, 0x80ad);
3221 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3222 rtl_writephy(tp, 0x13, 0x80b4);
3223 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3224 rtl_writephy(tp, 0x13, 0x80ac);
3225 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3226 rtl_writephy(tp, 0x1f, 0x0000);
3227
3228 /* CHN EST parameters adjust - fnet */
3229 rtl_writephy(tp, 0x1f, 0x0a43);
3230 rtl_writephy(tp, 0x13, 0x808e);
3231 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3232 rtl_writephy(tp, 0x13, 0x8090);
3233 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3234 rtl_writephy(tp, 0x13, 0x8092);
3235 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3236 rtl_writephy(tp, 0x1f, 0x0000);
3237
3238 /* enable R-tune & PGA-retune function */
3239 dout_tapbin = 0;
3240 rtl_writephy(tp, 0x1f, 0x0a46);
3241 data = rtl_readphy(tp, 0x13);
3242 data &= 3;
3243 data <<= 2;
3244 dout_tapbin |= data;
3245 data = rtl_readphy(tp, 0x12);
3246 data &= 0xc000;
3247 data >>= 14;
3248 dout_tapbin |= data;
3249 dout_tapbin = ~(dout_tapbin^0x08);
3250 dout_tapbin <<= 12;
3251 dout_tapbin &= 0xf000;
3252 rtl_writephy(tp, 0x1f, 0x0a43);
3253 rtl_writephy(tp, 0x13, 0x827a);
3254 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3255 rtl_writephy(tp, 0x13, 0x827b);
3256 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3257 rtl_writephy(tp, 0x13, 0x827c);
3258 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3259 rtl_writephy(tp, 0x13, 0x827d);
3260 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3261
3262 rtl_writephy(tp, 0x1f, 0x0a43);
3263 rtl_writephy(tp, 0x13, 0x0811);
3264 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3265 rtl_writephy(tp, 0x1f, 0x0a42);
3266 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3267 rtl_writephy(tp, 0x1f, 0x0000);
3268
3269 /* enable GPHY 10M */
3270 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3271
3272 /* SAR ADC performance */
3273 phy_modify_paged(tp->phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14));
3274
3275 rtl_writephy(tp, 0x1f, 0x0a43);
3276 rtl_writephy(tp, 0x13, 0x803f);
3277 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3278 rtl_writephy(tp, 0x13, 0x8047);
3279 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3280 rtl_writephy(tp, 0x13, 0x804f);
3281 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3282 rtl_writephy(tp, 0x13, 0x8057);
3283 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3284 rtl_writephy(tp, 0x13, 0x805f);
3285 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3286 rtl_writephy(tp, 0x13, 0x8067);
3287 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3288 rtl_writephy(tp, 0x13, 0x806f);
3289 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3290 rtl_writephy(tp, 0x1f, 0x0000);
3291
3292 /* disable phy pfm mode */
3293 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3294
3295 rtl8168g_disable_aldps(tp);
3296 rtl8168h_config_eee_phy(tp);
3297 rtl_enable_eee(tp);
3298 }
3299
3300 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3301 {
3302 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3303 u16 rlen;
3304 u32 data;
3305
3306 rtl_apply_firmware(tp);
3307
3308 /* CHIN EST parameter update */
3309 rtl_writephy(tp, 0x1f, 0x0a43);
3310 rtl_writephy(tp, 0x13, 0x808a);
3311 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3312 rtl_writephy(tp, 0x1f, 0x0000);
3313
3314 /* enable R-tune & PGA-retune function */
3315 rtl_writephy(tp, 0x1f, 0x0a43);
3316 rtl_writephy(tp, 0x13, 0x0811);
3317 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3318 rtl_writephy(tp, 0x1f, 0x0a42);
3319 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3320 rtl_writephy(tp, 0x1f, 0x0000);
3321
3322 /* enable GPHY 10M */
3323 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3324
3325 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3326 data = r8168_mac_ocp_read(tp, 0xdd02);
3327 ioffset_p3 = ((data & 0x80)>>7);
3328 ioffset_p3 <<= 3;
3329
3330 data = r8168_mac_ocp_read(tp, 0xdd00);
3331 ioffset_p3 |= ((data & (0xe000))>>13);
3332 ioffset_p2 = ((data & (0x1e00))>>9);
3333 ioffset_p1 = ((data & (0x01e0))>>5);
3334 ioffset_p0 = ((data & 0x0010)>>4);
3335 ioffset_p0 <<= 3;
3336 ioffset_p0 |= (data & (0x07));
3337 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3338
3339 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3340 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3341 rtl_writephy(tp, 0x1f, 0x0bcf);
3342 rtl_writephy(tp, 0x16, data);
3343 rtl_writephy(tp, 0x1f, 0x0000);
3344 }
3345
3346 /* Modify rlen (TX LPF corner frequency) level */
3347 rtl_writephy(tp, 0x1f, 0x0bcd);
3348 data = rtl_readphy(tp, 0x16);
3349 data &= 0x000f;
3350 rlen = 0;
3351 if (data > 3)
3352 rlen = data - 3;
3353 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3354 rtl_writephy(tp, 0x17, data);
3355 rtl_writephy(tp, 0x1f, 0x0bcd);
3356 rtl_writephy(tp, 0x1f, 0x0000);
3357
3358 /* disable phy pfm mode */
3359 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3360
3361 rtl8168g_disable_aldps(tp);
3362 rtl8168g_config_eee_phy(tp);
3363 rtl_enable_eee(tp);
3364 }
3365
3366 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3367 {
3368 /* Enable PHY auto speed down */
3369 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3370
3371 rtl8168g_phy_adjust_10m_aldps(tp);
3372
3373 /* Enable EEE auto-fallback function */
3374 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3375
3376 /* Enable UC LPF tune function */
3377 rtl_writephy(tp, 0x1f, 0x0a43);
3378 rtl_writephy(tp, 0x13, 0x8012);
3379 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3380 rtl_writephy(tp, 0x1f, 0x0000);
3381
3382 /* set rg_sel_sdm_rate */
3383 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3384
3385 rtl8168g_disable_aldps(tp);
3386 rtl8168g_config_eee_phy(tp);
3387 rtl_enable_eee(tp);
3388 }
3389
3390 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3391 {
3392 rtl8168g_phy_adjust_10m_aldps(tp);
3393
3394 /* Enable UC LPF tune function */
3395 rtl_writephy(tp, 0x1f, 0x0a43);
3396 rtl_writephy(tp, 0x13, 0x8012);
3397 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3398 rtl_writephy(tp, 0x1f, 0x0000);
3399
3400 /* Set rg_sel_sdm_rate */
3401 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3402
3403 /* Channel estimation parameters */
3404 rtl_writephy(tp, 0x1f, 0x0a43);
3405 rtl_writephy(tp, 0x13, 0x80f3);
3406 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3407 rtl_writephy(tp, 0x13, 0x80f0);
3408 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3409 rtl_writephy(tp, 0x13, 0x80ef);
3410 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3411 rtl_writephy(tp, 0x13, 0x80f6);
3412 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3413 rtl_writephy(tp, 0x13, 0x80ec);
3414 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3415 rtl_writephy(tp, 0x13, 0x80ed);
3416 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3417 rtl_writephy(tp, 0x13, 0x80f2);
3418 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3419 rtl_writephy(tp, 0x13, 0x80f4);
3420 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3421 rtl_writephy(tp, 0x1f, 0x0a43);
3422 rtl_writephy(tp, 0x13, 0x8110);
3423 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3424 rtl_writephy(tp, 0x13, 0x810f);
3425 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3426 rtl_writephy(tp, 0x13, 0x8111);
3427 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3428 rtl_writephy(tp, 0x13, 0x8113);
3429 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3430 rtl_writephy(tp, 0x13, 0x8115);
3431 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3432 rtl_writephy(tp, 0x13, 0x810e);
3433 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3434 rtl_writephy(tp, 0x13, 0x810c);
3435 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3436 rtl_writephy(tp, 0x13, 0x810b);
3437 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3438 rtl_writephy(tp, 0x1f, 0x0a43);
3439 rtl_writephy(tp, 0x13, 0x80d1);
3440 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3441 rtl_writephy(tp, 0x13, 0x80cd);
3442 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3443 rtl_writephy(tp, 0x13, 0x80d3);
3444 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3445 rtl_writephy(tp, 0x13, 0x80d5);
3446 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3447 rtl_writephy(tp, 0x13, 0x80d7);
3448 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3449
3450 /* Force PWM-mode */
3451 rtl_writephy(tp, 0x1f, 0x0bcd);
3452 rtl_writephy(tp, 0x14, 0x5065);
3453 rtl_writephy(tp, 0x14, 0xd065);
3454 rtl_writephy(tp, 0x1f, 0x0bc8);
3455 rtl_writephy(tp, 0x12, 0x00ed);
3456 rtl_writephy(tp, 0x1f, 0x0bcd);
3457 rtl_writephy(tp, 0x14, 0x1065);
3458 rtl_writephy(tp, 0x14, 0x9065);
3459 rtl_writephy(tp, 0x14, 0x1065);
3460 rtl_writephy(tp, 0x1f, 0x0000);
3461
3462 rtl8168g_disable_aldps(tp);
3463 rtl8168g_config_eee_phy(tp);
3464 rtl_enable_eee(tp);
3465 }
3466
3467 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3468 {
3469 static const struct phy_reg phy_reg_init[] = {
3470 { 0x1f, 0x0003 },
3471 { 0x08, 0x441d },
3472 { 0x01, 0x9100 },
3473 { 0x1f, 0x0000 }
3474 };
3475
3476 rtl_writephy(tp, 0x1f, 0x0000);
3477 rtl_patchphy(tp, 0x11, 1 << 12);
3478 rtl_patchphy(tp, 0x19, 1 << 13);
3479 rtl_patchphy(tp, 0x10, 1 << 15);
3480
3481 rtl_writephy_batch(tp, phy_reg_init);
3482 }
3483
3484 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3485 {
3486 static const struct phy_reg phy_reg_init[] = {
3487 { 0x1f, 0x0005 },
3488 { 0x1a, 0x0000 },
3489 { 0x1f, 0x0000 },
3490
3491 { 0x1f, 0x0004 },
3492 { 0x1c, 0x0000 },
3493 { 0x1f, 0x0000 },
3494
3495 { 0x1f, 0x0001 },
3496 { 0x15, 0x7701 },
3497 { 0x1f, 0x0000 }
3498 };
3499
3500 /* Disable ALDPS before ram code */
3501 rtl_writephy(tp, 0x1f, 0x0000);
3502 rtl_writephy(tp, 0x18, 0x0310);
3503 msleep(100);
3504
3505 rtl_apply_firmware(tp);
3506
3507 rtl_writephy_batch(tp, phy_reg_init);
3508 }
3509
3510 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3511 {
3512 /* Disable ALDPS before setting firmware */
3513 rtl_writephy(tp, 0x1f, 0x0000);
3514 rtl_writephy(tp, 0x18, 0x0310);
3515 msleep(20);
3516
3517 rtl_apply_firmware(tp);
3518
3519 /* EEE setting */
3520 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3521 rtl_writephy(tp, 0x1f, 0x0004);
3522 rtl_writephy(tp, 0x10, 0x401f);
3523 rtl_writephy(tp, 0x19, 0x7030);
3524 rtl_writephy(tp, 0x1f, 0x0000);
3525 }
3526
3527 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3528 {
3529 static const struct phy_reg phy_reg_init[] = {
3530 { 0x1f, 0x0004 },
3531 { 0x10, 0xc07f },
3532 { 0x19, 0x7030 },
3533 { 0x1f, 0x0000 }
3534 };
3535
3536 /* Disable ALDPS before ram code */
3537 rtl_writephy(tp, 0x1f, 0x0000);
3538 rtl_writephy(tp, 0x18, 0x0310);
3539 msleep(100);
3540
3541 rtl_apply_firmware(tp);
3542
3543 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3544 rtl_writephy_batch(tp, phy_reg_init);
3545
3546 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3547 }
3548
3549 static void rtl_hw_phy_config(struct net_device *dev)
3550 {
3551 static const rtl_generic_fct phy_configs[] = {
3552 /* PCI devices. */
3553 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
3554 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
3555 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
3556 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
3557 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
3558 /* PCI-E devices. */
3559 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
3560 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
3561 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
3562 [RTL_GIGA_MAC_VER_10] = NULL,
3563 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
3564 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config,
3565 [RTL_GIGA_MAC_VER_13] = NULL,
3566 [RTL_GIGA_MAC_VER_14] = NULL,
3567 [RTL_GIGA_MAC_VER_15] = NULL,
3568 [RTL_GIGA_MAC_VER_16] = NULL,
3569 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
3570 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
3571 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
3572 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
3573 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
3574 [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config,
3575 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
3576 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
3577 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
3578 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
3579 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config,
3580 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
3581 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
3582 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
3583 [RTL_GIGA_MAC_VER_31] = NULL,
3584 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
3585 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
3586 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
3587 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
3588 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
3589 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
3590 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
3591 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
3592 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
3593 [RTL_GIGA_MAC_VER_41] = NULL,
3594 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
3595 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
3596 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
3597 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config,
3598 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
3599 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config,
3600 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
3601 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config,
3602 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config,
3603 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
3604 };
3605 struct rtl8169_private *tp = netdev_priv(dev);
3606
3607 if (phy_configs[tp->mac_version])
3608 phy_configs[tp->mac_version](tp);
3609 }
3610
3611 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3612 {
3613 if (!test_and_set_bit(flag, tp->wk.flags))
3614 schedule_work(&tp->wk.work);
3615 }
3616
3617 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3618 {
3619 rtl_hw_phy_config(dev);
3620
3621 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3622 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3623 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3624 netif_dbg(tp, drv, dev,
3625 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3626 RTL_W8(tp, 0x82, 0x01);
3627 }
3628
3629 /* We may have called phy_speed_down before */
3630 phy_speed_up(tp->phydev);
3631
3632 genphy_soft_reset(tp->phydev);
3633 }
3634
3635 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3636 {
3637 rtl_lock_work(tp);
3638
3639 rtl_unlock_config_regs(tp);
3640
3641 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
3642 RTL_R32(tp, MAC4);
3643
3644 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3645 RTL_R32(tp, MAC0);
3646
3647 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3648 rtl_rar_exgmac_set(tp, addr);
3649
3650 rtl_lock_config_regs(tp);
3651
3652 rtl_unlock_work(tp);
3653 }
3654
3655 static int rtl_set_mac_address(struct net_device *dev, void *p)
3656 {
3657 struct rtl8169_private *tp = netdev_priv(dev);
3658 struct device *d = tp_to_dev(tp);
3659 int ret;
3660
3661 ret = eth_mac_addr(dev, p);
3662 if (ret)
3663 return ret;
3664
3665 pm_runtime_get_noresume(d);
3666
3667 if (pm_runtime_active(d))
3668 rtl_rar_set(tp, dev->dev_addr);
3669
3670 pm_runtime_put_noidle(d);
3671
3672 return 0;
3673 }
3674
3675 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3676 {
3677 struct rtl8169_private *tp = netdev_priv(dev);
3678
3679 if (!netif_running(dev))
3680 return -ENODEV;
3681
3682 return phy_mii_ioctl(tp->phydev, ifr, cmd);
3683 }
3684
3685 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3686 {
3687 switch (tp->mac_version) {
3688 case RTL_GIGA_MAC_VER_25:
3689 case RTL_GIGA_MAC_VER_26:
3690 case RTL_GIGA_MAC_VER_29:
3691 case RTL_GIGA_MAC_VER_30:
3692 case RTL_GIGA_MAC_VER_32:
3693 case RTL_GIGA_MAC_VER_33:
3694 case RTL_GIGA_MAC_VER_34:
3695 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
3696 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
3697 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3698 break;
3699 default:
3700 break;
3701 }
3702 }
3703
3704 static void rtl_pll_power_down(struct rtl8169_private *tp)
3705 {
3706 if (r8168_check_dash(tp))
3707 return;
3708
3709 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3710 tp->mac_version == RTL_GIGA_MAC_VER_33)
3711 rtl_ephy_write(tp, 0x19, 0xff64);
3712
3713 if (device_may_wakeup(tp_to_dev(tp))) {
3714 phy_speed_down(tp->phydev, false);
3715 rtl_wol_suspend_quirk(tp);
3716 return;
3717 }
3718
3719 switch (tp->mac_version) {
3720 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
3721 case RTL_GIGA_MAC_VER_37:
3722 case RTL_GIGA_MAC_VER_39:
3723 case RTL_GIGA_MAC_VER_43:
3724 case RTL_GIGA_MAC_VER_44:
3725 case RTL_GIGA_MAC_VER_45:
3726 case RTL_GIGA_MAC_VER_46:
3727 case RTL_GIGA_MAC_VER_47:
3728 case RTL_GIGA_MAC_VER_48:
3729 case RTL_GIGA_MAC_VER_50:
3730 case RTL_GIGA_MAC_VER_51:
3731 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
3732 break;
3733 case RTL_GIGA_MAC_VER_40:
3734 case RTL_GIGA_MAC_VER_41:
3735 case RTL_GIGA_MAC_VER_49:
3736 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
3737 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
3738 break;
3739 default:
3740 break;
3741 }
3742 }
3743
3744 static void rtl_pll_power_up(struct rtl8169_private *tp)
3745 {
3746 switch (tp->mac_version) {
3747 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
3748 case RTL_GIGA_MAC_VER_37:
3749 case RTL_GIGA_MAC_VER_39:
3750 case RTL_GIGA_MAC_VER_43:
3751 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
3752 break;
3753 case RTL_GIGA_MAC_VER_44:
3754 case RTL_GIGA_MAC_VER_45:
3755 case RTL_GIGA_MAC_VER_46:
3756 case RTL_GIGA_MAC_VER_47:
3757 case RTL_GIGA_MAC_VER_48:
3758 case RTL_GIGA_MAC_VER_50:
3759 case RTL_GIGA_MAC_VER_51:
3760 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
3761 break;
3762 case RTL_GIGA_MAC_VER_40:
3763 case RTL_GIGA_MAC_VER_41:
3764 case RTL_GIGA_MAC_VER_49:
3765 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
3766 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
3767 break;
3768 default:
3769 break;
3770 }
3771
3772 phy_resume(tp->phydev);
3773 /* give MAC/PHY some time to resume */
3774 msleep(20);
3775 }
3776
3777 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3778 {
3779 switch (tp->mac_version) {
3780 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
3781 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
3782 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3783 break;
3784 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
3785 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
3786 case RTL_GIGA_MAC_VER_38:
3787 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3788 break;
3789 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
3790 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
3791 break;
3792 default:
3793 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
3794 break;
3795 }
3796 }
3797
3798 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3799 {
3800 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
3801 }
3802
3803 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3804 {
3805 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3806 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
3807 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
3808 }
3809
3810 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3811 {
3812 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3813 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
3814 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
3815 }
3816
3817 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3818 {
3819 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3820 }
3821
3822 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3823 {
3824 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3825 }
3826
3827 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3828 {
3829 RTL_W8(tp, MaxTxPacketSize, 0x3f);
3830 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3831 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
3832 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
3833 }
3834
3835 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3836 {
3837 RTL_W8(tp, MaxTxPacketSize, 0x0c);
3838 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3839 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
3840 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
3841 }
3842
3843 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3844 {
3845 rtl_tx_performance_tweak(tp,
3846 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
3847 }
3848
3849 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3850 {
3851 rtl_tx_performance_tweak(tp,
3852 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
3853 }
3854
3855 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3856 {
3857 r8168b_0_hw_jumbo_enable(tp);
3858
3859 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
3860 }
3861
3862 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3863 {
3864 r8168b_0_hw_jumbo_disable(tp);
3865
3866 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
3867 }
3868
3869 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3870 {
3871 rtl_unlock_config_regs(tp);
3872 switch (tp->mac_version) {
3873 case RTL_GIGA_MAC_VER_11:
3874 r8168b_0_hw_jumbo_enable(tp);
3875 break;
3876 case RTL_GIGA_MAC_VER_12:
3877 case RTL_GIGA_MAC_VER_17:
3878 r8168b_1_hw_jumbo_enable(tp);
3879 break;
3880 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
3881 r8168c_hw_jumbo_enable(tp);
3882 break;
3883 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
3884 r8168dp_hw_jumbo_enable(tp);
3885 break;
3886 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
3887 r8168e_hw_jumbo_enable(tp);
3888 break;
3889 default:
3890 break;
3891 }
3892 rtl_lock_config_regs(tp);
3893 }
3894
3895 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3896 {
3897 rtl_unlock_config_regs(tp);
3898 switch (tp->mac_version) {
3899 case RTL_GIGA_MAC_VER_11:
3900 r8168b_0_hw_jumbo_disable(tp);
3901 break;
3902 case RTL_GIGA_MAC_VER_12:
3903 case RTL_GIGA_MAC_VER_17:
3904 r8168b_1_hw_jumbo_disable(tp);
3905 break;
3906 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
3907 r8168c_hw_jumbo_disable(tp);
3908 break;
3909 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
3910 r8168dp_hw_jumbo_disable(tp);
3911 break;
3912 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
3913 r8168e_hw_jumbo_disable(tp);
3914 break;
3915 default:
3916 break;
3917 }
3918 rtl_lock_config_regs(tp);
3919 }
3920
3921 DECLARE_RTL_COND(rtl_chipcmd_cond)
3922 {
3923 return RTL_R8(tp, ChipCmd) & CmdReset;
3924 }
3925
3926 static void rtl_hw_reset(struct rtl8169_private *tp)
3927 {
3928 RTL_W8(tp, ChipCmd, CmdReset);
3929
3930 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
3931 }
3932
3933 static void rtl_request_firmware(struct rtl8169_private *tp)
3934 {
3935 struct rtl_fw *rtl_fw;
3936
3937 /* firmware loaded already or no firmware available */
3938 if (tp->rtl_fw || !tp->fw_name)
3939 return;
3940
3941 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3942 if (!rtl_fw) {
3943 netif_warn(tp, ifup, tp->dev, "Unable to load firmware, out of memory\n");
3944 return;
3945 }
3946
3947 rtl_fw->phy_write = rtl_writephy;
3948 rtl_fw->phy_read = rtl_readphy;
3949 rtl_fw->mac_mcu_write = mac_mcu_write;
3950 rtl_fw->mac_mcu_read = mac_mcu_read;
3951 rtl_fw->fw_name = tp->fw_name;
3952 rtl_fw->dev = tp_to_dev(tp);
3953
3954 if (rtl_fw_request_firmware(rtl_fw))
3955 kfree(rtl_fw);
3956 else
3957 tp->rtl_fw = rtl_fw;
3958 }
3959
3960 static void rtl_rx_close(struct rtl8169_private *tp)
3961 {
3962 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
3963 }
3964
3965 DECLARE_RTL_COND(rtl_npq_cond)
3966 {
3967 return RTL_R8(tp, TxPoll) & NPQ;
3968 }
3969
3970 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
3971 {
3972 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
3973 }
3974
3975 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3976 {
3977 /* Disable interrupts */
3978 rtl8169_irq_mask_and_ack(tp);
3979
3980 rtl_rx_close(tp);
3981
3982 switch (tp->mac_version) {
3983 case RTL_GIGA_MAC_VER_27:
3984 case RTL_GIGA_MAC_VER_28:
3985 case RTL_GIGA_MAC_VER_31:
3986 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
3987 break;
3988 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
3989 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
3990 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3991 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
3992 break;
3993 default:
3994 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3995 udelay(100);
3996 break;
3997 }
3998
3999 rtl_hw_reset(tp);
4000 }
4001
4002 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4003 {
4004 u32 val = TX_DMA_BURST << TxDMAShift |
4005 InterFrameGap << TxInterFrameGapShift;
4006
4007 if (rtl_is_8168evl_up(tp))
4008 val |= TXCFG_AUTO_FIFO;
4009
4010 RTL_W32(tp, TxConfig, val);
4011 }
4012
4013 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4014 {
4015 /* Low hurts. Let's disable the filtering. */
4016 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4017 }
4018
4019 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4020 {
4021 /*
4022 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4023 * register to be written before TxDescAddrLow to work.
4024 * Switching from MMIO to I/O access fixes the issue as well.
4025 */
4026 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4027 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4028 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4029 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4030 }
4031
4032 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4033 {
4034 u32 val;
4035
4036 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4037 val = 0x000fff00;
4038 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4039 val = 0x00ffff00;
4040 else
4041 return;
4042
4043 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4044 val |= 0xff;
4045
4046 RTL_W32(tp, 0x7c, val);
4047 }
4048
4049 static void rtl_set_rx_mode(struct net_device *dev)
4050 {
4051 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
4052 /* Multicast hash filter */
4053 u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
4054 struct rtl8169_private *tp = netdev_priv(dev);
4055 u32 tmp;
4056
4057 if (dev->flags & IFF_PROMISC) {
4058 /* Unconditionally log net taps. */
4059 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4060 rx_mode |= AcceptAllPhys;
4061 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
4062 dev->flags & IFF_ALLMULTI ||
4063 tp->mac_version == RTL_GIGA_MAC_VER_35) {
4064 /* accept all multicasts */
4065 } else if (netdev_mc_empty(dev)) {
4066 rx_mode &= ~AcceptMulticast;
4067 } else {
4068 struct netdev_hw_addr *ha;
4069
4070 mc_filter[1] = mc_filter[0] = 0;
4071 netdev_for_each_mc_addr(ha, dev) {
4072 u32 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4073 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
4074 }
4075
4076 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4077 tmp = mc_filter[0];
4078 mc_filter[0] = swab32(mc_filter[1]);
4079 mc_filter[1] = swab32(tmp);
4080 }
4081 }
4082
4083 if (dev->features & NETIF_F_RXALL)
4084 rx_mode |= (AcceptErr | AcceptRunt);
4085
4086 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4087 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4088
4089 tmp = RTL_R32(tp, RxConfig);
4090 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_MASK) | rx_mode);
4091 }
4092
4093 DECLARE_RTL_COND(rtl_csiar_cond)
4094 {
4095 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4096 }
4097
4098 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4099 {
4100 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4101
4102 RTL_W32(tp, CSIDR, value);
4103 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4104 CSIAR_BYTE_ENABLE | func << 16);
4105
4106 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4107 }
4108
4109 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4110 {
4111 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4112
4113 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4114 CSIAR_BYTE_ENABLE);
4115
4116 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4117 RTL_R32(tp, CSIDR) : ~0;
4118 }
4119
4120 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4121 {
4122 struct pci_dev *pdev = tp->pci_dev;
4123 u32 csi;
4124
4125 /* According to Realtek the value at config space address 0x070f
4126 * controls the L0s/L1 entrance latency. We try standard ECAM access
4127 * first and if it fails fall back to CSI.
4128 */
4129 if (pdev->cfg_size > 0x070f &&
4130 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4131 return;
4132
4133 netdev_notice_once(tp->dev,
4134 "No native access to PCI extended config space, falling back to CSI\n");
4135 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4136 rtl_csi_write(tp, 0x070c, csi | val << 24);
4137 }
4138
4139 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4140 {
4141 rtl_csi_access_enable(tp, 0x27);
4142 }
4143
4144 struct ephy_info {
4145 unsigned int offset;
4146 u16 mask;
4147 u16 bits;
4148 };
4149
4150 static void __rtl_ephy_init(struct rtl8169_private *tp,
4151 const struct ephy_info *e, int len)
4152 {
4153 u16 w;
4154
4155 while (len-- > 0) {
4156 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4157 rtl_ephy_write(tp, e->offset, w);
4158 e++;
4159 }
4160 }
4161
4162 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
4163
4164 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4165 {
4166 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4167 PCI_EXP_LNKCTL_CLKREQ_EN);
4168 }
4169
4170 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4171 {
4172 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4173 PCI_EXP_LNKCTL_CLKREQ_EN);
4174 }
4175
4176 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
4177 {
4178 /* work around an issue when PCI reset occurs during L2/L3 state */
4179 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
4180 }
4181
4182 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4183 {
4184 /* Don't enable ASPM in the chip if OS can't control ASPM */
4185 if (enable && tp->aspm_manageable) {
4186 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4187 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4188 } else {
4189 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4190 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4191 }
4192
4193 udelay(10);
4194 }
4195
4196 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
4197 u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
4198 {
4199 /* Usage of dynamic vs. static FIFO is controlled by bit
4200 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
4201 */
4202 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
4203 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
4204 }
4205
4206 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
4207 u8 low, u8 high)
4208 {
4209 /* FIFO thresholds for pause flow control */
4210 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
4211 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
4212 }
4213
4214 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4215 {
4216 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4217
4218 if (tp->dev->mtu <= ETH_DATA_LEN) {
4219 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4220 PCI_EXP_DEVCTL_NOSNOOP_EN);
4221 }
4222 }
4223
4224 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4225 {
4226 rtl_hw_start_8168bb(tp);
4227
4228 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4229 }
4230
4231 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4232 {
4233 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4234
4235 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4236
4237 if (tp->dev->mtu <= ETH_DATA_LEN)
4238 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4239
4240 rtl_disable_clock_request(tp);
4241 }
4242
4243 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4244 {
4245 static const struct ephy_info e_info_8168cp[] = {
4246 { 0x01, 0, 0x0001 },
4247 { 0x02, 0x0800, 0x1000 },
4248 { 0x03, 0, 0x0042 },
4249 { 0x06, 0x0080, 0x0000 },
4250 { 0x07, 0, 0x2000 }
4251 };
4252
4253 rtl_set_def_aspm_entry_latency(tp);
4254
4255 rtl_ephy_init(tp, e_info_8168cp);
4256
4257 __rtl_hw_start_8168cp(tp);
4258 }
4259
4260 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4261 {
4262 rtl_set_def_aspm_entry_latency(tp);
4263
4264 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4265
4266 if (tp->dev->mtu <= ETH_DATA_LEN)
4267 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4268 }
4269
4270 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4271 {
4272 rtl_set_def_aspm_entry_latency(tp);
4273
4274 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4275
4276 /* Magic. */
4277 RTL_W8(tp, DBG_REG, 0x20);
4278
4279 if (tp->dev->mtu <= ETH_DATA_LEN)
4280 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4281 }
4282
4283 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4284 {
4285 static const struct ephy_info e_info_8168c_1[] = {
4286 { 0x02, 0x0800, 0x1000 },
4287 { 0x03, 0, 0x0002 },
4288 { 0x06, 0x0080, 0x0000 }
4289 };
4290
4291 rtl_set_def_aspm_entry_latency(tp);
4292
4293 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4294
4295 rtl_ephy_init(tp, e_info_8168c_1);
4296
4297 __rtl_hw_start_8168cp(tp);
4298 }
4299
4300 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4301 {
4302 static const struct ephy_info e_info_8168c_2[] = {
4303 { 0x01, 0, 0x0001 },
4304 { 0x03, 0x0400, 0x0020 }
4305 };
4306
4307 rtl_set_def_aspm_entry_latency(tp);
4308
4309 rtl_ephy_init(tp, e_info_8168c_2);
4310
4311 __rtl_hw_start_8168cp(tp);
4312 }
4313
4314 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4315 {
4316 rtl_hw_start_8168c_2(tp);
4317 }
4318
4319 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4320 {
4321 rtl_set_def_aspm_entry_latency(tp);
4322
4323 __rtl_hw_start_8168cp(tp);
4324 }
4325
4326 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4327 {
4328 rtl_set_def_aspm_entry_latency(tp);
4329
4330 rtl_disable_clock_request(tp);
4331
4332 if (tp->dev->mtu <= ETH_DATA_LEN)
4333 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4334 }
4335
4336 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4337 {
4338 rtl_set_def_aspm_entry_latency(tp);
4339
4340 if (tp->dev->mtu <= ETH_DATA_LEN)
4341 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4342
4343 rtl_disable_clock_request(tp);
4344 }
4345
4346 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4347 {
4348 static const struct ephy_info e_info_8168d_4[] = {
4349 { 0x0b, 0x0000, 0x0048 },
4350 { 0x19, 0x0020, 0x0050 },
4351 { 0x0c, 0x0100, 0x0020 },
4352 { 0x10, 0x0004, 0x0000 },
4353 };
4354
4355 rtl_set_def_aspm_entry_latency(tp);
4356
4357 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4358
4359 rtl_ephy_init(tp, e_info_8168d_4);
4360
4361 rtl_enable_clock_request(tp);
4362 }
4363
4364 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4365 {
4366 static const struct ephy_info e_info_8168e_1[] = {
4367 { 0x00, 0x0200, 0x0100 },
4368 { 0x00, 0x0000, 0x0004 },
4369 { 0x06, 0x0002, 0x0001 },
4370 { 0x06, 0x0000, 0x0030 },
4371 { 0x07, 0x0000, 0x2000 },
4372 { 0x00, 0x0000, 0x0020 },
4373 { 0x03, 0x5800, 0x2000 },
4374 { 0x03, 0x0000, 0x0001 },
4375 { 0x01, 0x0800, 0x1000 },
4376 { 0x07, 0x0000, 0x4000 },
4377 { 0x1e, 0x0000, 0x2000 },
4378 { 0x19, 0xffff, 0xfe6c },
4379 { 0x0a, 0x0000, 0x0040 }
4380 };
4381
4382 rtl_set_def_aspm_entry_latency(tp);
4383
4384 rtl_ephy_init(tp, e_info_8168e_1);
4385
4386 if (tp->dev->mtu <= ETH_DATA_LEN)
4387 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4388
4389 rtl_disable_clock_request(tp);
4390
4391 /* Reset tx FIFO pointer */
4392 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4393 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4394
4395 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4396 }
4397
4398 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4399 {
4400 static const struct ephy_info e_info_8168e_2[] = {
4401 { 0x09, 0x0000, 0x0080 },
4402 { 0x19, 0x0000, 0x0224 },
4403 { 0x00, 0x0000, 0x0004 },
4404 { 0x0c, 0x3df0, 0x0200 },
4405 };
4406
4407 rtl_set_def_aspm_entry_latency(tp);
4408
4409 rtl_ephy_init(tp, e_info_8168e_2);
4410
4411 if (tp->dev->mtu <= ETH_DATA_LEN)
4412 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4413
4414 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4415 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4416 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4417 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4418 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
4419 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4420 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4421
4422 rtl_disable_clock_request(tp);
4423
4424 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4425
4426 rtl8168_config_eee_mac(tp);
4427
4428 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4429 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4430 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4431
4432 rtl_hw_aspm_clkreq_enable(tp, true);
4433 }
4434
4435 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
4436 {
4437 rtl_set_def_aspm_entry_latency(tp);
4438
4439 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4440
4441 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4442 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4443 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4444 rtl_reset_packet_filter(tp);
4445 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4446 rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));
4447 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4448 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
4449
4450 rtl_disable_clock_request(tp);
4451
4452 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4453 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4454 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4455 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4456
4457 rtl8168_config_eee_mac(tp);
4458 }
4459
4460 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
4461 {
4462 static const struct ephy_info e_info_8168f_1[] = {
4463 { 0x06, 0x00c0, 0x0020 },
4464 { 0x08, 0x0001, 0x0002 },
4465 { 0x09, 0x0000, 0x0080 },
4466 { 0x19, 0x0000, 0x0224 },
4467 { 0x00, 0x0000, 0x0004 },
4468 { 0x0c, 0x3df0, 0x0200 },
4469 };
4470
4471 rtl_hw_start_8168f(tp);
4472
4473 rtl_ephy_init(tp, e_info_8168f_1);
4474
4475 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4476 }
4477
4478 static void rtl_hw_start_8411(struct rtl8169_private *tp)
4479 {
4480 static const struct ephy_info e_info_8168f_1[] = {
4481 { 0x06, 0x00c0, 0x0020 },
4482 { 0x0f, 0xffff, 0x5200 },
4483 { 0x19, 0x0000, 0x0224 },
4484 { 0x00, 0x0000, 0x0004 },
4485 { 0x0c, 0x3df0, 0x0200 },
4486 };
4487
4488 rtl_hw_start_8168f(tp);
4489 rtl_pcie_state_l2l3_disable(tp);
4490
4491 rtl_ephy_init(tp, e_info_8168f_1);
4492
4493 rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);
4494 }
4495
4496 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
4497 {
4498 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4499 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4500
4501 rtl_set_def_aspm_entry_latency(tp);
4502
4503 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4504
4505 rtl_reset_packet_filter(tp);
4506 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
4507
4508 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4509
4510 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4511 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4512
4513 rtl8168_config_eee_mac(tp);
4514
4515 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
4516 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4517
4518 rtl_pcie_state_l2l3_disable(tp);
4519 }
4520
4521 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
4522 {
4523 static const struct ephy_info e_info_8168g_1[] = {
4524 { 0x00, 0x0008, 0x0000 },
4525 { 0x0c, 0x3ff0, 0x0820 },
4526 { 0x1e, 0x0000, 0x0001 },
4527 { 0x19, 0x8000, 0x0000 }
4528 };
4529
4530 rtl_hw_start_8168g(tp);
4531
4532 /* disable aspm and clock request before access ephy */
4533 rtl_hw_aspm_clkreq_enable(tp, false);
4534 rtl_ephy_init(tp, e_info_8168g_1);
4535 rtl_hw_aspm_clkreq_enable(tp, true);
4536 }
4537
4538 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
4539 {
4540 static const struct ephy_info e_info_8168g_2[] = {
4541 { 0x00, 0x0008, 0x0000 },
4542 { 0x0c, 0x3ff0, 0x0820 },
4543 { 0x19, 0xffff, 0x7c00 },
4544 { 0x1e, 0xffff, 0x20eb },
4545 { 0x0d, 0xffff, 0x1666 },
4546 { 0x00, 0xffff, 0x10a3 },
4547 { 0x06, 0xffff, 0xf050 },
4548 { 0x04, 0x0000, 0x0010 },
4549 { 0x1d, 0x4000, 0x0000 },
4550 };
4551
4552 rtl_hw_start_8168g(tp);
4553
4554 /* disable aspm and clock request before access ephy */
4555 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4556 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4557 rtl_ephy_init(tp, e_info_8168g_2);
4558 }
4559
4560 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
4561 {
4562 static const struct ephy_info e_info_8411_2[] = {
4563 { 0x00, 0x0008, 0x0000 },
4564 { 0x0c, 0x37d0, 0x0820 },
4565 { 0x1e, 0x0000, 0x0001 },
4566 { 0x19, 0x8021, 0x0000 },
4567 { 0x1e, 0x0000, 0x2000 },
4568 { 0x0d, 0x0100, 0x0200 },
4569 { 0x00, 0x0000, 0x0080 },
4570 { 0x06, 0x0000, 0x0010 },
4571 { 0x04, 0x0000, 0x0010 },
4572 { 0x1d, 0x0000, 0x4000 },
4573 };
4574
4575 rtl_hw_start_8168g(tp);
4576
4577 /* disable aspm and clock request before access ephy */
4578 rtl_hw_aspm_clkreq_enable(tp, false);
4579 rtl_ephy_init(tp, e_info_8411_2);
4580
4581 /* The following Realtek-provided magic fixes an issue with the RX unit
4582 * getting confused after the PHY having been powered-down.
4583 */
4584 r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
4585 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
4586 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
4587 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
4588 r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
4589 r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
4590 r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
4591 r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
4592 mdelay(3);
4593 r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
4594
4595 r8168_mac_ocp_write(tp, 0xF800, 0xE008);
4596 r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
4597 r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
4598 r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
4599 r8168_mac_ocp_write(tp, 0xF808, 0xE027);
4600 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
4601 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
4602 r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
4603 r8168_mac_ocp_write(tp, 0xF810, 0xC602);
4604 r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
4605 r8168_mac_ocp_write(tp, 0xF814, 0x0000);
4606 r8168_mac_ocp_write(tp, 0xF816, 0xC502);
4607 r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
4608 r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
4609 r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
4610 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
4611 r8168_mac_ocp_write(tp, 0xF820, 0x080A);
4612 r8168_mac_ocp_write(tp, 0xF822, 0x6420);
4613 r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
4614 r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
4615 r8168_mac_ocp_write(tp, 0xF828, 0xC516);
4616 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
4617 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
4618 r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
4619 r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
4620 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
4621 r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
4622 r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
4623 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
4624 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
4625 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
4626 r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
4627 r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
4628 r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
4629 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
4630 r8168_mac_ocp_write(tp, 0xF846, 0xC404);
4631 r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
4632 r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
4633 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
4634 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
4635 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
4636 r8168_mac_ocp_write(tp, 0xF852, 0xE434);
4637 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
4638 r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
4639 r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
4640 r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
4641 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
4642 r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
4643 r8168_mac_ocp_write(tp, 0xF860, 0xF007);
4644 r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
4645 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
4646 r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
4647 r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
4648 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
4649 r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
4650 r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
4651 r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
4652 r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
4653 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
4654 r8168_mac_ocp_write(tp, 0xF876, 0xC516);
4655 r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
4656 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
4657 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
4658 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
4659 r8168_mac_ocp_write(tp, 0xF880, 0xC512);
4660 r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
4661 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
4662 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
4663 r8168_mac_ocp_write(tp, 0xF888, 0x483F);
4664 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
4665 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
4666 r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
4667 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
4668 r8168_mac_ocp_write(tp, 0xF892, 0xC505);
4669 r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
4670 r8168_mac_ocp_write(tp, 0xF896, 0xC502);
4671 r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
4672 r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
4673 r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
4674 r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
4675 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
4676 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
4677 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
4678 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
4679 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
4680 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
4681 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
4682 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
4683 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
4684 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
4685 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
4686 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
4687 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
4688 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
4689 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
4690 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
4691 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
4692 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
4693 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
4694 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
4695 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
4696 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
4697 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
4698 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
4699 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
4700 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
4701 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
4702 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
4703 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
4704 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
4705 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
4706
4707 r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
4708
4709 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
4710 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
4711 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
4712 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
4713 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
4714 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
4715 r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
4716
4717 rtl_hw_aspm_clkreq_enable(tp, true);
4718 }
4719
4720 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
4721 {
4722 static const struct ephy_info e_info_8168h_1[] = {
4723 { 0x1e, 0x0800, 0x0001 },
4724 { 0x1d, 0x0000, 0x0800 },
4725 { 0x05, 0xffff, 0x2089 },
4726 { 0x06, 0xffff, 0x5881 },
4727 { 0x04, 0xffff, 0x854a },
4728 { 0x01, 0xffff, 0x068b }
4729 };
4730 int rg_saw_cnt;
4731
4732 /* disable aspm and clock request before access ephy */
4733 rtl_hw_aspm_clkreq_enable(tp, false);
4734 rtl_ephy_init(tp, e_info_8168h_1);
4735
4736 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4737 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4738
4739 rtl_set_def_aspm_entry_latency(tp);
4740
4741 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4742
4743 rtl_reset_packet_filter(tp);
4744
4745 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
4746
4747 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);
4748
4749 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
4750
4751 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4752
4753 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4754 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4755
4756 rtl8168_config_eee_mac(tp);
4757
4758 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4759 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4760
4761 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
4762
4763 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4764
4765 rtl_pcie_state_l2l3_disable(tp);
4766
4767 rtl_writephy(tp, 0x1f, 0x0c42);
4768 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
4769 rtl_writephy(tp, 0x1f, 0x0000);
4770 if (rg_saw_cnt > 0) {
4771 u16 sw_cnt_1ms_ini;
4772
4773 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
4774 sw_cnt_1ms_ini &= 0x0fff;
4775 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
4776 }
4777
4778 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
4779 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
4780 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
4781 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
4782
4783 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
4784 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
4785 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
4786 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
4787
4788 rtl_hw_aspm_clkreq_enable(tp, true);
4789 }
4790
4791 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
4792 {
4793 rtl8168ep_stop_cmac(tp);
4794
4795 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4796 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
4797
4798 rtl_set_def_aspm_entry_latency(tp);
4799
4800 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4801
4802 rtl_reset_packet_filter(tp);
4803
4804 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
4805
4806 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
4807
4808 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4809
4810 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4811 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4812
4813 rtl8168_config_eee_mac(tp);
4814
4815 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
4816
4817 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
4818
4819 rtl_pcie_state_l2l3_disable(tp);
4820 }
4821
4822 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
4823 {
4824 static const struct ephy_info e_info_8168ep_1[] = {
4825 { 0x00, 0xffff, 0x10ab },
4826 { 0x06, 0xffff, 0xf030 },
4827 { 0x08, 0xffff, 0x2006 },
4828 { 0x0d, 0xffff, 0x1666 },
4829 { 0x0c, 0x3ff0, 0x0000 }
4830 };
4831
4832 /* disable aspm and clock request before access ephy */
4833 rtl_hw_aspm_clkreq_enable(tp, false);
4834 rtl_ephy_init(tp, e_info_8168ep_1);
4835
4836 rtl_hw_start_8168ep(tp);
4837
4838 rtl_hw_aspm_clkreq_enable(tp, true);
4839 }
4840
4841 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
4842 {
4843 static const struct ephy_info e_info_8168ep_2[] = {
4844 { 0x00, 0xffff, 0x10a3 },
4845 { 0x19, 0xffff, 0xfc00 },
4846 { 0x1e, 0xffff, 0x20ea }
4847 };
4848
4849 /* disable aspm and clock request before access ephy */
4850 rtl_hw_aspm_clkreq_enable(tp, false);
4851 rtl_ephy_init(tp, e_info_8168ep_2);
4852
4853 rtl_hw_start_8168ep(tp);
4854
4855 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4856 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4857
4858 rtl_hw_aspm_clkreq_enable(tp, true);
4859 }
4860
4861 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
4862 {
4863 static const struct ephy_info e_info_8168ep_3[] = {
4864 { 0x00, 0x0000, 0x0080 },
4865 { 0x0d, 0x0100, 0x0200 },
4866 { 0x19, 0x8021, 0x0000 },
4867 { 0x1e, 0x0000, 0x2000 },
4868 };
4869
4870 /* disable aspm and clock request before access ephy */
4871 rtl_hw_aspm_clkreq_enable(tp, false);
4872 rtl_ephy_init(tp, e_info_8168ep_3);
4873
4874 rtl_hw_start_8168ep(tp);
4875
4876 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4877 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4878
4879 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
4880 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
4881 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
4882
4883 rtl_hw_aspm_clkreq_enable(tp, true);
4884 }
4885
4886 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
4887 {
4888 static const struct ephy_info e_info_8102e_1[] = {
4889 { 0x01, 0, 0x6e65 },
4890 { 0x02, 0, 0x091f },
4891 { 0x03, 0, 0xc2f9 },
4892 { 0x06, 0, 0xafb5 },
4893 { 0x07, 0, 0x0e00 },
4894 { 0x19, 0, 0xec80 },
4895 { 0x01, 0, 0x2e65 },
4896 { 0x01, 0, 0x6e65 }
4897 };
4898 u8 cfg1;
4899
4900 rtl_set_def_aspm_entry_latency(tp);
4901
4902 RTL_W8(tp, DBG_REG, FIX_NAK_1);
4903
4904 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4905
4906 RTL_W8(tp, Config1,
4907 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4908 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4909
4910 cfg1 = RTL_R8(tp, Config1);
4911 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4912 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
4913
4914 rtl_ephy_init(tp, e_info_8102e_1);
4915 }
4916
4917 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
4918 {
4919 rtl_set_def_aspm_entry_latency(tp);
4920
4921 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4922
4923 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
4924 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4925 }
4926
4927 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
4928 {
4929 rtl_hw_start_8102e_2(tp);
4930
4931 rtl_ephy_write(tp, 0x03, 0xc2f9);
4932 }
4933
4934 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
4935 {
4936 static const struct ephy_info e_info_8105e_1[] = {
4937 { 0x07, 0, 0x4000 },
4938 { 0x19, 0, 0x0200 },
4939 { 0x19, 0, 0x0020 },
4940 { 0x1e, 0, 0x2000 },
4941 { 0x03, 0, 0x0001 },
4942 { 0x19, 0, 0x0100 },
4943 { 0x19, 0, 0x0004 },
4944 { 0x0a, 0, 0x0020 }
4945 };
4946
4947 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4948 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
4949
4950 /* Disable Early Tally Counter */
4951 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
4952
4953 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
4954 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4955
4956 rtl_ephy_init(tp, e_info_8105e_1);
4957
4958 rtl_pcie_state_l2l3_disable(tp);
4959 }
4960
4961 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
4962 {
4963 rtl_hw_start_8105e_1(tp);
4964 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
4965 }
4966
4967 static void rtl_hw_start_8402(struct rtl8169_private *tp)
4968 {
4969 static const struct ephy_info e_info_8402[] = {
4970 { 0x19, 0xffff, 0xff64 },
4971 { 0x1e, 0, 0x4000 }
4972 };
4973
4974 rtl_set_def_aspm_entry_latency(tp);
4975
4976 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4977 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
4978
4979 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4980
4981 rtl_ephy_init(tp, e_info_8402);
4982
4983 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4984
4985 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
4986 rtl_reset_packet_filter(tp);
4987 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4988 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4989 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
4990
4991 rtl_pcie_state_l2l3_disable(tp);
4992 }
4993
4994 static void rtl_hw_start_8106(struct rtl8169_private *tp)
4995 {
4996 rtl_hw_aspm_clkreq_enable(tp, false);
4997
4998 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4999 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5000
5001 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5002 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5003 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5004
5005 rtl_pcie_state_l2l3_disable(tp);
5006 rtl_hw_aspm_clkreq_enable(tp, true);
5007 }
5008
5009 static void rtl_hw_config(struct rtl8169_private *tp)
5010 {
5011 static const rtl_generic_fct hw_configs[] = {
5012 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
5013 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
5014 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
5015 [RTL_GIGA_MAC_VER_10] = NULL,
5016 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168bb,
5017 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168bef,
5018 [RTL_GIGA_MAC_VER_13] = NULL,
5019 [RTL_GIGA_MAC_VER_14] = NULL,
5020 [RTL_GIGA_MAC_VER_15] = NULL,
5021 [RTL_GIGA_MAC_VER_16] = NULL,
5022 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168bef,
5023 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
5024 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
5025 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
5026 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
5027 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
5028 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
5029 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
5030 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
5031 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
5032 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
5033 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
5034 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
5035 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
5036 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168dp,
5037 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
5038 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
5039 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
5040 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
5041 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
5042 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
5043 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
5044 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
5045 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
5046 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
5047 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
5048 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
5049 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
5050 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
5051 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
5052 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
5053 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
5054 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
5055 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
5056 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
5057 };
5058
5059 if (hw_configs[tp->mac_version])
5060 hw_configs[tp->mac_version](tp);
5061 }
5062
5063 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5064 {
5065 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5066 tp->mac_version == RTL_GIGA_MAC_VER_16)
5067 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5068 PCI_EXP_DEVCTL_NOSNOOP_EN);
5069
5070 if (rtl_is_8168evl_up(tp))
5071 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5072 else
5073 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5074
5075 rtl_hw_config(tp);
5076 }
5077
5078 static void rtl_hw_start_8169(struct rtl8169_private *tp)
5079 {
5080 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5081 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
5082
5083 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
5084
5085 tp->cp_cmd |= PCIMulRW;
5086
5087 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5088 tp->mac_version == RTL_GIGA_MAC_VER_03) {
5089 netif_dbg(tp, drv, tp->dev,
5090 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
5091 tp->cp_cmd |= (1 << 14);
5092 }
5093
5094 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5095
5096 rtl8169_set_magic_reg(tp, tp->mac_version);
5097
5098 RTL_W32(tp, RxMissed, 0);
5099 }
5100
5101 static void rtl_hw_start(struct rtl8169_private *tp)
5102 {
5103 rtl_unlock_config_regs(tp);
5104
5105 tp->cp_cmd &= CPCMD_MASK;
5106 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5107
5108 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5109 rtl_hw_start_8169(tp);
5110 else
5111 rtl_hw_start_8168(tp);
5112
5113 rtl_set_rx_max_size(tp);
5114 rtl_set_rx_tx_desc_registers(tp);
5115 rtl_lock_config_regs(tp);
5116
5117 /* disable interrupt coalescing */
5118 RTL_W16(tp, IntrMitigate, 0x0000);
5119 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5120 RTL_R8(tp, IntrMask);
5121 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
5122 rtl_init_rxcfg(tp);
5123 rtl_set_tx_config_registers(tp);
5124 rtl_set_rx_mode(tp->dev);
5125 rtl_irq_enable(tp);
5126 }
5127
5128 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5129 {
5130 struct rtl8169_private *tp = netdev_priv(dev);
5131
5132 if (new_mtu > ETH_DATA_LEN)
5133 rtl_hw_jumbo_enable(tp);
5134 else
5135 rtl_hw_jumbo_disable(tp);
5136
5137 dev->mtu = new_mtu;
5138 netdev_update_features(dev);
5139
5140 return 0;
5141 }
5142
5143 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5144 {
5145 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5146 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5147 }
5148
5149 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5150 {
5151 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5152
5153 /* Force memory writes to complete before releasing descriptor */
5154 dma_wmb();
5155
5156 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5157 }
5158
5159 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5160 struct RxDesc *desc)
5161 {
5162 struct device *d = tp_to_dev(tp);
5163 int node = dev_to_node(d);
5164 dma_addr_t mapping;
5165 struct page *data;
5166
5167 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
5168 if (!data)
5169 return NULL;
5170
5171 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5172 if (unlikely(dma_mapping_error(d, mapping))) {
5173 if (net_ratelimit())
5174 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5175 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
5176 return NULL;
5177 }
5178
5179 desc->addr = cpu_to_le64(mapping);
5180 rtl8169_mark_to_asic(desc);
5181
5182 return data;
5183 }
5184
5185 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5186 {
5187 unsigned int i;
5188
5189 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
5190 dma_unmap_page(tp_to_dev(tp),
5191 le64_to_cpu(tp->RxDescArray[i].addr),
5192 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5193 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
5194 tp->Rx_databuff[i] = NULL;
5195 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5196 }
5197 }
5198
5199 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5200 {
5201 desc->opts1 |= cpu_to_le32(RingEnd);
5202 }
5203
5204 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5205 {
5206 unsigned int i;
5207
5208 for (i = 0; i < NUM_RX_DESC; i++) {
5209 struct page *data;
5210
5211 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5212 if (!data) {
5213 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5214 goto err_out;
5215 }
5216 tp->Rx_databuff[i] = data;
5217 }
5218
5219 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5220 return 0;
5221
5222 err_out:
5223 rtl8169_rx_clear(tp);
5224 return -ENOMEM;
5225 }
5226
5227 static int rtl8169_init_ring(struct rtl8169_private *tp)
5228 {
5229 rtl8169_init_ring_indexes(tp);
5230
5231 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5232 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5233
5234 return rtl8169_rx_fill(tp);
5235 }
5236
5237 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5238 struct TxDesc *desc)
5239 {
5240 unsigned int len = tx_skb->len;
5241
5242 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5243
5244 desc->opts1 = 0x00;
5245 desc->opts2 = 0x00;
5246 desc->addr = 0x00;
5247 tx_skb->len = 0;
5248 }
5249
5250 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5251 unsigned int n)
5252 {
5253 unsigned int i;
5254
5255 for (i = 0; i < n; i++) {
5256 unsigned int entry = (start + i) % NUM_TX_DESC;
5257 struct ring_info *tx_skb = tp->tx_skb + entry;
5258 unsigned int len = tx_skb->len;
5259
5260 if (len) {
5261 struct sk_buff *skb = tx_skb->skb;
5262
5263 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5264 tp->TxDescArray + entry);
5265 if (skb) {
5266 dev_consume_skb_any(skb);
5267 tx_skb->skb = NULL;
5268 }
5269 }
5270 }
5271 }
5272
5273 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5274 {
5275 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5276 tp->cur_tx = tp->dirty_tx = 0;
5277 netdev_reset_queue(tp->dev);
5278 }
5279
5280 static void rtl_reset_work(struct rtl8169_private *tp)
5281 {
5282 struct net_device *dev = tp->dev;
5283 int i;
5284
5285 napi_disable(&tp->napi);
5286 netif_stop_queue(dev);
5287 synchronize_rcu();
5288
5289 rtl8169_hw_reset(tp);
5290
5291 for (i = 0; i < NUM_RX_DESC; i++)
5292 rtl8169_mark_to_asic(tp->RxDescArray + i);
5293
5294 rtl8169_tx_clear(tp);
5295 rtl8169_init_ring_indexes(tp);
5296
5297 napi_enable(&tp->napi);
5298 rtl_hw_start(tp);
5299 netif_wake_queue(dev);
5300 }
5301
5302 static void rtl8169_tx_timeout(struct net_device *dev)
5303 {
5304 struct rtl8169_private *tp = netdev_priv(dev);
5305
5306 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5307 }
5308
5309 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5310 {
5311 u32 status = opts0 | len;
5312
5313 if (entry == NUM_TX_DESC - 1)
5314 status |= RingEnd;
5315
5316 return cpu_to_le32(status);
5317 }
5318
5319 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5320 u32 *opts)
5321 {
5322 struct skb_shared_info *info = skb_shinfo(skb);
5323 unsigned int cur_frag, entry;
5324 struct TxDesc *uninitialized_var(txd);
5325 struct device *d = tp_to_dev(tp);
5326
5327 entry = tp->cur_tx;
5328 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5329 const skb_frag_t *frag = info->frags + cur_frag;
5330 dma_addr_t mapping;
5331 u32 len;
5332 void *addr;
5333
5334 entry = (entry + 1) % NUM_TX_DESC;
5335
5336 txd = tp->TxDescArray + entry;
5337 len = skb_frag_size(frag);
5338 addr = skb_frag_address(frag);
5339 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5340 if (unlikely(dma_mapping_error(d, mapping))) {
5341 if (net_ratelimit())
5342 netif_err(tp, drv, tp->dev,
5343 "Failed to map TX fragments DMA!\n");
5344 goto err_out;
5345 }
5346
5347 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5348 txd->opts2 = cpu_to_le32(opts[1]);
5349 txd->addr = cpu_to_le64(mapping);
5350
5351 tp->tx_skb[entry].len = len;
5352 }
5353
5354 if (cur_frag) {
5355 tp->tx_skb[entry].skb = skb;
5356 txd->opts1 |= cpu_to_le32(LastFrag);
5357 }
5358
5359 return cur_frag;
5360
5361 err_out:
5362 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5363 return -EIO;
5364 }
5365
5366 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5367 {
5368 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5369 }
5370
5371 /* msdn_giant_send_check()
5372 * According to the document of microsoft, the TCP Pseudo Header excludes the
5373 * packet length for IPv6 TCP large packets.
5374 */
5375 static int msdn_giant_send_check(struct sk_buff *skb)
5376 {
5377 const struct ipv6hdr *ipv6h;
5378 struct tcphdr *th;
5379 int ret;
5380
5381 ret = skb_cow_head(skb, 0);
5382 if (ret)
5383 return ret;
5384
5385 ipv6h = ipv6_hdr(skb);
5386 th = tcp_hdr(skb);
5387
5388 th->check = 0;
5389 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5390
5391 return ret;
5392 }
5393
5394 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
5395 {
5396 u32 mss = skb_shinfo(skb)->gso_size;
5397
5398 if (mss) {
5399 opts[0] |= TD_LSO;
5400 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5401 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5402 const struct iphdr *ip = ip_hdr(skb);
5403
5404 if (ip->protocol == IPPROTO_TCP)
5405 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5406 else if (ip->protocol == IPPROTO_UDP)
5407 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5408 else
5409 WARN_ON_ONCE(1);
5410 }
5411 }
5412
5413 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5414 struct sk_buff *skb, u32 *opts)
5415 {
5416 u32 transport_offset = (u32)skb_transport_offset(skb);
5417 u32 mss = skb_shinfo(skb)->gso_size;
5418
5419 if (mss) {
5420 switch (vlan_get_protocol(skb)) {
5421 case htons(ETH_P_IP):
5422 opts[0] |= TD1_GTSENV4;
5423 break;
5424
5425 case htons(ETH_P_IPV6):
5426 if (msdn_giant_send_check(skb))
5427 return false;
5428
5429 opts[0] |= TD1_GTSENV6;
5430 break;
5431
5432 default:
5433 WARN_ON_ONCE(1);
5434 break;
5435 }
5436
5437 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5438 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
5439 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5440 u8 ip_protocol;
5441
5442 switch (vlan_get_protocol(skb)) {
5443 case htons(ETH_P_IP):
5444 opts[1] |= TD1_IPv4_CS;
5445 ip_protocol = ip_hdr(skb)->protocol;
5446 break;
5447
5448 case htons(ETH_P_IPV6):
5449 opts[1] |= TD1_IPv6_CS;
5450 ip_protocol = ipv6_hdr(skb)->nexthdr;
5451 break;
5452
5453 default:
5454 ip_protocol = IPPROTO_RAW;
5455 break;
5456 }
5457
5458 if (ip_protocol == IPPROTO_TCP)
5459 opts[1] |= TD1_TCP_CS;
5460 else if (ip_protocol == IPPROTO_UDP)
5461 opts[1] |= TD1_UDP_CS;
5462 else
5463 WARN_ON_ONCE(1);
5464
5465 opts[1] |= transport_offset << TCPHO_SHIFT;
5466 } else {
5467 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5468 return !eth_skb_pad(skb);
5469 }
5470
5471 return true;
5472 }
5473
5474 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
5475 unsigned int nr_frags)
5476 {
5477 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
5478
5479 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
5480 return slots_avail > nr_frags;
5481 }
5482
5483 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
5484 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
5485 {
5486 switch (tp->mac_version) {
5487 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5488 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
5489 return false;
5490 default:
5491 return true;
5492 }
5493 }
5494
5495 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5496 struct net_device *dev)
5497 {
5498 struct rtl8169_private *tp = netdev_priv(dev);
5499 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5500 struct TxDesc *txd = tp->TxDescArray + entry;
5501 struct device *d = tp_to_dev(tp);
5502 dma_addr_t mapping;
5503 u32 opts[2], len;
5504 bool stop_queue;
5505 bool door_bell;
5506 int frags;
5507
5508 if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
5509 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5510 goto err_stop_0;
5511 }
5512
5513 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5514 goto err_stop_0;
5515
5516 opts[1] = rtl8169_tx_vlan_tag(skb);
5517 opts[0] = DescOwn;
5518
5519 if (rtl_chip_supports_csum_v2(tp)) {
5520 if (!rtl8169_tso_csum_v2(tp, skb, opts))
5521 goto err_dma_0;
5522 } else {
5523 rtl8169_tso_csum_v1(skb, opts);
5524 }
5525
5526 len = skb_headlen(skb);
5527 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5528 if (unlikely(dma_mapping_error(d, mapping))) {
5529 if (net_ratelimit())
5530 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5531 goto err_dma_0;
5532 }
5533
5534 tp->tx_skb[entry].len = len;
5535 txd->addr = cpu_to_le64(mapping);
5536
5537 frags = rtl8169_xmit_frags(tp, skb, opts);
5538 if (frags < 0)
5539 goto err_dma_1;
5540 else if (frags)
5541 opts[0] |= FirstFrag;
5542 else {
5543 opts[0] |= FirstFrag | LastFrag;
5544 tp->tx_skb[entry].skb = skb;
5545 }
5546
5547 txd->opts2 = cpu_to_le32(opts[1]);
5548
5549 skb_tx_timestamp(skb);
5550
5551 /* Force memory writes to complete before releasing descriptor */
5552 dma_wmb();
5553
5554 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
5555
5556 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5557
5558 /* Force all memory writes to complete before notifying device */
5559 wmb();
5560
5561 tp->cur_tx += frags + 1;
5562
5563 stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS);
5564 if (unlikely(stop_queue)) {
5565 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5566 * not miss a ring update when it notices a stopped queue.
5567 */
5568 smp_wmb();
5569 netif_stop_queue(dev);
5570 door_bell = true;
5571 }
5572
5573 if (door_bell)
5574 RTL_W8(tp, TxPoll, NPQ);
5575
5576 if (unlikely(stop_queue)) {
5577 /* Sync with rtl_tx:
5578 * - publish queue status and cur_tx ring index (write barrier)
5579 * - refresh dirty_tx ring index (read barrier).
5580 * May the current thread have a pessimistic view of the ring
5581 * status and forget to wake up queue, a racing rtl_tx thread
5582 * can't.
5583 */
5584 smp_mb();
5585 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
5586 netif_start_queue(dev);
5587 }
5588
5589 return NETDEV_TX_OK;
5590
5591 err_dma_1:
5592 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5593 err_dma_0:
5594 dev_kfree_skb_any(skb);
5595 dev->stats.tx_dropped++;
5596 return NETDEV_TX_OK;
5597
5598 err_stop_0:
5599 netif_stop_queue(dev);
5600 dev->stats.tx_dropped++;
5601 return NETDEV_TX_BUSY;
5602 }
5603
5604 static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
5605 struct net_device *dev,
5606 netdev_features_t features)
5607 {
5608 int transport_offset = skb_transport_offset(skb);
5609 struct rtl8169_private *tp = netdev_priv(dev);
5610
5611 if (skb_is_gso(skb)) {
5612 if (transport_offset > GTTCPHO_MAX &&
5613 rtl_chip_supports_csum_v2(tp))
5614 features &= ~NETIF_F_ALL_TSO;
5615 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5616 if (skb->len < ETH_ZLEN) {
5617 switch (tp->mac_version) {
5618 case RTL_GIGA_MAC_VER_11:
5619 case RTL_GIGA_MAC_VER_12:
5620 case RTL_GIGA_MAC_VER_17:
5621 case RTL_GIGA_MAC_VER_34:
5622 features &= ~NETIF_F_CSUM_MASK;
5623 break;
5624 default:
5625 break;
5626 }
5627 }
5628
5629 if (transport_offset > TCPHO_MAX &&
5630 rtl_chip_supports_csum_v2(tp))
5631 features &= ~NETIF_F_CSUM_MASK;
5632 }
5633
5634 return vlan_features_check(skb, features);
5635 }
5636
5637 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5638 {
5639 struct rtl8169_private *tp = netdev_priv(dev);
5640 struct pci_dev *pdev = tp->pci_dev;
5641 u16 pci_status, pci_cmd;
5642
5643 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5644 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5645
5646 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5647 pci_cmd, pci_status);
5648
5649 /*
5650 * The recovery sequence below admits a very elaborated explanation:
5651 * - it seems to work;
5652 * - I did not see what else could be done;
5653 * - it makes iop3xx happy.
5654 *
5655 * Feel free to adjust to your needs.
5656 */
5657 if (pdev->broken_parity_status)
5658 pci_cmd &= ~PCI_COMMAND_PARITY;
5659 else
5660 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5661
5662 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5663
5664 pci_write_config_word(pdev, PCI_STATUS,
5665 pci_status & (PCI_STATUS_DETECTED_PARITY |
5666 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5667 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5668
5669 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5670 }
5671
5672 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
5673 int budget)
5674 {
5675 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
5676
5677 dirty_tx = tp->dirty_tx;
5678 smp_rmb();
5679 tx_left = tp->cur_tx - dirty_tx;
5680
5681 while (tx_left > 0) {
5682 unsigned int entry = dirty_tx % NUM_TX_DESC;
5683 struct ring_info *tx_skb = tp->tx_skb + entry;
5684 u32 status;
5685
5686 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5687 if (status & DescOwn)
5688 break;
5689
5690 /* This barrier is needed to keep us from reading
5691 * any other fields out of the Tx descriptor until
5692 * we know the status of DescOwn
5693 */
5694 dma_rmb();
5695
5696 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5697 tp->TxDescArray + entry);
5698 if (status & LastFrag) {
5699 pkts_compl++;
5700 bytes_compl += tx_skb->skb->len;
5701 napi_consume_skb(tx_skb->skb, budget);
5702 tx_skb->skb = NULL;
5703 }
5704 dirty_tx++;
5705 tx_left--;
5706 }
5707
5708 if (tp->dirty_tx != dirty_tx) {
5709 netdev_completed_queue(dev, pkts_compl, bytes_compl);
5710
5711 u64_stats_update_begin(&tp->tx_stats.syncp);
5712 tp->tx_stats.packets += pkts_compl;
5713 tp->tx_stats.bytes += bytes_compl;
5714 u64_stats_update_end(&tp->tx_stats.syncp);
5715
5716 tp->dirty_tx = dirty_tx;
5717 /* Sync with rtl8169_start_xmit:
5718 * - publish dirty_tx ring index (write barrier)
5719 * - refresh cur_tx ring index and queue status (read barrier)
5720 * May the current thread miss the stopped queue condition,
5721 * a racing xmit thread can only have a right view of the
5722 * ring status.
5723 */
5724 smp_mb();
5725 if (netif_queue_stopped(dev) &&
5726 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
5727 netif_wake_queue(dev);
5728 }
5729 /*
5730 * 8168 hack: TxPoll requests are lost when the Tx packets are
5731 * too close. Let's kick an extra TxPoll request when a burst
5732 * of start_xmit activity is detected (if it is not detected,
5733 * it is slow enough). -- FR
5734 */
5735 if (tp->cur_tx != dirty_tx)
5736 RTL_W8(tp, TxPoll, NPQ);
5737 }
5738 }
5739
5740 static inline int rtl8169_fragmented_frame(u32 status)
5741 {
5742 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5743 }
5744
5745 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5746 {
5747 u32 status = opts1 & RxProtoMask;
5748
5749 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5750 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5751 skb->ip_summed = CHECKSUM_UNNECESSARY;
5752 else
5753 skb_checksum_none_assert(skb);
5754 }
5755
5756 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5757 {
5758 unsigned int cur_rx, rx_left;
5759 unsigned int count;
5760
5761 cur_rx = tp->cur_rx;
5762
5763 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
5764 unsigned int entry = cur_rx % NUM_RX_DESC;
5765 const void *rx_buf = page_address(tp->Rx_databuff[entry]);
5766 struct RxDesc *desc = tp->RxDescArray + entry;
5767 u32 status;
5768
5769 status = le32_to_cpu(desc->opts1);
5770 if (status & DescOwn)
5771 break;
5772
5773 /* This barrier is needed to keep us from reading
5774 * any other fields out of the Rx descriptor until
5775 * we know the status of DescOwn
5776 */
5777 dma_rmb();
5778
5779 if (unlikely(status & RxRES)) {
5780 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5781 status);
5782 dev->stats.rx_errors++;
5783 if (status & (RxRWT | RxRUNT))
5784 dev->stats.rx_length_errors++;
5785 if (status & RxCRC)
5786 dev->stats.rx_crc_errors++;
5787 if (status & (RxRUNT | RxCRC) && !(status & RxRWT) &&
5788 dev->features & NETIF_F_RXALL) {
5789 goto process_pkt;
5790 }
5791 } else {
5792 unsigned int pkt_size;
5793 struct sk_buff *skb;
5794
5795 process_pkt:
5796 pkt_size = status & GENMASK(13, 0);
5797 if (likely(!(dev->features & NETIF_F_RXFCS)))
5798 pkt_size -= ETH_FCS_LEN;
5799 /*
5800 * The driver does not support incoming fragmented
5801 * frames. They are seen as a symptom of over-mtu
5802 * sized frames.
5803 */
5804 if (unlikely(rtl8169_fragmented_frame(status))) {
5805 dev->stats.rx_dropped++;
5806 dev->stats.rx_length_errors++;
5807 goto release_descriptor;
5808 }
5809
5810 skb = napi_alloc_skb(&tp->napi, pkt_size);
5811 if (unlikely(!skb)) {
5812 dev->stats.rx_dropped++;
5813 goto release_descriptor;
5814 }
5815
5816 dma_sync_single_for_cpu(tp_to_dev(tp),
5817 le64_to_cpu(desc->addr),
5818 pkt_size, DMA_FROM_DEVICE);
5819 prefetch(rx_buf);
5820 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
5821 skb->tail += pkt_size;
5822 skb->len = pkt_size;
5823
5824 dma_sync_single_for_device(tp_to_dev(tp),
5825 le64_to_cpu(desc->addr),
5826 pkt_size, DMA_FROM_DEVICE);
5827
5828 rtl8169_rx_csum(skb, status);
5829 skb->protocol = eth_type_trans(skb, dev);
5830
5831 rtl8169_rx_vlan_tag(desc, skb);
5832
5833 if (skb->pkt_type == PACKET_MULTICAST)
5834 dev->stats.multicast++;
5835
5836 napi_gro_receive(&tp->napi, skb);
5837
5838 u64_stats_update_begin(&tp->rx_stats.syncp);
5839 tp->rx_stats.packets++;
5840 tp->rx_stats.bytes += pkt_size;
5841 u64_stats_update_end(&tp->rx_stats.syncp);
5842 }
5843 release_descriptor:
5844 desc->opts2 = 0;
5845 rtl8169_mark_to_asic(desc);
5846 }
5847
5848 count = cur_rx - tp->cur_rx;
5849 tp->cur_rx = cur_rx;
5850
5851 return count;
5852 }
5853
5854 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5855 {
5856 struct rtl8169_private *tp = dev_instance;
5857 u16 status = RTL_R16(tp, IntrStatus);
5858
5859 if (!tp->irq_enabled || status == 0xffff || !(status & tp->irq_mask))
5860 return IRQ_NONE;
5861
5862 if (unlikely(status & SYSErr)) {
5863 rtl8169_pcierr_interrupt(tp->dev);
5864 goto out;
5865 }
5866
5867 if (status & LinkChg)
5868 phy_mac_interrupt(tp->phydev);
5869
5870 if (unlikely(status & RxFIFOOver &&
5871 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
5872 netif_stop_queue(tp->dev);
5873 /* XXX - Hack alert. See rtl_task(). */
5874 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
5875 }
5876
5877 rtl_irq_disable(tp);
5878 napi_schedule_irqoff(&tp->napi);
5879 out:
5880 rtl_ack_events(tp, status);
5881
5882 return IRQ_HANDLED;
5883 }
5884
5885 static void rtl_task(struct work_struct *work)
5886 {
5887 static const struct {
5888 int bitnr;
5889 void (*action)(struct rtl8169_private *);
5890 } rtl_work[] = {
5891 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
5892 };
5893 struct rtl8169_private *tp =
5894 container_of(work, struct rtl8169_private, wk.work);
5895 struct net_device *dev = tp->dev;
5896 int i;
5897
5898 rtl_lock_work(tp);
5899
5900 if (!netif_running(dev) ||
5901 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
5902 goto out_unlock;
5903
5904 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
5905 bool pending;
5906
5907 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
5908 if (pending)
5909 rtl_work[i].action(tp);
5910 }
5911
5912 out_unlock:
5913 rtl_unlock_work(tp);
5914 }
5915
5916 static int rtl8169_poll(struct napi_struct *napi, int budget)
5917 {
5918 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5919 struct net_device *dev = tp->dev;
5920 int work_done;
5921
5922 work_done = rtl_rx(dev, tp, (u32) budget);
5923
5924 rtl_tx(dev, tp, budget);
5925
5926 if (work_done < budget) {
5927 napi_complete_done(napi, work_done);
5928 rtl_irq_enable(tp);
5929 }
5930
5931 return work_done;
5932 }
5933
5934 static void rtl8169_rx_missed(struct net_device *dev)
5935 {
5936 struct rtl8169_private *tp = netdev_priv(dev);
5937
5938 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5939 return;
5940
5941 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
5942 RTL_W32(tp, RxMissed, 0);
5943 }
5944
5945 static void r8169_phylink_handler(struct net_device *ndev)
5946 {
5947 struct rtl8169_private *tp = netdev_priv(ndev);
5948
5949 if (netif_carrier_ok(ndev)) {
5950 rtl_link_chg_patch(tp);
5951 pm_request_resume(&tp->pci_dev->dev);
5952 } else {
5953 pm_runtime_idle(&tp->pci_dev->dev);
5954 }
5955
5956 if (net_ratelimit())
5957 phy_print_status(tp->phydev);
5958 }
5959
5960 static int r8169_phy_connect(struct rtl8169_private *tp)
5961 {
5962 struct phy_device *phydev = tp->phydev;
5963 phy_interface_t phy_mode;
5964 int ret;
5965
5966 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
5967 PHY_INTERFACE_MODE_MII;
5968
5969 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
5970 phy_mode);
5971 if (ret)
5972 return ret;
5973
5974 if (!tp->supports_gmii)
5975 phy_set_max_speed(phydev, SPEED_100);
5976
5977 phy_support_asym_pause(phydev);
5978
5979 phy_attached_info(phydev);
5980
5981 return 0;
5982 }
5983
5984 static void rtl8169_down(struct net_device *dev)
5985 {
5986 struct rtl8169_private *tp = netdev_priv(dev);
5987
5988 phy_stop(tp->phydev);
5989
5990 napi_disable(&tp->napi);
5991 netif_stop_queue(dev);
5992
5993 rtl8169_hw_reset(tp);
5994 /*
5995 * At this point device interrupts can not be enabled in any function,
5996 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
5997 * and napi is disabled (rtl8169_poll).
5998 */
5999 rtl8169_rx_missed(dev);
6000
6001 /* Give a racing hard_start_xmit a few cycles to complete. */
6002 synchronize_rcu();
6003
6004 rtl8169_tx_clear(tp);
6005
6006 rtl8169_rx_clear(tp);
6007
6008 rtl_pll_power_down(tp);
6009 }
6010
6011 static int rtl8169_close(struct net_device *dev)
6012 {
6013 struct rtl8169_private *tp = netdev_priv(dev);
6014 struct pci_dev *pdev = tp->pci_dev;
6015
6016 pm_runtime_get_sync(&pdev->dev);
6017
6018 /* Update counters before going down */
6019 rtl8169_update_counters(tp);
6020
6021 rtl_lock_work(tp);
6022 /* Clear all task flags */
6023 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6024
6025 rtl8169_down(dev);
6026 rtl_unlock_work(tp);
6027
6028 cancel_work_sync(&tp->wk.work);
6029
6030 phy_disconnect(tp->phydev);
6031
6032 pci_free_irq(pdev, 0, tp);
6033
6034 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6035 tp->RxPhyAddr);
6036 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6037 tp->TxPhyAddr);
6038 tp->TxDescArray = NULL;
6039 tp->RxDescArray = NULL;
6040
6041 pm_runtime_put_sync(&pdev->dev);
6042
6043 return 0;
6044 }
6045
6046 #ifdef CONFIG_NET_POLL_CONTROLLER
6047 static void rtl8169_netpoll(struct net_device *dev)
6048 {
6049 struct rtl8169_private *tp = netdev_priv(dev);
6050
6051 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6052 }
6053 #endif
6054
6055 static int rtl_open(struct net_device *dev)
6056 {
6057 struct rtl8169_private *tp = netdev_priv(dev);
6058 struct pci_dev *pdev = tp->pci_dev;
6059 int retval = -ENOMEM;
6060
6061 pm_runtime_get_sync(&pdev->dev);
6062
6063 /*
6064 * Rx and Tx descriptors needs 256 bytes alignment.
6065 * dma_alloc_coherent provides more.
6066 */
6067 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6068 &tp->TxPhyAddr, GFP_KERNEL);
6069 if (!tp->TxDescArray)
6070 goto err_pm_runtime_put;
6071
6072 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6073 &tp->RxPhyAddr, GFP_KERNEL);
6074 if (!tp->RxDescArray)
6075 goto err_free_tx_0;
6076
6077 retval = rtl8169_init_ring(tp);
6078 if (retval < 0)
6079 goto err_free_rx_1;
6080
6081 rtl_request_firmware(tp);
6082
6083 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6084 dev->name);
6085 if (retval < 0)
6086 goto err_release_fw_2;
6087
6088 retval = r8169_phy_connect(tp);
6089 if (retval)
6090 goto err_free_irq;
6091
6092 rtl_lock_work(tp);
6093
6094 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6095
6096 napi_enable(&tp->napi);
6097
6098 rtl8169_init_phy(dev, tp);
6099
6100 rtl_pll_power_up(tp);
6101
6102 rtl_hw_start(tp);
6103
6104 if (!rtl8169_init_counter_offsets(tp))
6105 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6106
6107 phy_start(tp->phydev);
6108 netif_start_queue(dev);
6109
6110 rtl_unlock_work(tp);
6111
6112 pm_runtime_put_sync(&pdev->dev);
6113 out:
6114 return retval;
6115
6116 err_free_irq:
6117 pci_free_irq(pdev, 0, tp);
6118 err_release_fw_2:
6119 rtl_release_firmware(tp);
6120 rtl8169_rx_clear(tp);
6121 err_free_rx_1:
6122 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6123 tp->RxPhyAddr);
6124 tp->RxDescArray = NULL;
6125 err_free_tx_0:
6126 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6127 tp->TxPhyAddr);
6128 tp->TxDescArray = NULL;
6129 err_pm_runtime_put:
6130 pm_runtime_put_noidle(&pdev->dev);
6131 goto out;
6132 }
6133
6134 static void
6135 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6136 {
6137 struct rtl8169_private *tp = netdev_priv(dev);
6138 struct pci_dev *pdev = tp->pci_dev;
6139 struct rtl8169_counters *counters = tp->counters;
6140 unsigned int start;
6141
6142 pm_runtime_get_noresume(&pdev->dev);
6143
6144 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6145 rtl8169_rx_missed(dev);
6146
6147 do {
6148 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6149 stats->rx_packets = tp->rx_stats.packets;
6150 stats->rx_bytes = tp->rx_stats.bytes;
6151 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6152
6153 do {
6154 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6155 stats->tx_packets = tp->tx_stats.packets;
6156 stats->tx_bytes = tp->tx_stats.bytes;
6157 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6158
6159 stats->rx_dropped = dev->stats.rx_dropped;
6160 stats->tx_dropped = dev->stats.tx_dropped;
6161 stats->rx_length_errors = dev->stats.rx_length_errors;
6162 stats->rx_errors = dev->stats.rx_errors;
6163 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6164 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6165 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6166 stats->multicast = dev->stats.multicast;
6167
6168 /*
6169 * Fetch additional counter values missing in stats collected by driver
6170 * from tally counters.
6171 */
6172 if (pm_runtime_active(&pdev->dev))
6173 rtl8169_update_counters(tp);
6174
6175 /*
6176 * Subtract values fetched during initalization.
6177 * See rtl8169_init_counter_offsets for a description why we do that.
6178 */
6179 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6180 le64_to_cpu(tp->tc_offset.tx_errors);
6181 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6182 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6183 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6184 le16_to_cpu(tp->tc_offset.tx_aborted);
6185
6186 pm_runtime_put_noidle(&pdev->dev);
6187 }
6188
6189 static void rtl8169_net_suspend(struct net_device *dev)
6190 {
6191 struct rtl8169_private *tp = netdev_priv(dev);
6192
6193 if (!netif_running(dev))
6194 return;
6195
6196 phy_stop(tp->phydev);
6197 netif_device_detach(dev);
6198
6199 rtl_lock_work(tp);
6200 napi_disable(&tp->napi);
6201 /* Clear all task flags */
6202 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6203
6204 rtl_unlock_work(tp);
6205
6206 rtl_pll_power_down(tp);
6207 }
6208
6209 #ifdef CONFIG_PM
6210
6211 static int rtl8169_suspend(struct device *device)
6212 {
6213 struct net_device *dev = dev_get_drvdata(device);
6214 struct rtl8169_private *tp = netdev_priv(dev);
6215
6216 rtl8169_net_suspend(dev);
6217 clk_disable_unprepare(tp->clk);
6218
6219 return 0;
6220 }
6221
6222 static void __rtl8169_resume(struct net_device *dev)
6223 {
6224 struct rtl8169_private *tp = netdev_priv(dev);
6225
6226 netif_device_attach(dev);
6227
6228 rtl_pll_power_up(tp);
6229 rtl8169_init_phy(dev, tp);
6230
6231 phy_start(tp->phydev);
6232
6233 rtl_lock_work(tp);
6234 napi_enable(&tp->napi);
6235 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6236 rtl_reset_work(tp);
6237 rtl_unlock_work(tp);
6238 }
6239
6240 static int rtl8169_resume(struct device *device)
6241 {
6242 struct net_device *dev = dev_get_drvdata(device);
6243 struct rtl8169_private *tp = netdev_priv(dev);
6244
6245 rtl_rar_set(tp, dev->dev_addr);
6246
6247 clk_prepare_enable(tp->clk);
6248
6249 if (netif_running(dev))
6250 __rtl8169_resume(dev);
6251
6252 return 0;
6253 }
6254
6255 static int rtl8169_runtime_suspend(struct device *device)
6256 {
6257 struct net_device *dev = dev_get_drvdata(device);
6258 struct rtl8169_private *tp = netdev_priv(dev);
6259
6260 if (!tp->TxDescArray)
6261 return 0;
6262
6263 rtl_lock_work(tp);
6264 __rtl8169_set_wol(tp, WAKE_ANY);
6265 rtl_unlock_work(tp);
6266
6267 rtl8169_net_suspend(dev);
6268
6269 /* Update counters before going runtime suspend */
6270 rtl8169_rx_missed(dev);
6271 rtl8169_update_counters(tp);
6272
6273 return 0;
6274 }
6275
6276 static int rtl8169_runtime_resume(struct device *device)
6277 {
6278 struct net_device *dev = dev_get_drvdata(device);
6279 struct rtl8169_private *tp = netdev_priv(dev);
6280
6281 rtl_rar_set(tp, dev->dev_addr);
6282
6283 if (!tp->TxDescArray)
6284 return 0;
6285
6286 rtl_lock_work(tp);
6287 __rtl8169_set_wol(tp, tp->saved_wolopts);
6288 rtl_unlock_work(tp);
6289
6290 __rtl8169_resume(dev);
6291
6292 return 0;
6293 }
6294
6295 static int rtl8169_runtime_idle(struct device *device)
6296 {
6297 struct net_device *dev = dev_get_drvdata(device);
6298
6299 if (!netif_running(dev) || !netif_carrier_ok(dev))
6300 pm_schedule_suspend(device, 10000);
6301
6302 return -EBUSY;
6303 }
6304
6305 static const struct dev_pm_ops rtl8169_pm_ops = {
6306 .suspend = rtl8169_suspend,
6307 .resume = rtl8169_resume,
6308 .freeze = rtl8169_suspend,
6309 .thaw = rtl8169_resume,
6310 .poweroff = rtl8169_suspend,
6311 .restore = rtl8169_resume,
6312 .runtime_suspend = rtl8169_runtime_suspend,
6313 .runtime_resume = rtl8169_runtime_resume,
6314 .runtime_idle = rtl8169_runtime_idle,
6315 };
6316
6317 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
6318
6319 #else /* !CONFIG_PM */
6320
6321 #define RTL8169_PM_OPS NULL
6322
6323 #endif /* !CONFIG_PM */
6324
6325 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6326 {
6327 /* WoL fails with 8168b when the receiver is disabled. */
6328 switch (tp->mac_version) {
6329 case RTL_GIGA_MAC_VER_11:
6330 case RTL_GIGA_MAC_VER_12:
6331 case RTL_GIGA_MAC_VER_17:
6332 pci_clear_master(tp->pci_dev);
6333
6334 RTL_W8(tp, ChipCmd, CmdRxEnb);
6335 /* PCI commit */
6336 RTL_R8(tp, ChipCmd);
6337 break;
6338 default:
6339 break;
6340 }
6341 }
6342
6343 static void rtl_shutdown(struct pci_dev *pdev)
6344 {
6345 struct net_device *dev = pci_get_drvdata(pdev);
6346 struct rtl8169_private *tp = netdev_priv(dev);
6347
6348 rtl8169_net_suspend(dev);
6349
6350 /* Restore original MAC address */
6351 rtl_rar_set(tp, dev->perm_addr);
6352
6353 rtl8169_hw_reset(tp);
6354
6355 if (system_state == SYSTEM_POWER_OFF) {
6356 if (tp->saved_wolopts) {
6357 rtl_wol_suspend_quirk(tp);
6358 rtl_wol_shutdown_quirk(tp);
6359 }
6360
6361 pci_wake_from_d3(pdev, true);
6362 pci_set_power_state(pdev, PCI_D3hot);
6363 }
6364 }
6365
6366 static void rtl_remove_one(struct pci_dev *pdev)
6367 {
6368 struct net_device *dev = pci_get_drvdata(pdev);
6369 struct rtl8169_private *tp = netdev_priv(dev);
6370
6371 if (r8168_check_dash(tp))
6372 rtl8168_driver_stop(tp);
6373
6374 netif_napi_del(&tp->napi);
6375
6376 unregister_netdev(dev);
6377 mdiobus_unregister(tp->phydev->mdio.bus);
6378
6379 rtl_release_firmware(tp);
6380
6381 if (pci_dev_run_wake(pdev))
6382 pm_runtime_get_noresume(&pdev->dev);
6383
6384 /* restore original MAC address */
6385 rtl_rar_set(tp, dev->perm_addr);
6386 }
6387
6388 static const struct net_device_ops rtl_netdev_ops = {
6389 .ndo_open = rtl_open,
6390 .ndo_stop = rtl8169_close,
6391 .ndo_get_stats64 = rtl8169_get_stats64,
6392 .ndo_start_xmit = rtl8169_start_xmit,
6393 .ndo_features_check = rtl8169_features_check,
6394 .ndo_tx_timeout = rtl8169_tx_timeout,
6395 .ndo_validate_addr = eth_validate_addr,
6396 .ndo_change_mtu = rtl8169_change_mtu,
6397 .ndo_fix_features = rtl8169_fix_features,
6398 .ndo_set_features = rtl8169_set_features,
6399 .ndo_set_mac_address = rtl_set_mac_address,
6400 .ndo_do_ioctl = rtl8169_ioctl,
6401 .ndo_set_rx_mode = rtl_set_rx_mode,
6402 #ifdef CONFIG_NET_POLL_CONTROLLER
6403 .ndo_poll_controller = rtl8169_netpoll,
6404 #endif
6405
6406 };
6407
6408 static void rtl_set_irq_mask(struct rtl8169_private *tp)
6409 {
6410 tp->irq_mask = RTL_EVENT_NAPI | LinkChg;
6411
6412 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6413 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
6414 else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
6415 /* special workaround needed */
6416 tp->irq_mask |= RxFIFOOver;
6417 else
6418 tp->irq_mask |= RxOverflow;
6419 }
6420
6421 static int rtl_alloc_irq(struct rtl8169_private *tp)
6422 {
6423 unsigned int flags;
6424
6425 switch (tp->mac_version) {
6426 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
6427 rtl_unlock_config_regs(tp);
6428 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
6429 rtl_lock_config_regs(tp);
6430 /* fall through */
6431 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_24:
6432 flags = PCI_IRQ_LEGACY;
6433 break;
6434 default:
6435 flags = PCI_IRQ_ALL_TYPES;
6436 break;
6437 }
6438
6439 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
6440 }
6441
6442 static void rtl_read_mac_address(struct rtl8169_private *tp,
6443 u8 mac_addr[ETH_ALEN])
6444 {
6445 /* Get MAC address */
6446 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
6447 u32 value = rtl_eri_read(tp, 0xe0);
6448
6449 mac_addr[0] = (value >> 0) & 0xff;
6450 mac_addr[1] = (value >> 8) & 0xff;
6451 mac_addr[2] = (value >> 16) & 0xff;
6452 mac_addr[3] = (value >> 24) & 0xff;
6453
6454 value = rtl_eri_read(tp, 0xe4);
6455 mac_addr[4] = (value >> 0) & 0xff;
6456 mac_addr[5] = (value >> 8) & 0xff;
6457 }
6458 }
6459
6460 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6461 {
6462 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
6463 }
6464
6465 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6466 {
6467 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6468 }
6469
6470 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
6471 {
6472 struct rtl8169_private *tp = mii_bus->priv;
6473
6474 if (phyaddr > 0)
6475 return -ENODEV;
6476
6477 return rtl_readphy(tp, phyreg);
6478 }
6479
6480 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
6481 int phyreg, u16 val)
6482 {
6483 struct rtl8169_private *tp = mii_bus->priv;
6484
6485 if (phyaddr > 0)
6486 return -ENODEV;
6487
6488 rtl_writephy(tp, phyreg, val);
6489
6490 return 0;
6491 }
6492
6493 static int r8169_mdio_register(struct rtl8169_private *tp)
6494 {
6495 struct pci_dev *pdev = tp->pci_dev;
6496 struct mii_bus *new_bus;
6497 int ret;
6498
6499 new_bus = devm_mdiobus_alloc(&pdev->dev);
6500 if (!new_bus)
6501 return -ENOMEM;
6502
6503 new_bus->name = "r8169";
6504 new_bus->priv = tp;
6505 new_bus->parent = &pdev->dev;
6506 new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
6507 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
6508
6509 new_bus->read = r8169_mdio_read_reg;
6510 new_bus->write = r8169_mdio_write_reg;
6511
6512 ret = mdiobus_register(new_bus);
6513 if (ret)
6514 return ret;
6515
6516 tp->phydev = mdiobus_get_phy(new_bus, 0);
6517 if (!tp->phydev) {
6518 mdiobus_unregister(new_bus);
6519 return -ENODEV;
6520 }
6521
6522 /* PHY will be woken up in rtl_open() */
6523 phy_suspend(tp->phydev);
6524
6525 return 0;
6526 }
6527
6528 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6529 {
6530 tp->ocp_base = OCP_STD_PHY_BASE;
6531
6532 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
6533
6534 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6535 return;
6536
6537 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6538 return;
6539
6540 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6541 msleep(1);
6542 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6543
6544 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
6545
6546 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6547 return;
6548
6549 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
6550
6551 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
6552 }
6553
6554 static void rtl_hw_initialize(struct rtl8169_private *tp)
6555 {
6556 switch (tp->mac_version) {
6557 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
6558 rtl8168ep_stop_cmac(tp);
6559 /* fall through */
6560 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
6561 rtl_hw_init_8168g(tp);
6562 break;
6563 default:
6564 break;
6565 }
6566 }
6567
6568 static int rtl_jumbo_max(struct rtl8169_private *tp)
6569 {
6570 /* Non-GBit versions don't support jumbo frames */
6571 if (!tp->supports_gmii)
6572 return JUMBO_1K;
6573
6574 switch (tp->mac_version) {
6575 /* RTL8169 */
6576 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
6577 return JUMBO_7K;
6578 /* RTL8168b */
6579 case RTL_GIGA_MAC_VER_11:
6580 case RTL_GIGA_MAC_VER_12:
6581 case RTL_GIGA_MAC_VER_17:
6582 return JUMBO_4K;
6583 /* RTL8168c */
6584 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
6585 return JUMBO_6K;
6586 default:
6587 return JUMBO_9K;
6588 }
6589 }
6590
6591 static void rtl_disable_clk(void *data)
6592 {
6593 clk_disable_unprepare(data);
6594 }
6595
6596 static int rtl_get_ether_clk(struct rtl8169_private *tp)
6597 {
6598 struct device *d = tp_to_dev(tp);
6599 struct clk *clk;
6600 int rc;
6601
6602 clk = devm_clk_get(d, "ether_clk");
6603 if (IS_ERR(clk)) {
6604 rc = PTR_ERR(clk);
6605 if (rc == -ENOENT)
6606 /* clk-core allows NULL (for suspend / resume) */
6607 rc = 0;
6608 else if (rc != -EPROBE_DEFER)
6609 dev_err(d, "failed to get clk: %d\n", rc);
6610 } else {
6611 tp->clk = clk;
6612 rc = clk_prepare_enable(clk);
6613 if (rc)
6614 dev_err(d, "failed to enable clk: %d\n", rc);
6615 else
6616 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
6617 }
6618
6619 return rc;
6620 }
6621
6622 static void rtl_init_mac_address(struct rtl8169_private *tp)
6623 {
6624 struct net_device *dev = tp->dev;
6625 u8 *mac_addr = dev->dev_addr;
6626 int rc, i;
6627
6628 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
6629 if (!rc)
6630 goto done;
6631
6632 rtl_read_mac_address(tp, mac_addr);
6633 if (is_valid_ether_addr(mac_addr))
6634 goto done;
6635
6636 for (i = 0; i < ETH_ALEN; i++)
6637 mac_addr[i] = RTL_R8(tp, MAC0 + i);
6638 if (is_valid_ether_addr(mac_addr))
6639 goto done;
6640
6641 eth_hw_addr_random(dev);
6642 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
6643 done:
6644 rtl_rar_set(tp, mac_addr);
6645 }
6646
6647 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6648 {
6649 struct rtl8169_private *tp;
6650 struct net_device *dev;
6651 int chipset, region;
6652 int jumbo_max, rc;
6653
6654 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
6655 if (!dev)
6656 return -ENOMEM;
6657
6658 SET_NETDEV_DEV(dev, &pdev->dev);
6659 dev->netdev_ops = &rtl_netdev_ops;
6660 tp = netdev_priv(dev);
6661 tp->dev = dev;
6662 tp->pci_dev = pdev;
6663 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6664 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
6665
6666 /* Get the *optional* external "ether_clk" used on some boards */
6667 rc = rtl_get_ether_clk(tp);
6668 if (rc)
6669 return rc;
6670
6671 /* Disable ASPM completely as that cause random device stop working
6672 * problems as well as full system hangs for some PCIe devices users.
6673 */
6674 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
6675 PCIE_LINK_STATE_L1);
6676 tp->aspm_manageable = !rc;
6677
6678 /* enable device (incl. PCI PM wakeup and hotplug setup) */
6679 rc = pcim_enable_device(pdev);
6680 if (rc < 0) {
6681 dev_err(&pdev->dev, "enable failure\n");
6682 return rc;
6683 }
6684
6685 if (pcim_set_mwi(pdev) < 0)
6686 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
6687
6688 /* use first MMIO region */
6689 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
6690 if (region < 0) {
6691 dev_err(&pdev->dev, "no MMIO resource found\n");
6692 return -ENODEV;
6693 }
6694
6695 /* check for weird/broken PCI region reporting */
6696 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6697 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
6698 return -ENODEV;
6699 }
6700
6701 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
6702 if (rc < 0) {
6703 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
6704 return rc;
6705 }
6706
6707 tp->mmio_addr = pcim_iomap_table(pdev)[region];
6708
6709 /* Identify chip attached to board */
6710 rtl8169_get_mac_version(tp);
6711 if (tp->mac_version == RTL_GIGA_MAC_NONE)
6712 return -ENODEV;
6713
6714 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
6715
6716 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
6717 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
6718 dev->features |= NETIF_F_HIGHDMA;
6719
6720 rtl_init_rxcfg(tp);
6721
6722 rtl8169_irq_mask_and_ack(tp);
6723
6724 rtl_hw_initialize(tp);
6725
6726 rtl_hw_reset(tp);
6727
6728 pci_set_master(pdev);
6729
6730 chipset = tp->mac_version;
6731
6732 rc = rtl_alloc_irq(tp);
6733 if (rc < 0) {
6734 dev_err(&pdev->dev, "Can't allocate interrupt\n");
6735 return rc;
6736 }
6737
6738 mutex_init(&tp->wk.mutex);
6739 INIT_WORK(&tp->wk.work, rtl_task);
6740 u64_stats_init(&tp->rx_stats.syncp);
6741 u64_stats_init(&tp->tx_stats.syncp);
6742
6743 rtl_init_mac_address(tp);
6744
6745 dev->ethtool_ops = &rtl8169_ethtool_ops;
6746
6747 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
6748
6749 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6750 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
6751 NETIF_F_HW_VLAN_CTAG_RX;
6752 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6753 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
6754 NETIF_F_HW_VLAN_CTAG_RX;
6755 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6756 NETIF_F_HIGHDMA;
6757 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
6758
6759 tp->cp_cmd |= RxChkSum | RxVlan;
6760
6761 /*
6762 * Pretend we are using VLANs; This bypasses a nasty bug where
6763 * Interrupts stop flowing on high load on 8110SCd controllers.
6764 */
6765 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6766 /* Disallow toggling */
6767 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
6768
6769 if (rtl_chip_supports_csum_v2(tp)) {
6770 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
6771 dev->features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
6772 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2;
6773 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2;
6774 } else {
6775 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1;
6776 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1;
6777 }
6778
6779 /* RTL8168e-vl has a HW issue with TSO */
6780 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
6781 dev->vlan_features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG);
6782 dev->hw_features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG);
6783 dev->features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG);
6784 }
6785
6786 dev->hw_features |= NETIF_F_RXALL;
6787 dev->hw_features |= NETIF_F_RXFCS;
6788
6789 /* MTU range: 60 - hw-specific max */
6790 dev->min_mtu = ETH_ZLEN;
6791 jumbo_max = rtl_jumbo_max(tp);
6792 dev->max_mtu = jumbo_max;
6793
6794 rtl_set_irq_mask(tp);
6795
6796 tp->fw_name = rtl_chip_infos[chipset].fw_name;
6797
6798 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
6799 &tp->counters_phys_addr,
6800 GFP_KERNEL);
6801 if (!tp->counters)
6802 return -ENOMEM;
6803
6804 pci_set_drvdata(pdev, dev);
6805
6806 rc = r8169_mdio_register(tp);
6807 if (rc)
6808 return rc;
6809
6810 /* chip gets powered up in rtl_open() */
6811 rtl_pll_power_down(tp);
6812
6813 rc = register_netdev(dev);
6814 if (rc)
6815 goto err_mdio_unregister;
6816
6817 netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
6818 rtl_chip_infos[chipset].name, dev->dev_addr,
6819 (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
6820 pci_irq_vector(pdev, 0));
6821
6822 if (jumbo_max > JUMBO_1K)
6823 netif_info(tp, probe, dev,
6824 "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
6825 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
6826 "ok" : "ko");
6827
6828 if (r8168_check_dash(tp))
6829 rtl8168_driver_start(tp);
6830
6831 if (pci_dev_run_wake(pdev))
6832 pm_runtime_put_sync(&pdev->dev);
6833
6834 return 0;
6835
6836 err_mdio_unregister:
6837 mdiobus_unregister(tp->phydev->mdio.bus);
6838 return rc;
6839 }
6840
6841 static struct pci_driver rtl8169_pci_driver = {
6842 .name = MODULENAME,
6843 .id_table = rtl8169_pci_tbl,
6844 .probe = rtl_init_one,
6845 .remove = rtl_remove_one,
6846 .shutdown = rtl_shutdown,
6847 .driver.pm = RTL8169_PM_OPS,
6848 };
6849
6850 module_pci_driver(rtl8169_pci_driver);
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