1 // SPDX-License-Identifier: GPL-2.0-only
3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
7 * Copyright (c) a lot of people too. Please respect their work.
9 * See MAINTAINERS file for support contact information.
12 #include <linux/module.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/ethtool.h>
19 #include <linux/phy.h>
20 #include <linux/if_vlan.h>
24 #include <linux/tcp.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/bitfield.h>
29 #include <linux/prefetch.h>
30 #include <linux/ipv6.h>
31 #include <asm/unaligned.h>
32 #include <net/ip6_checksum.h>
35 #include "r8169_firmware.h"
37 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
38 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
39 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
40 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
41 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
42 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
43 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
44 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
45 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
46 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
47 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
48 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
49 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
50 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
51 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
52 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
53 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
54 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw"
55 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
56 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
57 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw"
58 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw"
60 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
61 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
62 #define MC_FILTER_LIMIT 32
64 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
65 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
67 #define R8169_REGS_SIZE 256
68 #define R8169_RX_BUF_SIZE (SZ_16K - 1)
69 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */
70 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
71 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
72 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
74 #define OCP_STD_PHY_BASE 0xa400
76 #define RTL_CFG_NO_GBIT 1
78 /* write/read MMIO register */
79 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
80 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
81 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
82 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
83 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
84 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
86 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
87 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
88 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
89 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
94 } rtl_chip_infos
[] = {
96 [RTL_GIGA_MAC_VER_02
] = {"RTL8169s" },
97 [RTL_GIGA_MAC_VER_03
] = {"RTL8110s" },
98 [RTL_GIGA_MAC_VER_04
] = {"RTL8169sb/8110sb" },
99 [RTL_GIGA_MAC_VER_05
] = {"RTL8169sc/8110sc" },
100 [RTL_GIGA_MAC_VER_06
] = {"RTL8169sc/8110sc" },
102 [RTL_GIGA_MAC_VER_07
] = {"RTL8102e" },
103 [RTL_GIGA_MAC_VER_08
] = {"RTL8102e" },
104 [RTL_GIGA_MAC_VER_09
] = {"RTL8102e/RTL8103e" },
105 [RTL_GIGA_MAC_VER_10
] = {"RTL8101e" },
106 [RTL_GIGA_MAC_VER_11
] = {"RTL8168b/8111b" },
107 [RTL_GIGA_MAC_VER_12
] = {"RTL8168b/8111b" },
108 [RTL_GIGA_MAC_VER_13
] = {"RTL8101e/RTL8100e" },
109 [RTL_GIGA_MAC_VER_14
] = {"RTL8401" },
110 [RTL_GIGA_MAC_VER_16
] = {"RTL8101e" },
111 [RTL_GIGA_MAC_VER_17
] = {"RTL8168b/8111b" },
112 [RTL_GIGA_MAC_VER_18
] = {"RTL8168cp/8111cp" },
113 [RTL_GIGA_MAC_VER_19
] = {"RTL8168c/8111c" },
114 [RTL_GIGA_MAC_VER_20
] = {"RTL8168c/8111c" },
115 [RTL_GIGA_MAC_VER_21
] = {"RTL8168c/8111c" },
116 [RTL_GIGA_MAC_VER_22
] = {"RTL8168c/8111c" },
117 [RTL_GIGA_MAC_VER_23
] = {"RTL8168cp/8111cp" },
118 [RTL_GIGA_MAC_VER_24
] = {"RTL8168cp/8111cp" },
119 [RTL_GIGA_MAC_VER_25
] = {"RTL8168d/8111d", FIRMWARE_8168D_1
},
120 [RTL_GIGA_MAC_VER_26
] = {"RTL8168d/8111d", FIRMWARE_8168D_2
},
121 [RTL_GIGA_MAC_VER_27
] = {"RTL8168dp/8111dp" },
122 [RTL_GIGA_MAC_VER_28
] = {"RTL8168dp/8111dp" },
123 [RTL_GIGA_MAC_VER_29
] = {"RTL8105e", FIRMWARE_8105E_1
},
124 [RTL_GIGA_MAC_VER_30
] = {"RTL8105e", FIRMWARE_8105E_1
},
125 [RTL_GIGA_MAC_VER_31
] = {"RTL8168dp/8111dp" },
126 [RTL_GIGA_MAC_VER_32
] = {"RTL8168e/8111e", FIRMWARE_8168E_1
},
127 [RTL_GIGA_MAC_VER_33
] = {"RTL8168e/8111e", FIRMWARE_8168E_2
},
128 [RTL_GIGA_MAC_VER_34
] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3
},
129 [RTL_GIGA_MAC_VER_35
] = {"RTL8168f/8111f", FIRMWARE_8168F_1
},
130 [RTL_GIGA_MAC_VER_36
] = {"RTL8168f/8111f", FIRMWARE_8168F_2
},
131 [RTL_GIGA_MAC_VER_37
] = {"RTL8402", FIRMWARE_8402_1
},
132 [RTL_GIGA_MAC_VER_38
] = {"RTL8411", FIRMWARE_8411_1
},
133 [RTL_GIGA_MAC_VER_39
] = {"RTL8106e", FIRMWARE_8106E_1
},
134 [RTL_GIGA_MAC_VER_40
] = {"RTL8168g/8111g", FIRMWARE_8168G_2
},
135 [RTL_GIGA_MAC_VER_41
] = {"RTL8168g/8111g" },
136 [RTL_GIGA_MAC_VER_42
] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3
},
137 [RTL_GIGA_MAC_VER_43
] = {"RTL8106eus", FIRMWARE_8106E_2
},
138 [RTL_GIGA_MAC_VER_44
] = {"RTL8411b", FIRMWARE_8411_2
},
139 [RTL_GIGA_MAC_VER_45
] = {"RTL8168h/8111h", FIRMWARE_8168H_1
},
140 [RTL_GIGA_MAC_VER_46
] = {"RTL8168h/8111h", FIRMWARE_8168H_2
},
141 [RTL_GIGA_MAC_VER_47
] = {"RTL8107e", FIRMWARE_8107E_1
},
142 [RTL_GIGA_MAC_VER_48
] = {"RTL8107e", FIRMWARE_8107E_2
},
143 [RTL_GIGA_MAC_VER_49
] = {"RTL8168ep/8111ep" },
144 [RTL_GIGA_MAC_VER_50
] = {"RTL8168ep/8111ep" },
145 [RTL_GIGA_MAC_VER_51
] = {"RTL8168ep/8111ep" },
146 [RTL_GIGA_MAC_VER_52
] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3
},
147 [RTL_GIGA_MAC_VER_53
] = {"RTL8168fp/RTL8117", },
148 [RTL_GIGA_MAC_VER_60
] = {"RTL8125A" },
149 [RTL_GIGA_MAC_VER_61
] = {"RTL8125A", FIRMWARE_8125A_3
},
150 /* reserve 62 for CFG_METHOD_4 in the vendor driver */
151 [RTL_GIGA_MAC_VER_63
] = {"RTL8125B", FIRMWARE_8125B_2
},
154 static const struct pci_device_id rtl8169_pci_tbl
[] = {
155 { PCI_VDEVICE(REALTEK
, 0x2502) },
156 { PCI_VDEVICE(REALTEK
, 0x2600) },
157 { PCI_VDEVICE(REALTEK
, 0x8129) },
158 { PCI_VDEVICE(REALTEK
, 0x8136), RTL_CFG_NO_GBIT
},
159 { PCI_VDEVICE(REALTEK
, 0x8161) },
160 { PCI_VDEVICE(REALTEK
, 0x8167) },
161 { PCI_VDEVICE(REALTEK
, 0x8168) },
162 { PCI_VDEVICE(NCUBE
, 0x8168) },
163 { PCI_VDEVICE(REALTEK
, 0x8169) },
164 { PCI_VENDOR_ID_DLINK
, 0x4300,
165 PCI_VENDOR_ID_DLINK
, 0x4b10, 0, 0 },
166 { PCI_VDEVICE(DLINK
, 0x4300) },
167 { PCI_VDEVICE(DLINK
, 0x4302) },
168 { PCI_VDEVICE(AT
, 0xc107) },
169 { PCI_VDEVICE(USR
, 0x0116) },
170 { PCI_VENDOR_ID_LINKSYS
, 0x1032, PCI_ANY_ID
, 0x0024 },
171 { 0x0001, 0x8168, PCI_ANY_ID
, 0x2410 },
172 { PCI_VDEVICE(REALTEK
, 0x8125) },
173 { PCI_VDEVICE(REALTEK
, 0x3000) },
177 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
180 MAC0
= 0, /* Ethernet hardware address. */
182 MAR0
= 8, /* Multicast filter. */
183 CounterAddrLow
= 0x10,
184 CounterAddrHigh
= 0x14,
185 TxDescStartAddrLow
= 0x20,
186 TxDescStartAddrHigh
= 0x24,
187 TxHDescStartAddrLow
= 0x28,
188 TxHDescStartAddrHigh
= 0x2c,
197 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
198 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
201 #define RX128_INT_EN (1 << 15) /* 8111c and later */
202 #define RX_MULTI_EN (1 << 14) /* 8111c only */
203 #define RXCFG_FIFO_SHIFT 13
204 /* No threshold before first PCI xfer */
205 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
206 #define RX_EARLY_OFF (1 << 11)
207 #define RXCFG_DMA_SHIFT 8
208 /* Unlimited maximum PCI burst. */
209 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
215 #define PME_SIGNAL (1 << 5) /* 8168c and later */
226 #define RTL_COALESCE_TX_USECS GENMASK(15, 12)
227 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8)
228 #define RTL_COALESCE_RX_USECS GENMASK(7, 4)
229 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0)
231 #define RTL_COALESCE_T_MAX 0x0fU
232 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4)
234 RxDescAddrLow
= 0xe4,
235 RxDescAddrHigh
= 0xe8,
236 EarlyTxThres
= 0xec, /* 8169. Unit of 32 bytes. */
238 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
240 MaxTxPacketSize
= 0xec, /* 8101/8168. Unit of 128 bytes. */
242 #define TxPacketMax (8064 >> 7)
243 #define EarlySize 0x27
246 FuncEventMask
= 0xf4,
247 FuncPresetState
= 0xf8,
252 FuncForceEvent
= 0xfc,
255 enum rtl8168_8101_registers
{
258 #define CSIAR_FLAG 0x80000000
259 #define CSIAR_WRITE_CMD 0x80000000
260 #define CSIAR_BYTE_ENABLE 0x0000f000
261 #define CSIAR_ADDR_MASK 0x00000fff
263 #define D3COLD_NO_PLL_DOWN BIT(7)
264 #define D3HOT_NO_PLL_DOWN BIT(6)
265 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6))
267 #define EPHYAR_FLAG 0x80000000
268 #define EPHYAR_WRITE_CMD 0x80000000
269 #define EPHYAR_REG_MASK 0x1f
270 #define EPHYAR_REG_SHIFT 16
271 #define EPHYAR_DATA_MASK 0xffff
273 #define PFM_EN (1 << 6)
274 #define TX_10M_PS_EN (1 << 7)
276 #define FIX_NAK_1 (1 << 4)
277 #define FIX_NAK_2 (1 << 3)
280 #define NOW_IS_OOB (1 << 7)
281 #define TX_EMPTY (1 << 5)
282 #define RX_EMPTY (1 << 4)
283 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
284 #define EN_NDP (1 << 3)
285 #define EN_OOB_RESET (1 << 2)
286 #define LINK_LIST_RDY (1 << 1)
288 #define EFUSEAR_FLAG 0x80000000
289 #define EFUSEAR_WRITE_CMD 0x80000000
290 #define EFUSEAR_READ_CMD 0x00000000
291 #define EFUSEAR_REG_MASK 0x03ff
292 #define EFUSEAR_REG_SHIFT 8
293 #define EFUSEAR_DATA_MASK 0xff
295 #define PFM_D3COLD_EN (1 << 6)
298 enum rtl8168_registers
{
303 #define ERIAR_FLAG 0x80000000
304 #define ERIAR_WRITE_CMD 0x80000000
305 #define ERIAR_READ_CMD 0x00000000
306 #define ERIAR_ADDR_BYTE_ALIGN 4
307 #define ERIAR_TYPE_SHIFT 16
308 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
309 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
310 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
311 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
312 #define ERIAR_MASK_SHIFT 12
313 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
314 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
315 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
316 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
317 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
318 EPHY_RXER_NUM
= 0x7c,
319 OCPDR
= 0xb0, /* OCP GPHY access */
320 #define OCPDR_WRITE_CMD 0x80000000
321 #define OCPDR_READ_CMD 0x00000000
322 #define OCPDR_REG_MASK 0x7f
323 #define OCPDR_GPHY_REG_SHIFT 16
324 #define OCPDR_DATA_MASK 0xffff
326 #define OCPAR_FLAG 0x80000000
327 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
328 #define OCPAR_GPHY_READ_CMD 0x0000f060
330 RDSAR1
= 0xd0, /* 8168c only. Undocumented on 8168dp */
331 MISC
= 0xf0, /* 8168e only. */
332 #define TXPLA_RST (1 << 29)
333 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
334 #define PWM_EN (1 << 22)
335 #define RXDV_GATED_EN (1 << 19)
336 #define EARLY_TALLY_EN (1 << 16)
339 enum rtl8125_registers
{
340 IntrMask_8125
= 0x38,
341 IntrStatus_8125
= 0x3c,
344 EEE_TXIDLE_TIMER_8125
= 0x6048,
347 #define RX_VLAN_INNER_8125 BIT(22)
348 #define RX_VLAN_OUTER_8125 BIT(23)
349 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
351 #define RX_FETCH_DFLT_8125 (8 << 27)
353 enum rtl_register_content
{
354 /* InterruptStatusBits */
358 TxDescUnavail
= 0x0080,
380 /* TXPoll register p.5 */
381 HPQ
= 0x80, /* Poll cmd on the high prio queue */
382 NPQ
= 0x40, /* Poll cmd on the low prio queue */
383 FSWInt
= 0x01, /* Forced software interrupt */
387 Cfg9346_Unlock
= 0xc0,
392 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30
393 AcceptBroadcast
= 0x08,
394 AcceptMulticast
= 0x04,
396 AcceptAllPhys
= 0x01,
397 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f
398 #define RX_CONFIG_ACCEPT_MASK 0x3f
401 TxInterFrameGapShift
= 24,
402 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
404 /* Config1 register p.24 */
407 Speed_down
= (1 << 4),
411 PMEnable
= (1 << 0), /* Power Management Enable */
413 /* Config2 register p. 25 */
414 ClkReqEn
= (1 << 7), /* Clock Request Enable */
415 MSIEnable
= (1 << 5), /* 8169 only. Reserved in the 8168. */
416 PCI_Clock_66MHz
= 0x01,
417 PCI_Clock_33MHz
= 0x00,
419 /* Config3 register p.25 */
420 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
421 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
422 Jumbo_En0
= (1 << 2), /* 8168 only. Reserved in the 8168b */
423 Rdy_to_L23
= (1 << 1), /* L23 Enable */
424 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
426 /* Config4 register */
427 Jumbo_En1
= (1 << 1), /* 8168 only. Reserved in the 8168b */
429 /* Config5 register p.27 */
430 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
431 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
432 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
434 LanWake
= (1 << 1), /* LanWake enable/disable */
435 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
436 ASPM_en
= (1 << 0), /* ASPM enable */
439 EnableBist
= (1 << 15), // 8168 8101
440 Mac_dbgo_oe
= (1 << 14), // 8168 8101
441 EnAnaPLL
= (1 << 14), // 8169
442 Normal_mode
= (1 << 13), // unused
443 Force_half_dup
= (1 << 12), // 8168 8101
444 Force_rxflow_en
= (1 << 11), // 8168 8101
445 Force_txflow_en
= (1 << 10), // 8168 8101
446 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
447 ASF
= (1 << 8), // 8168 8101
448 PktCntrDisable
= (1 << 7), // 8168 8101
449 Mac_dbgo_sel
= 0x001c, // 8168
454 #define INTT_MASK GENMASK(1, 0)
455 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
457 /* rtl8169_PHYstatus */
467 /* ResetCounterCommand */
470 /* DumpCounterCommand */
473 /* magic enable v2 */
474 MagicPacket_v2
= (1 << 16), /* Wake up when receives a Magic Packet */
478 /* First doubleword. */
479 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
480 RingEnd
= (1 << 30), /* End of descriptor ring */
481 FirstFrag
= (1 << 29), /* First segment of a packet */
482 LastFrag
= (1 << 28), /* Final segment of a packet */
486 enum rtl_tx_desc_bit
{
487 /* First doubleword. */
488 TD_LSO
= (1 << 27), /* Large Send Offload */
489 #define TD_MSS_MAX 0x07ffu /* MSS value */
491 /* Second doubleword. */
492 TxVlanTag
= (1 << 17), /* Add VLAN tag */
495 /* 8169, 8168b and 810x except 8102e. */
496 enum rtl_tx_desc_bit_0
{
497 /* First doubleword. */
498 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
499 TD0_TCP_CS
= (1 << 16), /* Calculate TCP/IP checksum */
500 TD0_UDP_CS
= (1 << 17), /* Calculate UDP/IP checksum */
501 TD0_IP_CS
= (1 << 18), /* Calculate IP checksum */
504 /* 8102e, 8168c and beyond. */
505 enum rtl_tx_desc_bit_1
{
506 /* First doubleword. */
507 TD1_GTSENV4
= (1 << 26), /* Giant Send for IPv4 */
508 TD1_GTSENV6
= (1 << 25), /* Giant Send for IPv6 */
509 #define GTTCPHO_SHIFT 18
510 #define GTTCPHO_MAX 0x7f
512 /* Second doubleword. */
513 #define TCPHO_SHIFT 18
514 #define TCPHO_MAX 0x3ff
515 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
516 TD1_IPv6_CS
= (1 << 28), /* Calculate IPv6 checksum */
517 TD1_IPv4_CS
= (1 << 29), /* Calculate IPv4 checksum */
518 TD1_TCP_CS
= (1 << 30), /* Calculate TCP/IP checksum */
519 TD1_UDP_CS
= (1 << 31), /* Calculate UDP/IP checksum */
522 enum rtl_rx_desc_bit
{
524 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
525 PID0
= (1 << 17), /* Protocol ID bit 0/2 */
527 #define RxProtoUDP (PID1)
528 #define RxProtoTCP (PID0)
529 #define RxProtoIP (PID1 | PID0)
530 #define RxProtoMask RxProtoIP
532 IPFail
= (1 << 16), /* IP checksum failed */
533 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
534 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
536 #define RxCSFailMask (IPFail | UDPFail | TCPFail)
538 RxVlanTag
= (1 << 16), /* VLAN tag available */
541 #define RTL_GSO_MAX_SIZE_V1 32000
542 #define RTL_GSO_MAX_SEGS_V1 24
543 #define RTL_GSO_MAX_SIZE_V2 64000
544 #define RTL_GSO_MAX_SEGS_V2 64
563 struct rtl8169_counters
{
570 __le32 tx_one_collision
;
571 __le32 tx_multi_collision
;
579 struct rtl8169_tc_offsets
{
582 __le32 tx_multi_collision
;
588 RTL_FLAG_TASK_ENABLED
= 0,
589 RTL_FLAG_TASK_RESET_PENDING
,
599 struct rtl8169_private
{
600 void __iomem
*mmio_addr
; /* memory map physical address */
601 struct pci_dev
*pci_dev
;
602 struct net_device
*dev
;
603 struct phy_device
*phydev
;
604 struct napi_struct napi
;
605 enum mac_version mac_version
;
606 enum rtl_dash_type dash_type
;
607 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
608 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
610 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
611 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
612 dma_addr_t TxPhyAddr
;
613 dma_addr_t RxPhyAddr
;
614 struct page
*Rx_databuff
[NUM_RX_DESC
]; /* Rx data buffers */
615 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
621 DECLARE_BITMAP(flags
, RTL_FLAG_MAX
);
622 struct work_struct work
;
625 unsigned supports_gmii
:1;
626 unsigned aspm_manageable
:1;
627 dma_addr_t counters_phys_addr
;
628 struct rtl8169_counters
*counters
;
629 struct rtl8169_tc_offsets tc_offset
;
634 struct rtl_fw
*rtl_fw
;
639 typedef void (*rtl_generic_fct
)(struct rtl8169_private
*tp
);
641 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
642 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
643 MODULE_SOFTDEP("pre: realtek");
644 MODULE_LICENSE("GPL");
645 MODULE_FIRMWARE(FIRMWARE_8168D_1
);
646 MODULE_FIRMWARE(FIRMWARE_8168D_2
);
647 MODULE_FIRMWARE(FIRMWARE_8168E_1
);
648 MODULE_FIRMWARE(FIRMWARE_8168E_2
);
649 MODULE_FIRMWARE(FIRMWARE_8168E_3
);
650 MODULE_FIRMWARE(FIRMWARE_8105E_1
);
651 MODULE_FIRMWARE(FIRMWARE_8168F_1
);
652 MODULE_FIRMWARE(FIRMWARE_8168F_2
);
653 MODULE_FIRMWARE(FIRMWARE_8402_1
);
654 MODULE_FIRMWARE(FIRMWARE_8411_1
);
655 MODULE_FIRMWARE(FIRMWARE_8411_2
);
656 MODULE_FIRMWARE(FIRMWARE_8106E_1
);
657 MODULE_FIRMWARE(FIRMWARE_8106E_2
);
658 MODULE_FIRMWARE(FIRMWARE_8168G_2
);
659 MODULE_FIRMWARE(FIRMWARE_8168G_3
);
660 MODULE_FIRMWARE(FIRMWARE_8168H_1
);
661 MODULE_FIRMWARE(FIRMWARE_8168H_2
);
662 MODULE_FIRMWARE(FIRMWARE_8168FP_3
);
663 MODULE_FIRMWARE(FIRMWARE_8107E_1
);
664 MODULE_FIRMWARE(FIRMWARE_8107E_2
);
665 MODULE_FIRMWARE(FIRMWARE_8125A_3
);
666 MODULE_FIRMWARE(FIRMWARE_8125B_2
);
668 static inline struct device
*tp_to_dev(struct rtl8169_private
*tp
)
670 return &tp
->pci_dev
->dev
;
673 static void rtl_lock_config_regs(struct rtl8169_private
*tp
)
675 RTL_W8(tp
, Cfg9346
, Cfg9346_Lock
);
678 static void rtl_unlock_config_regs(struct rtl8169_private
*tp
)
680 RTL_W8(tp
, Cfg9346
, Cfg9346_Unlock
);
683 static void rtl_pci_commit(struct rtl8169_private
*tp
)
685 /* Read an arbitrary register to commit a preceding PCI write */
689 static bool rtl_is_8125(struct rtl8169_private
*tp
)
691 return tp
->mac_version
>= RTL_GIGA_MAC_VER_60
;
694 static bool rtl_is_8168evl_up(struct rtl8169_private
*tp
)
696 return tp
->mac_version
>= RTL_GIGA_MAC_VER_34
&&
697 tp
->mac_version
!= RTL_GIGA_MAC_VER_39
&&
698 tp
->mac_version
<= RTL_GIGA_MAC_VER_53
;
701 static bool rtl_supports_eee(struct rtl8169_private
*tp
)
703 return tp
->mac_version
>= RTL_GIGA_MAC_VER_34
&&
704 tp
->mac_version
!= RTL_GIGA_MAC_VER_37
&&
705 tp
->mac_version
!= RTL_GIGA_MAC_VER_39
;
708 static void rtl_read_mac_from_reg(struct rtl8169_private
*tp
, u8
*mac
, int reg
)
712 for (i
= 0; i
< ETH_ALEN
; i
++)
713 mac
[i
] = RTL_R8(tp
, reg
+ i
);
717 bool (*check
)(struct rtl8169_private
*);
721 static bool rtl_loop_wait(struct rtl8169_private
*tp
, const struct rtl_cond
*c
,
722 unsigned long usecs
, int n
, bool high
)
726 for (i
= 0; i
< n
; i
++) {
727 if (c
->check(tp
) == high
)
733 netdev_err(tp
->dev
, "%s == %d (loop: %d, delay: %lu).\n",
734 c
->msg
, !high
, n
, usecs
);
738 static bool rtl_loop_wait_high(struct rtl8169_private
*tp
,
739 const struct rtl_cond
*c
,
740 unsigned long d
, int n
)
742 return rtl_loop_wait(tp
, c
, d
, n
, true);
745 static bool rtl_loop_wait_low(struct rtl8169_private
*tp
,
746 const struct rtl_cond
*c
,
747 unsigned long d
, int n
)
749 return rtl_loop_wait(tp
, c
, d
, n
, false);
752 #define DECLARE_RTL_COND(name) \
753 static bool name ## _check(struct rtl8169_private *); \
755 static const struct rtl_cond name = { \
756 .check = name ## _check, \
760 static bool name ## _check(struct rtl8169_private *tp)
762 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private
*tp
, u32
*cmd
, int type
)
764 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */
765 if (type
== ERIAR_OOB
&&
766 (tp
->mac_version
== RTL_GIGA_MAC_VER_52
||
767 tp
->mac_version
== RTL_GIGA_MAC_VER_53
))
771 DECLARE_RTL_COND(rtl_eriar_cond
)
773 return RTL_R32(tp
, ERIAR
) & ERIAR_FLAG
;
776 static void _rtl_eri_write(struct rtl8169_private
*tp
, int addr
, u32 mask
,
779 u32 cmd
= ERIAR_WRITE_CMD
| type
| mask
| addr
;
781 if (WARN(addr
& 3 || !mask
, "addr: 0x%x, mask: 0x%08x\n", addr
, mask
))
784 RTL_W32(tp
, ERIDR
, val
);
785 r8168fp_adjust_ocp_cmd(tp
, &cmd
, type
);
786 RTL_W32(tp
, ERIAR
, cmd
);
788 rtl_loop_wait_low(tp
, &rtl_eriar_cond
, 100, 100);
791 static void rtl_eri_write(struct rtl8169_private
*tp
, int addr
, u32 mask
,
794 _rtl_eri_write(tp
, addr
, mask
, val
, ERIAR_EXGMAC
);
797 static u32
_rtl_eri_read(struct rtl8169_private
*tp
, int addr
, int type
)
799 u32 cmd
= ERIAR_READ_CMD
| type
| ERIAR_MASK_1111
| addr
;
801 r8168fp_adjust_ocp_cmd(tp
, &cmd
, type
);
802 RTL_W32(tp
, ERIAR
, cmd
);
804 return rtl_loop_wait_high(tp
, &rtl_eriar_cond
, 100, 100) ?
805 RTL_R32(tp
, ERIDR
) : ~0;
808 static u32
rtl_eri_read(struct rtl8169_private
*tp
, int addr
)
810 return _rtl_eri_read(tp
, addr
, ERIAR_EXGMAC
);
813 static void rtl_w0w1_eri(struct rtl8169_private
*tp
, int addr
, u32 p
, u32 m
)
815 u32 val
= rtl_eri_read(tp
, addr
);
817 rtl_eri_write(tp
, addr
, ERIAR_MASK_1111
, (val
& ~m
) | p
);
820 static void rtl_eri_set_bits(struct rtl8169_private
*tp
, int addr
, u32 p
)
822 rtl_w0w1_eri(tp
, addr
, p
, 0);
825 static void rtl_eri_clear_bits(struct rtl8169_private
*tp
, int addr
, u32 m
)
827 rtl_w0w1_eri(tp
, addr
, 0, m
);
830 static bool rtl_ocp_reg_failure(u32 reg
)
832 return WARN_ONCE(reg
& 0xffff0001, "Invalid ocp reg %x!\n", reg
);
835 DECLARE_RTL_COND(rtl_ocp_gphy_cond
)
837 return RTL_R32(tp
, GPHY_OCP
) & OCPAR_FLAG
;
840 static void r8168_phy_ocp_write(struct rtl8169_private
*tp
, u32 reg
, u32 data
)
842 if (rtl_ocp_reg_failure(reg
))
845 RTL_W32(tp
, GPHY_OCP
, OCPAR_FLAG
| (reg
<< 15) | data
);
847 rtl_loop_wait_low(tp
, &rtl_ocp_gphy_cond
, 25, 10);
850 static int r8168_phy_ocp_read(struct rtl8169_private
*tp
, u32 reg
)
852 if (rtl_ocp_reg_failure(reg
))
855 RTL_W32(tp
, GPHY_OCP
, reg
<< 15);
857 return rtl_loop_wait_high(tp
, &rtl_ocp_gphy_cond
, 25, 10) ?
858 (RTL_R32(tp
, GPHY_OCP
) & 0xffff) : -ETIMEDOUT
;
861 static void r8168_mac_ocp_write(struct rtl8169_private
*tp
, u32 reg
, u32 data
)
863 if (rtl_ocp_reg_failure(reg
))
866 RTL_W32(tp
, OCPDR
, OCPAR_FLAG
| (reg
<< 15) | data
);
869 static u16
r8168_mac_ocp_read(struct rtl8169_private
*tp
, u32 reg
)
871 if (rtl_ocp_reg_failure(reg
))
874 RTL_W32(tp
, OCPDR
, reg
<< 15);
876 return RTL_R32(tp
, OCPDR
);
879 static void r8168_mac_ocp_modify(struct rtl8169_private
*tp
, u32 reg
, u16 mask
,
882 u16 data
= r8168_mac_ocp_read(tp
, reg
);
884 r8168_mac_ocp_write(tp
, reg
, (data
& ~mask
) | set
);
887 /* Work around a hw issue with RTL8168g PHY, the quirk disables
888 * PHY MCU interrupts before PHY power-down.
890 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private
*tp
, int value
)
892 switch (tp
->mac_version
) {
893 case RTL_GIGA_MAC_VER_40
:
894 case RTL_GIGA_MAC_VER_41
:
895 case RTL_GIGA_MAC_VER_49
:
896 if (value
& BMCR_RESET
|| !(value
& BMCR_PDOWN
))
897 rtl_eri_set_bits(tp
, 0x1a8, 0xfc000000);
899 rtl_eri_clear_bits(tp
, 0x1a8, 0xfc000000);
906 static void r8168g_mdio_write(struct rtl8169_private
*tp
, int reg
, int value
)
909 tp
->ocp_base
= value
? value
<< 4 : OCP_STD_PHY_BASE
;
913 if (tp
->ocp_base
!= OCP_STD_PHY_BASE
)
916 if (tp
->ocp_base
== OCP_STD_PHY_BASE
&& reg
== MII_BMCR
)
917 rtl8168g_phy_suspend_quirk(tp
, value
);
919 r8168_phy_ocp_write(tp
, tp
->ocp_base
+ reg
* 2, value
);
922 static int r8168g_mdio_read(struct rtl8169_private
*tp
, int reg
)
925 return tp
->ocp_base
== OCP_STD_PHY_BASE
? 0 : tp
->ocp_base
>> 4;
927 if (tp
->ocp_base
!= OCP_STD_PHY_BASE
)
930 return r8168_phy_ocp_read(tp
, tp
->ocp_base
+ reg
* 2);
933 static void mac_mcu_write(struct rtl8169_private
*tp
, int reg
, int value
)
936 tp
->ocp_base
= value
<< 4;
940 r8168_mac_ocp_write(tp
, tp
->ocp_base
+ reg
, value
);
943 static int mac_mcu_read(struct rtl8169_private
*tp
, int reg
)
945 return r8168_mac_ocp_read(tp
, tp
->ocp_base
+ reg
);
948 DECLARE_RTL_COND(rtl_phyar_cond
)
950 return RTL_R32(tp
, PHYAR
) & 0x80000000;
953 static void r8169_mdio_write(struct rtl8169_private
*tp
, int reg
, int value
)
955 RTL_W32(tp
, PHYAR
, 0x80000000 | (reg
& 0x1f) << 16 | (value
& 0xffff));
957 rtl_loop_wait_low(tp
, &rtl_phyar_cond
, 25, 20);
959 * According to hardware specs a 20us delay is required after write
960 * complete indication, but before sending next command.
965 static int r8169_mdio_read(struct rtl8169_private
*tp
, int reg
)
969 RTL_W32(tp
, PHYAR
, 0x0 | (reg
& 0x1f) << 16);
971 value
= rtl_loop_wait_high(tp
, &rtl_phyar_cond
, 25, 20) ?
972 RTL_R32(tp
, PHYAR
) & 0xffff : -ETIMEDOUT
;
975 * According to hardware specs a 20us delay is required after read
976 * complete indication, but before sending next command.
983 DECLARE_RTL_COND(rtl_ocpar_cond
)
985 return RTL_R32(tp
, OCPAR
) & OCPAR_FLAG
;
988 static void r8168dp_1_mdio_access(struct rtl8169_private
*tp
, int reg
, u32 data
)
990 RTL_W32(tp
, OCPDR
, data
| ((reg
& OCPDR_REG_MASK
) << OCPDR_GPHY_REG_SHIFT
));
991 RTL_W32(tp
, OCPAR
, OCPAR_GPHY_WRITE_CMD
);
992 RTL_W32(tp
, EPHY_RXER_NUM
, 0);
994 rtl_loop_wait_low(tp
, &rtl_ocpar_cond
, 1000, 100);
997 static void r8168dp_1_mdio_write(struct rtl8169_private
*tp
, int reg
, int value
)
999 r8168dp_1_mdio_access(tp
, reg
,
1000 OCPDR_WRITE_CMD
| (value
& OCPDR_DATA_MASK
));
1003 static int r8168dp_1_mdio_read(struct rtl8169_private
*tp
, int reg
)
1005 r8168dp_1_mdio_access(tp
, reg
, OCPDR_READ_CMD
);
1008 RTL_W32(tp
, OCPAR
, OCPAR_GPHY_READ_CMD
);
1009 RTL_W32(tp
, EPHY_RXER_NUM
, 0);
1011 return rtl_loop_wait_high(tp
, &rtl_ocpar_cond
, 1000, 100) ?
1012 RTL_R32(tp
, OCPDR
) & OCPDR_DATA_MASK
: -ETIMEDOUT
;
1015 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1017 static void r8168dp_2_mdio_start(struct rtl8169_private
*tp
)
1019 RTL_W32(tp
, 0xd0, RTL_R32(tp
, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT
);
1022 static void r8168dp_2_mdio_stop(struct rtl8169_private
*tp
)
1024 RTL_W32(tp
, 0xd0, RTL_R32(tp
, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT
);
1027 static void r8168dp_2_mdio_write(struct rtl8169_private
*tp
, int reg
, int value
)
1029 r8168dp_2_mdio_start(tp
);
1031 r8169_mdio_write(tp
, reg
, value
);
1033 r8168dp_2_mdio_stop(tp
);
1036 static int r8168dp_2_mdio_read(struct rtl8169_private
*tp
, int reg
)
1040 /* Work around issue with chip reporting wrong PHY ID */
1041 if (reg
== MII_PHYSID2
)
1044 r8168dp_2_mdio_start(tp
);
1046 value
= r8169_mdio_read(tp
, reg
);
1048 r8168dp_2_mdio_stop(tp
);
1053 static void rtl_writephy(struct rtl8169_private
*tp
, int location
, int val
)
1055 switch (tp
->mac_version
) {
1056 case RTL_GIGA_MAC_VER_27
:
1057 r8168dp_1_mdio_write(tp
, location
, val
);
1059 case RTL_GIGA_MAC_VER_28
:
1060 case RTL_GIGA_MAC_VER_31
:
1061 r8168dp_2_mdio_write(tp
, location
, val
);
1063 case RTL_GIGA_MAC_VER_40
... RTL_GIGA_MAC_VER_63
:
1064 r8168g_mdio_write(tp
, location
, val
);
1067 r8169_mdio_write(tp
, location
, val
);
1072 static int rtl_readphy(struct rtl8169_private
*tp
, int location
)
1074 switch (tp
->mac_version
) {
1075 case RTL_GIGA_MAC_VER_27
:
1076 return r8168dp_1_mdio_read(tp
, location
);
1077 case RTL_GIGA_MAC_VER_28
:
1078 case RTL_GIGA_MAC_VER_31
:
1079 return r8168dp_2_mdio_read(tp
, location
);
1080 case RTL_GIGA_MAC_VER_40
... RTL_GIGA_MAC_VER_63
:
1081 return r8168g_mdio_read(tp
, location
);
1083 return r8169_mdio_read(tp
, location
);
1087 DECLARE_RTL_COND(rtl_ephyar_cond
)
1089 return RTL_R32(tp
, EPHYAR
) & EPHYAR_FLAG
;
1092 static void rtl_ephy_write(struct rtl8169_private
*tp
, int reg_addr
, int value
)
1094 RTL_W32(tp
, EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
1095 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
1097 rtl_loop_wait_low(tp
, &rtl_ephyar_cond
, 10, 100);
1102 static u16
rtl_ephy_read(struct rtl8169_private
*tp
, int reg_addr
)
1104 RTL_W32(tp
, EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
1106 return rtl_loop_wait_high(tp
, &rtl_ephyar_cond
, 10, 100) ?
1107 RTL_R32(tp
, EPHYAR
) & EPHYAR_DATA_MASK
: ~0;
1110 static u32
r8168dp_ocp_read(struct rtl8169_private
*tp
, u16 reg
)
1112 RTL_W32(tp
, OCPAR
, 0x0fu
<< 12 | (reg
& 0x0fff));
1113 return rtl_loop_wait_high(tp
, &rtl_ocpar_cond
, 100, 20) ?
1114 RTL_R32(tp
, OCPDR
) : ~0;
1117 static u32
r8168ep_ocp_read(struct rtl8169_private
*tp
, u16 reg
)
1119 return _rtl_eri_read(tp
, reg
, ERIAR_OOB
);
1122 static void r8168dp_ocp_write(struct rtl8169_private
*tp
, u8 mask
, u16 reg
,
1125 RTL_W32(tp
, OCPDR
, data
);
1126 RTL_W32(tp
, OCPAR
, OCPAR_FLAG
| ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
1127 rtl_loop_wait_low(tp
, &rtl_ocpar_cond
, 100, 20);
1130 static void r8168ep_ocp_write(struct rtl8169_private
*tp
, u8 mask
, u16 reg
,
1133 _rtl_eri_write(tp
, reg
, ((u32
)mask
& 0x0f) << ERIAR_MASK_SHIFT
,
1137 static void r8168dp_oob_notify(struct rtl8169_private
*tp
, u8 cmd
)
1139 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_0001
, cmd
);
1141 r8168dp_ocp_write(tp
, 0x1, 0x30, 0x00000001);
1144 #define OOB_CMD_RESET 0x00
1145 #define OOB_CMD_DRIVER_START 0x05
1146 #define OOB_CMD_DRIVER_STOP 0x06
1148 static u16
rtl8168_get_ocp_reg(struct rtl8169_private
*tp
)
1150 return (tp
->mac_version
== RTL_GIGA_MAC_VER_31
) ? 0xb8 : 0x10;
1153 DECLARE_RTL_COND(rtl_dp_ocp_read_cond
)
1157 reg
= rtl8168_get_ocp_reg(tp
);
1159 return r8168dp_ocp_read(tp
, reg
) & 0x00000800;
1162 DECLARE_RTL_COND(rtl_ep_ocp_read_cond
)
1164 return r8168ep_ocp_read(tp
, 0x124) & 0x00000001;
1167 DECLARE_RTL_COND(rtl_ocp_tx_cond
)
1169 return RTL_R8(tp
, IBISR0
) & 0x20;
1172 static void rtl8168ep_stop_cmac(struct rtl8169_private
*tp
)
1174 RTL_W8(tp
, IBCR2
, RTL_R8(tp
, IBCR2
) & ~0x01);
1175 rtl_loop_wait_high(tp
, &rtl_ocp_tx_cond
, 50000, 2000);
1176 RTL_W8(tp
, IBISR0
, RTL_R8(tp
, IBISR0
) | 0x20);
1177 RTL_W8(tp
, IBCR0
, RTL_R8(tp
, IBCR0
) & ~0x01);
1180 static void rtl8168dp_driver_start(struct rtl8169_private
*tp
)
1182 r8168dp_oob_notify(tp
, OOB_CMD_DRIVER_START
);
1183 rtl_loop_wait_high(tp
, &rtl_dp_ocp_read_cond
, 10000, 10);
1186 static void rtl8168ep_driver_start(struct rtl8169_private
*tp
)
1188 r8168ep_ocp_write(tp
, 0x01, 0x180, OOB_CMD_DRIVER_START
);
1189 r8168ep_ocp_write(tp
, 0x01, 0x30, r8168ep_ocp_read(tp
, 0x30) | 0x01);
1190 rtl_loop_wait_high(tp
, &rtl_ep_ocp_read_cond
, 10000, 10);
1193 static void rtl8168_driver_start(struct rtl8169_private
*tp
)
1195 if (tp
->dash_type
== RTL_DASH_DP
)
1196 rtl8168dp_driver_start(tp
);
1198 rtl8168ep_driver_start(tp
);
1201 static void rtl8168dp_driver_stop(struct rtl8169_private
*tp
)
1203 r8168dp_oob_notify(tp
, OOB_CMD_DRIVER_STOP
);
1204 rtl_loop_wait_low(tp
, &rtl_dp_ocp_read_cond
, 10000, 10);
1207 static void rtl8168ep_driver_stop(struct rtl8169_private
*tp
)
1209 rtl8168ep_stop_cmac(tp
);
1210 r8168ep_ocp_write(tp
, 0x01, 0x180, OOB_CMD_DRIVER_STOP
);
1211 r8168ep_ocp_write(tp
, 0x01, 0x30, r8168ep_ocp_read(tp
, 0x30) | 0x01);
1212 rtl_loop_wait_low(tp
, &rtl_ep_ocp_read_cond
, 10000, 10);
1215 static void rtl8168_driver_stop(struct rtl8169_private
*tp
)
1217 if (tp
->dash_type
== RTL_DASH_DP
)
1218 rtl8168dp_driver_stop(tp
);
1220 rtl8168ep_driver_stop(tp
);
1223 static bool r8168dp_check_dash(struct rtl8169_private
*tp
)
1225 u16 reg
= rtl8168_get_ocp_reg(tp
);
1227 return r8168dp_ocp_read(tp
, reg
) & BIT(15);
1230 static bool r8168ep_check_dash(struct rtl8169_private
*tp
)
1232 return r8168ep_ocp_read(tp
, 0x128) & BIT(0);
1235 static enum rtl_dash_type
rtl_check_dash(struct rtl8169_private
*tp
)
1237 switch (tp
->mac_version
) {
1238 case RTL_GIGA_MAC_VER_27
:
1239 case RTL_GIGA_MAC_VER_28
:
1240 case RTL_GIGA_MAC_VER_31
:
1241 return r8168dp_check_dash(tp
) ? RTL_DASH_DP
: RTL_DASH_NONE
;
1242 case RTL_GIGA_MAC_VER_49
... RTL_GIGA_MAC_VER_53
:
1243 return r8168ep_check_dash(tp
) ? RTL_DASH_EP
: RTL_DASH_NONE
;
1245 return RTL_DASH_NONE
;
1249 static void rtl_set_d3_pll_down(struct rtl8169_private
*tp
, bool enable
)
1251 switch (tp
->mac_version
) {
1252 case RTL_GIGA_MAC_VER_25
... RTL_GIGA_MAC_VER_26
:
1253 case RTL_GIGA_MAC_VER_29
... RTL_GIGA_MAC_VER_30
:
1254 case RTL_GIGA_MAC_VER_32
... RTL_GIGA_MAC_VER_37
:
1255 case RTL_GIGA_MAC_VER_39
... RTL_GIGA_MAC_VER_63
:
1257 RTL_W8(tp
, PMCH
, RTL_R8(tp
, PMCH
) & ~D3_NO_PLL_DOWN
);
1259 RTL_W8(tp
, PMCH
, RTL_R8(tp
, PMCH
) | D3_NO_PLL_DOWN
);
1266 static void rtl_reset_packet_filter(struct rtl8169_private
*tp
)
1268 rtl_eri_clear_bits(tp
, 0xdc, BIT(0));
1269 rtl_eri_set_bits(tp
, 0xdc, BIT(0));
1272 DECLARE_RTL_COND(rtl_efusear_cond
)
1274 return RTL_R32(tp
, EFUSEAR
) & EFUSEAR_FLAG
;
1277 u8
rtl8168d_efuse_read(struct rtl8169_private
*tp
, int reg_addr
)
1279 RTL_W32(tp
, EFUSEAR
, (reg_addr
& EFUSEAR_REG_MASK
) << EFUSEAR_REG_SHIFT
);
1281 return rtl_loop_wait_high(tp
, &rtl_efusear_cond
, 100, 300) ?
1282 RTL_R32(tp
, EFUSEAR
) & EFUSEAR_DATA_MASK
: ~0;
1285 static u32
rtl_get_events(struct rtl8169_private
*tp
)
1287 if (rtl_is_8125(tp
))
1288 return RTL_R32(tp
, IntrStatus_8125
);
1290 return RTL_R16(tp
, IntrStatus
);
1293 static void rtl_ack_events(struct rtl8169_private
*tp
, u32 bits
)
1295 if (rtl_is_8125(tp
))
1296 RTL_W32(tp
, IntrStatus_8125
, bits
);
1298 RTL_W16(tp
, IntrStatus
, bits
);
1301 static void rtl_irq_disable(struct rtl8169_private
*tp
)
1303 if (rtl_is_8125(tp
))
1304 RTL_W32(tp
, IntrMask_8125
, 0);
1306 RTL_W16(tp
, IntrMask
, 0);
1309 static void rtl_irq_enable(struct rtl8169_private
*tp
)
1311 if (rtl_is_8125(tp
))
1312 RTL_W32(tp
, IntrMask_8125
, tp
->irq_mask
);
1314 RTL_W16(tp
, IntrMask
, tp
->irq_mask
);
1317 static void rtl8169_irq_mask_and_ack(struct rtl8169_private
*tp
)
1319 rtl_irq_disable(tp
);
1320 rtl_ack_events(tp
, 0xffffffff);
1324 static void rtl_link_chg_patch(struct rtl8169_private
*tp
)
1326 struct phy_device
*phydev
= tp
->phydev
;
1328 if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
||
1329 tp
->mac_version
== RTL_GIGA_MAC_VER_38
) {
1330 if (phydev
->speed
== SPEED_1000
) {
1331 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x00000011);
1332 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x00000005);
1333 } else if (phydev
->speed
== SPEED_100
) {
1334 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x0000001f);
1335 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x00000005);
1337 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x0000001f);
1338 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x0000003f);
1340 rtl_reset_packet_filter(tp
);
1341 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_35
||
1342 tp
->mac_version
== RTL_GIGA_MAC_VER_36
) {
1343 if (phydev
->speed
== SPEED_1000
) {
1344 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x00000011);
1345 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x00000005);
1347 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x0000001f);
1348 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x0000003f);
1350 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_37
) {
1351 if (phydev
->speed
== SPEED_10
) {
1352 rtl_eri_write(tp
, 0x1d0, ERIAR_MASK_0011
, 0x4d02);
1353 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_0011
, 0x0060a);
1355 rtl_eri_write(tp
, 0x1d0, ERIAR_MASK_0011
, 0x0000);
1360 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1362 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1364 struct rtl8169_private
*tp
= netdev_priv(dev
);
1366 wol
->supported
= WAKE_ANY
;
1367 wol
->wolopts
= tp
->saved_wolopts
;
1370 static void __rtl8169_set_wol(struct rtl8169_private
*tp
, u32 wolopts
)
1372 static const struct {
1377 { WAKE_PHY
, Config3
, LinkUp
},
1378 { WAKE_UCAST
, Config5
, UWF
},
1379 { WAKE_BCAST
, Config5
, BWF
},
1380 { WAKE_MCAST
, Config5
, MWF
},
1381 { WAKE_ANY
, Config5
, LanWake
},
1382 { WAKE_MAGIC
, Config3
, MagicPacket
}
1384 unsigned int i
, tmp
= ARRAY_SIZE(cfg
);
1387 rtl_unlock_config_regs(tp
);
1389 if (rtl_is_8168evl_up(tp
)) {
1391 if (wolopts
& WAKE_MAGIC
)
1392 rtl_eri_set_bits(tp
, 0x0dc, MagicPacket_v2
);
1394 rtl_eri_clear_bits(tp
, 0x0dc, MagicPacket_v2
);
1395 } else if (rtl_is_8125(tp
)) {
1397 if (wolopts
& WAKE_MAGIC
)
1398 r8168_mac_ocp_modify(tp
, 0xc0b6, 0, BIT(0));
1400 r8168_mac_ocp_modify(tp
, 0xc0b6, BIT(0), 0);
1403 for (i
= 0; i
< tmp
; i
++) {
1404 options
= RTL_R8(tp
, cfg
[i
].reg
) & ~cfg
[i
].mask
;
1405 if (wolopts
& cfg
[i
].opt
)
1406 options
|= cfg
[i
].mask
;
1407 RTL_W8(tp
, cfg
[i
].reg
, options
);
1410 switch (tp
->mac_version
) {
1411 case RTL_GIGA_MAC_VER_02
... RTL_GIGA_MAC_VER_06
:
1412 options
= RTL_R8(tp
, Config1
) & ~PMEnable
;
1414 options
|= PMEnable
;
1415 RTL_W8(tp
, Config1
, options
);
1417 case RTL_GIGA_MAC_VER_34
:
1418 case RTL_GIGA_MAC_VER_37
:
1419 case RTL_GIGA_MAC_VER_39
... RTL_GIGA_MAC_VER_63
:
1420 options
= RTL_R8(tp
, Config2
) & ~PME_SIGNAL
;
1422 options
|= PME_SIGNAL
;
1423 RTL_W8(tp
, Config2
, options
);
1429 rtl_lock_config_regs(tp
);
1431 device_set_wakeup_enable(tp_to_dev(tp
), wolopts
);
1432 rtl_set_d3_pll_down(tp
, !wolopts
);
1433 tp
->dev
->wol_enabled
= wolopts
? 1 : 0;
1436 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1438 struct rtl8169_private
*tp
= netdev_priv(dev
);
1440 if (wol
->wolopts
& ~WAKE_ANY
)
1443 tp
->saved_wolopts
= wol
->wolopts
;
1444 __rtl8169_set_wol(tp
, tp
->saved_wolopts
);
1449 static void rtl8169_get_drvinfo(struct net_device
*dev
,
1450 struct ethtool_drvinfo
*info
)
1452 struct rtl8169_private
*tp
= netdev_priv(dev
);
1453 struct rtl_fw
*rtl_fw
= tp
->rtl_fw
;
1455 strlcpy(info
->driver
, KBUILD_MODNAME
, sizeof(info
->driver
));
1456 strlcpy(info
->bus_info
, pci_name(tp
->pci_dev
), sizeof(info
->bus_info
));
1457 BUILD_BUG_ON(sizeof(info
->fw_version
) < sizeof(rtl_fw
->version
));
1459 strlcpy(info
->fw_version
, rtl_fw
->version
,
1460 sizeof(info
->fw_version
));
1463 static int rtl8169_get_regs_len(struct net_device
*dev
)
1465 return R8169_REGS_SIZE
;
1468 static netdev_features_t
rtl8169_fix_features(struct net_device
*dev
,
1469 netdev_features_t features
)
1471 struct rtl8169_private
*tp
= netdev_priv(dev
);
1473 if (dev
->mtu
> TD_MSS_MAX
)
1474 features
&= ~NETIF_F_ALL_TSO
;
1476 if (dev
->mtu
> ETH_DATA_LEN
&&
1477 tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
1478 features
&= ~(NETIF_F_CSUM_MASK
| NETIF_F_ALL_TSO
);
1483 static void rtl_set_rx_config_features(struct rtl8169_private
*tp
,
1484 netdev_features_t features
)
1486 u32 rx_config
= RTL_R32(tp
, RxConfig
);
1488 if (features
& NETIF_F_RXALL
)
1489 rx_config
|= RX_CONFIG_ACCEPT_ERR_MASK
;
1491 rx_config
&= ~RX_CONFIG_ACCEPT_ERR_MASK
;
1493 if (rtl_is_8125(tp
)) {
1494 if (features
& NETIF_F_HW_VLAN_CTAG_RX
)
1495 rx_config
|= RX_VLAN_8125
;
1497 rx_config
&= ~RX_VLAN_8125
;
1500 RTL_W32(tp
, RxConfig
, rx_config
);
1503 static int rtl8169_set_features(struct net_device
*dev
,
1504 netdev_features_t features
)
1506 struct rtl8169_private
*tp
= netdev_priv(dev
);
1508 rtl_set_rx_config_features(tp
, features
);
1510 if (features
& NETIF_F_RXCSUM
)
1511 tp
->cp_cmd
|= RxChkSum
;
1513 tp
->cp_cmd
&= ~RxChkSum
;
1515 if (!rtl_is_8125(tp
)) {
1516 if (features
& NETIF_F_HW_VLAN_CTAG_RX
)
1517 tp
->cp_cmd
|= RxVlan
;
1519 tp
->cp_cmd
&= ~RxVlan
;
1522 RTL_W16(tp
, CPlusCmd
, tp
->cp_cmd
);
1528 static inline u32
rtl8169_tx_vlan_tag(struct sk_buff
*skb
)
1530 return (skb_vlan_tag_present(skb
)) ?
1531 TxVlanTag
| swab16(skb_vlan_tag_get(skb
)) : 0x00;
1534 static void rtl8169_rx_vlan_tag(struct RxDesc
*desc
, struct sk_buff
*skb
)
1536 u32 opts2
= le32_to_cpu(desc
->opts2
);
1538 if (opts2
& RxVlanTag
)
1539 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
), swab16(opts2
& 0xffff));
1542 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1545 struct rtl8169_private
*tp
= netdev_priv(dev
);
1546 u32 __iomem
*data
= tp
->mmio_addr
;
1550 for (i
= 0; i
< R8169_REGS_SIZE
; i
+= 4)
1551 memcpy_fromio(dw
++, data
++, 4);
1554 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
1561 "tx_single_collisions",
1562 "tx_multi_collisions",
1570 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
1574 return ARRAY_SIZE(rtl8169_gstrings
);
1580 DECLARE_RTL_COND(rtl_counters_cond
)
1582 return RTL_R32(tp
, CounterAddrLow
) & (CounterReset
| CounterDump
);
1585 static void rtl8169_do_counters(struct rtl8169_private
*tp
, u32 counter_cmd
)
1587 u32 cmd
= lower_32_bits(tp
->counters_phys_addr
);
1589 RTL_W32(tp
, CounterAddrHigh
, upper_32_bits(tp
->counters_phys_addr
));
1591 RTL_W32(tp
, CounterAddrLow
, cmd
);
1592 RTL_W32(tp
, CounterAddrLow
, cmd
| counter_cmd
);
1594 rtl_loop_wait_low(tp
, &rtl_counters_cond
, 10, 1000);
1597 static void rtl8169_update_counters(struct rtl8169_private
*tp
)
1599 u8 val
= RTL_R8(tp
, ChipCmd
);
1602 * Some chips are unable to dump tally counters when the receiver
1603 * is disabled. If 0xff chip may be in a PCI power-save state.
1605 if (val
& CmdRxEnb
&& val
!= 0xff)
1606 rtl8169_do_counters(tp
, CounterDump
);
1609 static void rtl8169_init_counter_offsets(struct rtl8169_private
*tp
)
1611 struct rtl8169_counters
*counters
= tp
->counters
;
1614 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1615 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1616 * reset by a power cycle, while the counter values collected by the
1617 * driver are reset at every driver unload/load cycle.
1619 * To make sure the HW values returned by @get_stats64 match the SW
1620 * values, we collect the initial values at first open(*) and use them
1621 * as offsets to normalize the values returned by @get_stats64.
1623 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1624 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1625 * set at open time by rtl_hw_start.
1628 if (tp
->tc_offset
.inited
)
1631 if (tp
->mac_version
>= RTL_GIGA_MAC_VER_19
) {
1632 rtl8169_do_counters(tp
, CounterReset
);
1634 rtl8169_update_counters(tp
);
1635 tp
->tc_offset
.tx_errors
= counters
->tx_errors
;
1636 tp
->tc_offset
.tx_multi_collision
= counters
->tx_multi_collision
;
1637 tp
->tc_offset
.tx_aborted
= counters
->tx_aborted
;
1638 tp
->tc_offset
.rx_missed
= counters
->rx_missed
;
1641 tp
->tc_offset
.inited
= true;
1644 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
1645 struct ethtool_stats
*stats
, u64
*data
)
1647 struct rtl8169_private
*tp
= netdev_priv(dev
);
1648 struct rtl8169_counters
*counters
;
1650 counters
= tp
->counters
;
1651 rtl8169_update_counters(tp
);
1653 data
[0] = le64_to_cpu(counters
->tx_packets
);
1654 data
[1] = le64_to_cpu(counters
->rx_packets
);
1655 data
[2] = le64_to_cpu(counters
->tx_errors
);
1656 data
[3] = le32_to_cpu(counters
->rx_errors
);
1657 data
[4] = le16_to_cpu(counters
->rx_missed
);
1658 data
[5] = le16_to_cpu(counters
->align_errors
);
1659 data
[6] = le32_to_cpu(counters
->tx_one_collision
);
1660 data
[7] = le32_to_cpu(counters
->tx_multi_collision
);
1661 data
[8] = le64_to_cpu(counters
->rx_unicast
);
1662 data
[9] = le64_to_cpu(counters
->rx_broadcast
);
1663 data
[10] = le32_to_cpu(counters
->rx_multicast
);
1664 data
[11] = le16_to_cpu(counters
->tx_aborted
);
1665 data
[12] = le16_to_cpu(counters
->tx_underun
);
1668 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1672 memcpy(data
, rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
1678 * Interrupt coalescing
1680 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1681 * > 8169, 8168 and 810x line of chipsets
1683 * 8169, 8168, and 8136(810x) serial chipsets support it.
1685 * > 2 - the Tx timer unit at gigabit speed
1687 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1688 * (0xe0) bit 1 and bit 0.
1691 * bit[1:0] \ speed 1000M 100M 10M
1692 * 0 0 320ns 2.56us 40.96us
1693 * 0 1 2.56us 20.48us 327.7us
1694 * 1 0 5.12us 40.96us 655.4us
1695 * 1 1 10.24us 81.92us 1.31ms
1698 * bit[1:0] \ speed 1000M 100M 10M
1699 * 0 0 5us 2.56us 40.96us
1700 * 0 1 40us 20.48us 327.7us
1701 * 1 0 80us 40.96us 655.4us
1702 * 1 1 160us 81.92us 1.31ms
1705 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1706 struct rtl_coalesce_info
{
1711 /* produce array with base delay *1, *8, *8*2, *8*2*2 */
1712 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) }
1714 static const struct rtl_coalesce_info rtl_coalesce_info_8169
[] = {
1715 { SPEED_1000
, COALESCE_DELAY(320) },
1716 { SPEED_100
, COALESCE_DELAY(2560) },
1717 { SPEED_10
, COALESCE_DELAY(40960) },
1721 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136
[] = {
1722 { SPEED_1000
, COALESCE_DELAY(5000) },
1723 { SPEED_100
, COALESCE_DELAY(2560) },
1724 { SPEED_10
, COALESCE_DELAY(40960) },
1727 #undef COALESCE_DELAY
1729 /* get rx/tx scale vector corresponding to current speed */
1730 static const struct rtl_coalesce_info
*
1731 rtl_coalesce_info(struct rtl8169_private
*tp
)
1733 const struct rtl_coalesce_info
*ci
;
1735 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
1736 ci
= rtl_coalesce_info_8169
;
1738 ci
= rtl_coalesce_info_8168_8136
;
1740 /* if speed is unknown assume highest one */
1741 if (tp
->phydev
->speed
== SPEED_UNKNOWN
)
1744 for (; ci
->speed
; ci
++) {
1745 if (tp
->phydev
->speed
== ci
->speed
)
1749 return ERR_PTR(-ELNRNG
);
1752 static int rtl_get_coalesce(struct net_device
*dev
,
1753 struct ethtool_coalesce
*ec
,
1754 struct kernel_ethtool_coalesce
*kernel_coal
,
1755 struct netlink_ext_ack
*extack
)
1757 struct rtl8169_private
*tp
= netdev_priv(dev
);
1758 const struct rtl_coalesce_info
*ci
;
1759 u32 scale
, c_us
, c_fr
;
1762 if (rtl_is_8125(tp
))
1765 memset(ec
, 0, sizeof(*ec
));
1767 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1768 ci
= rtl_coalesce_info(tp
);
1772 scale
= ci
->scale_nsecs
[tp
->cp_cmd
& INTT_MASK
];
1774 intrmit
= RTL_R16(tp
, IntrMitigate
);
1776 c_us
= FIELD_GET(RTL_COALESCE_TX_USECS
, intrmit
);
1777 ec
->tx_coalesce_usecs
= DIV_ROUND_UP(c_us
* scale
, 1000);
1779 c_fr
= FIELD_GET(RTL_COALESCE_TX_FRAMES
, intrmit
);
1780 /* ethtool_coalesce states usecs and max_frames must not both be 0 */
1781 ec
->tx_max_coalesced_frames
= (c_us
|| c_fr
) ? c_fr
* 4 : 1;
1783 c_us
= FIELD_GET(RTL_COALESCE_RX_USECS
, intrmit
);
1784 ec
->rx_coalesce_usecs
= DIV_ROUND_UP(c_us
* scale
, 1000);
1786 c_fr
= FIELD_GET(RTL_COALESCE_RX_FRAMES
, intrmit
);
1787 ec
->rx_max_coalesced_frames
= (c_us
|| c_fr
) ? c_fr
* 4 : 1;
1792 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
1793 static int rtl_coalesce_choose_scale(struct rtl8169_private
*tp
, u32 usec
,
1796 const struct rtl_coalesce_info
*ci
;
1799 ci
= rtl_coalesce_info(tp
);
1803 for (i
= 0; i
< 4; i
++) {
1804 if (usec
<= ci
->scale_nsecs
[i
] * RTL_COALESCE_T_MAX
/ 1000U) {
1806 return ci
->scale_nsecs
[i
];
1813 static int rtl_set_coalesce(struct net_device
*dev
,
1814 struct ethtool_coalesce
*ec
,
1815 struct kernel_ethtool_coalesce
*kernel_coal
,
1816 struct netlink_ext_ack
*extack
)
1818 struct rtl8169_private
*tp
= netdev_priv(dev
);
1819 u32 tx_fr
= ec
->tx_max_coalesced_frames
;
1820 u32 rx_fr
= ec
->rx_max_coalesced_frames
;
1821 u32 coal_usec_max
, units
;
1822 u16 w
= 0, cp01
= 0;
1825 if (rtl_is_8125(tp
))
1828 if (rx_fr
> RTL_COALESCE_FRAME_MAX
|| tx_fr
> RTL_COALESCE_FRAME_MAX
)
1831 coal_usec_max
= max(ec
->rx_coalesce_usecs
, ec
->tx_coalesce_usecs
);
1832 scale
= rtl_coalesce_choose_scale(tp
, coal_usec_max
, &cp01
);
1836 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it
1837 * not only when usecs=0 because of e.g. the following scenario:
1839 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1840 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1841 * - then user does `ethtool -C eth0 rx-usecs 100`
1843 * Since ethtool sends to kernel whole ethtool_coalesce settings,
1844 * if we want to ignore rx_frames then it has to be set to 0.
1851 /* HW requires time limit to be set if frame limit is set */
1852 if ((tx_fr
&& !ec
->tx_coalesce_usecs
) ||
1853 (rx_fr
&& !ec
->rx_coalesce_usecs
))
1856 w
|= FIELD_PREP(RTL_COALESCE_TX_FRAMES
, DIV_ROUND_UP(tx_fr
, 4));
1857 w
|= FIELD_PREP(RTL_COALESCE_RX_FRAMES
, DIV_ROUND_UP(rx_fr
, 4));
1859 units
= DIV_ROUND_UP(ec
->tx_coalesce_usecs
* 1000U, scale
);
1860 w
|= FIELD_PREP(RTL_COALESCE_TX_USECS
, units
);
1861 units
= DIV_ROUND_UP(ec
->rx_coalesce_usecs
* 1000U, scale
);
1862 w
|= FIELD_PREP(RTL_COALESCE_RX_USECS
, units
);
1864 RTL_W16(tp
, IntrMitigate
, w
);
1866 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */
1867 if (rtl_is_8168evl_up(tp
)) {
1868 if (!rx_fr
&& !tx_fr
)
1869 /* disable packet counter */
1870 tp
->cp_cmd
|= PktCntrDisable
;
1872 tp
->cp_cmd
&= ~PktCntrDisable
;
1875 tp
->cp_cmd
= (tp
->cp_cmd
& ~INTT_MASK
) | cp01
;
1876 RTL_W16(tp
, CPlusCmd
, tp
->cp_cmd
);
1882 static int rtl8169_get_eee(struct net_device
*dev
, struct ethtool_eee
*data
)
1884 struct rtl8169_private
*tp
= netdev_priv(dev
);
1886 if (!rtl_supports_eee(tp
))
1889 return phy_ethtool_get_eee(tp
->phydev
, data
);
1892 static int rtl8169_set_eee(struct net_device
*dev
, struct ethtool_eee
*data
)
1894 struct rtl8169_private
*tp
= netdev_priv(dev
);
1897 if (!rtl_supports_eee(tp
))
1900 ret
= phy_ethtool_set_eee(tp
->phydev
, data
);
1903 tp
->eee_adv
= phy_read_mmd(dev
->phydev
, MDIO_MMD_AN
,
1908 static void rtl8169_get_ringparam(struct net_device
*dev
,
1909 struct ethtool_ringparam
*data
)
1911 data
->rx_max_pending
= NUM_RX_DESC
;
1912 data
->rx_pending
= NUM_RX_DESC
;
1913 data
->tx_max_pending
= NUM_TX_DESC
;
1914 data
->tx_pending
= NUM_TX_DESC
;
1917 static void rtl8169_get_pauseparam(struct net_device
*dev
,
1918 struct ethtool_pauseparam
*data
)
1920 struct rtl8169_private
*tp
= netdev_priv(dev
);
1921 bool tx_pause
, rx_pause
;
1923 phy_get_pause(tp
->phydev
, &tx_pause
, &rx_pause
);
1925 data
->autoneg
= tp
->phydev
->autoneg
;
1926 data
->tx_pause
= tx_pause
? 1 : 0;
1927 data
->rx_pause
= rx_pause
? 1 : 0;
1930 static int rtl8169_set_pauseparam(struct net_device
*dev
,
1931 struct ethtool_pauseparam
*data
)
1933 struct rtl8169_private
*tp
= netdev_priv(dev
);
1935 if (dev
->mtu
> ETH_DATA_LEN
)
1938 phy_set_asym_pause(tp
->phydev
, data
->rx_pause
, data
->tx_pause
);
1943 static const struct ethtool_ops rtl8169_ethtool_ops
= {
1944 .supported_coalesce_params
= ETHTOOL_COALESCE_USECS
|
1945 ETHTOOL_COALESCE_MAX_FRAMES
,
1946 .get_drvinfo
= rtl8169_get_drvinfo
,
1947 .get_regs_len
= rtl8169_get_regs_len
,
1948 .get_link
= ethtool_op_get_link
,
1949 .get_coalesce
= rtl_get_coalesce
,
1950 .set_coalesce
= rtl_set_coalesce
,
1951 .get_regs
= rtl8169_get_regs
,
1952 .get_wol
= rtl8169_get_wol
,
1953 .set_wol
= rtl8169_set_wol
,
1954 .get_strings
= rtl8169_get_strings
,
1955 .get_sset_count
= rtl8169_get_sset_count
,
1956 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
1957 .get_ts_info
= ethtool_op_get_ts_info
,
1958 .nway_reset
= phy_ethtool_nway_reset
,
1959 .get_eee
= rtl8169_get_eee
,
1960 .set_eee
= rtl8169_set_eee
,
1961 .get_link_ksettings
= phy_ethtool_get_link_ksettings
,
1962 .set_link_ksettings
= phy_ethtool_set_link_ksettings
,
1963 .get_ringparam
= rtl8169_get_ringparam
,
1964 .get_pauseparam
= rtl8169_get_pauseparam
,
1965 .set_pauseparam
= rtl8169_set_pauseparam
,
1968 static void rtl_enable_eee(struct rtl8169_private
*tp
)
1970 struct phy_device
*phydev
= tp
->phydev
;
1973 /* respect EEE advertisement the user may have set */
1974 if (tp
->eee_adv
>= 0)
1977 adv
= phy_read_mmd(phydev
, MDIO_MMD_PCS
, MDIO_PCS_EEE_ABLE
);
1980 phy_write_mmd(phydev
, MDIO_MMD_AN
, MDIO_AN_EEE_ADV
, adv
);
1983 static enum mac_version
rtl8169_get_mac_version(u16 xid
, bool gmii
)
1986 * The driver currently handles the 8168Bf and the 8168Be identically
1987 * but they can be identified more specifically through the test below
1990 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1992 * Same thing for the 8101Eb and the 8101Ec:
1994 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1996 static const struct rtl_mac_info
{
1999 enum mac_version ver
;
2002 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63
},
2005 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60
},
2006 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61
},
2009 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53
},
2010 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52
},
2012 /* 8168EP family. */
2013 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51
},
2014 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50
},
2015 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49
},
2018 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46
},
2019 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45
},
2022 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44
},
2023 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42
},
2024 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41
},
2025 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40
},
2028 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38
},
2029 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36
},
2030 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35
},
2033 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34
},
2034 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32
},
2035 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33
},
2038 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25
},
2039 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26
},
2041 /* 8168DP family. */
2042 /* It seems this early RTL8168dp version never made it to
2043 * the wild. Let's see whether somebody complains, if not
2044 * we'll remove support for this chip version completely.
2045 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2047 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28
},
2048 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31
},
2051 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23
},
2052 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18
},
2053 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24
},
2054 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19
},
2055 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20
},
2056 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21
},
2057 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22
},
2060 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12
},
2061 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17
},
2062 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11
},
2065 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39
},
2066 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37
},
2067 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29
},
2068 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30
},
2069 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08
},
2070 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08
},
2071 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07
},
2072 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07
},
2073 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13
},
2074 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14
},
2075 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10
},
2076 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16
},
2077 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09
},
2078 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09
},
2079 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16
},
2080 /* FIXME: where did these entries come from ? -- FR
2081 * Not even r8101 vendor driver knows these id's,
2082 * so let's disable detection for now. -- HK
2083 * { 0xfc8, 0x388, RTL_GIGA_MAC_VER_13 },
2084 * { 0xfc8, 0x308, RTL_GIGA_MAC_VER_13 },
2088 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06
},
2089 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05
},
2090 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04
},
2091 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03
},
2092 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02
},
2095 { 0x000, 0x000, RTL_GIGA_MAC_NONE
}
2097 const struct rtl_mac_info
*p
= mac_info
;
2098 enum mac_version ver
;
2100 while ((xid
& p
->mask
) != p
->val
)
2104 if (ver
!= RTL_GIGA_MAC_NONE
&& !gmii
) {
2105 if (ver
== RTL_GIGA_MAC_VER_42
)
2106 ver
= RTL_GIGA_MAC_VER_43
;
2107 else if (ver
== RTL_GIGA_MAC_VER_45
)
2108 ver
= RTL_GIGA_MAC_VER_47
;
2109 else if (ver
== RTL_GIGA_MAC_VER_46
)
2110 ver
= RTL_GIGA_MAC_VER_48
;
2116 static void rtl_release_firmware(struct rtl8169_private
*tp
)
2119 rtl_fw_release_firmware(tp
->rtl_fw
);
2125 void r8169_apply_firmware(struct rtl8169_private
*tp
)
2129 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2131 rtl_fw_write_firmware(tp
, tp
->rtl_fw
);
2132 /* At least one firmware doesn't reset tp->ocp_base. */
2133 tp
->ocp_base
= OCP_STD_PHY_BASE
;
2135 /* PHY soft reset may still be in progress */
2136 phy_read_poll_timeout(tp
->phydev
, MII_BMCR
, val
,
2137 !(val
& BMCR_RESET
),
2138 50000, 600000, true);
2142 static void rtl8168_config_eee_mac(struct rtl8169_private
*tp
)
2144 /* Adjust EEE LED frequency */
2145 if (tp
->mac_version
!= RTL_GIGA_MAC_VER_38
)
2146 RTL_W8(tp
, EEE_LED
, RTL_R8(tp
, EEE_LED
) & ~0x07);
2148 rtl_eri_set_bits(tp
, 0x1b0, 0x0003);
2151 static void rtl8125a_config_eee_mac(struct rtl8169_private
*tp
)
2153 r8168_mac_ocp_modify(tp
, 0xe040, 0, BIT(1) | BIT(0));
2154 r8168_mac_ocp_modify(tp
, 0xeb62, 0, BIT(2) | BIT(1));
2157 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private
*tp
)
2159 RTL_W16(tp
, EEE_TXIDLE_TIMER_8125
, tp
->dev
->mtu
+ ETH_HLEN
+ 0x20);
2162 static void rtl8125b_config_eee_mac(struct rtl8169_private
*tp
)
2164 rtl8125_set_eee_txidle_timer(tp
);
2165 r8168_mac_ocp_modify(tp
, 0xe040, 0, BIT(1) | BIT(0));
2168 static void rtl_rar_exgmac_set(struct rtl8169_private
*tp
, const u8
*addr
)
2170 rtl_eri_write(tp
, 0xe0, ERIAR_MASK_1111
, get_unaligned_le32(addr
));
2171 rtl_eri_write(tp
, 0xe4, ERIAR_MASK_1111
, get_unaligned_le16(addr
+ 4));
2172 rtl_eri_write(tp
, 0xf0, ERIAR_MASK_1111
, get_unaligned_le16(addr
) << 16);
2173 rtl_eri_write(tp
, 0xf4, ERIAR_MASK_1111
, get_unaligned_le32(addr
+ 2));
2176 u16
rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private
*tp
)
2178 u16 data1
, data2
, ioffset
;
2180 r8168_mac_ocp_write(tp
, 0xdd02, 0x807d);
2181 data1
= r8168_mac_ocp_read(tp
, 0xdd02);
2182 data2
= r8168_mac_ocp_read(tp
, 0xdd00);
2184 ioffset
= (data2
>> 1) & 0x7ff8;
2185 ioffset
|= data2
& 0x0007;
2192 static void rtl_schedule_task(struct rtl8169_private
*tp
, enum rtl_flag flag
)
2194 set_bit(flag
, tp
->wk
.flags
);
2195 schedule_work(&tp
->wk
.work
);
2198 static void rtl8169_init_phy(struct rtl8169_private
*tp
)
2200 r8169_hw_phy_config(tp
, tp
->phydev
, tp
->mac_version
);
2202 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
2203 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
2204 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
2205 /* set undocumented MAC Reg C+CR Offset 0x82h */
2206 RTL_W8(tp
, 0x82, 0x01);
2209 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
&&
2210 tp
->pci_dev
->subsystem_vendor
== PCI_VENDOR_ID_GIGABYTE
&&
2211 tp
->pci_dev
->subsystem_device
== 0xe000)
2212 phy_write_paged(tp
->phydev
, 0x0001, 0x10, 0xf01b);
2214 /* We may have called phy_speed_down before */
2215 phy_speed_up(tp
->phydev
);
2217 if (rtl_supports_eee(tp
))
2220 genphy_soft_reset(tp
->phydev
);
2223 static void rtl_rar_set(struct rtl8169_private
*tp
, const u8
*addr
)
2225 rtl_unlock_config_regs(tp
);
2227 RTL_W32(tp
, MAC4
, get_unaligned_le16(addr
+ 4));
2230 RTL_W32(tp
, MAC0
, get_unaligned_le32(addr
));
2233 if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
)
2234 rtl_rar_exgmac_set(tp
, addr
);
2236 rtl_lock_config_regs(tp
);
2239 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
2241 struct rtl8169_private
*tp
= netdev_priv(dev
);
2244 ret
= eth_mac_addr(dev
, p
);
2248 rtl_rar_set(tp
, dev
->dev_addr
);
2253 static void rtl_wol_enable_rx(struct rtl8169_private
*tp
)
2255 if (tp
->mac_version
>= RTL_GIGA_MAC_VER_25
)
2256 RTL_W32(tp
, RxConfig
, RTL_R32(tp
, RxConfig
) |
2257 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
);
2260 static void rtl_prepare_power_down(struct rtl8169_private
*tp
)
2262 if (tp
->dash_type
!= RTL_DASH_NONE
)
2265 if (tp
->mac_version
== RTL_GIGA_MAC_VER_32
||
2266 tp
->mac_version
== RTL_GIGA_MAC_VER_33
)
2267 rtl_ephy_write(tp
, 0x19, 0xff64);
2269 if (device_may_wakeup(tp_to_dev(tp
))) {
2270 phy_speed_down(tp
->phydev
, false);
2271 rtl_wol_enable_rx(tp
);
2275 static void rtl_init_rxcfg(struct rtl8169_private
*tp
)
2277 switch (tp
->mac_version
) {
2278 case RTL_GIGA_MAC_VER_02
... RTL_GIGA_MAC_VER_06
:
2279 case RTL_GIGA_MAC_VER_10
... RTL_GIGA_MAC_VER_17
:
2280 RTL_W32(tp
, RxConfig
, RX_FIFO_THRESH
| RX_DMA_BURST
);
2282 case RTL_GIGA_MAC_VER_18
... RTL_GIGA_MAC_VER_24
:
2283 case RTL_GIGA_MAC_VER_34
... RTL_GIGA_MAC_VER_36
:
2284 case RTL_GIGA_MAC_VER_38
:
2285 RTL_W32(tp
, RxConfig
, RX128_INT_EN
| RX_MULTI_EN
| RX_DMA_BURST
);
2287 case RTL_GIGA_MAC_VER_40
... RTL_GIGA_MAC_VER_53
:
2288 RTL_W32(tp
, RxConfig
, RX128_INT_EN
| RX_MULTI_EN
| RX_DMA_BURST
| RX_EARLY_OFF
);
2290 case RTL_GIGA_MAC_VER_60
... RTL_GIGA_MAC_VER_63
:
2291 RTL_W32(tp
, RxConfig
, RX_FETCH_DFLT_8125
| RX_DMA_BURST
);
2294 RTL_W32(tp
, RxConfig
, RX128_INT_EN
| RX_DMA_BURST
);
2299 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
2301 tp
->dirty_tx
= tp
->cur_tx
= tp
->cur_rx
= 0;
2304 static void r8168c_hw_jumbo_enable(struct rtl8169_private
*tp
)
2306 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) | Jumbo_En0
);
2307 RTL_W8(tp
, Config4
, RTL_R8(tp
, Config4
) | Jumbo_En1
);
2310 static void r8168c_hw_jumbo_disable(struct rtl8169_private
*tp
)
2312 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) & ~Jumbo_En0
);
2313 RTL_W8(tp
, Config4
, RTL_R8(tp
, Config4
) & ~Jumbo_En1
);
2316 static void r8168dp_hw_jumbo_enable(struct rtl8169_private
*tp
)
2318 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) | Jumbo_En0
);
2321 static void r8168dp_hw_jumbo_disable(struct rtl8169_private
*tp
)
2323 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) & ~Jumbo_En0
);
2326 static void r8168e_hw_jumbo_enable(struct rtl8169_private
*tp
)
2328 RTL_W8(tp
, MaxTxPacketSize
, 0x24);
2329 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) | Jumbo_En0
);
2330 RTL_W8(tp
, Config4
, RTL_R8(tp
, Config4
) | 0x01);
2333 static void r8168e_hw_jumbo_disable(struct rtl8169_private
*tp
)
2335 RTL_W8(tp
, MaxTxPacketSize
, 0x3f);
2336 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) & ~Jumbo_En0
);
2337 RTL_W8(tp
, Config4
, RTL_R8(tp
, Config4
) & ~0x01);
2340 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private
*tp
)
2342 RTL_W8(tp
, Config4
, RTL_R8(tp
, Config4
) | (1 << 0));
2345 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private
*tp
)
2347 RTL_W8(tp
, Config4
, RTL_R8(tp
, Config4
) & ~(1 << 0));
2350 static void rtl_jumbo_config(struct rtl8169_private
*tp
)
2352 bool jumbo
= tp
->dev
->mtu
> ETH_DATA_LEN
;
2355 rtl_unlock_config_regs(tp
);
2356 switch (tp
->mac_version
) {
2357 case RTL_GIGA_MAC_VER_12
:
2358 case RTL_GIGA_MAC_VER_17
:
2361 r8168b_1_hw_jumbo_enable(tp
);
2363 r8168b_1_hw_jumbo_disable(tp
);
2366 case RTL_GIGA_MAC_VER_18
... RTL_GIGA_MAC_VER_26
:
2369 r8168c_hw_jumbo_enable(tp
);
2371 r8168c_hw_jumbo_disable(tp
);
2374 case RTL_GIGA_MAC_VER_27
... RTL_GIGA_MAC_VER_28
:
2376 r8168dp_hw_jumbo_enable(tp
);
2378 r8168dp_hw_jumbo_disable(tp
);
2380 case RTL_GIGA_MAC_VER_31
... RTL_GIGA_MAC_VER_33
:
2382 r8168e_hw_jumbo_enable(tp
);
2384 r8168e_hw_jumbo_disable(tp
);
2389 rtl_lock_config_regs(tp
);
2391 if (pci_is_pcie(tp
->pci_dev
) && tp
->supports_gmii
)
2392 pcie_set_readrq(tp
->pci_dev
, readrq
);
2394 /* Chip doesn't support pause in jumbo mode */
2396 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT
,
2397 tp
->phydev
->advertising
);
2398 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT
,
2399 tp
->phydev
->advertising
);
2400 phy_start_aneg(tp
->phydev
);
2404 DECLARE_RTL_COND(rtl_chipcmd_cond
)
2406 return RTL_R8(tp
, ChipCmd
) & CmdReset
;
2409 static void rtl_hw_reset(struct rtl8169_private
*tp
)
2411 RTL_W8(tp
, ChipCmd
, CmdReset
);
2413 rtl_loop_wait_low(tp
, &rtl_chipcmd_cond
, 100, 100);
2416 static void rtl_request_firmware(struct rtl8169_private
*tp
)
2418 struct rtl_fw
*rtl_fw
;
2420 /* firmware loaded already or no firmware available */
2421 if (tp
->rtl_fw
|| !tp
->fw_name
)
2424 rtl_fw
= kzalloc(sizeof(*rtl_fw
), GFP_KERNEL
);
2428 rtl_fw
->phy_write
= rtl_writephy
;
2429 rtl_fw
->phy_read
= rtl_readphy
;
2430 rtl_fw
->mac_mcu_write
= mac_mcu_write
;
2431 rtl_fw
->mac_mcu_read
= mac_mcu_read
;
2432 rtl_fw
->fw_name
= tp
->fw_name
;
2433 rtl_fw
->dev
= tp_to_dev(tp
);
2435 if (rtl_fw_request_firmware(rtl_fw
))
2438 tp
->rtl_fw
= rtl_fw
;
2441 static void rtl_rx_close(struct rtl8169_private
*tp
)
2443 RTL_W32(tp
, RxConfig
, RTL_R32(tp
, RxConfig
) & ~RX_CONFIG_ACCEPT_MASK
);
2446 DECLARE_RTL_COND(rtl_npq_cond
)
2448 return RTL_R8(tp
, TxPoll
) & NPQ
;
2451 DECLARE_RTL_COND(rtl_txcfg_empty_cond
)
2453 return RTL_R32(tp
, TxConfig
) & TXCFG_EMPTY
;
2456 DECLARE_RTL_COND(rtl_rxtx_empty_cond
)
2458 return (RTL_R8(tp
, MCU
) & RXTX_EMPTY
) == RXTX_EMPTY
;
2461 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2
)
2463 /* IntrMitigate has new functionality on RTL8125 */
2464 return (RTL_R16(tp
, IntrMitigate
) & 0x0103) == 0x0103;
2467 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private
*tp
)
2469 switch (tp
->mac_version
) {
2470 case RTL_GIGA_MAC_VER_40
... RTL_GIGA_MAC_VER_53
:
2471 rtl_loop_wait_high(tp
, &rtl_txcfg_empty_cond
, 100, 42);
2472 rtl_loop_wait_high(tp
, &rtl_rxtx_empty_cond
, 100, 42);
2474 case RTL_GIGA_MAC_VER_60
... RTL_GIGA_MAC_VER_61
:
2475 rtl_loop_wait_high(tp
, &rtl_rxtx_empty_cond
, 100, 42);
2477 case RTL_GIGA_MAC_VER_63
:
2478 RTL_W8(tp
, ChipCmd
, RTL_R8(tp
, ChipCmd
) | StopReq
);
2479 rtl_loop_wait_high(tp
, &rtl_rxtx_empty_cond
, 100, 42);
2480 rtl_loop_wait_high(tp
, &rtl_rxtx_empty_cond_2
, 100, 42);
2487 static void rtl_enable_rxdvgate(struct rtl8169_private
*tp
)
2489 RTL_W32(tp
, MISC
, RTL_R32(tp
, MISC
) | RXDV_GATED_EN
);
2491 rtl_wait_txrx_fifo_empty(tp
);
2494 static void rtl_set_tx_config_registers(struct rtl8169_private
*tp
)
2496 u32 val
= TX_DMA_BURST
<< TxDMAShift
|
2497 InterFrameGap
<< TxInterFrameGapShift
;
2499 if (rtl_is_8168evl_up(tp
))
2500 val
|= TXCFG_AUTO_FIFO
;
2502 RTL_W32(tp
, TxConfig
, val
);
2505 static void rtl_set_rx_max_size(struct rtl8169_private
*tp
)
2507 /* Low hurts. Let's disable the filtering. */
2508 RTL_W16(tp
, RxMaxSize
, R8169_RX_BUF_SIZE
+ 1);
2511 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
)
2514 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2515 * register to be written before TxDescAddrLow to work.
2516 * Switching from MMIO to I/O access fixes the issue as well.
2518 RTL_W32(tp
, TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
2519 RTL_W32(tp
, TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_BIT_MASK(32));
2520 RTL_W32(tp
, RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
2521 RTL_W32(tp
, RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_BIT_MASK(32));
2524 static void rtl8169_set_magic_reg(struct rtl8169_private
*tp
)
2528 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
2530 else if (tp
->mac_version
== RTL_GIGA_MAC_VER_06
)
2535 if (RTL_R8(tp
, Config2
) & PCI_Clock_66MHz
)
2538 RTL_W32(tp
, 0x7c, val
);
2541 static void rtl_set_rx_mode(struct net_device
*dev
)
2543 u32 rx_mode
= AcceptBroadcast
| AcceptMyPhys
| AcceptMulticast
;
2544 /* Multicast hash filter */
2545 u32 mc_filter
[2] = { 0xffffffff, 0xffffffff };
2546 struct rtl8169_private
*tp
= netdev_priv(dev
);
2549 if (dev
->flags
& IFF_PROMISC
) {
2550 rx_mode
|= AcceptAllPhys
;
2551 } else if (netdev_mc_count(dev
) > MC_FILTER_LIMIT
||
2552 dev
->flags
& IFF_ALLMULTI
||
2553 tp
->mac_version
== RTL_GIGA_MAC_VER_35
) {
2554 /* accept all multicasts */
2555 } else if (netdev_mc_empty(dev
)) {
2556 rx_mode
&= ~AcceptMulticast
;
2558 struct netdev_hw_addr
*ha
;
2560 mc_filter
[1] = mc_filter
[0] = 0;
2561 netdev_for_each_mc_addr(ha
, dev
) {
2562 u32 bit_nr
= eth_hw_addr_crc(ha
) >> 26;
2563 mc_filter
[bit_nr
>> 5] |= BIT(bit_nr
& 31);
2566 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
2568 mc_filter
[0] = swab32(mc_filter
[1]);
2569 mc_filter
[1] = swab32(tmp
);
2573 RTL_W32(tp
, MAR0
+ 4, mc_filter
[1]);
2574 RTL_W32(tp
, MAR0
+ 0, mc_filter
[0]);
2576 tmp
= RTL_R32(tp
, RxConfig
);
2577 RTL_W32(tp
, RxConfig
, (tmp
& ~RX_CONFIG_ACCEPT_OK_MASK
) | rx_mode
);
2580 DECLARE_RTL_COND(rtl_csiar_cond
)
2582 return RTL_R32(tp
, CSIAR
) & CSIAR_FLAG
;
2585 static void rtl_csi_write(struct rtl8169_private
*tp
, int addr
, int value
)
2587 u32 func
= PCI_FUNC(tp
->pci_dev
->devfn
);
2589 RTL_W32(tp
, CSIDR
, value
);
2590 RTL_W32(tp
, CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
2591 CSIAR_BYTE_ENABLE
| func
<< 16);
2593 rtl_loop_wait_low(tp
, &rtl_csiar_cond
, 10, 100);
2596 static u32
rtl_csi_read(struct rtl8169_private
*tp
, int addr
)
2598 u32 func
= PCI_FUNC(tp
->pci_dev
->devfn
);
2600 RTL_W32(tp
, CSIAR
, (addr
& CSIAR_ADDR_MASK
) | func
<< 16 |
2603 return rtl_loop_wait_high(tp
, &rtl_csiar_cond
, 10, 100) ?
2604 RTL_R32(tp
, CSIDR
) : ~0;
2607 static void rtl_set_aspm_entry_latency(struct rtl8169_private
*tp
, u8 val
)
2609 struct pci_dev
*pdev
= tp
->pci_dev
;
2612 /* According to Realtek the value at config space address 0x070f
2613 * controls the L0s/L1 entrance latency. We try standard ECAM access
2614 * first and if it fails fall back to CSI.
2615 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo)
2616 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us
2618 if (pdev
->cfg_size
> 0x070f &&
2619 pci_write_config_byte(pdev
, 0x070f, val
) == PCIBIOS_SUCCESSFUL
)
2622 netdev_notice_once(tp
->dev
,
2623 "No native access to PCI extended config space, falling back to CSI\n");
2624 csi
= rtl_csi_read(tp
, 0x070c) & 0x00ffffff;
2625 rtl_csi_write(tp
, 0x070c, csi
| val
<< 24);
2628 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private
*tp
)
2630 /* L0 7us, L1 16us */
2631 rtl_set_aspm_entry_latency(tp
, 0x27);
2635 unsigned int offset
;
2640 static void __rtl_ephy_init(struct rtl8169_private
*tp
,
2641 const struct ephy_info
*e
, int len
)
2646 w
= (rtl_ephy_read(tp
, e
->offset
) & ~e
->mask
) | e
->bits
;
2647 rtl_ephy_write(tp
, e
->offset
, w
);
2652 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2654 static void rtl_disable_clock_request(struct rtl8169_private
*tp
)
2656 pcie_capability_clear_word(tp
->pci_dev
, PCI_EXP_LNKCTL
,
2657 PCI_EXP_LNKCTL_CLKREQ_EN
);
2660 static void rtl_enable_clock_request(struct rtl8169_private
*tp
)
2662 pcie_capability_set_word(tp
->pci_dev
, PCI_EXP_LNKCTL
,
2663 PCI_EXP_LNKCTL_CLKREQ_EN
);
2666 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private
*tp
)
2668 /* work around an issue when PCI reset occurs during L2/L3 state */
2669 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) & ~Rdy_to_L23
);
2672 static void rtl_enable_exit_l1(struct rtl8169_private
*tp
)
2674 /* Bits control which events trigger ASPM L1 exit:
2677 * Bit 10: txdma_poll
2682 switch (tp
->mac_version
) {
2683 case RTL_GIGA_MAC_VER_34
... RTL_GIGA_MAC_VER_36
:
2684 rtl_eri_set_bits(tp
, 0xd4, 0x1f00);
2686 case RTL_GIGA_MAC_VER_37
... RTL_GIGA_MAC_VER_38
:
2687 rtl_eri_set_bits(tp
, 0xd4, 0x0c00);
2689 case RTL_GIGA_MAC_VER_40
... RTL_GIGA_MAC_VER_53
:
2690 rtl_eri_set_bits(tp
, 0xd4, 0x1f80);
2692 case RTL_GIGA_MAC_VER_60
... RTL_GIGA_MAC_VER_63
:
2693 r8168_mac_ocp_modify(tp
, 0xc0ac, 0, 0x1f80);
2700 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private
*tp
, bool enable
)
2702 /* Don't enable ASPM in the chip if OS can't control ASPM */
2703 if (enable
&& tp
->aspm_manageable
) {
2704 RTL_W8(tp
, Config5
, RTL_R8(tp
, Config5
) | ASPM_en
);
2705 RTL_W8(tp
, Config2
, RTL_R8(tp
, Config2
) | ClkReqEn
);
2707 RTL_W8(tp
, Config2
, RTL_R8(tp
, Config2
) & ~ClkReqEn
);
2708 RTL_W8(tp
, Config5
, RTL_R8(tp
, Config5
) & ~ASPM_en
);
2714 static void rtl_set_fifo_size(struct rtl8169_private
*tp
, u16 rx_stat
,
2715 u16 tx_stat
, u16 rx_dyn
, u16 tx_dyn
)
2717 /* Usage of dynamic vs. static FIFO is controlled by bit
2718 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
2720 rtl_eri_write(tp
, 0xc8, ERIAR_MASK_1111
, (rx_stat
<< 16) | rx_dyn
);
2721 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_1111
, (tx_stat
<< 16) | tx_dyn
);
2724 static void rtl8168g_set_pause_thresholds(struct rtl8169_private
*tp
,
2727 /* FIFO thresholds for pause flow control */
2728 rtl_eri_write(tp
, 0xcc, ERIAR_MASK_0001
, low
);
2729 rtl_eri_write(tp
, 0xd0, ERIAR_MASK_0001
, high
);
2732 static void rtl_hw_start_8168b(struct rtl8169_private
*tp
)
2734 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) & ~Beacon_en
);
2737 static void __rtl_hw_start_8168cp(struct rtl8169_private
*tp
)
2739 RTL_W8(tp
, Config1
, RTL_R8(tp
, Config1
) | Speed_down
);
2741 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) & ~Beacon_en
);
2743 rtl_disable_clock_request(tp
);
2746 static void rtl_hw_start_8168cp_1(struct rtl8169_private
*tp
)
2748 static const struct ephy_info e_info_8168cp
[] = {
2749 { 0x01, 0, 0x0001 },
2750 { 0x02, 0x0800, 0x1000 },
2751 { 0x03, 0, 0x0042 },
2752 { 0x06, 0x0080, 0x0000 },
2756 rtl_set_def_aspm_entry_latency(tp
);
2758 rtl_ephy_init(tp
, e_info_8168cp
);
2760 __rtl_hw_start_8168cp(tp
);
2763 static void rtl_hw_start_8168cp_2(struct rtl8169_private
*tp
)
2765 rtl_set_def_aspm_entry_latency(tp
);
2767 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) & ~Beacon_en
);
2770 static void rtl_hw_start_8168cp_3(struct rtl8169_private
*tp
)
2772 rtl_set_def_aspm_entry_latency(tp
);
2774 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) & ~Beacon_en
);
2777 RTL_W8(tp
, DBG_REG
, 0x20);
2780 static void rtl_hw_start_8168c_1(struct rtl8169_private
*tp
)
2782 static const struct ephy_info e_info_8168c_1
[] = {
2783 { 0x02, 0x0800, 0x1000 },
2784 { 0x03, 0, 0x0002 },
2785 { 0x06, 0x0080, 0x0000 }
2788 rtl_set_def_aspm_entry_latency(tp
);
2790 RTL_W8(tp
, DBG_REG
, 0x06 | FIX_NAK_1
| FIX_NAK_2
);
2792 rtl_ephy_init(tp
, e_info_8168c_1
);
2794 __rtl_hw_start_8168cp(tp
);
2797 static void rtl_hw_start_8168c_2(struct rtl8169_private
*tp
)
2799 static const struct ephy_info e_info_8168c_2
[] = {
2800 { 0x01, 0, 0x0001 },
2801 { 0x03, 0x0400, 0x0020 }
2804 rtl_set_def_aspm_entry_latency(tp
);
2806 rtl_ephy_init(tp
, e_info_8168c_2
);
2808 __rtl_hw_start_8168cp(tp
);
2811 static void rtl_hw_start_8168c_4(struct rtl8169_private
*tp
)
2813 rtl_set_def_aspm_entry_latency(tp
);
2815 __rtl_hw_start_8168cp(tp
);
2818 static void rtl_hw_start_8168d(struct rtl8169_private
*tp
)
2820 rtl_set_def_aspm_entry_latency(tp
);
2822 rtl_disable_clock_request(tp
);
2825 static void rtl_hw_start_8168d_4(struct rtl8169_private
*tp
)
2827 static const struct ephy_info e_info_8168d_4
[] = {
2828 { 0x0b, 0x0000, 0x0048 },
2829 { 0x19, 0x0020, 0x0050 },
2830 { 0x0c, 0x0100, 0x0020 },
2831 { 0x10, 0x0004, 0x0000 },
2834 rtl_set_def_aspm_entry_latency(tp
);
2836 rtl_ephy_init(tp
, e_info_8168d_4
);
2838 rtl_enable_clock_request(tp
);
2841 static void rtl_hw_start_8168e_1(struct rtl8169_private
*tp
)
2843 static const struct ephy_info e_info_8168e_1
[] = {
2844 { 0x00, 0x0200, 0x0100 },
2845 { 0x00, 0x0000, 0x0004 },
2846 { 0x06, 0x0002, 0x0001 },
2847 { 0x06, 0x0000, 0x0030 },
2848 { 0x07, 0x0000, 0x2000 },
2849 { 0x00, 0x0000, 0x0020 },
2850 { 0x03, 0x5800, 0x2000 },
2851 { 0x03, 0x0000, 0x0001 },
2852 { 0x01, 0x0800, 0x1000 },
2853 { 0x07, 0x0000, 0x4000 },
2854 { 0x1e, 0x0000, 0x2000 },
2855 { 0x19, 0xffff, 0xfe6c },
2856 { 0x0a, 0x0000, 0x0040 }
2859 rtl_set_def_aspm_entry_latency(tp
);
2861 rtl_ephy_init(tp
, e_info_8168e_1
);
2863 rtl_disable_clock_request(tp
);
2865 /* Reset tx FIFO pointer */
2866 RTL_W32(tp
, MISC
, RTL_R32(tp
, MISC
) | TXPLA_RST
);
2867 RTL_W32(tp
, MISC
, RTL_R32(tp
, MISC
) & ~TXPLA_RST
);
2869 RTL_W8(tp
, Config5
, RTL_R8(tp
, Config5
) & ~Spi_en
);
2872 static void rtl_hw_start_8168e_2(struct rtl8169_private
*tp
)
2874 static const struct ephy_info e_info_8168e_2
[] = {
2875 { 0x09, 0x0000, 0x0080 },
2876 { 0x19, 0x0000, 0x0224 },
2877 { 0x00, 0x0000, 0x0004 },
2878 { 0x0c, 0x3df0, 0x0200 },
2881 rtl_set_def_aspm_entry_latency(tp
);
2883 rtl_ephy_init(tp
, e_info_8168e_2
);
2885 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000);
2886 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_1111
, 0x0000);
2887 rtl_set_fifo_size(tp
, 0x10, 0x10, 0x02, 0x06);
2888 rtl_eri_set_bits(tp
, 0x1d0, BIT(1));
2889 rtl_reset_packet_filter(tp
);
2890 rtl_eri_set_bits(tp
, 0x1b0, BIT(4));
2891 rtl_eri_write(tp
, 0xcc, ERIAR_MASK_1111
, 0x00000050);
2892 rtl_eri_write(tp
, 0xd0, ERIAR_MASK_1111
, 0x07ff0060);
2894 rtl_disable_clock_request(tp
);
2896 RTL_W8(tp
, MCU
, RTL_R8(tp
, MCU
) & ~NOW_IS_OOB
);
2898 rtl8168_config_eee_mac(tp
);
2900 RTL_W8(tp
, DLLPR
, RTL_R8(tp
, DLLPR
) | PFM_EN
);
2901 RTL_W32(tp
, MISC
, RTL_R32(tp
, MISC
) | PWM_EN
);
2902 RTL_W8(tp
, Config5
, RTL_R8(tp
, Config5
) & ~Spi_en
);
2904 rtl_hw_aspm_clkreq_enable(tp
, true);
2907 static void rtl_hw_start_8168f(struct rtl8169_private
*tp
)
2909 rtl_set_def_aspm_entry_latency(tp
);
2911 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000);
2912 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_1111
, 0x0000);
2913 rtl_set_fifo_size(tp
, 0x10, 0x10, 0x02, 0x06);
2914 rtl_reset_packet_filter(tp
);
2915 rtl_eri_set_bits(tp
, 0x1b0, BIT(4));
2916 rtl_eri_set_bits(tp
, 0x1d0, BIT(4) | BIT(1));
2917 rtl_eri_write(tp
, 0xcc, ERIAR_MASK_1111
, 0x00000050);
2918 rtl_eri_write(tp
, 0xd0, ERIAR_MASK_1111
, 0x00000060);
2920 rtl_disable_clock_request(tp
);
2922 RTL_W8(tp
, MCU
, RTL_R8(tp
, MCU
) & ~NOW_IS_OOB
);
2923 RTL_W8(tp
, DLLPR
, RTL_R8(tp
, DLLPR
) | PFM_EN
);
2924 RTL_W32(tp
, MISC
, RTL_R32(tp
, MISC
) | PWM_EN
);
2925 RTL_W8(tp
, Config5
, RTL_R8(tp
, Config5
) & ~Spi_en
);
2927 rtl8168_config_eee_mac(tp
);
2930 static void rtl_hw_start_8168f_1(struct rtl8169_private
*tp
)
2932 static const struct ephy_info e_info_8168f_1
[] = {
2933 { 0x06, 0x00c0, 0x0020 },
2934 { 0x08, 0x0001, 0x0002 },
2935 { 0x09, 0x0000, 0x0080 },
2936 { 0x19, 0x0000, 0x0224 },
2937 { 0x00, 0x0000, 0x0008 },
2938 { 0x0c, 0x3df0, 0x0200 },
2941 rtl_hw_start_8168f(tp
);
2943 rtl_ephy_init(tp
, e_info_8168f_1
);
2946 static void rtl_hw_start_8411(struct rtl8169_private
*tp
)
2948 static const struct ephy_info e_info_8168f_1
[] = {
2949 { 0x06, 0x00c0, 0x0020 },
2950 { 0x0f, 0xffff, 0x5200 },
2951 { 0x19, 0x0000, 0x0224 },
2952 { 0x00, 0x0000, 0x0008 },
2953 { 0x0c, 0x3df0, 0x0200 },
2956 rtl_hw_start_8168f(tp
);
2957 rtl_pcie_state_l2l3_disable(tp
);
2959 rtl_ephy_init(tp
, e_info_8168f_1
);
2962 static void rtl_hw_start_8168g(struct rtl8169_private
*tp
)
2964 rtl_set_fifo_size(tp
, 0x08, 0x10, 0x02, 0x06);
2965 rtl8168g_set_pause_thresholds(tp
, 0x38, 0x48);
2967 rtl_set_def_aspm_entry_latency(tp
);
2969 rtl_reset_packet_filter(tp
);
2970 rtl_eri_write(tp
, 0x2f8, ERIAR_MASK_0011
, 0x1d8f);
2972 RTL_W32(tp
, MISC
, RTL_R32(tp
, MISC
) & ~RXDV_GATED_EN
);
2974 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000);
2975 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000);
2977 rtl8168_config_eee_mac(tp
);
2979 rtl_w0w1_eri(tp
, 0x2fc, 0x01, 0x06);
2980 rtl_eri_clear_bits(tp
, 0x1b0, BIT(12));
2982 rtl_pcie_state_l2l3_disable(tp
);
2985 static void rtl_hw_start_8168g_1(struct rtl8169_private
*tp
)
2987 static const struct ephy_info e_info_8168g_1
[] = {
2988 { 0x00, 0x0008, 0x0000 },
2989 { 0x0c, 0x3ff0, 0x0820 },
2990 { 0x1e, 0x0000, 0x0001 },
2991 { 0x19, 0x8000, 0x0000 }
2994 rtl_hw_start_8168g(tp
);
2996 /* disable aspm and clock request before access ephy */
2997 rtl_hw_aspm_clkreq_enable(tp
, false);
2998 rtl_ephy_init(tp
, e_info_8168g_1
);
2999 rtl_hw_aspm_clkreq_enable(tp
, true);
3002 static void rtl_hw_start_8168g_2(struct rtl8169_private
*tp
)
3004 static const struct ephy_info e_info_8168g_2
[] = {
3005 { 0x00, 0x0008, 0x0000 },
3006 { 0x0c, 0x3ff0, 0x0820 },
3007 { 0x19, 0xffff, 0x7c00 },
3008 { 0x1e, 0xffff, 0x20eb },
3009 { 0x0d, 0xffff, 0x1666 },
3010 { 0x00, 0xffff, 0x10a3 },
3011 { 0x06, 0xffff, 0xf050 },
3012 { 0x04, 0x0000, 0x0010 },
3013 { 0x1d, 0x4000, 0x0000 },
3016 rtl_hw_start_8168g(tp
);
3018 /* disable aspm and clock request before access ephy */
3019 rtl_hw_aspm_clkreq_enable(tp
, false);
3020 rtl_ephy_init(tp
, e_info_8168g_2
);
3023 static void rtl_hw_start_8411_2(struct rtl8169_private
*tp
)
3025 static const struct ephy_info e_info_8411_2
[] = {
3026 { 0x00, 0x0008, 0x0000 },
3027 { 0x0c, 0x37d0, 0x0820 },
3028 { 0x1e, 0x0000, 0x0001 },
3029 { 0x19, 0x8021, 0x0000 },
3030 { 0x1e, 0x0000, 0x2000 },
3031 { 0x0d, 0x0100, 0x0200 },
3032 { 0x00, 0x0000, 0x0080 },
3033 { 0x06, 0x0000, 0x0010 },
3034 { 0x04, 0x0000, 0x0010 },
3035 { 0x1d, 0x0000, 0x4000 },
3038 rtl_hw_start_8168g(tp
);
3040 /* disable aspm and clock request before access ephy */
3041 rtl_hw_aspm_clkreq_enable(tp
, false);
3042 rtl_ephy_init(tp
, e_info_8411_2
);
3044 /* The following Realtek-provided magic fixes an issue with the RX unit
3045 * getting confused after the PHY having been powered-down.
3047 r8168_mac_ocp_write(tp
, 0xFC28, 0x0000);
3048 r8168_mac_ocp_write(tp
, 0xFC2A, 0x0000);
3049 r8168_mac_ocp_write(tp
, 0xFC2C, 0x0000);
3050 r8168_mac_ocp_write(tp
, 0xFC2E, 0x0000);
3051 r8168_mac_ocp_write(tp
, 0xFC30, 0x0000);
3052 r8168_mac_ocp_write(tp
, 0xFC32, 0x0000);
3053 r8168_mac_ocp_write(tp
, 0xFC34, 0x0000);
3054 r8168_mac_ocp_write(tp
, 0xFC36, 0x0000);
3056 r8168_mac_ocp_write(tp
, 0xFC26, 0x0000);
3058 r8168_mac_ocp_write(tp
, 0xF800, 0xE008);
3059 r8168_mac_ocp_write(tp
, 0xF802, 0xE00A);
3060 r8168_mac_ocp_write(tp
, 0xF804, 0xE00C);
3061 r8168_mac_ocp_write(tp
, 0xF806, 0xE00E);
3062 r8168_mac_ocp_write(tp
, 0xF808, 0xE027);
3063 r8168_mac_ocp_write(tp
, 0xF80A, 0xE04F);
3064 r8168_mac_ocp_write(tp
, 0xF80C, 0xE05E);
3065 r8168_mac_ocp_write(tp
, 0xF80E, 0xE065);
3066 r8168_mac_ocp_write(tp
, 0xF810, 0xC602);
3067 r8168_mac_ocp_write(tp
, 0xF812, 0xBE00);
3068 r8168_mac_ocp_write(tp
, 0xF814, 0x0000);
3069 r8168_mac_ocp_write(tp
, 0xF816, 0xC502);
3070 r8168_mac_ocp_write(tp
, 0xF818, 0xBD00);
3071 r8168_mac_ocp_write(tp
, 0xF81A, 0x074C);
3072 r8168_mac_ocp_write(tp
, 0xF81C, 0xC302);
3073 r8168_mac_ocp_write(tp
, 0xF81E, 0xBB00);
3074 r8168_mac_ocp_write(tp
, 0xF820, 0x080A);
3075 r8168_mac_ocp_write(tp
, 0xF822, 0x6420);
3076 r8168_mac_ocp_write(tp
, 0xF824, 0x48C2);
3077 r8168_mac_ocp_write(tp
, 0xF826, 0x8C20);
3078 r8168_mac_ocp_write(tp
, 0xF828, 0xC516);
3079 r8168_mac_ocp_write(tp
, 0xF82A, 0x64A4);
3080 r8168_mac_ocp_write(tp
, 0xF82C, 0x49C0);
3081 r8168_mac_ocp_write(tp
, 0xF82E, 0xF009);
3082 r8168_mac_ocp_write(tp
, 0xF830, 0x74A2);
3083 r8168_mac_ocp_write(tp
, 0xF832, 0x8CA5);
3084 r8168_mac_ocp_write(tp
, 0xF834, 0x74A0);
3085 r8168_mac_ocp_write(tp
, 0xF836, 0xC50E);
3086 r8168_mac_ocp_write(tp
, 0xF838, 0x9CA2);
3087 r8168_mac_ocp_write(tp
, 0xF83A, 0x1C11);
3088 r8168_mac_ocp_write(tp
, 0xF83C, 0x9CA0);
3089 r8168_mac_ocp_write(tp
, 0xF83E, 0xE006);
3090 r8168_mac_ocp_write(tp
, 0xF840, 0x74F8);
3091 r8168_mac_ocp_write(tp
, 0xF842, 0x48C4);
3092 r8168_mac_ocp_write(tp
, 0xF844, 0x8CF8);
3093 r8168_mac_ocp_write(tp
, 0xF846, 0xC404);
3094 r8168_mac_ocp_write(tp
, 0xF848, 0xBC00);
3095 r8168_mac_ocp_write(tp
, 0xF84A, 0xC403);
3096 r8168_mac_ocp_write(tp
, 0xF84C, 0xBC00);
3097 r8168_mac_ocp_write(tp
, 0xF84E, 0x0BF2);
3098 r8168_mac_ocp_write(tp
, 0xF850, 0x0C0A);
3099 r8168_mac_ocp_write(tp
, 0xF852, 0xE434);
3100 r8168_mac_ocp_write(tp
, 0xF854, 0xD3C0);
3101 r8168_mac_ocp_write(tp
, 0xF856, 0x49D9);
3102 r8168_mac_ocp_write(tp
, 0xF858, 0xF01F);
3103 r8168_mac_ocp_write(tp
, 0xF85A, 0xC526);
3104 r8168_mac_ocp_write(tp
, 0xF85C, 0x64A5);
3105 r8168_mac_ocp_write(tp
, 0xF85E, 0x1400);
3106 r8168_mac_ocp_write(tp
, 0xF860, 0xF007);
3107 r8168_mac_ocp_write(tp
, 0xF862, 0x0C01);
3108 r8168_mac_ocp_write(tp
, 0xF864, 0x8CA5);
3109 r8168_mac_ocp_write(tp
, 0xF866, 0x1C15);
3110 r8168_mac_ocp_write(tp
, 0xF868, 0xC51B);
3111 r8168_mac_ocp_write(tp
, 0xF86A, 0x9CA0);
3112 r8168_mac_ocp_write(tp
, 0xF86C, 0xE013);
3113 r8168_mac_ocp_write(tp
, 0xF86E, 0xC519);
3114 r8168_mac_ocp_write(tp
, 0xF870, 0x74A0);
3115 r8168_mac_ocp_write(tp
, 0xF872, 0x48C4);
3116 r8168_mac_ocp_write(tp
, 0xF874, 0x8CA0);
3117 r8168_mac_ocp_write(tp
, 0xF876, 0xC516);
3118 r8168_mac_ocp_write(tp
, 0xF878, 0x74A4);
3119 r8168_mac_ocp_write(tp
, 0xF87A, 0x48C8);
3120 r8168_mac_ocp_write(tp
, 0xF87C, 0x48CA);
3121 r8168_mac_ocp_write(tp
, 0xF87E, 0x9CA4);
3122 r8168_mac_ocp_write(tp
, 0xF880, 0xC512);
3123 r8168_mac_ocp_write(tp
, 0xF882, 0x1B00);
3124 r8168_mac_ocp_write(tp
, 0xF884, 0x9BA0);
3125 r8168_mac_ocp_write(tp
, 0xF886, 0x1B1C);
3126 r8168_mac_ocp_write(tp
, 0xF888, 0x483F);
3127 r8168_mac_ocp_write(tp
, 0xF88A, 0x9BA2);
3128 r8168_mac_ocp_write(tp
, 0xF88C, 0x1B04);
3129 r8168_mac_ocp_write(tp
, 0xF88E, 0xC508);
3130 r8168_mac_ocp_write(tp
, 0xF890, 0x9BA0);
3131 r8168_mac_ocp_write(tp
, 0xF892, 0xC505);
3132 r8168_mac_ocp_write(tp
, 0xF894, 0xBD00);
3133 r8168_mac_ocp_write(tp
, 0xF896, 0xC502);
3134 r8168_mac_ocp_write(tp
, 0xF898, 0xBD00);
3135 r8168_mac_ocp_write(tp
, 0xF89A, 0x0300);
3136 r8168_mac_ocp_write(tp
, 0xF89C, 0x051E);
3137 r8168_mac_ocp_write(tp
, 0xF89E, 0xE434);
3138 r8168_mac_ocp_write(tp
, 0xF8A0, 0xE018);
3139 r8168_mac_ocp_write(tp
, 0xF8A2, 0xE092);
3140 r8168_mac_ocp_write(tp
, 0xF8A4, 0xDE20);
3141 r8168_mac_ocp_write(tp
, 0xF8A6, 0xD3C0);
3142 r8168_mac_ocp_write(tp
, 0xF8A8, 0xC50F);
3143 r8168_mac_ocp_write(tp
, 0xF8AA, 0x76A4);
3144 r8168_mac_ocp_write(tp
, 0xF8AC, 0x49E3);
3145 r8168_mac_ocp_write(tp
, 0xF8AE, 0xF007);
3146 r8168_mac_ocp_write(tp
, 0xF8B0, 0x49C0);
3147 r8168_mac_ocp_write(tp
, 0xF8B2, 0xF103);
3148 r8168_mac_ocp_write(tp
, 0xF8B4, 0xC607);
3149 r8168_mac_ocp_write(tp
, 0xF8B6, 0xBE00);
3150 r8168_mac_ocp_write(tp
, 0xF8B8, 0xC606);
3151 r8168_mac_ocp_write(tp
, 0xF8BA, 0xBE00);
3152 r8168_mac_ocp_write(tp
, 0xF8BC, 0xC602);
3153 r8168_mac_ocp_write(tp
, 0xF8BE, 0xBE00);
3154 r8168_mac_ocp_write(tp
, 0xF8C0, 0x0C4C);
3155 r8168_mac_ocp_write(tp
, 0xF8C2, 0x0C28);
3156 r8168_mac_ocp_write(tp
, 0xF8C4, 0x0C2C);
3157 r8168_mac_ocp_write(tp
, 0xF8C6, 0xDC00);
3158 r8168_mac_ocp_write(tp
, 0xF8C8, 0xC707);
3159 r8168_mac_ocp_write(tp
, 0xF8CA, 0x1D00);
3160 r8168_mac_ocp_write(tp
, 0xF8CC, 0x8DE2);
3161 r8168_mac_ocp_write(tp
, 0xF8CE, 0x48C1);
3162 r8168_mac_ocp_write(tp
, 0xF8D0, 0xC502);
3163 r8168_mac_ocp_write(tp
, 0xF8D2, 0xBD00);
3164 r8168_mac_ocp_write(tp
, 0xF8D4, 0x00AA);
3165 r8168_mac_ocp_write(tp
, 0xF8D6, 0xE0C0);
3166 r8168_mac_ocp_write(tp
, 0xF8D8, 0xC502);
3167 r8168_mac_ocp_write(tp
, 0xF8DA, 0xBD00);
3168 r8168_mac_ocp_write(tp
, 0xF8DC, 0x0132);
3170 r8168_mac_ocp_write(tp
, 0xFC26, 0x8000);
3172 r8168_mac_ocp_write(tp
, 0xFC2A, 0x0743);
3173 r8168_mac_ocp_write(tp
, 0xFC2C, 0x0801);
3174 r8168_mac_ocp_write(tp
, 0xFC2E, 0x0BE9);
3175 r8168_mac_ocp_write(tp
, 0xFC30, 0x02FD);
3176 r8168_mac_ocp_write(tp
, 0xFC32, 0x0C25);
3177 r8168_mac_ocp_write(tp
, 0xFC34, 0x00A9);
3178 r8168_mac_ocp_write(tp
, 0xFC36, 0x012D);
3180 rtl_hw_aspm_clkreq_enable(tp
, true);
3183 static void rtl_hw_start_8168h_1(struct rtl8169_private
*tp
)
3185 static const struct ephy_info e_info_8168h_1
[] = {
3186 { 0x1e, 0x0800, 0x0001 },
3187 { 0x1d, 0x0000, 0x0800 },
3188 { 0x05, 0xffff, 0x2089 },
3189 { 0x06, 0xffff, 0x5881 },
3190 { 0x04, 0xffff, 0x854a },
3191 { 0x01, 0xffff, 0x068b }
3195 /* disable aspm and clock request before access ephy */
3196 rtl_hw_aspm_clkreq_enable(tp
, false);
3197 rtl_ephy_init(tp
, e_info_8168h_1
);
3199 rtl_set_fifo_size(tp
, 0x08, 0x10, 0x02, 0x06);
3200 rtl8168g_set_pause_thresholds(tp
, 0x38, 0x48);
3202 rtl_set_def_aspm_entry_latency(tp
);
3204 rtl_reset_packet_filter(tp
);
3206 rtl_eri_set_bits(tp
, 0xdc, 0x001c);
3208 rtl_eri_write(tp
, 0x5f0, ERIAR_MASK_0011
, 0x4f87);
3210 RTL_W32(tp
, MISC
, RTL_R32(tp
, MISC
) & ~RXDV_GATED_EN
);
3212 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000);
3213 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000);
3215 rtl8168_config_eee_mac(tp
);
3217 RTL_W8(tp
, DLLPR
, RTL_R8(tp
, DLLPR
) & ~PFM_EN
);
3218 RTL_W8(tp
, MISC_1
, RTL_R8(tp
, MISC_1
) & ~PFM_D3COLD_EN
);
3220 RTL_W8(tp
, DLLPR
, RTL_R8(tp
, DLLPR
) & ~TX_10M_PS_EN
);
3222 rtl_eri_clear_bits(tp
, 0x1b0, BIT(12));
3224 rtl_pcie_state_l2l3_disable(tp
);
3226 rg_saw_cnt
= phy_read_paged(tp
->phydev
, 0x0c42, 0x13) & 0x3fff;
3227 if (rg_saw_cnt
> 0) {
3230 sw_cnt_1ms_ini
= 16000000/rg_saw_cnt
;
3231 sw_cnt_1ms_ini
&= 0x0fff;
3232 r8168_mac_ocp_modify(tp
, 0xd412, 0x0fff, sw_cnt_1ms_ini
);
3235 r8168_mac_ocp_modify(tp
, 0xe056, 0x00f0, 0x0070);
3236 r8168_mac_ocp_modify(tp
, 0xe052, 0x6000, 0x8008);
3237 r8168_mac_ocp_modify(tp
, 0xe0d6, 0x01ff, 0x017f);
3238 r8168_mac_ocp_modify(tp
, 0xd420, 0x0fff, 0x047f);
3240 r8168_mac_ocp_write(tp
, 0xe63e, 0x0001);
3241 r8168_mac_ocp_write(tp
, 0xe63e, 0x0000);
3242 r8168_mac_ocp_write(tp
, 0xc094, 0x0000);
3243 r8168_mac_ocp_write(tp
, 0xc09e, 0x0000);
3245 rtl_hw_aspm_clkreq_enable(tp
, true);
3248 static void rtl_hw_start_8168ep(struct rtl8169_private
*tp
)
3250 rtl8168ep_stop_cmac(tp
);
3252 rtl_set_fifo_size(tp
, 0x08, 0x10, 0x02, 0x06);
3253 rtl8168g_set_pause_thresholds(tp
, 0x2f, 0x5f);
3255 rtl_set_def_aspm_entry_latency(tp
);
3257 rtl_reset_packet_filter(tp
);
3259 rtl_eri_write(tp
, 0x5f0, ERIAR_MASK_0011
, 0x4f87);
3261 RTL_W32(tp
, MISC
, RTL_R32(tp
, MISC
) & ~RXDV_GATED_EN
);
3263 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000);
3264 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000);
3266 rtl8168_config_eee_mac(tp
);
3268 rtl_w0w1_eri(tp
, 0x2fc, 0x01, 0x06);
3270 RTL_W8(tp
, DLLPR
, RTL_R8(tp
, DLLPR
) & ~TX_10M_PS_EN
);
3272 rtl_pcie_state_l2l3_disable(tp
);
3275 static void rtl_hw_start_8168ep_1(struct rtl8169_private
*tp
)
3277 static const struct ephy_info e_info_8168ep_1
[] = {
3278 { 0x00, 0xffff, 0x10ab },
3279 { 0x06, 0xffff, 0xf030 },
3280 { 0x08, 0xffff, 0x2006 },
3281 { 0x0d, 0xffff, 0x1666 },
3282 { 0x0c, 0x3ff0, 0x0000 }
3285 /* disable aspm and clock request before access ephy */
3286 rtl_hw_aspm_clkreq_enable(tp
, false);
3287 rtl_ephy_init(tp
, e_info_8168ep_1
);
3289 rtl_hw_start_8168ep(tp
);
3291 rtl_hw_aspm_clkreq_enable(tp
, true);
3294 static void rtl_hw_start_8168ep_2(struct rtl8169_private
*tp
)
3296 static const struct ephy_info e_info_8168ep_2
[] = {
3297 { 0x00, 0xffff, 0x10a3 },
3298 { 0x19, 0xffff, 0xfc00 },
3299 { 0x1e, 0xffff, 0x20ea }
3302 /* disable aspm and clock request before access ephy */
3303 rtl_hw_aspm_clkreq_enable(tp
, false);
3304 rtl_ephy_init(tp
, e_info_8168ep_2
);
3306 rtl_hw_start_8168ep(tp
);
3308 RTL_W8(tp
, DLLPR
, RTL_R8(tp
, DLLPR
) & ~PFM_EN
);
3309 RTL_W8(tp
, MISC_1
, RTL_R8(tp
, MISC_1
) & ~PFM_D3COLD_EN
);
3311 rtl_hw_aspm_clkreq_enable(tp
, true);
3314 static void rtl_hw_start_8168ep_3(struct rtl8169_private
*tp
)
3316 static const struct ephy_info e_info_8168ep_3
[] = {
3317 { 0x00, 0x0000, 0x0080 },
3318 { 0x0d, 0x0100, 0x0200 },
3319 { 0x19, 0x8021, 0x0000 },
3320 { 0x1e, 0x0000, 0x2000 },
3323 /* disable aspm and clock request before access ephy */
3324 rtl_hw_aspm_clkreq_enable(tp
, false);
3325 rtl_ephy_init(tp
, e_info_8168ep_3
);
3327 rtl_hw_start_8168ep(tp
);
3329 RTL_W8(tp
, DLLPR
, RTL_R8(tp
, DLLPR
) & ~PFM_EN
);
3330 RTL_W8(tp
, MISC_1
, RTL_R8(tp
, MISC_1
) & ~PFM_D3COLD_EN
);
3332 r8168_mac_ocp_modify(tp
, 0xd3e2, 0x0fff, 0x0271);
3333 r8168_mac_ocp_modify(tp
, 0xd3e4, 0x00ff, 0x0000);
3334 r8168_mac_ocp_modify(tp
, 0xe860, 0x0000, 0x0080);
3336 rtl_hw_aspm_clkreq_enable(tp
, true);
3339 static void rtl_hw_start_8117(struct rtl8169_private
*tp
)
3341 static const struct ephy_info e_info_8117
[] = {
3342 { 0x19, 0x0040, 0x1100 },
3343 { 0x59, 0x0040, 0x1100 },
3347 rtl8168ep_stop_cmac(tp
);
3349 /* disable aspm and clock request before access ephy */
3350 rtl_hw_aspm_clkreq_enable(tp
, false);
3351 rtl_ephy_init(tp
, e_info_8117
);
3353 rtl_set_fifo_size(tp
, 0x08, 0x10, 0x02, 0x06);
3354 rtl8168g_set_pause_thresholds(tp
, 0x2f, 0x5f);
3356 rtl_set_def_aspm_entry_latency(tp
);
3358 rtl_reset_packet_filter(tp
);
3360 rtl_eri_set_bits(tp
, 0xd4, 0x0010);
3362 rtl_eri_write(tp
, 0x5f0, ERIAR_MASK_0011
, 0x4f87);
3364 RTL_W32(tp
, MISC
, RTL_R32(tp
, MISC
) & ~RXDV_GATED_EN
);
3366 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000);
3367 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000);
3369 rtl8168_config_eee_mac(tp
);
3371 RTL_W8(tp
, DLLPR
, RTL_R8(tp
, DLLPR
) & ~PFM_EN
);
3372 RTL_W8(tp
, MISC_1
, RTL_R8(tp
, MISC_1
) & ~PFM_D3COLD_EN
);
3374 RTL_W8(tp
, DLLPR
, RTL_R8(tp
, DLLPR
) & ~TX_10M_PS_EN
);
3376 rtl_eri_clear_bits(tp
, 0x1b0, BIT(12));
3378 rtl_pcie_state_l2l3_disable(tp
);
3380 rg_saw_cnt
= phy_read_paged(tp
->phydev
, 0x0c42, 0x13) & 0x3fff;
3381 if (rg_saw_cnt
> 0) {
3384 sw_cnt_1ms_ini
= (16000000 / rg_saw_cnt
) & 0x0fff;
3385 r8168_mac_ocp_modify(tp
, 0xd412, 0x0fff, sw_cnt_1ms_ini
);
3388 r8168_mac_ocp_modify(tp
, 0xe056, 0x00f0, 0x0070);
3389 r8168_mac_ocp_write(tp
, 0xea80, 0x0003);
3390 r8168_mac_ocp_modify(tp
, 0xe052, 0x0000, 0x0009);
3391 r8168_mac_ocp_modify(tp
, 0xd420, 0x0fff, 0x047f);
3393 r8168_mac_ocp_write(tp
, 0xe63e, 0x0001);
3394 r8168_mac_ocp_write(tp
, 0xe63e, 0x0000);
3395 r8168_mac_ocp_write(tp
, 0xc094, 0x0000);
3396 r8168_mac_ocp_write(tp
, 0xc09e, 0x0000);
3398 /* firmware is for MAC only */
3399 r8169_apply_firmware(tp
);
3401 rtl_hw_aspm_clkreq_enable(tp
, true);
3404 static void rtl_hw_start_8102e_1(struct rtl8169_private
*tp
)
3406 static const struct ephy_info e_info_8102e_1
[] = {
3407 { 0x01, 0, 0x6e65 },
3408 { 0x02, 0, 0x091f },
3409 { 0x03, 0, 0xc2f9 },
3410 { 0x06, 0, 0xafb5 },
3411 { 0x07, 0, 0x0e00 },
3412 { 0x19, 0, 0xec80 },
3413 { 0x01, 0, 0x2e65 },
3418 rtl_set_def_aspm_entry_latency(tp
);
3420 RTL_W8(tp
, DBG_REG
, FIX_NAK_1
);
3423 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
3424 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) & ~Beacon_en
);
3426 cfg1
= RTL_R8(tp
, Config1
);
3427 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
3428 RTL_W8(tp
, Config1
, cfg1
& ~LEDS0
);
3430 rtl_ephy_init(tp
, e_info_8102e_1
);
3433 static void rtl_hw_start_8102e_2(struct rtl8169_private
*tp
)
3435 rtl_set_def_aspm_entry_latency(tp
);
3437 RTL_W8(tp
, Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
3438 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) & ~Beacon_en
);
3441 static void rtl_hw_start_8102e_3(struct rtl8169_private
*tp
)
3443 rtl_hw_start_8102e_2(tp
);
3445 rtl_ephy_write(tp
, 0x03, 0xc2f9);
3448 static void rtl_hw_start_8401(struct rtl8169_private
*tp
)
3450 static const struct ephy_info e_info_8401
[] = {
3451 { 0x01, 0xffff, 0x6fe5 },
3452 { 0x03, 0xffff, 0x0599 },
3453 { 0x06, 0xffff, 0xaf25 },
3454 { 0x07, 0xffff, 0x8e68 },
3457 rtl_ephy_init(tp
, e_info_8401
);
3458 RTL_W8(tp
, Config3
, RTL_R8(tp
, Config3
) & ~Beacon_en
);
3461 static void rtl_hw_start_8105e_1(struct rtl8169_private
*tp
)
3463 static const struct ephy_info e_info_8105e_1
[] = {
3464 { 0x07, 0, 0x4000 },
3465 { 0x19, 0, 0x0200 },
3466 { 0x19, 0, 0x0020 },
3467 { 0x1e, 0, 0x2000 },
3468 { 0x03, 0, 0x0001 },
3469 { 0x19, 0, 0x0100 },
3470 { 0x19, 0, 0x0004 },
3474 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3475 RTL_W32(tp
, FuncEvent
, RTL_R32(tp
, FuncEvent
) | 0x002800);
3477 /* Disable Early Tally Counter */
3478 RTL_W32(tp
, FuncEvent
, RTL_R32(tp
, FuncEvent
) & ~0x010000);
3480 RTL_W8(tp
, MCU
, RTL_R8(tp
, MCU
) | EN_NDP
| EN_OOB_RESET
);
3481 RTL_W8(tp
, DLLPR
, RTL_R8(tp
, DLLPR
) | PFM_EN
);
3483 rtl_ephy_init(tp
, e_info_8105e_1
);
3485 rtl_pcie_state_l2l3_disable(tp
);
3488 static void rtl_hw_start_8105e_2(struct rtl8169_private
*tp
)
3490 rtl_hw_start_8105e_1(tp
);
3491 rtl_ephy_write(tp
, 0x1e, rtl_ephy_read(tp
, 0x1e) | 0x8000);
3494 static void rtl_hw_start_8402(struct rtl8169_private
*tp
)
3496 static const struct ephy_info e_info_8402
[] = {
3497 { 0x19, 0xffff, 0xff64 },
3501 rtl_set_def_aspm_entry_latency(tp
);
3503 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3504 RTL_W32(tp
, FuncEvent
, RTL_R32(tp
, FuncEvent
) | 0x002800);
3506 RTL_W8(tp
, MCU
, RTL_R8(tp
, MCU
) & ~NOW_IS_OOB
);
3508 rtl_ephy_init(tp
, e_info_8402
);
3510 rtl_set_fifo_size(tp
, 0x00, 0x00, 0x02, 0x06);
3511 rtl_reset_packet_filter(tp
);
3512 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000);
3513 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000);
3514 rtl_w0w1_eri(tp
, 0x0d4, 0x0e00, 0xff00);
3517 rtl_eri_write(tp
, 0x1b0, ERIAR_MASK_0011
, 0x0000);
3519 rtl_pcie_state_l2l3_disable(tp
);
3522 static void rtl_hw_start_8106(struct rtl8169_private
*tp
)
3524 rtl_hw_aspm_clkreq_enable(tp
, false);
3526 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3527 RTL_W32(tp
, FuncEvent
, RTL_R32(tp
, FuncEvent
) | 0x002800);
3529 RTL_W32(tp
, MISC
, (RTL_R32(tp
, MISC
) | DISABLE_LAN_EN
) & ~EARLY_TALLY_EN
);
3530 RTL_W8(tp
, MCU
, RTL_R8(tp
, MCU
) | EN_NDP
| EN_OOB_RESET
);
3531 RTL_W8(tp
, DLLPR
, RTL_R8(tp
, DLLPR
) & ~PFM_EN
);
3533 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */
3534 rtl_set_aspm_entry_latency(tp
, 0x2f);
3536 rtl_eri_write(tp
, 0x1d0, ERIAR_MASK_0011
, 0x0000);
3539 rtl_eri_write(tp
, 0x1b0, ERIAR_MASK_0011
, 0x0000);
3541 rtl_pcie_state_l2l3_disable(tp
);
3542 rtl_hw_aspm_clkreq_enable(tp
, true);
3545 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond
)
3547 return r8168_mac_ocp_read(tp
, 0xe00e) & BIT(13);
3550 static void rtl_hw_start_8125_common(struct rtl8169_private
*tp
)
3552 rtl_pcie_state_l2l3_disable(tp
);
3554 RTL_W16(tp
, 0x382, 0x221b);
3555 RTL_W8(tp
, 0x4500, 0);
3556 RTL_W16(tp
, 0x4800, 0);
3559 r8168_mac_ocp_modify(tp
, 0xd40a, 0x0010, 0x0000);
3561 RTL_W8(tp
, Config1
, RTL_R8(tp
, Config1
) & ~0x10);
3563 r8168_mac_ocp_write(tp
, 0xc140, 0xffff);
3564 r8168_mac_ocp_write(tp
, 0xc142, 0xffff);
3566 r8168_mac_ocp_modify(tp
, 0xd3e2, 0x0fff, 0x03a9);
3567 r8168_mac_ocp_modify(tp
, 0xd3e4, 0x00ff, 0x0000);
3568 r8168_mac_ocp_modify(tp
, 0xe860, 0x0000, 0x0080);
3570 /* disable new tx descriptor format */
3571 r8168_mac_ocp_modify(tp
, 0xeb58, 0x0001, 0x0000);
3573 if (tp
->mac_version
== RTL_GIGA_MAC_VER_63
)
3574 r8168_mac_ocp_modify(tp
, 0xe614, 0x0700, 0x0200);
3576 r8168_mac_ocp_modify(tp
, 0xe614, 0x0700, 0x0400);
3578 if (tp
->mac_version
== RTL_GIGA_MAC_VER_63
)
3579 r8168_mac_ocp_modify(tp
, 0xe63e, 0x0c30, 0x0000);
3581 r8168_mac_ocp_modify(tp
, 0xe63e, 0x0c30, 0x0020);
3583 r8168_mac_ocp_modify(tp
, 0xc0b4, 0x0000, 0x000c);
3584 r8168_mac_ocp_modify(tp
, 0xeb6a, 0x00ff, 0x0033);
3585 r8168_mac_ocp_modify(tp
, 0xeb50, 0x03e0, 0x0040);
3586 r8168_mac_ocp_modify(tp
, 0xe056, 0x00f0, 0x0030);
3587 r8168_mac_ocp_modify(tp
, 0xe040, 0x1000, 0x0000);
3588 r8168_mac_ocp_modify(tp
, 0xea1c, 0x0003, 0x0001);
3589 r8168_mac_ocp_modify(tp
, 0xe0c0, 0x4f0f, 0x4403);
3590 r8168_mac_ocp_modify(tp
, 0xe052, 0x0080, 0x0068);
3591 r8168_mac_ocp_modify(tp
, 0xd430, 0x0fff, 0x047f);
3593 r8168_mac_ocp_modify(tp
, 0xea1c, 0x0004, 0x0000);
3594 r8168_mac_ocp_modify(tp
, 0xeb54, 0x0000, 0x0001);
3596 r8168_mac_ocp_modify(tp
, 0xeb54, 0x0001, 0x0000);
3597 RTL_W16(tp
, 0x1880, RTL_R16(tp
, 0x1880) & ~0x0030);
3599 r8168_mac_ocp_write(tp
, 0xe098, 0xc302);
3601 rtl_loop_wait_low(tp
, &rtl_mac_ocp_e00e_cond
, 1000, 10);
3603 if (tp
->mac_version
== RTL_GIGA_MAC_VER_63
)
3604 rtl8125b_config_eee_mac(tp
);
3606 rtl8125a_config_eee_mac(tp
);
3608 RTL_W32(tp
, MISC
, RTL_R32(tp
, MISC
) & ~RXDV_GATED_EN
);
3612 static void rtl_hw_start_8125a_1(struct rtl8169_private
*tp
)
3614 static const struct ephy_info e_info_8125a_1
[] = {
3615 { 0x01, 0xffff, 0xa812 },
3616 { 0x09, 0xffff, 0x520c },
3617 { 0x04, 0xffff, 0xd000 },
3618 { 0x0d, 0xffff, 0xf702 },
3619 { 0x0a, 0xffff, 0x8653 },
3620 { 0x06, 0xffff, 0x001e },
3621 { 0x08, 0xffff, 0x3595 },
3622 { 0x20, 0xffff, 0x9455 },
3623 { 0x21, 0xffff, 0x99ff },
3624 { 0x02, 0xffff, 0x6046 },
3625 { 0x29, 0xffff, 0xfe00 },
3626 { 0x23, 0xffff, 0xab62 },
3628 { 0x41, 0xffff, 0xa80c },
3629 { 0x49, 0xffff, 0x520c },
3630 { 0x44, 0xffff, 0xd000 },
3631 { 0x4d, 0xffff, 0xf702 },
3632 { 0x4a, 0xffff, 0x8653 },
3633 { 0x46, 0xffff, 0x001e },
3634 { 0x48, 0xffff, 0x3595 },
3635 { 0x60, 0xffff, 0x9455 },
3636 { 0x61, 0xffff, 0x99ff },
3637 { 0x42, 0xffff, 0x6046 },
3638 { 0x69, 0xffff, 0xfe00 },
3639 { 0x63, 0xffff, 0xab62 },
3642 rtl_set_def_aspm_entry_latency(tp
);
3644 /* disable aspm and clock request before access ephy */
3645 rtl_hw_aspm_clkreq_enable(tp
, false);
3646 rtl_ephy_init(tp
, e_info_8125a_1
);
3648 rtl_hw_start_8125_common(tp
);
3649 rtl_hw_aspm_clkreq_enable(tp
, true);
3652 static void rtl_hw_start_8125a_2(struct rtl8169_private
*tp
)
3654 static const struct ephy_info e_info_8125a_2
[] = {
3655 { 0x04, 0xffff, 0xd000 },
3656 { 0x0a, 0xffff, 0x8653 },
3657 { 0x23, 0xffff, 0xab66 },
3658 { 0x20, 0xffff, 0x9455 },
3659 { 0x21, 0xffff, 0x99ff },
3660 { 0x29, 0xffff, 0xfe04 },
3662 { 0x44, 0xffff, 0xd000 },
3663 { 0x4a, 0xffff, 0x8653 },
3664 { 0x63, 0xffff, 0xab66 },
3665 { 0x60, 0xffff, 0x9455 },
3666 { 0x61, 0xffff, 0x99ff },
3667 { 0x69, 0xffff, 0xfe04 },
3670 rtl_set_def_aspm_entry_latency(tp
);
3672 /* disable aspm and clock request before access ephy */
3673 rtl_hw_aspm_clkreq_enable(tp
, false);
3674 rtl_ephy_init(tp
, e_info_8125a_2
);
3676 rtl_hw_start_8125_common(tp
);
3677 rtl_hw_aspm_clkreq_enable(tp
, true);
3680 static void rtl_hw_start_8125b(struct rtl8169_private
*tp
)
3682 static const struct ephy_info e_info_8125b
[] = {
3683 { 0x0b, 0xffff, 0xa908 },
3684 { 0x1e, 0xffff, 0x20eb },
3685 { 0x4b, 0xffff, 0xa908 },
3686 { 0x5e, 0xffff, 0x20eb },
3687 { 0x22, 0x0030, 0x0020 },
3688 { 0x62, 0x0030, 0x0020 },
3691 rtl_set_def_aspm_entry_latency(tp
);
3692 rtl_hw_aspm_clkreq_enable(tp
, false);
3694 rtl_ephy_init(tp
, e_info_8125b
);
3695 rtl_hw_start_8125_common(tp
);
3697 rtl_hw_aspm_clkreq_enable(tp
, true);
3700 static void rtl_hw_config(struct rtl8169_private
*tp
)
3702 static const rtl_generic_fct hw_configs
[] = {
3703 [RTL_GIGA_MAC_VER_07
] = rtl_hw_start_8102e_1
,
3704 [RTL_GIGA_MAC_VER_08
] = rtl_hw_start_8102e_3
,
3705 [RTL_GIGA_MAC_VER_09
] = rtl_hw_start_8102e_2
,
3706 [RTL_GIGA_MAC_VER_10
] = NULL
,
3707 [RTL_GIGA_MAC_VER_11
] = rtl_hw_start_8168b
,
3708 [RTL_GIGA_MAC_VER_12
] = rtl_hw_start_8168b
,
3709 [RTL_GIGA_MAC_VER_13
] = NULL
,
3710 [RTL_GIGA_MAC_VER_14
] = rtl_hw_start_8401
,
3711 [RTL_GIGA_MAC_VER_16
] = NULL
,
3712 [RTL_GIGA_MAC_VER_17
] = rtl_hw_start_8168b
,
3713 [RTL_GIGA_MAC_VER_18
] = rtl_hw_start_8168cp_1
,
3714 [RTL_GIGA_MAC_VER_19
] = rtl_hw_start_8168c_1
,
3715 [RTL_GIGA_MAC_VER_20
] = rtl_hw_start_8168c_2
,
3716 [RTL_GIGA_MAC_VER_21
] = rtl_hw_start_8168c_2
,
3717 [RTL_GIGA_MAC_VER_22
] = rtl_hw_start_8168c_4
,
3718 [RTL_GIGA_MAC_VER_23
] = rtl_hw_start_8168cp_2
,
3719 [RTL_GIGA_MAC_VER_24
] = rtl_hw_start_8168cp_3
,
3720 [RTL_GIGA_MAC_VER_25
] = rtl_hw_start_8168d
,
3721 [RTL_GIGA_MAC_VER_26
] = rtl_hw_start_8168d
,
3722 [RTL_GIGA_MAC_VER_27
] = rtl_hw_start_8168d
,
3723 [RTL_GIGA_MAC_VER_28
] = rtl_hw_start_8168d_4
,
3724 [RTL_GIGA_MAC_VER_29
] = rtl_hw_start_8105e_1
,
3725 [RTL_GIGA_MAC_VER_30
] = rtl_hw_start_8105e_2
,
3726 [RTL_GIGA_MAC_VER_31
] = rtl_hw_start_8168d
,
3727 [RTL_GIGA_MAC_VER_32
] = rtl_hw_start_8168e_1
,
3728 [RTL_GIGA_MAC_VER_33
] = rtl_hw_start_8168e_1
,
3729 [RTL_GIGA_MAC_VER_34
] = rtl_hw_start_8168e_2
,
3730 [RTL_GIGA_MAC_VER_35
] = rtl_hw_start_8168f_1
,
3731 [RTL_GIGA_MAC_VER_36
] = rtl_hw_start_8168f_1
,
3732 [RTL_GIGA_MAC_VER_37
] = rtl_hw_start_8402
,
3733 [RTL_GIGA_MAC_VER_38
] = rtl_hw_start_8411
,
3734 [RTL_GIGA_MAC_VER_39
] = rtl_hw_start_8106
,
3735 [RTL_GIGA_MAC_VER_40
] = rtl_hw_start_8168g_1
,
3736 [RTL_GIGA_MAC_VER_41
] = rtl_hw_start_8168g_1
,
3737 [RTL_GIGA_MAC_VER_42
] = rtl_hw_start_8168g_2
,
3738 [RTL_GIGA_MAC_VER_43
] = rtl_hw_start_8168g_2
,
3739 [RTL_GIGA_MAC_VER_44
] = rtl_hw_start_8411_2
,
3740 [RTL_GIGA_MAC_VER_45
] = rtl_hw_start_8168h_1
,
3741 [RTL_GIGA_MAC_VER_46
] = rtl_hw_start_8168h_1
,
3742 [RTL_GIGA_MAC_VER_47
] = rtl_hw_start_8168h_1
,
3743 [RTL_GIGA_MAC_VER_48
] = rtl_hw_start_8168h_1
,
3744 [RTL_GIGA_MAC_VER_49
] = rtl_hw_start_8168ep_1
,
3745 [RTL_GIGA_MAC_VER_50
] = rtl_hw_start_8168ep_2
,
3746 [RTL_GIGA_MAC_VER_51
] = rtl_hw_start_8168ep_3
,
3747 [RTL_GIGA_MAC_VER_52
] = rtl_hw_start_8117
,
3748 [RTL_GIGA_MAC_VER_53
] = rtl_hw_start_8117
,
3749 [RTL_GIGA_MAC_VER_60
] = rtl_hw_start_8125a_1
,
3750 [RTL_GIGA_MAC_VER_61
] = rtl_hw_start_8125a_2
,
3751 [RTL_GIGA_MAC_VER_63
] = rtl_hw_start_8125b
,
3754 if (hw_configs
[tp
->mac_version
])
3755 hw_configs
[tp
->mac_version
](tp
);
3758 static void rtl_hw_start_8125(struct rtl8169_private
*tp
)
3762 /* disable interrupt coalescing */
3763 for (i
= 0xa00; i
< 0xb00; i
+= 4)
3769 static void rtl_hw_start_8168(struct rtl8169_private
*tp
)
3771 if (rtl_is_8168evl_up(tp
))
3772 RTL_W8(tp
, MaxTxPacketSize
, EarlySize
);
3774 RTL_W8(tp
, MaxTxPacketSize
, TxPacketMax
);
3778 /* disable interrupt coalescing */
3779 RTL_W16(tp
, IntrMitigate
, 0x0000);
3782 static void rtl_hw_start_8169(struct rtl8169_private
*tp
)
3784 RTL_W8(tp
, EarlyTxThres
, NoEarlyTx
);
3786 tp
->cp_cmd
|= PCIMulRW
;
3788 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
3789 tp
->mac_version
== RTL_GIGA_MAC_VER_03
)
3790 tp
->cp_cmd
|= EnAnaPLL
;
3792 RTL_W16(tp
, CPlusCmd
, tp
->cp_cmd
);
3794 rtl8169_set_magic_reg(tp
);
3796 /* disable interrupt coalescing */
3797 RTL_W16(tp
, IntrMitigate
, 0x0000);
3800 static void rtl_hw_start(struct rtl8169_private
*tp
)
3802 rtl_unlock_config_regs(tp
);
3804 RTL_W16(tp
, CPlusCmd
, tp
->cp_cmd
);
3806 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
3807 rtl_hw_start_8169(tp
);
3808 else if (rtl_is_8125(tp
))
3809 rtl_hw_start_8125(tp
);
3811 rtl_hw_start_8168(tp
);
3813 rtl_enable_exit_l1(tp
);
3814 rtl_set_rx_max_size(tp
);
3815 rtl_set_rx_tx_desc_registers(tp
);
3816 rtl_lock_config_regs(tp
);
3818 rtl_jumbo_config(tp
);
3820 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3823 RTL_W8(tp
, ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3825 rtl_set_tx_config_registers(tp
);
3826 rtl_set_rx_config_features(tp
, tp
->dev
->features
);
3827 rtl_set_rx_mode(tp
->dev
);
3831 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
3833 struct rtl8169_private
*tp
= netdev_priv(dev
);
3836 netdev_update_features(dev
);
3837 rtl_jumbo_config(tp
);
3839 switch (tp
->mac_version
) {
3840 case RTL_GIGA_MAC_VER_61
:
3841 case RTL_GIGA_MAC_VER_63
:
3842 rtl8125_set_eee_txidle_timer(tp
);
3851 static void rtl8169_mark_to_asic(struct RxDesc
*desc
)
3853 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
3856 /* Force memory writes to complete before releasing descriptor */
3858 WRITE_ONCE(desc
->opts1
, cpu_to_le32(DescOwn
| eor
| R8169_RX_BUF_SIZE
));
3861 static struct page
*rtl8169_alloc_rx_data(struct rtl8169_private
*tp
,
3862 struct RxDesc
*desc
)
3864 struct device
*d
= tp_to_dev(tp
);
3865 int node
= dev_to_node(d
);
3869 data
= alloc_pages_node(node
, GFP_KERNEL
, get_order(R8169_RX_BUF_SIZE
));
3873 mapping
= dma_map_page(d
, data
, 0, R8169_RX_BUF_SIZE
, DMA_FROM_DEVICE
);
3874 if (unlikely(dma_mapping_error(d
, mapping
))) {
3875 netdev_err(tp
->dev
, "Failed to map RX DMA!\n");
3876 __free_pages(data
, get_order(R8169_RX_BUF_SIZE
));
3880 desc
->addr
= cpu_to_le64(mapping
);
3881 rtl8169_mark_to_asic(desc
);
3886 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
3890 for (i
= 0; i
< NUM_RX_DESC
&& tp
->Rx_databuff
[i
]; i
++) {
3891 dma_unmap_page(tp_to_dev(tp
),
3892 le64_to_cpu(tp
->RxDescArray
[i
].addr
),
3893 R8169_RX_BUF_SIZE
, DMA_FROM_DEVICE
);
3894 __free_pages(tp
->Rx_databuff
[i
], get_order(R8169_RX_BUF_SIZE
));
3895 tp
->Rx_databuff
[i
] = NULL
;
3896 tp
->RxDescArray
[i
].addr
= 0;
3897 tp
->RxDescArray
[i
].opts1
= 0;
3901 static int rtl8169_rx_fill(struct rtl8169_private
*tp
)
3905 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
3908 data
= rtl8169_alloc_rx_data(tp
, tp
->RxDescArray
+ i
);
3910 rtl8169_rx_clear(tp
);
3913 tp
->Rx_databuff
[i
] = data
;
3916 /* mark as last descriptor in the ring */
3917 tp
->RxDescArray
[NUM_RX_DESC
- 1].opts1
|= cpu_to_le32(RingEnd
);
3922 static int rtl8169_init_ring(struct rtl8169_private
*tp
)
3924 rtl8169_init_ring_indexes(tp
);
3926 memset(tp
->tx_skb
, 0, sizeof(tp
->tx_skb
));
3927 memset(tp
->Rx_databuff
, 0, sizeof(tp
->Rx_databuff
));
3929 return rtl8169_rx_fill(tp
);
3932 static void rtl8169_unmap_tx_skb(struct rtl8169_private
*tp
, unsigned int entry
)
3934 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
3935 struct TxDesc
*desc
= tp
->TxDescArray
+ entry
;
3937 dma_unmap_single(tp_to_dev(tp
), le64_to_cpu(desc
->addr
), tx_skb
->len
,
3939 memset(desc
, 0, sizeof(*desc
));
3940 memset(tx_skb
, 0, sizeof(*tx_skb
));
3943 static void rtl8169_tx_clear_range(struct rtl8169_private
*tp
, u32 start
,
3948 for (i
= 0; i
< n
; i
++) {
3949 unsigned int entry
= (start
+ i
) % NUM_TX_DESC
;
3950 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
3951 unsigned int len
= tx_skb
->len
;
3954 struct sk_buff
*skb
= tx_skb
->skb
;
3956 rtl8169_unmap_tx_skb(tp
, entry
);
3958 dev_consume_skb_any(skb
);
3963 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
3965 rtl8169_tx_clear_range(tp
, tp
->dirty_tx
, NUM_TX_DESC
);
3966 netdev_reset_queue(tp
->dev
);
3969 static void rtl8169_cleanup(struct rtl8169_private
*tp
, bool going_down
)
3971 napi_disable(&tp
->napi
);
3973 /* Give a racing hard_start_xmit a few cycles to complete. */
3976 /* Disable interrupts */
3977 rtl8169_irq_mask_and_ack(tp
);
3981 if (going_down
&& tp
->dev
->wol_enabled
)
3984 switch (tp
->mac_version
) {
3985 case RTL_GIGA_MAC_VER_27
:
3986 case RTL_GIGA_MAC_VER_28
:
3987 case RTL_GIGA_MAC_VER_31
:
3988 rtl_loop_wait_low(tp
, &rtl_npq_cond
, 20, 2000);
3990 case RTL_GIGA_MAC_VER_34
... RTL_GIGA_MAC_VER_38
:
3991 RTL_W8(tp
, ChipCmd
, RTL_R8(tp
, ChipCmd
) | StopReq
);
3992 rtl_loop_wait_high(tp
, &rtl_txcfg_empty_cond
, 100, 666);
3994 case RTL_GIGA_MAC_VER_40
... RTL_GIGA_MAC_VER_63
:
3995 rtl_enable_rxdvgate(tp
);
3999 RTL_W8(tp
, ChipCmd
, RTL_R8(tp
, ChipCmd
) | StopReq
);
4006 rtl8169_tx_clear(tp
);
4007 rtl8169_init_ring_indexes(tp
);
4010 static void rtl_reset_work(struct rtl8169_private
*tp
)
4014 netif_stop_queue(tp
->dev
);
4016 rtl8169_cleanup(tp
, false);
4018 for (i
= 0; i
< NUM_RX_DESC
; i
++)
4019 rtl8169_mark_to_asic(tp
->RxDescArray
+ i
);
4021 napi_enable(&tp
->napi
);
4025 static void rtl8169_tx_timeout(struct net_device
*dev
, unsigned int txqueue
)
4027 struct rtl8169_private
*tp
= netdev_priv(dev
);
4029 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
4032 static int rtl8169_tx_map(struct rtl8169_private
*tp
, const u32
*opts
, u32 len
,
4033 void *addr
, unsigned int entry
, bool desc_own
)
4035 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
4036 struct device
*d
= tp_to_dev(tp
);
4041 mapping
= dma_map_single(d
, addr
, len
, DMA_TO_DEVICE
);
4042 ret
= dma_mapping_error(d
, mapping
);
4043 if (unlikely(ret
)) {
4044 if (net_ratelimit())
4045 netdev_err(tp
->dev
, "Failed to map TX data!\n");
4049 txd
->addr
= cpu_to_le64(mapping
);
4050 txd
->opts2
= cpu_to_le32(opts
[1]);
4052 opts1
= opts
[0] | len
;
4053 if (entry
== NUM_TX_DESC
- 1)
4057 txd
->opts1
= cpu_to_le32(opts1
);
4059 tp
->tx_skb
[entry
].len
= len
;
4064 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
4065 const u32
*opts
, unsigned int entry
)
4067 struct skb_shared_info
*info
= skb_shinfo(skb
);
4068 unsigned int cur_frag
;
4070 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
4071 const skb_frag_t
*frag
= info
->frags
+ cur_frag
;
4072 void *addr
= skb_frag_address(frag
);
4073 u32 len
= skb_frag_size(frag
);
4075 entry
= (entry
+ 1) % NUM_TX_DESC
;
4077 if (unlikely(rtl8169_tx_map(tp
, opts
, len
, addr
, entry
, true)))
4084 rtl8169_tx_clear_range(tp
, tp
->cur_tx
+ 1, cur_frag
);
4088 static bool rtl_skb_is_udp(struct sk_buff
*skb
)
4090 int no
= skb_network_offset(skb
);
4091 struct ipv6hdr
*i6h
, _i6h
;
4092 struct iphdr
*ih
, _ih
;
4094 switch (vlan_get_protocol(skb
)) {
4095 case htons(ETH_P_IP
):
4096 ih
= skb_header_pointer(skb
, no
, sizeof(_ih
), &_ih
);
4097 return ih
&& ih
->protocol
== IPPROTO_UDP
;
4098 case htons(ETH_P_IPV6
):
4099 i6h
= skb_header_pointer(skb
, no
, sizeof(_i6h
), &_i6h
);
4100 return i6h
&& i6h
->nexthdr
== IPPROTO_UDP
;
4106 #define RTL_MIN_PATCH_LEN 47
4108 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */
4109 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private
*tp
,
4110 struct sk_buff
*skb
)
4112 unsigned int padto
= 0, len
= skb
->len
;
4114 if (rtl_is_8125(tp
) && len
< 128 + RTL_MIN_PATCH_LEN
&&
4115 rtl_skb_is_udp(skb
) && skb_transport_header_was_set(skb
)) {
4116 unsigned int trans_data_len
= skb_tail_pointer(skb
) -
4117 skb_transport_header(skb
);
4119 if (trans_data_len
>= offsetof(struct udphdr
, len
) &&
4120 trans_data_len
< RTL_MIN_PATCH_LEN
) {
4121 u16 dest
= ntohs(udp_hdr(skb
)->dest
);
4123 /* dest is a standard PTP port */
4124 if (dest
== 319 || dest
== 320)
4125 padto
= len
+ RTL_MIN_PATCH_LEN
- trans_data_len
;
4128 if (trans_data_len
< sizeof(struct udphdr
))
4129 padto
= max_t(unsigned int, padto
,
4130 len
+ sizeof(struct udphdr
) - trans_data_len
);
4136 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private
*tp
,
4137 struct sk_buff
*skb
)
4141 padto
= rtl8125_quirk_udp_padto(tp
, skb
);
4143 switch (tp
->mac_version
) {
4144 case RTL_GIGA_MAC_VER_34
:
4145 case RTL_GIGA_MAC_VER_60
:
4146 case RTL_GIGA_MAC_VER_61
:
4147 case RTL_GIGA_MAC_VER_63
:
4148 padto
= max_t(unsigned int, padto
, ETH_ZLEN
);
4157 static void rtl8169_tso_csum_v1(struct sk_buff
*skb
, u32
*opts
)
4159 u32 mss
= skb_shinfo(skb
)->gso_size
;
4163 opts
[0] |= mss
<< TD0_MSS_SHIFT
;
4164 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
4165 const struct iphdr
*ip
= ip_hdr(skb
);
4167 if (ip
->protocol
== IPPROTO_TCP
)
4168 opts
[0] |= TD0_IP_CS
| TD0_TCP_CS
;
4169 else if (ip
->protocol
== IPPROTO_UDP
)
4170 opts
[0] |= TD0_IP_CS
| TD0_UDP_CS
;
4176 static bool rtl8169_tso_csum_v2(struct rtl8169_private
*tp
,
4177 struct sk_buff
*skb
, u32
*opts
)
4179 u32 transport_offset
= (u32
)skb_transport_offset(skb
);
4180 struct skb_shared_info
*shinfo
= skb_shinfo(skb
);
4181 u32 mss
= shinfo
->gso_size
;
4184 if (shinfo
->gso_type
& SKB_GSO_TCPV4
) {
4185 opts
[0] |= TD1_GTSENV4
;
4186 } else if (shinfo
->gso_type
& SKB_GSO_TCPV6
) {
4187 if (skb_cow_head(skb
, 0))
4190 tcp_v6_gso_csum_prep(skb
);
4191 opts
[0] |= TD1_GTSENV6
;
4196 opts
[0] |= transport_offset
<< GTTCPHO_SHIFT
;
4197 opts
[1] |= mss
<< TD1_MSS_SHIFT
;
4198 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
4201 switch (vlan_get_protocol(skb
)) {
4202 case htons(ETH_P_IP
):
4203 opts
[1] |= TD1_IPv4_CS
;
4204 ip_protocol
= ip_hdr(skb
)->protocol
;
4207 case htons(ETH_P_IPV6
):
4208 opts
[1] |= TD1_IPv6_CS
;
4209 ip_protocol
= ipv6_hdr(skb
)->nexthdr
;
4213 ip_protocol
= IPPROTO_RAW
;
4217 if (ip_protocol
== IPPROTO_TCP
)
4218 opts
[1] |= TD1_TCP_CS
;
4219 else if (ip_protocol
== IPPROTO_UDP
)
4220 opts
[1] |= TD1_UDP_CS
;
4224 opts
[1] |= transport_offset
<< TCPHO_SHIFT
;
4226 unsigned int padto
= rtl_quirk_packet_padto(tp
, skb
);
4228 /* skb_padto would free the skb on error */
4229 return !__skb_put_padto(skb
, padto
, false);
4235 static bool rtl_tx_slots_avail(struct rtl8169_private
*tp
)
4237 unsigned int slots_avail
= READ_ONCE(tp
->dirty_tx
) + NUM_TX_DESC
4238 - READ_ONCE(tp
->cur_tx
);
4240 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
4241 return slots_avail
> MAX_SKB_FRAGS
;
4244 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
4245 static bool rtl_chip_supports_csum_v2(struct rtl8169_private
*tp
)
4247 switch (tp
->mac_version
) {
4248 case RTL_GIGA_MAC_VER_02
... RTL_GIGA_MAC_VER_06
:
4249 case RTL_GIGA_MAC_VER_10
... RTL_GIGA_MAC_VER_17
:
4256 static void rtl8169_doorbell(struct rtl8169_private
*tp
)
4258 if (rtl_is_8125(tp
))
4259 RTL_W16(tp
, TxPoll_8125
, BIT(0));
4261 RTL_W8(tp
, TxPoll
, NPQ
);
4264 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
4265 struct net_device
*dev
)
4267 unsigned int frags
= skb_shinfo(skb
)->nr_frags
;
4268 struct rtl8169_private
*tp
= netdev_priv(dev
);
4269 unsigned int entry
= tp
->cur_tx
% NUM_TX_DESC
;
4270 struct TxDesc
*txd_first
, *txd_last
;
4271 bool stop_queue
, door_bell
;
4274 if (unlikely(!rtl_tx_slots_avail(tp
))) {
4275 if (net_ratelimit())
4276 netdev_err(dev
, "BUG! Tx Ring full when queue awake!\n");
4280 opts
[1] = rtl8169_tx_vlan_tag(skb
);
4283 if (!rtl_chip_supports_csum_v2(tp
))
4284 rtl8169_tso_csum_v1(skb
, opts
);
4285 else if (!rtl8169_tso_csum_v2(tp
, skb
, opts
))
4288 if (unlikely(rtl8169_tx_map(tp
, opts
, skb_headlen(skb
), skb
->data
,
4292 txd_first
= tp
->TxDescArray
+ entry
;
4295 if (rtl8169_xmit_frags(tp
, skb
, opts
, entry
))
4297 entry
= (entry
+ frags
) % NUM_TX_DESC
;
4300 txd_last
= tp
->TxDescArray
+ entry
;
4301 txd_last
->opts1
|= cpu_to_le32(LastFrag
);
4302 tp
->tx_skb
[entry
].skb
= skb
;
4304 skb_tx_timestamp(skb
);
4306 /* Force memory writes to complete before releasing descriptor */
4309 door_bell
= __netdev_sent_queue(dev
, skb
->len
, netdev_xmit_more());
4311 txd_first
->opts1
|= cpu_to_le32(DescOwn
| FirstFrag
);
4313 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */
4316 WRITE_ONCE(tp
->cur_tx
, tp
->cur_tx
+ frags
+ 1);
4318 stop_queue
= !rtl_tx_slots_avail(tp
);
4319 if (unlikely(stop_queue
)) {
4320 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
4321 * not miss a ring update when it notices a stopped queue.
4324 netif_stop_queue(dev
);
4325 /* Sync with rtl_tx:
4326 * - publish queue status and cur_tx ring index (write barrier)
4327 * - refresh dirty_tx ring index (read barrier).
4328 * May the current thread have a pessimistic view of the ring
4329 * status and forget to wake up queue, a racing rtl_tx thread
4332 smp_mb__after_atomic();
4333 if (rtl_tx_slots_avail(tp
))
4334 netif_start_queue(dev
);
4339 rtl8169_doorbell(tp
);
4341 return NETDEV_TX_OK
;
4344 rtl8169_unmap_tx_skb(tp
, entry
);
4346 dev_kfree_skb_any(skb
);
4347 dev
->stats
.tx_dropped
++;
4348 return NETDEV_TX_OK
;
4351 netif_stop_queue(dev
);
4352 dev
->stats
.tx_dropped
++;
4353 return NETDEV_TX_BUSY
;
4356 static unsigned int rtl_last_frag_len(struct sk_buff
*skb
)
4358 struct skb_shared_info
*info
= skb_shinfo(skb
);
4359 unsigned int nr_frags
= info
->nr_frags
;
4364 return skb_frag_size(info
->frags
+ nr_frags
- 1);
4367 /* Workaround for hw issues with TSO on RTL8168evl */
4368 static netdev_features_t
rtl8168evl_fix_tso(struct sk_buff
*skb
,
4369 netdev_features_t features
)
4371 /* IPv4 header has options field */
4372 if (vlan_get_protocol(skb
) == htons(ETH_P_IP
) &&
4373 ip_hdrlen(skb
) > sizeof(struct iphdr
))
4374 features
&= ~NETIF_F_ALL_TSO
;
4376 /* IPv4 TCP header has options field */
4377 else if (skb_shinfo(skb
)->gso_type
& SKB_GSO_TCPV4
&&
4378 tcp_hdrlen(skb
) > sizeof(struct tcphdr
))
4379 features
&= ~NETIF_F_ALL_TSO
;
4381 else if (rtl_last_frag_len(skb
) <= 6)
4382 features
&= ~NETIF_F_ALL_TSO
;
4387 static netdev_features_t
rtl8169_features_check(struct sk_buff
*skb
,
4388 struct net_device
*dev
,
4389 netdev_features_t features
)
4391 int transport_offset
= skb_transport_offset(skb
);
4392 struct rtl8169_private
*tp
= netdev_priv(dev
);
4394 if (skb_is_gso(skb
)) {
4395 if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
)
4396 features
= rtl8168evl_fix_tso(skb
, features
);
4398 if (transport_offset
> GTTCPHO_MAX
&&
4399 rtl_chip_supports_csum_v2(tp
))
4400 features
&= ~NETIF_F_ALL_TSO
;
4401 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
4402 /* work around hw bug on some chip versions */
4403 if (skb
->len
< ETH_ZLEN
)
4404 features
&= ~NETIF_F_CSUM_MASK
;
4406 if (rtl_quirk_packet_padto(tp
, skb
))
4407 features
&= ~NETIF_F_CSUM_MASK
;
4409 if (transport_offset
> TCPHO_MAX
&&
4410 rtl_chip_supports_csum_v2(tp
))
4411 features
&= ~NETIF_F_CSUM_MASK
;
4414 return vlan_features_check(skb
, features
);
4417 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
4419 struct rtl8169_private
*tp
= netdev_priv(dev
);
4420 struct pci_dev
*pdev
= tp
->pci_dev
;
4421 int pci_status_errs
;
4424 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
4426 pci_status_errs
= pci_status_get_and_clear_errors(pdev
);
4428 if (net_ratelimit())
4429 netdev_err(dev
, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n",
4430 pci_cmd
, pci_status_errs
);
4432 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
4435 static void rtl_tx(struct net_device
*dev
, struct rtl8169_private
*tp
,
4438 unsigned int dirty_tx
, bytes_compl
= 0, pkts_compl
= 0;
4439 struct sk_buff
*skb
;
4441 dirty_tx
= tp
->dirty_tx
;
4443 while (READ_ONCE(tp
->cur_tx
) != dirty_tx
) {
4444 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
4447 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
4448 if (status
& DescOwn
)
4451 skb
= tp
->tx_skb
[entry
].skb
;
4452 rtl8169_unmap_tx_skb(tp
, entry
);
4456 bytes_compl
+= skb
->len
;
4457 napi_consume_skb(skb
, budget
);
4462 if (tp
->dirty_tx
!= dirty_tx
) {
4463 netdev_completed_queue(dev
, pkts_compl
, bytes_compl
);
4464 dev_sw_netstats_tx_add(dev
, pkts_compl
, bytes_compl
);
4466 /* Sync with rtl8169_start_xmit:
4467 * - publish dirty_tx ring index (write barrier)
4468 * - refresh cur_tx ring index and queue status (read barrier)
4469 * May the current thread miss the stopped queue condition,
4470 * a racing xmit thread can only have a right view of the
4473 smp_store_mb(tp
->dirty_tx
, dirty_tx
);
4474 if (netif_queue_stopped(dev
) && rtl_tx_slots_avail(tp
))
4475 netif_wake_queue(dev
);
4477 * 8168 hack: TxPoll requests are lost when the Tx packets are
4478 * too close. Let's kick an extra TxPoll request when a burst
4479 * of start_xmit activity is detected (if it is not detected,
4480 * it is slow enough). -- FR
4481 * If skb is NULL then we come here again once a tx irq is
4482 * triggered after the last fragment is marked transmitted.
4484 if (tp
->cur_tx
!= dirty_tx
&& skb
)
4485 rtl8169_doorbell(tp
);
4489 static inline int rtl8169_fragmented_frame(u32 status
)
4491 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
4494 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, u32 opts1
)
4496 u32 status
= opts1
& (RxProtoMask
| RxCSFailMask
);
4498 if (status
== RxProtoTCP
|| status
== RxProtoUDP
)
4499 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
4501 skb_checksum_none_assert(skb
);
4504 static int rtl_rx(struct net_device
*dev
, struct rtl8169_private
*tp
, int budget
)
4506 struct device
*d
= tp_to_dev(tp
);
4509 for (count
= 0; count
< budget
; count
++, tp
->cur_rx
++) {
4510 unsigned int pkt_size
, entry
= tp
->cur_rx
% NUM_RX_DESC
;
4511 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
4512 struct sk_buff
*skb
;
4517 status
= le32_to_cpu(desc
->opts1
);
4518 if (status
& DescOwn
)
4521 /* This barrier is needed to keep us from reading
4522 * any other fields out of the Rx descriptor until
4523 * we know the status of DescOwn
4527 if (unlikely(status
& RxRES
)) {
4528 if (net_ratelimit())
4529 netdev_warn(dev
, "Rx ERROR. status = %08x\n",
4531 dev
->stats
.rx_errors
++;
4532 if (status
& (RxRWT
| RxRUNT
))
4533 dev
->stats
.rx_length_errors
++;
4535 dev
->stats
.rx_crc_errors
++;
4537 if (!(dev
->features
& NETIF_F_RXALL
))
4538 goto release_descriptor
;
4539 else if (status
& RxRWT
|| !(status
& (RxRUNT
| RxCRC
)))
4540 goto release_descriptor
;
4543 pkt_size
= status
& GENMASK(13, 0);
4544 if (likely(!(dev
->features
& NETIF_F_RXFCS
)))
4545 pkt_size
-= ETH_FCS_LEN
;
4547 /* The driver does not support incoming fragmented frames.
4548 * They are seen as a symptom of over-mtu sized frames.
4550 if (unlikely(rtl8169_fragmented_frame(status
))) {
4551 dev
->stats
.rx_dropped
++;
4552 dev
->stats
.rx_length_errors
++;
4553 goto release_descriptor
;
4556 skb
= napi_alloc_skb(&tp
->napi
, pkt_size
);
4557 if (unlikely(!skb
)) {
4558 dev
->stats
.rx_dropped
++;
4559 goto release_descriptor
;
4562 addr
= le64_to_cpu(desc
->addr
);
4563 rx_buf
= page_address(tp
->Rx_databuff
[entry
]);
4565 dma_sync_single_for_cpu(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
4567 skb_copy_to_linear_data(skb
, rx_buf
, pkt_size
);
4568 skb
->tail
+= pkt_size
;
4569 skb
->len
= pkt_size
;
4570 dma_sync_single_for_device(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
4572 rtl8169_rx_csum(skb
, status
);
4573 skb
->protocol
= eth_type_trans(skb
, dev
);
4575 rtl8169_rx_vlan_tag(desc
, skb
);
4577 if (skb
->pkt_type
== PACKET_MULTICAST
)
4578 dev
->stats
.multicast
++;
4580 napi_gro_receive(&tp
->napi
, skb
);
4582 dev_sw_netstats_rx_add(dev
, pkt_size
);
4584 rtl8169_mark_to_asic(desc
);
4590 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
4592 struct rtl8169_private
*tp
= dev_instance
;
4593 u32 status
= rtl_get_events(tp
);
4595 if ((status
& 0xffff) == 0xffff || !(status
& tp
->irq_mask
))
4598 if (unlikely(status
& SYSErr
)) {
4599 rtl8169_pcierr_interrupt(tp
->dev
);
4603 if (status
& LinkChg
)
4604 phy_mac_interrupt(tp
->phydev
);
4606 if (unlikely(status
& RxFIFOOver
&&
4607 tp
->mac_version
== RTL_GIGA_MAC_VER_11
)) {
4608 netif_stop_queue(tp
->dev
);
4609 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
4612 if (napi_schedule_prep(&tp
->napi
)) {
4613 rtl_irq_disable(tp
);
4614 __napi_schedule(&tp
->napi
);
4617 rtl_ack_events(tp
, status
);
4622 static void rtl_task(struct work_struct
*work
)
4624 struct rtl8169_private
*tp
=
4625 container_of(work
, struct rtl8169_private
, wk
.work
);
4629 if (!netif_running(tp
->dev
) ||
4630 !test_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
))
4633 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING
, tp
->wk
.flags
)) {
4635 netif_wake_queue(tp
->dev
);
4641 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
4643 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
4644 struct net_device
*dev
= tp
->dev
;
4647 rtl_tx(dev
, tp
, budget
);
4649 work_done
= rtl_rx(dev
, tp
, budget
);
4651 if (work_done
< budget
&& napi_complete_done(napi
, work_done
))
4657 static void r8169_phylink_handler(struct net_device
*ndev
)
4659 struct rtl8169_private
*tp
= netdev_priv(ndev
);
4661 if (netif_carrier_ok(ndev
)) {
4662 rtl_link_chg_patch(tp
);
4663 pm_request_resume(&tp
->pci_dev
->dev
);
4665 pm_runtime_idle(&tp
->pci_dev
->dev
);
4668 if (net_ratelimit())
4669 phy_print_status(tp
->phydev
);
4672 static int r8169_phy_connect(struct rtl8169_private
*tp
)
4674 struct phy_device
*phydev
= tp
->phydev
;
4675 phy_interface_t phy_mode
;
4678 phy_mode
= tp
->supports_gmii
? PHY_INTERFACE_MODE_GMII
:
4679 PHY_INTERFACE_MODE_MII
;
4681 ret
= phy_connect_direct(tp
->dev
, phydev
, r8169_phylink_handler
,
4686 if (!tp
->supports_gmii
)
4687 phy_set_max_speed(phydev
, SPEED_100
);
4689 phy_attached_info(phydev
);
4694 static void rtl8169_down(struct rtl8169_private
*tp
)
4696 /* Clear all task flags */
4697 bitmap_zero(tp
->wk
.flags
, RTL_FLAG_MAX
);
4699 phy_stop(tp
->phydev
);
4701 rtl8169_update_counters(tp
);
4703 pci_clear_master(tp
->pci_dev
);
4706 rtl8169_cleanup(tp
, true);
4708 rtl_prepare_power_down(tp
);
4711 static void rtl8169_up(struct rtl8169_private
*tp
)
4713 pci_set_master(tp
->pci_dev
);
4714 phy_init_hw(tp
->phydev
);
4715 phy_resume(tp
->phydev
);
4716 rtl8169_init_phy(tp
);
4717 napi_enable(&tp
->napi
);
4718 set_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
4721 phy_start(tp
->phydev
);
4724 static int rtl8169_close(struct net_device
*dev
)
4726 struct rtl8169_private
*tp
= netdev_priv(dev
);
4727 struct pci_dev
*pdev
= tp
->pci_dev
;
4729 pm_runtime_get_sync(&pdev
->dev
);
4731 netif_stop_queue(dev
);
4733 rtl8169_rx_clear(tp
);
4735 cancel_work_sync(&tp
->wk
.work
);
4737 free_irq(pci_irq_vector(pdev
, 0), tp
);
4739 phy_disconnect(tp
->phydev
);
4741 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
4743 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
4745 tp
->TxDescArray
= NULL
;
4746 tp
->RxDescArray
= NULL
;
4748 pm_runtime_put_sync(&pdev
->dev
);
4753 #ifdef CONFIG_NET_POLL_CONTROLLER
4754 static void rtl8169_netpoll(struct net_device
*dev
)
4756 struct rtl8169_private
*tp
= netdev_priv(dev
);
4758 rtl8169_interrupt(pci_irq_vector(tp
->pci_dev
, 0), tp
);
4762 static int rtl_open(struct net_device
*dev
)
4764 struct rtl8169_private
*tp
= netdev_priv(dev
);
4765 struct pci_dev
*pdev
= tp
->pci_dev
;
4766 unsigned long irqflags
;
4767 int retval
= -ENOMEM
;
4769 pm_runtime_get_sync(&pdev
->dev
);
4772 * Rx and Tx descriptors needs 256 bytes alignment.
4773 * dma_alloc_coherent provides more.
4775 tp
->TxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
,
4776 &tp
->TxPhyAddr
, GFP_KERNEL
);
4777 if (!tp
->TxDescArray
)
4780 tp
->RxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
,
4781 &tp
->RxPhyAddr
, GFP_KERNEL
);
4782 if (!tp
->RxDescArray
)
4785 retval
= rtl8169_init_ring(tp
);
4789 rtl_request_firmware(tp
);
4791 irqflags
= pci_dev_msi_enabled(pdev
) ? IRQF_NO_THREAD
: IRQF_SHARED
;
4792 retval
= request_irq(pci_irq_vector(pdev
, 0), rtl8169_interrupt
,
4793 irqflags
, dev
->name
, tp
);
4795 goto err_release_fw_2
;
4797 retval
= r8169_phy_connect(tp
);
4802 rtl8169_init_counter_offsets(tp
);
4803 netif_start_queue(dev
);
4805 pm_runtime_put_sync(&pdev
->dev
);
4810 free_irq(pci_irq_vector(pdev
, 0), tp
);
4812 rtl_release_firmware(tp
);
4813 rtl8169_rx_clear(tp
);
4815 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
4817 tp
->RxDescArray
= NULL
;
4819 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
4821 tp
->TxDescArray
= NULL
;
4826 rtl8169_get_stats64(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
4828 struct rtl8169_private
*tp
= netdev_priv(dev
);
4829 struct pci_dev
*pdev
= tp
->pci_dev
;
4830 struct rtl8169_counters
*counters
= tp
->counters
;
4832 pm_runtime_get_noresume(&pdev
->dev
);
4834 netdev_stats_to_stats64(stats
, &dev
->stats
);
4835 dev_fetch_sw_netstats(stats
, dev
->tstats
);
4838 * Fetch additional counter values missing in stats collected by driver
4839 * from tally counters.
4841 if (pm_runtime_active(&pdev
->dev
))
4842 rtl8169_update_counters(tp
);
4845 * Subtract values fetched during initalization.
4846 * See rtl8169_init_counter_offsets for a description why we do that.
4848 stats
->tx_errors
= le64_to_cpu(counters
->tx_errors
) -
4849 le64_to_cpu(tp
->tc_offset
.tx_errors
);
4850 stats
->collisions
= le32_to_cpu(counters
->tx_multi_collision
) -
4851 le32_to_cpu(tp
->tc_offset
.tx_multi_collision
);
4852 stats
->tx_aborted_errors
= le16_to_cpu(counters
->tx_aborted
) -
4853 le16_to_cpu(tp
->tc_offset
.tx_aborted
);
4854 stats
->rx_missed_errors
= le16_to_cpu(counters
->rx_missed
) -
4855 le16_to_cpu(tp
->tc_offset
.rx_missed
);
4857 pm_runtime_put_noidle(&pdev
->dev
);
4860 static void rtl8169_net_suspend(struct rtl8169_private
*tp
)
4862 netif_device_detach(tp
->dev
);
4864 if (netif_running(tp
->dev
))
4870 static int rtl8169_runtime_resume(struct device
*dev
)
4872 struct rtl8169_private
*tp
= dev_get_drvdata(dev
);
4874 rtl_rar_set(tp
, tp
->dev
->dev_addr
);
4875 __rtl8169_set_wol(tp
, tp
->saved_wolopts
);
4877 if (tp
->TxDescArray
)
4880 netif_device_attach(tp
->dev
);
4885 static int __maybe_unused
rtl8169_suspend(struct device
*device
)
4887 struct rtl8169_private
*tp
= dev_get_drvdata(device
);
4890 rtl8169_net_suspend(tp
);
4891 if (!device_may_wakeup(tp_to_dev(tp
)))
4892 clk_disable_unprepare(tp
->clk
);
4898 static int __maybe_unused
rtl8169_resume(struct device
*device
)
4900 struct rtl8169_private
*tp
= dev_get_drvdata(device
);
4902 if (!device_may_wakeup(tp_to_dev(tp
)))
4903 clk_prepare_enable(tp
->clk
);
4905 /* Reportedly at least Asus X453MA truncates packets otherwise */
4906 if (tp
->mac_version
== RTL_GIGA_MAC_VER_37
)
4909 return rtl8169_runtime_resume(device
);
4912 static int rtl8169_runtime_suspend(struct device
*device
)
4914 struct rtl8169_private
*tp
= dev_get_drvdata(device
);
4916 if (!tp
->TxDescArray
) {
4917 netif_device_detach(tp
->dev
);
4922 __rtl8169_set_wol(tp
, WAKE_PHY
);
4923 rtl8169_net_suspend(tp
);
4929 static int rtl8169_runtime_idle(struct device
*device
)
4931 struct rtl8169_private
*tp
= dev_get_drvdata(device
);
4933 if (!netif_running(tp
->dev
) || !netif_carrier_ok(tp
->dev
))
4934 pm_schedule_suspend(device
, 10000);
4939 static const struct dev_pm_ops rtl8169_pm_ops
= {
4940 SET_SYSTEM_SLEEP_PM_OPS(rtl8169_suspend
, rtl8169_resume
)
4941 SET_RUNTIME_PM_OPS(rtl8169_runtime_suspend
, rtl8169_runtime_resume
,
4942 rtl8169_runtime_idle
)
4945 #endif /* CONFIG_PM */
4947 static void rtl_wol_shutdown_quirk(struct rtl8169_private
*tp
)
4949 /* WoL fails with 8168b when the receiver is disabled. */
4950 switch (tp
->mac_version
) {
4951 case RTL_GIGA_MAC_VER_11
:
4952 case RTL_GIGA_MAC_VER_12
:
4953 case RTL_GIGA_MAC_VER_17
:
4954 pci_clear_master(tp
->pci_dev
);
4956 RTL_W8(tp
, ChipCmd
, CmdRxEnb
);
4964 static void rtl_shutdown(struct pci_dev
*pdev
)
4966 struct rtl8169_private
*tp
= pci_get_drvdata(pdev
);
4969 rtl8169_net_suspend(tp
);
4972 /* Restore original MAC address */
4973 rtl_rar_set(tp
, tp
->dev
->perm_addr
);
4975 if (system_state
== SYSTEM_POWER_OFF
) {
4976 if (tp
->saved_wolopts
)
4977 rtl_wol_shutdown_quirk(tp
);
4979 pci_wake_from_d3(pdev
, tp
->saved_wolopts
);
4980 pci_set_power_state(pdev
, PCI_D3hot
);
4984 static void rtl_remove_one(struct pci_dev
*pdev
)
4986 struct rtl8169_private
*tp
= pci_get_drvdata(pdev
);
4988 if (pci_dev_run_wake(pdev
))
4989 pm_runtime_get_noresume(&pdev
->dev
);
4991 unregister_netdev(tp
->dev
);
4993 if (tp
->dash_type
!= RTL_DASH_NONE
)
4994 rtl8168_driver_stop(tp
);
4996 rtl_release_firmware(tp
);
4998 /* restore original MAC address */
4999 rtl_rar_set(tp
, tp
->dev
->perm_addr
);
5002 static const struct net_device_ops rtl_netdev_ops
= {
5003 .ndo_open
= rtl_open
,
5004 .ndo_stop
= rtl8169_close
,
5005 .ndo_get_stats64
= rtl8169_get_stats64
,
5006 .ndo_start_xmit
= rtl8169_start_xmit
,
5007 .ndo_features_check
= rtl8169_features_check
,
5008 .ndo_tx_timeout
= rtl8169_tx_timeout
,
5009 .ndo_validate_addr
= eth_validate_addr
,
5010 .ndo_change_mtu
= rtl8169_change_mtu
,
5011 .ndo_fix_features
= rtl8169_fix_features
,
5012 .ndo_set_features
= rtl8169_set_features
,
5013 .ndo_set_mac_address
= rtl_set_mac_address
,
5014 .ndo_eth_ioctl
= phy_do_ioctl_running
,
5015 .ndo_set_rx_mode
= rtl_set_rx_mode
,
5016 #ifdef CONFIG_NET_POLL_CONTROLLER
5017 .ndo_poll_controller
= rtl8169_netpoll
,
5022 static void rtl_set_irq_mask(struct rtl8169_private
*tp
)
5024 tp
->irq_mask
= RxOK
| RxErr
| TxOK
| TxErr
| LinkChg
;
5026 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
5027 tp
->irq_mask
|= SYSErr
| RxOverflow
| RxFIFOOver
;
5028 else if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
)
5029 /* special workaround needed */
5030 tp
->irq_mask
|= RxFIFOOver
;
5032 tp
->irq_mask
|= RxOverflow
;
5035 static int rtl_alloc_irq(struct rtl8169_private
*tp
)
5039 switch (tp
->mac_version
) {
5040 case RTL_GIGA_MAC_VER_02
... RTL_GIGA_MAC_VER_06
:
5041 rtl_unlock_config_regs(tp
);
5042 RTL_W8(tp
, Config2
, RTL_R8(tp
, Config2
) & ~MSIEnable
);
5043 rtl_lock_config_regs(tp
);
5045 case RTL_GIGA_MAC_VER_07
... RTL_GIGA_MAC_VER_17
:
5046 flags
= PCI_IRQ_LEGACY
;
5049 flags
= PCI_IRQ_ALL_TYPES
;
5053 return pci_alloc_irq_vectors(tp
->pci_dev
, 1, 1, flags
);
5056 static void rtl_read_mac_address(struct rtl8169_private
*tp
,
5057 u8 mac_addr
[ETH_ALEN
])
5059 /* Get MAC address */
5060 if (rtl_is_8168evl_up(tp
) && tp
->mac_version
!= RTL_GIGA_MAC_VER_34
) {
5063 value
= rtl_eri_read(tp
, 0xe0);
5064 put_unaligned_le32(value
, mac_addr
);
5065 value
= rtl_eri_read(tp
, 0xe4);
5066 put_unaligned_le16(value
, mac_addr
+ 4);
5067 } else if (rtl_is_8125(tp
)) {
5068 rtl_read_mac_from_reg(tp
, mac_addr
, MAC0_BKP
);
5072 DECLARE_RTL_COND(rtl_link_list_ready_cond
)
5074 return RTL_R8(tp
, MCU
) & LINK_LIST_RDY
;
5077 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private
*tp
)
5079 rtl_loop_wait_high(tp
, &rtl_link_list_ready_cond
, 100, 42);
5082 static int r8169_mdio_read_reg(struct mii_bus
*mii_bus
, int phyaddr
, int phyreg
)
5084 struct rtl8169_private
*tp
= mii_bus
->priv
;
5089 return rtl_readphy(tp
, phyreg
);
5092 static int r8169_mdio_write_reg(struct mii_bus
*mii_bus
, int phyaddr
,
5093 int phyreg
, u16 val
)
5095 struct rtl8169_private
*tp
= mii_bus
->priv
;
5100 rtl_writephy(tp
, phyreg
, val
);
5105 static int r8169_mdio_register(struct rtl8169_private
*tp
)
5107 struct pci_dev
*pdev
= tp
->pci_dev
;
5108 struct mii_bus
*new_bus
;
5111 new_bus
= devm_mdiobus_alloc(&pdev
->dev
);
5115 new_bus
->name
= "r8169";
5117 new_bus
->parent
= &pdev
->dev
;
5118 new_bus
->irq
[0] = PHY_MAC_INTERRUPT
;
5119 snprintf(new_bus
->id
, MII_BUS_ID_SIZE
, "r8169-%x-%x",
5120 pci_domain_nr(pdev
->bus
), pci_dev_id(pdev
));
5122 new_bus
->read
= r8169_mdio_read_reg
;
5123 new_bus
->write
= r8169_mdio_write_reg
;
5125 ret
= devm_mdiobus_register(&pdev
->dev
, new_bus
);
5129 tp
->phydev
= mdiobus_get_phy(new_bus
, 0);
5132 } else if (!tp
->phydev
->drv
) {
5133 /* Most chip versions fail with the genphy driver.
5134 * Therefore ensure that the dedicated PHY driver is loaded.
5136 dev_err(&pdev
->dev
, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n",
5137 tp
->phydev
->phy_id
);
5141 tp
->phydev
->mac_managed_pm
= 1;
5143 phy_support_asym_pause(tp
->phydev
);
5145 /* PHY will be woken up in rtl_open() */
5146 phy_suspend(tp
->phydev
);
5151 static void rtl_hw_init_8168g(struct rtl8169_private
*tp
)
5153 rtl_enable_rxdvgate(tp
);
5155 RTL_W8(tp
, ChipCmd
, RTL_R8(tp
, ChipCmd
) & ~(CmdTxEnb
| CmdRxEnb
));
5157 RTL_W8(tp
, MCU
, RTL_R8(tp
, MCU
) & ~NOW_IS_OOB
);
5159 r8168_mac_ocp_modify(tp
, 0xe8de, BIT(14), 0);
5160 r8168g_wait_ll_share_fifo_ready(tp
);
5162 r8168_mac_ocp_modify(tp
, 0xe8de, 0, BIT(15));
5163 r8168g_wait_ll_share_fifo_ready(tp
);
5166 static void rtl_hw_init_8125(struct rtl8169_private
*tp
)
5168 rtl_enable_rxdvgate(tp
);
5170 RTL_W8(tp
, ChipCmd
, RTL_R8(tp
, ChipCmd
) & ~(CmdTxEnb
| CmdRxEnb
));
5172 RTL_W8(tp
, MCU
, RTL_R8(tp
, MCU
) & ~NOW_IS_OOB
);
5174 r8168_mac_ocp_modify(tp
, 0xe8de, BIT(14), 0);
5175 r8168g_wait_ll_share_fifo_ready(tp
);
5177 r8168_mac_ocp_write(tp
, 0xc0aa, 0x07d0);
5178 r8168_mac_ocp_write(tp
, 0xc0a6, 0x0150);
5179 r8168_mac_ocp_write(tp
, 0xc01e, 0x5555);
5180 r8168g_wait_ll_share_fifo_ready(tp
);
5183 static void rtl_hw_initialize(struct rtl8169_private
*tp
)
5185 switch (tp
->mac_version
) {
5186 case RTL_GIGA_MAC_VER_49
... RTL_GIGA_MAC_VER_53
:
5187 rtl8168ep_stop_cmac(tp
);
5189 case RTL_GIGA_MAC_VER_40
... RTL_GIGA_MAC_VER_48
:
5190 rtl_hw_init_8168g(tp
);
5192 case RTL_GIGA_MAC_VER_60
... RTL_GIGA_MAC_VER_63
:
5193 rtl_hw_init_8125(tp
);
5200 static int rtl_jumbo_max(struct rtl8169_private
*tp
)
5202 /* Non-GBit versions don't support jumbo frames */
5203 if (!tp
->supports_gmii
)
5206 switch (tp
->mac_version
) {
5208 case RTL_GIGA_MAC_VER_02
... RTL_GIGA_MAC_VER_06
:
5211 case RTL_GIGA_MAC_VER_11
:
5212 case RTL_GIGA_MAC_VER_12
:
5213 case RTL_GIGA_MAC_VER_17
:
5216 case RTL_GIGA_MAC_VER_18
... RTL_GIGA_MAC_VER_24
:
5223 static void rtl_disable_clk(void *data
)
5225 clk_disable_unprepare(data
);
5228 static int rtl_get_ether_clk(struct rtl8169_private
*tp
)
5230 struct device
*d
= tp_to_dev(tp
);
5234 clk
= devm_clk_get(d
, "ether_clk");
5238 /* clk-core allows NULL (for suspend / resume) */
5241 dev_err_probe(d
, rc
, "failed to get clk\n");
5244 rc
= clk_prepare_enable(clk
);
5246 dev_err(d
, "failed to enable clk: %d\n", rc
);
5248 rc
= devm_add_action_or_reset(d
, rtl_disable_clk
, clk
);
5254 static void rtl_init_mac_address(struct rtl8169_private
*tp
)
5256 struct net_device
*dev
= tp
->dev
;
5257 u8
*mac_addr
= dev
->dev_addr
;
5260 rc
= eth_platform_get_mac_address(tp_to_dev(tp
), mac_addr
);
5264 rtl_read_mac_address(tp
, mac_addr
);
5265 if (is_valid_ether_addr(mac_addr
))
5268 rtl_read_mac_from_reg(tp
, mac_addr
, MAC0
);
5269 if (is_valid_ether_addr(mac_addr
))
5272 eth_hw_addr_random(dev
);
5273 dev_warn(tp_to_dev(tp
), "can't read MAC address, setting random one\n");
5275 rtl_rar_set(tp
, mac_addr
);
5278 static int rtl_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
5280 struct rtl8169_private
*tp
;
5281 int jumbo_max
, region
, rc
;
5282 enum mac_version chipset
;
5283 struct net_device
*dev
;
5286 dev
= devm_alloc_etherdev(&pdev
->dev
, sizeof (*tp
));
5290 SET_NETDEV_DEV(dev
, &pdev
->dev
);
5291 dev
->netdev_ops
= &rtl_netdev_ops
;
5292 tp
= netdev_priv(dev
);
5295 tp
->supports_gmii
= ent
->driver_data
== RTL_CFG_NO_GBIT
? 0 : 1;
5297 tp
->ocp_base
= OCP_STD_PHY_BASE
;
5299 dev
->tstats
= devm_netdev_alloc_pcpu_stats(&pdev
->dev
,
5300 struct pcpu_sw_netstats
);
5304 /* Get the *optional* external "ether_clk" used on some boards */
5305 rc
= rtl_get_ether_clk(tp
);
5309 /* Disable ASPM L1 as that cause random device stop working
5310 * problems as well as full system hangs for some PCIe devices users.
5312 rc
= pci_disable_link_state(pdev
, PCIE_LINK_STATE_L1
);
5313 tp
->aspm_manageable
= !rc
;
5315 /* enable device (incl. PCI PM wakeup and hotplug setup) */
5316 rc
= pcim_enable_device(pdev
);
5318 dev_err(&pdev
->dev
, "enable failure\n");
5322 if (pcim_set_mwi(pdev
) < 0)
5323 dev_info(&pdev
->dev
, "Mem-Wr-Inval unavailable\n");
5325 /* use first MMIO region */
5326 region
= ffs(pci_select_bars(pdev
, IORESOURCE_MEM
)) - 1;
5328 dev_err(&pdev
->dev
, "no MMIO resource found\n");
5332 /* check for weird/broken PCI region reporting */
5333 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
5334 dev_err(&pdev
->dev
, "Invalid PCI region size(s), aborting\n");
5338 rc
= pcim_iomap_regions(pdev
, BIT(region
), KBUILD_MODNAME
);
5340 dev_err(&pdev
->dev
, "cannot remap MMIO, aborting\n");
5344 tp
->mmio_addr
= pcim_iomap_table(pdev
)[region
];
5346 xid
= (RTL_R32(tp
, TxConfig
) >> 20) & 0xfcf;
5348 /* Identify chip attached to board */
5349 chipset
= rtl8169_get_mac_version(xid
, tp
->supports_gmii
);
5350 if (chipset
== RTL_GIGA_MAC_NONE
) {
5351 dev_err(&pdev
->dev
, "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", xid
);
5355 tp
->mac_version
= chipset
;
5357 tp
->dash_type
= rtl_check_dash(tp
);
5359 tp
->cp_cmd
= RTL_R16(tp
, CPlusCmd
) & CPCMD_MASK
;
5361 if (sizeof(dma_addr_t
) > 4 && tp
->mac_version
>= RTL_GIGA_MAC_VER_18
&&
5362 !dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64)))
5363 dev
->features
|= NETIF_F_HIGHDMA
;
5367 rtl8169_irq_mask_and_ack(tp
);
5369 rtl_hw_initialize(tp
);
5373 rc
= rtl_alloc_irq(tp
);
5375 dev_err(&pdev
->dev
, "Can't allocate interrupt\n");
5379 INIT_WORK(&tp
->wk
.work
, rtl_task
);
5381 rtl_init_mac_address(tp
);
5383 dev
->ethtool_ops
= &rtl8169_ethtool_ops
;
5385 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, NAPI_POLL_WEIGHT
);
5387 dev
->hw_features
= NETIF_F_IP_CSUM
| NETIF_F_RXCSUM
|
5388 NETIF_F_HW_VLAN_CTAG_TX
| NETIF_F_HW_VLAN_CTAG_RX
;
5389 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
;
5390 dev
->priv_flags
|= IFF_LIVE_ADDR_CHANGE
;
5393 * Pretend we are using VLANs; This bypasses a nasty bug where
5394 * Interrupts stop flowing on high load on 8110SCd controllers.
5396 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
5397 /* Disallow toggling */
5398 dev
->hw_features
&= ~NETIF_F_HW_VLAN_CTAG_RX
;
5400 if (rtl_chip_supports_csum_v2(tp
))
5401 dev
->hw_features
|= NETIF_F_IPV6_CSUM
;
5403 dev
->features
|= dev
->hw_features
;
5405 /* There has been a number of reports that using SG/TSO results in
5406 * tx timeouts. However for a lot of people SG/TSO works fine.
5407 * Therefore disable both features by default, but allow users to
5408 * enable them. Use at own risk!
5410 if (rtl_chip_supports_csum_v2(tp
)) {
5411 dev
->hw_features
|= NETIF_F_SG
| NETIF_F_TSO
| NETIF_F_TSO6
;
5412 dev
->gso_max_size
= RTL_GSO_MAX_SIZE_V2
;
5413 dev
->gso_max_segs
= RTL_GSO_MAX_SEGS_V2
;
5415 dev
->hw_features
|= NETIF_F_SG
| NETIF_F_TSO
;
5416 dev
->gso_max_size
= RTL_GSO_MAX_SIZE_V1
;
5417 dev
->gso_max_segs
= RTL_GSO_MAX_SEGS_V1
;
5420 dev
->hw_features
|= NETIF_F_RXALL
;
5421 dev
->hw_features
|= NETIF_F_RXFCS
;
5423 /* configure chip for default features */
5424 rtl8169_set_features(dev
, dev
->features
);
5426 rtl_set_d3_pll_down(tp
, true);
5428 jumbo_max
= rtl_jumbo_max(tp
);
5430 dev
->max_mtu
= jumbo_max
;
5432 rtl_set_irq_mask(tp
);
5434 tp
->fw_name
= rtl_chip_infos
[chipset
].fw_name
;
5436 tp
->counters
= dmam_alloc_coherent (&pdev
->dev
, sizeof(*tp
->counters
),
5437 &tp
->counters_phys_addr
,
5442 pci_set_drvdata(pdev
, tp
);
5444 rc
= r8169_mdio_register(tp
);
5448 rc
= register_netdev(dev
);
5452 netdev_info(dev
, "%s, %pM, XID %03x, IRQ %d\n",
5453 rtl_chip_infos
[chipset
].name
, dev
->dev_addr
, xid
,
5454 pci_irq_vector(pdev
, 0));
5457 netdev_info(dev
, "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
5458 jumbo_max
, tp
->mac_version
<= RTL_GIGA_MAC_VER_06
?
5461 if (tp
->dash_type
!= RTL_DASH_NONE
) {
5462 netdev_info(dev
, "DASH enabled\n");
5463 rtl8168_driver_start(tp
);
5466 if (pci_dev_run_wake(pdev
))
5467 pm_runtime_put_sync(&pdev
->dev
);
5472 static struct pci_driver rtl8169_pci_driver
= {
5473 .name
= KBUILD_MODNAME
,
5474 .id_table
= rtl8169_pci_tbl
,
5475 .probe
= rtl_init_one
,
5476 .remove
= rtl_remove_one
,
5477 .shutdown
= rtl_shutdown
,
5478 .driver
.pm
= pm_ptr(&rtl8169_pm_ops
),
5481 module_pci_driver(rtl8169_pci_driver
);