1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Renesas Ethernet AVB device driver
4 * Copyright (C) 2014-2015 Renesas Electronics Corporation
5 * Copyright (C) 2015 Renesas Solutions Corp.
6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
8 * Based on the SuperH Ethernet driver
14 #include <linux/interrupt.h>
16 #include <linux/kernel.h>
17 #include <linux/mdio-bitbang.h>
18 #include <linux/netdevice.h>
19 #include <linux/phy.h>
20 #include <linux/platform_device.h>
21 #include <linux/ptp_clock_kernel.h>
23 #define BE_TX_RING_SIZE 64 /* TX ring size for Best Effort */
24 #define BE_RX_RING_SIZE 1024 /* RX ring size for Best Effort */
25 #define NC_TX_RING_SIZE 64 /* TX ring size for Network Control */
26 #define NC_RX_RING_SIZE 64 /* RX ring size for Network Control */
27 #define BE_TX_RING_MIN 64
28 #define BE_RX_RING_MIN 64
29 #define BE_TX_RING_MAX 1024
30 #define BE_RX_RING_MAX 2048
32 #define PKT_BUF_SZ 1538
34 /* Driver's parameters */
35 #define RAVB_ALIGN 128
37 /* Hardware time stamp */
38 #define RAVB_TXTSTAMP_VALID 0x00000001 /* TX timestamp valid */
39 #define RAVB_TXTSTAMP_ENABLED 0x00000010 /* Enable TX timestamping */
41 #define RAVB_RXTSTAMP_VALID 0x00000001 /* RX timestamp valid */
42 #define RAVB_RXTSTAMP_TYPE 0x00000006 /* RX type mask */
43 #define RAVB_RXTSTAMP_TYPE_V2_L2_EVENT 0x00000002
44 #define RAVB_RXTSTAMP_TYPE_ALL 0x00000006
45 #define RAVB_RXTSTAMP_ENABLED 0x00000010 /* Enable RX timestamping */
48 /* AVB-DMAC registers */
76 APSR
= 0x008C, /* R-Car Gen3 only */
158 CIE
= 0x0384, /* R-Car Gen3 only */
168 GCPT
= 0x03B4, /* Documented for R-Car Gen3 only */
172 GIE
= 0x03CC, /* R-Car Gen3 only */
173 GID
= 0x03D0, /* R-Car Gen3 only */
174 DIL
= 0x0440, /* R-Car Gen3 only */
175 RIE0
= 0x0460, /* R-Car Gen3 only */
176 RID0
= 0x0464, /* R-Car Gen3 only */
177 RIE2
= 0x0470, /* R-Car Gen3 only */
178 RID2
= 0x0474, /* R-Car Gen3 only */
179 TIE
= 0x0478, /* R-Car Gen3 only */
180 TID
= 0x047c, /* R-Car Gen3 only */
182 /* E-MAC registers */
196 TROCR
= 0x0700, /* R-Car Gen3 only */
206 /* Register bits of the Ethernet AVB */
209 CCC_OPC
= 0x00000003,
210 CCC_OPC_RESET
= 0x00000000,
211 CCC_OPC_CONFIG
= 0x00000001,
212 CCC_OPC_OPERATION
= 0x00000002,
213 CCC_GAC
= 0x00000080,
214 CCC_DTSR
= 0x00000100,
215 CCC_CSEL
= 0x00030000,
216 CCC_CSEL_HPB
= 0x00010000,
217 CCC_CSEL_ETH_TX
= 0x00020000,
218 CCC_CSEL_GMII_REF
= 0x00030000,
219 CCC_LBME
= 0x01000000,
224 CSR_OPS
= 0x0000000F,
225 CSR_OPS_RESET
= 0x00000001,
226 CSR_OPS_CONFIG
= 0x00000002,
227 CSR_OPS_OPERATION
= 0x00000004,
228 CSR_OPS_STANDBY
= 0x00000008, /* Documented for R-Car Gen3 only */
229 CSR_DTS
= 0x00000100,
230 CSR_TPO0
= 0x00010000,
231 CSR_TPO1
= 0x00020000,
232 CSR_TPO2
= 0x00040000,
233 CSR_TPO3
= 0x00080000,
234 CSR_RPO
= 0x00100000,
239 ESR_EQN
= 0x0000001F,
241 ESR_EIL
= 0x00001000,
244 /* APSR (R-Car Gen3 only) */
246 APSR_MEMS
= 0x00000002, /* Undocumented */
247 APSR_CMSW
= 0x00000010,
248 APSR_RDM
= 0x00002000,
249 APSR_TDM
= 0x00004000,
254 RCR_EFFS
= 0x00000001,
255 RCR_ENCF
= 0x00000002,
256 RCR_ESF
= 0x0000000C,
257 RCR_ETS0
= 0x00000010,
258 RCR_ETS2
= 0x00000020,
259 RCR_RFCL
= 0x1FFF0000,
264 RQC_RSM0
= 0x00000003,
265 RQC_UFCC0
= 0x00000030,
266 RQC_RSM1
= 0x00000300,
267 RQC_UFCC1
= 0x00003000,
268 RQC_RSM2
= 0x00030000,
269 RQC_UFCC2
= 0x00300000,
270 RQC_RSM3
= 0x03000000,
271 RQC_UFCC3
= 0x30000000,
276 RPC_PCNT
= 0x00000700,
277 RPC_DCNT
= 0x00FF0000,
282 UFCW_WL0
= 0x0000003F,
283 UFCW_WL1
= 0x00003F00,
284 UFCW_WL2
= 0x003F0000,
285 UFCW_WL3
= 0x3F000000,
290 UFCS_SL0
= 0x0000003F,
291 UFCS_SL1
= 0x00003F00,
292 UFCS_SL2
= 0x003F0000,
293 UFCS_SL3
= 0x3F000000,
298 UFCV_CV0
= 0x0000003F,
299 UFCV_CV1
= 0x00003F00,
300 UFCV_CV2
= 0x003F0000,
301 UFCV_CV3
= 0x3F000000,
306 UFCD_DV0
= 0x0000003F,
307 UFCD_DV1
= 0x00003F00,
308 UFCD_DV2
= 0x003F0000,
309 UFCD_DV3
= 0x3F000000,
314 SFO_FBP
= 0x0000003F,
319 RTC_MFL0
= 0x00000FFF,
320 RTC_MFL1
= 0x0FFF0000,
325 TGC_TSM0
= 0x00000001,
326 TGC_TSM1
= 0x00000002,
327 TGC_TSM2
= 0x00000004,
328 TGC_TSM3
= 0x00000008,
329 TGC_TQP
= 0x00000030,
330 TGC_TQP_NONAVB
= 0x00000000,
331 TGC_TQP_AVBMODE1
= 0x00000010,
332 TGC_TQP_AVBMODE2
= 0x00000030,
333 TGC_TBD0
= 0x00000300,
334 TGC_TBD1
= 0x00003000,
335 TGC_TBD2
= 0x00030000,
336 TGC_TBD3
= 0x00300000,
341 TCCR_TSRQ0
= 0x00000001,
342 TCCR_TSRQ1
= 0x00000002,
343 TCCR_TSRQ2
= 0x00000004,
344 TCCR_TSRQ3
= 0x00000008,
345 TCCR_TFEN
= 0x00000100,
346 TCCR_TFR
= 0x00000200,
351 TSR_CCS0
= 0x00000003,
352 TSR_CCS1
= 0x0000000C,
353 TSR_TFFL
= 0x00000700,
358 TFA2_TSV
= 0x0000FFFF,
359 TFA2_TST
= 0x03FF0000,
364 DIC_DPE1
= 0x00000002,
365 DIC_DPE2
= 0x00000004,
366 DIC_DPE3
= 0x00000008,
367 DIC_DPE4
= 0x00000010,
368 DIC_DPE5
= 0x00000020,
369 DIC_DPE6
= 0x00000040,
370 DIC_DPE7
= 0x00000080,
371 DIC_DPE8
= 0x00000100,
372 DIC_DPE9
= 0x00000200,
373 DIC_DPE10
= 0x00000400,
374 DIC_DPE11
= 0x00000800,
375 DIC_DPE12
= 0x00001000,
376 DIC_DPE13
= 0x00002000,
377 DIC_DPE14
= 0x00004000,
378 DIC_DPE15
= 0x00008000,
383 DIS_DPF1
= 0x00000002,
384 DIS_DPF2
= 0x00000004,
385 DIS_DPF3
= 0x00000008,
386 DIS_DPF4
= 0x00000010,
387 DIS_DPF5
= 0x00000020,
388 DIS_DPF6
= 0x00000040,
389 DIS_DPF7
= 0x00000080,
390 DIS_DPF8
= 0x00000100,
391 DIS_DPF9
= 0x00000200,
392 DIS_DPF10
= 0x00000400,
393 DIS_DPF11
= 0x00000800,
394 DIS_DPF12
= 0x00001000,
395 DIS_DPF13
= 0x00002000,
396 DIS_DPF14
= 0x00004000,
397 DIS_DPF15
= 0x00008000,
402 EIC_MREE
= 0x00000001,
403 EIC_MTEE
= 0x00000002,
404 EIC_QEE
= 0x00000004,
405 EIC_SEE
= 0x00000008,
406 EIC_CLLE0
= 0x00000010,
407 EIC_CLLE1
= 0x00000020,
408 EIC_CULE0
= 0x00000040,
409 EIC_CULE1
= 0x00000080,
410 EIC_TFFE
= 0x00000100,
415 EIS_MREF
= 0x00000001,
416 EIS_MTEF
= 0x00000002,
417 EIS_QEF
= 0x00000004,
418 EIS_SEF
= 0x00000008,
419 EIS_CLLF0
= 0x00000010,
420 EIS_CLLF1
= 0x00000020,
421 EIS_CULF0
= 0x00000040,
422 EIS_CULF1
= 0x00000080,
423 EIS_TFFF
= 0x00000100,
424 EIS_QFS
= 0x00010000,
425 EIS_RESERVED
= (GENMASK(31, 17) | GENMASK(15, 11)),
430 RIC0_FRE0
= 0x00000001,
431 RIC0_FRE1
= 0x00000002,
432 RIC0_FRE2
= 0x00000004,
433 RIC0_FRE3
= 0x00000008,
434 RIC0_FRE4
= 0x00000010,
435 RIC0_FRE5
= 0x00000020,
436 RIC0_FRE6
= 0x00000040,
437 RIC0_FRE7
= 0x00000080,
438 RIC0_FRE8
= 0x00000100,
439 RIC0_FRE9
= 0x00000200,
440 RIC0_FRE10
= 0x00000400,
441 RIC0_FRE11
= 0x00000800,
442 RIC0_FRE12
= 0x00001000,
443 RIC0_FRE13
= 0x00002000,
444 RIC0_FRE14
= 0x00004000,
445 RIC0_FRE15
= 0x00008000,
446 RIC0_FRE16
= 0x00010000,
447 RIC0_FRE17
= 0x00020000,
452 RIS0_FRF0
= 0x00000001,
453 RIS0_FRF1
= 0x00000002,
454 RIS0_FRF2
= 0x00000004,
455 RIS0_FRF3
= 0x00000008,
456 RIS0_FRF4
= 0x00000010,
457 RIS0_FRF5
= 0x00000020,
458 RIS0_FRF6
= 0x00000040,
459 RIS0_FRF7
= 0x00000080,
460 RIS0_FRF8
= 0x00000100,
461 RIS0_FRF9
= 0x00000200,
462 RIS0_FRF10
= 0x00000400,
463 RIS0_FRF11
= 0x00000800,
464 RIS0_FRF12
= 0x00001000,
465 RIS0_FRF13
= 0x00002000,
466 RIS0_FRF14
= 0x00004000,
467 RIS0_FRF15
= 0x00008000,
468 RIS0_FRF16
= 0x00010000,
469 RIS0_FRF17
= 0x00020000,
470 RIS0_RESERVED
= GENMASK(31, 18),
475 RIC1_RFWE
= 0x80000000,
480 RIS1_RFWF
= 0x80000000,
485 RIC2_QFE0
= 0x00000001,
486 RIC2_QFE1
= 0x00000002,
487 RIC2_QFE2
= 0x00000004,
488 RIC2_QFE3
= 0x00000008,
489 RIC2_QFE4
= 0x00000010,
490 RIC2_QFE5
= 0x00000020,
491 RIC2_QFE6
= 0x00000040,
492 RIC2_QFE7
= 0x00000080,
493 RIC2_QFE8
= 0x00000100,
494 RIC2_QFE9
= 0x00000200,
495 RIC2_QFE10
= 0x00000400,
496 RIC2_QFE11
= 0x00000800,
497 RIC2_QFE12
= 0x00001000,
498 RIC2_QFE13
= 0x00002000,
499 RIC2_QFE14
= 0x00004000,
500 RIC2_QFE15
= 0x00008000,
501 RIC2_QFE16
= 0x00010000,
502 RIC2_QFE17
= 0x00020000,
503 RIC2_RFFE
= 0x80000000,
508 RIS2_QFF0
= 0x00000001,
509 RIS2_QFF1
= 0x00000002,
510 RIS2_QFF2
= 0x00000004,
511 RIS2_QFF3
= 0x00000008,
512 RIS2_QFF4
= 0x00000010,
513 RIS2_QFF5
= 0x00000020,
514 RIS2_QFF6
= 0x00000040,
515 RIS2_QFF7
= 0x00000080,
516 RIS2_QFF8
= 0x00000100,
517 RIS2_QFF9
= 0x00000200,
518 RIS2_QFF10
= 0x00000400,
519 RIS2_QFF11
= 0x00000800,
520 RIS2_QFF12
= 0x00001000,
521 RIS2_QFF13
= 0x00002000,
522 RIS2_QFF14
= 0x00004000,
523 RIS2_QFF15
= 0x00008000,
524 RIS2_QFF16
= 0x00010000,
525 RIS2_QFF17
= 0x00020000,
526 RIS2_RFFF
= 0x80000000,
527 RIS2_RESERVED
= GENMASK(30, 18),
532 TIC_FTE0
= 0x00000001, /* Documented for R-Car Gen3 only */
533 TIC_FTE1
= 0x00000002, /* Documented for R-Car Gen3 only */
534 TIC_TFUE
= 0x00000100,
535 TIC_TFWE
= 0x00000200,
540 TIS_FTF0
= 0x00000001, /* Documented for R-Car Gen3 only */
541 TIS_FTF1
= 0x00000002, /* Documented for R-Car Gen3 only */
542 TIS_TFUF
= 0x00000100,
543 TIS_TFWF
= 0x00000200,
544 TIS_RESERVED
= (GENMASK(31, 20) | GENMASK(15, 12) | GENMASK(7, 4))
549 ISS_FRS
= 0x00000001, /* Documented for R-Car Gen3 only */
550 ISS_FTS
= 0x00000004, /* Documented for R-Car Gen3 only */
553 ISS_TFUS
= 0x00000100,
554 ISS_TFWS
= 0x00000200,
555 ISS_RFWS
= 0x00001000,
556 ISS_CGIS
= 0x00002000,
557 ISS_DPS1
= 0x00020000,
558 ISS_DPS2
= 0x00040000,
559 ISS_DPS3
= 0x00080000,
560 ISS_DPS4
= 0x00100000,
561 ISS_DPS5
= 0x00200000,
562 ISS_DPS6
= 0x00400000,
563 ISS_DPS7
= 0x00800000,
564 ISS_DPS8
= 0x01000000,
565 ISS_DPS9
= 0x02000000,
566 ISS_DPS10
= 0x04000000,
567 ISS_DPS11
= 0x08000000,
568 ISS_DPS12
= 0x10000000,
569 ISS_DPS13
= 0x20000000,
570 ISS_DPS14
= 0x40000000,
571 ISS_DPS15
= 0x80000000,
574 /* CIE (R-Car Gen3 only) */
576 CIE_CRIE
= 0x00000001,
577 CIE_CTIE
= 0x00000100,
578 CIE_RQFM
= 0x00010000,
579 CIE_CL0M
= 0x00020000,
580 CIE_RFWL
= 0x00040000,
581 CIE_RFFL
= 0x00080000,
586 GCCR_TCR
= 0x00000003,
587 GCCR_TCR_NOREQ
= 0x00000000, /* No request */
588 GCCR_TCR_RESET
= 0x00000001, /* gPTP/AVTP presentation timer reset */
589 GCCR_TCR_CAPTURE
= 0x00000003, /* Capture value set in GCCR.TCSS */
590 GCCR_LTO
= 0x00000004,
591 GCCR_LTI
= 0x00000008,
592 GCCR_LPTC
= 0x00000010,
593 GCCR_LMTT
= 0x00000020,
594 GCCR_TCSS
= 0x00000300,
595 GCCR_TCSS_GPTP
= 0x00000000, /* gPTP timer value */
596 GCCR_TCSS_ADJGPTP
= 0x00000100, /* Adjusted gPTP timer value */
597 GCCR_TCSS_AVTP
= 0x00000200, /* AVTP presentation time value */
602 GTI_TIV
= 0x0FFFFFFF,
605 #define GTI_TIV_MAX GTI_TIV
606 #define GTI_TIV_MIN 0x20
610 GIC_PTCE
= 0x00000001, /* Documented for R-Car Gen3 only */
611 GIC_PTME
= 0x00000004,
616 GIS_PTCF
= 0x00000001, /* Documented for R-Car Gen3 only */
617 GIS_PTMF
= 0x00000004,
618 GIS_RESERVED
= GENMASK(15, 10),
621 /* GIE (R-Car Gen3 only) */
623 GIE_PTCS
= 0x00000001,
624 GIE_PTOS
= 0x00000002,
625 GIE_PTMS0
= 0x00000004,
626 GIE_PTMS1
= 0x00000008,
627 GIE_PTMS2
= 0x00000010,
628 GIE_PTMS3
= 0x00000020,
629 GIE_PTMS4
= 0x00000040,
630 GIE_PTMS5
= 0x00000080,
631 GIE_PTMS6
= 0x00000100,
632 GIE_PTMS7
= 0x00000200,
633 GIE_ATCS0
= 0x00010000,
634 GIE_ATCS1
= 0x00020000,
635 GIE_ATCS2
= 0x00040000,
636 GIE_ATCS3
= 0x00080000,
637 GIE_ATCS4
= 0x00100000,
638 GIE_ATCS5
= 0x00200000,
639 GIE_ATCS6
= 0x00400000,
640 GIE_ATCS7
= 0x00800000,
641 GIE_ATCS8
= 0x01000000,
642 GIE_ATCS9
= 0x02000000,
643 GIE_ATCS10
= 0x04000000,
644 GIE_ATCS11
= 0x08000000,
645 GIE_ATCS12
= 0x10000000,
646 GIE_ATCS13
= 0x20000000,
647 GIE_ATCS14
= 0x40000000,
648 GIE_ATCS15
= 0x80000000,
651 /* GID (R-Car Gen3 only) */
653 GID_PTCD
= 0x00000001,
654 GID_PTOD
= 0x00000002,
655 GID_PTMD0
= 0x00000004,
656 GID_PTMD1
= 0x00000008,
657 GID_PTMD2
= 0x00000010,
658 GID_PTMD3
= 0x00000020,
659 GID_PTMD4
= 0x00000040,
660 GID_PTMD5
= 0x00000080,
661 GID_PTMD6
= 0x00000100,
662 GID_PTMD7
= 0x00000200,
663 GID_ATCD0
= 0x00010000,
664 GID_ATCD1
= 0x00020000,
665 GID_ATCD2
= 0x00040000,
666 GID_ATCD3
= 0x00080000,
667 GID_ATCD4
= 0x00100000,
668 GID_ATCD5
= 0x00200000,
669 GID_ATCD6
= 0x00400000,
670 GID_ATCD7
= 0x00800000,
671 GID_ATCD8
= 0x01000000,
672 GID_ATCD9
= 0x02000000,
673 GID_ATCD10
= 0x04000000,
674 GID_ATCD11
= 0x08000000,
675 GID_ATCD12
= 0x10000000,
676 GID_ATCD13
= 0x20000000,
677 GID_ATCD14
= 0x40000000,
678 GID_ATCD15
= 0x80000000,
681 /* RIE0 (R-Car Gen3 only) */
683 RIE0_FRS0
= 0x00000001,
684 RIE0_FRS1
= 0x00000002,
685 RIE0_FRS2
= 0x00000004,
686 RIE0_FRS3
= 0x00000008,
687 RIE0_FRS4
= 0x00000010,
688 RIE0_FRS5
= 0x00000020,
689 RIE0_FRS6
= 0x00000040,
690 RIE0_FRS7
= 0x00000080,
691 RIE0_FRS8
= 0x00000100,
692 RIE0_FRS9
= 0x00000200,
693 RIE0_FRS10
= 0x00000400,
694 RIE0_FRS11
= 0x00000800,
695 RIE0_FRS12
= 0x00001000,
696 RIE0_FRS13
= 0x00002000,
697 RIE0_FRS14
= 0x00004000,
698 RIE0_FRS15
= 0x00008000,
699 RIE0_FRS16
= 0x00010000,
700 RIE0_FRS17
= 0x00020000,
703 /* RID0 (R-Car Gen3 only) */
705 RID0_FRD0
= 0x00000001,
706 RID0_FRD1
= 0x00000002,
707 RID0_FRD2
= 0x00000004,
708 RID0_FRD3
= 0x00000008,
709 RID0_FRD4
= 0x00000010,
710 RID0_FRD5
= 0x00000020,
711 RID0_FRD6
= 0x00000040,
712 RID0_FRD7
= 0x00000080,
713 RID0_FRD8
= 0x00000100,
714 RID0_FRD9
= 0x00000200,
715 RID0_FRD10
= 0x00000400,
716 RID0_FRD11
= 0x00000800,
717 RID0_FRD12
= 0x00001000,
718 RID0_FRD13
= 0x00002000,
719 RID0_FRD14
= 0x00004000,
720 RID0_FRD15
= 0x00008000,
721 RID0_FRD16
= 0x00010000,
722 RID0_FRD17
= 0x00020000,
725 /* RIE2 (R-Car Gen3 only) */
727 RIE2_QFS0
= 0x00000001,
728 RIE2_QFS1
= 0x00000002,
729 RIE2_QFS2
= 0x00000004,
730 RIE2_QFS3
= 0x00000008,
731 RIE2_QFS4
= 0x00000010,
732 RIE2_QFS5
= 0x00000020,
733 RIE2_QFS6
= 0x00000040,
734 RIE2_QFS7
= 0x00000080,
735 RIE2_QFS8
= 0x00000100,
736 RIE2_QFS9
= 0x00000200,
737 RIE2_QFS10
= 0x00000400,
738 RIE2_QFS11
= 0x00000800,
739 RIE2_QFS12
= 0x00001000,
740 RIE2_QFS13
= 0x00002000,
741 RIE2_QFS14
= 0x00004000,
742 RIE2_QFS15
= 0x00008000,
743 RIE2_QFS16
= 0x00010000,
744 RIE2_QFS17
= 0x00020000,
745 RIE2_RFFS
= 0x80000000,
748 /* RID2 (R-Car Gen3 only) */
750 RID2_QFD0
= 0x00000001,
751 RID2_QFD1
= 0x00000002,
752 RID2_QFD2
= 0x00000004,
753 RID2_QFD3
= 0x00000008,
754 RID2_QFD4
= 0x00000010,
755 RID2_QFD5
= 0x00000020,
756 RID2_QFD6
= 0x00000040,
757 RID2_QFD7
= 0x00000080,
758 RID2_QFD8
= 0x00000100,
759 RID2_QFD9
= 0x00000200,
760 RID2_QFD10
= 0x00000400,
761 RID2_QFD11
= 0x00000800,
762 RID2_QFD12
= 0x00001000,
763 RID2_QFD13
= 0x00002000,
764 RID2_QFD14
= 0x00004000,
765 RID2_QFD15
= 0x00008000,
766 RID2_QFD16
= 0x00010000,
767 RID2_QFD17
= 0x00020000,
768 RID2_RFFD
= 0x80000000,
771 /* TIE (R-Car Gen3 only) */
773 TIE_FTS0
= 0x00000001,
774 TIE_FTS1
= 0x00000002,
775 TIE_FTS2
= 0x00000004,
776 TIE_FTS3
= 0x00000008,
777 TIE_TFUS
= 0x00000100,
778 TIE_TFWS
= 0x00000200,
779 TIE_MFUS
= 0x00000400,
780 TIE_MFWS
= 0x00000800,
781 TIE_TDPS0
= 0x00010000,
782 TIE_TDPS1
= 0x00020000,
783 TIE_TDPS2
= 0x00040000,
784 TIE_TDPS3
= 0x00080000,
787 /* TID (R-Car Gen3 only) */
789 TID_FTD0
= 0x00000001,
790 TID_FTD1
= 0x00000002,
791 TID_FTD2
= 0x00000004,
792 TID_FTD3
= 0x00000008,
793 TID_TFUD
= 0x00000100,
794 TID_TFWD
= 0x00000200,
795 TID_MFUD
= 0x00000400,
796 TID_MFWD
= 0x00000800,
797 TID_TDPD0
= 0x00010000,
798 TID_TDPD1
= 0x00020000,
799 TID_TDPD2
= 0x00040000,
800 TID_TDPD3
= 0x00080000,
805 ECMR_PRM
= 0x00000001,
806 ECMR_DM
= 0x00000002,
807 ECMR_TE
= 0x00000020,
808 ECMR_RE
= 0x00000040,
809 ECMR_MPDE
= 0x00000200,
810 ECMR_TXF
= 0x00010000, /* Documented for R-Car Gen3 only */
811 ECMR_RXF
= 0x00020000,
812 ECMR_PFR
= 0x00040000,
813 ECMR_ZPF
= 0x00080000, /* Documented for R-Car Gen3 only */
814 ECMR_RZPF
= 0x00100000,
815 ECMR_DPAD
= 0x00200000,
816 ECMR_RCSC
= 0x00800000,
817 ECMR_TRCCM
= 0x04000000,
822 ECSR_ICD
= 0x00000001,
823 ECSR_MPD
= 0x00000002,
824 ECSR_LCHNG
= 0x00000004,
825 ECSR_PHYI
= 0x00000008,
830 ECSIPR_ICDIP
= 0x00000001,
831 ECSIPR_MPDIP
= 0x00000002,
832 ECSIPR_LCHNGIP
= 0x00000004,
837 PIR_MDC
= 0x00000001,
838 PIR_MMD
= 0x00000002,
839 PIR_MDO
= 0x00000004,
840 PIR_MDI
= 0x00000008,
845 PSR_LMON
= 0x00000001,
850 PIPR_PHYIP
= 0x00000001,
860 GECMR_SPEED
= 0x00000001,
861 GECMR_SPEED_100
= 0x00000000,
862 GECMR_SPEED_1000
= 0x00000001,
865 /* The Ethernet AVB descriptor definitions. */
867 __le16 ds
; /* Descriptor size */
868 u8 cc
; /* Content control MSBs (reserved) */
869 u8 die_dt
; /* Descriptor interrupt enable and type */
870 __le32 dptr
; /* Descriptor pointer */
873 #define DPTR_ALIGN 4 /* Required descriptor pointer alignment */
885 /* HW/SW arbitration */
894 struct ravb_rx_desc
{
895 __le16 ds_cc
; /* Descriptor size and content control LSBs */
896 u8 msc
; /* MAC status code */
897 u8 die_dt
; /* Descriptor interrupt enable and type */
898 __le32 dptr
; /* Descpriptor pointer */
901 struct ravb_ex_rx_desc
{
902 __le16 ds_cc
; /* Descriptor size and content control lower bits */
903 u8 msc
; /* MAC status code */
904 u8 die_dt
; /* Descriptor interrupt enable and type */
905 __le32 dptr
; /* Descpriptor pointer */
906 __le32 ts_n
; /* Timestampe nsec */
907 __le32 ts_sl
; /* Timestamp low */
908 __le16 ts_sh
; /* Timestamp high */
909 __le16 res
; /* Reserved bits */
913 RX_DS
= 0x0fff, /* Data size */
914 RX_TR
= 0x1000, /* Truncation indication */
915 RX_EI
= 0x2000, /* Error indication */
916 RX_PS
= 0xc000, /* Padding selection */
919 /* E-MAC status code */
921 MSC_CRC
= 0x01, /* Frame CRC error */
922 MSC_RFE
= 0x02, /* Frame reception error (flagged by PHY) */
923 MSC_RTSF
= 0x04, /* Frame length error (frame too short) */
924 MSC_RTLF
= 0x08, /* Frame length error (frame too long) */
925 MSC_FRE
= 0x10, /* Fraction error (not a multiple of 8 bits) */
926 MSC_CRL
= 0x20, /* Carrier lost */
927 MSC_CEEF
= 0x40, /* Carrier extension error */
928 MSC_MC
= 0x80, /* Multicast frame reception */
931 struct ravb_tx_desc
{
932 __le16 ds_tagl
; /* Descriptor size and frame tag LSBs */
933 u8 tagh_tsr
; /* Frame tag MSBs and timestamp storage request bit */
934 u8 die_dt
; /* Descriptor interrupt enable and type */
935 __le32 dptr
; /* Descpriptor pointer */
938 enum TX_DS_TAGL_BIT
{
939 TX_DS
= 0x0fff, /* Data size */
940 TX_TAGL
= 0xf000, /* Frame tag LSBs */
943 enum TX_TAGH_TSR_BIT
{
944 TX_TAGH
= 0x3f, /* Frame tag MSBs */
945 TX_TSR
= 0x40, /* Timestamp storage request */
948 RAVB_BE
= 0, /* Best Effort Queue */
949 RAVB_NC
, /* Network Control Queue */
952 #define DBAT_ENTRY_NUM 22
953 #define RX_QUEUE_OFFSET 4
954 #define NUM_RX_QUEUE 2
955 #define NUM_TX_QUEUE 2
957 #define RX_BUF_SZ (2048 - ETH_FCS_LEN + sizeof(__sum16))
959 /* TX descriptors per packet */
960 #define NUM_TX_DESC_GEN2 2
961 #define NUM_TX_DESC_GEN3 1
963 struct ravb_tstamp_skb
{
964 struct list_head list
;
969 struct ravb_ptp_perout
{
978 struct ptp_clock
*clock
;
979 struct ptp_clock_info info
;
983 struct ravb_ptp_perout perout
[N_PER_OUT
];
991 struct ravb_private
{
992 struct net_device
*ndev
;
993 struct platform_device
*pdev
;
997 struct mdiobb_ctrl mdiobb
;
998 u32 num_rx_ring
[NUM_RX_QUEUE
];
999 u32 num_tx_ring
[NUM_TX_QUEUE
];
1001 dma_addr_t desc_bat_dma
;
1002 struct ravb_desc
*desc_bat
;
1003 dma_addr_t rx_desc_dma
[NUM_RX_QUEUE
];
1004 dma_addr_t tx_desc_dma
[NUM_TX_QUEUE
];
1005 struct ravb_ex_rx_desc
*rx_ring
[NUM_RX_QUEUE
];
1006 struct ravb_tx_desc
*tx_ring
[NUM_TX_QUEUE
];
1007 void *tx_align
[NUM_TX_QUEUE
];
1008 struct sk_buff
**rx_skb
[NUM_RX_QUEUE
];
1009 struct sk_buff
**tx_skb
[NUM_TX_QUEUE
];
1012 struct net_device_stats stats
[NUM_RX_QUEUE
];
1015 struct list_head ts_skb_list
;
1017 struct ravb_ptp ptp
;
1018 spinlock_t lock
; /* Register access lock */
1019 u32 cur_rx
[NUM_RX_QUEUE
]; /* Consumer ring indices */
1020 u32 dirty_rx
[NUM_RX_QUEUE
]; /* Producer ring indices */
1021 u32 cur_tx
[NUM_TX_QUEUE
];
1022 u32 dirty_tx
[NUM_TX_QUEUE
];
1023 struct napi_struct napi
[NUM_RX_QUEUE
];
1024 struct work_struct work
;
1025 /* MII transceiver section. */
1026 struct mii_bus
*mii_bus
; /* MDIO bus control */
1028 phy_interface_t phy_interface
;
1032 enum ravb_chip_id chip_id
;
1033 int rx_irqs
[NUM_RX_QUEUE
];
1034 int tx_irqs
[NUM_TX_QUEUE
];
1036 unsigned no_avb_link
:1;
1037 unsigned avb_link_active_low
:1;
1038 unsigned wol_enabled
:1;
1039 unsigned rxcidm
:1; /* RX Clock Internal Delay Mode */
1040 unsigned txcidm
:1; /* TX Clock Internal Delay Mode */
1041 unsigned rgmii_override
:1; /* Deprecated rgmii-*id behavior */
1042 int num_tx_desc
; /* TX descriptors per packet */
1045 static inline u32
ravb_read(struct net_device
*ndev
, enum ravb_reg reg
)
1047 struct ravb_private
*priv
= netdev_priv(ndev
);
1049 return ioread32(priv
->addr
+ reg
);
1052 static inline void ravb_write(struct net_device
*ndev
, u32 data
,
1055 struct ravb_private
*priv
= netdev_priv(ndev
);
1057 iowrite32(data
, priv
->addr
+ reg
);
1060 void ravb_modify(struct net_device
*ndev
, enum ravb_reg reg
, u32 clear
,
1062 int ravb_wait(struct net_device
*ndev
, enum ravb_reg reg
, u32 mask
, u32 value
);
1064 void ravb_ptp_interrupt(struct net_device
*ndev
);
1065 void ravb_ptp_init(struct net_device
*ndev
, struct platform_device
*pdev
);
1066 void ravb_ptp_stop(struct net_device
*ndev
);
1068 #endif /* #ifndef __RAVB_H__ */