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[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / renesas / ravb_main.c
1 /* Renesas Ethernet AVB device driver
2 *
3 * Copyright (C) 2014-2015 Renesas Electronics Corporation
4 * Copyright (C) 2015 Renesas Solutions Corp.
5 * Copyright (C) 2015 Cogent Embedded, Inc. <source@cogentembedded.com>
6 *
7 * Based on the SuperH Ethernet driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License version 2,
11 * as published by the Free Software Foundation.
12 */
13
14 #include <linux/cache.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/err.h>
19 #include <linux/etherdevice.h>
20 #include <linux/ethtool.h>
21 #include <linux/if_vlan.h>
22 #include <linux/kernel.h>
23 #include <linux/list.h>
24 #include <linux/module.h>
25 #include <linux/net_tstamp.h>
26 #include <linux/of.h>
27 #include <linux/of_device.h>
28 #include <linux/of_irq.h>
29 #include <linux/of_mdio.h>
30 #include <linux/of_net.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/slab.h>
33 #include <linux/spinlock.h>
34
35 #include <asm/div64.h>
36
37 #include "ravb.h"
38
39 #define RAVB_DEF_MSG_ENABLE \
40 (NETIF_MSG_LINK | \
41 NETIF_MSG_TIMER | \
42 NETIF_MSG_RX_ERR | \
43 NETIF_MSG_TX_ERR)
44
45 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
46 {
47 int i;
48
49 for (i = 0; i < 10000; i++) {
50 if ((ravb_read(ndev, reg) & mask) == value)
51 return 0;
52 udelay(10);
53 }
54 return -ETIMEDOUT;
55 }
56
57 static int ravb_config(struct net_device *ndev)
58 {
59 int error;
60
61 /* Set config mode */
62 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_CONFIG,
63 CCC);
64 /* Check if the operating mode is changed to the config mode */
65 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);
66 if (error)
67 netdev_err(ndev, "failed to switch device to config mode\n");
68
69 return error;
70 }
71
72 static void ravb_set_duplex(struct net_device *ndev)
73 {
74 struct ravb_private *priv = netdev_priv(ndev);
75 u32 ecmr = ravb_read(ndev, ECMR);
76
77 if (priv->duplex) /* Full */
78 ecmr |= ECMR_DM;
79 else /* Half */
80 ecmr &= ~ECMR_DM;
81 ravb_write(ndev, ecmr, ECMR);
82 }
83
84 static void ravb_set_rate(struct net_device *ndev)
85 {
86 struct ravb_private *priv = netdev_priv(ndev);
87
88 switch (priv->speed) {
89 case 100: /* 100BASE */
90 ravb_write(ndev, GECMR_SPEED_100, GECMR);
91 break;
92 case 1000: /* 1000BASE */
93 ravb_write(ndev, GECMR_SPEED_1000, GECMR);
94 break;
95 default:
96 break;
97 }
98 }
99
100 static void ravb_set_buffer_align(struct sk_buff *skb)
101 {
102 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
103
104 if (reserve)
105 skb_reserve(skb, RAVB_ALIGN - reserve);
106 }
107
108 /* Get MAC address from the MAC address registers
109 *
110 * Ethernet AVB device doesn't have ROM for MAC address.
111 * This function gets the MAC address that was used by a bootloader.
112 */
113 static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac)
114 {
115 if (mac) {
116 ether_addr_copy(ndev->dev_addr, mac);
117 } else {
118 u32 mahr = ravb_read(ndev, MAHR);
119 u32 malr = ravb_read(ndev, MALR);
120
121 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
122 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
123 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
124 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
125 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
126 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
127 }
128 }
129
130 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
131 {
132 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
133 mdiobb);
134 u32 pir = ravb_read(priv->ndev, PIR);
135
136 if (set)
137 pir |= mask;
138 else
139 pir &= ~mask;
140 ravb_write(priv->ndev, pir, PIR);
141 }
142
143 /* MDC pin control */
144 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
145 {
146 ravb_mdio_ctrl(ctrl, PIR_MDC, level);
147 }
148
149 /* Data I/O pin control */
150 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
151 {
152 ravb_mdio_ctrl(ctrl, PIR_MMD, output);
153 }
154
155 /* Set data bit */
156 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
157 {
158 ravb_mdio_ctrl(ctrl, PIR_MDO, value);
159 }
160
161 /* Get data bit */
162 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
163 {
164 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
165 mdiobb);
166
167 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
168 }
169
170 /* MDIO bus control struct */
171 static struct mdiobb_ops bb_ops = {
172 .owner = THIS_MODULE,
173 .set_mdc = ravb_set_mdc,
174 .set_mdio_dir = ravb_set_mdio_dir,
175 .set_mdio_data = ravb_set_mdio_data,
176 .get_mdio_data = ravb_get_mdio_data,
177 };
178
179 /* Free skb's and DMA buffers for Ethernet AVB */
180 static void ravb_ring_free(struct net_device *ndev, int q)
181 {
182 struct ravb_private *priv = netdev_priv(ndev);
183 int ring_size;
184 int i;
185
186 /* Free RX skb ringbuffer */
187 if (priv->rx_skb[q]) {
188 for (i = 0; i < priv->num_rx_ring[q]; i++)
189 dev_kfree_skb(priv->rx_skb[q][i]);
190 }
191 kfree(priv->rx_skb[q]);
192 priv->rx_skb[q] = NULL;
193
194 /* Free TX skb ringbuffer */
195 if (priv->tx_skb[q]) {
196 for (i = 0; i < priv->num_tx_ring[q]; i++)
197 dev_kfree_skb(priv->tx_skb[q][i]);
198 }
199 kfree(priv->tx_skb[q]);
200 priv->tx_skb[q] = NULL;
201
202 /* Free aligned TX buffers */
203 kfree(priv->tx_align[q]);
204 priv->tx_align[q] = NULL;
205
206 if (priv->rx_ring[q]) {
207 ring_size = sizeof(struct ravb_ex_rx_desc) *
208 (priv->num_rx_ring[q] + 1);
209 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q],
210 priv->rx_desc_dma[q]);
211 priv->rx_ring[q] = NULL;
212 }
213
214 if (priv->tx_ring[q]) {
215 ring_size = sizeof(struct ravb_tx_desc) *
216 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
217 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
218 priv->tx_desc_dma[q]);
219 priv->tx_ring[q] = NULL;
220 }
221 }
222
223 /* Format skb and descriptor buffer for Ethernet AVB */
224 static void ravb_ring_format(struct net_device *ndev, int q)
225 {
226 struct ravb_private *priv = netdev_priv(ndev);
227 struct ravb_ex_rx_desc *rx_desc;
228 struct ravb_tx_desc *tx_desc;
229 struct ravb_desc *desc;
230 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
231 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
232 NUM_TX_DESC;
233 dma_addr_t dma_addr;
234 int i;
235
236 priv->cur_rx[q] = 0;
237 priv->cur_tx[q] = 0;
238 priv->dirty_rx[q] = 0;
239 priv->dirty_tx[q] = 0;
240
241 memset(priv->rx_ring[q], 0, rx_ring_size);
242 /* Build RX ring buffer */
243 for (i = 0; i < priv->num_rx_ring[q]; i++) {
244 /* RX descriptor */
245 rx_desc = &priv->rx_ring[q][i];
246 /* The size of the buffer should be on 16-byte boundary. */
247 rx_desc->ds_cc = cpu_to_le16(ALIGN(PKT_BUF_SZ, 16));
248 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
249 ALIGN(PKT_BUF_SZ, 16),
250 DMA_FROM_DEVICE);
251 /* We just set the data size to 0 for a failed mapping which
252 * should prevent DMA from happening...
253 */
254 if (dma_mapping_error(ndev->dev.parent, dma_addr))
255 rx_desc->ds_cc = cpu_to_le16(0);
256 rx_desc->dptr = cpu_to_le32(dma_addr);
257 rx_desc->die_dt = DT_FEMPTY;
258 }
259 rx_desc = &priv->rx_ring[q][i];
260 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
261 rx_desc->die_dt = DT_LINKFIX; /* type */
262
263 memset(priv->tx_ring[q], 0, tx_ring_size);
264 /* Build TX ring buffer */
265 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
266 i++, tx_desc++) {
267 tx_desc->die_dt = DT_EEMPTY;
268 tx_desc++;
269 tx_desc->die_dt = DT_EEMPTY;
270 }
271 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
272 tx_desc->die_dt = DT_LINKFIX; /* type */
273
274 /* RX descriptor base address for best effort */
275 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
276 desc->die_dt = DT_LINKFIX; /* type */
277 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
278
279 /* TX descriptor base address for best effort */
280 desc = &priv->desc_bat[q];
281 desc->die_dt = DT_LINKFIX; /* type */
282 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
283 }
284
285 /* Init skb and descriptor buffer for Ethernet AVB */
286 static int ravb_ring_init(struct net_device *ndev, int q)
287 {
288 struct ravb_private *priv = netdev_priv(ndev);
289 struct sk_buff *skb;
290 int ring_size;
291 int i;
292
293 /* Allocate RX and TX skb rings */
294 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
295 sizeof(*priv->rx_skb[q]), GFP_KERNEL);
296 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
297 sizeof(*priv->tx_skb[q]), GFP_KERNEL);
298 if (!priv->rx_skb[q] || !priv->tx_skb[q])
299 goto error;
300
301 for (i = 0; i < priv->num_rx_ring[q]; i++) {
302 skb = netdev_alloc_skb(ndev, PKT_BUF_SZ + RAVB_ALIGN - 1);
303 if (!skb)
304 goto error;
305 ravb_set_buffer_align(skb);
306 priv->rx_skb[q][i] = skb;
307 }
308
309 /* Allocate rings for the aligned buffers */
310 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
311 DPTR_ALIGN - 1, GFP_KERNEL);
312 if (!priv->tx_align[q])
313 goto error;
314
315 /* Allocate all RX descriptors. */
316 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
317 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
318 &priv->rx_desc_dma[q],
319 GFP_KERNEL);
320 if (!priv->rx_ring[q])
321 goto error;
322
323 priv->dirty_rx[q] = 0;
324
325 /* Allocate all TX descriptors. */
326 ring_size = sizeof(struct ravb_tx_desc) *
327 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
328 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
329 &priv->tx_desc_dma[q],
330 GFP_KERNEL);
331 if (!priv->tx_ring[q])
332 goto error;
333
334 return 0;
335
336 error:
337 ravb_ring_free(ndev, q);
338
339 return -ENOMEM;
340 }
341
342 /* E-MAC init function */
343 static void ravb_emac_init(struct net_device *ndev)
344 {
345 struct ravb_private *priv = netdev_priv(ndev);
346 u32 ecmr;
347
348 /* Receive frame limit set register */
349 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
350
351 /* PAUSE prohibition */
352 ecmr = ravb_read(ndev, ECMR);
353 ecmr &= ECMR_DM;
354 ecmr |= ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
355 ravb_write(ndev, ecmr, ECMR);
356
357 ravb_set_rate(ndev);
358
359 /* Set MAC address */
360 ravb_write(ndev,
361 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
362 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
363 ravb_write(ndev,
364 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
365
366 ravb_write(ndev, 1, MPR);
367
368 /* E-MAC status register clear */
369 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
370
371 /* E-MAC interrupt enable register */
372 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
373 }
374
375 /* Device init function for Ethernet AVB */
376 static int ravb_dmac_init(struct net_device *ndev)
377 {
378 int error;
379
380 /* Set CONFIG mode */
381 error = ravb_config(ndev);
382 if (error)
383 return error;
384
385 error = ravb_ring_init(ndev, RAVB_BE);
386 if (error)
387 return error;
388 error = ravb_ring_init(ndev, RAVB_NC);
389 if (error) {
390 ravb_ring_free(ndev, RAVB_BE);
391 return error;
392 }
393
394 /* Descriptor format */
395 ravb_ring_format(ndev, RAVB_BE);
396 ravb_ring_format(ndev, RAVB_NC);
397
398 #if defined(__LITTLE_ENDIAN)
399 ravb_write(ndev, ravb_read(ndev, CCC) & ~CCC_BOC, CCC);
400 #else
401 ravb_write(ndev, ravb_read(ndev, CCC) | CCC_BOC, CCC);
402 #endif
403
404 /* Set AVB RX */
405 ravb_write(ndev, RCR_EFFS | RCR_ENCF | RCR_ETS0 | 0x18000000, RCR);
406
407 /* Set FIFO size */
408 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC);
409
410 /* Timestamp enable */
411 ravb_write(ndev, TCCR_TFEN, TCCR);
412
413 /* Interrupt init: */
414 /* Frame receive */
415 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
416 /* Disable FIFO full warning */
417 ravb_write(ndev, 0, RIC1);
418 /* Receive FIFO full error, descriptor empty */
419 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
420 /* Frame transmitted, timestamp FIFO updated */
421 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
422
423 /* Setting the control will start the AVB-DMAC process. */
424 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_OPERATION,
425 CCC);
426
427 return 0;
428 }
429
430 /* Free TX skb function for AVB-IP */
431 static int ravb_tx_free(struct net_device *ndev, int q)
432 {
433 struct ravb_private *priv = netdev_priv(ndev);
434 struct net_device_stats *stats = &priv->stats[q];
435 struct ravb_tx_desc *desc;
436 int free_num = 0;
437 int entry;
438 u32 size;
439
440 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
441 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
442 NUM_TX_DESC);
443 desc = &priv->tx_ring[q][entry];
444 if (desc->die_dt != DT_FEMPTY)
445 break;
446 /* Descriptor type must be checked before all other reads */
447 dma_rmb();
448 size = le16_to_cpu(desc->ds_tagl) & TX_DS;
449 /* Free the original skb. */
450 if (priv->tx_skb[q][entry / NUM_TX_DESC]) {
451 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
452 size, DMA_TO_DEVICE);
453 /* Last packet descriptor? */
454 if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) {
455 entry /= NUM_TX_DESC;
456 dev_kfree_skb_any(priv->tx_skb[q][entry]);
457 priv->tx_skb[q][entry] = NULL;
458 stats->tx_packets++;
459 }
460 free_num++;
461 }
462 stats->tx_bytes += size;
463 desc->die_dt = DT_EEMPTY;
464 }
465 return free_num;
466 }
467
468 static void ravb_get_tx_tstamp(struct net_device *ndev)
469 {
470 struct ravb_private *priv = netdev_priv(ndev);
471 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
472 struct skb_shared_hwtstamps shhwtstamps;
473 struct sk_buff *skb;
474 struct timespec64 ts;
475 u16 tag, tfa_tag;
476 int count;
477 u32 tfa2;
478
479 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
480 while (count--) {
481 tfa2 = ravb_read(ndev, TFA2);
482 tfa_tag = (tfa2 & TFA2_TST) >> 16;
483 ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
484 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
485 ravb_read(ndev, TFA1);
486 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
487 shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
488 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
489 list) {
490 skb = ts_skb->skb;
491 tag = ts_skb->tag;
492 list_del(&ts_skb->list);
493 kfree(ts_skb);
494 if (tag == tfa_tag) {
495 skb_tstamp_tx(skb, &shhwtstamps);
496 break;
497 }
498 }
499 ravb_write(ndev, ravb_read(ndev, TCCR) | TCCR_TFR, TCCR);
500 }
501 }
502
503 /* Packet receive function for Ethernet AVB */
504 static bool ravb_rx(struct net_device *ndev, int *quota, int q)
505 {
506 struct ravb_private *priv = netdev_priv(ndev);
507 int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
508 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
509 priv->cur_rx[q];
510 struct net_device_stats *stats = &priv->stats[q];
511 struct ravb_ex_rx_desc *desc;
512 struct sk_buff *skb;
513 dma_addr_t dma_addr;
514 struct timespec64 ts;
515 u8 desc_status;
516 u16 pkt_len;
517 int limit;
518
519 boguscnt = min(boguscnt, *quota);
520 limit = boguscnt;
521 desc = &priv->rx_ring[q][entry];
522 while (desc->die_dt != DT_FEMPTY) {
523 /* Descriptor type must be checked before all other reads */
524 dma_rmb();
525 desc_status = desc->msc;
526 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
527
528 if (--boguscnt < 0)
529 break;
530
531 /* We use 0-byte descriptors to mark the DMA mapping errors */
532 if (!pkt_len)
533 continue;
534
535 if (desc_status & MSC_MC)
536 stats->multicast++;
537
538 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
539 MSC_CEEF)) {
540 stats->rx_errors++;
541 if (desc_status & MSC_CRC)
542 stats->rx_crc_errors++;
543 if (desc_status & MSC_RFE)
544 stats->rx_frame_errors++;
545 if (desc_status & (MSC_RTLF | MSC_RTSF))
546 stats->rx_length_errors++;
547 if (desc_status & MSC_CEEF)
548 stats->rx_missed_errors++;
549 } else {
550 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
551
552 skb = priv->rx_skb[q][entry];
553 priv->rx_skb[q][entry] = NULL;
554 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
555 ALIGN(PKT_BUF_SZ, 16),
556 DMA_FROM_DEVICE);
557 get_ts &= (q == RAVB_NC) ?
558 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
559 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
560 if (get_ts) {
561 struct skb_shared_hwtstamps *shhwtstamps;
562
563 shhwtstamps = skb_hwtstamps(skb);
564 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
565 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
566 32) | le32_to_cpu(desc->ts_sl);
567 ts.tv_nsec = le32_to_cpu(desc->ts_n);
568 shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
569 }
570 skb_put(skb, pkt_len);
571 skb->protocol = eth_type_trans(skb, ndev);
572 napi_gro_receive(&priv->napi[q], skb);
573 stats->rx_packets++;
574 stats->rx_bytes += pkt_len;
575 }
576
577 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
578 desc = &priv->rx_ring[q][entry];
579 }
580
581 /* Refill the RX ring buffers. */
582 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
583 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
584 desc = &priv->rx_ring[q][entry];
585 /* The size of the buffer should be on 16-byte boundary. */
586 desc->ds_cc = cpu_to_le16(ALIGN(PKT_BUF_SZ, 16));
587
588 if (!priv->rx_skb[q][entry]) {
589 skb = netdev_alloc_skb(ndev,
590 PKT_BUF_SZ + RAVB_ALIGN - 1);
591 if (!skb)
592 break; /* Better luck next round. */
593 ravb_set_buffer_align(skb);
594 dma_addr = dma_map_single(ndev->dev.parent, skb->data,
595 le16_to_cpu(desc->ds_cc),
596 DMA_FROM_DEVICE);
597 skb_checksum_none_assert(skb);
598 /* We just set the data size to 0 for a failed mapping
599 * which should prevent DMA from happening...
600 */
601 if (dma_mapping_error(ndev->dev.parent, dma_addr))
602 desc->ds_cc = cpu_to_le16(0);
603 desc->dptr = cpu_to_le32(dma_addr);
604 priv->rx_skb[q][entry] = skb;
605 }
606 /* Descriptor type must be set after all the above writes */
607 dma_wmb();
608 desc->die_dt = DT_FEMPTY;
609 }
610
611 *quota -= limit - (++boguscnt);
612
613 return boguscnt <= 0;
614 }
615
616 static void ravb_rcv_snd_disable(struct net_device *ndev)
617 {
618 /* Disable TX and RX */
619 ravb_write(ndev, ravb_read(ndev, ECMR) & ~(ECMR_RE | ECMR_TE), ECMR);
620 }
621
622 static void ravb_rcv_snd_enable(struct net_device *ndev)
623 {
624 /* Enable TX and RX */
625 ravb_write(ndev, ravb_read(ndev, ECMR) | ECMR_RE | ECMR_TE, ECMR);
626 }
627
628 /* function for waiting dma process finished */
629 static int ravb_stop_dma(struct net_device *ndev)
630 {
631 int error;
632
633 /* Wait for stopping the hardware TX process */
634 error = ravb_wait(ndev, TCCR,
635 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0);
636 if (error)
637 return error;
638
639 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
640 0);
641 if (error)
642 return error;
643
644 /* Stop the E-MAC's RX/TX processes. */
645 ravb_rcv_snd_disable(ndev);
646
647 /* Wait for stopping the RX DMA process */
648 error = ravb_wait(ndev, CSR, CSR_RPO, 0);
649 if (error)
650 return error;
651
652 /* Stop AVB-DMAC process */
653 return ravb_config(ndev);
654 }
655
656 /* E-MAC interrupt handler */
657 static void ravb_emac_interrupt(struct net_device *ndev)
658 {
659 struct ravb_private *priv = netdev_priv(ndev);
660 u32 ecsr, psr;
661
662 ecsr = ravb_read(ndev, ECSR);
663 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */
664 if (ecsr & ECSR_ICD)
665 ndev->stats.tx_carrier_errors++;
666 if (ecsr & ECSR_LCHNG) {
667 /* Link changed */
668 if (priv->no_avb_link)
669 return;
670 psr = ravb_read(ndev, PSR);
671 if (priv->avb_link_active_low)
672 psr ^= PSR_LMON;
673 if (!(psr & PSR_LMON)) {
674 /* DIsable RX and TX */
675 ravb_rcv_snd_disable(ndev);
676 } else {
677 /* Enable RX and TX */
678 ravb_rcv_snd_enable(ndev);
679 }
680 }
681 }
682
683 /* Error interrupt handler */
684 static void ravb_error_interrupt(struct net_device *ndev)
685 {
686 struct ravb_private *priv = netdev_priv(ndev);
687 u32 eis, ris2;
688
689 eis = ravb_read(ndev, EIS);
690 ravb_write(ndev, ~EIS_QFS, EIS);
691 if (eis & EIS_QFS) {
692 ris2 = ravb_read(ndev, RIS2);
693 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF), RIS2);
694
695 /* Receive Descriptor Empty int */
696 if (ris2 & RIS2_QFF0)
697 priv->stats[RAVB_BE].rx_over_errors++;
698
699 /* Receive Descriptor Empty int */
700 if (ris2 & RIS2_QFF1)
701 priv->stats[RAVB_NC].rx_over_errors++;
702
703 /* Receive FIFO Overflow int */
704 if (ris2 & RIS2_RFFF)
705 priv->rx_fifo_errors++;
706 }
707 }
708
709 static irqreturn_t ravb_interrupt(int irq, void *dev_id)
710 {
711 struct net_device *ndev = dev_id;
712 struct ravb_private *priv = netdev_priv(ndev);
713 irqreturn_t result = IRQ_NONE;
714 u32 iss;
715
716 spin_lock(&priv->lock);
717 /* Get interrupt status */
718 iss = ravb_read(ndev, ISS);
719
720 /* Received and transmitted interrupts */
721 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
722 u32 ris0 = ravb_read(ndev, RIS0);
723 u32 ric0 = ravb_read(ndev, RIC0);
724 u32 tis = ravb_read(ndev, TIS);
725 u32 tic = ravb_read(ndev, TIC);
726 int q;
727
728 /* Timestamp updated */
729 if (tis & TIS_TFUF) {
730 ravb_write(ndev, ~TIS_TFUF, TIS);
731 ravb_get_tx_tstamp(ndev);
732 result = IRQ_HANDLED;
733 }
734
735 /* Network control and best effort queue RX/TX */
736 for (q = RAVB_NC; q >= RAVB_BE; q--) {
737 if (((ris0 & ric0) & BIT(q)) ||
738 ((tis & tic) & BIT(q))) {
739 if (napi_schedule_prep(&priv->napi[q])) {
740 /* Mask RX and TX interrupts */
741 ric0 &= ~BIT(q);
742 tic &= ~BIT(q);
743 ravb_write(ndev, ric0, RIC0);
744 ravb_write(ndev, tic, TIC);
745 __napi_schedule(&priv->napi[q]);
746 } else {
747 netdev_warn(ndev,
748 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
749 ris0, ric0);
750 netdev_warn(ndev,
751 " tx status 0x%08x, tx mask 0x%08x.\n",
752 tis, tic);
753 }
754 result = IRQ_HANDLED;
755 }
756 }
757 }
758
759 /* E-MAC status summary */
760 if (iss & ISS_MS) {
761 ravb_emac_interrupt(ndev);
762 result = IRQ_HANDLED;
763 }
764
765 /* Error status summary */
766 if (iss & ISS_ES) {
767 ravb_error_interrupt(ndev);
768 result = IRQ_HANDLED;
769 }
770
771 if (iss & ISS_CGIS)
772 result = ravb_ptp_interrupt(ndev);
773
774 mmiowb();
775 spin_unlock(&priv->lock);
776 return result;
777 }
778
779 static int ravb_poll(struct napi_struct *napi, int budget)
780 {
781 struct net_device *ndev = napi->dev;
782 struct ravb_private *priv = netdev_priv(ndev);
783 unsigned long flags;
784 int q = napi - priv->napi;
785 int mask = BIT(q);
786 int quota = budget;
787 u32 ris0, tis;
788
789 for (;;) {
790 tis = ravb_read(ndev, TIS);
791 ris0 = ravb_read(ndev, RIS0);
792 if (!((ris0 & mask) || (tis & mask)))
793 break;
794
795 /* Processing RX Descriptor Ring */
796 if (ris0 & mask) {
797 /* Clear RX interrupt */
798 ravb_write(ndev, ~mask, RIS0);
799 if (ravb_rx(ndev, &quota, q))
800 goto out;
801 }
802 /* Processing TX Descriptor Ring */
803 if (tis & mask) {
804 spin_lock_irqsave(&priv->lock, flags);
805 /* Clear TX interrupt */
806 ravb_write(ndev, ~mask, TIS);
807 ravb_tx_free(ndev, q);
808 netif_wake_subqueue(ndev, q);
809 mmiowb();
810 spin_unlock_irqrestore(&priv->lock, flags);
811 }
812 }
813
814 napi_complete(napi);
815
816 /* Re-enable RX/TX interrupts */
817 spin_lock_irqsave(&priv->lock, flags);
818 ravb_write(ndev, ravb_read(ndev, RIC0) | mask, RIC0);
819 ravb_write(ndev, ravb_read(ndev, TIC) | mask, TIC);
820 mmiowb();
821 spin_unlock_irqrestore(&priv->lock, flags);
822
823 /* Receive error message handling */
824 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors;
825 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
826 if (priv->rx_over_errors != ndev->stats.rx_over_errors) {
827 ndev->stats.rx_over_errors = priv->rx_over_errors;
828 netif_err(priv, rx_err, ndev, "Receive Descriptor Empty\n");
829 }
830 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) {
831 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
832 netif_err(priv, rx_err, ndev, "Receive FIFO Overflow\n");
833 }
834 out:
835 return budget - quota;
836 }
837
838 /* PHY state control function */
839 static void ravb_adjust_link(struct net_device *ndev)
840 {
841 struct ravb_private *priv = netdev_priv(ndev);
842 struct phy_device *phydev = priv->phydev;
843 bool new_state = false;
844
845 if (phydev->link) {
846 if (phydev->duplex != priv->duplex) {
847 new_state = true;
848 priv->duplex = phydev->duplex;
849 ravb_set_duplex(ndev);
850 }
851
852 if (phydev->speed != priv->speed) {
853 new_state = true;
854 priv->speed = phydev->speed;
855 ravb_set_rate(ndev);
856 }
857 if (!priv->link) {
858 ravb_write(ndev, ravb_read(ndev, ECMR) & ~ECMR_TXF,
859 ECMR);
860 new_state = true;
861 priv->link = phydev->link;
862 if (priv->no_avb_link)
863 ravb_rcv_snd_enable(ndev);
864 }
865 } else if (priv->link) {
866 new_state = true;
867 priv->link = 0;
868 priv->speed = 0;
869 priv->duplex = -1;
870 if (priv->no_avb_link)
871 ravb_rcv_snd_disable(ndev);
872 }
873
874 if (new_state && netif_msg_link(priv))
875 phy_print_status(phydev);
876 }
877
878 /* PHY init function */
879 static int ravb_phy_init(struct net_device *ndev)
880 {
881 struct device_node *np = ndev->dev.parent->of_node;
882 struct ravb_private *priv = netdev_priv(ndev);
883 struct phy_device *phydev;
884 struct device_node *pn;
885 int err;
886
887 priv->link = 0;
888 priv->speed = 0;
889 priv->duplex = -1;
890
891 /* Try connecting to PHY */
892 pn = of_parse_phandle(np, "phy-handle", 0);
893 if (!pn) {
894 /* In the case of a fixed PHY, the DT node associated
895 * to the PHY is the Ethernet MAC DT node.
896 */
897 if (of_phy_is_fixed_link(np)) {
898 err = of_phy_register_fixed_link(np);
899 if (err)
900 return err;
901 }
902 pn = of_node_get(np);
903 }
904 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0,
905 priv->phy_interface);
906 if (!phydev) {
907 netdev_err(ndev, "failed to connect PHY\n");
908 return -ENOENT;
909 }
910
911 /* This driver only support 10/100Mbit speeds on Gen3
912 * at this time.
913 */
914 if (priv->chip_id == RCAR_GEN3) {
915 int err;
916
917 err = phy_set_max_speed(phydev, SPEED_100);
918 if (err) {
919 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n");
920 phy_disconnect(phydev);
921 return err;
922 }
923
924 netdev_info(ndev, "limited PHY to 100Mbit/s\n");
925 }
926
927 /* 10BASE is not supported */
928 phydev->supported &= ~PHY_10BT_FEATURES;
929
930 netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
931 phydev->addr, phydev->irq, phydev_name(phydev));
932
933 priv->phydev = phydev;
934
935 return 0;
936 }
937
938 /* PHY control start function */
939 static int ravb_phy_start(struct net_device *ndev)
940 {
941 struct ravb_private *priv = netdev_priv(ndev);
942 int error;
943
944 error = ravb_phy_init(ndev);
945 if (error)
946 return error;
947
948 phy_start(priv->phydev);
949
950 return 0;
951 }
952
953 static int ravb_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
954 {
955 struct ravb_private *priv = netdev_priv(ndev);
956 int error = -ENODEV;
957 unsigned long flags;
958
959 if (priv->phydev) {
960 spin_lock_irqsave(&priv->lock, flags);
961 error = phy_ethtool_gset(priv->phydev, ecmd);
962 spin_unlock_irqrestore(&priv->lock, flags);
963 }
964
965 return error;
966 }
967
968 static int ravb_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
969 {
970 struct ravb_private *priv = netdev_priv(ndev);
971 unsigned long flags;
972 int error;
973
974 if (!priv->phydev)
975 return -ENODEV;
976
977 spin_lock_irqsave(&priv->lock, flags);
978
979 /* Disable TX and RX */
980 ravb_rcv_snd_disable(ndev);
981
982 error = phy_ethtool_sset(priv->phydev, ecmd);
983 if (error)
984 goto error_exit;
985
986 if (ecmd->duplex == DUPLEX_FULL)
987 priv->duplex = 1;
988 else
989 priv->duplex = 0;
990
991 ravb_set_duplex(ndev);
992
993 error_exit:
994 mdelay(1);
995
996 /* Enable TX and RX */
997 ravb_rcv_snd_enable(ndev);
998
999 mmiowb();
1000 spin_unlock_irqrestore(&priv->lock, flags);
1001
1002 return error;
1003 }
1004
1005 static int ravb_nway_reset(struct net_device *ndev)
1006 {
1007 struct ravb_private *priv = netdev_priv(ndev);
1008 int error = -ENODEV;
1009 unsigned long flags;
1010
1011 if (priv->phydev) {
1012 spin_lock_irqsave(&priv->lock, flags);
1013 error = phy_start_aneg(priv->phydev);
1014 spin_unlock_irqrestore(&priv->lock, flags);
1015 }
1016
1017 return error;
1018 }
1019
1020 static u32 ravb_get_msglevel(struct net_device *ndev)
1021 {
1022 struct ravb_private *priv = netdev_priv(ndev);
1023
1024 return priv->msg_enable;
1025 }
1026
1027 static void ravb_set_msglevel(struct net_device *ndev, u32 value)
1028 {
1029 struct ravb_private *priv = netdev_priv(ndev);
1030
1031 priv->msg_enable = value;
1032 }
1033
1034 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
1035 "rx_queue_0_current",
1036 "tx_queue_0_current",
1037 "rx_queue_0_dirty",
1038 "tx_queue_0_dirty",
1039 "rx_queue_0_packets",
1040 "tx_queue_0_packets",
1041 "rx_queue_0_bytes",
1042 "tx_queue_0_bytes",
1043 "rx_queue_0_mcast_packets",
1044 "rx_queue_0_errors",
1045 "rx_queue_0_crc_errors",
1046 "rx_queue_0_frame_errors",
1047 "rx_queue_0_length_errors",
1048 "rx_queue_0_missed_errors",
1049 "rx_queue_0_over_errors",
1050
1051 "rx_queue_1_current",
1052 "tx_queue_1_current",
1053 "rx_queue_1_dirty",
1054 "tx_queue_1_dirty",
1055 "rx_queue_1_packets",
1056 "tx_queue_1_packets",
1057 "rx_queue_1_bytes",
1058 "tx_queue_1_bytes",
1059 "rx_queue_1_mcast_packets",
1060 "rx_queue_1_errors",
1061 "rx_queue_1_crc_errors",
1062 "rx_queue_1_frame_errors",
1063 "rx_queue_1_length_errors",
1064 "rx_queue_1_missed_errors",
1065 "rx_queue_1_over_errors",
1066 };
1067
1068 #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats)
1069
1070 static int ravb_get_sset_count(struct net_device *netdev, int sset)
1071 {
1072 switch (sset) {
1073 case ETH_SS_STATS:
1074 return RAVB_STATS_LEN;
1075 default:
1076 return -EOPNOTSUPP;
1077 }
1078 }
1079
1080 static void ravb_get_ethtool_stats(struct net_device *ndev,
1081 struct ethtool_stats *stats, u64 *data)
1082 {
1083 struct ravb_private *priv = netdev_priv(ndev);
1084 int i = 0;
1085 int q;
1086
1087 /* Device-specific stats */
1088 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) {
1089 struct net_device_stats *stats = &priv->stats[q];
1090
1091 data[i++] = priv->cur_rx[q];
1092 data[i++] = priv->cur_tx[q];
1093 data[i++] = priv->dirty_rx[q];
1094 data[i++] = priv->dirty_tx[q];
1095 data[i++] = stats->rx_packets;
1096 data[i++] = stats->tx_packets;
1097 data[i++] = stats->rx_bytes;
1098 data[i++] = stats->tx_bytes;
1099 data[i++] = stats->multicast;
1100 data[i++] = stats->rx_errors;
1101 data[i++] = stats->rx_crc_errors;
1102 data[i++] = stats->rx_frame_errors;
1103 data[i++] = stats->rx_length_errors;
1104 data[i++] = stats->rx_missed_errors;
1105 data[i++] = stats->rx_over_errors;
1106 }
1107 }
1108
1109 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1110 {
1111 switch (stringset) {
1112 case ETH_SS_STATS:
1113 memcpy(data, *ravb_gstrings_stats, sizeof(ravb_gstrings_stats));
1114 break;
1115 }
1116 }
1117
1118 static void ravb_get_ringparam(struct net_device *ndev,
1119 struct ethtool_ringparam *ring)
1120 {
1121 struct ravb_private *priv = netdev_priv(ndev);
1122
1123 ring->rx_max_pending = BE_RX_RING_MAX;
1124 ring->tx_max_pending = BE_TX_RING_MAX;
1125 ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1126 ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1127 }
1128
1129 static int ravb_set_ringparam(struct net_device *ndev,
1130 struct ethtool_ringparam *ring)
1131 {
1132 struct ravb_private *priv = netdev_priv(ndev);
1133 int error;
1134
1135 if (ring->tx_pending > BE_TX_RING_MAX ||
1136 ring->rx_pending > BE_RX_RING_MAX ||
1137 ring->tx_pending < BE_TX_RING_MIN ||
1138 ring->rx_pending < BE_RX_RING_MIN)
1139 return -EINVAL;
1140 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1141 return -EINVAL;
1142
1143 if (netif_running(ndev)) {
1144 netif_device_detach(ndev);
1145 /* Stop PTP Clock driver */
1146 ravb_ptp_stop(ndev);
1147 /* Wait for DMA stopping */
1148 error = ravb_stop_dma(ndev);
1149 if (error) {
1150 netdev_err(ndev,
1151 "cannot set ringparam! Any AVB processes are still running?\n");
1152 return error;
1153 }
1154 synchronize_irq(ndev->irq);
1155
1156 /* Free all the skb's in the RX queue and the DMA buffers. */
1157 ravb_ring_free(ndev, RAVB_BE);
1158 ravb_ring_free(ndev, RAVB_NC);
1159 }
1160
1161 /* Set new parameters */
1162 priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1163 priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1164
1165 if (netif_running(ndev)) {
1166 error = ravb_dmac_init(ndev);
1167 if (error) {
1168 netdev_err(ndev,
1169 "%s: ravb_dmac_init() failed, error %d\n",
1170 __func__, error);
1171 return error;
1172 }
1173
1174 ravb_emac_init(ndev);
1175
1176 /* Initialise PTP Clock driver */
1177 ravb_ptp_init(ndev, priv->pdev);
1178
1179 netif_device_attach(ndev);
1180 }
1181
1182 return 0;
1183 }
1184
1185 static int ravb_get_ts_info(struct net_device *ndev,
1186 struct ethtool_ts_info *info)
1187 {
1188 struct ravb_private *priv = netdev_priv(ndev);
1189
1190 info->so_timestamping =
1191 SOF_TIMESTAMPING_TX_SOFTWARE |
1192 SOF_TIMESTAMPING_RX_SOFTWARE |
1193 SOF_TIMESTAMPING_SOFTWARE |
1194 SOF_TIMESTAMPING_TX_HARDWARE |
1195 SOF_TIMESTAMPING_RX_HARDWARE |
1196 SOF_TIMESTAMPING_RAW_HARDWARE;
1197 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1198 info->rx_filters =
1199 (1 << HWTSTAMP_FILTER_NONE) |
1200 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1201 (1 << HWTSTAMP_FILTER_ALL);
1202 info->phc_index = ptp_clock_index(priv->ptp.clock);
1203
1204 return 0;
1205 }
1206
1207 static const struct ethtool_ops ravb_ethtool_ops = {
1208 .get_settings = ravb_get_settings,
1209 .set_settings = ravb_set_settings,
1210 .nway_reset = ravb_nway_reset,
1211 .get_msglevel = ravb_get_msglevel,
1212 .set_msglevel = ravb_set_msglevel,
1213 .get_link = ethtool_op_get_link,
1214 .get_strings = ravb_get_strings,
1215 .get_ethtool_stats = ravb_get_ethtool_stats,
1216 .get_sset_count = ravb_get_sset_count,
1217 .get_ringparam = ravb_get_ringparam,
1218 .set_ringparam = ravb_set_ringparam,
1219 .get_ts_info = ravb_get_ts_info,
1220 };
1221
1222 /* Network device open function for Ethernet AVB */
1223 static int ravb_open(struct net_device *ndev)
1224 {
1225 struct ravb_private *priv = netdev_priv(ndev);
1226 int error;
1227
1228 napi_enable(&priv->napi[RAVB_BE]);
1229 napi_enable(&priv->napi[RAVB_NC]);
1230
1231 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, ndev->name,
1232 ndev);
1233 if (error) {
1234 netdev_err(ndev, "cannot request IRQ\n");
1235 goto out_napi_off;
1236 }
1237
1238 if (priv->chip_id == RCAR_GEN3) {
1239 error = request_irq(priv->emac_irq, ravb_interrupt,
1240 IRQF_SHARED, ndev->name, ndev);
1241 if (error) {
1242 netdev_err(ndev, "cannot request IRQ\n");
1243 goto out_free_irq;
1244 }
1245 }
1246
1247 /* Device init */
1248 error = ravb_dmac_init(ndev);
1249 if (error)
1250 goto out_free_irq2;
1251 ravb_emac_init(ndev);
1252
1253 /* Initialise PTP Clock driver */
1254 if (priv->chip_id == RCAR_GEN2)
1255 ravb_ptp_init(ndev, priv->pdev);
1256
1257 netif_tx_start_all_queues(ndev);
1258
1259 /* PHY control start */
1260 error = ravb_phy_start(ndev);
1261 if (error)
1262 goto out_ptp_stop;
1263
1264 return 0;
1265
1266 out_ptp_stop:
1267 /* Stop PTP Clock driver */
1268 if (priv->chip_id == RCAR_GEN2)
1269 ravb_ptp_stop(ndev);
1270 out_free_irq2:
1271 if (priv->chip_id == RCAR_GEN3)
1272 free_irq(priv->emac_irq, ndev);
1273 out_free_irq:
1274 free_irq(ndev->irq, ndev);
1275 out_napi_off:
1276 napi_disable(&priv->napi[RAVB_NC]);
1277 napi_disable(&priv->napi[RAVB_BE]);
1278 return error;
1279 }
1280
1281 /* Timeout function for Ethernet AVB */
1282 static void ravb_tx_timeout(struct net_device *ndev)
1283 {
1284 struct ravb_private *priv = netdev_priv(ndev);
1285
1286 netif_err(priv, tx_err, ndev,
1287 "transmit timed out, status %08x, resetting...\n",
1288 ravb_read(ndev, ISS));
1289
1290 /* tx_errors count up */
1291 ndev->stats.tx_errors++;
1292
1293 schedule_work(&priv->work);
1294 }
1295
1296 static void ravb_tx_timeout_work(struct work_struct *work)
1297 {
1298 struct ravb_private *priv = container_of(work, struct ravb_private,
1299 work);
1300 struct net_device *ndev = priv->ndev;
1301
1302 netif_tx_stop_all_queues(ndev);
1303
1304 /* Stop PTP Clock driver */
1305 ravb_ptp_stop(ndev);
1306
1307 /* Wait for DMA stopping */
1308 ravb_stop_dma(ndev);
1309
1310 ravb_ring_free(ndev, RAVB_BE);
1311 ravb_ring_free(ndev, RAVB_NC);
1312
1313 /* Device init */
1314 ravb_dmac_init(ndev);
1315 ravb_emac_init(ndev);
1316
1317 /* Initialise PTP Clock driver */
1318 ravb_ptp_init(ndev, priv->pdev);
1319
1320 netif_tx_start_all_queues(ndev);
1321 }
1322
1323 /* Packet transmit function for Ethernet AVB */
1324 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1325 {
1326 struct ravb_private *priv = netdev_priv(ndev);
1327 u16 q = skb_get_queue_mapping(skb);
1328 struct ravb_tstamp_skb *ts_skb;
1329 struct ravb_tx_desc *desc;
1330 unsigned long flags;
1331 u32 dma_addr;
1332 void *buffer;
1333 u32 entry;
1334 u32 len;
1335
1336 spin_lock_irqsave(&priv->lock, flags);
1337 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
1338 NUM_TX_DESC) {
1339 netif_err(priv, tx_queued, ndev,
1340 "still transmitting with the full ring!\n");
1341 netif_stop_subqueue(ndev, q);
1342 spin_unlock_irqrestore(&priv->lock, flags);
1343 return NETDEV_TX_BUSY;
1344 }
1345 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC);
1346 priv->tx_skb[q][entry / NUM_TX_DESC] = skb;
1347
1348 if (skb_put_padto(skb, ETH_ZLEN))
1349 goto drop;
1350
1351 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
1352 entry / NUM_TX_DESC * DPTR_ALIGN;
1353 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
1354 memcpy(buffer, skb->data, len);
1355 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1356 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1357 goto drop;
1358
1359 desc = &priv->tx_ring[q][entry];
1360 desc->ds_tagl = cpu_to_le16(len);
1361 desc->dptr = cpu_to_le32(dma_addr);
1362
1363 buffer = skb->data + len;
1364 len = skb->len - len;
1365 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1366 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1367 goto unmap;
1368
1369 desc++;
1370 desc->ds_tagl = cpu_to_le16(len);
1371 desc->dptr = cpu_to_le32(dma_addr);
1372
1373 /* TX timestamp required */
1374 if (q == RAVB_NC) {
1375 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
1376 if (!ts_skb) {
1377 desc--;
1378 dma_unmap_single(ndev->dev.parent, dma_addr, len,
1379 DMA_TO_DEVICE);
1380 goto unmap;
1381 }
1382 ts_skb->skb = skb;
1383 ts_skb->tag = priv->ts_skb_tag++;
1384 priv->ts_skb_tag &= 0x3ff;
1385 list_add_tail(&ts_skb->list, &priv->ts_skb_list);
1386
1387 /* TAG and timestamp required flag */
1388 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1389 skb_tx_timestamp(skb);
1390 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
1391 desc->ds_tagl |= le16_to_cpu(ts_skb->tag << 12);
1392 }
1393
1394 /* Descriptor type must be set after all the above writes */
1395 dma_wmb();
1396 desc->die_dt = DT_FEND;
1397 desc--;
1398 desc->die_dt = DT_FSTART;
1399
1400 ravb_write(ndev, ravb_read(ndev, TCCR) | (TCCR_TSRQ0 << q), TCCR);
1401
1402 priv->cur_tx[q] += NUM_TX_DESC;
1403 if (priv->cur_tx[q] - priv->dirty_tx[q] >
1404 (priv->num_tx_ring[q] - 1) * NUM_TX_DESC && !ravb_tx_free(ndev, q))
1405 netif_stop_subqueue(ndev, q);
1406
1407 exit:
1408 mmiowb();
1409 spin_unlock_irqrestore(&priv->lock, flags);
1410 return NETDEV_TX_OK;
1411
1412 unmap:
1413 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
1414 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
1415 drop:
1416 dev_kfree_skb_any(skb);
1417 priv->tx_skb[q][entry / NUM_TX_DESC] = NULL;
1418 goto exit;
1419 }
1420
1421 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
1422 void *accel_priv, select_queue_fallback_t fallback)
1423 {
1424 /* If skb needs TX timestamp, it is handled in network control queue */
1425 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
1426 RAVB_BE;
1427
1428 }
1429
1430 static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
1431 {
1432 struct ravb_private *priv = netdev_priv(ndev);
1433 struct net_device_stats *nstats, *stats0, *stats1;
1434
1435 nstats = &ndev->stats;
1436 stats0 = &priv->stats[RAVB_BE];
1437 stats1 = &priv->stats[RAVB_NC];
1438
1439 nstats->tx_dropped += ravb_read(ndev, TROCR);
1440 ravb_write(ndev, 0, TROCR); /* (write clear) */
1441 nstats->collisions += ravb_read(ndev, CDCR);
1442 ravb_write(ndev, 0, CDCR); /* (write clear) */
1443 nstats->tx_carrier_errors += ravb_read(ndev, LCCR);
1444 ravb_write(ndev, 0, LCCR); /* (write clear) */
1445
1446 nstats->tx_carrier_errors += ravb_read(ndev, CERCR);
1447 ravb_write(ndev, 0, CERCR); /* (write clear) */
1448 nstats->tx_carrier_errors += ravb_read(ndev, CEECR);
1449 ravb_write(ndev, 0, CEECR); /* (write clear) */
1450
1451 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets;
1452 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets;
1453 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes;
1454 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes;
1455 nstats->multicast = stats0->multicast + stats1->multicast;
1456 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors;
1457 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors;
1458 nstats->rx_frame_errors =
1459 stats0->rx_frame_errors + stats1->rx_frame_errors;
1460 nstats->rx_length_errors =
1461 stats0->rx_length_errors + stats1->rx_length_errors;
1462 nstats->rx_missed_errors =
1463 stats0->rx_missed_errors + stats1->rx_missed_errors;
1464 nstats->rx_over_errors =
1465 stats0->rx_over_errors + stats1->rx_over_errors;
1466
1467 return nstats;
1468 }
1469
1470 /* Update promiscuous bit */
1471 static void ravb_set_rx_mode(struct net_device *ndev)
1472 {
1473 struct ravb_private *priv = netdev_priv(ndev);
1474 unsigned long flags;
1475 u32 ecmr;
1476
1477 spin_lock_irqsave(&priv->lock, flags);
1478 ecmr = ravb_read(ndev, ECMR);
1479 if (ndev->flags & IFF_PROMISC)
1480 ecmr |= ECMR_PRM;
1481 else
1482 ecmr &= ~ECMR_PRM;
1483 ravb_write(ndev, ecmr, ECMR);
1484 mmiowb();
1485 spin_unlock_irqrestore(&priv->lock, flags);
1486 }
1487
1488 /* Device close function for Ethernet AVB */
1489 static int ravb_close(struct net_device *ndev)
1490 {
1491 struct ravb_private *priv = netdev_priv(ndev);
1492 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
1493
1494 netif_tx_stop_all_queues(ndev);
1495
1496 /* Disable interrupts by clearing the interrupt masks. */
1497 ravb_write(ndev, 0, RIC0);
1498 ravb_write(ndev, 0, RIC2);
1499 ravb_write(ndev, 0, TIC);
1500
1501 /* Stop PTP Clock driver */
1502 if (priv->chip_id == RCAR_GEN2)
1503 ravb_ptp_stop(ndev);
1504
1505 /* Set the config mode to stop the AVB-DMAC's processes */
1506 if (ravb_stop_dma(ndev) < 0)
1507 netdev_err(ndev,
1508 "device will be stopped after h/w processes are done.\n");
1509
1510 /* Clear the timestamp list */
1511 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
1512 list_del(&ts_skb->list);
1513 kfree(ts_skb);
1514 }
1515
1516 /* PHY disconnect */
1517 if (priv->phydev) {
1518 phy_stop(priv->phydev);
1519 phy_disconnect(priv->phydev);
1520 priv->phydev = NULL;
1521 }
1522
1523 free_irq(ndev->irq, ndev);
1524
1525 napi_disable(&priv->napi[RAVB_NC]);
1526 napi_disable(&priv->napi[RAVB_BE]);
1527
1528 /* Free all the skb's in the RX queue and the DMA buffers. */
1529 ravb_ring_free(ndev, RAVB_BE);
1530 ravb_ring_free(ndev, RAVB_NC);
1531
1532 return 0;
1533 }
1534
1535 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
1536 {
1537 struct ravb_private *priv = netdev_priv(ndev);
1538 struct hwtstamp_config config;
1539
1540 config.flags = 0;
1541 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
1542 HWTSTAMP_TX_OFF;
1543 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT)
1544 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1545 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL)
1546 config.rx_filter = HWTSTAMP_FILTER_ALL;
1547 else
1548 config.rx_filter = HWTSTAMP_FILTER_NONE;
1549
1550 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1551 -EFAULT : 0;
1552 }
1553
1554 /* Control hardware time stamping */
1555 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
1556 {
1557 struct ravb_private *priv = netdev_priv(ndev);
1558 struct hwtstamp_config config;
1559 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
1560 u32 tstamp_tx_ctrl;
1561
1562 if (copy_from_user(&config, req->ifr_data, sizeof(config)))
1563 return -EFAULT;
1564
1565 /* Reserved for future extensions */
1566 if (config.flags)
1567 return -EINVAL;
1568
1569 switch (config.tx_type) {
1570 case HWTSTAMP_TX_OFF:
1571 tstamp_tx_ctrl = 0;
1572 break;
1573 case HWTSTAMP_TX_ON:
1574 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
1575 break;
1576 default:
1577 return -ERANGE;
1578 }
1579
1580 switch (config.rx_filter) {
1581 case HWTSTAMP_FILTER_NONE:
1582 tstamp_rx_ctrl = 0;
1583 break;
1584 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1585 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
1586 break;
1587 default:
1588 config.rx_filter = HWTSTAMP_FILTER_ALL;
1589 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
1590 }
1591
1592 priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
1593 priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
1594
1595 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1596 -EFAULT : 0;
1597 }
1598
1599 /* ioctl to device function */
1600 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
1601 {
1602 struct ravb_private *priv = netdev_priv(ndev);
1603 struct phy_device *phydev = priv->phydev;
1604
1605 if (!netif_running(ndev))
1606 return -EINVAL;
1607
1608 if (!phydev)
1609 return -ENODEV;
1610
1611 switch (cmd) {
1612 case SIOCGHWTSTAMP:
1613 return ravb_hwtstamp_get(ndev, req);
1614 case SIOCSHWTSTAMP:
1615 return ravb_hwtstamp_set(ndev, req);
1616 }
1617
1618 return phy_mii_ioctl(phydev, req, cmd);
1619 }
1620
1621 static const struct net_device_ops ravb_netdev_ops = {
1622 .ndo_open = ravb_open,
1623 .ndo_stop = ravb_close,
1624 .ndo_start_xmit = ravb_start_xmit,
1625 .ndo_select_queue = ravb_select_queue,
1626 .ndo_get_stats = ravb_get_stats,
1627 .ndo_set_rx_mode = ravb_set_rx_mode,
1628 .ndo_tx_timeout = ravb_tx_timeout,
1629 .ndo_do_ioctl = ravb_do_ioctl,
1630 .ndo_validate_addr = eth_validate_addr,
1631 .ndo_set_mac_address = eth_mac_addr,
1632 .ndo_change_mtu = eth_change_mtu,
1633 };
1634
1635 /* MDIO bus init function */
1636 static int ravb_mdio_init(struct ravb_private *priv)
1637 {
1638 struct platform_device *pdev = priv->pdev;
1639 struct device *dev = &pdev->dev;
1640 int error;
1641
1642 /* Bitbang init */
1643 priv->mdiobb.ops = &bb_ops;
1644
1645 /* MII controller setting */
1646 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
1647 if (!priv->mii_bus)
1648 return -ENOMEM;
1649
1650 /* Hook up MII support for ethtool */
1651 priv->mii_bus->name = "ravb_mii";
1652 priv->mii_bus->parent = dev;
1653 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1654 pdev->name, pdev->id);
1655
1656 /* Register MDIO bus */
1657 error = of_mdiobus_register(priv->mii_bus, dev->of_node);
1658 if (error)
1659 goto out_free_bus;
1660
1661 return 0;
1662
1663 out_free_bus:
1664 free_mdio_bitbang(priv->mii_bus);
1665 return error;
1666 }
1667
1668 /* MDIO bus release function */
1669 static int ravb_mdio_release(struct ravb_private *priv)
1670 {
1671 /* Unregister mdio bus */
1672 mdiobus_unregister(priv->mii_bus);
1673
1674 /* Free bitbang info */
1675 free_mdio_bitbang(priv->mii_bus);
1676
1677 return 0;
1678 }
1679
1680 static const struct of_device_id ravb_match_table[] = {
1681 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 },
1682 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 },
1683 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 },
1684 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 },
1685 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 },
1686 { }
1687 };
1688 MODULE_DEVICE_TABLE(of, ravb_match_table);
1689
1690 static int ravb_set_gti(struct net_device *ndev)
1691 {
1692
1693 struct device *dev = ndev->dev.parent;
1694 struct device_node *np = dev->of_node;
1695 unsigned long rate;
1696 struct clk *clk;
1697 uint64_t inc;
1698
1699 clk = of_clk_get(np, 0);
1700 if (IS_ERR(clk)) {
1701 dev_err(dev, "could not get clock\n");
1702 return PTR_ERR(clk);
1703 }
1704
1705 rate = clk_get_rate(clk);
1706 clk_put(clk);
1707
1708 inc = 1000000000ULL << 20;
1709 do_div(inc, rate);
1710
1711 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) {
1712 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n",
1713 inc, GTI_TIV_MIN, GTI_TIV_MAX);
1714 return -EINVAL;
1715 }
1716
1717 ravb_write(ndev, inc, GTI);
1718
1719 return 0;
1720 }
1721
1722 static int ravb_probe(struct platform_device *pdev)
1723 {
1724 struct device_node *np = pdev->dev.of_node;
1725 const struct of_device_id *match;
1726 struct ravb_private *priv;
1727 enum ravb_chip_id chip_id;
1728 struct net_device *ndev;
1729 int error, irq, q;
1730 struct resource *res;
1731
1732 if (!np) {
1733 dev_err(&pdev->dev,
1734 "this driver is required to be instantiated from device tree\n");
1735 return -EINVAL;
1736 }
1737
1738 /* Get base address */
1739 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1740 if (!res) {
1741 dev_err(&pdev->dev, "invalid resource\n");
1742 return -EINVAL;
1743 }
1744
1745 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
1746 NUM_TX_QUEUE, NUM_RX_QUEUE);
1747 if (!ndev)
1748 return -ENOMEM;
1749
1750 pm_runtime_enable(&pdev->dev);
1751 pm_runtime_get_sync(&pdev->dev);
1752
1753 /* The Ether-specific entries in the device structure. */
1754 ndev->base_addr = res->start;
1755 ndev->dma = -1;
1756
1757 match = of_match_device(of_match_ptr(ravb_match_table), &pdev->dev);
1758 chip_id = (enum ravb_chip_id)match->data;
1759
1760 if (chip_id == RCAR_GEN3)
1761 irq = platform_get_irq_byname(pdev, "ch22");
1762 else
1763 irq = platform_get_irq(pdev, 0);
1764 if (irq < 0) {
1765 error = irq;
1766 goto out_release;
1767 }
1768 ndev->irq = irq;
1769
1770 SET_NETDEV_DEV(ndev, &pdev->dev);
1771
1772 priv = netdev_priv(ndev);
1773 priv->ndev = ndev;
1774 priv->pdev = pdev;
1775 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
1776 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
1777 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
1778 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
1779 priv->addr = devm_ioremap_resource(&pdev->dev, res);
1780 if (IS_ERR(priv->addr)) {
1781 error = PTR_ERR(priv->addr);
1782 goto out_release;
1783 }
1784
1785 spin_lock_init(&priv->lock);
1786 INIT_WORK(&priv->work, ravb_tx_timeout_work);
1787
1788 priv->phy_interface = of_get_phy_mode(np);
1789
1790 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
1791 priv->avb_link_active_low =
1792 of_property_read_bool(np, "renesas,ether-link-active-low");
1793
1794 if (chip_id == RCAR_GEN3) {
1795 irq = platform_get_irq_byname(pdev, "ch24");
1796 if (irq < 0) {
1797 error = irq;
1798 goto out_release;
1799 }
1800 priv->emac_irq = irq;
1801 }
1802
1803 priv->chip_id = chip_id;
1804
1805 /* Set function */
1806 ndev->netdev_ops = &ravb_netdev_ops;
1807 ndev->ethtool_ops = &ravb_ethtool_ops;
1808
1809 /* Set AVB config mode */
1810 if (chip_id == RCAR_GEN2) {
1811 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) |
1812 CCC_OPC_CONFIG, CCC);
1813 /* Set CSEL value */
1814 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_CSEL) |
1815 CCC_CSEL_HPB, CCC);
1816 } else {
1817 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) |
1818 CCC_OPC_CONFIG | CCC_GAC | CCC_CSEL_HPB, CCC);
1819 }
1820
1821 /* Set CSEL value */
1822 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_CSEL) | CCC_CSEL_HPB,
1823 CCC);
1824
1825 /* Set GTI value */
1826 error = ravb_set_gti(ndev);
1827 if (error)
1828 goto out_release;
1829
1830 /* Request GTI loading */
1831 ravb_write(ndev, ravb_read(ndev, GCCR) | GCCR_LTI, GCCR);
1832
1833 /* Allocate descriptor base address table */
1834 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
1835 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
1836 &priv->desc_bat_dma, GFP_KERNEL);
1837 if (!priv->desc_bat) {
1838 dev_err(&pdev->dev,
1839 "Cannot allocate desc base address table (size %d bytes)\n",
1840 priv->desc_bat_size);
1841 error = -ENOMEM;
1842 goto out_release;
1843 }
1844 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
1845 priv->desc_bat[q].die_dt = DT_EOS;
1846 ravb_write(ndev, priv->desc_bat_dma, DBAT);
1847
1848 /* Initialise HW timestamp list */
1849 INIT_LIST_HEAD(&priv->ts_skb_list);
1850
1851 /* Initialise PTP Clock driver */
1852 if (chip_id != RCAR_GEN2)
1853 ravb_ptp_init(ndev, pdev);
1854
1855 /* Debug message level */
1856 priv->msg_enable = RAVB_DEF_MSG_ENABLE;
1857
1858 /* Read and set MAC address */
1859 ravb_read_mac_address(ndev, of_get_mac_address(np));
1860 if (!is_valid_ether_addr(ndev->dev_addr)) {
1861 dev_warn(&pdev->dev,
1862 "no valid MAC address supplied, using a random one\n");
1863 eth_hw_addr_random(ndev);
1864 }
1865
1866 /* MDIO bus init */
1867 error = ravb_mdio_init(priv);
1868 if (error) {
1869 dev_err(&pdev->dev, "failed to initialize MDIO\n");
1870 goto out_dma_free;
1871 }
1872
1873 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64);
1874 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64);
1875
1876 /* Network device register */
1877 error = register_netdev(ndev);
1878 if (error)
1879 goto out_napi_del;
1880
1881 /* Print device information */
1882 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
1883 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
1884
1885 platform_set_drvdata(pdev, ndev);
1886
1887 return 0;
1888
1889 out_napi_del:
1890 netif_napi_del(&priv->napi[RAVB_NC]);
1891 netif_napi_del(&priv->napi[RAVB_BE]);
1892 ravb_mdio_release(priv);
1893 out_dma_free:
1894 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
1895 priv->desc_bat_dma);
1896
1897 /* Stop PTP Clock driver */
1898 if (chip_id != RCAR_GEN2)
1899 ravb_ptp_stop(ndev);
1900 out_release:
1901 if (ndev)
1902 free_netdev(ndev);
1903
1904 pm_runtime_put(&pdev->dev);
1905 pm_runtime_disable(&pdev->dev);
1906 return error;
1907 }
1908
1909 static int ravb_remove(struct platform_device *pdev)
1910 {
1911 struct net_device *ndev = platform_get_drvdata(pdev);
1912 struct ravb_private *priv = netdev_priv(ndev);
1913
1914 /* Stop PTP Clock driver */
1915 if (priv->chip_id != RCAR_GEN2)
1916 ravb_ptp_stop(ndev);
1917
1918 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
1919 priv->desc_bat_dma);
1920 /* Set reset mode */
1921 ravb_write(ndev, CCC_OPC_RESET, CCC);
1922 pm_runtime_put_sync(&pdev->dev);
1923 unregister_netdev(ndev);
1924 netif_napi_del(&priv->napi[RAVB_NC]);
1925 netif_napi_del(&priv->napi[RAVB_BE]);
1926 ravb_mdio_release(priv);
1927 pm_runtime_disable(&pdev->dev);
1928 free_netdev(ndev);
1929 platform_set_drvdata(pdev, NULL);
1930
1931 return 0;
1932 }
1933
1934 #ifdef CONFIG_PM
1935 static int ravb_runtime_nop(struct device *dev)
1936 {
1937 /* Runtime PM callback shared between ->runtime_suspend()
1938 * and ->runtime_resume(). Simply returns success.
1939 *
1940 * This driver re-initializes all registers after
1941 * pm_runtime_get_sync() anyway so there is no need
1942 * to save and restore registers here.
1943 */
1944 return 0;
1945 }
1946
1947 static const struct dev_pm_ops ravb_dev_pm_ops = {
1948 .runtime_suspend = ravb_runtime_nop,
1949 .runtime_resume = ravb_runtime_nop,
1950 };
1951
1952 #define RAVB_PM_OPS (&ravb_dev_pm_ops)
1953 #else
1954 #define RAVB_PM_OPS NULL
1955 #endif
1956
1957 static struct platform_driver ravb_driver = {
1958 .probe = ravb_probe,
1959 .remove = ravb_remove,
1960 .driver = {
1961 .name = "ravb",
1962 .pm = RAVB_PM_OPS,
1963 .of_match_table = ravb_match_table,
1964 },
1965 };
1966
1967 module_platform_driver(ravb_driver);
1968
1969 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
1970 MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
1971 MODULE_LICENSE("GPL v2");
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