]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blob - drivers/net/ethernet/renesas/sh_eth.c
projects / mirror_ubuntu-zesty-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge remote-tracking branches 'asoc/topic/sgtl5000', 'asoc/topic/simple', 'asoc...
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / renesas / sh_eth.c
1 /* SuperH Ethernet device driver
2 *
3 * Copyright (C) 2014 Renesas Electronics Corporation
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
6 * Copyright (C) 2013-2016 Cogent Embedded, Inc.
7 * Copyright (C) 2014 Codethink Limited
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 */
21
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/etherdevice.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/mdio-bitbang.h>
31 #include <linux/netdevice.h>
32 #include <linux/of.h>
33 #include <linux/of_device.h>
34 #include <linux/of_irq.h>
35 #include <linux/of_net.h>
36 #include <linux/phy.h>
37 #include <linux/cache.h>
38 #include <linux/io.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/slab.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43 #include <linux/clk.h>
44 #include <linux/sh_eth.h>
45 #include <linux/of_mdio.h>
46
47 #include "sh_eth.h"
48
49 #define SH_ETH_DEF_MSG_ENABLE \
50 (NETIF_MSG_LINK | \
51 NETIF_MSG_TIMER | \
52 NETIF_MSG_RX_ERR| \
53 NETIF_MSG_TX_ERR)
54
55 #define SH_ETH_OFFSET_INVALID ((u16)~0)
56
57 #define SH_ETH_OFFSET_DEFAULTS \
58 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
59
60 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
61 SH_ETH_OFFSET_DEFAULTS,
62
63 [EDSR] = 0x0000,
64 [EDMR] = 0x0400,
65 [EDTRR] = 0x0408,
66 [EDRRR] = 0x0410,
67 [EESR] = 0x0428,
68 [EESIPR] = 0x0430,
69 [TDLAR] = 0x0010,
70 [TDFAR] = 0x0014,
71 [TDFXR] = 0x0018,
72 [TDFFR] = 0x001c,
73 [RDLAR] = 0x0030,
74 [RDFAR] = 0x0034,
75 [RDFXR] = 0x0038,
76 [RDFFR] = 0x003c,
77 [TRSCER] = 0x0438,
78 [RMFCR] = 0x0440,
79 [TFTR] = 0x0448,
80 [FDR] = 0x0450,
81 [RMCR] = 0x0458,
82 [RPADIR] = 0x0460,
83 [FCFTR] = 0x0468,
84 [CSMR] = 0x04E4,
85
86 [ECMR] = 0x0500,
87 [ECSR] = 0x0510,
88 [ECSIPR] = 0x0518,
89 [PIR] = 0x0520,
90 [PSR] = 0x0528,
91 [PIPR] = 0x052c,
92 [RFLR] = 0x0508,
93 [APR] = 0x0554,
94 [MPR] = 0x0558,
95 [PFTCR] = 0x055c,
96 [PFRCR] = 0x0560,
97 [TPAUSER] = 0x0564,
98 [GECMR] = 0x05b0,
99 [BCULR] = 0x05b4,
100 [MAHR] = 0x05c0,
101 [MALR] = 0x05c8,
102 [TROCR] = 0x0700,
103 [CDCR] = 0x0708,
104 [LCCR] = 0x0710,
105 [CEFCR] = 0x0740,
106 [FRECR] = 0x0748,
107 [TSFRCR] = 0x0750,
108 [TLFRCR] = 0x0758,
109 [RFCR] = 0x0760,
110 [CERCR] = 0x0768,
111 [CEECR] = 0x0770,
112 [MAFCR] = 0x0778,
113 [RMII_MII] = 0x0790,
114
115 [ARSTR] = 0x0000,
116 [TSU_CTRST] = 0x0004,
117 [TSU_FWEN0] = 0x0010,
118 [TSU_FWEN1] = 0x0014,
119 [TSU_FCM] = 0x0018,
120 [TSU_BSYSL0] = 0x0020,
121 [TSU_BSYSL1] = 0x0024,
122 [TSU_PRISL0] = 0x0028,
123 [TSU_PRISL1] = 0x002c,
124 [TSU_FWSL0] = 0x0030,
125 [TSU_FWSL1] = 0x0034,
126 [TSU_FWSLC] = 0x0038,
127 [TSU_QTAG0] = 0x0040,
128 [TSU_QTAG1] = 0x0044,
129 [TSU_FWSR] = 0x0050,
130 [TSU_FWINMK] = 0x0054,
131 [TSU_ADQT0] = 0x0048,
132 [TSU_ADQT1] = 0x004c,
133 [TSU_VTAG0] = 0x0058,
134 [TSU_VTAG1] = 0x005c,
135 [TSU_ADSBSY] = 0x0060,
136 [TSU_TEN] = 0x0064,
137 [TSU_POST1] = 0x0070,
138 [TSU_POST2] = 0x0074,
139 [TSU_POST3] = 0x0078,
140 [TSU_POST4] = 0x007c,
141 [TSU_ADRH0] = 0x0100,
142
143 [TXNLCR0] = 0x0080,
144 [TXALCR0] = 0x0084,
145 [RXNLCR0] = 0x0088,
146 [RXALCR0] = 0x008c,
147 [FWNLCR0] = 0x0090,
148 [FWALCR0] = 0x0094,
149 [TXNLCR1] = 0x00a0,
150 [TXALCR1] = 0x00a0,
151 [RXNLCR1] = 0x00a8,
152 [RXALCR1] = 0x00ac,
153 [FWNLCR1] = 0x00b0,
154 [FWALCR1] = 0x00b4,
155 };
156
157 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
158 SH_ETH_OFFSET_DEFAULTS,
159
160 [EDSR] = 0x0000,
161 [EDMR] = 0x0400,
162 [EDTRR] = 0x0408,
163 [EDRRR] = 0x0410,
164 [EESR] = 0x0428,
165 [EESIPR] = 0x0430,
166 [TDLAR] = 0x0010,
167 [TDFAR] = 0x0014,
168 [TDFXR] = 0x0018,
169 [TDFFR] = 0x001c,
170 [RDLAR] = 0x0030,
171 [RDFAR] = 0x0034,
172 [RDFXR] = 0x0038,
173 [RDFFR] = 0x003c,
174 [TRSCER] = 0x0438,
175 [RMFCR] = 0x0440,
176 [TFTR] = 0x0448,
177 [FDR] = 0x0450,
178 [RMCR] = 0x0458,
179 [RPADIR] = 0x0460,
180 [FCFTR] = 0x0468,
181 [CSMR] = 0x04E4,
182
183 [ECMR] = 0x0500,
184 [RFLR] = 0x0508,
185 [ECSR] = 0x0510,
186 [ECSIPR] = 0x0518,
187 [PIR] = 0x0520,
188 [APR] = 0x0554,
189 [MPR] = 0x0558,
190 [PFTCR] = 0x055c,
191 [PFRCR] = 0x0560,
192 [TPAUSER] = 0x0564,
193 [MAHR] = 0x05c0,
194 [MALR] = 0x05c8,
195 [CEFCR] = 0x0740,
196 [FRECR] = 0x0748,
197 [TSFRCR] = 0x0750,
198 [TLFRCR] = 0x0758,
199 [RFCR] = 0x0760,
200 [MAFCR] = 0x0778,
201
202 [ARSTR] = 0x0000,
203 [TSU_CTRST] = 0x0004,
204 [TSU_FWSLC] = 0x0038,
205 [TSU_VTAG0] = 0x0058,
206 [TSU_ADSBSY] = 0x0060,
207 [TSU_TEN] = 0x0064,
208 [TSU_POST1] = 0x0070,
209 [TSU_POST2] = 0x0074,
210 [TSU_POST3] = 0x0078,
211 [TSU_POST4] = 0x007c,
212 [TSU_ADRH0] = 0x0100,
213
214 [TXNLCR0] = 0x0080,
215 [TXALCR0] = 0x0084,
216 [RXNLCR0] = 0x0088,
217 [RXALCR0] = 0x008C,
218 };
219
220 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
221 SH_ETH_OFFSET_DEFAULTS,
222
223 [ECMR] = 0x0300,
224 [RFLR] = 0x0308,
225 [ECSR] = 0x0310,
226 [ECSIPR] = 0x0318,
227 [PIR] = 0x0320,
228 [PSR] = 0x0328,
229 [RDMLR] = 0x0340,
230 [IPGR] = 0x0350,
231 [APR] = 0x0354,
232 [MPR] = 0x0358,
233 [RFCF] = 0x0360,
234 [TPAUSER] = 0x0364,
235 [TPAUSECR] = 0x0368,
236 [MAHR] = 0x03c0,
237 [MALR] = 0x03c8,
238 [TROCR] = 0x03d0,
239 [CDCR] = 0x03d4,
240 [LCCR] = 0x03d8,
241 [CNDCR] = 0x03dc,
242 [CEFCR] = 0x03e4,
243 [FRECR] = 0x03e8,
244 [TSFRCR] = 0x03ec,
245 [TLFRCR] = 0x03f0,
246 [RFCR] = 0x03f4,
247 [MAFCR] = 0x03f8,
248
249 [EDMR] = 0x0200,
250 [EDTRR] = 0x0208,
251 [EDRRR] = 0x0210,
252 [TDLAR] = 0x0218,
253 [RDLAR] = 0x0220,
254 [EESR] = 0x0228,
255 [EESIPR] = 0x0230,
256 [TRSCER] = 0x0238,
257 [RMFCR] = 0x0240,
258 [TFTR] = 0x0248,
259 [FDR] = 0x0250,
260 [RMCR] = 0x0258,
261 [TFUCR] = 0x0264,
262 [RFOCR] = 0x0268,
263 [RMIIMODE] = 0x026c,
264 [FCFTR] = 0x0270,
265 [TRIMD] = 0x027c,
266 };
267
268 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
269 SH_ETH_OFFSET_DEFAULTS,
270
271 [ECMR] = 0x0100,
272 [RFLR] = 0x0108,
273 [ECSR] = 0x0110,
274 [ECSIPR] = 0x0118,
275 [PIR] = 0x0120,
276 [PSR] = 0x0128,
277 [RDMLR] = 0x0140,
278 [IPGR] = 0x0150,
279 [APR] = 0x0154,
280 [MPR] = 0x0158,
281 [TPAUSER] = 0x0164,
282 [RFCF] = 0x0160,
283 [TPAUSECR] = 0x0168,
284 [BCFRR] = 0x016c,
285 [MAHR] = 0x01c0,
286 [MALR] = 0x01c8,
287 [TROCR] = 0x01d0,
288 [CDCR] = 0x01d4,
289 [LCCR] = 0x01d8,
290 [CNDCR] = 0x01dc,
291 [CEFCR] = 0x01e4,
292 [FRECR] = 0x01e8,
293 [TSFRCR] = 0x01ec,
294 [TLFRCR] = 0x01f0,
295 [RFCR] = 0x01f4,
296 [MAFCR] = 0x01f8,
297 [RTRATE] = 0x01fc,
298
299 [EDMR] = 0x0000,
300 [EDTRR] = 0x0008,
301 [EDRRR] = 0x0010,
302 [TDLAR] = 0x0018,
303 [RDLAR] = 0x0020,
304 [EESR] = 0x0028,
305 [EESIPR] = 0x0030,
306 [TRSCER] = 0x0038,
307 [RMFCR] = 0x0040,
308 [TFTR] = 0x0048,
309 [FDR] = 0x0050,
310 [RMCR] = 0x0058,
311 [TFUCR] = 0x0064,
312 [RFOCR] = 0x0068,
313 [FCFTR] = 0x0070,
314 [RPADIR] = 0x0078,
315 [TRIMD] = 0x007c,
316 [RBWAR] = 0x00c8,
317 [RDFAR] = 0x00cc,
318 [TBRAR] = 0x00d4,
319 [TDFAR] = 0x00d8,
320 };
321
322 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
323 SH_ETH_OFFSET_DEFAULTS,
324
325 [EDMR] = 0x0000,
326 [EDTRR] = 0x0004,
327 [EDRRR] = 0x0008,
328 [TDLAR] = 0x000c,
329 [RDLAR] = 0x0010,
330 [EESR] = 0x0014,
331 [EESIPR] = 0x0018,
332 [TRSCER] = 0x001c,
333 [RMFCR] = 0x0020,
334 [TFTR] = 0x0024,
335 [FDR] = 0x0028,
336 [RMCR] = 0x002c,
337 [EDOCR] = 0x0030,
338 [FCFTR] = 0x0034,
339 [RPADIR] = 0x0038,
340 [TRIMD] = 0x003c,
341 [RBWAR] = 0x0040,
342 [RDFAR] = 0x0044,
343 [TBRAR] = 0x004c,
344 [TDFAR] = 0x0050,
345
346 [ECMR] = 0x0160,
347 [ECSR] = 0x0164,
348 [ECSIPR] = 0x0168,
349 [PIR] = 0x016c,
350 [MAHR] = 0x0170,
351 [MALR] = 0x0174,
352 [RFLR] = 0x0178,
353 [PSR] = 0x017c,
354 [TROCR] = 0x0180,
355 [CDCR] = 0x0184,
356 [LCCR] = 0x0188,
357 [CNDCR] = 0x018c,
358 [CEFCR] = 0x0194,
359 [FRECR] = 0x0198,
360 [TSFRCR] = 0x019c,
361 [TLFRCR] = 0x01a0,
362 [RFCR] = 0x01a4,
363 [MAFCR] = 0x01a8,
364 [IPGR] = 0x01b4,
365 [APR] = 0x01b8,
366 [MPR] = 0x01bc,
367 [TPAUSER] = 0x01c4,
368 [BCFR] = 0x01cc,
369
370 [ARSTR] = 0x0000,
371 [TSU_CTRST] = 0x0004,
372 [TSU_FWEN0] = 0x0010,
373 [TSU_FWEN1] = 0x0014,
374 [TSU_FCM] = 0x0018,
375 [TSU_BSYSL0] = 0x0020,
376 [TSU_BSYSL1] = 0x0024,
377 [TSU_PRISL0] = 0x0028,
378 [TSU_PRISL1] = 0x002c,
379 [TSU_FWSL0] = 0x0030,
380 [TSU_FWSL1] = 0x0034,
381 [TSU_FWSLC] = 0x0038,
382 [TSU_QTAGM0] = 0x0040,
383 [TSU_QTAGM1] = 0x0044,
384 [TSU_ADQT0] = 0x0048,
385 [TSU_ADQT1] = 0x004c,
386 [TSU_FWSR] = 0x0050,
387 [TSU_FWINMK] = 0x0054,
388 [TSU_ADSBSY] = 0x0060,
389 [TSU_TEN] = 0x0064,
390 [TSU_POST1] = 0x0070,
391 [TSU_POST2] = 0x0074,
392 [TSU_POST3] = 0x0078,
393 [TSU_POST4] = 0x007c,
394
395 [TXNLCR0] = 0x0080,
396 [TXALCR0] = 0x0084,
397 [RXNLCR0] = 0x0088,
398 [RXALCR0] = 0x008c,
399 [FWNLCR0] = 0x0090,
400 [FWALCR0] = 0x0094,
401 [TXNLCR1] = 0x00a0,
402 [TXALCR1] = 0x00a0,
403 [RXNLCR1] = 0x00a8,
404 [RXALCR1] = 0x00ac,
405 [FWNLCR1] = 0x00b0,
406 [FWALCR1] = 0x00b4,
407
408 [TSU_ADRH0] = 0x0100,
409 };
410
411 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
412 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
413
414 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
415 {
416 struct sh_eth_private *mdp = netdev_priv(ndev);
417 u16 offset = mdp->reg_offset[enum_index];
418
419 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
420 return;
421
422 iowrite32(data, mdp->addr + offset);
423 }
424
425 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
426 {
427 struct sh_eth_private *mdp = netdev_priv(ndev);
428 u16 offset = mdp->reg_offset[enum_index];
429
430 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
431 return ~0U;
432
433 return ioread32(mdp->addr + offset);
434 }
435
436 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
437 u32 set)
438 {
439 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
440 enum_index);
441 }
442
443 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
444 {
445 return mdp->reg_offset == sh_eth_offset_gigabit;
446 }
447
448 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
449 {
450 return mdp->reg_offset == sh_eth_offset_fast_rz;
451 }
452
453 static void sh_eth_select_mii(struct net_device *ndev)
454 {
455 struct sh_eth_private *mdp = netdev_priv(ndev);
456 u32 value;
457
458 switch (mdp->phy_interface) {
459 case PHY_INTERFACE_MODE_GMII:
460 value = 0x2;
461 break;
462 case PHY_INTERFACE_MODE_MII:
463 value = 0x1;
464 break;
465 case PHY_INTERFACE_MODE_RMII:
466 value = 0x0;
467 break;
468 default:
469 netdev_warn(ndev,
470 "PHY interface mode was not setup. Set to MII.\n");
471 value = 0x1;
472 break;
473 }
474
475 sh_eth_write(ndev, value, RMII_MII);
476 }
477
478 static void sh_eth_set_duplex(struct net_device *ndev)
479 {
480 struct sh_eth_private *mdp = netdev_priv(ndev);
481
482 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
483 }
484
485 static void sh_eth_chip_reset(struct net_device *ndev)
486 {
487 struct sh_eth_private *mdp = netdev_priv(ndev);
488
489 /* reset device */
490 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
491 mdelay(1);
492 }
493
494 static void sh_eth_set_rate_gether(struct net_device *ndev)
495 {
496 struct sh_eth_private *mdp = netdev_priv(ndev);
497
498 switch (mdp->speed) {
499 case 10: /* 10BASE */
500 sh_eth_write(ndev, GECMR_10, GECMR);
501 break;
502 case 100:/* 100BASE */
503 sh_eth_write(ndev, GECMR_100, GECMR);
504 break;
505 case 1000: /* 1000BASE */
506 sh_eth_write(ndev, GECMR_1000, GECMR);
507 break;
508 }
509 }
510
511 #ifdef CONFIG_OF
512 /* R7S72100 */
513 static struct sh_eth_cpu_data r7s72100_data = {
514 .chip_reset = sh_eth_chip_reset,
515 .set_duplex = sh_eth_set_duplex,
516
517 .register_type = SH_ETH_REG_FAST_RZ,
518
519 .ecsr_value = ECSR_ICD,
520 .ecsipr_value = ECSIPR_ICDIP,
521 .eesipr_value = 0xff7f009f,
522
523 .tx_check = EESR_TC1 | EESR_FTC,
524 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
525 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
526 EESR_TDE | EESR_ECI,
527 .fdr_value = 0x0000070f,
528
529 .no_psr = 1,
530 .apr = 1,
531 .mpr = 1,
532 .tpauser = 1,
533 .hw_swap = 1,
534 .rpadir = 1,
535 .rpadir_value = 2 << 16,
536 .no_trimd = 1,
537 .no_ade = 1,
538 .hw_crc = 1,
539 .tsu = 1,
540 .shift_rd0 = 1,
541 };
542
543 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
544 {
545 sh_eth_chip_reset(ndev);
546
547 sh_eth_select_mii(ndev);
548 }
549
550 /* R8A7740 */
551 static struct sh_eth_cpu_data r8a7740_data = {
552 .chip_reset = sh_eth_chip_reset_r8a7740,
553 .set_duplex = sh_eth_set_duplex,
554 .set_rate = sh_eth_set_rate_gether,
555
556 .register_type = SH_ETH_REG_GIGABIT,
557
558 .ecsr_value = ECSR_ICD | ECSR_MPD,
559 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
560 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
561
562 .tx_check = EESR_TC1 | EESR_FTC,
563 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
564 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
565 EESR_TDE | EESR_ECI,
566 .fdr_value = 0x0000070f,
567
568 .apr = 1,
569 .mpr = 1,
570 .tpauser = 1,
571 .bculr = 1,
572 .hw_swap = 1,
573 .rpadir = 1,
574 .rpadir_value = 2 << 16,
575 .no_trimd = 1,
576 .no_ade = 1,
577 .tsu = 1,
578 .select_mii = 1,
579 .shift_rd0 = 1,
580 };
581
582 /* There is CPU dependent code */
583 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
584 {
585 struct sh_eth_private *mdp = netdev_priv(ndev);
586
587 switch (mdp->speed) {
588 case 10: /* 10BASE */
589 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
590 break;
591 case 100:/* 100BASE */
592 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
593 break;
594 }
595 }
596
597 /* R8A7778/9 */
598 static struct sh_eth_cpu_data r8a777x_data = {
599 .set_duplex = sh_eth_set_duplex,
600 .set_rate = sh_eth_set_rate_r8a777x,
601
602 .register_type = SH_ETH_REG_FAST_RCAR,
603
604 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
605 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
606 .eesipr_value = 0x01ff009f,
607
608 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
609 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
610 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
611 EESR_ECI,
612 .fdr_value = 0x00000f0f,
613
614 .apr = 1,
615 .mpr = 1,
616 .tpauser = 1,
617 .hw_swap = 1,
618 };
619
620 /* R8A7790/1 */
621 static struct sh_eth_cpu_data r8a779x_data = {
622 .set_duplex = sh_eth_set_duplex,
623 .set_rate = sh_eth_set_rate_r8a777x,
624
625 .register_type = SH_ETH_REG_FAST_RCAR,
626
627 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
628 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
629 .eesipr_value = 0x01ff009f,
630
631 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
632 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
633 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
634 EESR_ECI,
635 .fdr_value = 0x00000f0f,
636
637 .trscer_err_mask = DESC_I_RINT8,
638
639 .apr = 1,
640 .mpr = 1,
641 .tpauser = 1,
642 .hw_swap = 1,
643 .rmiimode = 1,
644 };
645 #endif /* CONFIG_OF */
646
647 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
648 {
649 struct sh_eth_private *mdp = netdev_priv(ndev);
650
651 switch (mdp->speed) {
652 case 10: /* 10BASE */
653 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
654 break;
655 case 100:/* 100BASE */
656 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
657 break;
658 }
659 }
660
661 /* SH7724 */
662 static struct sh_eth_cpu_data sh7724_data = {
663 .set_duplex = sh_eth_set_duplex,
664 .set_rate = sh_eth_set_rate_sh7724,
665
666 .register_type = SH_ETH_REG_FAST_SH4,
667
668 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
669 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
670 .eesipr_value = 0x01ff009f,
671
672 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
673 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
674 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
675 EESR_ECI,
676
677 .apr = 1,
678 .mpr = 1,
679 .tpauser = 1,
680 .hw_swap = 1,
681 .rpadir = 1,
682 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
683 };
684
685 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
686 {
687 struct sh_eth_private *mdp = netdev_priv(ndev);
688
689 switch (mdp->speed) {
690 case 10: /* 10BASE */
691 sh_eth_write(ndev, 0, RTRATE);
692 break;
693 case 100:/* 100BASE */
694 sh_eth_write(ndev, 1, RTRATE);
695 break;
696 }
697 }
698
699 /* SH7757 */
700 static struct sh_eth_cpu_data sh7757_data = {
701 .set_duplex = sh_eth_set_duplex,
702 .set_rate = sh_eth_set_rate_sh7757,
703
704 .register_type = SH_ETH_REG_FAST_SH4,
705
706 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
707
708 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
709 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
710 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
711 EESR_ECI,
712
713 .irq_flags = IRQF_SHARED,
714 .apr = 1,
715 .mpr = 1,
716 .tpauser = 1,
717 .hw_swap = 1,
718 .no_ade = 1,
719 .rpadir = 1,
720 .rpadir_value = 2 << 16,
721 .rtrate = 1,
722 };
723
724 #define SH_GIGA_ETH_BASE 0xfee00000UL
725 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
726 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
727 static void sh_eth_chip_reset_giga(struct net_device *ndev)
728 {
729 u32 mahr[2], malr[2];
730 int i;
731
732 /* save MAHR and MALR */
733 for (i = 0; i < 2; i++) {
734 malr[i] = ioread32((void *)GIGA_MALR(i));
735 mahr[i] = ioread32((void *)GIGA_MAHR(i));
736 }
737
738 sh_eth_chip_reset(ndev);
739
740 /* restore MAHR and MALR */
741 for (i = 0; i < 2; i++) {
742 iowrite32(malr[i], (void *)GIGA_MALR(i));
743 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
744 }
745 }
746
747 static void sh_eth_set_rate_giga(struct net_device *ndev)
748 {
749 struct sh_eth_private *mdp = netdev_priv(ndev);
750
751 switch (mdp->speed) {
752 case 10: /* 10BASE */
753 sh_eth_write(ndev, 0x00000000, GECMR);
754 break;
755 case 100:/* 100BASE */
756 sh_eth_write(ndev, 0x00000010, GECMR);
757 break;
758 case 1000: /* 1000BASE */
759 sh_eth_write(ndev, 0x00000020, GECMR);
760 break;
761 }
762 }
763
764 /* SH7757(GETHERC) */
765 static struct sh_eth_cpu_data sh7757_data_giga = {
766 .chip_reset = sh_eth_chip_reset_giga,
767 .set_duplex = sh_eth_set_duplex,
768 .set_rate = sh_eth_set_rate_giga,
769
770 .register_type = SH_ETH_REG_GIGABIT,
771
772 .ecsr_value = ECSR_ICD | ECSR_MPD,
773 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
774 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
775
776 .tx_check = EESR_TC1 | EESR_FTC,
777 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
778 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
779 EESR_TDE | EESR_ECI,
780 .fdr_value = 0x0000072f,
781
782 .irq_flags = IRQF_SHARED,
783 .apr = 1,
784 .mpr = 1,
785 .tpauser = 1,
786 .bculr = 1,
787 .hw_swap = 1,
788 .rpadir = 1,
789 .rpadir_value = 2 << 16,
790 .no_trimd = 1,
791 .no_ade = 1,
792 .tsu = 1,
793 };
794
795 /* SH7734 */
796 static struct sh_eth_cpu_data sh7734_data = {
797 .chip_reset = sh_eth_chip_reset,
798 .set_duplex = sh_eth_set_duplex,
799 .set_rate = sh_eth_set_rate_gether,
800
801 .register_type = SH_ETH_REG_GIGABIT,
802
803 .ecsr_value = ECSR_ICD | ECSR_MPD,
804 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
805 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
806
807 .tx_check = EESR_TC1 | EESR_FTC,
808 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
809 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
810 EESR_TDE | EESR_ECI,
811
812 .apr = 1,
813 .mpr = 1,
814 .tpauser = 1,
815 .bculr = 1,
816 .hw_swap = 1,
817 .no_trimd = 1,
818 .no_ade = 1,
819 .tsu = 1,
820 .hw_crc = 1,
821 .select_mii = 1,
822 };
823
824 /* SH7763 */
825 static struct sh_eth_cpu_data sh7763_data = {
826 .chip_reset = sh_eth_chip_reset,
827 .set_duplex = sh_eth_set_duplex,
828 .set_rate = sh_eth_set_rate_gether,
829
830 .register_type = SH_ETH_REG_GIGABIT,
831
832 .ecsr_value = ECSR_ICD | ECSR_MPD,
833 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
834 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
835
836 .tx_check = EESR_TC1 | EESR_FTC,
837 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
838 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
839 EESR_ECI,
840
841 .apr = 1,
842 .mpr = 1,
843 .tpauser = 1,
844 .bculr = 1,
845 .hw_swap = 1,
846 .no_trimd = 1,
847 .no_ade = 1,
848 .tsu = 1,
849 .irq_flags = IRQF_SHARED,
850 };
851
852 static struct sh_eth_cpu_data sh7619_data = {
853 .register_type = SH_ETH_REG_FAST_SH3_SH2,
854
855 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
856
857 .apr = 1,
858 .mpr = 1,
859 .tpauser = 1,
860 .hw_swap = 1,
861 };
862
863 static struct sh_eth_cpu_data sh771x_data = {
864 .register_type = SH_ETH_REG_FAST_SH3_SH2,
865
866 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
867 .tsu = 1,
868 };
869
870 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
871 {
872 if (!cd->ecsr_value)
873 cd->ecsr_value = DEFAULT_ECSR_INIT;
874
875 if (!cd->ecsipr_value)
876 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
877
878 if (!cd->fcftr_value)
879 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
880 DEFAULT_FIFO_F_D_RFD;
881
882 if (!cd->fdr_value)
883 cd->fdr_value = DEFAULT_FDR_INIT;
884
885 if (!cd->tx_check)
886 cd->tx_check = DEFAULT_TX_CHECK;
887
888 if (!cd->eesr_err_check)
889 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
890
891 if (!cd->trscer_err_mask)
892 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
893 }
894
895 static int sh_eth_check_reset(struct net_device *ndev)
896 {
897 int ret = 0;
898 int cnt = 100;
899
900 while (cnt > 0) {
901 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
902 break;
903 mdelay(1);
904 cnt--;
905 }
906 if (cnt <= 0) {
907 netdev_err(ndev, "Device reset failed\n");
908 ret = -ETIMEDOUT;
909 }
910 return ret;
911 }
912
913 static int sh_eth_reset(struct net_device *ndev)
914 {
915 struct sh_eth_private *mdp = netdev_priv(ndev);
916 int ret = 0;
917
918 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
919 sh_eth_write(ndev, EDSR_ENALL, EDSR);
920 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
921
922 ret = sh_eth_check_reset(ndev);
923 if (ret)
924 return ret;
925
926 /* Table Init */
927 sh_eth_write(ndev, 0x0, TDLAR);
928 sh_eth_write(ndev, 0x0, TDFAR);
929 sh_eth_write(ndev, 0x0, TDFXR);
930 sh_eth_write(ndev, 0x0, TDFFR);
931 sh_eth_write(ndev, 0x0, RDLAR);
932 sh_eth_write(ndev, 0x0, RDFAR);
933 sh_eth_write(ndev, 0x0, RDFXR);
934 sh_eth_write(ndev, 0x0, RDFFR);
935
936 /* Reset HW CRC register */
937 if (mdp->cd->hw_crc)
938 sh_eth_write(ndev, 0x0, CSMR);
939
940 /* Select MII mode */
941 if (mdp->cd->select_mii)
942 sh_eth_select_mii(ndev);
943 } else {
944 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
945 mdelay(3);
946 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
947 }
948
949 return ret;
950 }
951
952 static void sh_eth_set_receive_align(struct sk_buff *skb)
953 {
954 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
955
956 if (reserve)
957 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
958 }
959
960 /* Program the hardware MAC address from dev->dev_addr. */
961 static void update_mac_address(struct net_device *ndev)
962 {
963 sh_eth_write(ndev,
964 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
965 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
966 sh_eth_write(ndev,
967 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
968 }
969
970 /* Get MAC address from SuperH MAC address register
971 *
972 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
973 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
974 * When you want use this device, you must set MAC address in bootloader.
975 *
976 */
977 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
978 {
979 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
980 memcpy(ndev->dev_addr, mac, ETH_ALEN);
981 } else {
982 u32 mahr = sh_eth_read(ndev, MAHR);
983 u32 malr = sh_eth_read(ndev, MALR);
984
985 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
986 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
987 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
988 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
989 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
990 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
991 }
992 }
993
994 static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
995 {
996 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
997 return EDTRR_TRNS_GETHER;
998 else
999 return EDTRR_TRNS_ETHER;
1000 }
1001
1002 struct bb_info {
1003 void (*set_gate)(void *addr);
1004 struct mdiobb_ctrl ctrl;
1005 void *addr;
1006 };
1007
1008 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1009 {
1010 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1011 u32 pir;
1012
1013 if (bitbang->set_gate)
1014 bitbang->set_gate(bitbang->addr);
1015
1016 pir = ioread32(bitbang->addr);
1017 if (set)
1018 pir |= mask;
1019 else
1020 pir &= ~mask;
1021 iowrite32(pir, bitbang->addr);
1022 }
1023
1024 /* Data I/O pin control */
1025 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1026 {
1027 sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1028 }
1029
1030 /* Set bit data*/
1031 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1032 {
1033 sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1034 }
1035
1036 /* Get bit data*/
1037 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1038 {
1039 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1040
1041 if (bitbang->set_gate)
1042 bitbang->set_gate(bitbang->addr);
1043
1044 return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1045 }
1046
1047 /* MDC pin control */
1048 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1049 {
1050 sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1051 }
1052
1053 /* mdio bus control struct */
1054 static struct mdiobb_ops bb_ops = {
1055 .owner = THIS_MODULE,
1056 .set_mdc = sh_mdc_ctrl,
1057 .set_mdio_dir = sh_mmd_ctrl,
1058 .set_mdio_data = sh_set_mdio,
1059 .get_mdio_data = sh_get_mdio,
1060 };
1061
1062 /* free skb and descriptor buffer */
1063 static void sh_eth_ring_free(struct net_device *ndev)
1064 {
1065 struct sh_eth_private *mdp = netdev_priv(ndev);
1066 int ringsize, i;
1067
1068 /* Free Rx skb ringbuffer */
1069 if (mdp->rx_skbuff) {
1070 for (i = 0; i < mdp->num_rx_ring; i++)
1071 dev_kfree_skb(mdp->rx_skbuff[i]);
1072 }
1073 kfree(mdp->rx_skbuff);
1074 mdp->rx_skbuff = NULL;
1075
1076 /* Free Tx skb ringbuffer */
1077 if (mdp->tx_skbuff) {
1078 for (i = 0; i < mdp->num_tx_ring; i++)
1079 dev_kfree_skb(mdp->tx_skbuff[i]);
1080 }
1081 kfree(mdp->tx_skbuff);
1082 mdp->tx_skbuff = NULL;
1083
1084 if (mdp->rx_ring) {
1085 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1086 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1087 mdp->rx_desc_dma);
1088 mdp->rx_ring = NULL;
1089 }
1090
1091 if (mdp->tx_ring) {
1092 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1093 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1094 mdp->tx_desc_dma);
1095 mdp->tx_ring = NULL;
1096 }
1097 }
1098
1099 /* format skb and descriptor buffer */
1100 static void sh_eth_ring_format(struct net_device *ndev)
1101 {
1102 struct sh_eth_private *mdp = netdev_priv(ndev);
1103 int i;
1104 struct sk_buff *skb;
1105 struct sh_eth_rxdesc *rxdesc = NULL;
1106 struct sh_eth_txdesc *txdesc = NULL;
1107 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1108 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1109 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1110 dma_addr_t dma_addr;
1111 u32 buf_len;
1112
1113 mdp->cur_rx = 0;
1114 mdp->cur_tx = 0;
1115 mdp->dirty_rx = 0;
1116 mdp->dirty_tx = 0;
1117
1118 memset(mdp->rx_ring, 0, rx_ringsize);
1119
1120 /* build Rx ring buffer */
1121 for (i = 0; i < mdp->num_rx_ring; i++) {
1122 /* skb */
1123 mdp->rx_skbuff[i] = NULL;
1124 skb = netdev_alloc_skb(ndev, skbuff_size);
1125 if (skb == NULL)
1126 break;
1127 sh_eth_set_receive_align(skb);
1128
1129 /* The size of the buffer is a multiple of 32 bytes. */
1130 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1131 dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len,
1132 DMA_FROM_DEVICE);
1133 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1134 kfree_skb(skb);
1135 break;
1136 }
1137 mdp->rx_skbuff[i] = skb;
1138
1139 /* RX descriptor */
1140 rxdesc = &mdp->rx_ring[i];
1141 rxdesc->len = cpu_to_le32(buf_len << 16);
1142 rxdesc->addr = cpu_to_le32(dma_addr);
1143 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
1144
1145 /* Rx descriptor address set */
1146 if (i == 0) {
1147 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1148 if (sh_eth_is_gether(mdp) ||
1149 sh_eth_is_rz_fast_ether(mdp))
1150 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1151 }
1152 }
1153
1154 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1155
1156 /* Mark the last entry as wrapping the ring. */
1157 if (rxdesc)
1158 rxdesc->status |= cpu_to_le32(RD_RDLE);
1159
1160 memset(mdp->tx_ring, 0, tx_ringsize);
1161
1162 /* build Tx ring buffer */
1163 for (i = 0; i < mdp->num_tx_ring; i++) {
1164 mdp->tx_skbuff[i] = NULL;
1165 txdesc = &mdp->tx_ring[i];
1166 txdesc->status = cpu_to_le32(TD_TFP);
1167 txdesc->len = cpu_to_le32(0);
1168 if (i == 0) {
1169 /* Tx descriptor address set */
1170 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1171 if (sh_eth_is_gether(mdp) ||
1172 sh_eth_is_rz_fast_ether(mdp))
1173 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1174 }
1175 }
1176
1177 txdesc->status |= cpu_to_le32(TD_TDLE);
1178 }
1179
1180 /* Get skb and descriptor buffer */
1181 static int sh_eth_ring_init(struct net_device *ndev)
1182 {
1183 struct sh_eth_private *mdp = netdev_priv(ndev);
1184 int rx_ringsize, tx_ringsize;
1185
1186 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1187 * card needs room to do 8 byte alignment, +2 so we can reserve
1188 * the first 2 bytes, and +16 gets room for the status word from the
1189 * card.
1190 */
1191 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1192 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1193 if (mdp->cd->rpadir)
1194 mdp->rx_buf_sz += NET_IP_ALIGN;
1195
1196 /* Allocate RX and TX skb rings */
1197 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1198 GFP_KERNEL);
1199 if (!mdp->rx_skbuff)
1200 return -ENOMEM;
1201
1202 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1203 GFP_KERNEL);
1204 if (!mdp->tx_skbuff)
1205 goto ring_free;
1206
1207 /* Allocate all Rx descriptors. */
1208 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1209 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1210 GFP_KERNEL);
1211 if (!mdp->rx_ring)
1212 goto ring_free;
1213
1214 mdp->dirty_rx = 0;
1215
1216 /* Allocate all Tx descriptors. */
1217 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1218 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1219 GFP_KERNEL);
1220 if (!mdp->tx_ring)
1221 goto ring_free;
1222 return 0;
1223
1224 ring_free:
1225 /* Free Rx and Tx skb ring buffer and DMA buffer */
1226 sh_eth_ring_free(ndev);
1227
1228 return -ENOMEM;
1229 }
1230
1231 static int sh_eth_dev_init(struct net_device *ndev)
1232 {
1233 struct sh_eth_private *mdp = netdev_priv(ndev);
1234 int ret;
1235
1236 /* Soft Reset */
1237 ret = sh_eth_reset(ndev);
1238 if (ret)
1239 return ret;
1240
1241 if (mdp->cd->rmiimode)
1242 sh_eth_write(ndev, 0x1, RMIIMODE);
1243
1244 /* Descriptor format */
1245 sh_eth_ring_format(ndev);
1246 if (mdp->cd->rpadir)
1247 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1248
1249 /* all sh_eth int mask */
1250 sh_eth_write(ndev, 0, EESIPR);
1251
1252 #if defined(__LITTLE_ENDIAN)
1253 if (mdp->cd->hw_swap)
1254 sh_eth_write(ndev, EDMR_EL, EDMR);
1255 else
1256 #endif
1257 sh_eth_write(ndev, 0, EDMR);
1258
1259 /* FIFO size set */
1260 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1261 sh_eth_write(ndev, 0, TFTR);
1262
1263 /* Frame recv control (enable multiple-packets per rx irq) */
1264 sh_eth_write(ndev, RMCR_RNC, RMCR);
1265
1266 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1267
1268 if (mdp->cd->bculr)
1269 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
1270
1271 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1272
1273 if (!mdp->cd->no_trimd)
1274 sh_eth_write(ndev, 0, TRIMD);
1275
1276 /* Recv frame limit set register */
1277 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1278 RFLR);
1279
1280 sh_eth_modify(ndev, EESR, 0, 0);
1281 mdp->irq_enabled = true;
1282 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1283
1284 /* PAUSE Prohibition */
1285 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1286 ECMR_TE | ECMR_RE, ECMR);
1287
1288 if (mdp->cd->set_rate)
1289 mdp->cd->set_rate(ndev);
1290
1291 /* E-MAC Status Register clear */
1292 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1293
1294 /* E-MAC Interrupt Enable register */
1295 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1296
1297 /* Set MAC address */
1298 update_mac_address(ndev);
1299
1300 /* mask reset */
1301 if (mdp->cd->apr)
1302 sh_eth_write(ndev, APR_AP, APR);
1303 if (mdp->cd->mpr)
1304 sh_eth_write(ndev, MPR_MP, MPR);
1305 if (mdp->cd->tpauser)
1306 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1307
1308 /* Setting the Rx mode will start the Rx process. */
1309 sh_eth_write(ndev, EDRRR_R, EDRRR);
1310
1311 return ret;
1312 }
1313
1314 static void sh_eth_dev_exit(struct net_device *ndev)
1315 {
1316 struct sh_eth_private *mdp = netdev_priv(ndev);
1317 int i;
1318
1319 /* Deactivate all TX descriptors, so DMA should stop at next
1320 * packet boundary if it's currently running
1321 */
1322 for (i = 0; i < mdp->num_tx_ring; i++)
1323 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
1324
1325 /* Disable TX FIFO egress to MAC */
1326 sh_eth_rcv_snd_disable(ndev);
1327
1328 /* Stop RX DMA at next packet boundary */
1329 sh_eth_write(ndev, 0, EDRRR);
1330
1331 /* Aside from TX DMA, we can't tell when the hardware is
1332 * really stopped, so we need to reset to make sure.
1333 * Before doing that, wait for long enough to *probably*
1334 * finish transmitting the last packet and poll stats.
1335 */
1336 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1337 sh_eth_get_stats(ndev);
1338 sh_eth_reset(ndev);
1339
1340 /* Set MAC address again */
1341 update_mac_address(ndev);
1342 }
1343
1344 /* free Tx skb function */
1345 static int sh_eth_txfree(struct net_device *ndev)
1346 {
1347 struct sh_eth_private *mdp = netdev_priv(ndev);
1348 struct sh_eth_txdesc *txdesc;
1349 int free_num = 0;
1350 int entry;
1351
1352 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1353 entry = mdp->dirty_tx % mdp->num_tx_ring;
1354 txdesc = &mdp->tx_ring[entry];
1355 if (txdesc->status & cpu_to_le32(TD_TACT))
1356 break;
1357 /* TACT bit must be checked before all the following reads */
1358 dma_rmb();
1359 netif_info(mdp, tx_done, ndev,
1360 "tx entry %d status 0x%08x\n",
1361 entry, le32_to_cpu(txdesc->status));
1362 /* Free the original skb. */
1363 if (mdp->tx_skbuff[entry]) {
1364 dma_unmap_single(&ndev->dev, le32_to_cpu(txdesc->addr),
1365 le32_to_cpu(txdesc->len) >> 16,
1366 DMA_TO_DEVICE);
1367 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1368 mdp->tx_skbuff[entry] = NULL;
1369 free_num++;
1370 }
1371 txdesc->status = cpu_to_le32(TD_TFP);
1372 if (entry >= mdp->num_tx_ring - 1)
1373 txdesc->status |= cpu_to_le32(TD_TDLE);
1374
1375 ndev->stats.tx_packets++;
1376 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1377 }
1378 return free_num;
1379 }
1380
1381 /* Packet receive function */
1382 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1383 {
1384 struct sh_eth_private *mdp = netdev_priv(ndev);
1385 struct sh_eth_rxdesc *rxdesc;
1386
1387 int entry = mdp->cur_rx % mdp->num_rx_ring;
1388 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1389 int limit;
1390 struct sk_buff *skb;
1391 u32 desc_status;
1392 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1393 dma_addr_t dma_addr;
1394 u16 pkt_len;
1395 u32 buf_len;
1396
1397 boguscnt = min(boguscnt, *quota);
1398 limit = boguscnt;
1399 rxdesc = &mdp->rx_ring[entry];
1400 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
1401 /* RACT bit must be checked before all the following reads */
1402 dma_rmb();
1403 desc_status = le32_to_cpu(rxdesc->status);
1404 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
1405
1406 if (--boguscnt < 0)
1407 break;
1408
1409 netif_info(mdp, rx_status, ndev,
1410 "rx entry %d status 0x%08x len %d\n",
1411 entry, desc_status, pkt_len);
1412
1413 if (!(desc_status & RDFEND))
1414 ndev->stats.rx_length_errors++;
1415
1416 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1417 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1418 * bit 0. However, in case of the R8A7740 and R7S72100
1419 * the RFS bits are from bit 25 to bit 16. So, the
1420 * driver needs right shifting by 16.
1421 */
1422 if (mdp->cd->shift_rd0)
1423 desc_status >>= 16;
1424
1425 skb = mdp->rx_skbuff[entry];
1426 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1427 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1428 ndev->stats.rx_errors++;
1429 if (desc_status & RD_RFS1)
1430 ndev->stats.rx_crc_errors++;
1431 if (desc_status & RD_RFS2)
1432 ndev->stats.rx_frame_errors++;
1433 if (desc_status & RD_RFS3)
1434 ndev->stats.rx_length_errors++;
1435 if (desc_status & RD_RFS4)
1436 ndev->stats.rx_length_errors++;
1437 if (desc_status & RD_RFS6)
1438 ndev->stats.rx_missed_errors++;
1439 if (desc_status & RD_RFS10)
1440 ndev->stats.rx_over_errors++;
1441 } else if (skb) {
1442 dma_addr = le32_to_cpu(rxdesc->addr);
1443 if (!mdp->cd->hw_swap)
1444 sh_eth_soft_swap(
1445 phys_to_virt(ALIGN(dma_addr, 4)),
1446 pkt_len + 2);
1447 mdp->rx_skbuff[entry] = NULL;
1448 if (mdp->cd->rpadir)
1449 skb_reserve(skb, NET_IP_ALIGN);
1450 dma_unmap_single(&ndev->dev, dma_addr,
1451 ALIGN(mdp->rx_buf_sz, 32),
1452 DMA_FROM_DEVICE);
1453 skb_put(skb, pkt_len);
1454 skb->protocol = eth_type_trans(skb, ndev);
1455 netif_receive_skb(skb);
1456 ndev->stats.rx_packets++;
1457 ndev->stats.rx_bytes += pkt_len;
1458 if (desc_status & RD_RFS8)
1459 ndev->stats.multicast++;
1460 }
1461 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1462 rxdesc = &mdp->rx_ring[entry];
1463 }
1464
1465 /* Refill the Rx ring buffers. */
1466 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1467 entry = mdp->dirty_rx % mdp->num_rx_ring;
1468 rxdesc = &mdp->rx_ring[entry];
1469 /* The size of the buffer is 32 byte boundary. */
1470 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1471 rxdesc->len = cpu_to_le32(buf_len << 16);
1472
1473 if (mdp->rx_skbuff[entry] == NULL) {
1474 skb = netdev_alloc_skb(ndev, skbuff_size);
1475 if (skb == NULL)
1476 break; /* Better luck next round. */
1477 sh_eth_set_receive_align(skb);
1478 dma_addr = dma_map_single(&ndev->dev, skb->data,
1479 buf_len, DMA_FROM_DEVICE);
1480 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1481 kfree_skb(skb);
1482 break;
1483 }
1484 mdp->rx_skbuff[entry] = skb;
1485
1486 skb_checksum_none_assert(skb);
1487 rxdesc->addr = cpu_to_le32(dma_addr);
1488 }
1489 dma_wmb(); /* RACT bit must be set after all the above writes */
1490 if (entry >= mdp->num_rx_ring - 1)
1491 rxdesc->status |=
1492 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
1493 else
1494 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
1495 }
1496
1497 /* Restart Rx engine if stopped. */
1498 /* If we don't need to check status, don't. -KDU */
1499 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1500 /* fix the values for the next receiving if RDE is set */
1501 if (intr_status & EESR_RDE &&
1502 mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
1503 u32 count = (sh_eth_read(ndev, RDFAR) -
1504 sh_eth_read(ndev, RDLAR)) >> 4;
1505
1506 mdp->cur_rx = count;
1507 mdp->dirty_rx = count;
1508 }
1509 sh_eth_write(ndev, EDRRR_R, EDRRR);
1510 }
1511
1512 *quota -= limit - boguscnt - 1;
1513
1514 return *quota <= 0;
1515 }
1516
1517 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1518 {
1519 /* disable tx and rx */
1520 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1521 }
1522
1523 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1524 {
1525 /* enable tx and rx */
1526 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1527 }
1528
1529 /* error control function */
1530 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1531 {
1532 struct sh_eth_private *mdp = netdev_priv(ndev);
1533 u32 felic_stat;
1534 u32 link_stat;
1535 u32 mask;
1536
1537 if (intr_status & EESR_ECI) {
1538 felic_stat = sh_eth_read(ndev, ECSR);
1539 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1540 if (felic_stat & ECSR_ICD)
1541 ndev->stats.tx_carrier_errors++;
1542 if (felic_stat & ECSR_LCHNG) {
1543 /* Link Changed */
1544 if (mdp->cd->no_psr || mdp->no_ether_link) {
1545 goto ignore_link;
1546 } else {
1547 link_stat = (sh_eth_read(ndev, PSR));
1548 if (mdp->ether_link_active_low)
1549 link_stat = ~link_stat;
1550 }
1551 if (!(link_stat & PHY_ST_LINK)) {
1552 sh_eth_rcv_snd_disable(ndev);
1553 } else {
1554 /* Link Up */
1555 sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, 0);
1556 /* clear int */
1557 sh_eth_modify(ndev, ECSR, 0, 0);
1558 sh_eth_modify(ndev, EESIPR, DMAC_M_ECI,
1559 DMAC_M_ECI);
1560 /* enable tx and rx */
1561 sh_eth_rcv_snd_enable(ndev);
1562 }
1563 }
1564 }
1565
1566 ignore_link:
1567 if (intr_status & EESR_TWB) {
1568 /* Unused write back interrupt */
1569 if (intr_status & EESR_TABT) { /* Transmit Abort int */
1570 ndev->stats.tx_aborted_errors++;
1571 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1572 }
1573 }
1574
1575 if (intr_status & EESR_RABT) {
1576 /* Receive Abort int */
1577 if (intr_status & EESR_RFRMER) {
1578 /* Receive Frame Overflow int */
1579 ndev->stats.rx_frame_errors++;
1580 }
1581 }
1582
1583 if (intr_status & EESR_TDE) {
1584 /* Transmit Descriptor Empty int */
1585 ndev->stats.tx_fifo_errors++;
1586 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1587 }
1588
1589 if (intr_status & EESR_TFE) {
1590 /* FIFO under flow */
1591 ndev->stats.tx_fifo_errors++;
1592 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1593 }
1594
1595 if (intr_status & EESR_RDE) {
1596 /* Receive Descriptor Empty int */
1597 ndev->stats.rx_over_errors++;
1598 }
1599
1600 if (intr_status & EESR_RFE) {
1601 /* Receive FIFO Overflow int */
1602 ndev->stats.rx_fifo_errors++;
1603 }
1604
1605 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1606 /* Address Error */
1607 ndev->stats.tx_fifo_errors++;
1608 netif_err(mdp, tx_err, ndev, "Address Error\n");
1609 }
1610
1611 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1612 if (mdp->cd->no_ade)
1613 mask &= ~EESR_ADE;
1614 if (intr_status & mask) {
1615 /* Tx error */
1616 u32 edtrr = sh_eth_read(ndev, EDTRR);
1617
1618 /* dmesg */
1619 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1620 intr_status, mdp->cur_tx, mdp->dirty_tx,
1621 (u32)ndev->state, edtrr);
1622 /* dirty buffer free */
1623 sh_eth_txfree(ndev);
1624
1625 /* SH7712 BUG */
1626 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1627 /* tx dma start */
1628 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1629 }
1630 /* wakeup */
1631 netif_wake_queue(ndev);
1632 }
1633 }
1634
1635 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1636 {
1637 struct net_device *ndev = netdev;
1638 struct sh_eth_private *mdp = netdev_priv(ndev);
1639 struct sh_eth_cpu_data *cd = mdp->cd;
1640 irqreturn_t ret = IRQ_NONE;
1641 u32 intr_status, intr_enable;
1642
1643 spin_lock(&mdp->lock);
1644
1645 /* Get interrupt status */
1646 intr_status = sh_eth_read(ndev, EESR);
1647 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1648 * enabled since it's the one that comes thru regardless of the mask,
1649 * and we need to fully handle it in sh_eth_error() in order to quench
1650 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1651 */
1652 intr_enable = sh_eth_read(ndev, EESIPR);
1653 intr_status &= intr_enable | DMAC_M_ECI;
1654 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1655 ret = IRQ_HANDLED;
1656 else
1657 goto out;
1658
1659 if (!likely(mdp->irq_enabled)) {
1660 sh_eth_write(ndev, 0, EESIPR);
1661 goto out;
1662 }
1663
1664 if (intr_status & EESR_RX_CHECK) {
1665 if (napi_schedule_prep(&mdp->napi)) {
1666 /* Mask Rx interrupts */
1667 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1668 EESIPR);
1669 __napi_schedule(&mdp->napi);
1670 } else {
1671 netdev_warn(ndev,
1672 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1673 intr_status, intr_enable);
1674 }
1675 }
1676
1677 /* Tx Check */
1678 if (intr_status & cd->tx_check) {
1679 /* Clear Tx interrupts */
1680 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1681
1682 sh_eth_txfree(ndev);
1683 netif_wake_queue(ndev);
1684 }
1685
1686 if (intr_status & cd->eesr_err_check) {
1687 /* Clear error interrupts */
1688 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1689
1690 sh_eth_error(ndev, intr_status);
1691 }
1692
1693 out:
1694 spin_unlock(&mdp->lock);
1695
1696 return ret;
1697 }
1698
1699 static int sh_eth_poll(struct napi_struct *napi, int budget)
1700 {
1701 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1702 napi);
1703 struct net_device *ndev = napi->dev;
1704 int quota = budget;
1705 u32 intr_status;
1706
1707 for (;;) {
1708 intr_status = sh_eth_read(ndev, EESR);
1709 if (!(intr_status & EESR_RX_CHECK))
1710 break;
1711 /* Clear Rx interrupts */
1712 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1713
1714 if (sh_eth_rx(ndev, intr_status, &quota))
1715 goto out;
1716 }
1717
1718 napi_complete(napi);
1719
1720 /* Reenable Rx interrupts */
1721 if (mdp->irq_enabled)
1722 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1723 out:
1724 return budget - quota;
1725 }
1726
1727 /* PHY state control function */
1728 static void sh_eth_adjust_link(struct net_device *ndev)
1729 {
1730 struct sh_eth_private *mdp = netdev_priv(ndev);
1731 struct phy_device *phydev = mdp->phydev;
1732 int new_state = 0;
1733
1734 if (phydev->link) {
1735 if (phydev->duplex != mdp->duplex) {
1736 new_state = 1;
1737 mdp->duplex = phydev->duplex;
1738 if (mdp->cd->set_duplex)
1739 mdp->cd->set_duplex(ndev);
1740 }
1741
1742 if (phydev->speed != mdp->speed) {
1743 new_state = 1;
1744 mdp->speed = phydev->speed;
1745 if (mdp->cd->set_rate)
1746 mdp->cd->set_rate(ndev);
1747 }
1748 if (!mdp->link) {
1749 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
1750 new_state = 1;
1751 mdp->link = phydev->link;
1752 if (mdp->cd->no_psr || mdp->no_ether_link)
1753 sh_eth_rcv_snd_enable(ndev);
1754 }
1755 } else if (mdp->link) {
1756 new_state = 1;
1757 mdp->link = 0;
1758 mdp->speed = 0;
1759 mdp->duplex = -1;
1760 if (mdp->cd->no_psr || mdp->no_ether_link)
1761 sh_eth_rcv_snd_disable(ndev);
1762 }
1763
1764 if (new_state && netif_msg_link(mdp))
1765 phy_print_status(phydev);
1766 }
1767
1768 /* PHY init function */
1769 static int sh_eth_phy_init(struct net_device *ndev)
1770 {
1771 struct device_node *np = ndev->dev.parent->of_node;
1772 struct sh_eth_private *mdp = netdev_priv(ndev);
1773 struct phy_device *phydev;
1774
1775 mdp->link = 0;
1776 mdp->speed = 0;
1777 mdp->duplex = -1;
1778
1779 /* Try connect to PHY */
1780 if (np) {
1781 struct device_node *pn;
1782
1783 pn = of_parse_phandle(np, "phy-handle", 0);
1784 phydev = of_phy_connect(ndev, pn,
1785 sh_eth_adjust_link, 0,
1786 mdp->phy_interface);
1787
1788 of_node_put(pn);
1789 if (!phydev)
1790 phydev = ERR_PTR(-ENOENT);
1791 } else {
1792 char phy_id[MII_BUS_ID_SIZE + 3];
1793
1794 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1795 mdp->mii_bus->id, mdp->phy_id);
1796
1797 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1798 mdp->phy_interface);
1799 }
1800
1801 if (IS_ERR(phydev)) {
1802 netdev_err(ndev, "failed to connect PHY\n");
1803 return PTR_ERR(phydev);
1804 }
1805
1806 phy_attached_info(phydev);
1807
1808 mdp->phydev = phydev;
1809
1810 return 0;
1811 }
1812
1813 /* PHY control start function */
1814 static int sh_eth_phy_start(struct net_device *ndev)
1815 {
1816 struct sh_eth_private *mdp = netdev_priv(ndev);
1817 int ret;
1818
1819 ret = sh_eth_phy_init(ndev);
1820 if (ret)
1821 return ret;
1822
1823 phy_start(mdp->phydev);
1824
1825 return 0;
1826 }
1827
1828 static int sh_eth_get_settings(struct net_device *ndev,
1829 struct ethtool_cmd *ecmd)
1830 {
1831 struct sh_eth_private *mdp = netdev_priv(ndev);
1832 unsigned long flags;
1833 int ret;
1834
1835 if (!mdp->phydev)
1836 return -ENODEV;
1837
1838 spin_lock_irqsave(&mdp->lock, flags);
1839 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1840 spin_unlock_irqrestore(&mdp->lock, flags);
1841
1842 return ret;
1843 }
1844
1845 static int sh_eth_set_settings(struct net_device *ndev,
1846 struct ethtool_cmd *ecmd)
1847 {
1848 struct sh_eth_private *mdp = netdev_priv(ndev);
1849 unsigned long flags;
1850 int ret;
1851
1852 if (!mdp->phydev)
1853 return -ENODEV;
1854
1855 spin_lock_irqsave(&mdp->lock, flags);
1856
1857 /* disable tx and rx */
1858 sh_eth_rcv_snd_disable(ndev);
1859
1860 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1861 if (ret)
1862 goto error_exit;
1863
1864 if (ecmd->duplex == DUPLEX_FULL)
1865 mdp->duplex = 1;
1866 else
1867 mdp->duplex = 0;
1868
1869 if (mdp->cd->set_duplex)
1870 mdp->cd->set_duplex(ndev);
1871
1872 error_exit:
1873 mdelay(1);
1874
1875 /* enable tx and rx */
1876 sh_eth_rcv_snd_enable(ndev);
1877
1878 spin_unlock_irqrestore(&mdp->lock, flags);
1879
1880 return ret;
1881 }
1882
1883 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1884 * version must be bumped as well. Just adding registers up to that
1885 * limit is fine, as long as the existing register indices don't
1886 * change.
1887 */
1888 #define SH_ETH_REG_DUMP_VERSION 1
1889 #define SH_ETH_REG_DUMP_MAX_REGS 256
1890
1891 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1892 {
1893 struct sh_eth_private *mdp = netdev_priv(ndev);
1894 struct sh_eth_cpu_data *cd = mdp->cd;
1895 u32 *valid_map;
1896 size_t len;
1897
1898 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1899
1900 /* Dump starts with a bitmap that tells ethtool which
1901 * registers are defined for this chip.
1902 */
1903 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1904 if (buf) {
1905 valid_map = buf;
1906 buf += len;
1907 } else {
1908 valid_map = NULL;
1909 }
1910
1911 /* Add a register to the dump, if it has a defined offset.
1912 * This automatically skips most undefined registers, but for
1913 * some it is also necessary to check a capability flag in
1914 * struct sh_eth_cpu_data.
1915 */
1916 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1917 #define add_reg_from(reg, read_expr) do { \
1918 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
1919 if (buf) { \
1920 mark_reg_valid(reg); \
1921 *buf++ = read_expr; \
1922 } \
1923 ++len; \
1924 } \
1925 } while (0)
1926 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
1927 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
1928
1929 add_reg(EDSR);
1930 add_reg(EDMR);
1931 add_reg(EDTRR);
1932 add_reg(EDRRR);
1933 add_reg(EESR);
1934 add_reg(EESIPR);
1935 add_reg(TDLAR);
1936 add_reg(TDFAR);
1937 add_reg(TDFXR);
1938 add_reg(TDFFR);
1939 add_reg(RDLAR);
1940 add_reg(RDFAR);
1941 add_reg(RDFXR);
1942 add_reg(RDFFR);
1943 add_reg(TRSCER);
1944 add_reg(RMFCR);
1945 add_reg(TFTR);
1946 add_reg(FDR);
1947 add_reg(RMCR);
1948 add_reg(TFUCR);
1949 add_reg(RFOCR);
1950 if (cd->rmiimode)
1951 add_reg(RMIIMODE);
1952 add_reg(FCFTR);
1953 if (cd->rpadir)
1954 add_reg(RPADIR);
1955 if (!cd->no_trimd)
1956 add_reg(TRIMD);
1957 add_reg(ECMR);
1958 add_reg(ECSR);
1959 add_reg(ECSIPR);
1960 add_reg(PIR);
1961 if (!cd->no_psr)
1962 add_reg(PSR);
1963 add_reg(RDMLR);
1964 add_reg(RFLR);
1965 add_reg(IPGR);
1966 if (cd->apr)
1967 add_reg(APR);
1968 if (cd->mpr)
1969 add_reg(MPR);
1970 add_reg(RFCR);
1971 add_reg(RFCF);
1972 if (cd->tpauser)
1973 add_reg(TPAUSER);
1974 add_reg(TPAUSECR);
1975 add_reg(GECMR);
1976 if (cd->bculr)
1977 add_reg(BCULR);
1978 add_reg(MAHR);
1979 add_reg(MALR);
1980 add_reg(TROCR);
1981 add_reg(CDCR);
1982 add_reg(LCCR);
1983 add_reg(CNDCR);
1984 add_reg(CEFCR);
1985 add_reg(FRECR);
1986 add_reg(TSFRCR);
1987 add_reg(TLFRCR);
1988 add_reg(CERCR);
1989 add_reg(CEECR);
1990 add_reg(MAFCR);
1991 if (cd->rtrate)
1992 add_reg(RTRATE);
1993 if (cd->hw_crc)
1994 add_reg(CSMR);
1995 if (cd->select_mii)
1996 add_reg(RMII_MII);
1997 add_reg(ARSTR);
1998 if (cd->tsu) {
1999 add_tsu_reg(TSU_CTRST);
2000 add_tsu_reg(TSU_FWEN0);
2001 add_tsu_reg(TSU_FWEN1);
2002 add_tsu_reg(TSU_FCM);
2003 add_tsu_reg(TSU_BSYSL0);
2004 add_tsu_reg(TSU_BSYSL1);
2005 add_tsu_reg(TSU_PRISL0);
2006 add_tsu_reg(TSU_PRISL1);
2007 add_tsu_reg(TSU_FWSL0);
2008 add_tsu_reg(TSU_FWSL1);
2009 add_tsu_reg(TSU_FWSLC);
2010 add_tsu_reg(TSU_QTAG0);
2011 add_tsu_reg(TSU_QTAG1);
2012 add_tsu_reg(TSU_QTAGM0);
2013 add_tsu_reg(TSU_QTAGM1);
2014 add_tsu_reg(TSU_FWSR);
2015 add_tsu_reg(TSU_FWINMK);
2016 add_tsu_reg(TSU_ADQT0);
2017 add_tsu_reg(TSU_ADQT1);
2018 add_tsu_reg(TSU_VTAG0);
2019 add_tsu_reg(TSU_VTAG1);
2020 add_tsu_reg(TSU_ADSBSY);
2021 add_tsu_reg(TSU_TEN);
2022 add_tsu_reg(TSU_POST1);
2023 add_tsu_reg(TSU_POST2);
2024 add_tsu_reg(TSU_POST3);
2025 add_tsu_reg(TSU_POST4);
2026 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2027 /* This is the start of a table, not just a single
2028 * register.
2029 */
2030 if (buf) {
2031 unsigned int i;
2032
2033 mark_reg_valid(TSU_ADRH0);
2034 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2035 *buf++ = ioread32(
2036 mdp->tsu_addr +
2037 mdp->reg_offset[TSU_ADRH0] +
2038 i * 4);
2039 }
2040 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2041 }
2042 }
2043
2044 #undef mark_reg_valid
2045 #undef add_reg_from
2046 #undef add_reg
2047 #undef add_tsu_reg
2048
2049 return len * 4;
2050 }
2051
2052 static int sh_eth_get_regs_len(struct net_device *ndev)
2053 {
2054 return __sh_eth_get_regs(ndev, NULL);
2055 }
2056
2057 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2058 void *buf)
2059 {
2060 struct sh_eth_private *mdp = netdev_priv(ndev);
2061
2062 regs->version = SH_ETH_REG_DUMP_VERSION;
2063
2064 pm_runtime_get_sync(&mdp->pdev->dev);
2065 __sh_eth_get_regs(ndev, buf);
2066 pm_runtime_put_sync(&mdp->pdev->dev);
2067 }
2068
2069 static int sh_eth_nway_reset(struct net_device *ndev)
2070 {
2071 struct sh_eth_private *mdp = netdev_priv(ndev);
2072 unsigned long flags;
2073 int ret;
2074
2075 if (!mdp->phydev)
2076 return -ENODEV;
2077
2078 spin_lock_irqsave(&mdp->lock, flags);
2079 ret = phy_start_aneg(mdp->phydev);
2080 spin_unlock_irqrestore(&mdp->lock, flags);
2081
2082 return ret;
2083 }
2084
2085 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2086 {
2087 struct sh_eth_private *mdp = netdev_priv(ndev);
2088 return mdp->msg_enable;
2089 }
2090
2091 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2092 {
2093 struct sh_eth_private *mdp = netdev_priv(ndev);
2094 mdp->msg_enable = value;
2095 }
2096
2097 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2098 "rx_current", "tx_current",
2099 "rx_dirty", "tx_dirty",
2100 };
2101 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2102
2103 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2104 {
2105 switch (sset) {
2106 case ETH_SS_STATS:
2107 return SH_ETH_STATS_LEN;
2108 default:
2109 return -EOPNOTSUPP;
2110 }
2111 }
2112
2113 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2114 struct ethtool_stats *stats, u64 *data)
2115 {
2116 struct sh_eth_private *mdp = netdev_priv(ndev);
2117 int i = 0;
2118
2119 /* device-specific stats */
2120 data[i++] = mdp->cur_rx;
2121 data[i++] = mdp->cur_tx;
2122 data[i++] = mdp->dirty_rx;
2123 data[i++] = mdp->dirty_tx;
2124 }
2125
2126 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2127 {
2128 switch (stringset) {
2129 case ETH_SS_STATS:
2130 memcpy(data, *sh_eth_gstrings_stats,
2131 sizeof(sh_eth_gstrings_stats));
2132 break;
2133 }
2134 }
2135
2136 static void sh_eth_get_ringparam(struct net_device *ndev,
2137 struct ethtool_ringparam *ring)
2138 {
2139 struct sh_eth_private *mdp = netdev_priv(ndev);
2140
2141 ring->rx_max_pending = RX_RING_MAX;
2142 ring->tx_max_pending = TX_RING_MAX;
2143 ring->rx_pending = mdp->num_rx_ring;
2144 ring->tx_pending = mdp->num_tx_ring;
2145 }
2146
2147 static int sh_eth_set_ringparam(struct net_device *ndev,
2148 struct ethtool_ringparam *ring)
2149 {
2150 struct sh_eth_private *mdp = netdev_priv(ndev);
2151 int ret;
2152
2153 if (ring->tx_pending > TX_RING_MAX ||
2154 ring->rx_pending > RX_RING_MAX ||
2155 ring->tx_pending < TX_RING_MIN ||
2156 ring->rx_pending < RX_RING_MIN)
2157 return -EINVAL;
2158 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2159 return -EINVAL;
2160
2161 if (netif_running(ndev)) {
2162 netif_device_detach(ndev);
2163 netif_tx_disable(ndev);
2164
2165 /* Serialise with the interrupt handler and NAPI, then
2166 * disable interrupts. We have to clear the
2167 * irq_enabled flag first to ensure that interrupts
2168 * won't be re-enabled.
2169 */
2170 mdp->irq_enabled = false;
2171 synchronize_irq(ndev->irq);
2172 napi_synchronize(&mdp->napi);
2173 sh_eth_write(ndev, 0x0000, EESIPR);
2174
2175 sh_eth_dev_exit(ndev);
2176
2177 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2178 sh_eth_ring_free(ndev);
2179 }
2180
2181 /* Set new parameters */
2182 mdp->num_rx_ring = ring->rx_pending;
2183 mdp->num_tx_ring = ring->tx_pending;
2184
2185 if (netif_running(ndev)) {
2186 ret = sh_eth_ring_init(ndev);
2187 if (ret < 0) {
2188 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2189 __func__);
2190 return ret;
2191 }
2192 ret = sh_eth_dev_init(ndev);
2193 if (ret < 0) {
2194 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2195 __func__);
2196 return ret;
2197 }
2198
2199 netif_device_attach(ndev);
2200 }
2201
2202 return 0;
2203 }
2204
2205 static const struct ethtool_ops sh_eth_ethtool_ops = {
2206 .get_settings = sh_eth_get_settings,
2207 .set_settings = sh_eth_set_settings,
2208 .get_regs_len = sh_eth_get_regs_len,
2209 .get_regs = sh_eth_get_regs,
2210 .nway_reset = sh_eth_nway_reset,
2211 .get_msglevel = sh_eth_get_msglevel,
2212 .set_msglevel = sh_eth_set_msglevel,
2213 .get_link = ethtool_op_get_link,
2214 .get_strings = sh_eth_get_strings,
2215 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2216 .get_sset_count = sh_eth_get_sset_count,
2217 .get_ringparam = sh_eth_get_ringparam,
2218 .set_ringparam = sh_eth_set_ringparam,
2219 };
2220
2221 /* network device open function */
2222 static int sh_eth_open(struct net_device *ndev)
2223 {
2224 struct sh_eth_private *mdp = netdev_priv(ndev);
2225 int ret;
2226
2227 pm_runtime_get_sync(&mdp->pdev->dev);
2228
2229 napi_enable(&mdp->napi);
2230
2231 ret = request_irq(ndev->irq, sh_eth_interrupt,
2232 mdp->cd->irq_flags, ndev->name, ndev);
2233 if (ret) {
2234 netdev_err(ndev, "Can not assign IRQ number\n");
2235 goto out_napi_off;
2236 }
2237
2238 /* Descriptor set */
2239 ret = sh_eth_ring_init(ndev);
2240 if (ret)
2241 goto out_free_irq;
2242
2243 /* device init */
2244 ret = sh_eth_dev_init(ndev);
2245 if (ret)
2246 goto out_free_irq;
2247
2248 /* PHY control start*/
2249 ret = sh_eth_phy_start(ndev);
2250 if (ret)
2251 goto out_free_irq;
2252
2253 netif_start_queue(ndev);
2254
2255 mdp->is_opened = 1;
2256
2257 return ret;
2258
2259 out_free_irq:
2260 free_irq(ndev->irq, ndev);
2261 out_napi_off:
2262 napi_disable(&mdp->napi);
2263 pm_runtime_put_sync(&mdp->pdev->dev);
2264 return ret;
2265 }
2266
2267 /* Timeout function */
2268 static void sh_eth_tx_timeout(struct net_device *ndev)
2269 {
2270 struct sh_eth_private *mdp = netdev_priv(ndev);
2271 struct sh_eth_rxdesc *rxdesc;
2272 int i;
2273
2274 netif_stop_queue(ndev);
2275
2276 netif_err(mdp, timer, ndev,
2277 "transmit timed out, status %8.8x, resetting...\n",
2278 sh_eth_read(ndev, EESR));
2279
2280 /* tx_errors count up */
2281 ndev->stats.tx_errors++;
2282
2283 /* Free all the skbuffs in the Rx queue. */
2284 for (i = 0; i < mdp->num_rx_ring; i++) {
2285 rxdesc = &mdp->rx_ring[i];
2286 rxdesc->status = cpu_to_le32(0);
2287 rxdesc->addr = cpu_to_le32(0xBADF00D0);
2288 dev_kfree_skb(mdp->rx_skbuff[i]);
2289 mdp->rx_skbuff[i] = NULL;
2290 }
2291 for (i = 0; i < mdp->num_tx_ring; i++) {
2292 dev_kfree_skb(mdp->tx_skbuff[i]);
2293 mdp->tx_skbuff[i] = NULL;
2294 }
2295
2296 /* device init */
2297 sh_eth_dev_init(ndev);
2298
2299 netif_start_queue(ndev);
2300 }
2301
2302 /* Packet transmit function */
2303 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2304 {
2305 struct sh_eth_private *mdp = netdev_priv(ndev);
2306 struct sh_eth_txdesc *txdesc;
2307 dma_addr_t dma_addr;
2308 u32 entry;
2309 unsigned long flags;
2310
2311 spin_lock_irqsave(&mdp->lock, flags);
2312 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2313 if (!sh_eth_txfree(ndev)) {
2314 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2315 netif_stop_queue(ndev);
2316 spin_unlock_irqrestore(&mdp->lock, flags);
2317 return NETDEV_TX_BUSY;
2318 }
2319 }
2320 spin_unlock_irqrestore(&mdp->lock, flags);
2321
2322 if (skb_put_padto(skb, ETH_ZLEN))
2323 return NETDEV_TX_OK;
2324
2325 entry = mdp->cur_tx % mdp->num_tx_ring;
2326 mdp->tx_skbuff[entry] = skb;
2327 txdesc = &mdp->tx_ring[entry];
2328 /* soft swap. */
2329 if (!mdp->cd->hw_swap)
2330 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2331 dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2332 DMA_TO_DEVICE);
2333 if (dma_mapping_error(&ndev->dev, dma_addr)) {
2334 kfree_skb(skb);
2335 return NETDEV_TX_OK;
2336 }
2337 txdesc->addr = cpu_to_le32(dma_addr);
2338 txdesc->len = cpu_to_le32(skb->len << 16);
2339
2340 dma_wmb(); /* TACT bit must be set after all the above writes */
2341 if (entry >= mdp->num_tx_ring - 1)
2342 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
2343 else
2344 txdesc->status |= cpu_to_le32(TD_TACT);
2345
2346 mdp->cur_tx++;
2347
2348 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2349 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2350
2351 return NETDEV_TX_OK;
2352 }
2353
2354 /* The statistics registers have write-clear behaviour, which means we
2355 * will lose any increment between the read and write. We mitigate
2356 * this by only clearing when we read a non-zero value, so we will
2357 * never falsely report a total of zero.
2358 */
2359 static void
2360 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2361 {
2362 u32 delta = sh_eth_read(ndev, reg);
2363
2364 if (delta) {
2365 *stat += delta;
2366 sh_eth_write(ndev, 0, reg);
2367 }
2368 }
2369
2370 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2371 {
2372 struct sh_eth_private *mdp = netdev_priv(ndev);
2373
2374 if (sh_eth_is_rz_fast_ether(mdp))
2375 return &ndev->stats;
2376
2377 if (!mdp->is_opened)
2378 return &ndev->stats;
2379
2380 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2381 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2382 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2383
2384 if (sh_eth_is_gether(mdp)) {
2385 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2386 CERCR);
2387 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2388 CEECR);
2389 } else {
2390 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2391 CNDCR);
2392 }
2393
2394 return &ndev->stats;
2395 }
2396
2397 /* device close function */
2398 static int sh_eth_close(struct net_device *ndev)
2399 {
2400 struct sh_eth_private *mdp = netdev_priv(ndev);
2401
2402 netif_stop_queue(ndev);
2403
2404 /* Serialise with the interrupt handler and NAPI, then disable
2405 * interrupts. We have to clear the irq_enabled flag first to
2406 * ensure that interrupts won't be re-enabled.
2407 */
2408 mdp->irq_enabled = false;
2409 synchronize_irq(ndev->irq);
2410 napi_disable(&mdp->napi);
2411 sh_eth_write(ndev, 0x0000, EESIPR);
2412
2413 sh_eth_dev_exit(ndev);
2414
2415 /* PHY Disconnect */
2416 if (mdp->phydev) {
2417 phy_stop(mdp->phydev);
2418 phy_disconnect(mdp->phydev);
2419 mdp->phydev = NULL;
2420 }
2421
2422 free_irq(ndev->irq, ndev);
2423
2424 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2425 sh_eth_ring_free(ndev);
2426
2427 pm_runtime_put_sync(&mdp->pdev->dev);
2428
2429 mdp->is_opened = 0;
2430
2431 return 0;
2432 }
2433
2434 /* ioctl to device function */
2435 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2436 {
2437 struct sh_eth_private *mdp = netdev_priv(ndev);
2438 struct phy_device *phydev = mdp->phydev;
2439
2440 if (!netif_running(ndev))
2441 return -EINVAL;
2442
2443 if (!phydev)
2444 return -ENODEV;
2445
2446 return phy_mii_ioctl(phydev, rq, cmd);
2447 }
2448
2449 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2450 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2451 int entry)
2452 {
2453 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2454 }
2455
2456 static u32 sh_eth_tsu_get_post_mask(int entry)
2457 {
2458 return 0x0f << (28 - ((entry % 8) * 4));
2459 }
2460
2461 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2462 {
2463 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2464 }
2465
2466 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2467 int entry)
2468 {
2469 struct sh_eth_private *mdp = netdev_priv(ndev);
2470 u32 tmp;
2471 void *reg_offset;
2472
2473 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2474 tmp = ioread32(reg_offset);
2475 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2476 }
2477
2478 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2479 int entry)
2480 {
2481 struct sh_eth_private *mdp = netdev_priv(ndev);
2482 u32 post_mask, ref_mask, tmp;
2483 void *reg_offset;
2484
2485 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2486 post_mask = sh_eth_tsu_get_post_mask(entry);
2487 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2488
2489 tmp = ioread32(reg_offset);
2490 iowrite32(tmp & ~post_mask, reg_offset);
2491
2492 /* If other port enables, the function returns "true" */
2493 return tmp & ref_mask;
2494 }
2495
2496 static int sh_eth_tsu_busy(struct net_device *ndev)
2497 {
2498 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2499 struct sh_eth_private *mdp = netdev_priv(ndev);
2500
2501 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2502 udelay(10);
2503 timeout--;
2504 if (timeout <= 0) {
2505 netdev_err(ndev, "%s: timeout\n", __func__);
2506 return -ETIMEDOUT;
2507 }
2508 }
2509
2510 return 0;
2511 }
2512
2513 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2514 const u8 *addr)
2515 {
2516 u32 val;
2517
2518 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2519 iowrite32(val, reg);
2520 if (sh_eth_tsu_busy(ndev) < 0)
2521 return -EBUSY;
2522
2523 val = addr[4] << 8 | addr[5];
2524 iowrite32(val, reg + 4);
2525 if (sh_eth_tsu_busy(ndev) < 0)
2526 return -EBUSY;
2527
2528 return 0;
2529 }
2530
2531 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2532 {
2533 u32 val;
2534
2535 val = ioread32(reg);
2536 addr[0] = (val >> 24) & 0xff;
2537 addr[1] = (val >> 16) & 0xff;
2538 addr[2] = (val >> 8) & 0xff;
2539 addr[3] = val & 0xff;
2540 val = ioread32(reg + 4);
2541 addr[4] = (val >> 8) & 0xff;
2542 addr[5] = val & 0xff;
2543 }
2544
2545
2546 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2547 {
2548 struct sh_eth_private *mdp = netdev_priv(ndev);
2549 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2550 int i;
2551 u8 c_addr[ETH_ALEN];
2552
2553 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2554 sh_eth_tsu_read_entry(reg_offset, c_addr);
2555 if (ether_addr_equal(addr, c_addr))
2556 return i;
2557 }
2558
2559 return -ENOENT;
2560 }
2561
2562 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2563 {
2564 u8 blank[ETH_ALEN];
2565 int entry;
2566
2567 memset(blank, 0, sizeof(blank));
2568 entry = sh_eth_tsu_find_entry(ndev, blank);
2569 return (entry < 0) ? -ENOMEM : entry;
2570 }
2571
2572 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2573 int entry)
2574 {
2575 struct sh_eth_private *mdp = netdev_priv(ndev);
2576 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2577 int ret;
2578 u8 blank[ETH_ALEN];
2579
2580 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2581 ~(1 << (31 - entry)), TSU_TEN);
2582
2583 memset(blank, 0, sizeof(blank));
2584 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2585 if (ret < 0)
2586 return ret;
2587 return 0;
2588 }
2589
2590 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2591 {
2592 struct sh_eth_private *mdp = netdev_priv(ndev);
2593 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2594 int i, ret;
2595
2596 if (!mdp->cd->tsu)
2597 return 0;
2598
2599 i = sh_eth_tsu_find_entry(ndev, addr);
2600 if (i < 0) {
2601 /* No entry found, create one */
2602 i = sh_eth_tsu_find_empty(ndev);
2603 if (i < 0)
2604 return -ENOMEM;
2605 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2606 if (ret < 0)
2607 return ret;
2608
2609 /* Enable the entry */
2610 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2611 (1 << (31 - i)), TSU_TEN);
2612 }
2613
2614 /* Entry found or created, enable POST */
2615 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2616
2617 return 0;
2618 }
2619
2620 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2621 {
2622 struct sh_eth_private *mdp = netdev_priv(ndev);
2623 int i, ret;
2624
2625 if (!mdp->cd->tsu)
2626 return 0;
2627
2628 i = sh_eth_tsu_find_entry(ndev, addr);
2629 if (i) {
2630 /* Entry found */
2631 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2632 goto done;
2633
2634 /* Disable the entry if both ports was disabled */
2635 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2636 if (ret < 0)
2637 return ret;
2638 }
2639 done:
2640 return 0;
2641 }
2642
2643 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2644 {
2645 struct sh_eth_private *mdp = netdev_priv(ndev);
2646 int i, ret;
2647
2648 if (!mdp->cd->tsu)
2649 return 0;
2650
2651 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2652 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2653 continue;
2654
2655 /* Disable the entry if both ports was disabled */
2656 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2657 if (ret < 0)
2658 return ret;
2659 }
2660
2661 return 0;
2662 }
2663
2664 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2665 {
2666 struct sh_eth_private *mdp = netdev_priv(ndev);
2667 u8 addr[ETH_ALEN];
2668 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2669 int i;
2670
2671 if (!mdp->cd->tsu)
2672 return;
2673
2674 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2675 sh_eth_tsu_read_entry(reg_offset, addr);
2676 if (is_multicast_ether_addr(addr))
2677 sh_eth_tsu_del_entry(ndev, addr);
2678 }
2679 }
2680
2681 /* Update promiscuous flag and multicast filter */
2682 static void sh_eth_set_rx_mode(struct net_device *ndev)
2683 {
2684 struct sh_eth_private *mdp = netdev_priv(ndev);
2685 u32 ecmr_bits;
2686 int mcast_all = 0;
2687 unsigned long flags;
2688
2689 spin_lock_irqsave(&mdp->lock, flags);
2690 /* Initial condition is MCT = 1, PRM = 0.
2691 * Depending on ndev->flags, set PRM or clear MCT
2692 */
2693 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2694 if (mdp->cd->tsu)
2695 ecmr_bits |= ECMR_MCT;
2696
2697 if (!(ndev->flags & IFF_MULTICAST)) {
2698 sh_eth_tsu_purge_mcast(ndev);
2699 mcast_all = 1;
2700 }
2701 if (ndev->flags & IFF_ALLMULTI) {
2702 sh_eth_tsu_purge_mcast(ndev);
2703 ecmr_bits &= ~ECMR_MCT;
2704 mcast_all = 1;
2705 }
2706
2707 if (ndev->flags & IFF_PROMISC) {
2708 sh_eth_tsu_purge_all(ndev);
2709 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2710 } else if (mdp->cd->tsu) {
2711 struct netdev_hw_addr *ha;
2712 netdev_for_each_mc_addr(ha, ndev) {
2713 if (mcast_all && is_multicast_ether_addr(ha->addr))
2714 continue;
2715
2716 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2717 if (!mcast_all) {
2718 sh_eth_tsu_purge_mcast(ndev);
2719 ecmr_bits &= ~ECMR_MCT;
2720 mcast_all = 1;
2721 }
2722 }
2723 }
2724 }
2725
2726 /* update the ethernet mode */
2727 sh_eth_write(ndev, ecmr_bits, ECMR);
2728
2729 spin_unlock_irqrestore(&mdp->lock, flags);
2730 }
2731
2732 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2733 {
2734 if (!mdp->port)
2735 return TSU_VTAG0;
2736 else
2737 return TSU_VTAG1;
2738 }
2739
2740 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2741 __be16 proto, u16 vid)
2742 {
2743 struct sh_eth_private *mdp = netdev_priv(ndev);
2744 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2745
2746 if (unlikely(!mdp->cd->tsu))
2747 return -EPERM;
2748
2749 /* No filtering if vid = 0 */
2750 if (!vid)
2751 return 0;
2752
2753 mdp->vlan_num_ids++;
2754
2755 /* The controller has one VLAN tag HW filter. So, if the filter is
2756 * already enabled, the driver disables it and the filte
2757 */
2758 if (mdp->vlan_num_ids > 1) {
2759 /* disable VLAN filter */
2760 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2761 return 0;
2762 }
2763
2764 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2765 vtag_reg_index);
2766
2767 return 0;
2768 }
2769
2770 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2771 __be16 proto, u16 vid)
2772 {
2773 struct sh_eth_private *mdp = netdev_priv(ndev);
2774 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2775
2776 if (unlikely(!mdp->cd->tsu))
2777 return -EPERM;
2778
2779 /* No filtering if vid = 0 */
2780 if (!vid)
2781 return 0;
2782
2783 mdp->vlan_num_ids--;
2784 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2785
2786 return 0;
2787 }
2788
2789 /* SuperH's TSU register init function */
2790 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2791 {
2792 if (sh_eth_is_rz_fast_ether(mdp)) {
2793 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2794 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
2795 TSU_FWSLC); /* Enable POST registers */
2796 return;
2797 }
2798
2799 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2800 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2801 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2802 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2803 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2804 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2805 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2806 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2807 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2808 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2809 if (sh_eth_is_gether(mdp)) {
2810 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2811 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2812 } else {
2813 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2814 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2815 }
2816 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2817 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2818 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2819 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2820 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2821 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2822 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
2823 }
2824
2825 /* MDIO bus release function */
2826 static int sh_mdio_release(struct sh_eth_private *mdp)
2827 {
2828 /* unregister mdio bus */
2829 mdiobus_unregister(mdp->mii_bus);
2830
2831 /* free bitbang info */
2832 free_mdio_bitbang(mdp->mii_bus);
2833
2834 return 0;
2835 }
2836
2837 /* MDIO bus init function */
2838 static int sh_mdio_init(struct sh_eth_private *mdp,
2839 struct sh_eth_plat_data *pd)
2840 {
2841 int ret;
2842 struct bb_info *bitbang;
2843 struct platform_device *pdev = mdp->pdev;
2844 struct device *dev = &mdp->pdev->dev;
2845
2846 /* create bit control struct for PHY */
2847 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2848 if (!bitbang)
2849 return -ENOMEM;
2850
2851 /* bitbang init */
2852 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2853 bitbang->set_gate = pd->set_mdio_gate;
2854 bitbang->ctrl.ops = &bb_ops;
2855
2856 /* MII controller setting */
2857 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2858 if (!mdp->mii_bus)
2859 return -ENOMEM;
2860
2861 /* Hook up MII support for ethtool */
2862 mdp->mii_bus->name = "sh_mii";
2863 mdp->mii_bus->parent = dev;
2864 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2865 pdev->name, pdev->id);
2866
2867 /* register MDIO bus */
2868 if (dev->of_node) {
2869 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
2870 } else {
2871 if (pd->phy_irq > 0)
2872 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2873
2874 ret = mdiobus_register(mdp->mii_bus);
2875 }
2876
2877 if (ret)
2878 goto out_free_bus;
2879
2880 return 0;
2881
2882 out_free_bus:
2883 free_mdio_bitbang(mdp->mii_bus);
2884 return ret;
2885 }
2886
2887 static const u16 *sh_eth_get_register_offset(int register_type)
2888 {
2889 const u16 *reg_offset = NULL;
2890
2891 switch (register_type) {
2892 case SH_ETH_REG_GIGABIT:
2893 reg_offset = sh_eth_offset_gigabit;
2894 break;
2895 case SH_ETH_REG_FAST_RZ:
2896 reg_offset = sh_eth_offset_fast_rz;
2897 break;
2898 case SH_ETH_REG_FAST_RCAR:
2899 reg_offset = sh_eth_offset_fast_rcar;
2900 break;
2901 case SH_ETH_REG_FAST_SH4:
2902 reg_offset = sh_eth_offset_fast_sh4;
2903 break;
2904 case SH_ETH_REG_FAST_SH3_SH2:
2905 reg_offset = sh_eth_offset_fast_sh3_sh2;
2906 break;
2907 }
2908
2909 return reg_offset;
2910 }
2911
2912 static const struct net_device_ops sh_eth_netdev_ops = {
2913 .ndo_open = sh_eth_open,
2914 .ndo_stop = sh_eth_close,
2915 .ndo_start_xmit = sh_eth_start_xmit,
2916 .ndo_get_stats = sh_eth_get_stats,
2917 .ndo_set_rx_mode = sh_eth_set_rx_mode,
2918 .ndo_tx_timeout = sh_eth_tx_timeout,
2919 .ndo_do_ioctl = sh_eth_do_ioctl,
2920 .ndo_validate_addr = eth_validate_addr,
2921 .ndo_set_mac_address = eth_mac_addr,
2922 .ndo_change_mtu = eth_change_mtu,
2923 };
2924
2925 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2926 .ndo_open = sh_eth_open,
2927 .ndo_stop = sh_eth_close,
2928 .ndo_start_xmit = sh_eth_start_xmit,
2929 .ndo_get_stats = sh_eth_get_stats,
2930 .ndo_set_rx_mode = sh_eth_set_rx_mode,
2931 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2932 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2933 .ndo_tx_timeout = sh_eth_tx_timeout,
2934 .ndo_do_ioctl = sh_eth_do_ioctl,
2935 .ndo_validate_addr = eth_validate_addr,
2936 .ndo_set_mac_address = eth_mac_addr,
2937 .ndo_change_mtu = eth_change_mtu,
2938 };
2939
2940 #ifdef CONFIG_OF
2941 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2942 {
2943 struct device_node *np = dev->of_node;
2944 struct sh_eth_plat_data *pdata;
2945 const char *mac_addr;
2946
2947 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2948 if (!pdata)
2949 return NULL;
2950
2951 pdata->phy_interface = of_get_phy_mode(np);
2952
2953 mac_addr = of_get_mac_address(np);
2954 if (mac_addr)
2955 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2956
2957 pdata->no_ether_link =
2958 of_property_read_bool(np, "renesas,no-ether-link");
2959 pdata->ether_link_active_low =
2960 of_property_read_bool(np, "renesas,ether-link-active-low");
2961
2962 return pdata;
2963 }
2964
2965 static const struct of_device_id sh_eth_match_table[] = {
2966 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
2967 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2968 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2969 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
2970 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
2971 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
2972 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
2973 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
2974 { }
2975 };
2976 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
2977 #else
2978 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2979 {
2980 return NULL;
2981 }
2982 #endif
2983
2984 static int sh_eth_drv_probe(struct platform_device *pdev)
2985 {
2986 struct resource *res;
2987 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
2988 const struct platform_device_id *id = platform_get_device_id(pdev);
2989 struct sh_eth_private *mdp;
2990 struct net_device *ndev;
2991 int ret, devno;
2992
2993 /* get base addr */
2994 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2995
2996 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2997 if (!ndev)
2998 return -ENOMEM;
2999
3000 pm_runtime_enable(&pdev->dev);
3001 pm_runtime_get_sync(&pdev->dev);
3002
3003 devno = pdev->id;
3004 if (devno < 0)
3005 devno = 0;
3006
3007 ret = platform_get_irq(pdev, 0);
3008 if (ret < 0)
3009 goto out_release;
3010 ndev->irq = ret;
3011
3012 SET_NETDEV_DEV(ndev, &pdev->dev);
3013
3014 mdp = netdev_priv(ndev);
3015 mdp->num_tx_ring = TX_RING_SIZE;
3016 mdp->num_rx_ring = RX_RING_SIZE;
3017 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3018 if (IS_ERR(mdp->addr)) {
3019 ret = PTR_ERR(mdp->addr);
3020 goto out_release;
3021 }
3022
3023 ndev->base_addr = res->start;
3024
3025 spin_lock_init(&mdp->lock);
3026 mdp->pdev = pdev;
3027
3028 if (pdev->dev.of_node)
3029 pd = sh_eth_parse_dt(&pdev->dev);
3030 if (!pd) {
3031 dev_err(&pdev->dev, "no platform data\n");
3032 ret = -EINVAL;
3033 goto out_release;
3034 }
3035
3036 /* get PHY ID */
3037 mdp->phy_id = pd->phy;
3038 mdp->phy_interface = pd->phy_interface;
3039 mdp->no_ether_link = pd->no_ether_link;
3040 mdp->ether_link_active_low = pd->ether_link_active_low;
3041
3042 /* set cpu data */
3043 if (id)
3044 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3045 else
3046 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
3047
3048 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3049 if (!mdp->reg_offset) {
3050 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3051 mdp->cd->register_type);
3052 ret = -EINVAL;
3053 goto out_release;
3054 }
3055 sh_eth_set_default_cpu_data(mdp->cd);
3056
3057 /* set function */
3058 if (mdp->cd->tsu)
3059 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3060 else
3061 ndev->netdev_ops = &sh_eth_netdev_ops;
3062 ndev->ethtool_ops = &sh_eth_ethtool_ops;
3063 ndev->watchdog_timeo = TX_TIMEOUT;
3064
3065 /* debug message level */
3066 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3067
3068 /* read and set MAC address */
3069 read_mac_address(ndev, pd->mac_addr);
3070 if (!is_valid_ether_addr(ndev->dev_addr)) {
3071 dev_warn(&pdev->dev,
3072 "no valid MAC address supplied, using a random one.\n");
3073 eth_hw_addr_random(ndev);
3074 }
3075
3076 /* ioremap the TSU registers */
3077 if (mdp->cd->tsu) {
3078 struct resource *rtsu;
3079 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3080 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3081 if (IS_ERR(mdp->tsu_addr)) {
3082 ret = PTR_ERR(mdp->tsu_addr);
3083 goto out_release;
3084 }
3085 mdp->port = devno % 2;
3086 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3087 }
3088
3089 /* initialize first or needed device */
3090 if (!devno || pd->needs_init) {
3091 if (mdp->cd->chip_reset)
3092 mdp->cd->chip_reset(ndev);
3093
3094 if (mdp->cd->tsu) {
3095 /* TSU init (Init only)*/
3096 sh_eth_tsu_init(mdp);
3097 }
3098 }
3099
3100 if (mdp->cd->rmiimode)
3101 sh_eth_write(ndev, 0x1, RMIIMODE);
3102
3103 /* MDIO bus init */
3104 ret = sh_mdio_init(mdp, pd);
3105 if (ret) {
3106 dev_err(&ndev->dev, "failed to initialise MDIO\n");
3107 goto out_release;
3108 }
3109
3110 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3111
3112 /* network device register */
3113 ret = register_netdev(ndev);
3114 if (ret)
3115 goto out_napi_del;
3116
3117 /* print device information */
3118 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3119 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3120
3121 pm_runtime_put(&pdev->dev);
3122 platform_set_drvdata(pdev, ndev);
3123
3124 return ret;
3125
3126 out_napi_del:
3127 netif_napi_del(&mdp->napi);
3128 sh_mdio_release(mdp);
3129
3130 out_release:
3131 /* net_dev free */
3132 if (ndev)
3133 free_netdev(ndev);
3134
3135 pm_runtime_put(&pdev->dev);
3136 pm_runtime_disable(&pdev->dev);
3137 return ret;
3138 }
3139
3140 static int sh_eth_drv_remove(struct platform_device *pdev)
3141 {
3142 struct net_device *ndev = platform_get_drvdata(pdev);
3143 struct sh_eth_private *mdp = netdev_priv(ndev);
3144
3145 unregister_netdev(ndev);
3146 netif_napi_del(&mdp->napi);
3147 sh_mdio_release(mdp);
3148 pm_runtime_disable(&pdev->dev);
3149 free_netdev(ndev);
3150
3151 return 0;
3152 }
3153
3154 #ifdef CONFIG_PM
3155 #ifdef CONFIG_PM_SLEEP
3156 static int sh_eth_suspend(struct device *dev)
3157 {
3158 struct net_device *ndev = dev_get_drvdata(dev);
3159 int ret = 0;
3160
3161 if (netif_running(ndev)) {
3162 netif_device_detach(ndev);
3163 ret = sh_eth_close(ndev);
3164 }
3165
3166 return ret;
3167 }
3168
3169 static int sh_eth_resume(struct device *dev)
3170 {
3171 struct net_device *ndev = dev_get_drvdata(dev);
3172 int ret = 0;
3173
3174 if (netif_running(ndev)) {
3175 ret = sh_eth_open(ndev);
3176 if (ret < 0)
3177 return ret;
3178 netif_device_attach(ndev);
3179 }
3180
3181 return ret;
3182 }
3183 #endif
3184
3185 static int sh_eth_runtime_nop(struct device *dev)
3186 {
3187 /* Runtime PM callback shared between ->runtime_suspend()
3188 * and ->runtime_resume(). Simply returns success.
3189 *
3190 * This driver re-initializes all registers after
3191 * pm_runtime_get_sync() anyway so there is no need
3192 * to save and restore registers here.
3193 */
3194 return 0;
3195 }
3196
3197 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3198 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3199 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3200 };
3201 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3202 #else
3203 #define SH_ETH_PM_OPS NULL
3204 #endif
3205
3206 static struct platform_device_id sh_eth_id_table[] = {
3207 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3208 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3209 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3210 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3211 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3212 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3213 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3214 { }
3215 };
3216 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3217
3218 static struct platform_driver sh_eth_driver = {
3219 .probe = sh_eth_drv_probe,
3220 .remove = sh_eth_drv_remove,
3221 .id_table = sh_eth_id_table,
3222 .driver = {
3223 .name = CARDNAME,
3224 .pm = SH_ETH_PM_OPS,
3225 .of_match_table = of_match_ptr(sh_eth_match_table),
3226 },
3227 };
3228
3229 module_platform_driver(sh_eth_driver);
3230
3231 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3232 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3233 MODULE_LICENSE("GPL v2");
ubuntu-zesty-kernel mirror