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[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / renesas / sh_eth.c
1 /* SuperH Ethernet device driver
2 *
3 * Copyright (C) 2014 Renesas Electronics Corporation
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
6 * Copyright (C) 2013-2017 Cogent Embedded, Inc.
7 * Copyright (C) 2014 Codethink Limited
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 */
21
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/etherdevice.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/mdio-bitbang.h>
31 #include <linux/netdevice.h>
32 #include <linux/of.h>
33 #include <linux/of_device.h>
34 #include <linux/of_irq.h>
35 #include <linux/of_net.h>
36 #include <linux/phy.h>
37 #include <linux/cache.h>
38 #include <linux/io.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/slab.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43 #include <linux/clk.h>
44 #include <linux/sh_eth.h>
45 #include <linux/of_mdio.h>
46
47 #include "sh_eth.h"
48
49 #define SH_ETH_DEF_MSG_ENABLE \
50 (NETIF_MSG_LINK | \
51 NETIF_MSG_TIMER | \
52 NETIF_MSG_RX_ERR| \
53 NETIF_MSG_TX_ERR)
54
55 #define SH_ETH_OFFSET_INVALID ((u16)~0)
56
57 #define SH_ETH_OFFSET_DEFAULTS \
58 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
59
60 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
61 SH_ETH_OFFSET_DEFAULTS,
62
63 [EDSR] = 0x0000,
64 [EDMR] = 0x0400,
65 [EDTRR] = 0x0408,
66 [EDRRR] = 0x0410,
67 [EESR] = 0x0428,
68 [EESIPR] = 0x0430,
69 [TDLAR] = 0x0010,
70 [TDFAR] = 0x0014,
71 [TDFXR] = 0x0018,
72 [TDFFR] = 0x001c,
73 [RDLAR] = 0x0030,
74 [RDFAR] = 0x0034,
75 [RDFXR] = 0x0038,
76 [RDFFR] = 0x003c,
77 [TRSCER] = 0x0438,
78 [RMFCR] = 0x0440,
79 [TFTR] = 0x0448,
80 [FDR] = 0x0450,
81 [RMCR] = 0x0458,
82 [RPADIR] = 0x0460,
83 [FCFTR] = 0x0468,
84 [CSMR] = 0x04E4,
85
86 [ECMR] = 0x0500,
87 [ECSR] = 0x0510,
88 [ECSIPR] = 0x0518,
89 [PIR] = 0x0520,
90 [PSR] = 0x0528,
91 [PIPR] = 0x052c,
92 [RFLR] = 0x0508,
93 [APR] = 0x0554,
94 [MPR] = 0x0558,
95 [PFTCR] = 0x055c,
96 [PFRCR] = 0x0560,
97 [TPAUSER] = 0x0564,
98 [GECMR] = 0x05b0,
99 [BCULR] = 0x05b4,
100 [MAHR] = 0x05c0,
101 [MALR] = 0x05c8,
102 [TROCR] = 0x0700,
103 [CDCR] = 0x0708,
104 [LCCR] = 0x0710,
105 [CEFCR] = 0x0740,
106 [FRECR] = 0x0748,
107 [TSFRCR] = 0x0750,
108 [TLFRCR] = 0x0758,
109 [RFCR] = 0x0760,
110 [CERCR] = 0x0768,
111 [CEECR] = 0x0770,
112 [MAFCR] = 0x0778,
113 [RMII_MII] = 0x0790,
114
115 [ARSTR] = 0x0000,
116 [TSU_CTRST] = 0x0004,
117 [TSU_FWEN0] = 0x0010,
118 [TSU_FWEN1] = 0x0014,
119 [TSU_FCM] = 0x0018,
120 [TSU_BSYSL0] = 0x0020,
121 [TSU_BSYSL1] = 0x0024,
122 [TSU_PRISL0] = 0x0028,
123 [TSU_PRISL1] = 0x002c,
124 [TSU_FWSL0] = 0x0030,
125 [TSU_FWSL1] = 0x0034,
126 [TSU_FWSLC] = 0x0038,
127 [TSU_QTAG0] = 0x0040,
128 [TSU_QTAG1] = 0x0044,
129 [TSU_FWSR] = 0x0050,
130 [TSU_FWINMK] = 0x0054,
131 [TSU_ADQT0] = 0x0048,
132 [TSU_ADQT1] = 0x004c,
133 [TSU_VTAG0] = 0x0058,
134 [TSU_VTAG1] = 0x005c,
135 [TSU_ADSBSY] = 0x0060,
136 [TSU_TEN] = 0x0064,
137 [TSU_POST1] = 0x0070,
138 [TSU_POST2] = 0x0074,
139 [TSU_POST3] = 0x0078,
140 [TSU_POST4] = 0x007c,
141 [TSU_ADRH0] = 0x0100,
142
143 [TXNLCR0] = 0x0080,
144 [TXALCR0] = 0x0084,
145 [RXNLCR0] = 0x0088,
146 [RXALCR0] = 0x008c,
147 [FWNLCR0] = 0x0090,
148 [FWALCR0] = 0x0094,
149 [TXNLCR1] = 0x00a0,
150 [TXALCR1] = 0x00a0,
151 [RXNLCR1] = 0x00a8,
152 [RXALCR1] = 0x00ac,
153 [FWNLCR1] = 0x00b0,
154 [FWALCR1] = 0x00b4,
155 };
156
157 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
158 SH_ETH_OFFSET_DEFAULTS,
159
160 [EDSR] = 0x0000,
161 [EDMR] = 0x0400,
162 [EDTRR] = 0x0408,
163 [EDRRR] = 0x0410,
164 [EESR] = 0x0428,
165 [EESIPR] = 0x0430,
166 [TDLAR] = 0x0010,
167 [TDFAR] = 0x0014,
168 [TDFXR] = 0x0018,
169 [TDFFR] = 0x001c,
170 [RDLAR] = 0x0030,
171 [RDFAR] = 0x0034,
172 [RDFXR] = 0x0038,
173 [RDFFR] = 0x003c,
174 [TRSCER] = 0x0438,
175 [RMFCR] = 0x0440,
176 [TFTR] = 0x0448,
177 [FDR] = 0x0450,
178 [RMCR] = 0x0458,
179 [RPADIR] = 0x0460,
180 [FCFTR] = 0x0468,
181 [CSMR] = 0x04E4,
182
183 [ECMR] = 0x0500,
184 [RFLR] = 0x0508,
185 [ECSR] = 0x0510,
186 [ECSIPR] = 0x0518,
187 [PIR] = 0x0520,
188 [APR] = 0x0554,
189 [MPR] = 0x0558,
190 [PFTCR] = 0x055c,
191 [PFRCR] = 0x0560,
192 [TPAUSER] = 0x0564,
193 [MAHR] = 0x05c0,
194 [MALR] = 0x05c8,
195 [CEFCR] = 0x0740,
196 [FRECR] = 0x0748,
197 [TSFRCR] = 0x0750,
198 [TLFRCR] = 0x0758,
199 [RFCR] = 0x0760,
200 [MAFCR] = 0x0778,
201
202 [ARSTR] = 0x0000,
203 [TSU_CTRST] = 0x0004,
204 [TSU_FWSLC] = 0x0038,
205 [TSU_VTAG0] = 0x0058,
206 [TSU_ADSBSY] = 0x0060,
207 [TSU_TEN] = 0x0064,
208 [TSU_POST1] = 0x0070,
209 [TSU_POST2] = 0x0074,
210 [TSU_POST3] = 0x0078,
211 [TSU_POST4] = 0x007c,
212 [TSU_ADRH0] = 0x0100,
213
214 [TXNLCR0] = 0x0080,
215 [TXALCR0] = 0x0084,
216 [RXNLCR0] = 0x0088,
217 [RXALCR0] = 0x008C,
218 };
219
220 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
221 SH_ETH_OFFSET_DEFAULTS,
222
223 [ECMR] = 0x0300,
224 [RFLR] = 0x0308,
225 [ECSR] = 0x0310,
226 [ECSIPR] = 0x0318,
227 [PIR] = 0x0320,
228 [PSR] = 0x0328,
229 [RDMLR] = 0x0340,
230 [IPGR] = 0x0350,
231 [APR] = 0x0354,
232 [MPR] = 0x0358,
233 [RFCF] = 0x0360,
234 [TPAUSER] = 0x0364,
235 [TPAUSECR] = 0x0368,
236 [MAHR] = 0x03c0,
237 [MALR] = 0x03c8,
238 [TROCR] = 0x03d0,
239 [CDCR] = 0x03d4,
240 [LCCR] = 0x03d8,
241 [CNDCR] = 0x03dc,
242 [CEFCR] = 0x03e4,
243 [FRECR] = 0x03e8,
244 [TSFRCR] = 0x03ec,
245 [TLFRCR] = 0x03f0,
246 [RFCR] = 0x03f4,
247 [MAFCR] = 0x03f8,
248
249 [EDMR] = 0x0200,
250 [EDTRR] = 0x0208,
251 [EDRRR] = 0x0210,
252 [TDLAR] = 0x0218,
253 [RDLAR] = 0x0220,
254 [EESR] = 0x0228,
255 [EESIPR] = 0x0230,
256 [TRSCER] = 0x0238,
257 [RMFCR] = 0x0240,
258 [TFTR] = 0x0248,
259 [FDR] = 0x0250,
260 [RMCR] = 0x0258,
261 [TFUCR] = 0x0264,
262 [RFOCR] = 0x0268,
263 [RMIIMODE] = 0x026c,
264 [FCFTR] = 0x0270,
265 [TRIMD] = 0x027c,
266 };
267
268 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
269 SH_ETH_OFFSET_DEFAULTS,
270
271 [ECMR] = 0x0100,
272 [RFLR] = 0x0108,
273 [ECSR] = 0x0110,
274 [ECSIPR] = 0x0118,
275 [PIR] = 0x0120,
276 [PSR] = 0x0128,
277 [RDMLR] = 0x0140,
278 [IPGR] = 0x0150,
279 [APR] = 0x0154,
280 [MPR] = 0x0158,
281 [TPAUSER] = 0x0164,
282 [RFCF] = 0x0160,
283 [TPAUSECR] = 0x0168,
284 [BCFRR] = 0x016c,
285 [MAHR] = 0x01c0,
286 [MALR] = 0x01c8,
287 [TROCR] = 0x01d0,
288 [CDCR] = 0x01d4,
289 [LCCR] = 0x01d8,
290 [CNDCR] = 0x01dc,
291 [CEFCR] = 0x01e4,
292 [FRECR] = 0x01e8,
293 [TSFRCR] = 0x01ec,
294 [TLFRCR] = 0x01f0,
295 [RFCR] = 0x01f4,
296 [MAFCR] = 0x01f8,
297 [RTRATE] = 0x01fc,
298
299 [EDMR] = 0x0000,
300 [EDTRR] = 0x0008,
301 [EDRRR] = 0x0010,
302 [TDLAR] = 0x0018,
303 [RDLAR] = 0x0020,
304 [EESR] = 0x0028,
305 [EESIPR] = 0x0030,
306 [TRSCER] = 0x0038,
307 [RMFCR] = 0x0040,
308 [TFTR] = 0x0048,
309 [FDR] = 0x0050,
310 [RMCR] = 0x0058,
311 [TFUCR] = 0x0064,
312 [RFOCR] = 0x0068,
313 [FCFTR] = 0x0070,
314 [RPADIR] = 0x0078,
315 [TRIMD] = 0x007c,
316 [RBWAR] = 0x00c8,
317 [RDFAR] = 0x00cc,
318 [TBRAR] = 0x00d4,
319 [TDFAR] = 0x00d8,
320 };
321
322 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
323 SH_ETH_OFFSET_DEFAULTS,
324
325 [EDMR] = 0x0000,
326 [EDTRR] = 0x0004,
327 [EDRRR] = 0x0008,
328 [TDLAR] = 0x000c,
329 [RDLAR] = 0x0010,
330 [EESR] = 0x0014,
331 [EESIPR] = 0x0018,
332 [TRSCER] = 0x001c,
333 [RMFCR] = 0x0020,
334 [TFTR] = 0x0024,
335 [FDR] = 0x0028,
336 [RMCR] = 0x002c,
337 [EDOCR] = 0x0030,
338 [FCFTR] = 0x0034,
339 [RPADIR] = 0x0038,
340 [TRIMD] = 0x003c,
341 [RBWAR] = 0x0040,
342 [RDFAR] = 0x0044,
343 [TBRAR] = 0x004c,
344 [TDFAR] = 0x0050,
345
346 [ECMR] = 0x0160,
347 [ECSR] = 0x0164,
348 [ECSIPR] = 0x0168,
349 [PIR] = 0x016c,
350 [MAHR] = 0x0170,
351 [MALR] = 0x0174,
352 [RFLR] = 0x0178,
353 [PSR] = 0x017c,
354 [TROCR] = 0x0180,
355 [CDCR] = 0x0184,
356 [LCCR] = 0x0188,
357 [CNDCR] = 0x018c,
358 [CEFCR] = 0x0194,
359 [FRECR] = 0x0198,
360 [TSFRCR] = 0x019c,
361 [TLFRCR] = 0x01a0,
362 [RFCR] = 0x01a4,
363 [MAFCR] = 0x01a8,
364 [IPGR] = 0x01b4,
365 [APR] = 0x01b8,
366 [MPR] = 0x01bc,
367 [TPAUSER] = 0x01c4,
368 [BCFR] = 0x01cc,
369
370 [ARSTR] = 0x0000,
371 [TSU_CTRST] = 0x0004,
372 [TSU_FWEN0] = 0x0010,
373 [TSU_FWEN1] = 0x0014,
374 [TSU_FCM] = 0x0018,
375 [TSU_BSYSL0] = 0x0020,
376 [TSU_BSYSL1] = 0x0024,
377 [TSU_PRISL0] = 0x0028,
378 [TSU_PRISL1] = 0x002c,
379 [TSU_FWSL0] = 0x0030,
380 [TSU_FWSL1] = 0x0034,
381 [TSU_FWSLC] = 0x0038,
382 [TSU_QTAGM0] = 0x0040,
383 [TSU_QTAGM1] = 0x0044,
384 [TSU_ADQT0] = 0x0048,
385 [TSU_ADQT1] = 0x004c,
386 [TSU_FWSR] = 0x0050,
387 [TSU_FWINMK] = 0x0054,
388 [TSU_ADSBSY] = 0x0060,
389 [TSU_TEN] = 0x0064,
390 [TSU_POST1] = 0x0070,
391 [TSU_POST2] = 0x0074,
392 [TSU_POST3] = 0x0078,
393 [TSU_POST4] = 0x007c,
394
395 [TXNLCR0] = 0x0080,
396 [TXALCR0] = 0x0084,
397 [RXNLCR0] = 0x0088,
398 [RXALCR0] = 0x008c,
399 [FWNLCR0] = 0x0090,
400 [FWALCR0] = 0x0094,
401 [TXNLCR1] = 0x00a0,
402 [TXALCR1] = 0x00a0,
403 [RXNLCR1] = 0x00a8,
404 [RXALCR1] = 0x00ac,
405 [FWNLCR1] = 0x00b0,
406 [FWALCR1] = 0x00b4,
407
408 [TSU_ADRH0] = 0x0100,
409 };
410
411 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
412 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
413
414 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
415 {
416 struct sh_eth_private *mdp = netdev_priv(ndev);
417 u16 offset = mdp->reg_offset[enum_index];
418
419 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
420 return;
421
422 iowrite32(data, mdp->addr + offset);
423 }
424
425 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
426 {
427 struct sh_eth_private *mdp = netdev_priv(ndev);
428 u16 offset = mdp->reg_offset[enum_index];
429
430 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
431 return ~0U;
432
433 return ioread32(mdp->addr + offset);
434 }
435
436 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
437 u32 set)
438 {
439 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
440 enum_index);
441 }
442
443 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
444 {
445 return mdp->reg_offset == sh_eth_offset_gigabit;
446 }
447
448 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
449 {
450 return mdp->reg_offset == sh_eth_offset_fast_rz;
451 }
452
453 static void sh_eth_select_mii(struct net_device *ndev)
454 {
455 struct sh_eth_private *mdp = netdev_priv(ndev);
456 u32 value;
457
458 switch (mdp->phy_interface) {
459 case PHY_INTERFACE_MODE_GMII:
460 value = 0x2;
461 break;
462 case PHY_INTERFACE_MODE_MII:
463 value = 0x1;
464 break;
465 case PHY_INTERFACE_MODE_RMII:
466 value = 0x0;
467 break;
468 default:
469 netdev_warn(ndev,
470 "PHY interface mode was not setup. Set to MII.\n");
471 value = 0x1;
472 break;
473 }
474
475 sh_eth_write(ndev, value, RMII_MII);
476 }
477
478 static void sh_eth_set_duplex(struct net_device *ndev)
479 {
480 struct sh_eth_private *mdp = netdev_priv(ndev);
481
482 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
483 }
484
485 static void sh_eth_chip_reset(struct net_device *ndev)
486 {
487 struct sh_eth_private *mdp = netdev_priv(ndev);
488
489 /* reset device */
490 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
491 mdelay(1);
492 }
493
494 static void sh_eth_set_rate_gether(struct net_device *ndev)
495 {
496 struct sh_eth_private *mdp = netdev_priv(ndev);
497
498 switch (mdp->speed) {
499 case 10: /* 10BASE */
500 sh_eth_write(ndev, GECMR_10, GECMR);
501 break;
502 case 100:/* 100BASE */
503 sh_eth_write(ndev, GECMR_100, GECMR);
504 break;
505 case 1000: /* 1000BASE */
506 sh_eth_write(ndev, GECMR_1000, GECMR);
507 break;
508 }
509 }
510
511 #ifdef CONFIG_OF
512 /* R7S72100 */
513 static struct sh_eth_cpu_data r7s72100_data = {
514 .chip_reset = sh_eth_chip_reset,
515 .set_duplex = sh_eth_set_duplex,
516
517 .register_type = SH_ETH_REG_FAST_RZ,
518
519 .ecsr_value = ECSR_ICD,
520 .ecsipr_value = ECSIPR_ICDIP,
521 .eesipr_value = 0xe77f009f,
522
523 .tx_check = EESR_TC1 | EESR_FTC,
524 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
525 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
526 EESR_TDE,
527 .fdr_value = 0x0000070f,
528
529 .no_psr = 1,
530 .apr = 1,
531 .mpr = 1,
532 .tpauser = 1,
533 .hw_swap = 1,
534 .rpadir = 1,
535 .rpadir_value = 2 << 16,
536 .no_trimd = 1,
537 .no_ade = 1,
538 .hw_crc = 1,
539 .tsu = 1,
540 .shift_rd0 = 1,
541 };
542
543 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
544 {
545 sh_eth_chip_reset(ndev);
546
547 sh_eth_select_mii(ndev);
548 }
549
550 /* R8A7740 */
551 static struct sh_eth_cpu_data r8a7740_data = {
552 .chip_reset = sh_eth_chip_reset_r8a7740,
553 .set_duplex = sh_eth_set_duplex,
554 .set_rate = sh_eth_set_rate_gether,
555
556 .register_type = SH_ETH_REG_GIGABIT,
557
558 .ecsr_value = ECSR_ICD | ECSR_MPD,
559 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
560 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
561
562 .tx_check = EESR_TC1 | EESR_FTC,
563 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
564 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
565 EESR_TDE,
566 .fdr_value = 0x0000070f,
567
568 .apr = 1,
569 .mpr = 1,
570 .tpauser = 1,
571 .bculr = 1,
572 .hw_swap = 1,
573 .rpadir = 1,
574 .rpadir_value = 2 << 16,
575 .no_trimd = 1,
576 .no_ade = 1,
577 .hw_crc = 1,
578 .tsu = 1,
579 .select_mii = 1,
580 .shift_rd0 = 1,
581 };
582
583 /* There is CPU dependent code */
584 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
585 {
586 struct sh_eth_private *mdp = netdev_priv(ndev);
587
588 switch (mdp->speed) {
589 case 10: /* 10BASE */
590 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
591 break;
592 case 100:/* 100BASE */
593 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
594 break;
595 }
596 }
597
598 /* R8A7778/9 */
599 static struct sh_eth_cpu_data r8a777x_data = {
600 .set_duplex = sh_eth_set_duplex,
601 .set_rate = sh_eth_set_rate_r8a777x,
602
603 .register_type = SH_ETH_REG_FAST_RCAR,
604
605 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
606 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
607 .eesipr_value = 0x01ff009f,
608
609 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
610 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
611 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
612 .fdr_value = 0x00000f0f,
613
614 .apr = 1,
615 .mpr = 1,
616 .tpauser = 1,
617 .hw_swap = 1,
618 };
619
620 /* R8A7790/1 */
621 static struct sh_eth_cpu_data r8a779x_data = {
622 .set_duplex = sh_eth_set_duplex,
623 .set_rate = sh_eth_set_rate_r8a777x,
624
625 .register_type = SH_ETH_REG_FAST_RCAR,
626
627 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
628 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
629 .eesipr_value = 0x01ff009f,
630
631 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
632 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
633 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
634 .fdr_value = 0x00000f0f,
635
636 .trscer_err_mask = DESC_I_RINT8,
637
638 .apr = 1,
639 .mpr = 1,
640 .tpauser = 1,
641 .hw_swap = 1,
642 .rmiimode = 1,
643 };
644 #endif /* CONFIG_OF */
645
646 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
647 {
648 struct sh_eth_private *mdp = netdev_priv(ndev);
649
650 switch (mdp->speed) {
651 case 10: /* 10BASE */
652 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
653 break;
654 case 100:/* 100BASE */
655 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
656 break;
657 }
658 }
659
660 /* SH7724 */
661 static struct sh_eth_cpu_data sh7724_data = {
662 .set_duplex = sh_eth_set_duplex,
663 .set_rate = sh_eth_set_rate_sh7724,
664
665 .register_type = SH_ETH_REG_FAST_SH4,
666
667 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
668 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
669 .eesipr_value = 0x01ff009f,
670
671 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
672 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
673 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
674
675 .apr = 1,
676 .mpr = 1,
677 .tpauser = 1,
678 .hw_swap = 1,
679 .rpadir = 1,
680 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
681 };
682
683 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
684 {
685 struct sh_eth_private *mdp = netdev_priv(ndev);
686
687 switch (mdp->speed) {
688 case 10: /* 10BASE */
689 sh_eth_write(ndev, 0, RTRATE);
690 break;
691 case 100:/* 100BASE */
692 sh_eth_write(ndev, 1, RTRATE);
693 break;
694 }
695 }
696
697 /* SH7757 */
698 static struct sh_eth_cpu_data sh7757_data = {
699 .set_duplex = sh_eth_set_duplex,
700 .set_rate = sh_eth_set_rate_sh7757,
701
702 .register_type = SH_ETH_REG_FAST_SH4,
703
704 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
705
706 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
707 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
708 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
709
710 .irq_flags = IRQF_SHARED,
711 .apr = 1,
712 .mpr = 1,
713 .tpauser = 1,
714 .hw_swap = 1,
715 .no_ade = 1,
716 .rpadir = 1,
717 .rpadir_value = 2 << 16,
718 .rtrate = 1,
719 };
720
721 #define SH_GIGA_ETH_BASE 0xfee00000UL
722 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
723 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
724 static void sh_eth_chip_reset_giga(struct net_device *ndev)
725 {
726 u32 mahr[2], malr[2];
727 int i;
728
729 /* save MAHR and MALR */
730 for (i = 0; i < 2; i++) {
731 malr[i] = ioread32((void *)GIGA_MALR(i));
732 mahr[i] = ioread32((void *)GIGA_MAHR(i));
733 }
734
735 sh_eth_chip_reset(ndev);
736
737 /* restore MAHR and MALR */
738 for (i = 0; i < 2; i++) {
739 iowrite32(malr[i], (void *)GIGA_MALR(i));
740 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
741 }
742 }
743
744 static void sh_eth_set_rate_giga(struct net_device *ndev)
745 {
746 struct sh_eth_private *mdp = netdev_priv(ndev);
747
748 switch (mdp->speed) {
749 case 10: /* 10BASE */
750 sh_eth_write(ndev, 0x00000000, GECMR);
751 break;
752 case 100:/* 100BASE */
753 sh_eth_write(ndev, 0x00000010, GECMR);
754 break;
755 case 1000: /* 1000BASE */
756 sh_eth_write(ndev, 0x00000020, GECMR);
757 break;
758 }
759 }
760
761 /* SH7757(GETHERC) */
762 static struct sh_eth_cpu_data sh7757_data_giga = {
763 .chip_reset = sh_eth_chip_reset_giga,
764 .set_duplex = sh_eth_set_duplex,
765 .set_rate = sh_eth_set_rate_giga,
766
767 .register_type = SH_ETH_REG_GIGABIT,
768
769 .ecsr_value = ECSR_ICD | ECSR_MPD,
770 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
771 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
772
773 .tx_check = EESR_TC1 | EESR_FTC,
774 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
775 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
776 EESR_TDE,
777 .fdr_value = 0x0000072f,
778
779 .irq_flags = IRQF_SHARED,
780 .apr = 1,
781 .mpr = 1,
782 .tpauser = 1,
783 .bculr = 1,
784 .hw_swap = 1,
785 .rpadir = 1,
786 .rpadir_value = 2 << 16,
787 .no_trimd = 1,
788 .no_ade = 1,
789 .tsu = 1,
790 };
791
792 /* SH7734 */
793 static struct sh_eth_cpu_data sh7734_data = {
794 .chip_reset = sh_eth_chip_reset,
795 .set_duplex = sh_eth_set_duplex,
796 .set_rate = sh_eth_set_rate_gether,
797
798 .register_type = SH_ETH_REG_GIGABIT,
799
800 .ecsr_value = ECSR_ICD | ECSR_MPD,
801 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
802 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003f07ff,
803
804 .tx_check = EESR_TC1 | EESR_FTC,
805 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
806 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
807 EESR_TDE,
808
809 .apr = 1,
810 .mpr = 1,
811 .tpauser = 1,
812 .bculr = 1,
813 .hw_swap = 1,
814 .no_trimd = 1,
815 .no_ade = 1,
816 .tsu = 1,
817 .hw_crc = 1,
818 .select_mii = 1,
819 .shift_rd0 = 1,
820 };
821
822 /* SH7763 */
823 static struct sh_eth_cpu_data sh7763_data = {
824 .chip_reset = sh_eth_chip_reset,
825 .set_duplex = sh_eth_set_duplex,
826 .set_rate = sh_eth_set_rate_gether,
827
828 .register_type = SH_ETH_REG_GIGABIT,
829
830 .ecsr_value = ECSR_ICD | ECSR_MPD,
831 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
832 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003f07ff,
833
834 .tx_check = EESR_TC1 | EESR_FTC,
835 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
836 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
837
838 .apr = 1,
839 .mpr = 1,
840 .tpauser = 1,
841 .bculr = 1,
842 .hw_swap = 1,
843 .no_trimd = 1,
844 .no_ade = 1,
845 .tsu = 1,
846 .irq_flags = IRQF_SHARED,
847 };
848
849 static struct sh_eth_cpu_data sh7619_data = {
850 .register_type = SH_ETH_REG_FAST_SH3_SH2,
851
852 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
853
854 .apr = 1,
855 .mpr = 1,
856 .tpauser = 1,
857 .hw_swap = 1,
858 };
859
860 static struct sh_eth_cpu_data sh771x_data = {
861 .register_type = SH_ETH_REG_FAST_SH3_SH2,
862
863 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
864 .tsu = 1,
865 };
866
867 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
868 {
869 if (!cd->ecsr_value)
870 cd->ecsr_value = DEFAULT_ECSR_INIT;
871
872 if (!cd->ecsipr_value)
873 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
874
875 if (!cd->fcftr_value)
876 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
877 DEFAULT_FIFO_F_D_RFD;
878
879 if (!cd->fdr_value)
880 cd->fdr_value = DEFAULT_FDR_INIT;
881
882 if (!cd->tx_check)
883 cd->tx_check = DEFAULT_TX_CHECK;
884
885 if (!cd->eesr_err_check)
886 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
887
888 if (!cd->trscer_err_mask)
889 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
890 }
891
892 static int sh_eth_check_reset(struct net_device *ndev)
893 {
894 int ret = 0;
895 int cnt = 100;
896
897 while (cnt > 0) {
898 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
899 break;
900 mdelay(1);
901 cnt--;
902 }
903 if (cnt <= 0) {
904 netdev_err(ndev, "Device reset failed\n");
905 ret = -ETIMEDOUT;
906 }
907 return ret;
908 }
909
910 static int sh_eth_reset(struct net_device *ndev)
911 {
912 struct sh_eth_private *mdp = netdev_priv(ndev);
913 int ret = 0;
914
915 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
916 sh_eth_write(ndev, EDSR_ENALL, EDSR);
917 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
918
919 ret = sh_eth_check_reset(ndev);
920 if (ret)
921 return ret;
922
923 /* Table Init */
924 sh_eth_write(ndev, 0x0, TDLAR);
925 sh_eth_write(ndev, 0x0, TDFAR);
926 sh_eth_write(ndev, 0x0, TDFXR);
927 sh_eth_write(ndev, 0x0, TDFFR);
928 sh_eth_write(ndev, 0x0, RDLAR);
929 sh_eth_write(ndev, 0x0, RDFAR);
930 sh_eth_write(ndev, 0x0, RDFXR);
931 sh_eth_write(ndev, 0x0, RDFFR);
932
933 /* Reset HW CRC register */
934 if (mdp->cd->hw_crc)
935 sh_eth_write(ndev, 0x0, CSMR);
936
937 /* Select MII mode */
938 if (mdp->cd->select_mii)
939 sh_eth_select_mii(ndev);
940 } else {
941 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
942 mdelay(3);
943 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
944 }
945
946 return ret;
947 }
948
949 static void sh_eth_set_receive_align(struct sk_buff *skb)
950 {
951 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
952
953 if (reserve)
954 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
955 }
956
957 /* Program the hardware MAC address from dev->dev_addr. */
958 static void update_mac_address(struct net_device *ndev)
959 {
960 sh_eth_write(ndev,
961 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
962 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
963 sh_eth_write(ndev,
964 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
965 }
966
967 /* Get MAC address from SuperH MAC address register
968 *
969 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
970 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
971 * When you want use this device, you must set MAC address in bootloader.
972 *
973 */
974 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
975 {
976 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
977 memcpy(ndev->dev_addr, mac, ETH_ALEN);
978 } else {
979 u32 mahr = sh_eth_read(ndev, MAHR);
980 u32 malr = sh_eth_read(ndev, MALR);
981
982 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
983 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
984 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
985 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
986 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
987 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
988 }
989 }
990
991 static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
992 {
993 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
994 return EDTRR_TRNS_GETHER;
995 else
996 return EDTRR_TRNS_ETHER;
997 }
998
999 struct bb_info {
1000 void (*set_gate)(void *addr);
1001 struct mdiobb_ctrl ctrl;
1002 void *addr;
1003 };
1004
1005 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1006 {
1007 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1008 u32 pir;
1009
1010 if (bitbang->set_gate)
1011 bitbang->set_gate(bitbang->addr);
1012
1013 pir = ioread32(bitbang->addr);
1014 if (set)
1015 pir |= mask;
1016 else
1017 pir &= ~mask;
1018 iowrite32(pir, bitbang->addr);
1019 }
1020
1021 /* Data I/O pin control */
1022 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1023 {
1024 sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1025 }
1026
1027 /* Set bit data*/
1028 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1029 {
1030 sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1031 }
1032
1033 /* Get bit data*/
1034 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1035 {
1036 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1037
1038 if (bitbang->set_gate)
1039 bitbang->set_gate(bitbang->addr);
1040
1041 return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1042 }
1043
1044 /* MDC pin control */
1045 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1046 {
1047 sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1048 }
1049
1050 /* mdio bus control struct */
1051 static struct mdiobb_ops bb_ops = {
1052 .owner = THIS_MODULE,
1053 .set_mdc = sh_mdc_ctrl,
1054 .set_mdio_dir = sh_mmd_ctrl,
1055 .set_mdio_data = sh_set_mdio,
1056 .get_mdio_data = sh_get_mdio,
1057 };
1058
1059 /* free skb and descriptor buffer */
1060 static void sh_eth_ring_free(struct net_device *ndev)
1061 {
1062 struct sh_eth_private *mdp = netdev_priv(ndev);
1063 int ringsize, i;
1064
1065 /* Free Rx skb ringbuffer */
1066 if (mdp->rx_skbuff) {
1067 for (i = 0; i < mdp->num_rx_ring; i++)
1068 dev_kfree_skb(mdp->rx_skbuff[i]);
1069 }
1070 kfree(mdp->rx_skbuff);
1071 mdp->rx_skbuff = NULL;
1072
1073 /* Free Tx skb ringbuffer */
1074 if (mdp->tx_skbuff) {
1075 for (i = 0; i < mdp->num_tx_ring; i++)
1076 dev_kfree_skb(mdp->tx_skbuff[i]);
1077 }
1078 kfree(mdp->tx_skbuff);
1079 mdp->tx_skbuff = NULL;
1080
1081 if (mdp->rx_ring) {
1082 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1083 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1084 mdp->rx_desc_dma);
1085 mdp->rx_ring = NULL;
1086 }
1087
1088 if (mdp->tx_ring) {
1089 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1090 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1091 mdp->tx_desc_dma);
1092 mdp->tx_ring = NULL;
1093 }
1094 }
1095
1096 /* format skb and descriptor buffer */
1097 static void sh_eth_ring_format(struct net_device *ndev)
1098 {
1099 struct sh_eth_private *mdp = netdev_priv(ndev);
1100 int i;
1101 struct sk_buff *skb;
1102 struct sh_eth_rxdesc *rxdesc = NULL;
1103 struct sh_eth_txdesc *txdesc = NULL;
1104 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1105 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1106 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1107 dma_addr_t dma_addr;
1108 u32 buf_len;
1109
1110 mdp->cur_rx = 0;
1111 mdp->cur_tx = 0;
1112 mdp->dirty_rx = 0;
1113 mdp->dirty_tx = 0;
1114
1115 memset(mdp->rx_ring, 0, rx_ringsize);
1116
1117 /* build Rx ring buffer */
1118 for (i = 0; i < mdp->num_rx_ring; i++) {
1119 /* skb */
1120 mdp->rx_skbuff[i] = NULL;
1121 skb = netdev_alloc_skb(ndev, skbuff_size);
1122 if (skb == NULL)
1123 break;
1124 sh_eth_set_receive_align(skb);
1125
1126 /* The size of the buffer is a multiple of 32 bytes. */
1127 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1128 dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len,
1129 DMA_FROM_DEVICE);
1130 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1131 kfree_skb(skb);
1132 break;
1133 }
1134 mdp->rx_skbuff[i] = skb;
1135
1136 /* RX descriptor */
1137 rxdesc = &mdp->rx_ring[i];
1138 rxdesc->len = cpu_to_le32(buf_len << 16);
1139 rxdesc->addr = cpu_to_le32(dma_addr);
1140 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
1141
1142 /* Rx descriptor address set */
1143 if (i == 0) {
1144 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1145 if (sh_eth_is_gether(mdp) ||
1146 sh_eth_is_rz_fast_ether(mdp))
1147 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1148 }
1149 }
1150
1151 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1152
1153 /* Mark the last entry as wrapping the ring. */
1154 if (rxdesc)
1155 rxdesc->status |= cpu_to_le32(RD_RDLE);
1156
1157 memset(mdp->tx_ring, 0, tx_ringsize);
1158
1159 /* build Tx ring buffer */
1160 for (i = 0; i < mdp->num_tx_ring; i++) {
1161 mdp->tx_skbuff[i] = NULL;
1162 txdesc = &mdp->tx_ring[i];
1163 txdesc->status = cpu_to_le32(TD_TFP);
1164 txdesc->len = cpu_to_le32(0);
1165 if (i == 0) {
1166 /* Tx descriptor address set */
1167 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1168 if (sh_eth_is_gether(mdp) ||
1169 sh_eth_is_rz_fast_ether(mdp))
1170 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1171 }
1172 }
1173
1174 txdesc->status |= cpu_to_le32(TD_TDLE);
1175 }
1176
1177 /* Get skb and descriptor buffer */
1178 static int sh_eth_ring_init(struct net_device *ndev)
1179 {
1180 struct sh_eth_private *mdp = netdev_priv(ndev);
1181 int rx_ringsize, tx_ringsize;
1182
1183 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1184 * card needs room to do 8 byte alignment, +2 so we can reserve
1185 * the first 2 bytes, and +16 gets room for the status word from the
1186 * card.
1187 */
1188 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1189 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1190 if (mdp->cd->rpadir)
1191 mdp->rx_buf_sz += NET_IP_ALIGN;
1192
1193 /* Allocate RX and TX skb rings */
1194 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1195 GFP_KERNEL);
1196 if (!mdp->rx_skbuff)
1197 return -ENOMEM;
1198
1199 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1200 GFP_KERNEL);
1201 if (!mdp->tx_skbuff)
1202 goto ring_free;
1203
1204 /* Allocate all Rx descriptors. */
1205 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1206 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1207 GFP_KERNEL);
1208 if (!mdp->rx_ring)
1209 goto ring_free;
1210
1211 mdp->dirty_rx = 0;
1212
1213 /* Allocate all Tx descriptors. */
1214 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1215 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1216 GFP_KERNEL);
1217 if (!mdp->tx_ring)
1218 goto ring_free;
1219 return 0;
1220
1221 ring_free:
1222 /* Free Rx and Tx skb ring buffer and DMA buffer */
1223 sh_eth_ring_free(ndev);
1224
1225 return -ENOMEM;
1226 }
1227
1228 static int sh_eth_dev_init(struct net_device *ndev)
1229 {
1230 struct sh_eth_private *mdp = netdev_priv(ndev);
1231 int ret;
1232
1233 /* Soft Reset */
1234 ret = sh_eth_reset(ndev);
1235 if (ret)
1236 return ret;
1237
1238 if (mdp->cd->rmiimode)
1239 sh_eth_write(ndev, 0x1, RMIIMODE);
1240
1241 /* Descriptor format */
1242 sh_eth_ring_format(ndev);
1243 if (mdp->cd->rpadir)
1244 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1245
1246 /* all sh_eth int mask */
1247 sh_eth_write(ndev, 0, EESIPR);
1248
1249 #if defined(__LITTLE_ENDIAN)
1250 if (mdp->cd->hw_swap)
1251 sh_eth_write(ndev, EDMR_EL, EDMR);
1252 else
1253 #endif
1254 sh_eth_write(ndev, 0, EDMR);
1255
1256 /* FIFO size set */
1257 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1258 sh_eth_write(ndev, 0, TFTR);
1259
1260 /* Frame recv control (enable multiple-packets per rx irq) */
1261 sh_eth_write(ndev, RMCR_RNC, RMCR);
1262
1263 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1264
1265 if (mdp->cd->bculr)
1266 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
1267
1268 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1269
1270 if (!mdp->cd->no_trimd)
1271 sh_eth_write(ndev, 0, TRIMD);
1272
1273 /* Recv frame limit set register */
1274 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1275 RFLR);
1276
1277 sh_eth_modify(ndev, EESR, 0, 0);
1278 mdp->irq_enabled = true;
1279 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1280
1281 /* PAUSE Prohibition */
1282 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1283 ECMR_TE | ECMR_RE, ECMR);
1284
1285 if (mdp->cd->set_rate)
1286 mdp->cd->set_rate(ndev);
1287
1288 /* E-MAC Status Register clear */
1289 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1290
1291 /* E-MAC Interrupt Enable register */
1292 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1293
1294 /* Set MAC address */
1295 update_mac_address(ndev);
1296
1297 /* mask reset */
1298 if (mdp->cd->apr)
1299 sh_eth_write(ndev, APR_AP, APR);
1300 if (mdp->cd->mpr)
1301 sh_eth_write(ndev, MPR_MP, MPR);
1302 if (mdp->cd->tpauser)
1303 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1304
1305 /* Setting the Rx mode will start the Rx process. */
1306 sh_eth_write(ndev, EDRRR_R, EDRRR);
1307
1308 return ret;
1309 }
1310
1311 static void sh_eth_dev_exit(struct net_device *ndev)
1312 {
1313 struct sh_eth_private *mdp = netdev_priv(ndev);
1314 int i;
1315
1316 /* Deactivate all TX descriptors, so DMA should stop at next
1317 * packet boundary if it's currently running
1318 */
1319 for (i = 0; i < mdp->num_tx_ring; i++)
1320 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
1321
1322 /* Disable TX FIFO egress to MAC */
1323 sh_eth_rcv_snd_disable(ndev);
1324
1325 /* Stop RX DMA at next packet boundary */
1326 sh_eth_write(ndev, 0, EDRRR);
1327
1328 /* Aside from TX DMA, we can't tell when the hardware is
1329 * really stopped, so we need to reset to make sure.
1330 * Before doing that, wait for long enough to *probably*
1331 * finish transmitting the last packet and poll stats.
1332 */
1333 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1334 sh_eth_get_stats(ndev);
1335 sh_eth_reset(ndev);
1336
1337 /* Set MAC address again */
1338 update_mac_address(ndev);
1339 }
1340
1341 /* free Tx skb function */
1342 static int sh_eth_txfree(struct net_device *ndev)
1343 {
1344 struct sh_eth_private *mdp = netdev_priv(ndev);
1345 struct sh_eth_txdesc *txdesc;
1346 int free_num = 0;
1347 int entry;
1348
1349 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1350 entry = mdp->dirty_tx % mdp->num_tx_ring;
1351 txdesc = &mdp->tx_ring[entry];
1352 if (txdesc->status & cpu_to_le32(TD_TACT))
1353 break;
1354 /* TACT bit must be checked before all the following reads */
1355 dma_rmb();
1356 netif_info(mdp, tx_done, ndev,
1357 "tx entry %d status 0x%08x\n",
1358 entry, le32_to_cpu(txdesc->status));
1359 /* Free the original skb. */
1360 if (mdp->tx_skbuff[entry]) {
1361 dma_unmap_single(&ndev->dev, le32_to_cpu(txdesc->addr),
1362 le32_to_cpu(txdesc->len) >> 16,
1363 DMA_TO_DEVICE);
1364 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1365 mdp->tx_skbuff[entry] = NULL;
1366 free_num++;
1367 }
1368 txdesc->status = cpu_to_le32(TD_TFP);
1369 if (entry >= mdp->num_tx_ring - 1)
1370 txdesc->status |= cpu_to_le32(TD_TDLE);
1371
1372 ndev->stats.tx_packets++;
1373 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1374 }
1375 return free_num;
1376 }
1377
1378 /* Packet receive function */
1379 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1380 {
1381 struct sh_eth_private *mdp = netdev_priv(ndev);
1382 struct sh_eth_rxdesc *rxdesc;
1383
1384 int entry = mdp->cur_rx % mdp->num_rx_ring;
1385 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1386 int limit;
1387 struct sk_buff *skb;
1388 u32 desc_status;
1389 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1390 dma_addr_t dma_addr;
1391 u16 pkt_len;
1392 u32 buf_len;
1393
1394 boguscnt = min(boguscnt, *quota);
1395 limit = boguscnt;
1396 rxdesc = &mdp->rx_ring[entry];
1397 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
1398 /* RACT bit must be checked before all the following reads */
1399 dma_rmb();
1400 desc_status = le32_to_cpu(rxdesc->status);
1401 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
1402
1403 if (--boguscnt < 0)
1404 break;
1405
1406 netif_info(mdp, rx_status, ndev,
1407 "rx entry %d status 0x%08x len %d\n",
1408 entry, desc_status, pkt_len);
1409
1410 if (!(desc_status & RDFEND))
1411 ndev->stats.rx_length_errors++;
1412
1413 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1414 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1415 * bit 0. However, in case of the R8A7740 and R7S72100
1416 * the RFS bits are from bit 25 to bit 16. So, the
1417 * driver needs right shifting by 16.
1418 */
1419 if (mdp->cd->shift_rd0)
1420 desc_status >>= 16;
1421
1422 skb = mdp->rx_skbuff[entry];
1423 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1424 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1425 ndev->stats.rx_errors++;
1426 if (desc_status & RD_RFS1)
1427 ndev->stats.rx_crc_errors++;
1428 if (desc_status & RD_RFS2)
1429 ndev->stats.rx_frame_errors++;
1430 if (desc_status & RD_RFS3)
1431 ndev->stats.rx_length_errors++;
1432 if (desc_status & RD_RFS4)
1433 ndev->stats.rx_length_errors++;
1434 if (desc_status & RD_RFS6)
1435 ndev->stats.rx_missed_errors++;
1436 if (desc_status & RD_RFS10)
1437 ndev->stats.rx_over_errors++;
1438 } else if (skb) {
1439 dma_addr = le32_to_cpu(rxdesc->addr);
1440 if (!mdp->cd->hw_swap)
1441 sh_eth_soft_swap(
1442 phys_to_virt(ALIGN(dma_addr, 4)),
1443 pkt_len + 2);
1444 mdp->rx_skbuff[entry] = NULL;
1445 if (mdp->cd->rpadir)
1446 skb_reserve(skb, NET_IP_ALIGN);
1447 dma_unmap_single(&ndev->dev, dma_addr,
1448 ALIGN(mdp->rx_buf_sz, 32),
1449 DMA_FROM_DEVICE);
1450 skb_put(skb, pkt_len);
1451 skb->protocol = eth_type_trans(skb, ndev);
1452 netif_receive_skb(skb);
1453 ndev->stats.rx_packets++;
1454 ndev->stats.rx_bytes += pkt_len;
1455 if (desc_status & RD_RFS8)
1456 ndev->stats.multicast++;
1457 }
1458 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1459 rxdesc = &mdp->rx_ring[entry];
1460 }
1461
1462 /* Refill the Rx ring buffers. */
1463 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1464 entry = mdp->dirty_rx % mdp->num_rx_ring;
1465 rxdesc = &mdp->rx_ring[entry];
1466 /* The size of the buffer is 32 byte boundary. */
1467 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1468 rxdesc->len = cpu_to_le32(buf_len << 16);
1469
1470 if (mdp->rx_skbuff[entry] == NULL) {
1471 skb = netdev_alloc_skb(ndev, skbuff_size);
1472 if (skb == NULL)
1473 break; /* Better luck next round. */
1474 sh_eth_set_receive_align(skb);
1475 dma_addr = dma_map_single(&ndev->dev, skb->data,
1476 buf_len, DMA_FROM_DEVICE);
1477 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1478 kfree_skb(skb);
1479 break;
1480 }
1481 mdp->rx_skbuff[entry] = skb;
1482
1483 skb_checksum_none_assert(skb);
1484 rxdesc->addr = cpu_to_le32(dma_addr);
1485 }
1486 dma_wmb(); /* RACT bit must be set after all the above writes */
1487 if (entry >= mdp->num_rx_ring - 1)
1488 rxdesc->status |=
1489 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
1490 else
1491 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
1492 }
1493
1494 /* Restart Rx engine if stopped. */
1495 /* If we don't need to check status, don't. -KDU */
1496 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1497 /* fix the values for the next receiving if RDE is set */
1498 if (intr_status & EESR_RDE &&
1499 mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
1500 u32 count = (sh_eth_read(ndev, RDFAR) -
1501 sh_eth_read(ndev, RDLAR)) >> 4;
1502
1503 mdp->cur_rx = count;
1504 mdp->dirty_rx = count;
1505 }
1506 sh_eth_write(ndev, EDRRR_R, EDRRR);
1507 }
1508
1509 *quota -= limit - boguscnt - 1;
1510
1511 return *quota <= 0;
1512 }
1513
1514 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1515 {
1516 /* disable tx and rx */
1517 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1518 }
1519
1520 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1521 {
1522 /* enable tx and rx */
1523 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1524 }
1525
1526 /* E-MAC interrupt handler */
1527 static void sh_eth_emac_interrupt(struct net_device *ndev)
1528 {
1529 struct sh_eth_private *mdp = netdev_priv(ndev);
1530 u32 felic_stat;
1531 u32 link_stat;
1532
1533 felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR);
1534 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1535 if (felic_stat & ECSR_ICD)
1536 ndev->stats.tx_carrier_errors++;
1537 if (felic_stat & ECSR_LCHNG) {
1538 /* Link Changed */
1539 if (mdp->cd->no_psr || mdp->no_ether_link)
1540 return;
1541 link_stat = sh_eth_read(ndev, PSR);
1542 if (mdp->ether_link_active_low)
1543 link_stat = ~link_stat;
1544 if (!(link_stat & PHY_ST_LINK)) {
1545 sh_eth_rcv_snd_disable(ndev);
1546 } else {
1547 /* Link Up */
1548 sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, 0);
1549 /* clear int */
1550 sh_eth_modify(ndev, ECSR, 0, 0);
1551 sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, DMAC_M_ECI);
1552 /* enable tx and rx */
1553 sh_eth_rcv_snd_enable(ndev);
1554 }
1555 }
1556 }
1557
1558 /* error control function */
1559 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1560 {
1561 struct sh_eth_private *mdp = netdev_priv(ndev);
1562 u32 mask;
1563
1564 if (intr_status & EESR_TWB) {
1565 /* Unused write back interrupt */
1566 if (intr_status & EESR_TABT) { /* Transmit Abort int */
1567 ndev->stats.tx_aborted_errors++;
1568 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1569 }
1570 }
1571
1572 if (intr_status & EESR_RABT) {
1573 /* Receive Abort int */
1574 if (intr_status & EESR_RFRMER) {
1575 /* Receive Frame Overflow int */
1576 ndev->stats.rx_frame_errors++;
1577 }
1578 }
1579
1580 if (intr_status & EESR_TDE) {
1581 /* Transmit Descriptor Empty int */
1582 ndev->stats.tx_fifo_errors++;
1583 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1584 }
1585
1586 if (intr_status & EESR_TFE) {
1587 /* FIFO under flow */
1588 ndev->stats.tx_fifo_errors++;
1589 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1590 }
1591
1592 if (intr_status & EESR_RDE) {
1593 /* Receive Descriptor Empty int */
1594 ndev->stats.rx_over_errors++;
1595 }
1596
1597 if (intr_status & EESR_RFE) {
1598 /* Receive FIFO Overflow int */
1599 ndev->stats.rx_fifo_errors++;
1600 }
1601
1602 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1603 /* Address Error */
1604 ndev->stats.tx_fifo_errors++;
1605 netif_err(mdp, tx_err, ndev, "Address Error\n");
1606 }
1607
1608 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1609 if (mdp->cd->no_ade)
1610 mask &= ~EESR_ADE;
1611 if (intr_status & mask) {
1612 /* Tx error */
1613 u32 edtrr = sh_eth_read(ndev, EDTRR);
1614
1615 /* dmesg */
1616 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1617 intr_status, mdp->cur_tx, mdp->dirty_tx,
1618 (u32)ndev->state, edtrr);
1619 /* dirty buffer free */
1620 sh_eth_txfree(ndev);
1621
1622 /* SH7712 BUG */
1623 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1624 /* tx dma start */
1625 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1626 }
1627 /* wakeup */
1628 netif_wake_queue(ndev);
1629 }
1630 }
1631
1632 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1633 {
1634 struct net_device *ndev = netdev;
1635 struct sh_eth_private *mdp = netdev_priv(ndev);
1636 struct sh_eth_cpu_data *cd = mdp->cd;
1637 irqreturn_t ret = IRQ_NONE;
1638 u32 intr_status, intr_enable;
1639
1640 spin_lock(&mdp->lock);
1641
1642 /* Get interrupt status */
1643 intr_status = sh_eth_read(ndev, EESR);
1644 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1645 * enabled since it's the one that comes thru regardless of the mask,
1646 * and we need to fully handle it in sh_eth_emac_interrupt() in order
1647 * to quench it as it doesn't get cleared by just writing 1 to the ECI
1648 * bit...
1649 */
1650 intr_enable = sh_eth_read(ndev, EESIPR);
1651 intr_status &= intr_enable | DMAC_M_ECI;
1652 if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI |
1653 cd->eesr_err_check))
1654 ret = IRQ_HANDLED;
1655 else
1656 goto out;
1657
1658 if (unlikely(!mdp->irq_enabled)) {
1659 sh_eth_write(ndev, 0, EESIPR);
1660 goto out;
1661 }
1662
1663 if (intr_status & EESR_RX_CHECK) {
1664 if (napi_schedule_prep(&mdp->napi)) {
1665 /* Mask Rx interrupts */
1666 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1667 EESIPR);
1668 __napi_schedule(&mdp->napi);
1669 } else {
1670 netdev_warn(ndev,
1671 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1672 intr_status, intr_enable);
1673 }
1674 }
1675
1676 /* Tx Check */
1677 if (intr_status & cd->tx_check) {
1678 /* Clear Tx interrupts */
1679 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1680
1681 sh_eth_txfree(ndev);
1682 netif_wake_queue(ndev);
1683 }
1684
1685 /* E-MAC interrupt */
1686 if (intr_status & EESR_ECI)
1687 sh_eth_emac_interrupt(ndev);
1688
1689 if (intr_status & cd->eesr_err_check) {
1690 /* Clear error interrupts */
1691 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1692
1693 sh_eth_error(ndev, intr_status);
1694 }
1695
1696 out:
1697 spin_unlock(&mdp->lock);
1698
1699 return ret;
1700 }
1701
1702 static int sh_eth_poll(struct napi_struct *napi, int budget)
1703 {
1704 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1705 napi);
1706 struct net_device *ndev = napi->dev;
1707 int quota = budget;
1708 u32 intr_status;
1709
1710 for (;;) {
1711 intr_status = sh_eth_read(ndev, EESR);
1712 if (!(intr_status & EESR_RX_CHECK))
1713 break;
1714 /* Clear Rx interrupts */
1715 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1716
1717 if (sh_eth_rx(ndev, intr_status, &quota))
1718 goto out;
1719 }
1720
1721 napi_complete(napi);
1722
1723 /* Reenable Rx interrupts */
1724 if (mdp->irq_enabled)
1725 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1726 out:
1727 return budget - quota;
1728 }
1729
1730 /* PHY state control function */
1731 static void sh_eth_adjust_link(struct net_device *ndev)
1732 {
1733 struct sh_eth_private *mdp = netdev_priv(ndev);
1734 struct phy_device *phydev = ndev->phydev;
1735 int new_state = 0;
1736
1737 if (phydev->link) {
1738 if (phydev->duplex != mdp->duplex) {
1739 new_state = 1;
1740 mdp->duplex = phydev->duplex;
1741 if (mdp->cd->set_duplex)
1742 mdp->cd->set_duplex(ndev);
1743 }
1744
1745 if (phydev->speed != mdp->speed) {
1746 new_state = 1;
1747 mdp->speed = phydev->speed;
1748 if (mdp->cd->set_rate)
1749 mdp->cd->set_rate(ndev);
1750 }
1751 if (!mdp->link) {
1752 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
1753 new_state = 1;
1754 mdp->link = phydev->link;
1755 if (mdp->cd->no_psr || mdp->no_ether_link)
1756 sh_eth_rcv_snd_enable(ndev);
1757 }
1758 } else if (mdp->link) {
1759 new_state = 1;
1760 mdp->link = 0;
1761 mdp->speed = 0;
1762 mdp->duplex = -1;
1763 if (mdp->cd->no_psr || mdp->no_ether_link)
1764 sh_eth_rcv_snd_disable(ndev);
1765 }
1766
1767 if (new_state && netif_msg_link(mdp))
1768 phy_print_status(phydev);
1769 }
1770
1771 /* PHY init function */
1772 static int sh_eth_phy_init(struct net_device *ndev)
1773 {
1774 struct device_node *np = ndev->dev.parent->of_node;
1775 struct sh_eth_private *mdp = netdev_priv(ndev);
1776 struct phy_device *phydev;
1777
1778 mdp->link = 0;
1779 mdp->speed = 0;
1780 mdp->duplex = -1;
1781
1782 /* Try connect to PHY */
1783 if (np) {
1784 struct device_node *pn;
1785
1786 pn = of_parse_phandle(np, "phy-handle", 0);
1787 phydev = of_phy_connect(ndev, pn,
1788 sh_eth_adjust_link, 0,
1789 mdp->phy_interface);
1790
1791 of_node_put(pn);
1792 if (!phydev)
1793 phydev = ERR_PTR(-ENOENT);
1794 } else {
1795 char phy_id[MII_BUS_ID_SIZE + 3];
1796
1797 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1798 mdp->mii_bus->id, mdp->phy_id);
1799
1800 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1801 mdp->phy_interface);
1802 }
1803
1804 if (IS_ERR(phydev)) {
1805 netdev_err(ndev, "failed to connect PHY\n");
1806 return PTR_ERR(phydev);
1807 }
1808
1809 phy_attached_info(phydev);
1810
1811 return 0;
1812 }
1813
1814 /* PHY control start function */
1815 static int sh_eth_phy_start(struct net_device *ndev)
1816 {
1817 int ret;
1818
1819 ret = sh_eth_phy_init(ndev);
1820 if (ret)
1821 return ret;
1822
1823 phy_start(ndev->phydev);
1824
1825 return 0;
1826 }
1827
1828 static int sh_eth_get_link_ksettings(struct net_device *ndev,
1829 struct ethtool_link_ksettings *cmd)
1830 {
1831 struct sh_eth_private *mdp = netdev_priv(ndev);
1832 unsigned long flags;
1833 int ret;
1834
1835 if (!ndev->phydev)
1836 return -ENODEV;
1837
1838 spin_lock_irqsave(&mdp->lock, flags);
1839 ret = phy_ethtool_ksettings_get(ndev->phydev, cmd);
1840 spin_unlock_irqrestore(&mdp->lock, flags);
1841
1842 return ret;
1843 }
1844
1845 static int sh_eth_set_link_ksettings(struct net_device *ndev,
1846 const struct ethtool_link_ksettings *cmd)
1847 {
1848 struct sh_eth_private *mdp = netdev_priv(ndev);
1849 unsigned long flags;
1850 int ret;
1851
1852 if (!ndev->phydev)
1853 return -ENODEV;
1854
1855 spin_lock_irqsave(&mdp->lock, flags);
1856
1857 /* disable tx and rx */
1858 sh_eth_rcv_snd_disable(ndev);
1859
1860 ret = phy_ethtool_ksettings_set(ndev->phydev, cmd);
1861 if (ret)
1862 goto error_exit;
1863
1864 if (cmd->base.duplex == DUPLEX_FULL)
1865 mdp->duplex = 1;
1866 else
1867 mdp->duplex = 0;
1868
1869 if (mdp->cd->set_duplex)
1870 mdp->cd->set_duplex(ndev);
1871
1872 error_exit:
1873 mdelay(1);
1874
1875 /* enable tx and rx */
1876 sh_eth_rcv_snd_enable(ndev);
1877
1878 spin_unlock_irqrestore(&mdp->lock, flags);
1879
1880 return ret;
1881 }
1882
1883 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1884 * version must be bumped as well. Just adding registers up to that
1885 * limit is fine, as long as the existing register indices don't
1886 * change.
1887 */
1888 #define SH_ETH_REG_DUMP_VERSION 1
1889 #define SH_ETH_REG_DUMP_MAX_REGS 256
1890
1891 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1892 {
1893 struct sh_eth_private *mdp = netdev_priv(ndev);
1894 struct sh_eth_cpu_data *cd = mdp->cd;
1895 u32 *valid_map;
1896 size_t len;
1897
1898 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1899
1900 /* Dump starts with a bitmap that tells ethtool which
1901 * registers are defined for this chip.
1902 */
1903 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1904 if (buf) {
1905 valid_map = buf;
1906 buf += len;
1907 } else {
1908 valid_map = NULL;
1909 }
1910
1911 /* Add a register to the dump, if it has a defined offset.
1912 * This automatically skips most undefined registers, but for
1913 * some it is also necessary to check a capability flag in
1914 * struct sh_eth_cpu_data.
1915 */
1916 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1917 #define add_reg_from(reg, read_expr) do { \
1918 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
1919 if (buf) { \
1920 mark_reg_valid(reg); \
1921 *buf++ = read_expr; \
1922 } \
1923 ++len; \
1924 } \
1925 } while (0)
1926 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
1927 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
1928
1929 add_reg(EDSR);
1930 add_reg(EDMR);
1931 add_reg(EDTRR);
1932 add_reg(EDRRR);
1933 add_reg(EESR);
1934 add_reg(EESIPR);
1935 add_reg(TDLAR);
1936 add_reg(TDFAR);
1937 add_reg(TDFXR);
1938 add_reg(TDFFR);
1939 add_reg(RDLAR);
1940 add_reg(RDFAR);
1941 add_reg(RDFXR);
1942 add_reg(RDFFR);
1943 add_reg(TRSCER);
1944 add_reg(RMFCR);
1945 add_reg(TFTR);
1946 add_reg(FDR);
1947 add_reg(RMCR);
1948 add_reg(TFUCR);
1949 add_reg(RFOCR);
1950 if (cd->rmiimode)
1951 add_reg(RMIIMODE);
1952 add_reg(FCFTR);
1953 if (cd->rpadir)
1954 add_reg(RPADIR);
1955 if (!cd->no_trimd)
1956 add_reg(TRIMD);
1957 add_reg(ECMR);
1958 add_reg(ECSR);
1959 add_reg(ECSIPR);
1960 add_reg(PIR);
1961 if (!cd->no_psr)
1962 add_reg(PSR);
1963 add_reg(RDMLR);
1964 add_reg(RFLR);
1965 add_reg(IPGR);
1966 if (cd->apr)
1967 add_reg(APR);
1968 if (cd->mpr)
1969 add_reg(MPR);
1970 add_reg(RFCR);
1971 add_reg(RFCF);
1972 if (cd->tpauser)
1973 add_reg(TPAUSER);
1974 add_reg(TPAUSECR);
1975 add_reg(GECMR);
1976 if (cd->bculr)
1977 add_reg(BCULR);
1978 add_reg(MAHR);
1979 add_reg(MALR);
1980 add_reg(TROCR);
1981 add_reg(CDCR);
1982 add_reg(LCCR);
1983 add_reg(CNDCR);
1984 add_reg(CEFCR);
1985 add_reg(FRECR);
1986 add_reg(TSFRCR);
1987 add_reg(TLFRCR);
1988 add_reg(CERCR);
1989 add_reg(CEECR);
1990 add_reg(MAFCR);
1991 if (cd->rtrate)
1992 add_reg(RTRATE);
1993 if (cd->hw_crc)
1994 add_reg(CSMR);
1995 if (cd->select_mii)
1996 add_reg(RMII_MII);
1997 add_reg(ARSTR);
1998 if (cd->tsu) {
1999 add_tsu_reg(TSU_CTRST);
2000 add_tsu_reg(TSU_FWEN0);
2001 add_tsu_reg(TSU_FWEN1);
2002 add_tsu_reg(TSU_FCM);
2003 add_tsu_reg(TSU_BSYSL0);
2004 add_tsu_reg(TSU_BSYSL1);
2005 add_tsu_reg(TSU_PRISL0);
2006 add_tsu_reg(TSU_PRISL1);
2007 add_tsu_reg(TSU_FWSL0);
2008 add_tsu_reg(TSU_FWSL1);
2009 add_tsu_reg(TSU_FWSLC);
2010 add_tsu_reg(TSU_QTAG0);
2011 add_tsu_reg(TSU_QTAG1);
2012 add_tsu_reg(TSU_QTAGM0);
2013 add_tsu_reg(TSU_QTAGM1);
2014 add_tsu_reg(TSU_FWSR);
2015 add_tsu_reg(TSU_FWINMK);
2016 add_tsu_reg(TSU_ADQT0);
2017 add_tsu_reg(TSU_ADQT1);
2018 add_tsu_reg(TSU_VTAG0);
2019 add_tsu_reg(TSU_VTAG1);
2020 add_tsu_reg(TSU_ADSBSY);
2021 add_tsu_reg(TSU_TEN);
2022 add_tsu_reg(TSU_POST1);
2023 add_tsu_reg(TSU_POST2);
2024 add_tsu_reg(TSU_POST3);
2025 add_tsu_reg(TSU_POST4);
2026 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2027 /* This is the start of a table, not just a single
2028 * register.
2029 */
2030 if (buf) {
2031 unsigned int i;
2032
2033 mark_reg_valid(TSU_ADRH0);
2034 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2035 *buf++ = ioread32(
2036 mdp->tsu_addr +
2037 mdp->reg_offset[TSU_ADRH0] +
2038 i * 4);
2039 }
2040 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2041 }
2042 }
2043
2044 #undef mark_reg_valid
2045 #undef add_reg_from
2046 #undef add_reg
2047 #undef add_tsu_reg
2048
2049 return len * 4;
2050 }
2051
2052 static int sh_eth_get_regs_len(struct net_device *ndev)
2053 {
2054 return __sh_eth_get_regs(ndev, NULL);
2055 }
2056
2057 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2058 void *buf)
2059 {
2060 struct sh_eth_private *mdp = netdev_priv(ndev);
2061
2062 regs->version = SH_ETH_REG_DUMP_VERSION;
2063
2064 pm_runtime_get_sync(&mdp->pdev->dev);
2065 __sh_eth_get_regs(ndev, buf);
2066 pm_runtime_put_sync(&mdp->pdev->dev);
2067 }
2068
2069 static int sh_eth_nway_reset(struct net_device *ndev)
2070 {
2071 struct sh_eth_private *mdp = netdev_priv(ndev);
2072 unsigned long flags;
2073 int ret;
2074
2075 if (!ndev->phydev)
2076 return -ENODEV;
2077
2078 spin_lock_irqsave(&mdp->lock, flags);
2079 ret = phy_start_aneg(ndev->phydev);
2080 spin_unlock_irqrestore(&mdp->lock, flags);
2081
2082 return ret;
2083 }
2084
2085 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2086 {
2087 struct sh_eth_private *mdp = netdev_priv(ndev);
2088 return mdp->msg_enable;
2089 }
2090
2091 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2092 {
2093 struct sh_eth_private *mdp = netdev_priv(ndev);
2094 mdp->msg_enable = value;
2095 }
2096
2097 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2098 "rx_current", "tx_current",
2099 "rx_dirty", "tx_dirty",
2100 };
2101 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2102
2103 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2104 {
2105 switch (sset) {
2106 case ETH_SS_STATS:
2107 return SH_ETH_STATS_LEN;
2108 default:
2109 return -EOPNOTSUPP;
2110 }
2111 }
2112
2113 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2114 struct ethtool_stats *stats, u64 *data)
2115 {
2116 struct sh_eth_private *mdp = netdev_priv(ndev);
2117 int i = 0;
2118
2119 /* device-specific stats */
2120 data[i++] = mdp->cur_rx;
2121 data[i++] = mdp->cur_tx;
2122 data[i++] = mdp->dirty_rx;
2123 data[i++] = mdp->dirty_tx;
2124 }
2125
2126 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2127 {
2128 switch (stringset) {
2129 case ETH_SS_STATS:
2130 memcpy(data, *sh_eth_gstrings_stats,
2131 sizeof(sh_eth_gstrings_stats));
2132 break;
2133 }
2134 }
2135
2136 static void sh_eth_get_ringparam(struct net_device *ndev,
2137 struct ethtool_ringparam *ring)
2138 {
2139 struct sh_eth_private *mdp = netdev_priv(ndev);
2140
2141 ring->rx_max_pending = RX_RING_MAX;
2142 ring->tx_max_pending = TX_RING_MAX;
2143 ring->rx_pending = mdp->num_rx_ring;
2144 ring->tx_pending = mdp->num_tx_ring;
2145 }
2146
2147 static int sh_eth_set_ringparam(struct net_device *ndev,
2148 struct ethtool_ringparam *ring)
2149 {
2150 struct sh_eth_private *mdp = netdev_priv(ndev);
2151 int ret;
2152
2153 if (ring->tx_pending > TX_RING_MAX ||
2154 ring->rx_pending > RX_RING_MAX ||
2155 ring->tx_pending < TX_RING_MIN ||
2156 ring->rx_pending < RX_RING_MIN)
2157 return -EINVAL;
2158 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2159 return -EINVAL;
2160
2161 if (netif_running(ndev)) {
2162 netif_device_detach(ndev);
2163 netif_tx_disable(ndev);
2164
2165 /* Serialise with the interrupt handler and NAPI, then
2166 * disable interrupts. We have to clear the
2167 * irq_enabled flag first to ensure that interrupts
2168 * won't be re-enabled.
2169 */
2170 mdp->irq_enabled = false;
2171 synchronize_irq(ndev->irq);
2172 napi_synchronize(&mdp->napi);
2173 sh_eth_write(ndev, 0x0000, EESIPR);
2174
2175 sh_eth_dev_exit(ndev);
2176
2177 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2178 sh_eth_ring_free(ndev);
2179 }
2180
2181 /* Set new parameters */
2182 mdp->num_rx_ring = ring->rx_pending;
2183 mdp->num_tx_ring = ring->tx_pending;
2184
2185 if (netif_running(ndev)) {
2186 ret = sh_eth_ring_init(ndev);
2187 if (ret < 0) {
2188 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2189 __func__);
2190 return ret;
2191 }
2192 ret = sh_eth_dev_init(ndev);
2193 if (ret < 0) {
2194 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2195 __func__);
2196 return ret;
2197 }
2198
2199 netif_device_attach(ndev);
2200 }
2201
2202 return 0;
2203 }
2204
2205 static const struct ethtool_ops sh_eth_ethtool_ops = {
2206 .get_regs_len = sh_eth_get_regs_len,
2207 .get_regs = sh_eth_get_regs,
2208 .nway_reset = sh_eth_nway_reset,
2209 .get_msglevel = sh_eth_get_msglevel,
2210 .set_msglevel = sh_eth_set_msglevel,
2211 .get_link = ethtool_op_get_link,
2212 .get_strings = sh_eth_get_strings,
2213 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2214 .get_sset_count = sh_eth_get_sset_count,
2215 .get_ringparam = sh_eth_get_ringparam,
2216 .set_ringparam = sh_eth_set_ringparam,
2217 .get_link_ksettings = sh_eth_get_link_ksettings,
2218 .set_link_ksettings = sh_eth_set_link_ksettings,
2219 };
2220
2221 /* network device open function */
2222 static int sh_eth_open(struct net_device *ndev)
2223 {
2224 struct sh_eth_private *mdp = netdev_priv(ndev);
2225 int ret;
2226
2227 pm_runtime_get_sync(&mdp->pdev->dev);
2228
2229 napi_enable(&mdp->napi);
2230
2231 ret = request_irq(ndev->irq, sh_eth_interrupt,
2232 mdp->cd->irq_flags, ndev->name, ndev);
2233 if (ret) {
2234 netdev_err(ndev, "Can not assign IRQ number\n");
2235 goto out_napi_off;
2236 }
2237
2238 /* Descriptor set */
2239 ret = sh_eth_ring_init(ndev);
2240 if (ret)
2241 goto out_free_irq;
2242
2243 /* device init */
2244 ret = sh_eth_dev_init(ndev);
2245 if (ret)
2246 goto out_free_irq;
2247
2248 /* PHY control start*/
2249 ret = sh_eth_phy_start(ndev);
2250 if (ret)
2251 goto out_free_irq;
2252
2253 netif_start_queue(ndev);
2254
2255 mdp->is_opened = 1;
2256
2257 return ret;
2258
2259 out_free_irq:
2260 free_irq(ndev->irq, ndev);
2261 out_napi_off:
2262 napi_disable(&mdp->napi);
2263 pm_runtime_put_sync(&mdp->pdev->dev);
2264 return ret;
2265 }
2266
2267 /* Timeout function */
2268 static void sh_eth_tx_timeout(struct net_device *ndev)
2269 {
2270 struct sh_eth_private *mdp = netdev_priv(ndev);
2271 struct sh_eth_rxdesc *rxdesc;
2272 int i;
2273
2274 netif_stop_queue(ndev);
2275
2276 netif_err(mdp, timer, ndev,
2277 "transmit timed out, status %8.8x, resetting...\n",
2278 sh_eth_read(ndev, EESR));
2279
2280 /* tx_errors count up */
2281 ndev->stats.tx_errors++;
2282
2283 /* Free all the skbuffs in the Rx queue. */
2284 for (i = 0; i < mdp->num_rx_ring; i++) {
2285 rxdesc = &mdp->rx_ring[i];
2286 rxdesc->status = cpu_to_le32(0);
2287 rxdesc->addr = cpu_to_le32(0xBADF00D0);
2288 dev_kfree_skb(mdp->rx_skbuff[i]);
2289 mdp->rx_skbuff[i] = NULL;
2290 }
2291 for (i = 0; i < mdp->num_tx_ring; i++) {
2292 dev_kfree_skb(mdp->tx_skbuff[i]);
2293 mdp->tx_skbuff[i] = NULL;
2294 }
2295
2296 /* device init */
2297 sh_eth_dev_init(ndev);
2298
2299 netif_start_queue(ndev);
2300 }
2301
2302 /* Packet transmit function */
2303 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2304 {
2305 struct sh_eth_private *mdp = netdev_priv(ndev);
2306 struct sh_eth_txdesc *txdesc;
2307 dma_addr_t dma_addr;
2308 u32 entry;
2309 unsigned long flags;
2310
2311 spin_lock_irqsave(&mdp->lock, flags);
2312 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2313 if (!sh_eth_txfree(ndev)) {
2314 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2315 netif_stop_queue(ndev);
2316 spin_unlock_irqrestore(&mdp->lock, flags);
2317 return NETDEV_TX_BUSY;
2318 }
2319 }
2320 spin_unlock_irqrestore(&mdp->lock, flags);
2321
2322 if (skb_put_padto(skb, ETH_ZLEN))
2323 return NETDEV_TX_OK;
2324
2325 entry = mdp->cur_tx % mdp->num_tx_ring;
2326 mdp->tx_skbuff[entry] = skb;
2327 txdesc = &mdp->tx_ring[entry];
2328 /* soft swap. */
2329 if (!mdp->cd->hw_swap)
2330 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2331 dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2332 DMA_TO_DEVICE);
2333 if (dma_mapping_error(&ndev->dev, dma_addr)) {
2334 kfree_skb(skb);
2335 return NETDEV_TX_OK;
2336 }
2337 txdesc->addr = cpu_to_le32(dma_addr);
2338 txdesc->len = cpu_to_le32(skb->len << 16);
2339
2340 dma_wmb(); /* TACT bit must be set after all the above writes */
2341 if (entry >= mdp->num_tx_ring - 1)
2342 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
2343 else
2344 txdesc->status |= cpu_to_le32(TD_TACT);
2345
2346 mdp->cur_tx++;
2347
2348 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2349 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2350
2351 return NETDEV_TX_OK;
2352 }
2353
2354 /* The statistics registers have write-clear behaviour, which means we
2355 * will lose any increment between the read and write. We mitigate
2356 * this by only clearing when we read a non-zero value, so we will
2357 * never falsely report a total of zero.
2358 */
2359 static void
2360 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2361 {
2362 u32 delta = sh_eth_read(ndev, reg);
2363
2364 if (delta) {
2365 *stat += delta;
2366 sh_eth_write(ndev, 0, reg);
2367 }
2368 }
2369
2370 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2371 {
2372 struct sh_eth_private *mdp = netdev_priv(ndev);
2373
2374 if (sh_eth_is_rz_fast_ether(mdp))
2375 return &ndev->stats;
2376
2377 if (!mdp->is_opened)
2378 return &ndev->stats;
2379
2380 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2381 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2382 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2383
2384 if (sh_eth_is_gether(mdp)) {
2385 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2386 CERCR);
2387 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2388 CEECR);
2389 } else {
2390 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2391 CNDCR);
2392 }
2393
2394 return &ndev->stats;
2395 }
2396
2397 /* device close function */
2398 static int sh_eth_close(struct net_device *ndev)
2399 {
2400 struct sh_eth_private *mdp = netdev_priv(ndev);
2401
2402 netif_stop_queue(ndev);
2403
2404 /* Serialise with the interrupt handler and NAPI, then disable
2405 * interrupts. We have to clear the irq_enabled flag first to
2406 * ensure that interrupts won't be re-enabled.
2407 */
2408 mdp->irq_enabled = false;
2409 synchronize_irq(ndev->irq);
2410 napi_disable(&mdp->napi);
2411 sh_eth_write(ndev, 0x0000, EESIPR);
2412
2413 sh_eth_dev_exit(ndev);
2414
2415 /* PHY Disconnect */
2416 if (ndev->phydev) {
2417 phy_stop(ndev->phydev);
2418 phy_disconnect(ndev->phydev);
2419 }
2420
2421 free_irq(ndev->irq, ndev);
2422
2423 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2424 sh_eth_ring_free(ndev);
2425
2426 pm_runtime_put_sync(&mdp->pdev->dev);
2427
2428 mdp->is_opened = 0;
2429
2430 return 0;
2431 }
2432
2433 /* ioctl to device function */
2434 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2435 {
2436 struct phy_device *phydev = ndev->phydev;
2437
2438 if (!netif_running(ndev))
2439 return -EINVAL;
2440
2441 if (!phydev)
2442 return -ENODEV;
2443
2444 return phy_mii_ioctl(phydev, rq, cmd);
2445 }
2446
2447 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2448 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2449 int entry)
2450 {
2451 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2452 }
2453
2454 static u32 sh_eth_tsu_get_post_mask(int entry)
2455 {
2456 return 0x0f << (28 - ((entry % 8) * 4));
2457 }
2458
2459 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2460 {
2461 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2462 }
2463
2464 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2465 int entry)
2466 {
2467 struct sh_eth_private *mdp = netdev_priv(ndev);
2468 u32 tmp;
2469 void *reg_offset;
2470
2471 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2472 tmp = ioread32(reg_offset);
2473 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2474 }
2475
2476 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2477 int entry)
2478 {
2479 struct sh_eth_private *mdp = netdev_priv(ndev);
2480 u32 post_mask, ref_mask, tmp;
2481 void *reg_offset;
2482
2483 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2484 post_mask = sh_eth_tsu_get_post_mask(entry);
2485 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2486
2487 tmp = ioread32(reg_offset);
2488 iowrite32(tmp & ~post_mask, reg_offset);
2489
2490 /* If other port enables, the function returns "true" */
2491 return tmp & ref_mask;
2492 }
2493
2494 static int sh_eth_tsu_busy(struct net_device *ndev)
2495 {
2496 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2497 struct sh_eth_private *mdp = netdev_priv(ndev);
2498
2499 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2500 udelay(10);
2501 timeout--;
2502 if (timeout <= 0) {
2503 netdev_err(ndev, "%s: timeout\n", __func__);
2504 return -ETIMEDOUT;
2505 }
2506 }
2507
2508 return 0;
2509 }
2510
2511 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2512 const u8 *addr)
2513 {
2514 u32 val;
2515
2516 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2517 iowrite32(val, reg);
2518 if (sh_eth_tsu_busy(ndev) < 0)
2519 return -EBUSY;
2520
2521 val = addr[4] << 8 | addr[5];
2522 iowrite32(val, reg + 4);
2523 if (sh_eth_tsu_busy(ndev) < 0)
2524 return -EBUSY;
2525
2526 return 0;
2527 }
2528
2529 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2530 {
2531 u32 val;
2532
2533 val = ioread32(reg);
2534 addr[0] = (val >> 24) & 0xff;
2535 addr[1] = (val >> 16) & 0xff;
2536 addr[2] = (val >> 8) & 0xff;
2537 addr[3] = val & 0xff;
2538 val = ioread32(reg + 4);
2539 addr[4] = (val >> 8) & 0xff;
2540 addr[5] = val & 0xff;
2541 }
2542
2543
2544 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2545 {
2546 struct sh_eth_private *mdp = netdev_priv(ndev);
2547 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2548 int i;
2549 u8 c_addr[ETH_ALEN];
2550
2551 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2552 sh_eth_tsu_read_entry(reg_offset, c_addr);
2553 if (ether_addr_equal(addr, c_addr))
2554 return i;
2555 }
2556
2557 return -ENOENT;
2558 }
2559
2560 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2561 {
2562 u8 blank[ETH_ALEN];
2563 int entry;
2564
2565 memset(blank, 0, sizeof(blank));
2566 entry = sh_eth_tsu_find_entry(ndev, blank);
2567 return (entry < 0) ? -ENOMEM : entry;
2568 }
2569
2570 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2571 int entry)
2572 {
2573 struct sh_eth_private *mdp = netdev_priv(ndev);
2574 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2575 int ret;
2576 u8 blank[ETH_ALEN];
2577
2578 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2579 ~(1 << (31 - entry)), TSU_TEN);
2580
2581 memset(blank, 0, sizeof(blank));
2582 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2583 if (ret < 0)
2584 return ret;
2585 return 0;
2586 }
2587
2588 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2589 {
2590 struct sh_eth_private *mdp = netdev_priv(ndev);
2591 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2592 int i, ret;
2593
2594 if (!mdp->cd->tsu)
2595 return 0;
2596
2597 i = sh_eth_tsu_find_entry(ndev, addr);
2598 if (i < 0) {
2599 /* No entry found, create one */
2600 i = sh_eth_tsu_find_empty(ndev);
2601 if (i < 0)
2602 return -ENOMEM;
2603 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2604 if (ret < 0)
2605 return ret;
2606
2607 /* Enable the entry */
2608 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2609 (1 << (31 - i)), TSU_TEN);
2610 }
2611
2612 /* Entry found or created, enable POST */
2613 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2614
2615 return 0;
2616 }
2617
2618 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2619 {
2620 struct sh_eth_private *mdp = netdev_priv(ndev);
2621 int i, ret;
2622
2623 if (!mdp->cd->tsu)
2624 return 0;
2625
2626 i = sh_eth_tsu_find_entry(ndev, addr);
2627 if (i) {
2628 /* Entry found */
2629 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2630 goto done;
2631
2632 /* Disable the entry if both ports was disabled */
2633 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2634 if (ret < 0)
2635 return ret;
2636 }
2637 done:
2638 return 0;
2639 }
2640
2641 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2642 {
2643 struct sh_eth_private *mdp = netdev_priv(ndev);
2644 int i, ret;
2645
2646 if (!mdp->cd->tsu)
2647 return 0;
2648
2649 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2650 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2651 continue;
2652
2653 /* Disable the entry if both ports was disabled */
2654 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2655 if (ret < 0)
2656 return ret;
2657 }
2658
2659 return 0;
2660 }
2661
2662 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2663 {
2664 struct sh_eth_private *mdp = netdev_priv(ndev);
2665 u8 addr[ETH_ALEN];
2666 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2667 int i;
2668
2669 if (!mdp->cd->tsu)
2670 return;
2671
2672 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2673 sh_eth_tsu_read_entry(reg_offset, addr);
2674 if (is_multicast_ether_addr(addr))
2675 sh_eth_tsu_del_entry(ndev, addr);
2676 }
2677 }
2678
2679 /* Update promiscuous flag and multicast filter */
2680 static void sh_eth_set_rx_mode(struct net_device *ndev)
2681 {
2682 struct sh_eth_private *mdp = netdev_priv(ndev);
2683 u32 ecmr_bits;
2684 int mcast_all = 0;
2685 unsigned long flags;
2686
2687 spin_lock_irqsave(&mdp->lock, flags);
2688 /* Initial condition is MCT = 1, PRM = 0.
2689 * Depending on ndev->flags, set PRM or clear MCT
2690 */
2691 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2692 if (mdp->cd->tsu)
2693 ecmr_bits |= ECMR_MCT;
2694
2695 if (!(ndev->flags & IFF_MULTICAST)) {
2696 sh_eth_tsu_purge_mcast(ndev);
2697 mcast_all = 1;
2698 }
2699 if (ndev->flags & IFF_ALLMULTI) {
2700 sh_eth_tsu_purge_mcast(ndev);
2701 ecmr_bits &= ~ECMR_MCT;
2702 mcast_all = 1;
2703 }
2704
2705 if (ndev->flags & IFF_PROMISC) {
2706 sh_eth_tsu_purge_all(ndev);
2707 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2708 } else if (mdp->cd->tsu) {
2709 struct netdev_hw_addr *ha;
2710 netdev_for_each_mc_addr(ha, ndev) {
2711 if (mcast_all && is_multicast_ether_addr(ha->addr))
2712 continue;
2713
2714 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2715 if (!mcast_all) {
2716 sh_eth_tsu_purge_mcast(ndev);
2717 ecmr_bits &= ~ECMR_MCT;
2718 mcast_all = 1;
2719 }
2720 }
2721 }
2722 }
2723
2724 /* update the ethernet mode */
2725 sh_eth_write(ndev, ecmr_bits, ECMR);
2726
2727 spin_unlock_irqrestore(&mdp->lock, flags);
2728 }
2729
2730 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2731 {
2732 if (!mdp->port)
2733 return TSU_VTAG0;
2734 else
2735 return TSU_VTAG1;
2736 }
2737
2738 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2739 __be16 proto, u16 vid)
2740 {
2741 struct sh_eth_private *mdp = netdev_priv(ndev);
2742 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2743
2744 if (unlikely(!mdp->cd->tsu))
2745 return -EPERM;
2746
2747 /* No filtering if vid = 0 */
2748 if (!vid)
2749 return 0;
2750
2751 mdp->vlan_num_ids++;
2752
2753 /* The controller has one VLAN tag HW filter. So, if the filter is
2754 * already enabled, the driver disables it and the filte
2755 */
2756 if (mdp->vlan_num_ids > 1) {
2757 /* disable VLAN filter */
2758 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2759 return 0;
2760 }
2761
2762 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2763 vtag_reg_index);
2764
2765 return 0;
2766 }
2767
2768 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2769 __be16 proto, u16 vid)
2770 {
2771 struct sh_eth_private *mdp = netdev_priv(ndev);
2772 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2773
2774 if (unlikely(!mdp->cd->tsu))
2775 return -EPERM;
2776
2777 /* No filtering if vid = 0 */
2778 if (!vid)
2779 return 0;
2780
2781 mdp->vlan_num_ids--;
2782 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2783
2784 return 0;
2785 }
2786
2787 /* SuperH's TSU register init function */
2788 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2789 {
2790 if (sh_eth_is_rz_fast_ether(mdp)) {
2791 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2792 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
2793 TSU_FWSLC); /* Enable POST registers */
2794 return;
2795 }
2796
2797 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2798 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2799 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2800 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2801 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2802 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2803 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2804 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2805 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2806 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2807 if (sh_eth_is_gether(mdp)) {
2808 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2809 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2810 } else {
2811 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2812 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2813 }
2814 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2815 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2816 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2817 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2818 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2819 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2820 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
2821 }
2822
2823 /* MDIO bus release function */
2824 static int sh_mdio_release(struct sh_eth_private *mdp)
2825 {
2826 /* unregister mdio bus */
2827 mdiobus_unregister(mdp->mii_bus);
2828
2829 /* free bitbang info */
2830 free_mdio_bitbang(mdp->mii_bus);
2831
2832 return 0;
2833 }
2834
2835 /* MDIO bus init function */
2836 static int sh_mdio_init(struct sh_eth_private *mdp,
2837 struct sh_eth_plat_data *pd)
2838 {
2839 int ret;
2840 struct bb_info *bitbang;
2841 struct platform_device *pdev = mdp->pdev;
2842 struct device *dev = &mdp->pdev->dev;
2843
2844 /* create bit control struct for PHY */
2845 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2846 if (!bitbang)
2847 return -ENOMEM;
2848
2849 /* bitbang init */
2850 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2851 bitbang->set_gate = pd->set_mdio_gate;
2852 bitbang->ctrl.ops = &bb_ops;
2853
2854 /* MII controller setting */
2855 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2856 if (!mdp->mii_bus)
2857 return -ENOMEM;
2858
2859 /* Hook up MII support for ethtool */
2860 mdp->mii_bus->name = "sh_mii";
2861 mdp->mii_bus->parent = dev;
2862 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2863 pdev->name, pdev->id);
2864
2865 /* register MDIO bus */
2866 if (dev->of_node) {
2867 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
2868 } else {
2869 if (pd->phy_irq > 0)
2870 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2871
2872 ret = mdiobus_register(mdp->mii_bus);
2873 }
2874
2875 if (ret)
2876 goto out_free_bus;
2877
2878 return 0;
2879
2880 out_free_bus:
2881 free_mdio_bitbang(mdp->mii_bus);
2882 return ret;
2883 }
2884
2885 static const u16 *sh_eth_get_register_offset(int register_type)
2886 {
2887 const u16 *reg_offset = NULL;
2888
2889 switch (register_type) {
2890 case SH_ETH_REG_GIGABIT:
2891 reg_offset = sh_eth_offset_gigabit;
2892 break;
2893 case SH_ETH_REG_FAST_RZ:
2894 reg_offset = sh_eth_offset_fast_rz;
2895 break;
2896 case SH_ETH_REG_FAST_RCAR:
2897 reg_offset = sh_eth_offset_fast_rcar;
2898 break;
2899 case SH_ETH_REG_FAST_SH4:
2900 reg_offset = sh_eth_offset_fast_sh4;
2901 break;
2902 case SH_ETH_REG_FAST_SH3_SH2:
2903 reg_offset = sh_eth_offset_fast_sh3_sh2;
2904 break;
2905 }
2906
2907 return reg_offset;
2908 }
2909
2910 static const struct net_device_ops sh_eth_netdev_ops = {
2911 .ndo_open = sh_eth_open,
2912 .ndo_stop = sh_eth_close,
2913 .ndo_start_xmit = sh_eth_start_xmit,
2914 .ndo_get_stats = sh_eth_get_stats,
2915 .ndo_set_rx_mode = sh_eth_set_rx_mode,
2916 .ndo_tx_timeout = sh_eth_tx_timeout,
2917 .ndo_do_ioctl = sh_eth_do_ioctl,
2918 .ndo_validate_addr = eth_validate_addr,
2919 .ndo_set_mac_address = eth_mac_addr,
2920 };
2921
2922 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2923 .ndo_open = sh_eth_open,
2924 .ndo_stop = sh_eth_close,
2925 .ndo_start_xmit = sh_eth_start_xmit,
2926 .ndo_get_stats = sh_eth_get_stats,
2927 .ndo_set_rx_mode = sh_eth_set_rx_mode,
2928 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2929 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2930 .ndo_tx_timeout = sh_eth_tx_timeout,
2931 .ndo_do_ioctl = sh_eth_do_ioctl,
2932 .ndo_validate_addr = eth_validate_addr,
2933 .ndo_set_mac_address = eth_mac_addr,
2934 };
2935
2936 #ifdef CONFIG_OF
2937 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2938 {
2939 struct device_node *np = dev->of_node;
2940 struct sh_eth_plat_data *pdata;
2941 const char *mac_addr;
2942
2943 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2944 if (!pdata)
2945 return NULL;
2946
2947 pdata->phy_interface = of_get_phy_mode(np);
2948
2949 mac_addr = of_get_mac_address(np);
2950 if (mac_addr)
2951 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2952
2953 pdata->no_ether_link =
2954 of_property_read_bool(np, "renesas,no-ether-link");
2955 pdata->ether_link_active_low =
2956 of_property_read_bool(np, "renesas,ether-link-active-low");
2957
2958 return pdata;
2959 }
2960
2961 static const struct of_device_id sh_eth_match_table[] = {
2962 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
2963 { .compatible = "renesas,ether-r8a7743", .data = &r8a779x_data },
2964 { .compatible = "renesas,ether-r8a7745", .data = &r8a779x_data },
2965 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2966 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2967 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
2968 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
2969 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
2970 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
2971 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
2972 { }
2973 };
2974 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
2975 #else
2976 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2977 {
2978 return NULL;
2979 }
2980 #endif
2981
2982 static int sh_eth_drv_probe(struct platform_device *pdev)
2983 {
2984 struct resource *res;
2985 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
2986 const struct platform_device_id *id = platform_get_device_id(pdev);
2987 struct sh_eth_private *mdp;
2988 struct net_device *ndev;
2989 int ret, devno;
2990
2991 /* get base addr */
2992 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2993
2994 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2995 if (!ndev)
2996 return -ENOMEM;
2997
2998 pm_runtime_enable(&pdev->dev);
2999 pm_runtime_get_sync(&pdev->dev);
3000
3001 devno = pdev->id;
3002 if (devno < 0)
3003 devno = 0;
3004
3005 ret = platform_get_irq(pdev, 0);
3006 if (ret < 0)
3007 goto out_release;
3008 ndev->irq = ret;
3009
3010 SET_NETDEV_DEV(ndev, &pdev->dev);
3011
3012 mdp = netdev_priv(ndev);
3013 mdp->num_tx_ring = TX_RING_SIZE;
3014 mdp->num_rx_ring = RX_RING_SIZE;
3015 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3016 if (IS_ERR(mdp->addr)) {
3017 ret = PTR_ERR(mdp->addr);
3018 goto out_release;
3019 }
3020
3021 ndev->base_addr = res->start;
3022
3023 spin_lock_init(&mdp->lock);
3024 mdp->pdev = pdev;
3025
3026 if (pdev->dev.of_node)
3027 pd = sh_eth_parse_dt(&pdev->dev);
3028 if (!pd) {
3029 dev_err(&pdev->dev, "no platform data\n");
3030 ret = -EINVAL;
3031 goto out_release;
3032 }
3033
3034 /* get PHY ID */
3035 mdp->phy_id = pd->phy;
3036 mdp->phy_interface = pd->phy_interface;
3037 mdp->no_ether_link = pd->no_ether_link;
3038 mdp->ether_link_active_low = pd->ether_link_active_low;
3039
3040 /* set cpu data */
3041 if (id)
3042 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3043 else
3044 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
3045
3046 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3047 if (!mdp->reg_offset) {
3048 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3049 mdp->cd->register_type);
3050 ret = -EINVAL;
3051 goto out_release;
3052 }
3053 sh_eth_set_default_cpu_data(mdp->cd);
3054
3055 /* set function */
3056 if (mdp->cd->tsu)
3057 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3058 else
3059 ndev->netdev_ops = &sh_eth_netdev_ops;
3060 ndev->ethtool_ops = &sh_eth_ethtool_ops;
3061 ndev->watchdog_timeo = TX_TIMEOUT;
3062
3063 /* debug message level */
3064 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3065
3066 /* read and set MAC address */
3067 read_mac_address(ndev, pd->mac_addr);
3068 if (!is_valid_ether_addr(ndev->dev_addr)) {
3069 dev_warn(&pdev->dev,
3070 "no valid MAC address supplied, using a random one.\n");
3071 eth_hw_addr_random(ndev);
3072 }
3073
3074 /* ioremap the TSU registers */
3075 if (mdp->cd->tsu) {
3076 struct resource *rtsu;
3077 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3078 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3079 if (IS_ERR(mdp->tsu_addr)) {
3080 ret = PTR_ERR(mdp->tsu_addr);
3081 goto out_release;
3082 }
3083 mdp->port = devno % 2;
3084 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3085 }
3086
3087 /* initialize first or needed device */
3088 if (!devno || pd->needs_init) {
3089 if (mdp->cd->chip_reset)
3090 mdp->cd->chip_reset(ndev);
3091
3092 if (mdp->cd->tsu) {
3093 /* TSU init (Init only)*/
3094 sh_eth_tsu_init(mdp);
3095 }
3096 }
3097
3098 if (mdp->cd->rmiimode)
3099 sh_eth_write(ndev, 0x1, RMIIMODE);
3100
3101 /* MDIO bus init */
3102 ret = sh_mdio_init(mdp, pd);
3103 if (ret) {
3104 dev_err(&ndev->dev, "failed to initialise MDIO\n");
3105 goto out_release;
3106 }
3107
3108 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3109
3110 /* network device register */
3111 ret = register_netdev(ndev);
3112 if (ret)
3113 goto out_napi_del;
3114
3115 /* print device information */
3116 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3117 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3118
3119 pm_runtime_put(&pdev->dev);
3120 platform_set_drvdata(pdev, ndev);
3121
3122 return ret;
3123
3124 out_napi_del:
3125 netif_napi_del(&mdp->napi);
3126 sh_mdio_release(mdp);
3127
3128 out_release:
3129 /* net_dev free */
3130 if (ndev)
3131 free_netdev(ndev);
3132
3133 pm_runtime_put(&pdev->dev);
3134 pm_runtime_disable(&pdev->dev);
3135 return ret;
3136 }
3137
3138 static int sh_eth_drv_remove(struct platform_device *pdev)
3139 {
3140 struct net_device *ndev = platform_get_drvdata(pdev);
3141 struct sh_eth_private *mdp = netdev_priv(ndev);
3142
3143 unregister_netdev(ndev);
3144 netif_napi_del(&mdp->napi);
3145 sh_mdio_release(mdp);
3146 pm_runtime_disable(&pdev->dev);
3147 free_netdev(ndev);
3148
3149 return 0;
3150 }
3151
3152 #ifdef CONFIG_PM
3153 #ifdef CONFIG_PM_SLEEP
3154 static int sh_eth_suspend(struct device *dev)
3155 {
3156 struct net_device *ndev = dev_get_drvdata(dev);
3157 int ret = 0;
3158
3159 if (netif_running(ndev)) {
3160 netif_device_detach(ndev);
3161 ret = sh_eth_close(ndev);
3162 }
3163
3164 return ret;
3165 }
3166
3167 static int sh_eth_resume(struct device *dev)
3168 {
3169 struct net_device *ndev = dev_get_drvdata(dev);
3170 int ret = 0;
3171
3172 if (netif_running(ndev)) {
3173 ret = sh_eth_open(ndev);
3174 if (ret < 0)
3175 return ret;
3176 netif_device_attach(ndev);
3177 }
3178
3179 return ret;
3180 }
3181 #endif
3182
3183 static int sh_eth_runtime_nop(struct device *dev)
3184 {
3185 /* Runtime PM callback shared between ->runtime_suspend()
3186 * and ->runtime_resume(). Simply returns success.
3187 *
3188 * This driver re-initializes all registers after
3189 * pm_runtime_get_sync() anyway so there is no need
3190 * to save and restore registers here.
3191 */
3192 return 0;
3193 }
3194
3195 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3196 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3197 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3198 };
3199 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3200 #else
3201 #define SH_ETH_PM_OPS NULL
3202 #endif
3203
3204 static struct platform_device_id sh_eth_id_table[] = {
3205 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3206 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3207 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3208 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3209 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3210 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3211 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3212 { }
3213 };
3214 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3215
3216 static struct platform_driver sh_eth_driver = {
3217 .probe = sh_eth_drv_probe,
3218 .remove = sh_eth_drv_remove,
3219 .id_table = sh_eth_id_table,
3220 .driver = {
3221 .name = CARDNAME,
3222 .pm = SH_ETH_PM_OPS,
3223 .of_match_table = of_match_ptr(sh_eth_match_table),
3224 },
3225 };
3226
3227 module_platform_driver(sh_eth_driver);
3228
3229 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3230 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3231 MODULE_LICENSE("GPL v2");
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