1 /* SuperH Ethernet device driver
3 * Copyright (C) 2014 Renesas Electronics Corporation
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
6 * Copyright (C) 2013-2017 Cogent Embedded, Inc.
7 * Copyright (C) 2014 Codethink Limited
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/etherdevice.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/mdio-bitbang.h>
31 #include <linux/netdevice.h>
33 #include <linux/of_device.h>
34 #include <linux/of_irq.h>
35 #include <linux/of_net.h>
36 #include <linux/phy.h>
37 #include <linux/cache.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/slab.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43 #include <linux/clk.h>
44 #include <linux/sh_eth.h>
45 #include <linux/of_mdio.h>
49 #define SH_ETH_DEF_MSG_ENABLE \
55 #define SH_ETH_OFFSET_INVALID ((u16)~0)
57 #define SH_ETH_OFFSET_DEFAULTS \
58 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
60 static const u16 sh_eth_offset_gigabit
[SH_ETH_MAX_REGISTER_OFFSET
] = {
61 SH_ETH_OFFSET_DEFAULTS
,
116 [TSU_CTRST
] = 0x0004,
117 [TSU_FWEN0
] = 0x0010,
118 [TSU_FWEN1
] = 0x0014,
120 [TSU_BSYSL0
] = 0x0020,
121 [TSU_BSYSL1
] = 0x0024,
122 [TSU_PRISL0
] = 0x0028,
123 [TSU_PRISL1
] = 0x002c,
124 [TSU_FWSL0
] = 0x0030,
125 [TSU_FWSL1
] = 0x0034,
126 [TSU_FWSLC
] = 0x0038,
127 [TSU_QTAG0
] = 0x0040,
128 [TSU_QTAG1
] = 0x0044,
130 [TSU_FWINMK
] = 0x0054,
131 [TSU_ADQT0
] = 0x0048,
132 [TSU_ADQT1
] = 0x004c,
133 [TSU_VTAG0
] = 0x0058,
134 [TSU_VTAG1
] = 0x005c,
135 [TSU_ADSBSY
] = 0x0060,
137 [TSU_POST1
] = 0x0070,
138 [TSU_POST2
] = 0x0074,
139 [TSU_POST3
] = 0x0078,
140 [TSU_POST4
] = 0x007c,
141 [TSU_ADRH0
] = 0x0100,
157 static const u16 sh_eth_offset_fast_rz
[SH_ETH_MAX_REGISTER_OFFSET
] = {
158 SH_ETH_OFFSET_DEFAULTS
,
203 [TSU_CTRST
] = 0x0004,
204 [TSU_FWSLC
] = 0x0038,
205 [TSU_VTAG0
] = 0x0058,
206 [TSU_ADSBSY
] = 0x0060,
208 [TSU_POST1
] = 0x0070,
209 [TSU_POST2
] = 0x0074,
210 [TSU_POST3
] = 0x0078,
211 [TSU_POST4
] = 0x007c,
212 [TSU_ADRH0
] = 0x0100,
220 static const u16 sh_eth_offset_fast_rcar
[SH_ETH_MAX_REGISTER_OFFSET
] = {
221 SH_ETH_OFFSET_DEFAULTS
,
268 static const u16 sh_eth_offset_fast_sh4
[SH_ETH_MAX_REGISTER_OFFSET
] = {
269 SH_ETH_OFFSET_DEFAULTS
,
322 static const u16 sh_eth_offset_fast_sh3_sh2
[SH_ETH_MAX_REGISTER_OFFSET
] = {
323 SH_ETH_OFFSET_DEFAULTS
,
371 [TSU_CTRST
] = 0x0004,
372 [TSU_FWEN0
] = 0x0010,
373 [TSU_FWEN1
] = 0x0014,
375 [TSU_BSYSL0
] = 0x0020,
376 [TSU_BSYSL1
] = 0x0024,
377 [TSU_PRISL0
] = 0x0028,
378 [TSU_PRISL1
] = 0x002c,
379 [TSU_FWSL0
] = 0x0030,
380 [TSU_FWSL1
] = 0x0034,
381 [TSU_FWSLC
] = 0x0038,
382 [TSU_QTAGM0
] = 0x0040,
383 [TSU_QTAGM1
] = 0x0044,
384 [TSU_ADQT0
] = 0x0048,
385 [TSU_ADQT1
] = 0x004c,
387 [TSU_FWINMK
] = 0x0054,
388 [TSU_ADSBSY
] = 0x0060,
390 [TSU_POST1
] = 0x0070,
391 [TSU_POST2
] = 0x0074,
392 [TSU_POST3
] = 0x0078,
393 [TSU_POST4
] = 0x007c,
408 [TSU_ADRH0
] = 0x0100,
411 static void sh_eth_rcv_snd_disable(struct net_device
*ndev
);
412 static struct net_device_stats
*sh_eth_get_stats(struct net_device
*ndev
);
414 static void sh_eth_write(struct net_device
*ndev
, u32 data
, int enum_index
)
416 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
417 u16 offset
= mdp
->reg_offset
[enum_index
];
419 if (WARN_ON(offset
== SH_ETH_OFFSET_INVALID
))
422 iowrite32(data
, mdp
->addr
+ offset
);
425 static u32
sh_eth_read(struct net_device
*ndev
, int enum_index
)
427 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
428 u16 offset
= mdp
->reg_offset
[enum_index
];
430 if (WARN_ON(offset
== SH_ETH_OFFSET_INVALID
))
433 return ioread32(mdp
->addr
+ offset
);
436 static void sh_eth_modify(struct net_device
*ndev
, int enum_index
, u32 clear
,
439 sh_eth_write(ndev
, (sh_eth_read(ndev
, enum_index
) & ~clear
) | set
,
443 static bool sh_eth_is_gether(struct sh_eth_private
*mdp
)
445 return mdp
->reg_offset
== sh_eth_offset_gigabit
;
448 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private
*mdp
)
450 return mdp
->reg_offset
== sh_eth_offset_fast_rz
;
453 static void sh_eth_select_mii(struct net_device
*ndev
)
455 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
458 switch (mdp
->phy_interface
) {
459 case PHY_INTERFACE_MODE_GMII
:
462 case PHY_INTERFACE_MODE_MII
:
465 case PHY_INTERFACE_MODE_RMII
:
470 "PHY interface mode was not setup. Set to MII.\n");
475 sh_eth_write(ndev
, value
, RMII_MII
);
478 static void sh_eth_set_duplex(struct net_device
*ndev
)
480 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
482 sh_eth_modify(ndev
, ECMR
, ECMR_DM
, mdp
->duplex
? ECMR_DM
: 0);
485 static void sh_eth_chip_reset(struct net_device
*ndev
)
487 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
490 sh_eth_tsu_write(mdp
, ARSTR_ARST
, ARSTR
);
494 static void sh_eth_set_rate_gether(struct net_device
*ndev
)
496 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
498 switch (mdp
->speed
) {
499 case 10: /* 10BASE */
500 sh_eth_write(ndev
, GECMR_10
, GECMR
);
502 case 100:/* 100BASE */
503 sh_eth_write(ndev
, GECMR_100
, GECMR
);
505 case 1000: /* 1000BASE */
506 sh_eth_write(ndev
, GECMR_1000
, GECMR
);
513 static struct sh_eth_cpu_data r7s72100_data
= {
514 .chip_reset
= sh_eth_chip_reset
,
515 .set_duplex
= sh_eth_set_duplex
,
517 .register_type
= SH_ETH_REG_FAST_RZ
,
519 .ecsr_value
= ECSR_ICD
,
520 .ecsipr_value
= ECSIPR_ICDIP
,
521 .eesipr_value
= EESIPR_TWB1IP
| EESIPR_TWBIP
| EESIPR_TC1IP
|
522 EESIPR_TABTIP
| EESIPR_RABTIP
| EESIPR_RFCOFIP
|
524 EESIPR_FTCIP
| EESIPR_TDEIP
| EESIPR_TFUFIP
|
525 EESIPR_FRIP
| EESIPR_RDEIP
| EESIPR_RFOFIP
|
526 EESIPR_RMAFIP
| EESIPR_RRFIP
|
527 EESIPR_RTLFIP
| EESIPR_RTSFIP
|
528 EESIPR_PREIP
| EESIPR_CERFIP
,
530 .tx_check
= EESR_TC1
| EESR_FTC
,
531 .eesr_err_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_RABT
|
532 EESR_RFE
| EESR_RDE
| EESR_RFRMER
| EESR_TFE
|
534 .fdr_value
= 0x0000070f,
542 .rpadir_value
= 2 << 16,
549 static void sh_eth_chip_reset_r8a7740(struct net_device
*ndev
)
551 sh_eth_chip_reset(ndev
);
553 sh_eth_select_mii(ndev
);
557 static struct sh_eth_cpu_data r8a7740_data
= {
558 .chip_reset
= sh_eth_chip_reset_r8a7740
,
559 .set_duplex
= sh_eth_set_duplex
,
560 .set_rate
= sh_eth_set_rate_gether
,
562 .register_type
= SH_ETH_REG_GIGABIT
,
564 .ecsr_value
= ECSR_ICD
| ECSR_MPD
,
565 .ecsipr_value
= ECSIPR_LCHNGIP
| ECSIPR_ICDIP
| ECSIPR_MPDIP
,
566 .eesipr_value
= EESIPR_RFCOFIP
| EESIPR_ECIIP
|
567 EESIPR_FTCIP
| EESIPR_TDEIP
| EESIPR_TFUFIP
|
568 EESIPR_FRIP
| EESIPR_RDEIP
| EESIPR_RFOFIP
|
569 0x0000f000 | EESIPR_CNDIP
| EESIPR_DLCIP
|
570 EESIPR_CDIP
| EESIPR_TROIP
| EESIPR_RMAFIP
|
571 EESIPR_CEEFIP
| EESIPR_CELFIP
|
572 EESIPR_RRFIP
| EESIPR_RTLFIP
| EESIPR_RTSFIP
|
573 EESIPR_PREIP
| EESIPR_CERFIP
,
575 .tx_check
= EESR_TC1
| EESR_FTC
,
576 .eesr_err_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_RABT
|
577 EESR_RFE
| EESR_RDE
| EESR_RFRMER
| EESR_TFE
|
579 .fdr_value
= 0x0000070f,
587 .rpadir_value
= 2 << 16,
596 /* There is CPU dependent code */
597 static void sh_eth_set_rate_rcar(struct net_device
*ndev
)
599 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
601 switch (mdp
->speed
) {
602 case 10: /* 10BASE */
603 sh_eth_modify(ndev
, ECMR
, ECMR_ELB
, 0);
605 case 100:/* 100BASE */
606 sh_eth_modify(ndev
, ECMR
, ECMR_ELB
, ECMR_ELB
);
612 static struct sh_eth_cpu_data rcar_gen1_data
= {
613 .set_duplex
= sh_eth_set_duplex
,
614 .set_rate
= sh_eth_set_rate_rcar
,
616 .register_type
= SH_ETH_REG_FAST_RCAR
,
618 .ecsr_value
= ECSR_PSRTO
| ECSR_LCHNG
| ECSR_ICD
,
619 .ecsipr_value
= ECSIPR_PSRTOIP
| ECSIPR_LCHNGIP
| ECSIPR_ICDIP
,
620 .eesipr_value
= EESIPR_RFCOFIP
| EESIPR_ADEIP
| EESIPR_ECIIP
|
621 EESIPR_FTCIP
| EESIPR_TDEIP
| EESIPR_TFUFIP
|
622 EESIPR_FRIP
| EESIPR_RDEIP
| EESIPR_RFOFIP
|
623 EESIPR_RMAFIP
| EESIPR_RRFIP
|
624 EESIPR_RTLFIP
| EESIPR_RTSFIP
|
625 EESIPR_PREIP
| EESIPR_CERFIP
,
627 .tx_check
= EESR_FTC
| EESR_CND
| EESR_DLC
| EESR_CD
| EESR_RTO
,
628 .eesr_err_check
= EESR_TWB
| EESR_TABT
| EESR_RABT
| EESR_RFE
|
629 EESR_RDE
| EESR_RFRMER
| EESR_TFE
| EESR_TDE
,
630 .fdr_value
= 0x00000f0f,
638 /* R-Car Gen2 and RZ/G1 */
639 static struct sh_eth_cpu_data rcar_gen2_data
= {
640 .set_duplex
= sh_eth_set_duplex
,
641 .set_rate
= sh_eth_set_rate_rcar
,
643 .register_type
= SH_ETH_REG_FAST_RCAR
,
645 .ecsr_value
= ECSR_PSRTO
| ECSR_LCHNG
| ECSR_ICD
| ECSR_MPD
,
646 .ecsipr_value
= ECSIPR_PSRTOIP
| ECSIPR_LCHNGIP
| ECSIPR_ICDIP
|
648 .eesipr_value
= EESIPR_RFCOFIP
| EESIPR_ADEIP
| EESIPR_ECIIP
|
649 EESIPR_FTCIP
| EESIPR_TDEIP
| EESIPR_TFUFIP
|
650 EESIPR_FRIP
| EESIPR_RDEIP
| EESIPR_RFOFIP
|
651 EESIPR_RMAFIP
| EESIPR_RRFIP
|
652 EESIPR_RTLFIP
| EESIPR_RTSFIP
|
653 EESIPR_PREIP
| EESIPR_CERFIP
,
655 .tx_check
= EESR_FTC
| EESR_CND
| EESR_DLC
| EESR_CD
| EESR_RTO
,
656 .eesr_err_check
= EESR_TWB
| EESR_TABT
| EESR_RABT
| EESR_RFE
|
657 EESR_RDE
| EESR_RFRMER
| EESR_TFE
| EESR_TDE
,
658 .fdr_value
= 0x00000f0f,
660 .trscer_err_mask
= DESC_I_RINT8
,
669 #endif /* CONFIG_OF */
671 static void sh_eth_set_rate_sh7724(struct net_device
*ndev
)
673 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
675 switch (mdp
->speed
) {
676 case 10: /* 10BASE */
677 sh_eth_modify(ndev
, ECMR
, ECMR_RTM
, 0);
679 case 100:/* 100BASE */
680 sh_eth_modify(ndev
, ECMR
, ECMR_RTM
, ECMR_RTM
);
686 static struct sh_eth_cpu_data sh7724_data
= {
687 .set_duplex
= sh_eth_set_duplex
,
688 .set_rate
= sh_eth_set_rate_sh7724
,
690 .register_type
= SH_ETH_REG_FAST_SH4
,
692 .ecsr_value
= ECSR_PSRTO
| ECSR_LCHNG
| ECSR_ICD
,
693 .ecsipr_value
= ECSIPR_PSRTOIP
| ECSIPR_LCHNGIP
| ECSIPR_ICDIP
,
694 .eesipr_value
= EESIPR_RFCOFIP
| EESIPR_ADEIP
| EESIPR_ECIIP
|
695 EESIPR_FTCIP
| EESIPR_TDEIP
| EESIPR_TFUFIP
|
696 EESIPR_FRIP
| EESIPR_RDEIP
| EESIPR_RFOFIP
|
697 EESIPR_RMAFIP
| EESIPR_RRFIP
|
698 EESIPR_RTLFIP
| EESIPR_RTSFIP
|
699 EESIPR_PREIP
| EESIPR_CERFIP
,
701 .tx_check
= EESR_FTC
| EESR_CND
| EESR_DLC
| EESR_CD
| EESR_RTO
,
702 .eesr_err_check
= EESR_TWB
| EESR_TABT
| EESR_RABT
| EESR_RFE
|
703 EESR_RDE
| EESR_RFRMER
| EESR_TFE
| EESR_TDE
,
710 .rpadir_value
= 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
713 static void sh_eth_set_rate_sh7757(struct net_device
*ndev
)
715 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
717 switch (mdp
->speed
) {
718 case 10: /* 10BASE */
719 sh_eth_write(ndev
, 0, RTRATE
);
721 case 100:/* 100BASE */
722 sh_eth_write(ndev
, 1, RTRATE
);
728 static struct sh_eth_cpu_data sh7757_data
= {
729 .set_duplex
= sh_eth_set_duplex
,
730 .set_rate
= sh_eth_set_rate_sh7757
,
732 .register_type
= SH_ETH_REG_FAST_SH4
,
734 .eesipr_value
= EESIPR_RFCOFIP
| EESIPR_ECIIP
|
735 EESIPR_FTCIP
| EESIPR_TDEIP
| EESIPR_TFUFIP
|
736 EESIPR_FRIP
| EESIPR_RDEIP
| EESIPR_RFOFIP
|
737 0x0000f000 | EESIPR_CNDIP
| EESIPR_DLCIP
|
738 EESIPR_CDIP
| EESIPR_TROIP
| EESIPR_RMAFIP
|
739 EESIPR_CEEFIP
| EESIPR_CELFIP
|
740 EESIPR_RRFIP
| EESIPR_RTLFIP
| EESIPR_RTSFIP
|
741 EESIPR_PREIP
| EESIPR_CERFIP
,
743 .tx_check
= EESR_FTC
| EESR_CND
| EESR_DLC
| EESR_CD
| EESR_RTO
,
744 .eesr_err_check
= EESR_TWB
| EESR_TABT
| EESR_RABT
| EESR_RFE
|
745 EESR_RDE
| EESR_RFRMER
| EESR_TFE
| EESR_TDE
,
747 .irq_flags
= IRQF_SHARED
,
754 .rpadir_value
= 2 << 16,
758 #define SH_GIGA_ETH_BASE 0xfee00000UL
759 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
760 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
761 static void sh_eth_chip_reset_giga(struct net_device
*ndev
)
763 u32 mahr
[2], malr
[2];
766 /* save MAHR and MALR */
767 for (i
= 0; i
< 2; i
++) {
768 malr
[i
] = ioread32((void *)GIGA_MALR(i
));
769 mahr
[i
] = ioread32((void *)GIGA_MAHR(i
));
772 sh_eth_chip_reset(ndev
);
774 /* restore MAHR and MALR */
775 for (i
= 0; i
< 2; i
++) {
776 iowrite32(malr
[i
], (void *)GIGA_MALR(i
));
777 iowrite32(mahr
[i
], (void *)GIGA_MAHR(i
));
781 static void sh_eth_set_rate_giga(struct net_device
*ndev
)
783 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
785 switch (mdp
->speed
) {
786 case 10: /* 10BASE */
787 sh_eth_write(ndev
, 0x00000000, GECMR
);
789 case 100:/* 100BASE */
790 sh_eth_write(ndev
, 0x00000010, GECMR
);
792 case 1000: /* 1000BASE */
793 sh_eth_write(ndev
, 0x00000020, GECMR
);
798 /* SH7757(GETHERC) */
799 static struct sh_eth_cpu_data sh7757_data_giga
= {
800 .chip_reset
= sh_eth_chip_reset_giga
,
801 .set_duplex
= sh_eth_set_duplex
,
802 .set_rate
= sh_eth_set_rate_giga
,
804 .register_type
= SH_ETH_REG_GIGABIT
,
806 .ecsr_value
= ECSR_ICD
| ECSR_MPD
,
807 .ecsipr_value
= ECSIPR_LCHNGIP
| ECSIPR_ICDIP
| ECSIPR_MPDIP
,
808 .eesipr_value
= EESIPR_RFCOFIP
| EESIPR_ECIIP
|
809 EESIPR_FTCIP
| EESIPR_TDEIP
| EESIPR_TFUFIP
|
810 EESIPR_FRIP
| EESIPR_RDEIP
| EESIPR_RFOFIP
|
811 0x0000f000 | EESIPR_CNDIP
| EESIPR_DLCIP
|
812 EESIPR_CDIP
| EESIPR_TROIP
| EESIPR_RMAFIP
|
813 EESIPR_CEEFIP
| EESIPR_CELFIP
|
814 EESIPR_RRFIP
| EESIPR_RTLFIP
| EESIPR_RTSFIP
|
815 EESIPR_PREIP
| EESIPR_CERFIP
,
817 .tx_check
= EESR_TC1
| EESR_FTC
,
818 .eesr_err_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_RABT
|
819 EESR_RFE
| EESR_RDE
| EESR_RFRMER
| EESR_TFE
|
821 .fdr_value
= 0x0000072f,
823 .irq_flags
= IRQF_SHARED
,
830 .rpadir_value
= 2 << 16,
837 static struct sh_eth_cpu_data sh7734_data
= {
838 .chip_reset
= sh_eth_chip_reset
,
839 .set_duplex
= sh_eth_set_duplex
,
840 .set_rate
= sh_eth_set_rate_gether
,
842 .register_type
= SH_ETH_REG_GIGABIT
,
844 .ecsr_value
= ECSR_ICD
| ECSR_MPD
,
845 .ecsipr_value
= ECSIPR_LCHNGIP
| ECSIPR_ICDIP
| ECSIPR_MPDIP
,
846 .eesipr_value
= EESIPR_RFCOFIP
| EESIPR_ECIIP
|
847 EESIPR_FTCIP
| EESIPR_TDEIP
| EESIPR_TFUFIP
|
848 EESIPR_FRIP
| EESIPR_RDEIP
| EESIPR_RFOFIP
|
849 EESIPR_DLCIP
| EESIPR_CDIP
| EESIPR_TROIP
|
850 EESIPR_RMAFIP
| EESIPR_CEEFIP
| EESIPR_CELFIP
|
851 EESIPR_RRFIP
| EESIPR_RTLFIP
| EESIPR_RTSFIP
|
852 EESIPR_PREIP
| EESIPR_CERFIP
,
854 .tx_check
= EESR_TC1
| EESR_FTC
,
855 .eesr_err_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_RABT
|
856 EESR_RFE
| EESR_RDE
| EESR_RFRMER
| EESR_TFE
|
873 static struct sh_eth_cpu_data sh7763_data
= {
874 .chip_reset
= sh_eth_chip_reset
,
875 .set_duplex
= sh_eth_set_duplex
,
876 .set_rate
= sh_eth_set_rate_gether
,
878 .register_type
= SH_ETH_REG_GIGABIT
,
880 .ecsr_value
= ECSR_ICD
| ECSR_MPD
,
881 .ecsipr_value
= ECSIPR_LCHNGIP
| ECSIPR_ICDIP
| ECSIPR_MPDIP
,
882 .eesipr_value
= EESIPR_RFCOFIP
| EESIPR_ECIIP
|
883 EESIPR_FTCIP
| EESIPR_TDEIP
| EESIPR_TFUFIP
|
884 EESIPR_FRIP
| EESIPR_RDEIP
| EESIPR_RFOFIP
|
885 EESIPR_DLCIP
| EESIPR_CDIP
| EESIPR_TROIP
|
886 EESIPR_RMAFIP
| EESIPR_CEEFIP
| EESIPR_CELFIP
|
887 EESIPR_RRFIP
| EESIPR_RTLFIP
| EESIPR_RTSFIP
|
888 EESIPR_PREIP
| EESIPR_CERFIP
,
890 .tx_check
= EESR_TC1
| EESR_FTC
,
891 .eesr_err_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_RABT
|
892 EESR_RDE
| EESR_RFRMER
| EESR_TFE
| EESR_TDE
,
902 .irq_flags
= IRQF_SHARED
,
906 static struct sh_eth_cpu_data sh7619_data
= {
907 .register_type
= SH_ETH_REG_FAST_SH3_SH2
,
909 .eesipr_value
= EESIPR_RFCOFIP
| EESIPR_ECIIP
|
910 EESIPR_FTCIP
| EESIPR_TDEIP
| EESIPR_TFUFIP
|
911 EESIPR_FRIP
| EESIPR_RDEIP
| EESIPR_RFOFIP
|
912 0x0000f000 | EESIPR_CNDIP
| EESIPR_DLCIP
|
913 EESIPR_CDIP
| EESIPR_TROIP
| EESIPR_RMAFIP
|
914 EESIPR_CEEFIP
| EESIPR_CELFIP
|
915 EESIPR_RRFIP
| EESIPR_RTLFIP
| EESIPR_RTSFIP
|
916 EESIPR_PREIP
| EESIPR_CERFIP
,
924 static struct sh_eth_cpu_data sh771x_data
= {
925 .register_type
= SH_ETH_REG_FAST_SH3_SH2
,
927 .eesipr_value
= EESIPR_RFCOFIP
| EESIPR_ECIIP
|
928 EESIPR_FTCIP
| EESIPR_TDEIP
| EESIPR_TFUFIP
|
929 EESIPR_FRIP
| EESIPR_RDEIP
| EESIPR_RFOFIP
|
930 0x0000f000 | EESIPR_CNDIP
| EESIPR_DLCIP
|
931 EESIPR_CDIP
| EESIPR_TROIP
| EESIPR_RMAFIP
|
932 EESIPR_CEEFIP
| EESIPR_CELFIP
|
933 EESIPR_RRFIP
| EESIPR_RTLFIP
| EESIPR_RTSFIP
|
934 EESIPR_PREIP
| EESIPR_CERFIP
,
938 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data
*cd
)
941 cd
->ecsr_value
= DEFAULT_ECSR_INIT
;
943 if (!cd
->ecsipr_value
)
944 cd
->ecsipr_value
= DEFAULT_ECSIPR_INIT
;
946 if (!cd
->fcftr_value
)
947 cd
->fcftr_value
= DEFAULT_FIFO_F_D_RFF
|
948 DEFAULT_FIFO_F_D_RFD
;
951 cd
->fdr_value
= DEFAULT_FDR_INIT
;
954 cd
->tx_check
= DEFAULT_TX_CHECK
;
956 if (!cd
->eesr_err_check
)
957 cd
->eesr_err_check
= DEFAULT_EESR_ERR_CHECK
;
959 if (!cd
->trscer_err_mask
)
960 cd
->trscer_err_mask
= DEFAULT_TRSCER_ERR_MASK
;
963 static int sh_eth_check_reset(struct net_device
*ndev
)
969 if (!(sh_eth_read(ndev
, EDMR
) & EDMR_SRST_GETHER
))
975 netdev_err(ndev
, "Device reset failed\n");
981 static int sh_eth_reset(struct net_device
*ndev
)
983 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
986 if (sh_eth_is_gether(mdp
) || sh_eth_is_rz_fast_ether(mdp
)) {
987 sh_eth_write(ndev
, EDSR_ENALL
, EDSR
);
988 sh_eth_modify(ndev
, EDMR
, EDMR_SRST_GETHER
, EDMR_SRST_GETHER
);
990 ret
= sh_eth_check_reset(ndev
);
995 sh_eth_write(ndev
, 0x0, TDLAR
);
996 sh_eth_write(ndev
, 0x0, TDFAR
);
997 sh_eth_write(ndev
, 0x0, TDFXR
);
998 sh_eth_write(ndev
, 0x0, TDFFR
);
999 sh_eth_write(ndev
, 0x0, RDLAR
);
1000 sh_eth_write(ndev
, 0x0, RDFAR
);
1001 sh_eth_write(ndev
, 0x0, RDFXR
);
1002 sh_eth_write(ndev
, 0x0, RDFFR
);
1004 /* Reset HW CRC register */
1005 if (mdp
->cd
->hw_checksum
)
1006 sh_eth_write(ndev
, 0x0, CSMR
);
1008 /* Select MII mode */
1009 if (mdp
->cd
->select_mii
)
1010 sh_eth_select_mii(ndev
);
1012 sh_eth_modify(ndev
, EDMR
, EDMR_SRST_ETHER
, EDMR_SRST_ETHER
);
1014 sh_eth_modify(ndev
, EDMR
, EDMR_SRST_ETHER
, 0);
1020 static void sh_eth_set_receive_align(struct sk_buff
*skb
)
1022 uintptr_t reserve
= (uintptr_t)skb
->data
& (SH_ETH_RX_ALIGN
- 1);
1025 skb_reserve(skb
, SH_ETH_RX_ALIGN
- reserve
);
1028 /* Program the hardware MAC address from dev->dev_addr. */
1029 static void update_mac_address(struct net_device
*ndev
)
1032 (ndev
->dev_addr
[0] << 24) | (ndev
->dev_addr
[1] << 16) |
1033 (ndev
->dev_addr
[2] << 8) | (ndev
->dev_addr
[3]), MAHR
);
1035 (ndev
->dev_addr
[4] << 8) | (ndev
->dev_addr
[5]), MALR
);
1038 /* Get MAC address from SuperH MAC address register
1040 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
1041 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
1042 * When you want use this device, you must set MAC address in bootloader.
1045 static void read_mac_address(struct net_device
*ndev
, unsigned char *mac
)
1047 if (mac
[0] || mac
[1] || mac
[2] || mac
[3] || mac
[4] || mac
[5]) {
1048 memcpy(ndev
->dev_addr
, mac
, ETH_ALEN
);
1050 u32 mahr
= sh_eth_read(ndev
, MAHR
);
1051 u32 malr
= sh_eth_read(ndev
, MALR
);
1053 ndev
->dev_addr
[0] = (mahr
>> 24) & 0xFF;
1054 ndev
->dev_addr
[1] = (mahr
>> 16) & 0xFF;
1055 ndev
->dev_addr
[2] = (mahr
>> 8) & 0xFF;
1056 ndev
->dev_addr
[3] = (mahr
>> 0) & 0xFF;
1057 ndev
->dev_addr
[4] = (malr
>> 8) & 0xFF;
1058 ndev
->dev_addr
[5] = (malr
>> 0) & 0xFF;
1062 static u32
sh_eth_get_edtrr_trns(struct sh_eth_private
*mdp
)
1064 if (sh_eth_is_gether(mdp
) || sh_eth_is_rz_fast_ether(mdp
))
1065 return EDTRR_TRNS_GETHER
;
1067 return EDTRR_TRNS_ETHER
;
1071 void (*set_gate
)(void *addr
);
1072 struct mdiobb_ctrl ctrl
;
1076 static void sh_mdio_ctrl(struct mdiobb_ctrl
*ctrl
, u32 mask
, int set
)
1078 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
1081 if (bitbang
->set_gate
)
1082 bitbang
->set_gate(bitbang
->addr
);
1084 pir
= ioread32(bitbang
->addr
);
1089 iowrite32(pir
, bitbang
->addr
);
1092 /* Data I/O pin control */
1093 static void sh_mmd_ctrl(struct mdiobb_ctrl
*ctrl
, int bit
)
1095 sh_mdio_ctrl(ctrl
, PIR_MMD
, bit
);
1099 static void sh_set_mdio(struct mdiobb_ctrl
*ctrl
, int bit
)
1101 sh_mdio_ctrl(ctrl
, PIR_MDO
, bit
);
1105 static int sh_get_mdio(struct mdiobb_ctrl
*ctrl
)
1107 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
1109 if (bitbang
->set_gate
)
1110 bitbang
->set_gate(bitbang
->addr
);
1112 return (ioread32(bitbang
->addr
) & PIR_MDI
) != 0;
1115 /* MDC pin control */
1116 static void sh_mdc_ctrl(struct mdiobb_ctrl
*ctrl
, int bit
)
1118 sh_mdio_ctrl(ctrl
, PIR_MDC
, bit
);
1121 /* mdio bus control struct */
1122 static struct mdiobb_ops bb_ops
= {
1123 .owner
= THIS_MODULE
,
1124 .set_mdc
= sh_mdc_ctrl
,
1125 .set_mdio_dir
= sh_mmd_ctrl
,
1126 .set_mdio_data
= sh_set_mdio
,
1127 .get_mdio_data
= sh_get_mdio
,
1130 /* free Tx skb function */
1131 static int sh_eth_tx_free(struct net_device
*ndev
, bool sent_only
)
1133 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1134 struct sh_eth_txdesc
*txdesc
;
1139 for (; mdp
->cur_tx
- mdp
->dirty_tx
> 0; mdp
->dirty_tx
++) {
1140 entry
= mdp
->dirty_tx
% mdp
->num_tx_ring
;
1141 txdesc
= &mdp
->tx_ring
[entry
];
1142 sent
= !(txdesc
->status
& cpu_to_le32(TD_TACT
));
1143 if (sent_only
&& !sent
)
1145 /* TACT bit must be checked before all the following reads */
1147 netif_info(mdp
, tx_done
, ndev
,
1148 "tx entry %d status 0x%08x\n",
1149 entry
, le32_to_cpu(txdesc
->status
));
1150 /* Free the original skb. */
1151 if (mdp
->tx_skbuff
[entry
]) {
1152 dma_unmap_single(&mdp
->pdev
->dev
,
1153 le32_to_cpu(txdesc
->addr
),
1154 le32_to_cpu(txdesc
->len
) >> 16,
1156 dev_kfree_skb_irq(mdp
->tx_skbuff
[entry
]);
1157 mdp
->tx_skbuff
[entry
] = NULL
;
1160 txdesc
->status
= cpu_to_le32(TD_TFP
);
1161 if (entry
>= mdp
->num_tx_ring
- 1)
1162 txdesc
->status
|= cpu_to_le32(TD_TDLE
);
1165 ndev
->stats
.tx_packets
++;
1166 ndev
->stats
.tx_bytes
+= le32_to_cpu(txdesc
->len
) >> 16;
1172 /* free skb and descriptor buffer */
1173 static void sh_eth_ring_free(struct net_device
*ndev
)
1175 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1179 for (i
= 0; i
< mdp
->num_rx_ring
; i
++) {
1180 if (mdp
->rx_skbuff
[i
]) {
1181 struct sh_eth_rxdesc
*rxdesc
= &mdp
->rx_ring
[i
];
1183 dma_unmap_single(&mdp
->pdev
->dev
,
1184 le32_to_cpu(rxdesc
->addr
),
1185 ALIGN(mdp
->rx_buf_sz
, 32),
1189 ringsize
= sizeof(struct sh_eth_rxdesc
) * mdp
->num_rx_ring
;
1190 dma_free_coherent(&mdp
->pdev
->dev
, ringsize
, mdp
->rx_ring
,
1192 mdp
->rx_ring
= NULL
;
1195 /* Free Rx skb ringbuffer */
1196 if (mdp
->rx_skbuff
) {
1197 for (i
= 0; i
< mdp
->num_rx_ring
; i
++)
1198 dev_kfree_skb(mdp
->rx_skbuff
[i
]);
1200 kfree(mdp
->rx_skbuff
);
1201 mdp
->rx_skbuff
= NULL
;
1204 sh_eth_tx_free(ndev
, false);
1206 ringsize
= sizeof(struct sh_eth_txdesc
) * mdp
->num_tx_ring
;
1207 dma_free_coherent(&mdp
->pdev
->dev
, ringsize
, mdp
->tx_ring
,
1209 mdp
->tx_ring
= NULL
;
1212 /* Free Tx skb ringbuffer */
1213 kfree(mdp
->tx_skbuff
);
1214 mdp
->tx_skbuff
= NULL
;
1217 /* format skb and descriptor buffer */
1218 static void sh_eth_ring_format(struct net_device
*ndev
)
1220 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1222 struct sk_buff
*skb
;
1223 struct sh_eth_rxdesc
*rxdesc
= NULL
;
1224 struct sh_eth_txdesc
*txdesc
= NULL
;
1225 int rx_ringsize
= sizeof(*rxdesc
) * mdp
->num_rx_ring
;
1226 int tx_ringsize
= sizeof(*txdesc
) * mdp
->num_tx_ring
;
1227 int skbuff_size
= mdp
->rx_buf_sz
+ SH_ETH_RX_ALIGN
+ 32 - 1;
1228 dma_addr_t dma_addr
;
1236 memset(mdp
->rx_ring
, 0, rx_ringsize
);
1238 /* build Rx ring buffer */
1239 for (i
= 0; i
< mdp
->num_rx_ring
; i
++) {
1241 mdp
->rx_skbuff
[i
] = NULL
;
1242 skb
= netdev_alloc_skb(ndev
, skbuff_size
);
1245 sh_eth_set_receive_align(skb
);
1247 /* The size of the buffer is a multiple of 32 bytes. */
1248 buf_len
= ALIGN(mdp
->rx_buf_sz
, 32);
1249 dma_addr
= dma_map_single(&mdp
->pdev
->dev
, skb
->data
, buf_len
,
1251 if (dma_mapping_error(&mdp
->pdev
->dev
, dma_addr
)) {
1255 mdp
->rx_skbuff
[i
] = skb
;
1258 rxdesc
= &mdp
->rx_ring
[i
];
1259 rxdesc
->len
= cpu_to_le32(buf_len
<< 16);
1260 rxdesc
->addr
= cpu_to_le32(dma_addr
);
1261 rxdesc
->status
= cpu_to_le32(RD_RACT
| RD_RFP
);
1263 /* Rx descriptor address set */
1265 sh_eth_write(ndev
, mdp
->rx_desc_dma
, RDLAR
);
1266 if (sh_eth_is_gether(mdp
) ||
1267 sh_eth_is_rz_fast_ether(mdp
))
1268 sh_eth_write(ndev
, mdp
->rx_desc_dma
, RDFAR
);
1272 mdp
->dirty_rx
= (u32
) (i
- mdp
->num_rx_ring
);
1274 /* Mark the last entry as wrapping the ring. */
1276 rxdesc
->status
|= cpu_to_le32(RD_RDLE
);
1278 memset(mdp
->tx_ring
, 0, tx_ringsize
);
1280 /* build Tx ring buffer */
1281 for (i
= 0; i
< mdp
->num_tx_ring
; i
++) {
1282 mdp
->tx_skbuff
[i
] = NULL
;
1283 txdesc
= &mdp
->tx_ring
[i
];
1284 txdesc
->status
= cpu_to_le32(TD_TFP
);
1285 txdesc
->len
= cpu_to_le32(0);
1287 /* Tx descriptor address set */
1288 sh_eth_write(ndev
, mdp
->tx_desc_dma
, TDLAR
);
1289 if (sh_eth_is_gether(mdp
) ||
1290 sh_eth_is_rz_fast_ether(mdp
))
1291 sh_eth_write(ndev
, mdp
->tx_desc_dma
, TDFAR
);
1295 txdesc
->status
|= cpu_to_le32(TD_TDLE
);
1298 /* Get skb and descriptor buffer */
1299 static int sh_eth_ring_init(struct net_device
*ndev
)
1301 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1302 int rx_ringsize
, tx_ringsize
;
1304 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1305 * card needs room to do 8 byte alignment, +2 so we can reserve
1306 * the first 2 bytes, and +16 gets room for the status word from the
1309 mdp
->rx_buf_sz
= (ndev
->mtu
<= 1492 ? PKT_BUF_SZ
:
1310 (((ndev
->mtu
+ 26 + 7) & ~7) + 2 + 16));
1311 if (mdp
->cd
->rpadir
)
1312 mdp
->rx_buf_sz
+= NET_IP_ALIGN
;
1314 /* Allocate RX and TX skb rings */
1315 mdp
->rx_skbuff
= kcalloc(mdp
->num_rx_ring
, sizeof(*mdp
->rx_skbuff
),
1317 if (!mdp
->rx_skbuff
)
1320 mdp
->tx_skbuff
= kcalloc(mdp
->num_tx_ring
, sizeof(*mdp
->tx_skbuff
),
1322 if (!mdp
->tx_skbuff
)
1325 /* Allocate all Rx descriptors. */
1326 rx_ringsize
= sizeof(struct sh_eth_rxdesc
) * mdp
->num_rx_ring
;
1327 mdp
->rx_ring
= dma_alloc_coherent(&mdp
->pdev
->dev
, rx_ringsize
,
1328 &mdp
->rx_desc_dma
, GFP_KERNEL
);
1334 /* Allocate all Tx descriptors. */
1335 tx_ringsize
= sizeof(struct sh_eth_txdesc
) * mdp
->num_tx_ring
;
1336 mdp
->tx_ring
= dma_alloc_coherent(&mdp
->pdev
->dev
, tx_ringsize
,
1337 &mdp
->tx_desc_dma
, GFP_KERNEL
);
1343 /* Free Rx and Tx skb ring buffer and DMA buffer */
1344 sh_eth_ring_free(ndev
);
1349 static int sh_eth_dev_init(struct net_device
*ndev
)
1351 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1355 ret
= sh_eth_reset(ndev
);
1359 if (mdp
->cd
->rmiimode
)
1360 sh_eth_write(ndev
, 0x1, RMIIMODE
);
1362 /* Descriptor format */
1363 sh_eth_ring_format(ndev
);
1364 if (mdp
->cd
->rpadir
)
1365 sh_eth_write(ndev
, mdp
->cd
->rpadir_value
, RPADIR
);
1367 /* all sh_eth int mask */
1368 sh_eth_write(ndev
, 0, EESIPR
);
1370 #if defined(__LITTLE_ENDIAN)
1371 if (mdp
->cd
->hw_swap
)
1372 sh_eth_write(ndev
, EDMR_EL
, EDMR
);
1375 sh_eth_write(ndev
, 0, EDMR
);
1378 sh_eth_write(ndev
, mdp
->cd
->fdr_value
, FDR
);
1379 sh_eth_write(ndev
, 0, TFTR
);
1381 /* Frame recv control (enable multiple-packets per rx irq) */
1382 sh_eth_write(ndev
, RMCR_RNC
, RMCR
);
1384 sh_eth_write(ndev
, mdp
->cd
->trscer_err_mask
, TRSCER
);
1387 sh_eth_write(ndev
, 0x800, BCULR
); /* Burst sycle set */
1389 sh_eth_write(ndev
, mdp
->cd
->fcftr_value
, FCFTR
);
1391 if (!mdp
->cd
->no_trimd
)
1392 sh_eth_write(ndev
, 0, TRIMD
);
1394 /* Recv frame limit set register */
1395 sh_eth_write(ndev
, ndev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
+ ETH_FCS_LEN
,
1398 sh_eth_modify(ndev
, EESR
, 0, 0);
1399 mdp
->irq_enabled
= true;
1400 sh_eth_write(ndev
, mdp
->cd
->eesipr_value
, EESIPR
);
1402 /* PAUSE Prohibition */
1403 sh_eth_write(ndev
, ECMR_ZPF
| (mdp
->duplex
? ECMR_DM
: 0) |
1404 ECMR_TE
| ECMR_RE
, ECMR
);
1406 if (mdp
->cd
->set_rate
)
1407 mdp
->cd
->set_rate(ndev
);
1409 /* E-MAC Status Register clear */
1410 sh_eth_write(ndev
, mdp
->cd
->ecsr_value
, ECSR
);
1412 /* E-MAC Interrupt Enable register */
1413 sh_eth_write(ndev
, mdp
->cd
->ecsipr_value
, ECSIPR
);
1415 /* Set MAC address */
1416 update_mac_address(ndev
);
1420 sh_eth_write(ndev
, APR_AP
, APR
);
1422 sh_eth_write(ndev
, MPR_MP
, MPR
);
1423 if (mdp
->cd
->tpauser
)
1424 sh_eth_write(ndev
, TPAUSER_UNLIMITED
, TPAUSER
);
1426 /* Setting the Rx mode will start the Rx process. */
1427 sh_eth_write(ndev
, EDRRR_R
, EDRRR
);
1432 static void sh_eth_dev_exit(struct net_device
*ndev
)
1434 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1437 /* Deactivate all TX descriptors, so DMA should stop at next
1438 * packet boundary if it's currently running
1440 for (i
= 0; i
< mdp
->num_tx_ring
; i
++)
1441 mdp
->tx_ring
[i
].status
&= ~cpu_to_le32(TD_TACT
);
1443 /* Disable TX FIFO egress to MAC */
1444 sh_eth_rcv_snd_disable(ndev
);
1446 /* Stop RX DMA at next packet boundary */
1447 sh_eth_write(ndev
, 0, EDRRR
);
1449 /* Aside from TX DMA, we can't tell when the hardware is
1450 * really stopped, so we need to reset to make sure.
1451 * Before doing that, wait for long enough to *probably*
1452 * finish transmitting the last packet and poll stats.
1454 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1455 sh_eth_get_stats(ndev
);
1458 /* Set MAC address again */
1459 update_mac_address(ndev
);
1462 /* Packet receive function */
1463 static int sh_eth_rx(struct net_device
*ndev
, u32 intr_status
, int *quota
)
1465 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1466 struct sh_eth_rxdesc
*rxdesc
;
1468 int entry
= mdp
->cur_rx
% mdp
->num_rx_ring
;
1469 int boguscnt
= (mdp
->dirty_rx
+ mdp
->num_rx_ring
) - mdp
->cur_rx
;
1471 struct sk_buff
*skb
;
1473 int skbuff_size
= mdp
->rx_buf_sz
+ SH_ETH_RX_ALIGN
+ 32 - 1;
1474 dma_addr_t dma_addr
;
1478 boguscnt
= min(boguscnt
, *quota
);
1480 rxdesc
= &mdp
->rx_ring
[entry
];
1481 while (!(rxdesc
->status
& cpu_to_le32(RD_RACT
))) {
1482 /* RACT bit must be checked before all the following reads */
1484 desc_status
= le32_to_cpu(rxdesc
->status
);
1485 pkt_len
= le32_to_cpu(rxdesc
->len
) & RD_RFL
;
1490 netif_info(mdp
, rx_status
, ndev
,
1491 "rx entry %d status 0x%08x len %d\n",
1492 entry
, desc_status
, pkt_len
);
1494 if (!(desc_status
& RDFEND
))
1495 ndev
->stats
.rx_length_errors
++;
1497 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1498 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1499 * bit 0. However, in case of the R8A7740 and R7S72100
1500 * the RFS bits are from bit 25 to bit 16. So, the
1501 * driver needs right shifting by 16.
1503 if (mdp
->cd
->hw_checksum
)
1506 skb
= mdp
->rx_skbuff
[entry
];
1507 if (desc_status
& (RD_RFS1
| RD_RFS2
| RD_RFS3
| RD_RFS4
|
1508 RD_RFS5
| RD_RFS6
| RD_RFS10
)) {
1509 ndev
->stats
.rx_errors
++;
1510 if (desc_status
& RD_RFS1
)
1511 ndev
->stats
.rx_crc_errors
++;
1512 if (desc_status
& RD_RFS2
)
1513 ndev
->stats
.rx_frame_errors
++;
1514 if (desc_status
& RD_RFS3
)
1515 ndev
->stats
.rx_length_errors
++;
1516 if (desc_status
& RD_RFS4
)
1517 ndev
->stats
.rx_length_errors
++;
1518 if (desc_status
& RD_RFS6
)
1519 ndev
->stats
.rx_missed_errors
++;
1520 if (desc_status
& RD_RFS10
)
1521 ndev
->stats
.rx_over_errors
++;
1523 dma_addr
= le32_to_cpu(rxdesc
->addr
);
1524 if (!mdp
->cd
->hw_swap
)
1526 phys_to_virt(ALIGN(dma_addr
, 4)),
1528 mdp
->rx_skbuff
[entry
] = NULL
;
1529 if (mdp
->cd
->rpadir
)
1530 skb_reserve(skb
, NET_IP_ALIGN
);
1531 dma_unmap_single(&mdp
->pdev
->dev
, dma_addr
,
1532 ALIGN(mdp
->rx_buf_sz
, 32),
1534 skb_put(skb
, pkt_len
);
1535 skb
->protocol
= eth_type_trans(skb
, ndev
);
1536 netif_receive_skb(skb
);
1537 ndev
->stats
.rx_packets
++;
1538 ndev
->stats
.rx_bytes
+= pkt_len
;
1539 if (desc_status
& RD_RFS8
)
1540 ndev
->stats
.multicast
++;
1542 entry
= (++mdp
->cur_rx
) % mdp
->num_rx_ring
;
1543 rxdesc
= &mdp
->rx_ring
[entry
];
1546 /* Refill the Rx ring buffers. */
1547 for (; mdp
->cur_rx
- mdp
->dirty_rx
> 0; mdp
->dirty_rx
++) {
1548 entry
= mdp
->dirty_rx
% mdp
->num_rx_ring
;
1549 rxdesc
= &mdp
->rx_ring
[entry
];
1550 /* The size of the buffer is 32 byte boundary. */
1551 buf_len
= ALIGN(mdp
->rx_buf_sz
, 32);
1552 rxdesc
->len
= cpu_to_le32(buf_len
<< 16);
1554 if (mdp
->rx_skbuff
[entry
] == NULL
) {
1555 skb
= netdev_alloc_skb(ndev
, skbuff_size
);
1557 break; /* Better luck next round. */
1558 sh_eth_set_receive_align(skb
);
1559 dma_addr
= dma_map_single(&mdp
->pdev
->dev
, skb
->data
,
1560 buf_len
, DMA_FROM_DEVICE
);
1561 if (dma_mapping_error(&mdp
->pdev
->dev
, dma_addr
)) {
1565 mdp
->rx_skbuff
[entry
] = skb
;
1567 skb_checksum_none_assert(skb
);
1568 rxdesc
->addr
= cpu_to_le32(dma_addr
);
1570 dma_wmb(); /* RACT bit must be set after all the above writes */
1571 if (entry
>= mdp
->num_rx_ring
- 1)
1573 cpu_to_le32(RD_RACT
| RD_RFP
| RD_RDLE
);
1575 rxdesc
->status
|= cpu_to_le32(RD_RACT
| RD_RFP
);
1578 /* Restart Rx engine if stopped. */
1579 /* If we don't need to check status, don't. -KDU */
1580 if (!(sh_eth_read(ndev
, EDRRR
) & EDRRR_R
)) {
1581 /* fix the values for the next receiving if RDE is set */
1582 if (intr_status
& EESR_RDE
&&
1583 mdp
->reg_offset
[RDFAR
] != SH_ETH_OFFSET_INVALID
) {
1584 u32 count
= (sh_eth_read(ndev
, RDFAR
) -
1585 sh_eth_read(ndev
, RDLAR
)) >> 4;
1587 mdp
->cur_rx
= count
;
1588 mdp
->dirty_rx
= count
;
1590 sh_eth_write(ndev
, EDRRR_R
, EDRRR
);
1593 *quota
-= limit
- boguscnt
- 1;
1598 static void sh_eth_rcv_snd_disable(struct net_device
*ndev
)
1600 /* disable tx and rx */
1601 sh_eth_modify(ndev
, ECMR
, ECMR_RE
| ECMR_TE
, 0);
1604 static void sh_eth_rcv_snd_enable(struct net_device
*ndev
)
1606 /* enable tx and rx */
1607 sh_eth_modify(ndev
, ECMR
, ECMR_RE
| ECMR_TE
, ECMR_RE
| ECMR_TE
);
1610 /* E-MAC interrupt handler */
1611 static void sh_eth_emac_interrupt(struct net_device
*ndev
)
1613 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1617 felic_stat
= sh_eth_read(ndev
, ECSR
) & sh_eth_read(ndev
, ECSIPR
);
1618 sh_eth_write(ndev
, felic_stat
, ECSR
); /* clear int */
1619 if (felic_stat
& ECSR_ICD
)
1620 ndev
->stats
.tx_carrier_errors
++;
1621 if (felic_stat
& ECSR_MPD
)
1622 pm_wakeup_event(&mdp
->pdev
->dev
, 0);
1623 if (felic_stat
& ECSR_LCHNG
) {
1625 if (mdp
->cd
->no_psr
|| mdp
->no_ether_link
)
1627 link_stat
= sh_eth_read(ndev
, PSR
);
1628 if (mdp
->ether_link_active_low
)
1629 link_stat
= ~link_stat
;
1630 if (!(link_stat
& PHY_ST_LINK
)) {
1631 sh_eth_rcv_snd_disable(ndev
);
1634 sh_eth_modify(ndev
, EESIPR
, EESIPR_ECIIP
, 0);
1636 sh_eth_modify(ndev
, ECSR
, 0, 0);
1637 sh_eth_modify(ndev
, EESIPR
, EESIPR_ECIIP
, EESIPR_ECIIP
);
1638 /* enable tx and rx */
1639 sh_eth_rcv_snd_enable(ndev
);
1644 /* error control function */
1645 static void sh_eth_error(struct net_device
*ndev
, u32 intr_status
)
1647 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1650 if (intr_status
& EESR_TWB
) {
1651 /* Unused write back interrupt */
1652 if (intr_status
& EESR_TABT
) { /* Transmit Abort int */
1653 ndev
->stats
.tx_aborted_errors
++;
1654 netif_err(mdp
, tx_err
, ndev
, "Transmit Abort\n");
1658 if (intr_status
& EESR_RABT
) {
1659 /* Receive Abort int */
1660 if (intr_status
& EESR_RFRMER
) {
1661 /* Receive Frame Overflow int */
1662 ndev
->stats
.rx_frame_errors
++;
1666 if (intr_status
& EESR_TDE
) {
1667 /* Transmit Descriptor Empty int */
1668 ndev
->stats
.tx_fifo_errors
++;
1669 netif_err(mdp
, tx_err
, ndev
, "Transmit Descriptor Empty\n");
1672 if (intr_status
& EESR_TFE
) {
1673 /* FIFO under flow */
1674 ndev
->stats
.tx_fifo_errors
++;
1675 netif_err(mdp
, tx_err
, ndev
, "Transmit FIFO Under flow\n");
1678 if (intr_status
& EESR_RDE
) {
1679 /* Receive Descriptor Empty int */
1680 ndev
->stats
.rx_over_errors
++;
1683 if (intr_status
& EESR_RFE
) {
1684 /* Receive FIFO Overflow int */
1685 ndev
->stats
.rx_fifo_errors
++;
1688 if (!mdp
->cd
->no_ade
&& (intr_status
& EESR_ADE
)) {
1690 ndev
->stats
.tx_fifo_errors
++;
1691 netif_err(mdp
, tx_err
, ndev
, "Address Error\n");
1694 mask
= EESR_TWB
| EESR_TABT
| EESR_ADE
| EESR_TDE
| EESR_TFE
;
1695 if (mdp
->cd
->no_ade
)
1697 if (intr_status
& mask
) {
1699 u32 edtrr
= sh_eth_read(ndev
, EDTRR
);
1702 netdev_err(ndev
, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1703 intr_status
, mdp
->cur_tx
, mdp
->dirty_tx
,
1704 (u32
)ndev
->state
, edtrr
);
1705 /* dirty buffer free */
1706 sh_eth_tx_free(ndev
, true);
1709 if (edtrr
^ sh_eth_get_edtrr_trns(mdp
)) {
1711 sh_eth_write(ndev
, sh_eth_get_edtrr_trns(mdp
), EDTRR
);
1714 netif_wake_queue(ndev
);
1718 static irqreturn_t
sh_eth_interrupt(int irq
, void *netdev
)
1720 struct net_device
*ndev
= netdev
;
1721 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1722 struct sh_eth_cpu_data
*cd
= mdp
->cd
;
1723 irqreturn_t ret
= IRQ_NONE
;
1724 u32 intr_status
, intr_enable
;
1726 spin_lock(&mdp
->lock
);
1728 /* Get interrupt status */
1729 intr_status
= sh_eth_read(ndev
, EESR
);
1730 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1731 * enabled since it's the one that comes thru regardless of the mask,
1732 * and we need to fully handle it in sh_eth_emac_interrupt() in order
1733 * to quench it as it doesn't get cleared by just writing 1 to the ECI
1736 intr_enable
= sh_eth_read(ndev
, EESIPR
);
1737 intr_status
&= intr_enable
| EESIPR_ECIIP
;
1738 if (intr_status
& (EESR_RX_CHECK
| cd
->tx_check
| EESR_ECI
|
1739 cd
->eesr_err_check
))
1744 if (unlikely(!mdp
->irq_enabled
)) {
1745 sh_eth_write(ndev
, 0, EESIPR
);
1749 if (intr_status
& EESR_RX_CHECK
) {
1750 if (napi_schedule_prep(&mdp
->napi
)) {
1751 /* Mask Rx interrupts */
1752 sh_eth_write(ndev
, intr_enable
& ~EESR_RX_CHECK
,
1754 __napi_schedule(&mdp
->napi
);
1757 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1758 intr_status
, intr_enable
);
1763 if (intr_status
& cd
->tx_check
) {
1764 /* Clear Tx interrupts */
1765 sh_eth_write(ndev
, intr_status
& cd
->tx_check
, EESR
);
1767 sh_eth_tx_free(ndev
, true);
1768 netif_wake_queue(ndev
);
1771 /* E-MAC interrupt */
1772 if (intr_status
& EESR_ECI
)
1773 sh_eth_emac_interrupt(ndev
);
1775 if (intr_status
& cd
->eesr_err_check
) {
1776 /* Clear error interrupts */
1777 sh_eth_write(ndev
, intr_status
& cd
->eesr_err_check
, EESR
);
1779 sh_eth_error(ndev
, intr_status
);
1783 spin_unlock(&mdp
->lock
);
1788 static int sh_eth_poll(struct napi_struct
*napi
, int budget
)
1790 struct sh_eth_private
*mdp
= container_of(napi
, struct sh_eth_private
,
1792 struct net_device
*ndev
= napi
->dev
;
1797 intr_status
= sh_eth_read(ndev
, EESR
);
1798 if (!(intr_status
& EESR_RX_CHECK
))
1800 /* Clear Rx interrupts */
1801 sh_eth_write(ndev
, intr_status
& EESR_RX_CHECK
, EESR
);
1803 if (sh_eth_rx(ndev
, intr_status
, "a
))
1807 napi_complete(napi
);
1809 /* Reenable Rx interrupts */
1810 if (mdp
->irq_enabled
)
1811 sh_eth_write(ndev
, mdp
->cd
->eesipr_value
, EESIPR
);
1813 return budget
- quota
;
1816 /* PHY state control function */
1817 static void sh_eth_adjust_link(struct net_device
*ndev
)
1819 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1820 struct phy_device
*phydev
= ndev
->phydev
;
1824 if (phydev
->duplex
!= mdp
->duplex
) {
1826 mdp
->duplex
= phydev
->duplex
;
1827 if (mdp
->cd
->set_duplex
)
1828 mdp
->cd
->set_duplex(ndev
);
1831 if (phydev
->speed
!= mdp
->speed
) {
1833 mdp
->speed
= phydev
->speed
;
1834 if (mdp
->cd
->set_rate
)
1835 mdp
->cd
->set_rate(ndev
);
1838 sh_eth_modify(ndev
, ECMR
, ECMR_TXF
, 0);
1840 mdp
->link
= phydev
->link
;
1841 if (mdp
->cd
->no_psr
|| mdp
->no_ether_link
)
1842 sh_eth_rcv_snd_enable(ndev
);
1844 } else if (mdp
->link
) {
1849 if (mdp
->cd
->no_psr
|| mdp
->no_ether_link
)
1850 sh_eth_rcv_snd_disable(ndev
);
1853 if (new_state
&& netif_msg_link(mdp
))
1854 phy_print_status(phydev
);
1857 /* PHY init function */
1858 static int sh_eth_phy_init(struct net_device
*ndev
)
1860 struct device_node
*np
= ndev
->dev
.parent
->of_node
;
1861 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1862 struct phy_device
*phydev
;
1868 /* Try connect to PHY */
1870 struct device_node
*pn
;
1872 pn
= of_parse_phandle(np
, "phy-handle", 0);
1873 phydev
= of_phy_connect(ndev
, pn
,
1874 sh_eth_adjust_link
, 0,
1875 mdp
->phy_interface
);
1879 phydev
= ERR_PTR(-ENOENT
);
1881 char phy_id
[MII_BUS_ID_SIZE
+ 3];
1883 snprintf(phy_id
, sizeof(phy_id
), PHY_ID_FMT
,
1884 mdp
->mii_bus
->id
, mdp
->phy_id
);
1886 phydev
= phy_connect(ndev
, phy_id
, sh_eth_adjust_link
,
1887 mdp
->phy_interface
);
1890 if (IS_ERR(phydev
)) {
1891 netdev_err(ndev
, "failed to connect PHY\n");
1892 return PTR_ERR(phydev
);
1895 /* mask with MAC supported features */
1896 if (mdp
->cd
->register_type
!= SH_ETH_REG_GIGABIT
) {
1897 int err
= phy_set_max_speed(phydev
, SPEED_100
);
1899 netdev_err(ndev
, "failed to limit PHY to 100 Mbit/s\n");
1900 phy_disconnect(phydev
);
1905 phy_attached_info(phydev
);
1910 /* PHY control start function */
1911 static int sh_eth_phy_start(struct net_device
*ndev
)
1915 ret
= sh_eth_phy_init(ndev
);
1919 phy_start(ndev
->phydev
);
1924 static int sh_eth_get_link_ksettings(struct net_device
*ndev
,
1925 struct ethtool_link_ksettings
*cmd
)
1927 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1928 unsigned long flags
;
1933 spin_lock_irqsave(&mdp
->lock
, flags
);
1934 phy_ethtool_ksettings_get(ndev
->phydev
, cmd
);
1935 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1940 static int sh_eth_set_link_ksettings(struct net_device
*ndev
,
1941 const struct ethtool_link_ksettings
*cmd
)
1943 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1944 unsigned long flags
;
1950 spin_lock_irqsave(&mdp
->lock
, flags
);
1952 /* disable tx and rx */
1953 sh_eth_rcv_snd_disable(ndev
);
1955 ret
= phy_ethtool_ksettings_set(ndev
->phydev
, cmd
);
1959 if (cmd
->base
.duplex
== DUPLEX_FULL
)
1964 if (mdp
->cd
->set_duplex
)
1965 mdp
->cd
->set_duplex(ndev
);
1970 /* enable tx and rx */
1971 sh_eth_rcv_snd_enable(ndev
);
1973 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1978 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1979 * version must be bumped as well. Just adding registers up to that
1980 * limit is fine, as long as the existing register indices don't
1983 #define SH_ETH_REG_DUMP_VERSION 1
1984 #define SH_ETH_REG_DUMP_MAX_REGS 256
1986 static size_t __sh_eth_get_regs(struct net_device
*ndev
, u32
*buf
)
1988 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1989 struct sh_eth_cpu_data
*cd
= mdp
->cd
;
1993 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET
> SH_ETH_REG_DUMP_MAX_REGS
);
1995 /* Dump starts with a bitmap that tells ethtool which
1996 * registers are defined for this chip.
1998 len
= DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS
, 32);
2006 /* Add a register to the dump, if it has a defined offset.
2007 * This automatically skips most undefined registers, but for
2008 * some it is also necessary to check a capability flag in
2009 * struct sh_eth_cpu_data.
2011 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
2012 #define add_reg_from(reg, read_expr) do { \
2013 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
2015 mark_reg_valid(reg); \
2016 *buf++ = read_expr; \
2021 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
2022 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
2088 if (cd
->hw_checksum
)
2094 add_tsu_reg(TSU_CTRST
);
2095 add_tsu_reg(TSU_FWEN0
);
2096 add_tsu_reg(TSU_FWEN1
);
2097 add_tsu_reg(TSU_FCM
);
2098 add_tsu_reg(TSU_BSYSL0
);
2099 add_tsu_reg(TSU_BSYSL1
);
2100 add_tsu_reg(TSU_PRISL0
);
2101 add_tsu_reg(TSU_PRISL1
);
2102 add_tsu_reg(TSU_FWSL0
);
2103 add_tsu_reg(TSU_FWSL1
);
2104 add_tsu_reg(TSU_FWSLC
);
2105 add_tsu_reg(TSU_QTAG0
);
2106 add_tsu_reg(TSU_QTAG1
);
2107 add_tsu_reg(TSU_QTAGM0
);
2108 add_tsu_reg(TSU_QTAGM1
);
2109 add_tsu_reg(TSU_FWSR
);
2110 add_tsu_reg(TSU_FWINMK
);
2111 add_tsu_reg(TSU_ADQT0
);
2112 add_tsu_reg(TSU_ADQT1
);
2113 add_tsu_reg(TSU_VTAG0
);
2114 add_tsu_reg(TSU_VTAG1
);
2115 add_tsu_reg(TSU_ADSBSY
);
2116 add_tsu_reg(TSU_TEN
);
2117 add_tsu_reg(TSU_POST1
);
2118 add_tsu_reg(TSU_POST2
);
2119 add_tsu_reg(TSU_POST3
);
2120 add_tsu_reg(TSU_POST4
);
2121 if (mdp
->reg_offset
[TSU_ADRH0
] != SH_ETH_OFFSET_INVALID
) {
2122 /* This is the start of a table, not just a single
2128 mark_reg_valid(TSU_ADRH0
);
2129 for (i
= 0; i
< SH_ETH_TSU_CAM_ENTRIES
* 2; i
++)
2132 mdp
->reg_offset
[TSU_ADRH0
] +
2135 len
+= SH_ETH_TSU_CAM_ENTRIES
* 2;
2139 #undef mark_reg_valid
2147 static int sh_eth_get_regs_len(struct net_device
*ndev
)
2149 return __sh_eth_get_regs(ndev
, NULL
);
2152 static void sh_eth_get_regs(struct net_device
*ndev
, struct ethtool_regs
*regs
,
2155 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2157 regs
->version
= SH_ETH_REG_DUMP_VERSION
;
2159 pm_runtime_get_sync(&mdp
->pdev
->dev
);
2160 __sh_eth_get_regs(ndev
, buf
);
2161 pm_runtime_put_sync(&mdp
->pdev
->dev
);
2164 static int sh_eth_nway_reset(struct net_device
*ndev
)
2166 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2167 unsigned long flags
;
2173 spin_lock_irqsave(&mdp
->lock
, flags
);
2174 ret
= phy_start_aneg(ndev
->phydev
);
2175 spin_unlock_irqrestore(&mdp
->lock
, flags
);
2180 static u32
sh_eth_get_msglevel(struct net_device
*ndev
)
2182 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2183 return mdp
->msg_enable
;
2186 static void sh_eth_set_msglevel(struct net_device
*ndev
, u32 value
)
2188 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2189 mdp
->msg_enable
= value
;
2192 static const char sh_eth_gstrings_stats
[][ETH_GSTRING_LEN
] = {
2193 "rx_current", "tx_current",
2194 "rx_dirty", "tx_dirty",
2196 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2198 static int sh_eth_get_sset_count(struct net_device
*netdev
, int sset
)
2202 return SH_ETH_STATS_LEN
;
2208 static void sh_eth_get_ethtool_stats(struct net_device
*ndev
,
2209 struct ethtool_stats
*stats
, u64
*data
)
2211 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2214 /* device-specific stats */
2215 data
[i
++] = mdp
->cur_rx
;
2216 data
[i
++] = mdp
->cur_tx
;
2217 data
[i
++] = mdp
->dirty_rx
;
2218 data
[i
++] = mdp
->dirty_tx
;
2221 static void sh_eth_get_strings(struct net_device
*ndev
, u32 stringset
, u8
*data
)
2223 switch (stringset
) {
2225 memcpy(data
, *sh_eth_gstrings_stats
,
2226 sizeof(sh_eth_gstrings_stats
));
2231 static void sh_eth_get_ringparam(struct net_device
*ndev
,
2232 struct ethtool_ringparam
*ring
)
2234 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2236 ring
->rx_max_pending
= RX_RING_MAX
;
2237 ring
->tx_max_pending
= TX_RING_MAX
;
2238 ring
->rx_pending
= mdp
->num_rx_ring
;
2239 ring
->tx_pending
= mdp
->num_tx_ring
;
2242 static int sh_eth_set_ringparam(struct net_device
*ndev
,
2243 struct ethtool_ringparam
*ring
)
2245 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2248 if (ring
->tx_pending
> TX_RING_MAX
||
2249 ring
->rx_pending
> RX_RING_MAX
||
2250 ring
->tx_pending
< TX_RING_MIN
||
2251 ring
->rx_pending
< RX_RING_MIN
)
2253 if (ring
->rx_mini_pending
|| ring
->rx_jumbo_pending
)
2256 if (netif_running(ndev
)) {
2257 netif_device_detach(ndev
);
2258 netif_tx_disable(ndev
);
2260 /* Serialise with the interrupt handler and NAPI, then
2261 * disable interrupts. We have to clear the
2262 * irq_enabled flag first to ensure that interrupts
2263 * won't be re-enabled.
2265 mdp
->irq_enabled
= false;
2266 synchronize_irq(ndev
->irq
);
2267 napi_synchronize(&mdp
->napi
);
2268 sh_eth_write(ndev
, 0x0000, EESIPR
);
2270 sh_eth_dev_exit(ndev
);
2272 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2273 sh_eth_ring_free(ndev
);
2276 /* Set new parameters */
2277 mdp
->num_rx_ring
= ring
->rx_pending
;
2278 mdp
->num_tx_ring
= ring
->tx_pending
;
2280 if (netif_running(ndev
)) {
2281 ret
= sh_eth_ring_init(ndev
);
2283 netdev_err(ndev
, "%s: sh_eth_ring_init failed.\n",
2287 ret
= sh_eth_dev_init(ndev
);
2289 netdev_err(ndev
, "%s: sh_eth_dev_init failed.\n",
2294 netif_device_attach(ndev
);
2300 static void sh_eth_get_wol(struct net_device
*ndev
, struct ethtool_wolinfo
*wol
)
2302 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2307 if (mdp
->cd
->magic
&& mdp
->clk
) {
2308 wol
->supported
= WAKE_MAGIC
;
2309 wol
->wolopts
= mdp
->wol_enabled
? WAKE_MAGIC
: 0;
2313 static int sh_eth_set_wol(struct net_device
*ndev
, struct ethtool_wolinfo
*wol
)
2315 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2317 if (!mdp
->cd
->magic
|| !mdp
->clk
|| wol
->wolopts
& ~WAKE_MAGIC
)
2320 mdp
->wol_enabled
= !!(wol
->wolopts
& WAKE_MAGIC
);
2322 device_set_wakeup_enable(&mdp
->pdev
->dev
, mdp
->wol_enabled
);
2327 static const struct ethtool_ops sh_eth_ethtool_ops
= {
2328 .get_regs_len
= sh_eth_get_regs_len
,
2329 .get_regs
= sh_eth_get_regs
,
2330 .nway_reset
= sh_eth_nway_reset
,
2331 .get_msglevel
= sh_eth_get_msglevel
,
2332 .set_msglevel
= sh_eth_set_msglevel
,
2333 .get_link
= ethtool_op_get_link
,
2334 .get_strings
= sh_eth_get_strings
,
2335 .get_ethtool_stats
= sh_eth_get_ethtool_stats
,
2336 .get_sset_count
= sh_eth_get_sset_count
,
2337 .get_ringparam
= sh_eth_get_ringparam
,
2338 .set_ringparam
= sh_eth_set_ringparam
,
2339 .get_link_ksettings
= sh_eth_get_link_ksettings
,
2340 .set_link_ksettings
= sh_eth_set_link_ksettings
,
2341 .get_wol
= sh_eth_get_wol
,
2342 .set_wol
= sh_eth_set_wol
,
2345 /* network device open function */
2346 static int sh_eth_open(struct net_device
*ndev
)
2348 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2351 pm_runtime_get_sync(&mdp
->pdev
->dev
);
2353 napi_enable(&mdp
->napi
);
2355 ret
= request_irq(ndev
->irq
, sh_eth_interrupt
,
2356 mdp
->cd
->irq_flags
, ndev
->name
, ndev
);
2358 netdev_err(ndev
, "Can not assign IRQ number\n");
2362 /* Descriptor set */
2363 ret
= sh_eth_ring_init(ndev
);
2368 ret
= sh_eth_dev_init(ndev
);
2372 /* PHY control start*/
2373 ret
= sh_eth_phy_start(ndev
);
2377 netif_start_queue(ndev
);
2384 free_irq(ndev
->irq
, ndev
);
2386 napi_disable(&mdp
->napi
);
2387 pm_runtime_put_sync(&mdp
->pdev
->dev
);
2391 /* Timeout function */
2392 static void sh_eth_tx_timeout(struct net_device
*ndev
)
2394 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2395 struct sh_eth_rxdesc
*rxdesc
;
2398 netif_stop_queue(ndev
);
2400 netif_err(mdp
, timer
, ndev
,
2401 "transmit timed out, status %8.8x, resetting...\n",
2402 sh_eth_read(ndev
, EESR
));
2404 /* tx_errors count up */
2405 ndev
->stats
.tx_errors
++;
2407 /* Free all the skbuffs in the Rx queue. */
2408 for (i
= 0; i
< mdp
->num_rx_ring
; i
++) {
2409 rxdesc
= &mdp
->rx_ring
[i
];
2410 rxdesc
->status
= cpu_to_le32(0);
2411 rxdesc
->addr
= cpu_to_le32(0xBADF00D0);
2412 dev_kfree_skb(mdp
->rx_skbuff
[i
]);
2413 mdp
->rx_skbuff
[i
] = NULL
;
2415 for (i
= 0; i
< mdp
->num_tx_ring
; i
++) {
2416 dev_kfree_skb(mdp
->tx_skbuff
[i
]);
2417 mdp
->tx_skbuff
[i
] = NULL
;
2421 sh_eth_dev_init(ndev
);
2423 netif_start_queue(ndev
);
2426 /* Packet transmit function */
2427 static int sh_eth_start_xmit(struct sk_buff
*skb
, struct net_device
*ndev
)
2429 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2430 struct sh_eth_txdesc
*txdesc
;
2431 dma_addr_t dma_addr
;
2433 unsigned long flags
;
2435 spin_lock_irqsave(&mdp
->lock
, flags
);
2436 if ((mdp
->cur_tx
- mdp
->dirty_tx
) >= (mdp
->num_tx_ring
- 4)) {
2437 if (!sh_eth_tx_free(ndev
, true)) {
2438 netif_warn(mdp
, tx_queued
, ndev
, "TxFD exhausted.\n");
2439 netif_stop_queue(ndev
);
2440 spin_unlock_irqrestore(&mdp
->lock
, flags
);
2441 return NETDEV_TX_BUSY
;
2444 spin_unlock_irqrestore(&mdp
->lock
, flags
);
2446 if (skb_put_padto(skb
, ETH_ZLEN
))
2447 return NETDEV_TX_OK
;
2449 entry
= mdp
->cur_tx
% mdp
->num_tx_ring
;
2450 mdp
->tx_skbuff
[entry
] = skb
;
2451 txdesc
= &mdp
->tx_ring
[entry
];
2453 if (!mdp
->cd
->hw_swap
)
2454 sh_eth_soft_swap(PTR_ALIGN(skb
->data
, 4), skb
->len
+ 2);
2455 dma_addr
= dma_map_single(&mdp
->pdev
->dev
, skb
->data
, skb
->len
,
2457 if (dma_mapping_error(&mdp
->pdev
->dev
, dma_addr
)) {
2459 return NETDEV_TX_OK
;
2461 txdesc
->addr
= cpu_to_le32(dma_addr
);
2462 txdesc
->len
= cpu_to_le32(skb
->len
<< 16);
2464 dma_wmb(); /* TACT bit must be set after all the above writes */
2465 if (entry
>= mdp
->num_tx_ring
- 1)
2466 txdesc
->status
|= cpu_to_le32(TD_TACT
| TD_TDLE
);
2468 txdesc
->status
|= cpu_to_le32(TD_TACT
);
2472 if (!(sh_eth_read(ndev
, EDTRR
) & sh_eth_get_edtrr_trns(mdp
)))
2473 sh_eth_write(ndev
, sh_eth_get_edtrr_trns(mdp
), EDTRR
);
2475 return NETDEV_TX_OK
;
2478 /* The statistics registers have write-clear behaviour, which means we
2479 * will lose any increment between the read and write. We mitigate
2480 * this by only clearing when we read a non-zero value, so we will
2481 * never falsely report a total of zero.
2484 sh_eth_update_stat(struct net_device
*ndev
, unsigned long *stat
, int reg
)
2486 u32 delta
= sh_eth_read(ndev
, reg
);
2490 sh_eth_write(ndev
, 0, reg
);
2494 static struct net_device_stats
*sh_eth_get_stats(struct net_device
*ndev
)
2496 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2498 if (sh_eth_is_rz_fast_ether(mdp
))
2499 return &ndev
->stats
;
2501 if (!mdp
->is_opened
)
2502 return &ndev
->stats
;
2504 sh_eth_update_stat(ndev
, &ndev
->stats
.tx_dropped
, TROCR
);
2505 sh_eth_update_stat(ndev
, &ndev
->stats
.collisions
, CDCR
);
2506 sh_eth_update_stat(ndev
, &ndev
->stats
.tx_carrier_errors
, LCCR
);
2508 if (sh_eth_is_gether(mdp
)) {
2509 sh_eth_update_stat(ndev
, &ndev
->stats
.tx_carrier_errors
,
2511 sh_eth_update_stat(ndev
, &ndev
->stats
.tx_carrier_errors
,
2514 sh_eth_update_stat(ndev
, &ndev
->stats
.tx_carrier_errors
,
2518 return &ndev
->stats
;
2521 /* device close function */
2522 static int sh_eth_close(struct net_device
*ndev
)
2524 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2526 netif_stop_queue(ndev
);
2528 /* Serialise with the interrupt handler and NAPI, then disable
2529 * interrupts. We have to clear the irq_enabled flag first to
2530 * ensure that interrupts won't be re-enabled.
2532 mdp
->irq_enabled
= false;
2533 synchronize_irq(ndev
->irq
);
2534 napi_disable(&mdp
->napi
);
2535 sh_eth_write(ndev
, 0x0000, EESIPR
);
2537 sh_eth_dev_exit(ndev
);
2539 /* PHY Disconnect */
2541 phy_stop(ndev
->phydev
);
2542 phy_disconnect(ndev
->phydev
);
2545 free_irq(ndev
->irq
, ndev
);
2547 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2548 sh_eth_ring_free(ndev
);
2550 pm_runtime_put_sync(&mdp
->pdev
->dev
);
2557 /* ioctl to device function */
2558 static int sh_eth_do_ioctl(struct net_device
*ndev
, struct ifreq
*rq
, int cmd
)
2560 struct phy_device
*phydev
= ndev
->phydev
;
2562 if (!netif_running(ndev
))
2568 return phy_mii_ioctl(phydev
, rq
, cmd
);
2571 static int sh_eth_change_mtu(struct net_device
*ndev
, int new_mtu
)
2573 if (netif_running(ndev
))
2576 ndev
->mtu
= new_mtu
;
2577 netdev_update_features(ndev
);
2582 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2583 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private
*mdp
,
2586 return sh_eth_tsu_get_offset(mdp
, TSU_POST1
) + (entry
/ 8 * 4);
2589 static u32
sh_eth_tsu_get_post_mask(int entry
)
2591 return 0x0f << (28 - ((entry
% 8) * 4));
2594 static u32
sh_eth_tsu_get_post_bit(struct sh_eth_private
*mdp
, int entry
)
2596 return (0x08 >> (mdp
->port
<< 1)) << (28 - ((entry
% 8) * 4));
2599 static void sh_eth_tsu_enable_cam_entry_post(struct net_device
*ndev
,
2602 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2606 reg_offset
= sh_eth_tsu_get_post_reg_offset(mdp
, entry
);
2607 tmp
= ioread32(reg_offset
);
2608 iowrite32(tmp
| sh_eth_tsu_get_post_bit(mdp
, entry
), reg_offset
);
2611 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device
*ndev
,
2614 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2615 u32 post_mask
, ref_mask
, tmp
;
2618 reg_offset
= sh_eth_tsu_get_post_reg_offset(mdp
, entry
);
2619 post_mask
= sh_eth_tsu_get_post_mask(entry
);
2620 ref_mask
= sh_eth_tsu_get_post_bit(mdp
, entry
) & ~post_mask
;
2622 tmp
= ioread32(reg_offset
);
2623 iowrite32(tmp
& ~post_mask
, reg_offset
);
2625 /* If other port enables, the function returns "true" */
2626 return tmp
& ref_mask
;
2629 static int sh_eth_tsu_busy(struct net_device
*ndev
)
2631 int timeout
= SH_ETH_TSU_TIMEOUT_MS
* 100;
2632 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2634 while ((sh_eth_tsu_read(mdp
, TSU_ADSBSY
) & TSU_ADSBSY_0
)) {
2638 netdev_err(ndev
, "%s: timeout\n", __func__
);
2646 static int sh_eth_tsu_write_entry(struct net_device
*ndev
, void *reg
,
2651 val
= addr
[0] << 24 | addr
[1] << 16 | addr
[2] << 8 | addr
[3];
2652 iowrite32(val
, reg
);
2653 if (sh_eth_tsu_busy(ndev
) < 0)
2656 val
= addr
[4] << 8 | addr
[5];
2657 iowrite32(val
, reg
+ 4);
2658 if (sh_eth_tsu_busy(ndev
) < 0)
2664 static void sh_eth_tsu_read_entry(void *reg
, u8
*addr
)
2668 val
= ioread32(reg
);
2669 addr
[0] = (val
>> 24) & 0xff;
2670 addr
[1] = (val
>> 16) & 0xff;
2671 addr
[2] = (val
>> 8) & 0xff;
2672 addr
[3] = val
& 0xff;
2673 val
= ioread32(reg
+ 4);
2674 addr
[4] = (val
>> 8) & 0xff;
2675 addr
[5] = val
& 0xff;
2679 static int sh_eth_tsu_find_entry(struct net_device
*ndev
, const u8
*addr
)
2681 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2682 void *reg_offset
= sh_eth_tsu_get_offset(mdp
, TSU_ADRH0
);
2684 u8 c_addr
[ETH_ALEN
];
2686 for (i
= 0; i
< SH_ETH_TSU_CAM_ENTRIES
; i
++, reg_offset
+= 8) {
2687 sh_eth_tsu_read_entry(reg_offset
, c_addr
);
2688 if (ether_addr_equal(addr
, c_addr
))
2695 static int sh_eth_tsu_find_empty(struct net_device
*ndev
)
2700 memset(blank
, 0, sizeof(blank
));
2701 entry
= sh_eth_tsu_find_entry(ndev
, blank
);
2702 return (entry
< 0) ? -ENOMEM
: entry
;
2705 static int sh_eth_tsu_disable_cam_entry_table(struct net_device
*ndev
,
2708 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2709 void *reg_offset
= sh_eth_tsu_get_offset(mdp
, TSU_ADRH0
);
2713 sh_eth_tsu_write(mdp
, sh_eth_tsu_read(mdp
, TSU_TEN
) &
2714 ~(1 << (31 - entry
)), TSU_TEN
);
2716 memset(blank
, 0, sizeof(blank
));
2717 ret
= sh_eth_tsu_write_entry(ndev
, reg_offset
+ entry
* 8, blank
);
2723 static int sh_eth_tsu_add_entry(struct net_device
*ndev
, const u8
*addr
)
2725 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2726 void *reg_offset
= sh_eth_tsu_get_offset(mdp
, TSU_ADRH0
);
2732 i
= sh_eth_tsu_find_entry(ndev
, addr
);
2734 /* No entry found, create one */
2735 i
= sh_eth_tsu_find_empty(ndev
);
2738 ret
= sh_eth_tsu_write_entry(ndev
, reg_offset
+ i
* 8, addr
);
2742 /* Enable the entry */
2743 sh_eth_tsu_write(mdp
, sh_eth_tsu_read(mdp
, TSU_TEN
) |
2744 (1 << (31 - i
)), TSU_TEN
);
2747 /* Entry found or created, enable POST */
2748 sh_eth_tsu_enable_cam_entry_post(ndev
, i
);
2753 static int sh_eth_tsu_del_entry(struct net_device
*ndev
, const u8
*addr
)
2755 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2761 i
= sh_eth_tsu_find_entry(ndev
, addr
);
2764 if (sh_eth_tsu_disable_cam_entry_post(ndev
, i
))
2767 /* Disable the entry if both ports was disabled */
2768 ret
= sh_eth_tsu_disable_cam_entry_table(ndev
, i
);
2776 static int sh_eth_tsu_purge_all(struct net_device
*ndev
)
2778 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2784 for (i
= 0; i
< SH_ETH_TSU_CAM_ENTRIES
; i
++) {
2785 if (sh_eth_tsu_disable_cam_entry_post(ndev
, i
))
2788 /* Disable the entry if both ports was disabled */
2789 ret
= sh_eth_tsu_disable_cam_entry_table(ndev
, i
);
2797 static void sh_eth_tsu_purge_mcast(struct net_device
*ndev
)
2799 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2801 void *reg_offset
= sh_eth_tsu_get_offset(mdp
, TSU_ADRH0
);
2807 for (i
= 0; i
< SH_ETH_TSU_CAM_ENTRIES
; i
++, reg_offset
+= 8) {
2808 sh_eth_tsu_read_entry(reg_offset
, addr
);
2809 if (is_multicast_ether_addr(addr
))
2810 sh_eth_tsu_del_entry(ndev
, addr
);
2814 /* Update promiscuous flag and multicast filter */
2815 static void sh_eth_set_rx_mode(struct net_device
*ndev
)
2817 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2820 unsigned long flags
;
2822 spin_lock_irqsave(&mdp
->lock
, flags
);
2823 /* Initial condition is MCT = 1, PRM = 0.
2824 * Depending on ndev->flags, set PRM or clear MCT
2826 ecmr_bits
= sh_eth_read(ndev
, ECMR
) & ~ECMR_PRM
;
2828 ecmr_bits
|= ECMR_MCT
;
2830 if (!(ndev
->flags
& IFF_MULTICAST
)) {
2831 sh_eth_tsu_purge_mcast(ndev
);
2834 if (ndev
->flags
& IFF_ALLMULTI
) {
2835 sh_eth_tsu_purge_mcast(ndev
);
2836 ecmr_bits
&= ~ECMR_MCT
;
2840 if (ndev
->flags
& IFF_PROMISC
) {
2841 sh_eth_tsu_purge_all(ndev
);
2842 ecmr_bits
= (ecmr_bits
& ~ECMR_MCT
) | ECMR_PRM
;
2843 } else if (mdp
->cd
->tsu
) {
2844 struct netdev_hw_addr
*ha
;
2845 netdev_for_each_mc_addr(ha
, ndev
) {
2846 if (mcast_all
&& is_multicast_ether_addr(ha
->addr
))
2849 if (sh_eth_tsu_add_entry(ndev
, ha
->addr
) < 0) {
2851 sh_eth_tsu_purge_mcast(ndev
);
2852 ecmr_bits
&= ~ECMR_MCT
;
2859 /* update the ethernet mode */
2860 sh_eth_write(ndev
, ecmr_bits
, ECMR
);
2862 spin_unlock_irqrestore(&mdp
->lock
, flags
);
2865 static int sh_eth_get_vtag_index(struct sh_eth_private
*mdp
)
2873 static int sh_eth_vlan_rx_add_vid(struct net_device
*ndev
,
2874 __be16 proto
, u16 vid
)
2876 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2877 int vtag_reg_index
= sh_eth_get_vtag_index(mdp
);
2879 if (unlikely(!mdp
->cd
->tsu
))
2882 /* No filtering if vid = 0 */
2886 mdp
->vlan_num_ids
++;
2888 /* The controller has one VLAN tag HW filter. So, if the filter is
2889 * already enabled, the driver disables it and the filte
2891 if (mdp
->vlan_num_ids
> 1) {
2892 /* disable VLAN filter */
2893 sh_eth_tsu_write(mdp
, 0, vtag_reg_index
);
2897 sh_eth_tsu_write(mdp
, TSU_VTAG_ENABLE
| (vid
& TSU_VTAG_VID_MASK
),
2903 static int sh_eth_vlan_rx_kill_vid(struct net_device
*ndev
,
2904 __be16 proto
, u16 vid
)
2906 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
2907 int vtag_reg_index
= sh_eth_get_vtag_index(mdp
);
2909 if (unlikely(!mdp
->cd
->tsu
))
2912 /* No filtering if vid = 0 */
2916 mdp
->vlan_num_ids
--;
2917 sh_eth_tsu_write(mdp
, 0, vtag_reg_index
);
2922 /* SuperH's TSU register init function */
2923 static void sh_eth_tsu_init(struct sh_eth_private
*mdp
)
2925 if (sh_eth_is_rz_fast_ether(mdp
)) {
2926 sh_eth_tsu_write(mdp
, 0, TSU_TEN
); /* Disable all CAM entry */
2927 sh_eth_tsu_write(mdp
, TSU_FWSLC_POSTENU
| TSU_FWSLC_POSTENL
,
2928 TSU_FWSLC
); /* Enable POST registers */
2932 sh_eth_tsu_write(mdp
, 0, TSU_FWEN0
); /* Disable forward(0->1) */
2933 sh_eth_tsu_write(mdp
, 0, TSU_FWEN1
); /* Disable forward(1->0) */
2934 sh_eth_tsu_write(mdp
, 0, TSU_FCM
); /* forward fifo 3k-3k */
2935 sh_eth_tsu_write(mdp
, 0xc, TSU_BSYSL0
);
2936 sh_eth_tsu_write(mdp
, 0xc, TSU_BSYSL1
);
2937 sh_eth_tsu_write(mdp
, 0, TSU_PRISL0
);
2938 sh_eth_tsu_write(mdp
, 0, TSU_PRISL1
);
2939 sh_eth_tsu_write(mdp
, 0, TSU_FWSL0
);
2940 sh_eth_tsu_write(mdp
, 0, TSU_FWSL1
);
2941 sh_eth_tsu_write(mdp
, TSU_FWSLC_POSTENU
| TSU_FWSLC_POSTENL
, TSU_FWSLC
);
2942 if (sh_eth_is_gether(mdp
)) {
2943 sh_eth_tsu_write(mdp
, 0, TSU_QTAG0
); /* Disable QTAG(0->1) */
2944 sh_eth_tsu_write(mdp
, 0, TSU_QTAG1
); /* Disable QTAG(1->0) */
2946 sh_eth_tsu_write(mdp
, 0, TSU_QTAGM0
); /* Disable QTAG(0->1) */
2947 sh_eth_tsu_write(mdp
, 0, TSU_QTAGM1
); /* Disable QTAG(1->0) */
2949 sh_eth_tsu_write(mdp
, 0, TSU_FWSR
); /* all interrupt status clear */
2950 sh_eth_tsu_write(mdp
, 0, TSU_FWINMK
); /* Disable all interrupt */
2951 sh_eth_tsu_write(mdp
, 0, TSU_TEN
); /* Disable all CAM entry */
2952 sh_eth_tsu_write(mdp
, 0, TSU_POST1
); /* Disable CAM entry [ 0- 7] */
2953 sh_eth_tsu_write(mdp
, 0, TSU_POST2
); /* Disable CAM entry [ 8-15] */
2954 sh_eth_tsu_write(mdp
, 0, TSU_POST3
); /* Disable CAM entry [16-23] */
2955 sh_eth_tsu_write(mdp
, 0, TSU_POST4
); /* Disable CAM entry [24-31] */
2958 /* MDIO bus release function */
2959 static int sh_mdio_release(struct sh_eth_private
*mdp
)
2961 /* unregister mdio bus */
2962 mdiobus_unregister(mdp
->mii_bus
);
2964 /* free bitbang info */
2965 free_mdio_bitbang(mdp
->mii_bus
);
2970 /* MDIO bus init function */
2971 static int sh_mdio_init(struct sh_eth_private
*mdp
,
2972 struct sh_eth_plat_data
*pd
)
2975 struct bb_info
*bitbang
;
2976 struct platform_device
*pdev
= mdp
->pdev
;
2977 struct device
*dev
= &mdp
->pdev
->dev
;
2979 /* create bit control struct for PHY */
2980 bitbang
= devm_kzalloc(dev
, sizeof(struct bb_info
), GFP_KERNEL
);
2985 bitbang
->addr
= mdp
->addr
+ mdp
->reg_offset
[PIR
];
2986 bitbang
->set_gate
= pd
->set_mdio_gate
;
2987 bitbang
->ctrl
.ops
= &bb_ops
;
2989 /* MII controller setting */
2990 mdp
->mii_bus
= alloc_mdio_bitbang(&bitbang
->ctrl
);
2994 /* Hook up MII support for ethtool */
2995 mdp
->mii_bus
->name
= "sh_mii";
2996 mdp
->mii_bus
->parent
= dev
;
2997 snprintf(mdp
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%s-%x",
2998 pdev
->name
, pdev
->id
);
3000 /* register MDIO bus */
3002 ret
= of_mdiobus_register(mdp
->mii_bus
, dev
->of_node
);
3004 if (pd
->phy_irq
> 0)
3005 mdp
->mii_bus
->irq
[pd
->phy
] = pd
->phy_irq
;
3007 ret
= mdiobus_register(mdp
->mii_bus
);
3016 free_mdio_bitbang(mdp
->mii_bus
);
3020 static const u16
*sh_eth_get_register_offset(int register_type
)
3022 const u16
*reg_offset
= NULL
;
3024 switch (register_type
) {
3025 case SH_ETH_REG_GIGABIT
:
3026 reg_offset
= sh_eth_offset_gigabit
;
3028 case SH_ETH_REG_FAST_RZ
:
3029 reg_offset
= sh_eth_offset_fast_rz
;
3031 case SH_ETH_REG_FAST_RCAR
:
3032 reg_offset
= sh_eth_offset_fast_rcar
;
3034 case SH_ETH_REG_FAST_SH4
:
3035 reg_offset
= sh_eth_offset_fast_sh4
;
3037 case SH_ETH_REG_FAST_SH3_SH2
:
3038 reg_offset
= sh_eth_offset_fast_sh3_sh2
;
3045 static const struct net_device_ops sh_eth_netdev_ops
= {
3046 .ndo_open
= sh_eth_open
,
3047 .ndo_stop
= sh_eth_close
,
3048 .ndo_start_xmit
= sh_eth_start_xmit
,
3049 .ndo_get_stats
= sh_eth_get_stats
,
3050 .ndo_set_rx_mode
= sh_eth_set_rx_mode
,
3051 .ndo_tx_timeout
= sh_eth_tx_timeout
,
3052 .ndo_do_ioctl
= sh_eth_do_ioctl
,
3053 .ndo_change_mtu
= sh_eth_change_mtu
,
3054 .ndo_validate_addr
= eth_validate_addr
,
3055 .ndo_set_mac_address
= eth_mac_addr
,
3058 static const struct net_device_ops sh_eth_netdev_ops_tsu
= {
3059 .ndo_open
= sh_eth_open
,
3060 .ndo_stop
= sh_eth_close
,
3061 .ndo_start_xmit
= sh_eth_start_xmit
,
3062 .ndo_get_stats
= sh_eth_get_stats
,
3063 .ndo_set_rx_mode
= sh_eth_set_rx_mode
,
3064 .ndo_vlan_rx_add_vid
= sh_eth_vlan_rx_add_vid
,
3065 .ndo_vlan_rx_kill_vid
= sh_eth_vlan_rx_kill_vid
,
3066 .ndo_tx_timeout
= sh_eth_tx_timeout
,
3067 .ndo_do_ioctl
= sh_eth_do_ioctl
,
3068 .ndo_change_mtu
= sh_eth_change_mtu
,
3069 .ndo_validate_addr
= eth_validate_addr
,
3070 .ndo_set_mac_address
= eth_mac_addr
,
3074 static struct sh_eth_plat_data
*sh_eth_parse_dt(struct device
*dev
)
3076 struct device_node
*np
= dev
->of_node
;
3077 struct sh_eth_plat_data
*pdata
;
3078 const char *mac_addr
;
3080 pdata
= devm_kzalloc(dev
, sizeof(*pdata
), GFP_KERNEL
);
3084 pdata
->phy_interface
= of_get_phy_mode(np
);
3086 mac_addr
= of_get_mac_address(np
);
3088 memcpy(pdata
->mac_addr
, mac_addr
, ETH_ALEN
);
3090 pdata
->no_ether_link
=
3091 of_property_read_bool(np
, "renesas,no-ether-link");
3092 pdata
->ether_link_active_low
=
3093 of_property_read_bool(np
, "renesas,ether-link-active-low");
3098 static const struct of_device_id sh_eth_match_table
[] = {
3099 { .compatible
= "renesas,gether-r8a7740", .data
= &r8a7740_data
},
3100 { .compatible
= "renesas,ether-r8a7743", .data
= &rcar_gen2_data
},
3101 { .compatible
= "renesas,ether-r8a7745", .data
= &rcar_gen2_data
},
3102 { .compatible
= "renesas,ether-r8a7778", .data
= &rcar_gen1_data
},
3103 { .compatible
= "renesas,ether-r8a7779", .data
= &rcar_gen1_data
},
3104 { .compatible
= "renesas,ether-r8a7790", .data
= &rcar_gen2_data
},
3105 { .compatible
= "renesas,ether-r8a7791", .data
= &rcar_gen2_data
},
3106 { .compatible
= "renesas,ether-r8a7793", .data
= &rcar_gen2_data
},
3107 { .compatible
= "renesas,ether-r8a7794", .data
= &rcar_gen2_data
},
3108 { .compatible
= "renesas,ether-r7s72100", .data
= &r7s72100_data
},
3109 { .compatible
= "renesas,rcar-gen1-ether", .data
= &rcar_gen1_data
},
3110 { .compatible
= "renesas,rcar-gen2-ether", .data
= &rcar_gen2_data
},
3113 MODULE_DEVICE_TABLE(of
, sh_eth_match_table
);
3115 static inline struct sh_eth_plat_data
*sh_eth_parse_dt(struct device
*dev
)
3121 static int sh_eth_drv_probe(struct platform_device
*pdev
)
3123 struct resource
*res
;
3124 struct sh_eth_plat_data
*pd
= dev_get_platdata(&pdev
->dev
);
3125 const struct platform_device_id
*id
= platform_get_device_id(pdev
);
3126 struct sh_eth_private
*mdp
;
3127 struct net_device
*ndev
;
3131 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
3133 ndev
= alloc_etherdev(sizeof(struct sh_eth_private
));
3137 pm_runtime_enable(&pdev
->dev
);
3138 pm_runtime_get_sync(&pdev
->dev
);
3144 ret
= platform_get_irq(pdev
, 0);
3149 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
3151 mdp
= netdev_priv(ndev
);
3152 mdp
->num_tx_ring
= TX_RING_SIZE
;
3153 mdp
->num_rx_ring
= RX_RING_SIZE
;
3154 mdp
->addr
= devm_ioremap_resource(&pdev
->dev
, res
);
3155 if (IS_ERR(mdp
->addr
)) {
3156 ret
= PTR_ERR(mdp
->addr
);
3160 /* Get clock, if not found that's OK but Wake-On-Lan is unavailable */
3161 mdp
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
3162 if (IS_ERR(mdp
->clk
))
3165 ndev
->base_addr
= res
->start
;
3167 spin_lock_init(&mdp
->lock
);
3170 if (pdev
->dev
.of_node
)
3171 pd
= sh_eth_parse_dt(&pdev
->dev
);
3173 dev_err(&pdev
->dev
, "no platform data\n");
3179 mdp
->phy_id
= pd
->phy
;
3180 mdp
->phy_interface
= pd
->phy_interface
;
3181 mdp
->no_ether_link
= pd
->no_ether_link
;
3182 mdp
->ether_link_active_low
= pd
->ether_link_active_low
;
3186 mdp
->cd
= (struct sh_eth_cpu_data
*)id
->driver_data
;
3188 mdp
->cd
= (struct sh_eth_cpu_data
*)of_device_get_match_data(&pdev
->dev
);
3190 mdp
->reg_offset
= sh_eth_get_register_offset(mdp
->cd
->register_type
);
3191 if (!mdp
->reg_offset
) {
3192 dev_err(&pdev
->dev
, "Unknown register type (%d)\n",
3193 mdp
->cd
->register_type
);
3197 sh_eth_set_default_cpu_data(mdp
->cd
);
3199 /* User's manual states max MTU should be 2048 but due to the
3200 * alignment calculations in sh_eth_ring_init() the practical
3201 * MTU is a bit less. Maybe this can be optimized some more.
3203 ndev
->max_mtu
= 2000 - (ETH_HLEN
+ VLAN_HLEN
+ ETH_FCS_LEN
);
3204 ndev
->min_mtu
= ETH_MIN_MTU
;
3208 ndev
->netdev_ops
= &sh_eth_netdev_ops_tsu
;
3210 ndev
->netdev_ops
= &sh_eth_netdev_ops
;
3211 ndev
->ethtool_ops
= &sh_eth_ethtool_ops
;
3212 ndev
->watchdog_timeo
= TX_TIMEOUT
;
3214 /* debug message level */
3215 mdp
->msg_enable
= SH_ETH_DEF_MSG_ENABLE
;
3217 /* read and set MAC address */
3218 read_mac_address(ndev
, pd
->mac_addr
);
3219 if (!is_valid_ether_addr(ndev
->dev_addr
)) {
3220 dev_warn(&pdev
->dev
,
3221 "no valid MAC address supplied, using a random one.\n");
3222 eth_hw_addr_random(ndev
);
3225 /* ioremap the TSU registers */
3227 struct resource
*rtsu
;
3229 rtsu
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
3231 dev_err(&pdev
->dev
, "no TSU resource\n");
3235 /* We can only request the TSU region for the first port
3236 * of the two sharing this TSU for the probe to succeed...
3238 if (devno
% 2 == 0 &&
3239 !devm_request_mem_region(&pdev
->dev
, rtsu
->start
,
3240 resource_size(rtsu
),
3241 dev_name(&pdev
->dev
))) {
3242 dev_err(&pdev
->dev
, "can't request TSU resource.\n");
3246 mdp
->tsu_addr
= devm_ioremap(&pdev
->dev
, rtsu
->start
,
3247 resource_size(rtsu
));
3248 if (!mdp
->tsu_addr
) {
3249 dev_err(&pdev
->dev
, "TSU region ioremap() failed.\n");
3253 mdp
->port
= devno
% 2;
3254 ndev
->features
= NETIF_F_HW_VLAN_CTAG_FILTER
;
3257 /* Need to init only the first port of the two sharing a TSU */
3258 if (devno
% 2 == 0) {
3259 if (mdp
->cd
->chip_reset
)
3260 mdp
->cd
->chip_reset(ndev
);
3263 /* TSU init (Init only)*/
3264 sh_eth_tsu_init(mdp
);
3268 if (mdp
->cd
->rmiimode
)
3269 sh_eth_write(ndev
, 0x1, RMIIMODE
);
3272 ret
= sh_mdio_init(mdp
, pd
);
3274 if (ret
!= -EPROBE_DEFER
)
3275 dev_err(&pdev
->dev
, "MDIO init failed: %d\n", ret
);
3279 netif_napi_add(ndev
, &mdp
->napi
, sh_eth_poll
, 64);
3281 /* network device register */
3282 ret
= register_netdev(ndev
);
3286 if (mdp
->cd
->magic
&& mdp
->clk
)
3287 device_set_wakeup_capable(&pdev
->dev
, 1);
3289 /* print device information */
3290 netdev_info(ndev
, "Base address at 0x%x, %pM, IRQ %d.\n",
3291 (u32
)ndev
->base_addr
, ndev
->dev_addr
, ndev
->irq
);
3293 pm_runtime_put(&pdev
->dev
);
3294 platform_set_drvdata(pdev
, ndev
);
3299 netif_napi_del(&mdp
->napi
);
3300 sh_mdio_release(mdp
);
3307 pm_runtime_put(&pdev
->dev
);
3308 pm_runtime_disable(&pdev
->dev
);
3312 static int sh_eth_drv_remove(struct platform_device
*pdev
)
3314 struct net_device
*ndev
= platform_get_drvdata(pdev
);
3315 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
3317 unregister_netdev(ndev
);
3318 netif_napi_del(&mdp
->napi
);
3319 sh_mdio_release(mdp
);
3320 pm_runtime_disable(&pdev
->dev
);
3327 #ifdef CONFIG_PM_SLEEP
3328 static int sh_eth_wol_setup(struct net_device
*ndev
)
3330 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
3332 /* Only allow ECI interrupts */
3333 synchronize_irq(ndev
->irq
);
3334 napi_disable(&mdp
->napi
);
3335 sh_eth_write(ndev
, EESIPR_ECIIP
, EESIPR
);
3337 /* Enable MagicPacket */
3338 sh_eth_modify(ndev
, ECMR
, ECMR_MPDE
, ECMR_MPDE
);
3340 /* Increased clock usage so device won't be suspended */
3341 clk_enable(mdp
->clk
);
3343 return enable_irq_wake(ndev
->irq
);
3346 static int sh_eth_wol_restore(struct net_device
*ndev
)
3348 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
3351 napi_enable(&mdp
->napi
);
3353 /* Disable MagicPacket */
3354 sh_eth_modify(ndev
, ECMR
, ECMR_MPDE
, 0);
3356 /* The device needs to be reset to restore MagicPacket logic
3357 * for next wakeup. If we close and open the device it will
3358 * both be reset and all registers restored. This is what
3359 * happens during suspend and resume without WoL enabled.
3361 ret
= sh_eth_close(ndev
);
3364 ret
= sh_eth_open(ndev
);
3368 /* Restore clock usage count */
3369 clk_disable(mdp
->clk
);
3371 return disable_irq_wake(ndev
->irq
);
3374 static int sh_eth_suspend(struct device
*dev
)
3376 struct net_device
*ndev
= dev_get_drvdata(dev
);
3377 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
3380 if (!netif_running(ndev
))
3383 netif_device_detach(ndev
);
3385 if (mdp
->wol_enabled
)
3386 ret
= sh_eth_wol_setup(ndev
);
3388 ret
= sh_eth_close(ndev
);
3393 static int sh_eth_resume(struct device
*dev
)
3395 struct net_device
*ndev
= dev_get_drvdata(dev
);
3396 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
3399 if (!netif_running(ndev
))
3402 if (mdp
->wol_enabled
)
3403 ret
= sh_eth_wol_restore(ndev
);
3405 ret
= sh_eth_open(ndev
);
3410 netif_device_attach(ndev
);
3416 static int sh_eth_runtime_nop(struct device
*dev
)
3418 /* Runtime PM callback shared between ->runtime_suspend()
3419 * and ->runtime_resume(). Simply returns success.
3421 * This driver re-initializes all registers after
3422 * pm_runtime_get_sync() anyway so there is no need
3423 * to save and restore registers here.
3428 static const struct dev_pm_ops sh_eth_dev_pm_ops
= {
3429 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend
, sh_eth_resume
)
3430 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop
, sh_eth_runtime_nop
, NULL
)
3432 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3434 #define SH_ETH_PM_OPS NULL
3437 static const struct platform_device_id sh_eth_id_table
[] = {
3438 { "sh7619-ether", (kernel_ulong_t
)&sh7619_data
},
3439 { "sh771x-ether", (kernel_ulong_t
)&sh771x_data
},
3440 { "sh7724-ether", (kernel_ulong_t
)&sh7724_data
},
3441 { "sh7734-gether", (kernel_ulong_t
)&sh7734_data
},
3442 { "sh7757-ether", (kernel_ulong_t
)&sh7757_data
},
3443 { "sh7757-gether", (kernel_ulong_t
)&sh7757_data_giga
},
3444 { "sh7763-gether", (kernel_ulong_t
)&sh7763_data
},
3447 MODULE_DEVICE_TABLE(platform
, sh_eth_id_table
);
3449 static struct platform_driver sh_eth_driver
= {
3450 .probe
= sh_eth_drv_probe
,
3451 .remove
= sh_eth_drv_remove
,
3452 .id_table
= sh_eth_id_table
,
3455 .pm
= SH_ETH_PM_OPS
,
3456 .of_match_table
= of_match_ptr(sh_eth_match_table
),
3460 module_platform_driver(sh_eth_driver
);
3462 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3463 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3464 MODULE_LICENSE("GPL v2");