drivers/net/ethernet/samsung/sxgbe/sxgbe_desc.h

   1 /* 10G controller driver for Samsung SoCs
   2  *
   3  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * Author: Siva Reddy Kallam <siva.kallam@samsung.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #ifndef __SXGBE_DESC_H__
  13 #define __SXGBE_DESC_H__
  14
  15 #define SXGBE_DESC_SIZE_BYTES   16
  16
  17 /* forward declaration */
  18 struct sxgbe_extra_stats;
  19
  20 /* Transmit checksum insertion control */
  21 enum tdes_csum_insertion {
  22         cic_disabled            = 0,    /* Checksum Insertion Control */
  23         cic_only_ip             = 1,    /* Only IP header */
  24         /* IP header but pseudoheader is not calculated */
  25         cic_no_pseudoheader     = 2,
  26         cic_full                = 3,    /* IP header and pseudoheader */
  27 };
  28
  29 struct sxgbe_tx_norm_desc {
  30         u64 tdes01; /* buf1 address */
  31         union {
  32                 /* TX Read-Format Desc 2,3 */
  33                 struct {
  34                         /* TDES2 */
  35                         u32 buf1_size:14;
  36                         u32 vlan_tag_ctl:2;
  37                         u32 buf2_size:14;
  38                         u32 timestmp_enable:1;
  39                         u32 int_on_com:1;
  40                         /* TDES3 */
  41                         union {
  42                                 u32 tcp_payload_len:18;
  43                                 struct {
  44                                         u32 total_pkt_len:15;
  45                                         u32 reserved1:1;
  46                                         u32 cksum_ctl:2;
  47                                 } cksum_pktlen;
  48                         } tx_pkt_len;
  49
  50                         u32 tse_bit:1;
  51                         u32 tcp_hdr_len:4;
  52                         u32 sa_insert_ctl:3;
  53                         u32 crc_pad_ctl:2;
  54                         u32 last_desc:1;
  55                         u32 first_desc:1;
  56                         u32 ctxt_bit:1;
  57                         u32 own_bit:1;
  58                 } tx_rd_des23;
  59
  60                 /* tx write back Desc 2,3 */
  61                 struct {
  62                         /* WB TES2 */
  63                         u32 reserved1;
  64                         /* WB TES3 */
  65                         u32 reserved2:31;
  66                         u32 own_bit:1;
  67                 } tx_wb_des23;
  68         } tdes23;
  69 };
  70
  71 struct sxgbe_rx_norm_desc {
  72         union {
  73                 u32 rdes0; /* buf1 address */
  74                 struct {
  75                         u32 out_vlan_tag:16;
  76                         u32 in_vlan_tag:16;
  77                 } wb_rx_des0;
  78         } rd_wb_des0;
  79
  80         union {
  81                 u32 rdes1;      /* buf2 address or buf1[63:32] */
  82                 u32 rss_hash;   /* Write-back RX */
  83         } rd_wb_des1;
  84
  85         union {
  86                 /* RX Read format Desc 2,3 */
  87                 struct{
  88                         /* RDES2 */
  89                         u32 buf2_addr;
  90                         /* RDES3 */
  91                         u32 buf2_hi_addr:30;
  92                         u32 int_on_com:1;
  93                         u32 own_bit:1;
  94                 } rx_rd_des23;
  95
  96                 /* RX write back */
  97                 struct{
  98                         /* WB RDES2 */
  99                         u32 hdr_len:10;
 100                         u32 rdes2_reserved:2;
 101                         u32 elrd_val:1;
 102                         u32 iovt_sel:1;
 103                         u32 res_pkt:1;
 104                         u32 vlan_filter_match:1;
 105                         u32 sa_filter_fail:1;
 106                         u32 da_filter_fail:1;
 107                         u32 hash_filter_pass:1;
 108                         u32 macaddr_filter_match:8;
 109                         u32 l3_filter_match:1;
 110                         u32 l4_filter_match:1;
 111                         u32 l34_filter_num:3;
 112
 113                         /* WB RDES3 */
 114                         u32 pkt_len:14;
 115                         u32 rdes3_reserved:1;
 116                         u32 err_summary:1;
 117                         u32 err_l2_type:4;
 118                         u32 layer34_pkt_type:4;
 119                         u32 no_coagulation_pkt:1;
 120                         u32 in_seq_pkt:1;
 121                         u32 rss_valid:1;
 122                         u32 context_des_avail:1;
 123                         u32 last_desc:1;
 124                         u32 first_desc:1;
 125                         u32 recv_context_desc:1;
 126                         u32 own_bit:1;
 127                 } rx_wb_des23;
 128         } rdes23;
 129 };
 130
 131 /* Context descriptor structure */
 132 struct sxgbe_tx_ctxt_desc {
 133         u32 tstamp_lo;
 134         u32 tstamp_hi;
 135         u32 maxseg_size:15;
 136         u32 reserved1:1;
 137         u32 ivlan_tag:16;
 138         u32 vlan_tag:16;
 139         u32 vltag_valid:1;
 140         u32 ivlan_tag_valid:1;
 141         u32 ivlan_tag_ctl:2;
 142         u32 reserved2:3;
 143         u32 ctxt_desc_err:1;
 144         u32 reserved3:2;
 145         u32 ostc:1;
 146         u32 tcmssv:1;
 147         u32 reserved4:2;
 148         u32 ctxt_bit:1;
 149         u32 own_bit:1;
 150 };
 151
 152 struct sxgbe_rx_ctxt_desc {
 153         u32 tstamp_lo;
 154         u32 tstamp_hi;
 155         u32 reserved1;
 156         u32 ptp_msgtype:4;
 157         u32 tstamp_available:1;
 158         u32 ptp_rsp_err:1;
 159         u32 tstamp_dropped:1;
 160         u32 reserved2:23;
 161         u32 rx_ctxt_desc:1;
 162         u32 own_bit:1;
 163 };
 164
 165 struct sxgbe_desc_ops {
 166         /* DMA TX descriptor ring initialization */
 167         void (*init_tx_desc)(struct sxgbe_tx_norm_desc *p);
 168
 169         /* Invoked by the xmit function to prepare the tx descriptor */
 170         void (*tx_desc_enable_tse)(struct sxgbe_tx_norm_desc *p, u8 is_tse,
 171                                    u32 total_hdr_len, u32 tcp_hdr_len,
 172                                    u32 tcp_payload_len);
 173
 174         /* Assign buffer lengths for descriptor */
 175         void (*prepare_tx_desc)(struct sxgbe_tx_norm_desc *p, u8 is_fd,
 176                                 int buf1_len, int pkt_len, int cksum);
 177
 178         /* Set VLAN control information */
 179         void (*tx_vlanctl_desc)(struct sxgbe_tx_norm_desc *p, int vlan_ctl);
 180
 181         /* Set the owner of the descriptor */
 182         void (*set_tx_owner)(struct sxgbe_tx_norm_desc *p);
 183
 184         /* Get the owner of the descriptor */
 185         int (*get_tx_owner)(struct sxgbe_tx_norm_desc *p);
 186
 187         /* Invoked by the xmit function to close the tx descriptor */
 188         void (*close_tx_desc)(struct sxgbe_tx_norm_desc *p);
 189
 190         /* Clean the tx descriptor as soon as the tx irq is received */
 191         void (*release_tx_desc)(struct sxgbe_tx_norm_desc *p);
 192
 193         /* Clear interrupt on tx frame completion. When this bit is
 194          * set an interrupt happens as soon as the frame is transmitted
 195          */
 196         void (*clear_tx_ic)(struct sxgbe_tx_norm_desc *p);
 197
 198         /* Last tx segment reports the transmit status */
 199         int (*get_tx_ls)(struct sxgbe_tx_norm_desc *p);
 200
 201         /* Get the buffer size from the descriptor */
 202         int (*get_tx_len)(struct sxgbe_tx_norm_desc *p);
 203
 204         /* Set tx timestamp enable bit */
 205         void (*tx_enable_tstamp)(struct sxgbe_tx_norm_desc *p);
 206
 207         /* get tx timestamp status */
 208         int (*get_tx_timestamp_status)(struct sxgbe_tx_norm_desc *p);
 209
 210         /* TX Context Descripto Specific */
 211         void (*tx_ctxt_desc_set_ctxt)(struct sxgbe_tx_ctxt_desc *p);
 212
 213         /* Set the owner of the TX context descriptor */
 214         void (*tx_ctxt_desc_set_owner)(struct sxgbe_tx_ctxt_desc *p);
 215
 216         /* Get the owner of the TX context descriptor */
 217         int (*get_tx_ctxt_owner)(struct sxgbe_tx_ctxt_desc *p);
 218
 219         /* Set TX mss */
 220         void (*tx_ctxt_desc_set_mss)(struct sxgbe_tx_ctxt_desc *p, u16 mss);
 221
 222         /* Set TX mss */
 223         int (*tx_ctxt_desc_get_mss)(struct sxgbe_tx_ctxt_desc *p);
 224
 225         /* Set TX tcmssv */
 226         void (*tx_ctxt_desc_set_tcmssv)(struct sxgbe_tx_ctxt_desc *p);
 227
 228         /* Reset TX ostc */
 229         void (*tx_ctxt_desc_reset_ostc)(struct sxgbe_tx_ctxt_desc *p);
 230
 231         /* Set IVLAN information */
 232         void (*tx_ctxt_desc_set_ivlantag)(struct sxgbe_tx_ctxt_desc *p,
 233                                           int is_ivlanvalid, int ivlan_tag,
 234                                           int ivlan_ctl);
 235
 236         /* Return IVLAN Tag */
 237         int (*tx_ctxt_desc_get_ivlantag)(struct sxgbe_tx_ctxt_desc *p);
 238
 239         /* Set VLAN Tag */
 240         void (*tx_ctxt_desc_set_vlantag)(struct sxgbe_tx_ctxt_desc *p,
 241                                          int is_vlanvalid, int vlan_tag);
 242
 243         /* Return VLAN Tag */
 244         int (*tx_ctxt_desc_get_vlantag)(struct sxgbe_tx_ctxt_desc *p);
 245
 246         /* Set Time stamp */
 247         void (*tx_ctxt_set_tstamp)(struct sxgbe_tx_ctxt_desc *p,
 248                                    u8 ostc_enable, u64 tstamp);
 249
 250         /* Close TX context descriptor */
 251         void (*close_tx_ctxt_desc)(struct sxgbe_tx_ctxt_desc *p);
 252
 253         /* WB status of context descriptor */
 254         int (*get_tx_ctxt_cde)(struct sxgbe_tx_ctxt_desc *p);
 255
 256         /* DMA RX descriptor ring initialization */
 257         void (*init_rx_desc)(struct sxgbe_rx_norm_desc *p, int disable_rx_ic,
 258                              int mode, int end);
 259
 260         /* Get own bit */
 261         int (*get_rx_owner)(struct sxgbe_rx_norm_desc *p);
 262
 263         /* Set own bit */
 264         void (*set_rx_owner)(struct sxgbe_rx_norm_desc *p);
 265
 266         /* Get the receive frame size */
 267         int (*get_rx_frame_len)(struct sxgbe_rx_norm_desc *p);
 268
 269         /* Return first Descriptor status */
 270         int (*get_rx_fd_status)(struct sxgbe_rx_norm_desc *p);
 271
 272         /* Return first Descriptor status */
 273         int (*get_rx_ld_status)(struct sxgbe_rx_norm_desc *p);
 274
 275         /* Return the reception status looking at the RDES1 */
 276         int (*rx_wbstatus)(struct sxgbe_rx_norm_desc *p,
 277                            struct sxgbe_extra_stats *x, int *checksum);
 278
 279         /* Get own bit */
 280         int (*get_rx_ctxt_owner)(struct sxgbe_rx_ctxt_desc *p);
 281
 282         /* Set own bit */
 283         void (*set_rx_ctxt_owner)(struct sxgbe_rx_ctxt_desc *p);
 284
 285         /* Return the reception status looking at Context control information */
 286         void (*rx_ctxt_wbstatus)(struct sxgbe_rx_ctxt_desc *p,
 287                                  struct sxgbe_extra_stats *x);
 288
 289         /* Get rx timestamp status */
 290         int (*get_rx_ctxt_tstamp_status)(struct sxgbe_rx_ctxt_desc *p);
 291
 292         /* Get timestamp value for rx, need to check this */
 293         u64 (*get_timestamp)(struct sxgbe_rx_ctxt_desc *p);
 294 };
 295
 296 const struct sxgbe_desc_ops *sxgbe_get_desc_ops(void);
 297
 298 #endif /* __SXGBE_DESC_H__ */