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efi/arm: Fix boot crash with CONFIG_CPUMASK_OFFSTACK=y
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / sfc / ef10.c
1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10 #include "net_driver.h"
11 #include "ef10_regs.h"
12 #include "io.h"
13 #include "mcdi.h"
14 #include "mcdi_pcol.h"
15 #include "nic.h"
16 #include "workarounds.h"
17 #include "selftest.h"
18 #include "ef10_sriov.h"
19 #include <linux/in.h>
20 #include <linux/jhash.h>
21 #include <linux/wait.h>
22 #include <linux/workqueue.h>
23
24 /* Hardware control for EF10 architecture including 'Huntington'. */
25
26 #define EFX_EF10_DRVGEN_EV 7
27 enum {
28 EFX_EF10_TEST = 1,
29 EFX_EF10_REFILL,
30 };
31
32 /* The reserved RSS context value */
33 #define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
34 /* The maximum size of a shared RSS context */
35 /* TODO: this should really be from the mcdi protocol export */
36 #define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
37
38 /* The filter table(s) are managed by firmware and we have write-only
39 * access. When removing filters we must identify them to the
40 * firmware by a 64-bit handle, but this is too wide for Linux kernel
41 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
42 * be able to tell in advance whether a requested insertion will
43 * replace an existing filter. Therefore we maintain a software hash
44 * table, which should be at least as large as the hardware hash
45 * table.
46 *
47 * Huntington has a single 8K filter table shared between all filter
48 * types and both ports.
49 */
50 #define HUNT_FILTER_TBL_ROWS 8192
51
52 #define EFX_EF10_FILTER_ID_INVALID 0xffff
53
54 #define EFX_EF10_FILTER_DEV_UC_MAX 32
55 #define EFX_EF10_FILTER_DEV_MC_MAX 256
56
57 /* VLAN list entry */
58 struct efx_ef10_vlan {
59 struct list_head list;
60 u16 vid;
61 };
62
63 enum efx_ef10_default_filters {
64 EFX_EF10_BCAST,
65 EFX_EF10_UCDEF,
66 EFX_EF10_MCDEF,
67 EFX_EF10_VXLAN4_UCDEF,
68 EFX_EF10_VXLAN4_MCDEF,
69 EFX_EF10_VXLAN6_UCDEF,
70 EFX_EF10_VXLAN6_MCDEF,
71 EFX_EF10_NVGRE4_UCDEF,
72 EFX_EF10_NVGRE4_MCDEF,
73 EFX_EF10_NVGRE6_UCDEF,
74 EFX_EF10_NVGRE6_MCDEF,
75 EFX_EF10_GENEVE4_UCDEF,
76 EFX_EF10_GENEVE4_MCDEF,
77 EFX_EF10_GENEVE6_UCDEF,
78 EFX_EF10_GENEVE6_MCDEF,
79
80 EFX_EF10_NUM_DEFAULT_FILTERS
81 };
82
83 /* Per-VLAN filters information */
84 struct efx_ef10_filter_vlan {
85 struct list_head list;
86 u16 vid;
87 u16 uc[EFX_EF10_FILTER_DEV_UC_MAX];
88 u16 mc[EFX_EF10_FILTER_DEV_MC_MAX];
89 u16 default_filters[EFX_EF10_NUM_DEFAULT_FILTERS];
90 };
91
92 struct efx_ef10_dev_addr {
93 u8 addr[ETH_ALEN];
94 };
95
96 struct efx_ef10_filter_table {
97 /* The MCDI match masks supported by this fw & hw, in order of priority */
98 u32 rx_match_mcdi_flags[
99 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM * 2];
100 unsigned int rx_match_count;
101
102 struct {
103 unsigned long spec; /* pointer to spec plus flag bits */
104 /* BUSY flag indicates that an update is in progress. AUTO_OLD is
105 * used to mark and sweep MAC filters for the device address lists.
106 */
107 #define EFX_EF10_FILTER_FLAG_BUSY 1UL
108 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
109 #define EFX_EF10_FILTER_FLAGS 3UL
110 u64 handle; /* firmware handle */
111 } *entry;
112 wait_queue_head_t waitq;
113 /* Shadow of net_device address lists, guarded by mac_lock */
114 struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX];
115 struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
116 int dev_uc_count;
117 int dev_mc_count;
118 bool uc_promisc;
119 bool mc_promisc;
120 /* Whether in multicast promiscuous mode when last changed */
121 bool mc_promisc_last;
122 bool vlan_filter;
123 struct list_head vlan_list;
124 };
125
126 /* An arbitrary search limit for the software hash table */
127 #define EFX_EF10_FILTER_SEARCH_LIMIT 200
128
129 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
130 static void efx_ef10_filter_table_remove(struct efx_nic *efx);
131 static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid);
132 static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
133 struct efx_ef10_filter_vlan *vlan);
134 static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid);
135 static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading);
136
137 static u32 efx_ef10_filter_get_unsafe_id(u32 filter_id)
138 {
139 WARN_ON_ONCE(filter_id == EFX_EF10_FILTER_ID_INVALID);
140 return filter_id & (HUNT_FILTER_TBL_ROWS - 1);
141 }
142
143 static unsigned int efx_ef10_filter_get_unsafe_pri(u32 filter_id)
144 {
145 return filter_id / (HUNT_FILTER_TBL_ROWS * 2);
146 }
147
148 static u32 efx_ef10_make_filter_id(unsigned int pri, u16 idx)
149 {
150 return pri * HUNT_FILTER_TBL_ROWS * 2 + idx;
151 }
152
153 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
154 {
155 efx_dword_t reg;
156
157 efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
158 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
159 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
160 }
161
162 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
163 {
164 int bar;
165
166 bar = efx->type->mem_bar;
167 return resource_size(&efx->pci_dev->resource[bar]);
168 }
169
170 static bool efx_ef10_is_vf(struct efx_nic *efx)
171 {
172 return efx->type->is_vf;
173 }
174
175 static int efx_ef10_get_pf_index(struct efx_nic *efx)
176 {
177 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
178 struct efx_ef10_nic_data *nic_data = efx->nic_data;
179 size_t outlen;
180 int rc;
181
182 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
183 sizeof(outbuf), &outlen);
184 if (rc)
185 return rc;
186 if (outlen < sizeof(outbuf))
187 return -EIO;
188
189 nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
190 return 0;
191 }
192
193 #ifdef CONFIG_SFC_SRIOV
194 static int efx_ef10_get_vf_index(struct efx_nic *efx)
195 {
196 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
197 struct efx_ef10_nic_data *nic_data = efx->nic_data;
198 size_t outlen;
199 int rc;
200
201 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
202 sizeof(outbuf), &outlen);
203 if (rc)
204 return rc;
205 if (outlen < sizeof(outbuf))
206 return -EIO;
207
208 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
209 return 0;
210 }
211 #endif
212
213 static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
214 {
215 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V2_OUT_LEN);
216 struct efx_ef10_nic_data *nic_data = efx->nic_data;
217 size_t outlen;
218 int rc;
219
220 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
221
222 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
223 outbuf, sizeof(outbuf), &outlen);
224 if (rc)
225 return rc;
226 if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
227 netif_err(efx, drv, efx->net_dev,
228 "unable to read datapath firmware capabilities\n");
229 return -EIO;
230 }
231
232 nic_data->datapath_caps =
233 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
234
235 if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) {
236 nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
237 GET_CAPABILITIES_V2_OUT_FLAGS2);
238 nic_data->piobuf_size = MCDI_WORD(outbuf,
239 GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF);
240 } else {
241 nic_data->datapath_caps2 = 0;
242 nic_data->piobuf_size = ER_DZ_TX_PIOBUF_SIZE;
243 }
244
245 /* record the DPCPU firmware IDs to determine VEB vswitching support.
246 */
247 nic_data->rx_dpcpu_fw_id =
248 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
249 nic_data->tx_dpcpu_fw_id =
250 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
251
252 if (!(nic_data->datapath_caps &
253 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
254 netif_err(efx, probe, efx->net_dev,
255 "current firmware does not support an RX prefix\n");
256 return -ENODEV;
257 }
258
259 return 0;
260 }
261
262 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
263 {
264 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
265 int rc;
266
267 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
268 outbuf, sizeof(outbuf), NULL);
269 if (rc)
270 return rc;
271 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
272 return rc > 0 ? rc : -ERANGE;
273 }
274
275 static int efx_ef10_get_timer_workarounds(struct efx_nic *efx)
276 {
277 struct efx_ef10_nic_data *nic_data = efx->nic_data;
278 unsigned int implemented;
279 unsigned int enabled;
280 int rc;
281
282 nic_data->workaround_35388 = false;
283 nic_data->workaround_61265 = false;
284
285 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
286
287 if (rc == -ENOSYS) {
288 /* Firmware without GET_WORKAROUNDS - not a problem. */
289 rc = 0;
290 } else if (rc == 0) {
291 /* Bug61265 workaround is always enabled if implemented. */
292 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG61265)
293 nic_data->workaround_61265 = true;
294
295 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
296 nic_data->workaround_35388 = true;
297 } else if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
298 /* Workaround is implemented but not enabled.
299 * Try to enable it.
300 */
301 rc = efx_mcdi_set_workaround(efx,
302 MC_CMD_WORKAROUND_BUG35388,
303 true, NULL);
304 if (rc == 0)
305 nic_data->workaround_35388 = true;
306 /* If we failed to set the workaround just carry on. */
307 rc = 0;
308 }
309 }
310
311 netif_dbg(efx, probe, efx->net_dev,
312 "workaround for bug 35388 is %sabled\n",
313 nic_data->workaround_35388 ? "en" : "dis");
314 netif_dbg(efx, probe, efx->net_dev,
315 "workaround for bug 61265 is %sabled\n",
316 nic_data->workaround_61265 ? "en" : "dis");
317
318 return rc;
319 }
320
321 static void efx_ef10_process_timer_config(struct efx_nic *efx,
322 const efx_dword_t *data)
323 {
324 unsigned int max_count;
325
326 if (EFX_EF10_WORKAROUND_61265(efx)) {
327 efx->timer_quantum_ns = MCDI_DWORD(data,
328 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS);
329 efx->timer_max_ns = MCDI_DWORD(data,
330 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS);
331 } else if (EFX_EF10_WORKAROUND_35388(efx)) {
332 efx->timer_quantum_ns = MCDI_DWORD(data,
333 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT);
334 max_count = MCDI_DWORD(data,
335 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT);
336 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
337 } else {
338 efx->timer_quantum_ns = MCDI_DWORD(data,
339 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT);
340 max_count = MCDI_DWORD(data,
341 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT);
342 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
343 }
344
345 netif_dbg(efx, probe, efx->net_dev,
346 "got timer properties from MC: quantum %u ns; max %u ns\n",
347 efx->timer_quantum_ns, efx->timer_max_ns);
348 }
349
350 static int efx_ef10_get_timer_config(struct efx_nic *efx)
351 {
352 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN);
353 int rc;
354
355 rc = efx_ef10_get_timer_workarounds(efx);
356 if (rc)
357 return rc;
358
359 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, NULL, 0,
360 outbuf, sizeof(outbuf), NULL);
361
362 if (rc == 0) {
363 efx_ef10_process_timer_config(efx, outbuf);
364 } else if (rc == -ENOSYS || rc == -EPERM) {
365 /* Not available - fall back to Huntington defaults. */
366 unsigned int quantum;
367
368 rc = efx_ef10_get_sysclk_freq(efx);
369 if (rc < 0)
370 return rc;
371
372 quantum = 1536000 / rc; /* 1536 cycles */
373 efx->timer_quantum_ns = quantum;
374 efx->timer_max_ns = efx->type->timer_period_max * quantum;
375 rc = 0;
376 } else {
377 efx_mcdi_display_error(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES,
378 MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN,
379 NULL, 0, rc);
380 }
381
382 return rc;
383 }
384
385 static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
386 {
387 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
388 size_t outlen;
389 int rc;
390
391 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
392
393 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
394 outbuf, sizeof(outbuf), &outlen);
395 if (rc)
396 return rc;
397 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
398 return -EIO;
399
400 ether_addr_copy(mac_address,
401 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
402 return 0;
403 }
404
405 static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
406 {
407 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
408 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
409 size_t outlen;
410 int num_addrs, rc;
411
412 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
413 EVB_PORT_ID_ASSIGNED);
414 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
415 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
416
417 if (rc)
418 return rc;
419 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
420 return -EIO;
421
422 num_addrs = MCDI_DWORD(outbuf,
423 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
424
425 WARN_ON(num_addrs != 1);
426
427 ether_addr_copy(mac_address,
428 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
429
430 return 0;
431 }
432
433 static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
434 struct device_attribute *attr,
435 char *buf)
436 {
437 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
438
439 return sprintf(buf, "%d\n",
440 ((efx->mcdi->fn_flags) &
441 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
442 ? 1 : 0);
443 }
444
445 static ssize_t efx_ef10_show_primary_flag(struct device *dev,
446 struct device_attribute *attr,
447 char *buf)
448 {
449 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
450
451 return sprintf(buf, "%d\n",
452 ((efx->mcdi->fn_flags) &
453 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
454 ? 1 : 0);
455 }
456
457 static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid)
458 {
459 struct efx_ef10_nic_data *nic_data = efx->nic_data;
460 struct efx_ef10_vlan *vlan;
461
462 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
463
464 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
465 if (vlan->vid == vid)
466 return vlan;
467 }
468
469 return NULL;
470 }
471
472 static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid)
473 {
474 struct efx_ef10_nic_data *nic_data = efx->nic_data;
475 struct efx_ef10_vlan *vlan;
476 int rc;
477
478 mutex_lock(&nic_data->vlan_lock);
479
480 vlan = efx_ef10_find_vlan(efx, vid);
481 if (vlan) {
482 /* We add VID 0 on init. 8021q adds it on module init
483 * for all interfaces with VLAN filtring feature.
484 */
485 if (vid == 0)
486 goto done_unlock;
487 netif_warn(efx, drv, efx->net_dev,
488 "VLAN %u already added\n", vid);
489 rc = -EALREADY;
490 goto fail_exist;
491 }
492
493 rc = -ENOMEM;
494 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
495 if (!vlan)
496 goto fail_alloc;
497
498 vlan->vid = vid;
499
500 list_add_tail(&vlan->list, &nic_data->vlan_list);
501
502 if (efx->filter_state) {
503 mutex_lock(&efx->mac_lock);
504 down_write(&efx->filter_sem);
505 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
506 up_write(&efx->filter_sem);
507 mutex_unlock(&efx->mac_lock);
508 if (rc)
509 goto fail_filter_add_vlan;
510 }
511
512 done_unlock:
513 mutex_unlock(&nic_data->vlan_lock);
514 return 0;
515
516 fail_filter_add_vlan:
517 list_del(&vlan->list);
518 kfree(vlan);
519 fail_alloc:
520 fail_exist:
521 mutex_unlock(&nic_data->vlan_lock);
522 return rc;
523 }
524
525 static void efx_ef10_del_vlan_internal(struct efx_nic *efx,
526 struct efx_ef10_vlan *vlan)
527 {
528 struct efx_ef10_nic_data *nic_data = efx->nic_data;
529
530 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
531
532 if (efx->filter_state) {
533 down_write(&efx->filter_sem);
534 efx_ef10_filter_del_vlan(efx, vlan->vid);
535 up_write(&efx->filter_sem);
536 }
537
538 list_del(&vlan->list);
539 kfree(vlan);
540 }
541
542 static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid)
543 {
544 struct efx_ef10_nic_data *nic_data = efx->nic_data;
545 struct efx_ef10_vlan *vlan;
546 int rc = 0;
547
548 /* 8021q removes VID 0 on module unload for all interfaces
549 * with VLAN filtering feature. We need to keep it to receive
550 * untagged traffic.
551 */
552 if (vid == 0)
553 return 0;
554
555 mutex_lock(&nic_data->vlan_lock);
556
557 vlan = efx_ef10_find_vlan(efx, vid);
558 if (!vlan) {
559 netif_err(efx, drv, efx->net_dev,
560 "VLAN %u to be deleted not found\n", vid);
561 rc = -ENOENT;
562 } else {
563 efx_ef10_del_vlan_internal(efx, vlan);
564 }
565
566 mutex_unlock(&nic_data->vlan_lock);
567
568 return rc;
569 }
570
571 static void efx_ef10_cleanup_vlans(struct efx_nic *efx)
572 {
573 struct efx_ef10_nic_data *nic_data = efx->nic_data;
574 struct efx_ef10_vlan *vlan, *next_vlan;
575
576 mutex_lock(&nic_data->vlan_lock);
577 list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list)
578 efx_ef10_del_vlan_internal(efx, vlan);
579 mutex_unlock(&nic_data->vlan_lock);
580 }
581
582 static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
583 NULL);
584 static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
585
586 static int efx_ef10_probe(struct efx_nic *efx)
587 {
588 struct efx_ef10_nic_data *nic_data;
589 int i, rc;
590
591 /* We can have one VI for each 8K region. However, until we
592 * use TX option descriptors we need two TX queues per channel.
593 */
594 efx->max_channels = min_t(unsigned int,
595 EFX_MAX_CHANNELS,
596 efx_ef10_mem_map_size(efx) /
597 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
598 efx->max_tx_channels = efx->max_channels;
599 if (WARN_ON(efx->max_channels == 0))
600 return -EIO;
601
602 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
603 if (!nic_data)
604 return -ENOMEM;
605 efx->nic_data = nic_data;
606
607 /* we assume later that we can copy from this buffer in dwords */
608 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
609
610 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
611 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
612 if (rc)
613 goto fail1;
614
615 /* Get the MC's warm boot count. In case it's rebooting right
616 * now, be prepared to retry.
617 */
618 i = 0;
619 for (;;) {
620 rc = efx_ef10_get_warm_boot_count(efx);
621 if (rc >= 0)
622 break;
623 if (++i == 5)
624 goto fail2;
625 ssleep(1);
626 }
627 nic_data->warm_boot_count = rc;
628
629 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
630
631 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
632
633 /* In case we're recovering from a crash (kexec), we want to
634 * cancel any outstanding request by the previous user of this
635 * function. We send a special message using the least
636 * significant bits of the 'high' (doorbell) register.
637 */
638 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
639
640 rc = efx_mcdi_init(efx);
641 if (rc)
642 goto fail2;
643
644 mutex_init(&nic_data->udp_tunnels_lock);
645
646 /* Reset (most) configuration for this function */
647 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
648 if (rc)
649 goto fail3;
650
651 /* Enable event logging */
652 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
653 if (rc)
654 goto fail3;
655
656 rc = device_create_file(&efx->pci_dev->dev,
657 &dev_attr_link_control_flag);
658 if (rc)
659 goto fail3;
660
661 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
662 if (rc)
663 goto fail4;
664
665 rc = efx_ef10_get_pf_index(efx);
666 if (rc)
667 goto fail5;
668
669 rc = efx_ef10_init_datapath_caps(efx);
670 if (rc < 0)
671 goto fail5;
672
673 efx->rx_packet_len_offset =
674 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
675
676 rc = efx_mcdi_port_get_number(efx);
677 if (rc < 0)
678 goto fail5;
679 efx->port_num = rc;
680
681 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
682 if (rc)
683 goto fail5;
684
685 rc = efx_ef10_get_timer_config(efx);
686 if (rc < 0)
687 goto fail5;
688
689 rc = efx_mcdi_mon_probe(efx);
690 if (rc && rc != -EPERM)
691 goto fail5;
692
693 efx_ptp_probe(efx, NULL);
694
695 #ifdef CONFIG_SFC_SRIOV
696 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
697 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
698 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
699
700 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
701 } else
702 #endif
703 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
704
705 INIT_LIST_HEAD(&nic_data->vlan_list);
706 mutex_init(&nic_data->vlan_lock);
707
708 /* Add unspecified VID to support VLAN filtering being disabled */
709 rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
710 if (rc)
711 goto fail_add_vid_unspec;
712
713 /* If VLAN filtering is enabled, we need VID 0 to get untagged
714 * traffic. It is added automatically if 8021q module is loaded,
715 * but we can't rely on it since module may be not loaded.
716 */
717 rc = efx_ef10_add_vlan(efx, 0);
718 if (rc)
719 goto fail_add_vid_0;
720
721 return 0;
722
723 fail_add_vid_0:
724 efx_ef10_cleanup_vlans(efx);
725 fail_add_vid_unspec:
726 mutex_destroy(&nic_data->vlan_lock);
727 efx_ptp_remove(efx);
728 efx_mcdi_mon_remove(efx);
729 fail5:
730 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
731 fail4:
732 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
733 fail3:
734 efx_mcdi_detach(efx);
735
736 mutex_lock(&nic_data->udp_tunnels_lock);
737 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels));
738 (void)efx_ef10_set_udp_tnl_ports(efx, true);
739 mutex_unlock(&nic_data->udp_tunnels_lock);
740 mutex_destroy(&nic_data->udp_tunnels_lock);
741
742 efx_mcdi_fini(efx);
743 fail2:
744 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
745 fail1:
746 kfree(nic_data);
747 efx->nic_data = NULL;
748 return rc;
749 }
750
751 static int efx_ef10_free_vis(struct efx_nic *efx)
752 {
753 MCDI_DECLARE_BUF_ERR(outbuf);
754 size_t outlen;
755 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
756 outbuf, sizeof(outbuf), &outlen);
757
758 /* -EALREADY means nothing to free, so ignore */
759 if (rc == -EALREADY)
760 rc = 0;
761 if (rc)
762 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
763 rc);
764 return rc;
765 }
766
767 #ifdef EFX_USE_PIO
768
769 static void efx_ef10_free_piobufs(struct efx_nic *efx)
770 {
771 struct efx_ef10_nic_data *nic_data = efx->nic_data;
772 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
773 unsigned int i;
774 int rc;
775
776 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
777
778 for (i = 0; i < nic_data->n_piobufs; i++) {
779 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
780 nic_data->piobuf_handle[i]);
781 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
782 NULL, 0, NULL);
783 WARN_ON(rc);
784 }
785
786 nic_data->n_piobufs = 0;
787 }
788
789 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
790 {
791 struct efx_ef10_nic_data *nic_data = efx->nic_data;
792 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
793 unsigned int i;
794 size_t outlen;
795 int rc = 0;
796
797 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
798
799 for (i = 0; i < n; i++) {
800 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
801 outbuf, sizeof(outbuf), &outlen);
802 if (rc) {
803 /* Don't display the MC error if we didn't have space
804 * for a VF.
805 */
806 if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC))
807 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF,
808 0, outbuf, outlen, rc);
809 break;
810 }
811 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
812 rc = -EIO;
813 break;
814 }
815 nic_data->piobuf_handle[i] =
816 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
817 netif_dbg(efx, probe, efx->net_dev,
818 "allocated PIO buffer %u handle %x\n", i,
819 nic_data->piobuf_handle[i]);
820 }
821
822 nic_data->n_piobufs = i;
823 if (rc)
824 efx_ef10_free_piobufs(efx);
825 return rc;
826 }
827
828 static int efx_ef10_link_piobufs(struct efx_nic *efx)
829 {
830 struct efx_ef10_nic_data *nic_data = efx->nic_data;
831 _MCDI_DECLARE_BUF(inbuf,
832 max(MC_CMD_LINK_PIOBUF_IN_LEN,
833 MC_CMD_UNLINK_PIOBUF_IN_LEN));
834 struct efx_channel *channel;
835 struct efx_tx_queue *tx_queue;
836 unsigned int offset, index;
837 int rc;
838
839 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
840 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
841
842 memset(inbuf, 0, sizeof(inbuf));
843
844 /* Link a buffer to each VI in the write-combining mapping */
845 for (index = 0; index < nic_data->n_piobufs; ++index) {
846 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
847 nic_data->piobuf_handle[index]);
848 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
849 nic_data->pio_write_vi_base + index);
850 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
851 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
852 NULL, 0, NULL);
853 if (rc) {
854 netif_err(efx, drv, efx->net_dev,
855 "failed to link VI %u to PIO buffer %u (%d)\n",
856 nic_data->pio_write_vi_base + index, index,
857 rc);
858 goto fail;
859 }
860 netif_dbg(efx, probe, efx->net_dev,
861 "linked VI %u to PIO buffer %u\n",
862 nic_data->pio_write_vi_base + index, index);
863 }
864
865 /* Link a buffer to each TX queue */
866 efx_for_each_channel(channel, efx) {
867 efx_for_each_channel_tx_queue(tx_queue, channel) {
868 /* We assign the PIO buffers to queues in
869 * reverse order to allow for the following
870 * special case.
871 */
872 offset = ((efx->tx_channel_offset + efx->n_tx_channels -
873 tx_queue->channel->channel - 1) *
874 efx_piobuf_size);
875 index = offset / nic_data->piobuf_size;
876 offset = offset % nic_data->piobuf_size;
877
878 /* When the host page size is 4K, the first
879 * host page in the WC mapping may be within
880 * the same VI page as the last TX queue. We
881 * can only link one buffer to each VI.
882 */
883 if (tx_queue->queue == nic_data->pio_write_vi_base) {
884 BUG_ON(index != 0);
885 rc = 0;
886 } else {
887 MCDI_SET_DWORD(inbuf,
888 LINK_PIOBUF_IN_PIOBUF_HANDLE,
889 nic_data->piobuf_handle[index]);
890 MCDI_SET_DWORD(inbuf,
891 LINK_PIOBUF_IN_TXQ_INSTANCE,
892 tx_queue->queue);
893 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
894 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
895 NULL, 0, NULL);
896 }
897
898 if (rc) {
899 /* This is non-fatal; the TX path just
900 * won't use PIO for this queue
901 */
902 netif_err(efx, drv, efx->net_dev,
903 "failed to link VI %u to PIO buffer %u (%d)\n",
904 tx_queue->queue, index, rc);
905 tx_queue->piobuf = NULL;
906 } else {
907 tx_queue->piobuf =
908 nic_data->pio_write_base +
909 index * EFX_VI_PAGE_SIZE + offset;
910 tx_queue->piobuf_offset = offset;
911 netif_dbg(efx, probe, efx->net_dev,
912 "linked VI %u to PIO buffer %u offset %x addr %p\n",
913 tx_queue->queue, index,
914 tx_queue->piobuf_offset,
915 tx_queue->piobuf);
916 }
917 }
918 }
919
920 return 0;
921
922 fail:
923 while (index--) {
924 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
925 nic_data->pio_write_vi_base + index);
926 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
927 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
928 NULL, 0, NULL);
929 }
930 return rc;
931 }
932
933 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
934 {
935 struct efx_channel *channel;
936 struct efx_tx_queue *tx_queue;
937
938 /* All our existing PIO buffers went away */
939 efx_for_each_channel(channel, efx)
940 efx_for_each_channel_tx_queue(tx_queue, channel)
941 tx_queue->piobuf = NULL;
942 }
943
944 #else /* !EFX_USE_PIO */
945
946 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
947 {
948 return n == 0 ? 0 : -ENOBUFS;
949 }
950
951 static int efx_ef10_link_piobufs(struct efx_nic *efx)
952 {
953 return 0;
954 }
955
956 static void efx_ef10_free_piobufs(struct efx_nic *efx)
957 {
958 }
959
960 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
961 {
962 }
963
964 #endif /* EFX_USE_PIO */
965
966 static void efx_ef10_remove(struct efx_nic *efx)
967 {
968 struct efx_ef10_nic_data *nic_data = efx->nic_data;
969 int rc;
970
971 #ifdef CONFIG_SFC_SRIOV
972 struct efx_ef10_nic_data *nic_data_pf;
973 struct pci_dev *pci_dev_pf;
974 struct efx_nic *efx_pf;
975 struct ef10_vf *vf;
976
977 if (efx->pci_dev->is_virtfn) {
978 pci_dev_pf = efx->pci_dev->physfn;
979 if (pci_dev_pf) {
980 efx_pf = pci_get_drvdata(pci_dev_pf);
981 nic_data_pf = efx_pf->nic_data;
982 vf = nic_data_pf->vf + nic_data->vf_index;
983 vf->efx = NULL;
984 } else
985 netif_info(efx, drv, efx->net_dev,
986 "Could not get the PF id from VF\n");
987 }
988 #endif
989
990 efx_ef10_cleanup_vlans(efx);
991 mutex_destroy(&nic_data->vlan_lock);
992
993 efx_ptp_remove(efx);
994
995 efx_mcdi_mon_remove(efx);
996
997 efx_ef10_rx_free_indir_table(efx);
998
999 if (nic_data->wc_membase)
1000 iounmap(nic_data->wc_membase);
1001
1002 rc = efx_ef10_free_vis(efx);
1003 WARN_ON(rc != 0);
1004
1005 if (!nic_data->must_restore_piobufs)
1006 efx_ef10_free_piobufs(efx);
1007
1008 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
1009 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
1010
1011 efx_mcdi_detach(efx);
1012
1013 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels));
1014 mutex_lock(&nic_data->udp_tunnels_lock);
1015 (void)efx_ef10_set_udp_tnl_ports(efx, true);
1016 mutex_unlock(&nic_data->udp_tunnels_lock);
1017
1018 mutex_destroy(&nic_data->udp_tunnels_lock);
1019
1020 efx_mcdi_fini(efx);
1021 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
1022 kfree(nic_data);
1023 }
1024
1025 static int efx_ef10_probe_pf(struct efx_nic *efx)
1026 {
1027 return efx_ef10_probe(efx);
1028 }
1029
1030 int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id,
1031 u32 *port_flags, u32 *vadaptor_flags,
1032 unsigned int *vlan_tags)
1033 {
1034 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1035 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN);
1036 MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN);
1037 size_t outlen;
1038 int rc;
1039
1040 if (nic_data->datapath_caps &
1041 (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) {
1042 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID,
1043 port_id);
1044
1045 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf),
1046 outbuf, sizeof(outbuf), &outlen);
1047 if (rc)
1048 return rc;
1049
1050 if (outlen < sizeof(outbuf)) {
1051 rc = -EIO;
1052 return rc;
1053 }
1054 }
1055
1056 if (port_flags)
1057 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS);
1058 if (vadaptor_flags)
1059 *vadaptor_flags =
1060 MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS);
1061 if (vlan_tags)
1062 *vlan_tags =
1063 MCDI_DWORD(outbuf,
1064 VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS);
1065
1066 return 0;
1067 }
1068
1069 int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
1070 {
1071 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
1072
1073 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
1074 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
1075 NULL, 0, NULL);
1076 }
1077
1078 int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
1079 {
1080 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
1081
1082 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
1083 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
1084 NULL, 0, NULL);
1085 }
1086
1087 int efx_ef10_vport_add_mac(struct efx_nic *efx,
1088 unsigned int port_id, u8 *mac)
1089 {
1090 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
1091
1092 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
1093 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
1094
1095 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
1096 sizeof(inbuf), NULL, 0, NULL);
1097 }
1098
1099 int efx_ef10_vport_del_mac(struct efx_nic *efx,
1100 unsigned int port_id, u8 *mac)
1101 {
1102 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
1103
1104 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
1105 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
1106
1107 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
1108 sizeof(inbuf), NULL, 0, NULL);
1109 }
1110
1111 #ifdef CONFIG_SFC_SRIOV
1112 static int efx_ef10_probe_vf(struct efx_nic *efx)
1113 {
1114 int rc;
1115 struct pci_dev *pci_dev_pf;
1116
1117 /* If the parent PF has no VF data structure, it doesn't know about this
1118 * VF so fail probe. The VF needs to be re-created. This can happen
1119 * if the PF driver is unloaded while the VF is assigned to a guest.
1120 */
1121 pci_dev_pf = efx->pci_dev->physfn;
1122 if (pci_dev_pf) {
1123 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
1124 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
1125
1126 if (!nic_data_pf->vf) {
1127 netif_info(efx, drv, efx->net_dev,
1128 "The VF cannot link to its parent PF; "
1129 "please destroy and re-create the VF\n");
1130 return -EBUSY;
1131 }
1132 }
1133
1134 rc = efx_ef10_probe(efx);
1135 if (rc)
1136 return rc;
1137
1138 rc = efx_ef10_get_vf_index(efx);
1139 if (rc)
1140 goto fail;
1141
1142 if (efx->pci_dev->is_virtfn) {
1143 if (efx->pci_dev->physfn) {
1144 struct efx_nic *efx_pf =
1145 pci_get_drvdata(efx->pci_dev->physfn);
1146 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
1147 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1148
1149 nic_data_p->vf[nic_data->vf_index].efx = efx;
1150 nic_data_p->vf[nic_data->vf_index].pci_dev =
1151 efx->pci_dev;
1152 } else
1153 netif_info(efx, drv, efx->net_dev,
1154 "Could not get the PF id from VF\n");
1155 }
1156
1157 return 0;
1158
1159 fail:
1160 efx_ef10_remove(efx);
1161 return rc;
1162 }
1163 #else
1164 static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
1165 {
1166 return 0;
1167 }
1168 #endif
1169
1170 static int efx_ef10_alloc_vis(struct efx_nic *efx,
1171 unsigned int min_vis, unsigned int max_vis)
1172 {
1173 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
1174 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
1175 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1176 size_t outlen;
1177 int rc;
1178
1179 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
1180 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
1181 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
1182 outbuf, sizeof(outbuf), &outlen);
1183 if (rc != 0)
1184 return rc;
1185
1186 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
1187 return -EIO;
1188
1189 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
1190 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
1191
1192 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
1193 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
1194 return 0;
1195 }
1196
1197 /* Note that the failure path of this function does not free
1198 * resources, as this will be done by efx_ef10_remove().
1199 */
1200 static int efx_ef10_dimension_resources(struct efx_nic *efx)
1201 {
1202 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1203 unsigned int uc_mem_map_size, wc_mem_map_size;
1204 unsigned int min_vis = max(EFX_TXQ_TYPES,
1205 efx_separate_tx_channels ? 2 : 1);
1206 unsigned int channel_vis, pio_write_vi_base, max_vis;
1207 void __iomem *membase;
1208 int rc;
1209
1210 channel_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
1211
1212 #ifdef EFX_USE_PIO
1213 /* Try to allocate PIO buffers if wanted and if the full
1214 * number of PIO buffers would be sufficient to allocate one
1215 * copy-buffer per TX channel. Failure is non-fatal, as there
1216 * are only a small number of PIO buffers shared between all
1217 * functions of the controller.
1218 */
1219 if (efx_piobuf_size != 0 &&
1220 nic_data->piobuf_size / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
1221 efx->n_tx_channels) {
1222 unsigned int n_piobufs =
1223 DIV_ROUND_UP(efx->n_tx_channels,
1224 nic_data->piobuf_size / efx_piobuf_size);
1225
1226 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
1227 if (rc == -ENOSPC)
1228 netif_dbg(efx, probe, efx->net_dev,
1229 "out of PIO buffers; cannot allocate more\n");
1230 else if (rc == -EPERM)
1231 netif_dbg(efx, probe, efx->net_dev,
1232 "not permitted to allocate PIO buffers\n");
1233 else if (rc)
1234 netif_err(efx, probe, efx->net_dev,
1235 "failed to allocate PIO buffers (%d)\n", rc);
1236 else
1237 netif_dbg(efx, probe, efx->net_dev,
1238 "allocated %u PIO buffers\n", n_piobufs);
1239 }
1240 #else
1241 nic_data->n_piobufs = 0;
1242 #endif
1243
1244 /* PIO buffers should be mapped with write-combining enabled,
1245 * and we want to make single UC and WC mappings rather than
1246 * several of each (in fact that's the only option if host
1247 * page size is >4K). So we may allocate some extra VIs just
1248 * for writing PIO buffers through.
1249 *
1250 * The UC mapping contains (channel_vis - 1) complete VIs and the
1251 * first half of the next VI. Then the WC mapping begins with
1252 * the second half of this last VI.
1253 */
1254 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * EFX_VI_PAGE_SIZE +
1255 ER_DZ_TX_PIOBUF);
1256 if (nic_data->n_piobufs) {
1257 /* pio_write_vi_base rounds down to give the number of complete
1258 * VIs inside the UC mapping.
1259 */
1260 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
1261 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
1262 nic_data->n_piobufs) *
1263 EFX_VI_PAGE_SIZE) -
1264 uc_mem_map_size);
1265 max_vis = pio_write_vi_base + nic_data->n_piobufs;
1266 } else {
1267 pio_write_vi_base = 0;
1268 wc_mem_map_size = 0;
1269 max_vis = channel_vis;
1270 }
1271
1272 /* In case the last attached driver failed to free VIs, do it now */
1273 rc = efx_ef10_free_vis(efx);
1274 if (rc != 0)
1275 return rc;
1276
1277 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
1278 if (rc != 0)
1279 return rc;
1280
1281 if (nic_data->n_allocated_vis < channel_vis) {
1282 netif_info(efx, drv, efx->net_dev,
1283 "Could not allocate enough VIs to satisfy RSS"
1284 " requirements. Performance may not be optimal.\n");
1285 /* We didn't get the VIs to populate our channels.
1286 * We could keep what we got but then we'd have more
1287 * interrupts than we need.
1288 * Instead calculate new max_channels and restart
1289 */
1290 efx->max_channels = nic_data->n_allocated_vis;
1291 efx->max_tx_channels =
1292 nic_data->n_allocated_vis / EFX_TXQ_TYPES;
1293
1294 efx_ef10_free_vis(efx);
1295 return -EAGAIN;
1296 }
1297
1298 /* If we didn't get enough VIs to map all the PIO buffers, free the
1299 * PIO buffers
1300 */
1301 if (nic_data->n_piobufs &&
1302 nic_data->n_allocated_vis <
1303 pio_write_vi_base + nic_data->n_piobufs) {
1304 netif_dbg(efx, probe, efx->net_dev,
1305 "%u VIs are not sufficient to map %u PIO buffers\n",
1306 nic_data->n_allocated_vis, nic_data->n_piobufs);
1307 efx_ef10_free_piobufs(efx);
1308 }
1309
1310 /* Shrink the original UC mapping of the memory BAR */
1311 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
1312 if (!membase) {
1313 netif_err(efx, probe, efx->net_dev,
1314 "could not shrink memory BAR to %x\n",
1315 uc_mem_map_size);
1316 return -ENOMEM;
1317 }
1318 iounmap(efx->membase);
1319 efx->membase = membase;
1320
1321 /* Set up the WC mapping if needed */
1322 if (wc_mem_map_size) {
1323 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
1324 uc_mem_map_size,
1325 wc_mem_map_size);
1326 if (!nic_data->wc_membase) {
1327 netif_err(efx, probe, efx->net_dev,
1328 "could not allocate WC mapping of size %x\n",
1329 wc_mem_map_size);
1330 return -ENOMEM;
1331 }
1332 nic_data->pio_write_vi_base = pio_write_vi_base;
1333 nic_data->pio_write_base =
1334 nic_data->wc_membase +
1335 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
1336 uc_mem_map_size);
1337
1338 rc = efx_ef10_link_piobufs(efx);
1339 if (rc)
1340 efx_ef10_free_piobufs(efx);
1341 }
1342
1343 netif_dbg(efx, probe, efx->net_dev,
1344 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
1345 &efx->membase_phys, efx->membase, uc_mem_map_size,
1346 nic_data->wc_membase, wc_mem_map_size);
1347
1348 return 0;
1349 }
1350
1351 static int efx_ef10_init_nic(struct efx_nic *efx)
1352 {
1353 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1354 int rc;
1355
1356 if (nic_data->must_check_datapath_caps) {
1357 rc = efx_ef10_init_datapath_caps(efx);
1358 if (rc)
1359 return rc;
1360 nic_data->must_check_datapath_caps = false;
1361 }
1362
1363 if (nic_data->must_realloc_vis) {
1364 /* We cannot let the number of VIs change now */
1365 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
1366 nic_data->n_allocated_vis);
1367 if (rc)
1368 return rc;
1369 nic_data->must_realloc_vis = false;
1370 }
1371
1372 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
1373 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
1374 if (rc == 0) {
1375 rc = efx_ef10_link_piobufs(efx);
1376 if (rc)
1377 efx_ef10_free_piobufs(efx);
1378 }
1379
1380 /* Log an error on failure, but this is non-fatal.
1381 * Permission errors are less important - we've presumably
1382 * had the PIO buffer licence removed.
1383 */
1384 if (rc == -EPERM)
1385 netif_dbg(efx, drv, efx->net_dev,
1386 "not permitted to restore PIO buffers\n");
1387 else if (rc)
1388 netif_err(efx, drv, efx->net_dev,
1389 "failed to restore PIO buffers (%d)\n", rc);
1390 nic_data->must_restore_piobufs = false;
1391 }
1392
1393 /* don't fail init if RSS setup doesn't work */
1394 rc = efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table, NULL);
1395 efx->rss_active = (rc == 0);
1396
1397 return 0;
1398 }
1399
1400 static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
1401 {
1402 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1403 #ifdef CONFIG_SFC_SRIOV
1404 unsigned int i;
1405 #endif
1406
1407 /* All our allocations have been reset */
1408 nic_data->must_realloc_vis = true;
1409 nic_data->must_restore_filters = true;
1410 nic_data->must_restore_piobufs = true;
1411 efx_ef10_forget_old_piobufs(efx);
1412 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1413
1414 /* Driver-created vswitches and vports must be re-created */
1415 nic_data->must_probe_vswitching = true;
1416 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1417 #ifdef CONFIG_SFC_SRIOV
1418 if (nic_data->vf)
1419 for (i = 0; i < efx->vf_count; i++)
1420 nic_data->vf[i].vport_id = 0;
1421 #endif
1422 }
1423
1424 static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1425 {
1426 if (reason == RESET_TYPE_MC_FAILURE)
1427 return RESET_TYPE_DATAPATH;
1428
1429 return efx_mcdi_map_reset_reason(reason);
1430 }
1431
1432 static int efx_ef10_map_reset_flags(u32 *flags)
1433 {
1434 enum {
1435 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1436 ETH_RESET_SHARED_SHIFT),
1437 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1438 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1439 ETH_RESET_PHY | ETH_RESET_MGMT) <<
1440 ETH_RESET_SHARED_SHIFT)
1441 };
1442
1443 /* We assume for now that our PCI function is permitted to
1444 * reset everything.
1445 */
1446
1447 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1448 *flags &= ~EF10_RESET_MC;
1449 return RESET_TYPE_WORLD;
1450 }
1451
1452 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1453 *flags &= ~EF10_RESET_PORT;
1454 return RESET_TYPE_ALL;
1455 }
1456
1457 /* no invisible reset implemented */
1458
1459 return -EINVAL;
1460 }
1461
1462 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1463 {
1464 int rc = efx_mcdi_reset(efx, reset_type);
1465
1466 /* Unprivileged functions return -EPERM, but need to return success
1467 * here so that the datapath is brought back up.
1468 */
1469 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1470 rc = 0;
1471
1472 /* If it was a port reset, trigger reallocation of MC resources.
1473 * Note that on an MC reset nothing needs to be done now because we'll
1474 * detect the MC reset later and handle it then.
1475 * For an FLR, we never get an MC reset event, but the MC has reset all
1476 * resources assigned to us, so we have to trigger reallocation now.
1477 */
1478 if ((reset_type == RESET_TYPE_ALL ||
1479 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
1480 efx_ef10_reset_mc_allocations(efx);
1481 return rc;
1482 }
1483
1484 #define EF10_DMA_STAT(ext_name, mcdi_name) \
1485 [EF10_STAT_ ## ext_name] = \
1486 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1487 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
1488 [EF10_STAT_ ## int_name] = \
1489 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1490 #define EF10_OTHER_STAT(ext_name) \
1491 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1492 #define GENERIC_SW_STAT(ext_name) \
1493 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1494
1495 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
1496 EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1497 EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1498 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1499 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1500 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1501 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1502 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1503 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1504 EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1505 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1506 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1507 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1508 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1509 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1510 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1511 EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1512 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1513 EF10_OTHER_STAT(port_rx_good_bytes),
1514 EF10_OTHER_STAT(port_rx_bad_bytes),
1515 EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1516 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1517 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1518 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1519 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1520 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1521 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1522 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1523 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1524 EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1525 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1526 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1527 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1528 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1529 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1530 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1531 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1532 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1533 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1534 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1535 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1536 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
1537 GENERIC_SW_STAT(rx_nodesc_trunc),
1538 GENERIC_SW_STAT(rx_noskb_drops),
1539 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1540 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1541 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1542 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1543 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1544 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1545 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1546 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1547 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1548 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1549 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1550 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
1551 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1552 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1553 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1554 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1555 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1556 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1557 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1558 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1559 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1560 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1561 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1562 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1563 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1564 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1565 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1566 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1567 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1568 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
1569 };
1570
1571 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \
1572 (1ULL << EF10_STAT_port_tx_packets) | \
1573 (1ULL << EF10_STAT_port_tx_pause) | \
1574 (1ULL << EF10_STAT_port_tx_unicast) | \
1575 (1ULL << EF10_STAT_port_tx_multicast) | \
1576 (1ULL << EF10_STAT_port_tx_broadcast) | \
1577 (1ULL << EF10_STAT_port_rx_bytes) | \
1578 (1ULL << \
1579 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1580 (1ULL << EF10_STAT_port_rx_good_bytes) | \
1581 (1ULL << EF10_STAT_port_rx_bad_bytes) | \
1582 (1ULL << EF10_STAT_port_rx_packets) | \
1583 (1ULL << EF10_STAT_port_rx_good) | \
1584 (1ULL << EF10_STAT_port_rx_bad) | \
1585 (1ULL << EF10_STAT_port_rx_pause) | \
1586 (1ULL << EF10_STAT_port_rx_control) | \
1587 (1ULL << EF10_STAT_port_rx_unicast) | \
1588 (1ULL << EF10_STAT_port_rx_multicast) | \
1589 (1ULL << EF10_STAT_port_rx_broadcast) | \
1590 (1ULL << EF10_STAT_port_rx_lt64) | \
1591 (1ULL << EF10_STAT_port_rx_64) | \
1592 (1ULL << EF10_STAT_port_rx_65_to_127) | \
1593 (1ULL << EF10_STAT_port_rx_128_to_255) | \
1594 (1ULL << EF10_STAT_port_rx_256_to_511) | \
1595 (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1596 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1597 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1598 (1ULL << EF10_STAT_port_rx_gtjumbo) | \
1599 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1600 (1ULL << EF10_STAT_port_rx_overflow) | \
1601 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
1602 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1603 (1ULL << GENERIC_STAT_rx_noskb_drops))
1604
1605 /* On 7000 series NICs, these statistics are only provided by the 10G MAC.
1606 * For a 10G/40G switchable port we do not expose these because they might
1607 * not include all the packets they should.
1608 * On 8000 series NICs these statistics are always provided.
1609 */
1610 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \
1611 (1ULL << EF10_STAT_port_tx_lt64) | \
1612 (1ULL << EF10_STAT_port_tx_64) | \
1613 (1ULL << EF10_STAT_port_tx_65_to_127) |\
1614 (1ULL << EF10_STAT_port_tx_128_to_255) |\
1615 (1ULL << EF10_STAT_port_tx_256_to_511) |\
1616 (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1617 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1618 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
1619
1620 /* These statistics are only provided by the 40G MAC. For a 10G/40G
1621 * switchable port we do expose these because the errors will otherwise
1622 * be silent.
1623 */
1624 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1625 (1ULL << EF10_STAT_port_rx_length_error))
1626
1627 /* These statistics are only provided if the firmware supports the
1628 * capability PM_AND_RXDP_COUNTERS.
1629 */
1630 #define HUNT_PM_AND_RXDP_STAT_MASK ( \
1631 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \
1632 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \
1633 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \
1634 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \
1635 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \
1636 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \
1637 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \
1638 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \
1639 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \
1640 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \
1641 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \
1642 (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
1643
1644 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
1645 {
1646 u64 raw_mask = HUNT_COMMON_STAT_MASK;
1647 u32 port_caps = efx_mcdi_phy_get_caps(efx);
1648 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1649
1650 if (!(efx->mcdi->fn_flags &
1651 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1652 return 0;
1653
1654 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) {
1655 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
1656 /* 8000 series have everything even at 40G */
1657 if (nic_data->datapath_caps2 &
1658 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN))
1659 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1660 } else {
1661 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1662 }
1663
1664 if (nic_data->datapath_caps &
1665 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1666 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1667
1668 return raw_mask;
1669 }
1670
1671 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1672 {
1673 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1674 u64 raw_mask[2];
1675
1676 raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1677
1678 /* Only show vadaptor stats when EVB capability is present */
1679 if (nic_data->datapath_caps &
1680 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1681 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1682 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1;
1683 } else {
1684 raw_mask[1] = 0;
1685 }
1686
1687 #if BITS_PER_LONG == 64
1688 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 2);
1689 mask[0] = raw_mask[0];
1690 mask[1] = raw_mask[1];
1691 #else
1692 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 3);
1693 mask[0] = raw_mask[0] & 0xffffffff;
1694 mask[1] = raw_mask[0] >> 32;
1695 mask[2] = raw_mask[1] & 0xffffffff;
1696 #endif
1697 }
1698
1699 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1700 {
1701 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1702
1703 efx_ef10_get_stat_mask(efx, mask);
1704 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
1705 mask, names);
1706 }
1707
1708 static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1709 struct rtnl_link_stats64 *core_stats)
1710 {
1711 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1712 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1713 u64 *stats = nic_data->stats;
1714 size_t stats_count = 0, index;
1715
1716 efx_ef10_get_stat_mask(efx, mask);
1717
1718 if (full_stats) {
1719 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1720 if (efx_ef10_stat_desc[index].name) {
1721 *full_stats++ = stats[index];
1722 ++stats_count;
1723 }
1724 }
1725 }
1726
1727 if (!core_stats)
1728 return stats_count;
1729
1730 if (nic_data->datapath_caps &
1731 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1732 /* Use vadaptor stats. */
1733 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1734 stats[EF10_STAT_rx_multicast] +
1735 stats[EF10_STAT_rx_broadcast];
1736 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1737 stats[EF10_STAT_tx_multicast] +
1738 stats[EF10_STAT_tx_broadcast];
1739 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1740 stats[EF10_STAT_rx_multicast_bytes] +
1741 stats[EF10_STAT_rx_broadcast_bytes];
1742 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1743 stats[EF10_STAT_tx_multicast_bytes] +
1744 stats[EF10_STAT_tx_broadcast_bytes];
1745 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
1746 stats[GENERIC_STAT_rx_noskb_drops];
1747 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1748 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1749 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1750 core_stats->rx_errors = core_stats->rx_crc_errors;
1751 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
1752 } else {
1753 /* Use port stats. */
1754 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1755 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1756 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1757 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1758 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1759 stats[GENERIC_STAT_rx_nodesc_trunc] +
1760 stats[GENERIC_STAT_rx_noskb_drops];
1761 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1762 core_stats->rx_length_errors =
1763 stats[EF10_STAT_port_rx_gtjumbo] +
1764 stats[EF10_STAT_port_rx_length_error];
1765 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1766 core_stats->rx_frame_errors =
1767 stats[EF10_STAT_port_rx_align_error];
1768 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1769 core_stats->rx_errors = (core_stats->rx_length_errors +
1770 core_stats->rx_crc_errors +
1771 core_stats->rx_frame_errors);
1772 }
1773
1774 return stats_count;
1775 }
1776
1777 static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
1778 {
1779 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1780 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1781 __le64 generation_start, generation_end;
1782 u64 *stats = nic_data->stats;
1783 __le64 *dma_stats;
1784
1785 efx_ef10_get_stat_mask(efx, mask);
1786
1787 dma_stats = efx->stats_buffer.addr;
1788
1789 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1790 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1791 return 0;
1792 rmb();
1793 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1794 stats, efx->stats_buffer.addr, false);
1795 rmb();
1796 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1797 if (generation_end != generation_start)
1798 return -EAGAIN;
1799
1800 /* Update derived statistics */
1801 efx_nic_fix_nodesc_drop_stat(efx,
1802 &stats[EF10_STAT_port_rx_nodesc_drops]);
1803 stats[EF10_STAT_port_rx_good_bytes] =
1804 stats[EF10_STAT_port_rx_bytes] -
1805 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1806 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1807 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
1808 efx_update_sw_stats(efx, stats);
1809 return 0;
1810 }
1811
1812
1813 static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1814 struct rtnl_link_stats64 *core_stats)
1815 {
1816 int retry;
1817
1818 /* If we're unlucky enough to read statistics during the DMA, wait
1819 * up to 10ms for it to finish (typically takes <500us)
1820 */
1821 for (retry = 0; retry < 100; ++retry) {
1822 if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
1823 break;
1824 udelay(100);
1825 }
1826
1827 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1828 }
1829
1830 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1831 {
1832 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1833 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1834 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1835 __le64 generation_start, generation_end;
1836 u64 *stats = nic_data->stats;
1837 u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64);
1838 struct efx_buffer stats_buf;
1839 __le64 *dma_stats;
1840 int rc;
1841
1842 spin_unlock_bh(&efx->stats_lock);
1843
1844 if (in_interrupt()) {
1845 /* If in atomic context, cannot update stats. Just update the
1846 * software stats and return so the caller can continue.
1847 */
1848 spin_lock_bh(&efx->stats_lock);
1849 efx_update_sw_stats(efx, stats);
1850 return 0;
1851 }
1852
1853 efx_ef10_get_stat_mask(efx, mask);
1854
1855 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
1856 if (rc) {
1857 spin_lock_bh(&efx->stats_lock);
1858 return rc;
1859 }
1860
1861 dma_stats = stats_buf.addr;
1862 dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID;
1863
1864 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
1865 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
1866 MAC_STATS_IN_DMA, 1);
1867 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
1868 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1869
1870 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
1871 NULL, 0, NULL);
1872 spin_lock_bh(&efx->stats_lock);
1873 if (rc) {
1874 /* Expect ENOENT if DMA queues have not been set up */
1875 if (rc != -ENOENT || atomic_read(&efx->active_queues))
1876 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
1877 sizeof(inbuf), NULL, 0, rc);
1878 goto out;
1879 }
1880
1881 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1882 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
1883 WARN_ON_ONCE(1);
1884 goto out;
1885 }
1886 rmb();
1887 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1888 stats, stats_buf.addr, false);
1889 rmb();
1890 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1891 if (generation_end != generation_start) {
1892 rc = -EAGAIN;
1893 goto out;
1894 }
1895
1896 efx_update_sw_stats(efx, stats);
1897 out:
1898 efx_nic_free_buffer(efx, &stats_buf);
1899 return rc;
1900 }
1901
1902 static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
1903 struct rtnl_link_stats64 *core_stats)
1904 {
1905 if (efx_ef10_try_update_nic_stats_vf(efx))
1906 return 0;
1907
1908 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1909 }
1910
1911 static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1912 {
1913 struct efx_nic *efx = channel->efx;
1914 unsigned int mode, usecs;
1915 efx_dword_t timer_cmd;
1916
1917 if (channel->irq_moderation_us) {
1918 mode = 3;
1919 usecs = channel->irq_moderation_us;
1920 } else {
1921 mode = 0;
1922 usecs = 0;
1923 }
1924
1925 if (EFX_EF10_WORKAROUND_61265(efx)) {
1926 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_EVQ_TMR_IN_LEN);
1927 unsigned int ns = usecs * 1000;
1928
1929 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_INSTANCE,
1930 channel->channel);
1931 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, ns);
1932 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, ns);
1933 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_MODE, mode);
1934
1935 efx_mcdi_rpc_async(efx, MC_CMD_SET_EVQ_TMR,
1936 inbuf, sizeof(inbuf), 0, NULL, 0);
1937 } else if (EFX_EF10_WORKAROUND_35388(efx)) {
1938 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
1939
1940 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1941 EFE_DD_EVQ_IND_TIMER_FLAGS,
1942 ERF_DD_EVQ_IND_TIMER_MODE, mode,
1943 ERF_DD_EVQ_IND_TIMER_VAL, ticks);
1944 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1945 channel->channel);
1946 } else {
1947 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
1948
1949 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
1950 ERF_DZ_TC_TIMER_VAL, ticks);
1951 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1952 channel->channel);
1953 }
1954 }
1955
1956 static void efx_ef10_get_wol_vf(struct efx_nic *efx,
1957 struct ethtool_wolinfo *wol) {}
1958
1959 static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
1960 {
1961 return -EOPNOTSUPP;
1962 }
1963
1964 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1965 {
1966 wol->supported = 0;
1967 wol->wolopts = 0;
1968 memset(&wol->sopass, 0, sizeof(wol->sopass));
1969 }
1970
1971 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1972 {
1973 if (type != 0)
1974 return -EINVAL;
1975 return 0;
1976 }
1977
1978 static void efx_ef10_mcdi_request(struct efx_nic *efx,
1979 const efx_dword_t *hdr, size_t hdr_len,
1980 const efx_dword_t *sdu, size_t sdu_len)
1981 {
1982 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1983 u8 *pdu = nic_data->mcdi_buf.addr;
1984
1985 memcpy(pdu, hdr, hdr_len);
1986 memcpy(pdu + hdr_len, sdu, sdu_len);
1987 wmb();
1988
1989 /* The hardware provides 'low' and 'high' (doorbell) registers
1990 * for passing the 64-bit address of an MCDI request to
1991 * firmware. However the dwords are swapped by firmware. The
1992 * least significant bits of the doorbell are then 0 for all
1993 * MCDI requests due to alignment.
1994 */
1995 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1996 ER_DZ_MC_DB_LWRD);
1997 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1998 ER_DZ_MC_DB_HWRD);
1999 }
2000
2001 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
2002 {
2003 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2004 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
2005
2006 rmb();
2007 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
2008 }
2009
2010 static void
2011 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
2012 size_t offset, size_t outlen)
2013 {
2014 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2015 const u8 *pdu = nic_data->mcdi_buf.addr;
2016
2017 memcpy(outbuf, pdu + offset, outlen);
2018 }
2019
2020 static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx)
2021 {
2022 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2023
2024 /* All our allocations have been reset */
2025 efx_ef10_reset_mc_allocations(efx);
2026
2027 /* The datapath firmware might have been changed */
2028 nic_data->must_check_datapath_caps = true;
2029
2030 /* MAC statistics have been cleared on the NIC; clear the local
2031 * statistic that we update with efx_update_diff_stat().
2032 */
2033 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
2034 }
2035
2036 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
2037 {
2038 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2039 int rc;
2040
2041 rc = efx_ef10_get_warm_boot_count(efx);
2042 if (rc < 0) {
2043 /* The firmware is presumably in the process of
2044 * rebooting. However, we are supposed to report each
2045 * reboot just once, so we must only do that once we
2046 * can read and store the updated warm boot count.
2047 */
2048 return 0;
2049 }
2050
2051 if (rc == nic_data->warm_boot_count)
2052 return 0;
2053
2054 nic_data->warm_boot_count = rc;
2055 efx_ef10_mcdi_reboot_detected(efx);
2056
2057 return -EIO;
2058 }
2059
2060 /* Handle an MSI interrupt
2061 *
2062 * Handle an MSI hardware interrupt. This routine schedules event
2063 * queue processing. No interrupt acknowledgement cycle is necessary.
2064 * Also, we never need to check that the interrupt is for us, since
2065 * MSI interrupts cannot be shared.
2066 */
2067 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
2068 {
2069 struct efx_msi_context *context = dev_id;
2070 struct efx_nic *efx = context->efx;
2071
2072 netif_vdbg(efx, intr, efx->net_dev,
2073 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
2074
2075 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
2076 /* Note test interrupts */
2077 if (context->index == efx->irq_level)
2078 efx->last_irq_cpu = raw_smp_processor_id();
2079
2080 /* Schedule processing of the channel */
2081 efx_schedule_channel_irq(efx->channel[context->index]);
2082 }
2083
2084 return IRQ_HANDLED;
2085 }
2086
2087 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
2088 {
2089 struct efx_nic *efx = dev_id;
2090 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
2091 struct efx_channel *channel;
2092 efx_dword_t reg;
2093 u32 queues;
2094
2095 /* Read the ISR which also ACKs the interrupts */
2096 efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
2097 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
2098
2099 if (queues == 0)
2100 return IRQ_NONE;
2101
2102 if (likely(soft_enabled)) {
2103 /* Note test interrupts */
2104 if (queues & (1U << efx->irq_level))
2105 efx->last_irq_cpu = raw_smp_processor_id();
2106
2107 efx_for_each_channel(channel, efx) {
2108 if (queues & 1)
2109 efx_schedule_channel_irq(channel);
2110 queues >>= 1;
2111 }
2112 }
2113
2114 netif_vdbg(efx, intr, efx->net_dev,
2115 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
2116 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
2117
2118 return IRQ_HANDLED;
2119 }
2120
2121 static int efx_ef10_irq_test_generate(struct efx_nic *efx)
2122 {
2123 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
2124
2125 if (efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG41750, true,
2126 NULL) == 0)
2127 return -ENOTSUPP;
2128
2129 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
2130
2131 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
2132 return efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
2133 inbuf, sizeof(inbuf), NULL, 0, NULL);
2134 }
2135
2136 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
2137 {
2138 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
2139 (tx_queue->ptr_mask + 1) *
2140 sizeof(efx_qword_t),
2141 GFP_KERNEL);
2142 }
2143
2144 /* This writes to the TX_DESC_WPTR and also pushes data */
2145 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
2146 const efx_qword_t *txd)
2147 {
2148 unsigned int write_ptr;
2149 efx_oword_t reg;
2150
2151 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2152 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
2153 reg.qword[0] = *txd;
2154 efx_writeo_page(tx_queue->efx, &reg,
2155 ER_DZ_TX_DESC_UPD, tx_queue->queue);
2156 }
2157
2158 /* Add Firmware-Assisted TSO v2 option descriptors to a queue.
2159 */
2160 static int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue,
2161 struct sk_buff *skb,
2162 bool *data_mapped)
2163 {
2164 struct efx_tx_buffer *buffer;
2165 struct tcphdr *tcp;
2166 struct iphdr *ip;
2167
2168 u16 ipv4_id;
2169 u32 seqnum;
2170 u32 mss;
2171
2172 EFX_WARN_ON_ONCE_PARANOID(tx_queue->tso_version != 2);
2173
2174 mss = skb_shinfo(skb)->gso_size;
2175
2176 if (unlikely(mss < 4)) {
2177 WARN_ONCE(1, "MSS of %u is too small for TSO v2\n", mss);
2178 return -EINVAL;
2179 }
2180
2181 ip = ip_hdr(skb);
2182 if (ip->version == 4) {
2183 /* Modify IPv4 header if needed. */
2184 ip->tot_len = 0;
2185 ip->check = 0;
2186 ipv4_id = ip->id;
2187 } else {
2188 /* Modify IPv6 header if needed. */
2189 struct ipv6hdr *ipv6 = ipv6_hdr(skb);
2190
2191 ipv6->payload_len = 0;
2192 ipv4_id = 0;
2193 }
2194
2195 tcp = tcp_hdr(skb);
2196 seqnum = ntohl(tcp->seq);
2197
2198 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2199
2200 buffer->flags = EFX_TX_BUF_OPTION;
2201 buffer->len = 0;
2202 buffer->unmap_len = 0;
2203 EFX_POPULATE_QWORD_5(buffer->option,
2204 ESF_DZ_TX_DESC_IS_OPT, 1,
2205 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2206 ESF_DZ_TX_TSO_OPTION_TYPE,
2207 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A,
2208 ESF_DZ_TX_TSO_IP_ID, ipv4_id,
2209 ESF_DZ_TX_TSO_TCP_SEQNO, seqnum
2210 );
2211 ++tx_queue->insert_count;
2212
2213 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2214
2215 buffer->flags = EFX_TX_BUF_OPTION;
2216 buffer->len = 0;
2217 buffer->unmap_len = 0;
2218 EFX_POPULATE_QWORD_4(buffer->option,
2219 ESF_DZ_TX_DESC_IS_OPT, 1,
2220 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2221 ESF_DZ_TX_TSO_OPTION_TYPE,
2222 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B,
2223 ESF_DZ_TX_TSO_TCP_MSS, mss
2224 );
2225 ++tx_queue->insert_count;
2226
2227 return 0;
2228 }
2229
2230 static u32 efx_ef10_tso_versions(struct efx_nic *efx)
2231 {
2232 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2233 u32 tso_versions = 0;
2234
2235 if (nic_data->datapath_caps &
2236 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))
2237 tso_versions |= BIT(1);
2238 if (nic_data->datapath_caps2 &
2239 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN))
2240 tso_versions |= BIT(2);
2241 return tso_versions;
2242 }
2243
2244 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
2245 {
2246 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2247 EFX_BUF_SIZE));
2248 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
2249 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
2250 struct efx_channel *channel = tx_queue->channel;
2251 struct efx_nic *efx = tx_queue->efx;
2252 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2253 bool tso_v2 = false;
2254 size_t inlen;
2255 dma_addr_t dma_addr;
2256 efx_qword_t *txd;
2257 int rc;
2258 int i;
2259 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
2260
2261 /* TSOv2 is a limited resource that can only be configured on a limited
2262 * number of queues. TSO without checksum offload is not really a thing,
2263 * so we only enable it for those queues.
2264 */
2265 if (csum_offload && (nic_data->datapath_caps2 &
2266 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN))) {
2267 tso_v2 = true;
2268 netif_dbg(efx, hw, efx->net_dev, "Using TSOv2 for channel %u\n",
2269 channel->channel);
2270 }
2271
2272 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
2273 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
2274 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
2275 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
2276 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
2277 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
2278
2279 dma_addr = tx_queue->txd.buf.dma_addr;
2280
2281 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
2282 tx_queue->queue, entries, (u64)dma_addr);
2283
2284 for (i = 0; i < entries; ++i) {
2285 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
2286 dma_addr += EFX_BUF_SIZE;
2287 }
2288
2289 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
2290
2291 do {
2292 MCDI_POPULATE_DWORD_3(inbuf, INIT_TXQ_IN_FLAGS,
2293 /* This flag was removed from mcdi_pcol.h for
2294 * the non-_EXT version of INIT_TXQ. However,
2295 * firmware still honours it.
2296 */
2297 INIT_TXQ_EXT_IN_FLAG_TSOV2_EN, tso_v2,
2298 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
2299 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
2300
2301 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
2302 NULL, 0, NULL);
2303 if (rc == -ENOSPC && tso_v2) {
2304 /* Retry without TSOv2 if we're short on contexts. */
2305 tso_v2 = false;
2306 netif_warn(efx, probe, efx->net_dev,
2307 "TSOv2 context not available to segment in hardware. TCP performance may be reduced.\n");
2308 } else if (rc) {
2309 efx_mcdi_display_error(efx, MC_CMD_INIT_TXQ,
2310 MC_CMD_INIT_TXQ_EXT_IN_LEN,
2311 NULL, 0, rc);
2312 goto fail;
2313 }
2314 } while (rc);
2315
2316 /* A previous user of this TX queue might have set us up the
2317 * bomb by writing a descriptor to the TX push collector but
2318 * not the doorbell. (Each collector belongs to a port, not a
2319 * queue or function, so cannot easily be reset.) We must
2320 * attempt to push a no-op descriptor in its place.
2321 */
2322 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
2323 tx_queue->insert_count = 1;
2324 txd = efx_tx_desc(tx_queue, 0);
2325 EFX_POPULATE_QWORD_4(*txd,
2326 ESF_DZ_TX_DESC_IS_OPT, true,
2327 ESF_DZ_TX_OPTION_TYPE,
2328 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
2329 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
2330 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
2331 tx_queue->write_count = 1;
2332
2333 if (tso_v2) {
2334 tx_queue->handle_tso = efx_ef10_tx_tso_desc;
2335 tx_queue->tso_version = 2;
2336 } else if (nic_data->datapath_caps &
2337 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) {
2338 tx_queue->tso_version = 1;
2339 }
2340
2341 wmb();
2342 efx_ef10_push_tx_desc(tx_queue, txd);
2343
2344 return;
2345
2346 fail:
2347 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
2348 tx_queue->queue);
2349 }
2350
2351 static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
2352 {
2353 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
2354 MCDI_DECLARE_BUF_ERR(outbuf);
2355 struct efx_nic *efx = tx_queue->efx;
2356 size_t outlen;
2357 int rc;
2358
2359 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
2360 tx_queue->queue);
2361
2362 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
2363 outbuf, sizeof(outbuf), &outlen);
2364
2365 if (rc && rc != -EALREADY)
2366 goto fail;
2367
2368 return;
2369
2370 fail:
2371 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
2372 outbuf, outlen, rc);
2373 }
2374
2375 static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
2376 {
2377 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
2378 }
2379
2380 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
2381 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
2382 {
2383 unsigned int write_ptr;
2384 efx_dword_t reg;
2385
2386 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2387 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
2388 efx_writed_page(tx_queue->efx, &reg,
2389 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
2390 }
2391
2392 #define EFX_EF10_MAX_TX_DESCRIPTOR_LEN 0x3fff
2393
2394 static unsigned int efx_ef10_tx_limit_len(struct efx_tx_queue *tx_queue,
2395 dma_addr_t dma_addr, unsigned int len)
2396 {
2397 if (len > EFX_EF10_MAX_TX_DESCRIPTOR_LEN) {
2398 /* If we need to break across multiple descriptors we should
2399 * stop at a page boundary. This assumes the length limit is
2400 * greater than the page size.
2401 */
2402 dma_addr_t end = dma_addr + EFX_EF10_MAX_TX_DESCRIPTOR_LEN;
2403
2404 BUILD_BUG_ON(EFX_EF10_MAX_TX_DESCRIPTOR_LEN < EFX_PAGE_SIZE);
2405 len = (end & (~(EFX_PAGE_SIZE - 1))) - dma_addr;
2406 }
2407
2408 return len;
2409 }
2410
2411 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
2412 {
2413 unsigned int old_write_count = tx_queue->write_count;
2414 struct efx_tx_buffer *buffer;
2415 unsigned int write_ptr;
2416 efx_qword_t *txd;
2417
2418 tx_queue->xmit_more_available = false;
2419 if (unlikely(tx_queue->write_count == tx_queue->insert_count))
2420 return;
2421
2422 do {
2423 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2424 buffer = &tx_queue->buffer[write_ptr];
2425 txd = efx_tx_desc(tx_queue, write_ptr);
2426 ++tx_queue->write_count;
2427
2428 /* Create TX descriptor ring entry */
2429 if (buffer->flags & EFX_TX_BUF_OPTION) {
2430 *txd = buffer->option;
2431 if (EFX_QWORD_FIELD(*txd, ESF_DZ_TX_OPTION_TYPE) == 1)
2432 /* PIO descriptor */
2433 tx_queue->packet_write_count = tx_queue->write_count;
2434 } else {
2435 tx_queue->packet_write_count = tx_queue->write_count;
2436 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
2437 EFX_POPULATE_QWORD_3(
2438 *txd,
2439 ESF_DZ_TX_KER_CONT,
2440 buffer->flags & EFX_TX_BUF_CONT,
2441 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
2442 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
2443 }
2444 } while (tx_queue->write_count != tx_queue->insert_count);
2445
2446 wmb(); /* Ensure descriptors are written before they are fetched */
2447
2448 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
2449 txd = efx_tx_desc(tx_queue,
2450 old_write_count & tx_queue->ptr_mask);
2451 efx_ef10_push_tx_desc(tx_queue, txd);
2452 ++tx_queue->pushes;
2453 } else {
2454 efx_ef10_notify_tx_desc(tx_queue);
2455 }
2456 }
2457
2458 #define RSS_MODE_HASH_ADDRS (1 << RSS_MODE_HASH_SRC_ADDR_LBN |\
2459 1 << RSS_MODE_HASH_DST_ADDR_LBN)
2460 #define RSS_MODE_HASH_PORTS (1 << RSS_MODE_HASH_SRC_PORT_LBN |\
2461 1 << RSS_MODE_HASH_DST_PORT_LBN)
2462 #define RSS_CONTEXT_FLAGS_DEFAULT (1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN |\
2463 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN |\
2464 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN |\
2465 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN |\
2466 (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN |\
2467 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN |\
2468 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN |\
2469 (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN |\
2470 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN |\
2471 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN)
2472
2473 static int efx_ef10_get_rss_flags(struct efx_nic *efx, u32 context, u32 *flags)
2474 {
2475 /* Firmware had a bug (sfc bug 61952) where it would not actually
2476 * fill in the flags field in the response to MC_CMD_RSS_CONTEXT_GET_FLAGS.
2477 * This meant that it would always contain whatever was previously
2478 * in the MCDI buffer. Fortunately, all firmware versions with
2479 * this bug have the same default flags value for a newly-allocated
2480 * RSS context, and the only time we want to get the flags is just
2481 * after allocating. Moreover, the response has a 32-bit hole
2482 * where the context ID would be in the request, so we can use an
2483 * overlength buffer in the request and pre-fill the flags field
2484 * with what we believe the default to be. Thus if the firmware
2485 * has the bug, it will leave our pre-filled value in the flags
2486 * field of the response, and we will get the right answer.
2487 *
2488 * However, this does mean that this function should NOT be used if
2489 * the RSS context flags might not be their defaults - it is ONLY
2490 * reliably correct for a newly-allocated RSS context.
2491 */
2492 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2493 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2494 size_t outlen;
2495 int rc;
2496
2497 /* Check we have a hole for the context ID */
2498 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN != MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST);
2499 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID, context);
2500 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS,
2501 RSS_CONTEXT_FLAGS_DEFAULT);
2502 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_FLAGS, inbuf,
2503 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
2504 if (rc == 0) {
2505 if (outlen < MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN)
2506 rc = -EIO;
2507 else
2508 *flags = MCDI_DWORD(outbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS);
2509 }
2510 return rc;
2511 }
2512
2513 /* Attempt to enable 4-tuple UDP hashing on the specified RSS context.
2514 * If we fail, we just leave the RSS context at its default hash settings,
2515 * which is safe but may slightly reduce performance.
2516 * Defaults are 4-tuple for TCP and 2-tuple for UDP and other-IP, so we
2517 * just need to set the UDP ports flags (for both IP versions).
2518 */
2519 static void efx_ef10_set_rss_flags(struct efx_nic *efx, u32 context)
2520 {
2521 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN);
2522 u32 flags;
2523
2524 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN != 0);
2525
2526 if (efx_ef10_get_rss_flags(efx, context, &flags) != 0)
2527 return;
2528 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID, context);
2529 flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN;
2530 flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN;
2531 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_FLAGS, flags);
2532 if (!efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_FLAGS, inbuf, sizeof(inbuf),
2533 NULL, 0, NULL))
2534 /* Succeeded, so UDP 4-tuple is now enabled */
2535 efx->rx_hash_udp_4tuple = true;
2536 }
2537
2538 static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
2539 bool exclusive, unsigned *context_size)
2540 {
2541 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
2542 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
2543 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2544 size_t outlen;
2545 int rc;
2546 u32 alloc_type = exclusive ?
2547 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
2548 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
2549 unsigned rss_spread = exclusive ?
2550 efx->rss_spread :
2551 min(rounddown_pow_of_two(efx->rss_spread),
2552 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
2553
2554 if (!exclusive && rss_spread == 1) {
2555 *context = EFX_EF10_RSS_CONTEXT_INVALID;
2556 if (context_size)
2557 *context_size = 1;
2558 return 0;
2559 }
2560
2561 if (nic_data->datapath_caps &
2562 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN)
2563 return -EOPNOTSUPP;
2564
2565 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
2566 nic_data->vport_id);
2567 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
2568 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
2569
2570 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
2571 outbuf, sizeof(outbuf), &outlen);
2572 if (rc != 0)
2573 return rc;
2574
2575 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
2576 return -EIO;
2577
2578 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
2579
2580 if (context_size)
2581 *context_size = rss_spread;
2582
2583 if (nic_data->datapath_caps &
2584 1 << MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN)
2585 efx_ef10_set_rss_flags(efx, *context);
2586
2587 return 0;
2588 }
2589
2590 static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
2591 {
2592 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
2593 int rc;
2594
2595 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
2596 context);
2597
2598 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
2599 NULL, 0, NULL);
2600 WARN_ON(rc != 0);
2601 }
2602
2603 static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
2604 const u32 *rx_indir_table, const u8 *key)
2605 {
2606 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
2607 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
2608 int i, rc;
2609
2610 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
2611 context);
2612 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
2613 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
2614
2615 /* This iterates over the length of efx->rx_indir_table, but copies
2616 * bytes from rx_indir_table. That's because the latter is a pointer
2617 * rather than an array, but should have the same length.
2618 * The efx->rx_hash_key loop below is similar.
2619 */
2620 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
2621 MCDI_PTR(tablebuf,
2622 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
2623 (u8) rx_indir_table[i];
2624
2625 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
2626 sizeof(tablebuf), NULL, 0, NULL);
2627 if (rc != 0)
2628 return rc;
2629
2630 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
2631 context);
2632 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
2633 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2634 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
2635 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] = key[i];
2636
2637 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
2638 sizeof(keybuf), NULL, 0, NULL);
2639 }
2640
2641 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
2642 {
2643 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2644
2645 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2646 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
2647 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
2648 }
2649
2650 static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
2651 unsigned *context_size)
2652 {
2653 u32 new_rx_rss_context;
2654 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2655 int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2656 false, context_size);
2657
2658 if (rc != 0)
2659 return rc;
2660
2661 nic_data->rx_rss_context = new_rx_rss_context;
2662 nic_data->rx_rss_context_exclusive = false;
2663 efx_set_default_rx_indir_table(efx);
2664 return 0;
2665 }
2666
2667 static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
2668 const u32 *rx_indir_table,
2669 const u8 *key)
2670 {
2671 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2672 int rc;
2673 u32 new_rx_rss_context;
2674
2675 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
2676 !nic_data->rx_rss_context_exclusive) {
2677 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2678 true, NULL);
2679 if (rc == -EOPNOTSUPP)
2680 return rc;
2681 else if (rc != 0)
2682 goto fail1;
2683 } else {
2684 new_rx_rss_context = nic_data->rx_rss_context;
2685 }
2686
2687 rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
2688 rx_indir_table, key);
2689 if (rc != 0)
2690 goto fail2;
2691
2692 if (nic_data->rx_rss_context != new_rx_rss_context)
2693 efx_ef10_rx_free_indir_table(efx);
2694 nic_data->rx_rss_context = new_rx_rss_context;
2695 nic_data->rx_rss_context_exclusive = true;
2696 if (rx_indir_table != efx->rx_indir_table)
2697 memcpy(efx->rx_indir_table, rx_indir_table,
2698 sizeof(efx->rx_indir_table));
2699 if (key != efx->rx_hash_key)
2700 memcpy(efx->rx_hash_key, key, efx->type->rx_hash_key_size);
2701
2702 return 0;
2703
2704 fail2:
2705 if (new_rx_rss_context != nic_data->rx_rss_context)
2706 efx_ef10_free_rss_context(efx, new_rx_rss_context);
2707 fail1:
2708 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2709 return rc;
2710 }
2711
2712 static int efx_ef10_rx_pull_rss_config(struct efx_nic *efx)
2713 {
2714 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2715 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN);
2716 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN);
2717 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN);
2718 size_t outlen;
2719 int rc, i;
2720
2721 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN !=
2722 MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN);
2723
2724 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID)
2725 return -ENOENT;
2726
2727 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID,
2728 nic_data->rx_rss_context);
2729 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
2730 MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN);
2731 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_TABLE, inbuf, sizeof(inbuf),
2732 tablebuf, sizeof(tablebuf), &outlen);
2733 if (rc != 0)
2734 return rc;
2735
2736 if (WARN_ON(outlen != MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN))
2737 return -EIO;
2738
2739 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++)
2740 efx->rx_indir_table[i] = MCDI_PTR(tablebuf,
2741 RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE)[i];
2742
2743 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID,
2744 nic_data->rx_rss_context);
2745 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
2746 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2747 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_KEY, inbuf, sizeof(inbuf),
2748 keybuf, sizeof(keybuf), &outlen);
2749 if (rc != 0)
2750 return rc;
2751
2752 if (WARN_ON(outlen != MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN))
2753 return -EIO;
2754
2755 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
2756 efx->rx_hash_key[i] = MCDI_PTR(
2757 keybuf, RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY)[i];
2758
2759 return 0;
2760 }
2761
2762 static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
2763 const u32 *rx_indir_table,
2764 const u8 *key)
2765 {
2766 int rc;
2767
2768 if (efx->rss_spread == 1)
2769 return 0;
2770
2771 if (!key)
2772 key = efx->rx_hash_key;
2773
2774 rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table, key);
2775
2776 if (rc == -ENOBUFS && !user) {
2777 unsigned context_size;
2778 bool mismatch = false;
2779 size_t i;
2780
2781 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
2782 i++)
2783 mismatch = rx_indir_table[i] !=
2784 ethtool_rxfh_indir_default(i, efx->rss_spread);
2785
2786 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
2787 if (rc == 0) {
2788 if (context_size != efx->rss_spread)
2789 netif_warn(efx, probe, efx->net_dev,
2790 "Could not allocate an exclusive RSS"
2791 " context; allocated a shared one of"
2792 " different size."
2793 " Wanted %u, got %u.\n",
2794 efx->rss_spread, context_size);
2795 else if (mismatch)
2796 netif_warn(efx, probe, efx->net_dev,
2797 "Could not allocate an exclusive RSS"
2798 " context; allocated a shared one but"
2799 " could not apply custom"
2800 " indirection.\n");
2801 else
2802 netif_info(efx, probe, efx->net_dev,
2803 "Could not allocate an exclusive RSS"
2804 " context; allocated a shared one.\n");
2805 }
2806 }
2807 return rc;
2808 }
2809
2810 static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
2811 const u32 *rx_indir_table
2812 __attribute__ ((unused)),
2813 const u8 *key
2814 __attribute__ ((unused)))
2815 {
2816 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2817
2818 if (user)
2819 return -EOPNOTSUPP;
2820 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2821 return 0;
2822 return efx_ef10_rx_push_shared_rss_config(efx, NULL);
2823 }
2824
2825 static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
2826 {
2827 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
2828 (rx_queue->ptr_mask + 1) *
2829 sizeof(efx_qword_t),
2830 GFP_KERNEL);
2831 }
2832
2833 static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
2834 {
2835 MCDI_DECLARE_BUF(inbuf,
2836 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2837 EFX_BUF_SIZE));
2838 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2839 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
2840 struct efx_nic *efx = rx_queue->efx;
2841 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2842 size_t inlen;
2843 dma_addr_t dma_addr;
2844 int rc;
2845 int i;
2846 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
2847
2848 rx_queue->scatter_n = 0;
2849 rx_queue->scatter_len = 0;
2850
2851 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
2852 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
2853 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
2854 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
2855 efx_rx_queue_index(rx_queue));
2856 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
2857 INIT_RXQ_IN_FLAG_PREFIX, 1,
2858 INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
2859 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
2860 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
2861
2862 dma_addr = rx_queue->rxd.buf.dma_addr;
2863
2864 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
2865 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
2866
2867 for (i = 0; i < entries; ++i) {
2868 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
2869 dma_addr += EFX_BUF_SIZE;
2870 }
2871
2872 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
2873
2874 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
2875 NULL, 0, NULL);
2876 if (rc)
2877 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
2878 efx_rx_queue_index(rx_queue));
2879 }
2880
2881 static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
2882 {
2883 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
2884 MCDI_DECLARE_BUF_ERR(outbuf);
2885 struct efx_nic *efx = rx_queue->efx;
2886 size_t outlen;
2887 int rc;
2888
2889 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
2890 efx_rx_queue_index(rx_queue));
2891
2892 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
2893 outbuf, sizeof(outbuf), &outlen);
2894
2895 if (rc && rc != -EALREADY)
2896 goto fail;
2897
2898 return;
2899
2900 fail:
2901 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
2902 outbuf, outlen, rc);
2903 }
2904
2905 static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
2906 {
2907 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
2908 }
2909
2910 /* This creates an entry in the RX descriptor queue */
2911 static inline void
2912 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
2913 {
2914 struct efx_rx_buffer *rx_buf;
2915 efx_qword_t *rxd;
2916
2917 rxd = efx_rx_desc(rx_queue, index);
2918 rx_buf = efx_rx_buffer(rx_queue, index);
2919 EFX_POPULATE_QWORD_2(*rxd,
2920 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
2921 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
2922 }
2923
2924 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
2925 {
2926 struct efx_nic *efx = rx_queue->efx;
2927 unsigned int write_count;
2928 efx_dword_t reg;
2929
2930 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2931 write_count = rx_queue->added_count & ~7;
2932 if (rx_queue->notified_count == write_count)
2933 return;
2934
2935 do
2936 efx_ef10_build_rx_desc(
2937 rx_queue,
2938 rx_queue->notified_count & rx_queue->ptr_mask);
2939 while (++rx_queue->notified_count != write_count);
2940
2941 wmb();
2942 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
2943 write_count & rx_queue->ptr_mask);
2944 efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
2945 efx_rx_queue_index(rx_queue));
2946 }
2947
2948 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
2949
2950 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
2951 {
2952 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2953 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2954 efx_qword_t event;
2955
2956 EFX_POPULATE_QWORD_2(event,
2957 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2958 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
2959
2960 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2961
2962 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2963 * already swapped the data to little-endian order.
2964 */
2965 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2966 sizeof(efx_qword_t));
2967
2968 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
2969 inbuf, sizeof(inbuf), 0,
2970 efx_ef10_rx_defer_refill_complete, 0);
2971 }
2972
2973 static void
2974 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
2975 int rc, efx_dword_t *outbuf,
2976 size_t outlen_actual)
2977 {
2978 /* nothing to do */
2979 }
2980
2981 static int efx_ef10_ev_probe(struct efx_channel *channel)
2982 {
2983 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
2984 (channel->eventq_mask + 1) *
2985 sizeof(efx_qword_t),
2986 GFP_KERNEL);
2987 }
2988
2989 static void efx_ef10_ev_fini(struct efx_channel *channel)
2990 {
2991 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
2992 MCDI_DECLARE_BUF_ERR(outbuf);
2993 struct efx_nic *efx = channel->efx;
2994 size_t outlen;
2995 int rc;
2996
2997 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
2998
2999 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
3000 outbuf, sizeof(outbuf), &outlen);
3001
3002 if (rc && rc != -EALREADY)
3003 goto fail;
3004
3005 return;
3006
3007 fail:
3008 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
3009 outbuf, outlen, rc);
3010 }
3011
3012 static int efx_ef10_ev_init(struct efx_channel *channel)
3013 {
3014 MCDI_DECLARE_BUF(inbuf,
3015 MC_CMD_INIT_EVQ_V2_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
3016 EFX_BUF_SIZE));
3017 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_V2_OUT_LEN);
3018 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
3019 struct efx_nic *efx = channel->efx;
3020 struct efx_ef10_nic_data *nic_data;
3021 size_t inlen, outlen;
3022 unsigned int enabled, implemented;
3023 dma_addr_t dma_addr;
3024 int rc;
3025 int i;
3026
3027 nic_data = efx->nic_data;
3028
3029 /* Fill event queue with all ones (i.e. empty events) */
3030 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
3031
3032 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
3033 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
3034 /* INIT_EVQ expects index in vector table, not absolute */
3035 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
3036 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
3037 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
3038 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
3039 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
3040 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
3041 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
3042 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
3043
3044 if (nic_data->datapath_caps2 &
3045 1 << MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN) {
3046 /* Use the new generic approach to specifying event queue
3047 * configuration, requesting lower latency or higher throughput.
3048 * The options that actually get used appear in the output.
3049 */
3050 MCDI_POPULATE_DWORD_2(inbuf, INIT_EVQ_V2_IN_FLAGS,
3051 INIT_EVQ_V2_IN_FLAG_INTERRUPTING, 1,
3052 INIT_EVQ_V2_IN_FLAG_TYPE,
3053 MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO);
3054 } else {
3055 bool cut_thru = !(nic_data->datapath_caps &
3056 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
3057
3058 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
3059 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
3060 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
3061 INIT_EVQ_IN_FLAG_TX_MERGE, 1,
3062 INIT_EVQ_IN_FLAG_CUT_THRU, cut_thru);
3063 }
3064
3065 dma_addr = channel->eventq.buf.dma_addr;
3066 for (i = 0; i < entries; ++i) {
3067 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
3068 dma_addr += EFX_BUF_SIZE;
3069 }
3070
3071 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
3072
3073 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
3074 outbuf, sizeof(outbuf), &outlen);
3075
3076 if (outlen >= MC_CMD_INIT_EVQ_V2_OUT_LEN)
3077 netif_dbg(efx, drv, efx->net_dev,
3078 "Channel %d using event queue flags %08x\n",
3079 channel->channel,
3080 MCDI_DWORD(outbuf, INIT_EVQ_V2_OUT_FLAGS));
3081
3082 /* IRQ return is ignored */
3083 if (channel->channel || rc)
3084 return rc;
3085
3086 /* Successfully created event queue on channel 0 */
3087 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
3088 if (rc == -ENOSYS) {
3089 /* GET_WORKAROUNDS was implemented before this workaround,
3090 * thus it must be unavailable in this firmware.
3091 */
3092 nic_data->workaround_26807 = false;
3093 rc = 0;
3094 } else if (rc) {
3095 goto fail;
3096 } else {
3097 nic_data->workaround_26807 =
3098 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
3099
3100 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 &&
3101 !nic_data->workaround_26807) {
3102 unsigned int flags;
3103
3104 rc = efx_mcdi_set_workaround(efx,
3105 MC_CMD_WORKAROUND_BUG26807,
3106 true, &flags);
3107
3108 if (!rc) {
3109 if (flags &
3110 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
3111 netif_info(efx, drv, efx->net_dev,
3112 "other functions on NIC have been reset\n");
3113
3114 /* With MCFW v4.6.x and earlier, the
3115 * boot count will have incremented,
3116 * so re-read the warm_boot_count
3117 * value now to ensure this function
3118 * doesn't think it has changed next
3119 * time it checks.
3120 */
3121 rc = efx_ef10_get_warm_boot_count(efx);
3122 if (rc >= 0) {
3123 nic_data->warm_boot_count = rc;
3124 rc = 0;
3125 }
3126 }
3127 nic_data->workaround_26807 = true;
3128 } else if (rc == -EPERM) {
3129 rc = 0;
3130 }
3131 }
3132 }
3133
3134 if (!rc)
3135 return 0;
3136
3137 fail:
3138 efx_ef10_ev_fini(channel);
3139 return rc;
3140 }
3141
3142 static void efx_ef10_ev_remove(struct efx_channel *channel)
3143 {
3144 efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
3145 }
3146
3147 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
3148 unsigned int rx_queue_label)
3149 {
3150 struct efx_nic *efx = rx_queue->efx;
3151
3152 netif_info(efx, hw, efx->net_dev,
3153 "rx event arrived on queue %d labeled as queue %u\n",
3154 efx_rx_queue_index(rx_queue), rx_queue_label);
3155
3156 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
3157 }
3158
3159 static void
3160 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
3161 unsigned int actual, unsigned int expected)
3162 {
3163 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
3164 struct efx_nic *efx = rx_queue->efx;
3165
3166 netif_info(efx, hw, efx->net_dev,
3167 "dropped %d events (index=%d expected=%d)\n",
3168 dropped, actual, expected);
3169
3170 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
3171 }
3172
3173 /* partially received RX was aborted. clean up. */
3174 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
3175 {
3176 unsigned int rx_desc_ptr;
3177
3178 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
3179 "scattered RX aborted (dropping %u buffers)\n",
3180 rx_queue->scatter_n);
3181
3182 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
3183
3184 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
3185 0, EFX_RX_PKT_DISCARD);
3186
3187 rx_queue->removed_count += rx_queue->scatter_n;
3188 rx_queue->scatter_n = 0;
3189 rx_queue->scatter_len = 0;
3190 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
3191 }
3192
3193 static u16 efx_ef10_handle_rx_event_errors(struct efx_channel *channel,
3194 unsigned int n_packets,
3195 unsigned int rx_encap_hdr,
3196 unsigned int rx_l3_class,
3197 unsigned int rx_l4_class,
3198 const efx_qword_t *event)
3199 {
3200 struct efx_nic *efx = channel->efx;
3201
3202 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)) {
3203 if (!efx->loopback_selftest)
3204 channel->n_rx_eth_crc_err += n_packets;
3205 return EFX_RX_PKT_DISCARD;
3206 }
3207 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR)) {
3208 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN &&
3209 rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3210 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG &&
3211 rx_l3_class != ESE_DZ_L3_CLASS_IP6 &&
3212 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG))
3213 netdev_WARN(efx->net_dev,
3214 "invalid class for RX_IPCKSUM_ERR: event="
3215 EFX_QWORD_FMT "\n",
3216 EFX_QWORD_VAL(*event));
3217 if (!efx->loopback_selftest)
3218 *(rx_encap_hdr ?
3219 &channel->n_rx_outer_ip_hdr_chksum_err :
3220 &channel->n_rx_ip_hdr_chksum_err) += n_packets;
3221 return 0;
3222 }
3223 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) {
3224 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN &&
3225 ((rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3226 rx_l3_class != ESE_DZ_L3_CLASS_IP6) ||
3227 (rx_l4_class != ESE_DZ_L4_CLASS_TCP &&
3228 rx_l4_class != ESE_DZ_L4_CLASS_UDP))))
3229 netdev_WARN(efx->net_dev,
3230 "invalid class for RX_TCPUDP_CKSUM_ERR: event="
3231 EFX_QWORD_FMT "\n",
3232 EFX_QWORD_VAL(*event));
3233 if (!efx->loopback_selftest)
3234 *(rx_encap_hdr ?
3235 &channel->n_rx_outer_tcp_udp_chksum_err :
3236 &channel->n_rx_tcp_udp_chksum_err) += n_packets;
3237 return 0;
3238 }
3239 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_IP_INNER_CHKSUM_ERR)) {
3240 if (unlikely(!rx_encap_hdr))
3241 netdev_WARN(efx->net_dev,
3242 "invalid encapsulation type for RX_IP_INNER_CHKSUM_ERR: event="
3243 EFX_QWORD_FMT "\n",
3244 EFX_QWORD_VAL(*event));
3245 else if (unlikely(rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3246 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG &&
3247 rx_l3_class != ESE_DZ_L3_CLASS_IP6 &&
3248 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG))
3249 netdev_WARN(efx->net_dev,
3250 "invalid class for RX_IP_INNER_CHKSUM_ERR: event="
3251 EFX_QWORD_FMT "\n",
3252 EFX_QWORD_VAL(*event));
3253 if (!efx->loopback_selftest)
3254 channel->n_rx_inner_ip_hdr_chksum_err += n_packets;
3255 return 0;
3256 }
3257 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR)) {
3258 if (unlikely(!rx_encap_hdr))
3259 netdev_WARN(efx->net_dev,
3260 "invalid encapsulation type for RX_TCP_UDP_INNER_CHKSUM_ERR: event="
3261 EFX_QWORD_FMT "\n",
3262 EFX_QWORD_VAL(*event));
3263 else if (unlikely((rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3264 rx_l3_class != ESE_DZ_L3_CLASS_IP6) ||
3265 (rx_l4_class != ESE_DZ_L4_CLASS_TCP &&
3266 rx_l4_class != ESE_DZ_L4_CLASS_UDP)))
3267 netdev_WARN(efx->net_dev,
3268 "invalid class for RX_TCP_UDP_INNER_CHKSUM_ERR: event="
3269 EFX_QWORD_FMT "\n",
3270 EFX_QWORD_VAL(*event));
3271 if (!efx->loopback_selftest)
3272 channel->n_rx_inner_tcp_udp_chksum_err += n_packets;
3273 return 0;
3274 }
3275
3276 WARN_ON(1); /* No error bits were recognised */
3277 return 0;
3278 }
3279
3280 static int efx_ef10_handle_rx_event(struct efx_channel *channel,
3281 const efx_qword_t *event)
3282 {
3283 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label;
3284 unsigned int rx_l3_class, rx_l4_class, rx_encap_hdr;
3285 unsigned int n_descs, n_packets, i;
3286 struct efx_nic *efx = channel->efx;
3287 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3288 struct efx_rx_queue *rx_queue;
3289 efx_qword_t errors;
3290 bool rx_cont;
3291 u16 flags = 0;
3292
3293 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
3294 return 0;
3295
3296 /* Basic packet information */
3297 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
3298 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
3299 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
3300 rx_l3_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L3_CLASS);
3301 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
3302 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
3303 rx_encap_hdr =
3304 nic_data->datapath_caps &
3305 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) ?
3306 EFX_QWORD_FIELD(*event, ESF_EZ_RX_ENCAP_HDR) :
3307 ESE_EZ_ENCAP_HDR_NONE;
3308
3309 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
3310 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
3311 EFX_QWORD_FMT "\n",
3312 EFX_QWORD_VAL(*event));
3313
3314 rx_queue = efx_channel_get_rx_queue(channel);
3315
3316 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
3317 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
3318
3319 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
3320 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
3321
3322 if (n_descs != rx_queue->scatter_n + 1) {
3323 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3324
3325 /* detect rx abort */
3326 if (unlikely(n_descs == rx_queue->scatter_n)) {
3327 if (rx_queue->scatter_n == 0 || rx_bytes != 0)
3328 netdev_WARN(efx->net_dev,
3329 "invalid RX abort: scatter_n=%u event="
3330 EFX_QWORD_FMT "\n",
3331 rx_queue->scatter_n,
3332 EFX_QWORD_VAL(*event));
3333 efx_ef10_handle_rx_abort(rx_queue);
3334 return 0;
3335 }
3336
3337 /* Check that RX completion merging is valid, i.e.
3338 * the current firmware supports it and this is a
3339 * non-scattered packet.
3340 */
3341 if (!(nic_data->datapath_caps &
3342 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
3343 rx_queue->scatter_n != 0 || rx_cont) {
3344 efx_ef10_handle_rx_bad_lbits(
3345 rx_queue, next_ptr_lbits,
3346 (rx_queue->removed_count +
3347 rx_queue->scatter_n + 1) &
3348 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
3349 return 0;
3350 }
3351
3352 /* Merged completion for multiple non-scattered packets */
3353 rx_queue->scatter_n = 1;
3354 rx_queue->scatter_len = 0;
3355 n_packets = n_descs;
3356 ++channel->n_rx_merge_events;
3357 channel->n_rx_merge_packets += n_packets;
3358 flags |= EFX_RX_PKT_PREFIX_LEN;
3359 } else {
3360 ++rx_queue->scatter_n;
3361 rx_queue->scatter_len += rx_bytes;
3362 if (rx_cont)
3363 return 0;
3364 n_packets = 1;
3365 }
3366
3367 EFX_POPULATE_QWORD_5(errors, ESF_DZ_RX_ECRC_ERR, 1,
3368 ESF_DZ_RX_IPCKSUM_ERR, 1,
3369 ESF_DZ_RX_TCPUDP_CKSUM_ERR, 1,
3370 ESF_EZ_RX_IP_INNER_CHKSUM_ERR, 1,
3371 ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR, 1);
3372 EFX_AND_QWORD(errors, *event, errors);
3373 if (unlikely(!EFX_QWORD_IS_ZERO(errors))) {
3374 flags |= efx_ef10_handle_rx_event_errors(channel, n_packets,
3375 rx_encap_hdr,
3376 rx_l3_class, rx_l4_class,
3377 event);
3378 } else {
3379 bool tcpudp = rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
3380 rx_l4_class == ESE_DZ_L4_CLASS_UDP;
3381
3382 switch (rx_encap_hdr) {
3383 case ESE_EZ_ENCAP_HDR_VXLAN: /* VxLAN or GENEVE */
3384 flags |= EFX_RX_PKT_CSUMMED; /* outer UDP csum */
3385 if (tcpudp)
3386 flags |= EFX_RX_PKT_CSUM_LEVEL; /* inner L4 */
3387 break;
3388 case ESE_EZ_ENCAP_HDR_GRE:
3389 case ESE_EZ_ENCAP_HDR_NONE:
3390 if (tcpudp)
3391 flags |= EFX_RX_PKT_CSUMMED;
3392 break;
3393 default:
3394 netdev_WARN(efx->net_dev,
3395 "unknown encapsulation type: event="
3396 EFX_QWORD_FMT "\n",
3397 EFX_QWORD_VAL(*event));
3398 }
3399 }
3400
3401 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
3402 flags |= EFX_RX_PKT_TCP;
3403
3404 channel->irq_mod_score += 2 * n_packets;
3405
3406 /* Handle received packet(s) */
3407 for (i = 0; i < n_packets; i++) {
3408 efx_rx_packet(rx_queue,
3409 rx_queue->removed_count & rx_queue->ptr_mask,
3410 rx_queue->scatter_n, rx_queue->scatter_len,
3411 flags);
3412 rx_queue->removed_count += rx_queue->scatter_n;
3413 }
3414
3415 rx_queue->scatter_n = 0;
3416 rx_queue->scatter_len = 0;
3417
3418 return n_packets;
3419 }
3420
3421 static int
3422 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
3423 {
3424 struct efx_nic *efx = channel->efx;
3425 struct efx_tx_queue *tx_queue;
3426 unsigned int tx_ev_desc_ptr;
3427 unsigned int tx_ev_q_label;
3428 int tx_descs = 0;
3429
3430 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
3431 return 0;
3432
3433 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
3434 return 0;
3435
3436 /* Transmit completion */
3437 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
3438 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
3439 tx_queue = efx_channel_get_tx_queue(channel,
3440 tx_ev_q_label % EFX_TXQ_TYPES);
3441 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
3442 tx_queue->ptr_mask);
3443 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
3444
3445 return tx_descs;
3446 }
3447
3448 static void
3449 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
3450 {
3451 struct efx_nic *efx = channel->efx;
3452 int subcode;
3453
3454 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
3455
3456 switch (subcode) {
3457 case ESE_DZ_DRV_TIMER_EV:
3458 case ESE_DZ_DRV_WAKE_UP_EV:
3459 break;
3460 case ESE_DZ_DRV_START_UP_EV:
3461 /* event queue init complete. ok. */
3462 break;
3463 default:
3464 netif_err(efx, hw, efx->net_dev,
3465 "channel %d unknown driver event type %d"
3466 " (data " EFX_QWORD_FMT ")\n",
3467 channel->channel, subcode,
3468 EFX_QWORD_VAL(*event));
3469
3470 }
3471 }
3472
3473 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
3474 efx_qword_t *event)
3475 {
3476 struct efx_nic *efx = channel->efx;
3477 u32 subcode;
3478
3479 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
3480
3481 switch (subcode) {
3482 case EFX_EF10_TEST:
3483 channel->event_test_cpu = raw_smp_processor_id();
3484 break;
3485 case EFX_EF10_REFILL:
3486 /* The queue must be empty, so we won't receive any rx
3487 * events, so efx_process_channel() won't refill the
3488 * queue. Refill it here
3489 */
3490 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
3491 break;
3492 default:
3493 netif_err(efx, hw, efx->net_dev,
3494 "channel %d unknown driver event type %u"
3495 " (data " EFX_QWORD_FMT ")\n",
3496 channel->channel, (unsigned) subcode,
3497 EFX_QWORD_VAL(*event));
3498 }
3499 }
3500
3501 static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
3502 {
3503 struct efx_nic *efx = channel->efx;
3504 efx_qword_t event, *p_event;
3505 unsigned int read_ptr;
3506 int ev_code;
3507 int tx_descs = 0;
3508 int spent = 0;
3509
3510 if (quota <= 0)
3511 return spent;
3512
3513 read_ptr = channel->eventq_read_ptr;
3514
3515 for (;;) {
3516 p_event = efx_event(channel, read_ptr);
3517 event = *p_event;
3518
3519 if (!efx_event_present(&event))
3520 break;
3521
3522 EFX_SET_QWORD(*p_event);
3523
3524 ++read_ptr;
3525
3526 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
3527
3528 netif_vdbg(efx, drv, efx->net_dev,
3529 "processing event on %d " EFX_QWORD_FMT "\n",
3530 channel->channel, EFX_QWORD_VAL(event));
3531
3532 switch (ev_code) {
3533 case ESE_DZ_EV_CODE_MCDI_EV:
3534 efx_mcdi_process_event(channel, &event);
3535 break;
3536 case ESE_DZ_EV_CODE_RX_EV:
3537 spent += efx_ef10_handle_rx_event(channel, &event);
3538 if (spent >= quota) {
3539 /* XXX can we split a merged event to
3540 * avoid going over-quota?
3541 */
3542 spent = quota;
3543 goto out;
3544 }
3545 break;
3546 case ESE_DZ_EV_CODE_TX_EV:
3547 tx_descs += efx_ef10_handle_tx_event(channel, &event);
3548 if (tx_descs > efx->txq_entries) {
3549 spent = quota;
3550 goto out;
3551 } else if (++spent == quota) {
3552 goto out;
3553 }
3554 break;
3555 case ESE_DZ_EV_CODE_DRIVER_EV:
3556 efx_ef10_handle_driver_event(channel, &event);
3557 if (++spent == quota)
3558 goto out;
3559 break;
3560 case EFX_EF10_DRVGEN_EV:
3561 efx_ef10_handle_driver_generated_event(channel, &event);
3562 break;
3563 default:
3564 netif_err(efx, hw, efx->net_dev,
3565 "channel %d unknown event type %d"
3566 " (data " EFX_QWORD_FMT ")\n",
3567 channel->channel, ev_code,
3568 EFX_QWORD_VAL(event));
3569 }
3570 }
3571
3572 out:
3573 channel->eventq_read_ptr = read_ptr;
3574 return spent;
3575 }
3576
3577 static void efx_ef10_ev_read_ack(struct efx_channel *channel)
3578 {
3579 struct efx_nic *efx = channel->efx;
3580 efx_dword_t rptr;
3581
3582 if (EFX_EF10_WORKAROUND_35388(efx)) {
3583 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
3584 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
3585 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
3586 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
3587
3588 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3589 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
3590 ERF_DD_EVQ_IND_RPTR,
3591 (channel->eventq_read_ptr &
3592 channel->eventq_mask) >>
3593 ERF_DD_EVQ_IND_RPTR_WIDTH);
3594 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3595 channel->channel);
3596 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3597 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
3598 ERF_DD_EVQ_IND_RPTR,
3599 channel->eventq_read_ptr &
3600 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
3601 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3602 channel->channel);
3603 } else {
3604 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
3605 channel->eventq_read_ptr &
3606 channel->eventq_mask);
3607 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
3608 }
3609 }
3610
3611 static void efx_ef10_ev_test_generate(struct efx_channel *channel)
3612 {
3613 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
3614 struct efx_nic *efx = channel->efx;
3615 efx_qword_t event;
3616 int rc;
3617
3618 EFX_POPULATE_QWORD_2(event,
3619 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
3620 ESF_DZ_EV_DATA, EFX_EF10_TEST);
3621
3622 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
3623
3624 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3625 * already swapped the data to little-endian order.
3626 */
3627 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
3628 sizeof(efx_qword_t));
3629
3630 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
3631 NULL, 0, NULL);
3632 if (rc != 0)
3633 goto fail;
3634
3635 return;
3636
3637 fail:
3638 WARN_ON(true);
3639 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
3640 }
3641
3642 void efx_ef10_handle_drain_event(struct efx_nic *efx)
3643 {
3644 if (atomic_dec_and_test(&efx->active_queues))
3645 wake_up(&efx->flush_wq);
3646
3647 WARN_ON(atomic_read(&efx->active_queues) < 0);
3648 }
3649
3650 static int efx_ef10_fini_dmaq(struct efx_nic *efx)
3651 {
3652 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3653 struct efx_channel *channel;
3654 struct efx_tx_queue *tx_queue;
3655 struct efx_rx_queue *rx_queue;
3656 int pending;
3657
3658 /* If the MC has just rebooted, the TX/RX queues will have already been
3659 * torn down, but efx->active_queues needs to be set to zero.
3660 */
3661 if (nic_data->must_realloc_vis) {
3662 atomic_set(&efx->active_queues, 0);
3663 return 0;
3664 }
3665
3666 /* Do not attempt to write to the NIC during EEH recovery */
3667 if (efx->state != STATE_RECOVERY) {
3668 efx_for_each_channel(channel, efx) {
3669 efx_for_each_channel_rx_queue(rx_queue, channel)
3670 efx_ef10_rx_fini(rx_queue);
3671 efx_for_each_channel_tx_queue(tx_queue, channel)
3672 efx_ef10_tx_fini(tx_queue);
3673 }
3674
3675 wait_event_timeout(efx->flush_wq,
3676 atomic_read(&efx->active_queues) == 0,
3677 msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
3678 pending = atomic_read(&efx->active_queues);
3679 if (pending) {
3680 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
3681 pending);
3682 return -ETIMEDOUT;
3683 }
3684 }
3685
3686 return 0;
3687 }
3688
3689 static void efx_ef10_prepare_flr(struct efx_nic *efx)
3690 {
3691 atomic_set(&efx->active_queues, 0);
3692 }
3693
3694 static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
3695 const struct efx_filter_spec *right)
3696 {
3697 if ((left->match_flags ^ right->match_flags) |
3698 ((left->flags ^ right->flags) &
3699 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
3700 return false;
3701
3702 return memcmp(&left->outer_vid, &right->outer_vid,
3703 sizeof(struct efx_filter_spec) -
3704 offsetof(struct efx_filter_spec, outer_vid)) == 0;
3705 }
3706
3707 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
3708 {
3709 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
3710 return jhash2((const u32 *)&spec->outer_vid,
3711 (sizeof(struct efx_filter_spec) -
3712 offsetof(struct efx_filter_spec, outer_vid)) / 4,
3713 0);
3714 /* XXX should we randomise the initval? */
3715 }
3716
3717 /* Decide whether a filter should be exclusive or else should allow
3718 * delivery to additional recipients. Currently we decide that
3719 * filters for specific local unicast MAC and IP addresses are
3720 * exclusive.
3721 */
3722 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
3723 {
3724 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
3725 !is_multicast_ether_addr(spec->loc_mac))
3726 return true;
3727
3728 if ((spec->match_flags &
3729 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
3730 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
3731 if (spec->ether_type == htons(ETH_P_IP) &&
3732 !ipv4_is_multicast(spec->loc_host[0]))
3733 return true;
3734 if (spec->ether_type == htons(ETH_P_IPV6) &&
3735 ((const u8 *)spec->loc_host)[0] != 0xff)
3736 return true;
3737 }
3738
3739 return false;
3740 }
3741
3742 static struct efx_filter_spec *
3743 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
3744 unsigned int filter_idx)
3745 {
3746 return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
3747 ~EFX_EF10_FILTER_FLAGS);
3748 }
3749
3750 static unsigned int
3751 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
3752 unsigned int filter_idx)
3753 {
3754 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
3755 }
3756
3757 static void
3758 efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
3759 unsigned int filter_idx,
3760 const struct efx_filter_spec *spec,
3761 unsigned int flags)
3762 {
3763 table->entry[filter_idx].spec = (unsigned long)spec | flags;
3764 }
3765
3766 static void
3767 efx_ef10_filter_push_prep_set_match_fields(struct efx_nic *efx,
3768 const struct efx_filter_spec *spec,
3769 efx_dword_t *inbuf)
3770 {
3771 enum efx_encap_type encap_type = efx_filter_get_encap_type(spec);
3772 u32 match_fields = 0, uc_match, mc_match;
3773
3774 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3775 efx_ef10_filter_is_exclusive(spec) ?
3776 MC_CMD_FILTER_OP_IN_OP_INSERT :
3777 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
3778
3779 /* Convert match flags and values. Unlike almost
3780 * everything else in MCDI, these fields are in
3781 * network byte order.
3782 */
3783 #define COPY_VALUE(value, mcdi_field) \
3784 do { \
3785 match_fields |= \
3786 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3787 mcdi_field ## _LBN; \
3788 BUILD_BUG_ON( \
3789 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
3790 sizeof(value)); \
3791 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
3792 &value, sizeof(value)); \
3793 } while (0)
3794 #define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
3795 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
3796 COPY_VALUE(spec->gen_field, mcdi_field); \
3797 }
3798 /* Handle encap filters first. They will always be mismatch
3799 * (unknown UC or MC) filters
3800 */
3801 if (encap_type) {
3802 /* ether_type and outer_ip_proto need to be variables
3803 * because COPY_VALUE wants to memcpy them
3804 */
3805 __be16 ether_type =
3806 htons(encap_type & EFX_ENCAP_FLAG_IPV6 ?
3807 ETH_P_IPV6 : ETH_P_IP);
3808 u8 vni_type = MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE;
3809 u8 outer_ip_proto;
3810
3811 switch (encap_type & EFX_ENCAP_TYPES_MASK) {
3812 case EFX_ENCAP_TYPE_VXLAN:
3813 vni_type = MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN;
3814 /* fallthrough */
3815 case EFX_ENCAP_TYPE_GENEVE:
3816 COPY_VALUE(ether_type, ETHER_TYPE);
3817 outer_ip_proto = IPPROTO_UDP;
3818 COPY_VALUE(outer_ip_proto, IP_PROTO);
3819 /* We always need to set the type field, even
3820 * though we're not matching on the TNI.
3821 */
3822 MCDI_POPULATE_DWORD_1(inbuf,
3823 FILTER_OP_EXT_IN_VNI_OR_VSID,
3824 FILTER_OP_EXT_IN_VNI_TYPE,
3825 vni_type);
3826 break;
3827 case EFX_ENCAP_TYPE_NVGRE:
3828 COPY_VALUE(ether_type, ETHER_TYPE);
3829 outer_ip_proto = IPPROTO_GRE;
3830 COPY_VALUE(outer_ip_proto, IP_PROTO);
3831 break;
3832 default:
3833 WARN_ON(1);
3834 }
3835
3836 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN;
3837 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN;
3838 } else {
3839 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
3840 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN;
3841 }
3842
3843 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
3844 match_fields |=
3845 is_multicast_ether_addr(spec->loc_mac) ?
3846 1 << mc_match :
3847 1 << uc_match;
3848 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
3849 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
3850 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
3851 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
3852 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
3853 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
3854 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
3855 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
3856 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
3857 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
3858 #undef COPY_FIELD
3859 #undef COPY_VALUE
3860 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
3861 match_fields);
3862 }
3863
3864 static void efx_ef10_filter_push_prep(struct efx_nic *efx,
3865 const struct efx_filter_spec *spec,
3866 efx_dword_t *inbuf, u64 handle,
3867 bool replacing)
3868 {
3869 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3870 u32 flags = spec->flags;
3871
3872 memset(inbuf, 0, MC_CMD_FILTER_OP_EXT_IN_LEN);
3873
3874 /* Remove RSS flag if we don't have an RSS context. */
3875 if (flags & EFX_FILTER_FLAG_RX_RSS &&
3876 spec->rss_context == EFX_FILTER_RSS_CONTEXT_DEFAULT &&
3877 nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID)
3878 flags &= ~EFX_FILTER_FLAG_RX_RSS;
3879
3880 if (replacing) {
3881 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3882 MC_CMD_FILTER_OP_IN_OP_REPLACE);
3883 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
3884 } else {
3885 efx_ef10_filter_push_prep_set_match_fields(efx, spec, inbuf);
3886 }
3887
3888 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
3889 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
3890 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3891 MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
3892 MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
3893 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
3894 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
3895 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
3896 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
3897 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3898 0 : spec->dmaq_id);
3899 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
3900 (flags & EFX_FILTER_FLAG_RX_RSS) ?
3901 MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
3902 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
3903 if (flags & EFX_FILTER_FLAG_RX_RSS)
3904 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
3905 spec->rss_context !=
3906 EFX_FILTER_RSS_CONTEXT_DEFAULT ?
3907 spec->rss_context : nic_data->rx_rss_context);
3908 }
3909
3910 static int efx_ef10_filter_push(struct efx_nic *efx,
3911 const struct efx_filter_spec *spec,
3912 u64 *handle, bool replacing)
3913 {
3914 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
3915 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_EXT_OUT_LEN);
3916 int rc;
3917
3918 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
3919 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3920 outbuf, sizeof(outbuf), NULL);
3921 if (rc == 0)
3922 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
3923 if (rc == -ENOSPC)
3924 rc = -EBUSY; /* to match efx_farch_filter_insert() */
3925 return rc;
3926 }
3927
3928 static u32 efx_ef10_filter_mcdi_flags_from_spec(const struct efx_filter_spec *spec)
3929 {
3930 enum efx_encap_type encap_type = efx_filter_get_encap_type(spec);
3931 unsigned int match_flags = spec->match_flags;
3932 unsigned int uc_match, mc_match;
3933 u32 mcdi_flags = 0;
3934
3935 #define MAP_FILTER_TO_MCDI_FLAG(gen_flag, mcdi_field, encap) { \
3936 unsigned int old_match_flags = match_flags; \
3937 match_flags &= ~EFX_FILTER_MATCH_ ## gen_flag; \
3938 if (match_flags != old_match_flags) \
3939 mcdi_flags |= \
3940 (1 << ((encap) ? \
3941 MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ ## \
3942 mcdi_field ## _LBN : \
3943 MC_CMD_FILTER_OP_EXT_IN_MATCH_ ##\
3944 mcdi_field ## _LBN)); \
3945 }
3946 /* inner or outer based on encap type */
3947 MAP_FILTER_TO_MCDI_FLAG(REM_HOST, SRC_IP, encap_type);
3948 MAP_FILTER_TO_MCDI_FLAG(LOC_HOST, DST_IP, encap_type);
3949 MAP_FILTER_TO_MCDI_FLAG(REM_MAC, SRC_MAC, encap_type);
3950 MAP_FILTER_TO_MCDI_FLAG(REM_PORT, SRC_PORT, encap_type);
3951 MAP_FILTER_TO_MCDI_FLAG(LOC_MAC, DST_MAC, encap_type);
3952 MAP_FILTER_TO_MCDI_FLAG(LOC_PORT, DST_PORT, encap_type);
3953 MAP_FILTER_TO_MCDI_FLAG(ETHER_TYPE, ETHER_TYPE, encap_type);
3954 MAP_FILTER_TO_MCDI_FLAG(IP_PROTO, IP_PROTO, encap_type);
3955 /* always outer */
3956 MAP_FILTER_TO_MCDI_FLAG(INNER_VID, INNER_VLAN, false);
3957 MAP_FILTER_TO_MCDI_FLAG(OUTER_VID, OUTER_VLAN, false);
3958 #undef MAP_FILTER_TO_MCDI_FLAG
3959
3960 /* special handling for encap type, and mismatch */
3961 if (encap_type) {
3962 match_flags &= ~EFX_FILTER_MATCH_ENCAP_TYPE;
3963 mcdi_flags |=
3964 (1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN);
3965 mcdi_flags |= (1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN);
3966
3967 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN;
3968 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN;
3969 } else {
3970 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
3971 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN;
3972 }
3973
3974 if (match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) {
3975 match_flags &= ~EFX_FILTER_MATCH_LOC_MAC_IG;
3976 mcdi_flags |=
3977 is_multicast_ether_addr(spec->loc_mac) ?
3978 1 << mc_match :
3979 1 << uc_match;
3980 }
3981
3982 /* Did we map them all? */
3983 WARN_ON_ONCE(match_flags);
3984
3985 return mcdi_flags;
3986 }
3987
3988 static int efx_ef10_filter_pri(struct efx_ef10_filter_table *table,
3989 const struct efx_filter_spec *spec)
3990 {
3991 u32 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
3992 unsigned int match_pri;
3993
3994 for (match_pri = 0;
3995 match_pri < table->rx_match_count;
3996 match_pri++)
3997 if (table->rx_match_mcdi_flags[match_pri] == mcdi_flags)
3998 return match_pri;
3999
4000 return -EPROTONOSUPPORT;
4001 }
4002
4003 static s32 efx_ef10_filter_insert(struct efx_nic *efx,
4004 struct efx_filter_spec *spec,
4005 bool replace_equal)
4006 {
4007 struct efx_ef10_filter_table *table = efx->filter_state;
4008 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
4009 struct efx_filter_spec *saved_spec;
4010 unsigned int match_pri, hash;
4011 unsigned int priv_flags;
4012 bool replacing = false;
4013 int ins_index = -1;
4014 DEFINE_WAIT(wait);
4015 bool is_mc_recip;
4016 s32 rc;
4017
4018 /* For now, only support RX filters */
4019 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
4020 EFX_FILTER_FLAG_RX)
4021 return -EINVAL;
4022
4023 rc = efx_ef10_filter_pri(table, spec);
4024 if (rc < 0)
4025 return rc;
4026 match_pri = rc;
4027
4028 hash = efx_ef10_filter_hash(spec);
4029 is_mc_recip = efx_filter_is_mc_recipient(spec);
4030 if (is_mc_recip)
4031 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
4032
4033 /* Find any existing filters with the same match tuple or
4034 * else a free slot to insert at. If any of them are busy,
4035 * we have to wait and retry.
4036 */
4037 for (;;) {
4038 unsigned int depth = 1;
4039 unsigned int i;
4040
4041 spin_lock_bh(&efx->filter_lock);
4042
4043 for (;;) {
4044 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4045 saved_spec = efx_ef10_filter_entry_spec(table, i);
4046
4047 if (!saved_spec) {
4048 if (ins_index < 0)
4049 ins_index = i;
4050 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
4051 if (table->entry[i].spec &
4052 EFX_EF10_FILTER_FLAG_BUSY)
4053 break;
4054 if (spec->priority < saved_spec->priority &&
4055 spec->priority != EFX_FILTER_PRI_AUTO) {
4056 rc = -EPERM;
4057 goto out_unlock;
4058 }
4059 if (!is_mc_recip) {
4060 /* This is the only one */
4061 if (spec->priority ==
4062 saved_spec->priority &&
4063 !replace_equal) {
4064 rc = -EEXIST;
4065 goto out_unlock;
4066 }
4067 ins_index = i;
4068 goto found;
4069 } else if (spec->priority >
4070 saved_spec->priority ||
4071 (spec->priority ==
4072 saved_spec->priority &&
4073 replace_equal)) {
4074 if (ins_index < 0)
4075 ins_index = i;
4076 else
4077 __set_bit(depth, mc_rem_map);
4078 }
4079 }
4080
4081 /* Once we reach the maximum search depth, use
4082 * the first suitable slot or return -EBUSY if
4083 * there was none
4084 */
4085 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
4086 if (ins_index < 0) {
4087 rc = -EBUSY;
4088 goto out_unlock;
4089 }
4090 goto found;
4091 }
4092
4093 ++depth;
4094 }
4095
4096 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
4097 spin_unlock_bh(&efx->filter_lock);
4098 schedule();
4099 }
4100
4101 found:
4102 /* Create a software table entry if necessary, and mark it
4103 * busy. We might yet fail to insert, but any attempt to
4104 * insert a conflicting filter while we're waiting for the
4105 * firmware must find the busy entry.
4106 */
4107 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
4108 if (saved_spec) {
4109 if (spec->priority == EFX_FILTER_PRI_AUTO &&
4110 saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
4111 /* Just make sure it won't be removed */
4112 if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
4113 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
4114 table->entry[ins_index].spec &=
4115 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
4116 rc = ins_index;
4117 goto out_unlock;
4118 }
4119 replacing = true;
4120 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
4121 } else {
4122 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
4123 if (!saved_spec) {
4124 rc = -ENOMEM;
4125 goto out_unlock;
4126 }
4127 *saved_spec = *spec;
4128 priv_flags = 0;
4129 }
4130 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
4131 priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
4132
4133 /* Mark lower-priority multicast recipients busy prior to removal */
4134 if (is_mc_recip) {
4135 unsigned int depth, i;
4136
4137 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
4138 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4139 if (test_bit(depth, mc_rem_map))
4140 table->entry[i].spec |=
4141 EFX_EF10_FILTER_FLAG_BUSY;
4142 }
4143 }
4144
4145 spin_unlock_bh(&efx->filter_lock);
4146
4147 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
4148 replacing);
4149
4150 /* Finalise the software table entry */
4151 spin_lock_bh(&efx->filter_lock);
4152 if (rc == 0) {
4153 if (replacing) {
4154 /* Update the fields that may differ */
4155 if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
4156 saved_spec->flags |=
4157 EFX_FILTER_FLAG_RX_OVER_AUTO;
4158 saved_spec->priority = spec->priority;
4159 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
4160 saved_spec->flags |= spec->flags;
4161 saved_spec->rss_context = spec->rss_context;
4162 saved_spec->dmaq_id = spec->dmaq_id;
4163 }
4164 } else if (!replacing) {
4165 kfree(saved_spec);
4166 saved_spec = NULL;
4167 }
4168 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
4169
4170 /* Remove and finalise entries for lower-priority multicast
4171 * recipients
4172 */
4173 if (is_mc_recip) {
4174 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
4175 unsigned int depth, i;
4176
4177 memset(inbuf, 0, sizeof(inbuf));
4178
4179 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
4180 if (!test_bit(depth, mc_rem_map))
4181 continue;
4182
4183 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4184 saved_spec = efx_ef10_filter_entry_spec(table, i);
4185 priv_flags = efx_ef10_filter_entry_flags(table, i);
4186
4187 if (rc == 0) {
4188 spin_unlock_bh(&efx->filter_lock);
4189 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4190 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4191 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4192 table->entry[i].handle);
4193 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
4194 inbuf, sizeof(inbuf),
4195 NULL, 0, NULL);
4196 spin_lock_bh(&efx->filter_lock);
4197 }
4198
4199 if (rc == 0) {
4200 kfree(saved_spec);
4201 saved_spec = NULL;
4202 priv_flags = 0;
4203 } else {
4204 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
4205 }
4206 efx_ef10_filter_set_entry(table, i, saved_spec,
4207 priv_flags);
4208 }
4209 }
4210
4211 /* If successful, return the inserted filter ID */
4212 if (rc == 0)
4213 rc = efx_ef10_make_filter_id(match_pri, ins_index);
4214
4215 wake_up_all(&table->waitq);
4216 out_unlock:
4217 spin_unlock_bh(&efx->filter_lock);
4218 finish_wait(&table->waitq, &wait);
4219 return rc;
4220 }
4221
4222 static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
4223 {
4224 /* no need to do anything here on EF10 */
4225 }
4226
4227 /* Remove a filter.
4228 * If !by_index, remove by ID
4229 * If by_index, remove by index
4230 * Filter ID may come from userland and must be range-checked.
4231 */
4232 static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
4233 unsigned int priority_mask,
4234 u32 filter_id, bool by_index)
4235 {
4236 unsigned int filter_idx = efx_ef10_filter_get_unsafe_id(filter_id);
4237 struct efx_ef10_filter_table *table = efx->filter_state;
4238 MCDI_DECLARE_BUF(inbuf,
4239 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
4240 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
4241 struct efx_filter_spec *spec;
4242 DEFINE_WAIT(wait);
4243 int rc;
4244
4245 /* Find the software table entry and mark it busy. Don't
4246 * remove it yet; any attempt to update while we're waiting
4247 * for the firmware must find the busy entry.
4248 */
4249 for (;;) {
4250 spin_lock_bh(&efx->filter_lock);
4251 if (!(table->entry[filter_idx].spec &
4252 EFX_EF10_FILTER_FLAG_BUSY))
4253 break;
4254 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
4255 spin_unlock_bh(&efx->filter_lock);
4256 schedule();
4257 }
4258
4259 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4260 if (!spec ||
4261 (!by_index &&
4262 efx_ef10_filter_pri(table, spec) !=
4263 efx_ef10_filter_get_unsafe_pri(filter_id))) {
4264 rc = -ENOENT;
4265 goto out_unlock;
4266 }
4267
4268 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
4269 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
4270 /* Just remove flags */
4271 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
4272 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
4273 rc = 0;
4274 goto out_unlock;
4275 }
4276
4277 if (!(priority_mask & (1U << spec->priority))) {
4278 rc = -ENOENT;
4279 goto out_unlock;
4280 }
4281
4282 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4283 spin_unlock_bh(&efx->filter_lock);
4284
4285 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
4286 /* Reset to an automatic filter */
4287
4288 struct efx_filter_spec new_spec = *spec;
4289
4290 new_spec.priority = EFX_FILTER_PRI_AUTO;
4291 new_spec.flags = (EFX_FILTER_FLAG_RX |
4292 (efx_rss_enabled(efx) ?
4293 EFX_FILTER_FLAG_RX_RSS : 0));
4294 new_spec.dmaq_id = 0;
4295 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
4296 rc = efx_ef10_filter_push(efx, &new_spec,
4297 &table->entry[filter_idx].handle,
4298 true);
4299
4300 spin_lock_bh(&efx->filter_lock);
4301 if (rc == 0)
4302 *spec = new_spec;
4303 } else {
4304 /* Really remove the filter */
4305
4306 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4307 efx_ef10_filter_is_exclusive(spec) ?
4308 MC_CMD_FILTER_OP_IN_OP_REMOVE :
4309 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4310 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4311 table->entry[filter_idx].handle);
4312 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP,
4313 inbuf, sizeof(inbuf), NULL, 0, NULL);
4314
4315 spin_lock_bh(&efx->filter_lock);
4316 if ((rc == 0) || (rc == -ENOENT)) {
4317 /* Filter removed OK or didn't actually exist */
4318 kfree(spec);
4319 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4320 } else {
4321 efx_mcdi_display_error(efx, MC_CMD_FILTER_OP,
4322 MC_CMD_FILTER_OP_IN_LEN,
4323 NULL, 0, rc);
4324 }
4325 }
4326
4327 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
4328 wake_up_all(&table->waitq);
4329 out_unlock:
4330 spin_unlock_bh(&efx->filter_lock);
4331 finish_wait(&table->waitq, &wait);
4332 return rc;
4333 }
4334
4335 static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
4336 enum efx_filter_priority priority,
4337 u32 filter_id)
4338 {
4339 return efx_ef10_filter_remove_internal(efx, 1U << priority,
4340 filter_id, false);
4341 }
4342
4343 static void efx_ef10_filter_remove_unsafe(struct efx_nic *efx,
4344 enum efx_filter_priority priority,
4345 u32 filter_id)
4346 {
4347 if (filter_id == EFX_EF10_FILTER_ID_INVALID)
4348 return;
4349 efx_ef10_filter_remove_internal(efx, 1U << priority, filter_id, true);
4350 }
4351
4352 static int efx_ef10_filter_get_safe(struct efx_nic *efx,
4353 enum efx_filter_priority priority,
4354 u32 filter_id, struct efx_filter_spec *spec)
4355 {
4356 unsigned int filter_idx = efx_ef10_filter_get_unsafe_id(filter_id);
4357 struct efx_ef10_filter_table *table = efx->filter_state;
4358 const struct efx_filter_spec *saved_spec;
4359 int rc;
4360
4361 spin_lock_bh(&efx->filter_lock);
4362 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
4363 if (saved_spec && saved_spec->priority == priority &&
4364 efx_ef10_filter_pri(table, saved_spec) ==
4365 efx_ef10_filter_get_unsafe_pri(filter_id)) {
4366 *spec = *saved_spec;
4367 rc = 0;
4368 } else {
4369 rc = -ENOENT;
4370 }
4371 spin_unlock_bh(&efx->filter_lock);
4372 return rc;
4373 }
4374
4375 static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
4376 enum efx_filter_priority priority)
4377 {
4378 unsigned int priority_mask;
4379 unsigned int i;
4380 int rc;
4381
4382 priority_mask = (((1U << (priority + 1)) - 1) &
4383 ~(1U << EFX_FILTER_PRI_AUTO));
4384
4385 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4386 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
4387 i, true);
4388 if (rc && rc != -ENOENT)
4389 return rc;
4390 }
4391
4392 return 0;
4393 }
4394
4395 static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
4396 enum efx_filter_priority priority)
4397 {
4398 struct efx_ef10_filter_table *table = efx->filter_state;
4399 unsigned int filter_idx;
4400 s32 count = 0;
4401
4402 spin_lock_bh(&efx->filter_lock);
4403 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4404 if (table->entry[filter_idx].spec &&
4405 efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
4406 priority)
4407 ++count;
4408 }
4409 spin_unlock_bh(&efx->filter_lock);
4410 return count;
4411 }
4412
4413 static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
4414 {
4415 struct efx_ef10_filter_table *table = efx->filter_state;
4416
4417 return table->rx_match_count * HUNT_FILTER_TBL_ROWS * 2;
4418 }
4419
4420 static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
4421 enum efx_filter_priority priority,
4422 u32 *buf, u32 size)
4423 {
4424 struct efx_ef10_filter_table *table = efx->filter_state;
4425 struct efx_filter_spec *spec;
4426 unsigned int filter_idx;
4427 s32 count = 0;
4428
4429 spin_lock_bh(&efx->filter_lock);
4430 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4431 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4432 if (spec && spec->priority == priority) {
4433 if (count == size) {
4434 count = -EMSGSIZE;
4435 break;
4436 }
4437 buf[count++] =
4438 efx_ef10_make_filter_id(
4439 efx_ef10_filter_pri(table, spec),
4440 filter_idx);
4441 }
4442 }
4443 spin_unlock_bh(&efx->filter_lock);
4444 return count;
4445 }
4446
4447 #ifdef CONFIG_RFS_ACCEL
4448
4449 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
4450
4451 static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
4452 struct efx_filter_spec *spec)
4453 {
4454 struct efx_ef10_filter_table *table = efx->filter_state;
4455 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
4456 struct efx_filter_spec *saved_spec;
4457 unsigned int hash, i, depth = 1;
4458 bool replacing = false;
4459 int ins_index = -1;
4460 u64 cookie;
4461 s32 rc;
4462
4463 /* Must be an RX filter without RSS and not for a multicast
4464 * destination address (RFS only works for connected sockets).
4465 * These restrictions allow us to pass only a tiny amount of
4466 * data through to the completion function.
4467 */
4468 EFX_WARN_ON_PARANOID(spec->flags !=
4469 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
4470 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
4471 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
4472
4473 hash = efx_ef10_filter_hash(spec);
4474
4475 spin_lock_bh(&efx->filter_lock);
4476
4477 /* Find any existing filter with the same match tuple or else
4478 * a free slot to insert at. If an existing filter is busy,
4479 * we have to give up.
4480 */
4481 for (;;) {
4482 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4483 saved_spec = efx_ef10_filter_entry_spec(table, i);
4484
4485 if (!saved_spec) {
4486 if (ins_index < 0)
4487 ins_index = i;
4488 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
4489 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
4490 rc = -EBUSY;
4491 goto fail_unlock;
4492 }
4493 if (spec->priority < saved_spec->priority) {
4494 rc = -EPERM;
4495 goto fail_unlock;
4496 }
4497 ins_index = i;
4498 break;
4499 }
4500
4501 /* Once we reach the maximum search depth, use the
4502 * first suitable slot or return -EBUSY if there was
4503 * none
4504 */
4505 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
4506 if (ins_index < 0) {
4507 rc = -EBUSY;
4508 goto fail_unlock;
4509 }
4510 break;
4511 }
4512
4513 ++depth;
4514 }
4515
4516 /* Create a software table entry if necessary, and mark it
4517 * busy. We might yet fail to insert, but any attempt to
4518 * insert a conflicting filter while we're waiting for the
4519 * firmware must find the busy entry.
4520 */
4521 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
4522 if (saved_spec) {
4523 replacing = true;
4524 } else {
4525 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
4526 if (!saved_spec) {
4527 rc = -ENOMEM;
4528 goto fail_unlock;
4529 }
4530 *saved_spec = *spec;
4531 }
4532 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
4533 EFX_EF10_FILTER_FLAG_BUSY);
4534
4535 spin_unlock_bh(&efx->filter_lock);
4536
4537 /* Pack up the variables needed on completion */
4538 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
4539
4540 efx_ef10_filter_push_prep(efx, spec, inbuf,
4541 table->entry[ins_index].handle, replacing);
4542 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
4543 MC_CMD_FILTER_OP_OUT_LEN,
4544 efx_ef10_filter_rfs_insert_complete, cookie);
4545
4546 return ins_index;
4547
4548 fail_unlock:
4549 spin_unlock_bh(&efx->filter_lock);
4550 return rc;
4551 }
4552
4553 static void
4554 efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
4555 int rc, efx_dword_t *outbuf,
4556 size_t outlen_actual)
4557 {
4558 struct efx_ef10_filter_table *table = efx->filter_state;
4559 unsigned int ins_index, dmaq_id;
4560 struct efx_filter_spec *spec;
4561 bool replacing;
4562
4563 /* Unpack the cookie */
4564 replacing = cookie >> 31;
4565 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
4566 dmaq_id = cookie & 0xffff;
4567
4568 spin_lock_bh(&efx->filter_lock);
4569 spec = efx_ef10_filter_entry_spec(table, ins_index);
4570 if (rc == 0) {
4571 table->entry[ins_index].handle =
4572 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
4573 if (replacing)
4574 spec->dmaq_id = dmaq_id;
4575 } else if (!replacing) {
4576 kfree(spec);
4577 spec = NULL;
4578 }
4579 efx_ef10_filter_set_entry(table, ins_index, spec, 0);
4580 spin_unlock_bh(&efx->filter_lock);
4581
4582 wake_up_all(&table->waitq);
4583 }
4584
4585 static void
4586 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
4587 unsigned long filter_idx,
4588 int rc, efx_dword_t *outbuf,
4589 size_t outlen_actual);
4590
4591 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
4592 unsigned int filter_idx)
4593 {
4594 struct efx_ef10_filter_table *table = efx->filter_state;
4595 struct efx_filter_spec *spec =
4596 efx_ef10_filter_entry_spec(table, filter_idx);
4597 MCDI_DECLARE_BUF(inbuf,
4598 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
4599 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
4600
4601 if (!spec ||
4602 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
4603 spec->priority != EFX_FILTER_PRI_HINT ||
4604 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
4605 flow_id, filter_idx))
4606 return false;
4607
4608 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4609 MC_CMD_FILTER_OP_IN_OP_REMOVE);
4610 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4611 table->entry[filter_idx].handle);
4612 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
4613 efx_ef10_filter_rfs_expire_complete, filter_idx))
4614 return false;
4615
4616 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4617 return true;
4618 }
4619
4620 static void
4621 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
4622 unsigned long filter_idx,
4623 int rc, efx_dword_t *outbuf,
4624 size_t outlen_actual)
4625 {
4626 struct efx_ef10_filter_table *table = efx->filter_state;
4627 struct efx_filter_spec *spec =
4628 efx_ef10_filter_entry_spec(table, filter_idx);
4629
4630 spin_lock_bh(&efx->filter_lock);
4631 if (rc == 0) {
4632 kfree(spec);
4633 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4634 }
4635 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
4636 wake_up_all(&table->waitq);
4637 spin_unlock_bh(&efx->filter_lock);
4638 }
4639
4640 #endif /* CONFIG_RFS_ACCEL */
4641
4642 static int efx_ef10_filter_match_flags_from_mcdi(bool encap, u32 mcdi_flags)
4643 {
4644 int match_flags = 0;
4645
4646 #define MAP_FLAG(gen_flag, mcdi_field) do { \
4647 u32 old_mcdi_flags = mcdi_flags; \
4648 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ ## \
4649 mcdi_field ## _LBN); \
4650 if (mcdi_flags != old_mcdi_flags) \
4651 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
4652 } while (0)
4653
4654 if (encap) {
4655 /* encap filters must specify encap type */
4656 match_flags |= EFX_FILTER_MATCH_ENCAP_TYPE;
4657 /* and imply ethertype and ip proto */
4658 mcdi_flags &=
4659 ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN);
4660 mcdi_flags &=
4661 ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN);
4662 /* VLAN tags refer to the outer packet */
4663 MAP_FLAG(INNER_VID, INNER_VLAN);
4664 MAP_FLAG(OUTER_VID, OUTER_VLAN);
4665 /* everything else refers to the inner packet */
4666 MAP_FLAG(LOC_MAC_IG, IFRM_UNKNOWN_UCAST_DST);
4667 MAP_FLAG(LOC_MAC_IG, IFRM_UNKNOWN_MCAST_DST);
4668 MAP_FLAG(REM_HOST, IFRM_SRC_IP);
4669 MAP_FLAG(LOC_HOST, IFRM_DST_IP);
4670 MAP_FLAG(REM_MAC, IFRM_SRC_MAC);
4671 MAP_FLAG(REM_PORT, IFRM_SRC_PORT);
4672 MAP_FLAG(LOC_MAC, IFRM_DST_MAC);
4673 MAP_FLAG(LOC_PORT, IFRM_DST_PORT);
4674 MAP_FLAG(ETHER_TYPE, IFRM_ETHER_TYPE);
4675 MAP_FLAG(IP_PROTO, IFRM_IP_PROTO);
4676 } else {
4677 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
4678 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
4679 MAP_FLAG(REM_HOST, SRC_IP);
4680 MAP_FLAG(LOC_HOST, DST_IP);
4681 MAP_FLAG(REM_MAC, SRC_MAC);
4682 MAP_FLAG(REM_PORT, SRC_PORT);
4683 MAP_FLAG(LOC_MAC, DST_MAC);
4684 MAP_FLAG(LOC_PORT, DST_PORT);
4685 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
4686 MAP_FLAG(INNER_VID, INNER_VLAN);
4687 MAP_FLAG(OUTER_VID, OUTER_VLAN);
4688 MAP_FLAG(IP_PROTO, IP_PROTO);
4689 }
4690 #undef MAP_FLAG
4691
4692 /* Did we map them all? */
4693 if (mcdi_flags)
4694 return -EINVAL;
4695
4696 return match_flags;
4697 }
4698
4699 static void efx_ef10_filter_cleanup_vlans(struct efx_nic *efx)
4700 {
4701 struct efx_ef10_filter_table *table = efx->filter_state;
4702 struct efx_ef10_filter_vlan *vlan, *next_vlan;
4703
4704 /* See comment in efx_ef10_filter_table_remove() */
4705 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4706 return;
4707
4708 if (!table)
4709 return;
4710
4711 list_for_each_entry_safe(vlan, next_vlan, &table->vlan_list, list)
4712 efx_ef10_filter_del_vlan_internal(efx, vlan);
4713 }
4714
4715 static bool efx_ef10_filter_match_supported(struct efx_ef10_filter_table *table,
4716 bool encap,
4717 enum efx_filter_match_flags match_flags)
4718 {
4719 unsigned int match_pri;
4720 int mf;
4721
4722 for (match_pri = 0;
4723 match_pri < table->rx_match_count;
4724 match_pri++) {
4725 mf = efx_ef10_filter_match_flags_from_mcdi(encap,
4726 table->rx_match_mcdi_flags[match_pri]);
4727 if (mf == match_flags)
4728 return true;
4729 }
4730
4731 return false;
4732 }
4733
4734 static int
4735 efx_ef10_filter_table_probe_matches(struct efx_nic *efx,
4736 struct efx_ef10_filter_table *table,
4737 bool encap)
4738 {
4739 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
4740 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
4741 unsigned int pd_match_pri, pd_match_count;
4742 size_t outlen;
4743 int rc;
4744
4745 /* Find out which RX filter types are supported, and their priorities */
4746 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
4747 encap ?
4748 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES :
4749 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
4750 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
4751 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
4752 &outlen);
4753 if (rc)
4754 return rc;
4755
4756 pd_match_count = MCDI_VAR_ARRAY_LEN(
4757 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
4758
4759 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
4760 u32 mcdi_flags =
4761 MCDI_ARRAY_DWORD(
4762 outbuf,
4763 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
4764 pd_match_pri);
4765 rc = efx_ef10_filter_match_flags_from_mcdi(encap, mcdi_flags);
4766 if (rc < 0) {
4767 netif_dbg(efx, probe, efx->net_dev,
4768 "%s: fw flags %#x pri %u not supported in driver\n",
4769 __func__, mcdi_flags, pd_match_pri);
4770 } else {
4771 netif_dbg(efx, probe, efx->net_dev,
4772 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
4773 __func__, mcdi_flags, pd_match_pri,
4774 rc, table->rx_match_count);
4775 table->rx_match_mcdi_flags[table->rx_match_count] = mcdi_flags;
4776 table->rx_match_count++;
4777 }
4778 }
4779
4780 return 0;
4781 }
4782
4783 static int efx_ef10_filter_table_probe(struct efx_nic *efx)
4784 {
4785 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4786 struct net_device *net_dev = efx->net_dev;
4787 struct efx_ef10_filter_table *table;
4788 struct efx_ef10_vlan *vlan;
4789 int rc;
4790
4791 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4792 return -EINVAL;
4793
4794 if (efx->filter_state) /* already probed */
4795 return 0;
4796
4797 table = kzalloc(sizeof(*table), GFP_KERNEL);
4798 if (!table)
4799 return -ENOMEM;
4800
4801 table->rx_match_count = 0;
4802 rc = efx_ef10_filter_table_probe_matches(efx, table, false);
4803 if (rc)
4804 goto fail;
4805 if (nic_data->datapath_caps &
4806 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))
4807 rc = efx_ef10_filter_table_probe_matches(efx, table, true);
4808 if (rc)
4809 goto fail;
4810 if ((efx_supported_features(efx) & NETIF_F_HW_VLAN_CTAG_FILTER) &&
4811 !(efx_ef10_filter_match_supported(table, false,
4812 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC)) &&
4813 efx_ef10_filter_match_supported(table, false,
4814 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC_IG)))) {
4815 netif_info(efx, probe, net_dev,
4816 "VLAN filters are not supported in this firmware variant\n");
4817 net_dev->features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4818 efx->fixed_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4819 net_dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4820 }
4821
4822 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
4823 if (!table->entry) {
4824 rc = -ENOMEM;
4825 goto fail;
4826 }
4827
4828 table->mc_promisc_last = false;
4829 table->vlan_filter =
4830 !!(efx->net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
4831 INIT_LIST_HEAD(&table->vlan_list);
4832
4833 efx->filter_state = table;
4834 init_waitqueue_head(&table->waitq);
4835
4836 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
4837 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
4838 if (rc)
4839 goto fail_add_vlan;
4840 }
4841
4842 return 0;
4843
4844 fail_add_vlan:
4845 efx_ef10_filter_cleanup_vlans(efx);
4846 efx->filter_state = NULL;
4847 fail:
4848 kfree(table);
4849 return rc;
4850 }
4851
4852 /* Caller must hold efx->filter_sem for read if race against
4853 * efx_ef10_filter_table_remove() is possible
4854 */
4855 static void efx_ef10_filter_table_restore(struct efx_nic *efx)
4856 {
4857 struct efx_ef10_filter_table *table = efx->filter_state;
4858 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4859 unsigned int invalid_filters = 0, failed = 0;
4860 struct efx_ef10_filter_vlan *vlan;
4861 struct efx_filter_spec *spec;
4862 unsigned int filter_idx;
4863 u32 mcdi_flags;
4864 int match_pri;
4865 int rc, i;
4866
4867 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
4868
4869 if (!nic_data->must_restore_filters)
4870 return;
4871
4872 if (!table)
4873 return;
4874
4875 spin_lock_bh(&efx->filter_lock);
4876
4877 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4878 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4879 if (!spec)
4880 continue;
4881
4882 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
4883 match_pri = 0;
4884 while (match_pri < table->rx_match_count &&
4885 table->rx_match_mcdi_flags[match_pri] != mcdi_flags)
4886 ++match_pri;
4887 if (match_pri >= table->rx_match_count) {
4888 invalid_filters++;
4889 goto not_restored;
4890 }
4891 if (spec->rss_context != EFX_FILTER_RSS_CONTEXT_DEFAULT &&
4892 spec->rss_context != nic_data->rx_rss_context)
4893 netif_warn(efx, drv, efx->net_dev,
4894 "Warning: unable to restore a filter with specific RSS context.\n");
4895
4896 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4897 spin_unlock_bh(&efx->filter_lock);
4898
4899 rc = efx_ef10_filter_push(efx, spec,
4900 &table->entry[filter_idx].handle,
4901 false);
4902 if (rc)
4903 failed++;
4904 spin_lock_bh(&efx->filter_lock);
4905
4906 if (rc) {
4907 not_restored:
4908 list_for_each_entry(vlan, &table->vlan_list, list)
4909 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; ++i)
4910 if (vlan->default_filters[i] == filter_idx)
4911 vlan->default_filters[i] =
4912 EFX_EF10_FILTER_ID_INVALID;
4913
4914 kfree(spec);
4915 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4916 } else {
4917 table->entry[filter_idx].spec &=
4918 ~EFX_EF10_FILTER_FLAG_BUSY;
4919 }
4920 }
4921
4922 spin_unlock_bh(&efx->filter_lock);
4923
4924 /* This can happen validly if the MC's capabilities have changed, so
4925 * is not an error.
4926 */
4927 if (invalid_filters)
4928 netif_dbg(efx, drv, efx->net_dev,
4929 "Did not restore %u filters that are now unsupported.\n",
4930 invalid_filters);
4931
4932 if (failed)
4933 netif_err(efx, hw, efx->net_dev,
4934 "unable to restore %u filters\n", failed);
4935 else
4936 nic_data->must_restore_filters = false;
4937 }
4938
4939 static void efx_ef10_filter_table_remove(struct efx_nic *efx)
4940 {
4941 struct efx_ef10_filter_table *table = efx->filter_state;
4942 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
4943 struct efx_filter_spec *spec;
4944 unsigned int filter_idx;
4945 int rc;
4946
4947 efx_ef10_filter_cleanup_vlans(efx);
4948 efx->filter_state = NULL;
4949 /* If we were called without locking, then it's not safe to free
4950 * the table as others might be using it. So we just WARN, leak
4951 * the memory, and potentially get an inconsistent filter table
4952 * state.
4953 * This should never actually happen.
4954 */
4955 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4956 return;
4957
4958 if (!table)
4959 return;
4960
4961 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4962 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4963 if (!spec)
4964 continue;
4965
4966 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4967 efx_ef10_filter_is_exclusive(spec) ?
4968 MC_CMD_FILTER_OP_IN_OP_REMOVE :
4969 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4970 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4971 table->entry[filter_idx].handle);
4972 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP, inbuf,
4973 sizeof(inbuf), NULL, 0, NULL);
4974 if (rc)
4975 netif_info(efx, drv, efx->net_dev,
4976 "%s: filter %04x remove failed\n",
4977 __func__, filter_idx);
4978 kfree(spec);
4979 }
4980
4981 vfree(table->entry);
4982 kfree(table);
4983 }
4984
4985 static void efx_ef10_filter_mark_one_old(struct efx_nic *efx, uint16_t *id)
4986 {
4987 struct efx_ef10_filter_table *table = efx->filter_state;
4988 unsigned int filter_idx;
4989
4990 if (*id != EFX_EF10_FILTER_ID_INVALID) {
4991 filter_idx = efx_ef10_filter_get_unsafe_id(*id);
4992 if (!table->entry[filter_idx].spec)
4993 netif_dbg(efx, drv, efx->net_dev,
4994 "marked null spec old %04x:%04x\n", *id,
4995 filter_idx);
4996 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
4997 *id = EFX_EF10_FILTER_ID_INVALID;
4998 }
4999 }
5000
5001 /* Mark old per-VLAN filters that may need to be removed */
5002 static void _efx_ef10_filter_vlan_mark_old(struct efx_nic *efx,
5003 struct efx_ef10_filter_vlan *vlan)
5004 {
5005 struct efx_ef10_filter_table *table = efx->filter_state;
5006 unsigned int i;
5007
5008 for (i = 0; i < table->dev_uc_count; i++)
5009 efx_ef10_filter_mark_one_old(efx, &vlan->uc[i]);
5010 for (i = 0; i < table->dev_mc_count; i++)
5011 efx_ef10_filter_mark_one_old(efx, &vlan->mc[i]);
5012 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5013 efx_ef10_filter_mark_one_old(efx, &vlan->default_filters[i]);
5014 }
5015
5016 /* Mark old filters that may need to be removed.
5017 * Caller must hold efx->filter_sem for read if race against
5018 * efx_ef10_filter_table_remove() is possible
5019 */
5020 static void efx_ef10_filter_mark_old(struct efx_nic *efx)
5021 {
5022 struct efx_ef10_filter_table *table = efx->filter_state;
5023 struct efx_ef10_filter_vlan *vlan;
5024
5025 spin_lock_bh(&efx->filter_lock);
5026 list_for_each_entry(vlan, &table->vlan_list, list)
5027 _efx_ef10_filter_vlan_mark_old(efx, vlan);
5028 spin_unlock_bh(&efx->filter_lock);
5029 }
5030
5031 static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx)
5032 {
5033 struct efx_ef10_filter_table *table = efx->filter_state;
5034 struct net_device *net_dev = efx->net_dev;
5035 struct netdev_hw_addr *uc;
5036 int addr_count;
5037 unsigned int i;
5038
5039 addr_count = netdev_uc_count(net_dev);
5040 table->uc_promisc = !!(net_dev->flags & IFF_PROMISC);
5041 table->dev_uc_count = 1 + addr_count;
5042 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
5043 i = 1;
5044 netdev_for_each_uc_addr(uc, net_dev) {
5045 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) {
5046 table->uc_promisc = true;
5047 break;
5048 }
5049 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
5050 i++;
5051 }
5052 }
5053
5054 static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx)
5055 {
5056 struct efx_ef10_filter_table *table = efx->filter_state;
5057 struct net_device *net_dev = efx->net_dev;
5058 struct netdev_hw_addr *mc;
5059 unsigned int i, addr_count;
5060
5061 table->mc_promisc = !!(net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI));
5062
5063 addr_count = netdev_mc_count(net_dev);
5064 i = 0;
5065 netdev_for_each_mc_addr(mc, net_dev) {
5066 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) {
5067 table->mc_promisc = true;
5068 break;
5069 }
5070 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
5071 i++;
5072 }
5073
5074 table->dev_mc_count = i;
5075 }
5076
5077 static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx,
5078 struct efx_ef10_filter_vlan *vlan,
5079 bool multicast, bool rollback)
5080 {
5081 struct efx_ef10_filter_table *table = efx->filter_state;
5082 struct efx_ef10_dev_addr *addr_list;
5083 enum efx_filter_flags filter_flags;
5084 struct efx_filter_spec spec;
5085 u8 baddr[ETH_ALEN];
5086 unsigned int i, j;
5087 int addr_count;
5088 u16 *ids;
5089 int rc;
5090
5091 if (multicast) {
5092 addr_list = table->dev_mc_list;
5093 addr_count = table->dev_mc_count;
5094 ids = vlan->mc;
5095 } else {
5096 addr_list = table->dev_uc_list;
5097 addr_count = table->dev_uc_count;
5098 ids = vlan->uc;
5099 }
5100
5101 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
5102
5103 /* Insert/renew filters */
5104 for (i = 0; i < addr_count; i++) {
5105 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
5106 efx_filter_set_eth_local(&spec, vlan->vid, addr_list[i].addr);
5107 rc = efx_ef10_filter_insert(efx, &spec, true);
5108 if (rc < 0) {
5109 if (rollback) {
5110 netif_info(efx, drv, efx->net_dev,
5111 "efx_ef10_filter_insert failed rc=%d\n",
5112 rc);
5113 /* Fall back to promiscuous */
5114 for (j = 0; j < i; j++) {
5115 efx_ef10_filter_remove_unsafe(
5116 efx, EFX_FILTER_PRI_AUTO,
5117 ids[j]);
5118 ids[j] = EFX_EF10_FILTER_ID_INVALID;
5119 }
5120 return rc;
5121 } else {
5122 /* mark as not inserted, and carry on */
5123 rc = EFX_EF10_FILTER_ID_INVALID;
5124 }
5125 }
5126 ids[i] = efx_ef10_filter_get_unsafe_id(rc);
5127 }
5128
5129 if (multicast && rollback) {
5130 /* Also need an Ethernet broadcast filter */
5131 EFX_WARN_ON_PARANOID(vlan->default_filters[EFX_EF10_BCAST] !=
5132 EFX_EF10_FILTER_ID_INVALID);
5133 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
5134 eth_broadcast_addr(baddr);
5135 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
5136 rc = efx_ef10_filter_insert(efx, &spec, true);
5137 if (rc < 0) {
5138 netif_warn(efx, drv, efx->net_dev,
5139 "Broadcast filter insert failed rc=%d\n", rc);
5140 /* Fall back to promiscuous */
5141 for (j = 0; j < i; j++) {
5142 efx_ef10_filter_remove_unsafe(
5143 efx, EFX_FILTER_PRI_AUTO,
5144 ids[j]);
5145 ids[j] = EFX_EF10_FILTER_ID_INVALID;
5146 }
5147 return rc;
5148 } else {
5149 vlan->default_filters[EFX_EF10_BCAST] =
5150 efx_ef10_filter_get_unsafe_id(rc);
5151 }
5152 }
5153
5154 return 0;
5155 }
5156
5157 static int efx_ef10_filter_insert_def(struct efx_nic *efx,
5158 struct efx_ef10_filter_vlan *vlan,
5159 enum efx_encap_type encap_type,
5160 bool multicast, bool rollback)
5161 {
5162 struct efx_ef10_nic_data *nic_data = efx->nic_data;
5163 enum efx_filter_flags filter_flags;
5164 struct efx_filter_spec spec;
5165 u8 baddr[ETH_ALEN];
5166 int rc;
5167 u16 *id;
5168
5169 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
5170
5171 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
5172
5173 if (multicast)
5174 efx_filter_set_mc_def(&spec);
5175 else
5176 efx_filter_set_uc_def(&spec);
5177
5178 if (encap_type) {
5179 if (nic_data->datapath_caps &
5180 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))
5181 efx_filter_set_encap_type(&spec, encap_type);
5182 else
5183 /* don't insert encap filters on non-supporting
5184 * platforms. ID will be left as INVALID.
5185 */
5186 return 0;
5187 }
5188
5189 if (vlan->vid != EFX_FILTER_VID_UNSPEC)
5190 efx_filter_set_eth_local(&spec, vlan->vid, NULL);
5191
5192 rc = efx_ef10_filter_insert(efx, &spec, true);
5193 if (rc < 0) {
5194 const char *um = multicast ? "Multicast" : "Unicast";
5195 const char *encap_name = "";
5196 const char *encap_ipv = "";
5197
5198 if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5199 EFX_ENCAP_TYPE_VXLAN)
5200 encap_name = "VXLAN ";
5201 else if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5202 EFX_ENCAP_TYPE_NVGRE)
5203 encap_name = "NVGRE ";
5204 else if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5205 EFX_ENCAP_TYPE_GENEVE)
5206 encap_name = "GENEVE ";
5207 if (encap_type & EFX_ENCAP_FLAG_IPV6)
5208 encap_ipv = "IPv6 ";
5209 else if (encap_type)
5210 encap_ipv = "IPv4 ";
5211
5212 /* unprivileged functions can't insert mismatch filters
5213 * for encapsulated or unicast traffic, so downgrade
5214 * those warnings to debug.
5215 */
5216 netif_cond_dbg(efx, drv, efx->net_dev,
5217 rc == -EPERM && (encap_type || !multicast), warn,
5218 "%s%s%s mismatch filter insert failed rc=%d\n",
5219 encap_name, encap_ipv, um, rc);
5220 } else if (multicast) {
5221 /* mapping from encap types to default filter IDs (multicast) */
5222 static enum efx_ef10_default_filters map[] = {
5223 [EFX_ENCAP_TYPE_NONE] = EFX_EF10_MCDEF,
5224 [EFX_ENCAP_TYPE_VXLAN] = EFX_EF10_VXLAN4_MCDEF,
5225 [EFX_ENCAP_TYPE_NVGRE] = EFX_EF10_NVGRE4_MCDEF,
5226 [EFX_ENCAP_TYPE_GENEVE] = EFX_EF10_GENEVE4_MCDEF,
5227 [EFX_ENCAP_TYPE_VXLAN | EFX_ENCAP_FLAG_IPV6] =
5228 EFX_EF10_VXLAN6_MCDEF,
5229 [EFX_ENCAP_TYPE_NVGRE | EFX_ENCAP_FLAG_IPV6] =
5230 EFX_EF10_NVGRE6_MCDEF,
5231 [EFX_ENCAP_TYPE_GENEVE | EFX_ENCAP_FLAG_IPV6] =
5232 EFX_EF10_GENEVE6_MCDEF,
5233 };
5234
5235 /* quick bounds check (BCAST result impossible) */
5236 BUILD_BUG_ON(EFX_EF10_BCAST != 0);
5237 if (encap_type >= ARRAY_SIZE(map) || map[encap_type] == 0) {
5238 WARN_ON(1);
5239 return -EINVAL;
5240 }
5241 /* then follow map */
5242 id = &vlan->default_filters[map[encap_type]];
5243
5244 EFX_WARN_ON_PARANOID(*id != EFX_EF10_FILTER_ID_INVALID);
5245 *id = efx_ef10_filter_get_unsafe_id(rc);
5246 if (!nic_data->workaround_26807 && !encap_type) {
5247 /* Also need an Ethernet broadcast filter */
5248 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
5249 filter_flags, 0);
5250 eth_broadcast_addr(baddr);
5251 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
5252 rc = efx_ef10_filter_insert(efx, &spec, true);
5253 if (rc < 0) {
5254 netif_warn(efx, drv, efx->net_dev,
5255 "Broadcast filter insert failed rc=%d\n",
5256 rc);
5257 if (rollback) {
5258 /* Roll back the mc_def filter */
5259 efx_ef10_filter_remove_unsafe(
5260 efx, EFX_FILTER_PRI_AUTO,
5261 *id);
5262 *id = EFX_EF10_FILTER_ID_INVALID;
5263 return rc;
5264 }
5265 } else {
5266 EFX_WARN_ON_PARANOID(
5267 vlan->default_filters[EFX_EF10_BCAST] !=
5268 EFX_EF10_FILTER_ID_INVALID);
5269 vlan->default_filters[EFX_EF10_BCAST] =
5270 efx_ef10_filter_get_unsafe_id(rc);
5271 }
5272 }
5273 rc = 0;
5274 } else {
5275 /* mapping from encap types to default filter IDs (unicast) */
5276 static enum efx_ef10_default_filters map[] = {
5277 [EFX_ENCAP_TYPE_NONE] = EFX_EF10_UCDEF,
5278 [EFX_ENCAP_TYPE_VXLAN] = EFX_EF10_VXLAN4_UCDEF,
5279 [EFX_ENCAP_TYPE_NVGRE] = EFX_EF10_NVGRE4_UCDEF,
5280 [EFX_ENCAP_TYPE_GENEVE] = EFX_EF10_GENEVE4_UCDEF,
5281 [EFX_ENCAP_TYPE_VXLAN | EFX_ENCAP_FLAG_IPV6] =
5282 EFX_EF10_VXLAN6_UCDEF,
5283 [EFX_ENCAP_TYPE_NVGRE | EFX_ENCAP_FLAG_IPV6] =
5284 EFX_EF10_NVGRE6_UCDEF,
5285 [EFX_ENCAP_TYPE_GENEVE | EFX_ENCAP_FLAG_IPV6] =
5286 EFX_EF10_GENEVE6_UCDEF,
5287 };
5288
5289 /* quick bounds check (BCAST result impossible) */
5290 BUILD_BUG_ON(EFX_EF10_BCAST != 0);
5291 if (encap_type >= ARRAY_SIZE(map) || map[encap_type] == 0) {
5292 WARN_ON(1);
5293 return -EINVAL;
5294 }
5295 /* then follow map */
5296 id = &vlan->default_filters[map[encap_type]];
5297 EFX_WARN_ON_PARANOID(*id != EFX_EF10_FILTER_ID_INVALID);
5298 *id = rc;
5299 rc = 0;
5300 }
5301 return rc;
5302 }
5303
5304 /* Remove filters that weren't renewed. Since nothing else changes the AUTO_OLD
5305 * flag or removes these filters, we don't need to hold the filter_lock while
5306 * scanning for these filters.
5307 */
5308 static void efx_ef10_filter_remove_old(struct efx_nic *efx)
5309 {
5310 struct efx_ef10_filter_table *table = efx->filter_state;
5311 int remove_failed = 0;
5312 int remove_noent = 0;
5313 int rc;
5314 int i;
5315
5316 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
5317 if (ACCESS_ONCE(table->entry[i].spec) &
5318 EFX_EF10_FILTER_FLAG_AUTO_OLD) {
5319 rc = efx_ef10_filter_remove_internal(efx,
5320 1U << EFX_FILTER_PRI_AUTO, i, true);
5321 if (rc == -ENOENT)
5322 remove_noent++;
5323 else if (rc)
5324 remove_failed++;
5325 }
5326 }
5327
5328 if (remove_failed)
5329 netif_info(efx, drv, efx->net_dev,
5330 "%s: failed to remove %d filters\n",
5331 __func__, remove_failed);
5332 if (remove_noent)
5333 netif_info(efx, drv, efx->net_dev,
5334 "%s: failed to remove %d non-existent filters\n",
5335 __func__, remove_noent);
5336 }
5337
5338 static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
5339 {
5340 struct efx_ef10_nic_data *nic_data = efx->nic_data;
5341 u8 mac_old[ETH_ALEN];
5342 int rc, rc2;
5343
5344 /* Only reconfigure a PF-created vport */
5345 if (is_zero_ether_addr(nic_data->vport_mac))
5346 return 0;
5347
5348 efx_device_detach_sync(efx);
5349 efx_net_stop(efx->net_dev);
5350 down_write(&efx->filter_sem);
5351 efx_ef10_filter_table_remove(efx);
5352 up_write(&efx->filter_sem);
5353
5354 rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
5355 if (rc)
5356 goto restore_filters;
5357
5358 ether_addr_copy(mac_old, nic_data->vport_mac);
5359 rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
5360 nic_data->vport_mac);
5361 if (rc)
5362 goto restore_vadaptor;
5363
5364 rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
5365 efx->net_dev->dev_addr);
5366 if (!rc) {
5367 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
5368 } else {
5369 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
5370 if (rc2) {
5371 /* Failed to add original MAC, so clear vport_mac */
5372 eth_zero_addr(nic_data->vport_mac);
5373 goto reset_nic;
5374 }
5375 }
5376
5377 restore_vadaptor:
5378 rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
5379 if (rc2)
5380 goto reset_nic;
5381 restore_filters:
5382 down_write(&efx->filter_sem);
5383 rc2 = efx_ef10_filter_table_probe(efx);
5384 up_write(&efx->filter_sem);
5385 if (rc2)
5386 goto reset_nic;
5387
5388 rc2 = efx_net_open(efx->net_dev);
5389 if (rc2)
5390 goto reset_nic;
5391
5392 efx_device_attach_if_not_resetting(efx);
5393
5394 return rc;
5395
5396 reset_nic:
5397 netif_err(efx, drv, efx->net_dev,
5398 "Failed to restore when changing MAC address - scheduling reset\n");
5399 efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
5400
5401 return rc ? rc : rc2;
5402 }
5403
5404 /* Caller must hold efx->filter_sem for read if race against
5405 * efx_ef10_filter_table_remove() is possible
5406 */
5407 static void efx_ef10_filter_vlan_sync_rx_mode(struct efx_nic *efx,
5408 struct efx_ef10_filter_vlan *vlan)
5409 {
5410 struct efx_ef10_filter_table *table = efx->filter_state;
5411 struct efx_ef10_nic_data *nic_data = efx->nic_data;
5412
5413 /* Do not install unspecified VID if VLAN filtering is enabled.
5414 * Do not install all specified VIDs if VLAN filtering is disabled.
5415 */
5416 if ((vlan->vid == EFX_FILTER_VID_UNSPEC) == table->vlan_filter)
5417 return;
5418
5419 /* Insert/renew unicast filters */
5420 if (table->uc_promisc) {
5421 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NONE,
5422 false, false);
5423 efx_ef10_filter_insert_addr_list(efx, vlan, false, false);
5424 } else {
5425 /* If any of the filters failed to insert, fall back to
5426 * promiscuous mode - add in the uc_def filter. But keep
5427 * our individual unicast filters.
5428 */
5429 if (efx_ef10_filter_insert_addr_list(efx, vlan, false, false))
5430 efx_ef10_filter_insert_def(efx, vlan,
5431 EFX_ENCAP_TYPE_NONE,
5432 false, false);
5433 }
5434 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN,
5435 false, false);
5436 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN |
5437 EFX_ENCAP_FLAG_IPV6,
5438 false, false);
5439 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE,
5440 false, false);
5441 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE |
5442 EFX_ENCAP_FLAG_IPV6,
5443 false, false);
5444 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE,
5445 false, false);
5446 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE |
5447 EFX_ENCAP_FLAG_IPV6,
5448 false, false);
5449
5450 /* Insert/renew multicast filters */
5451 /* If changing promiscuous state with cascaded multicast filters, remove
5452 * old filters first, so that packets are dropped rather than duplicated
5453 */
5454 if (nic_data->workaround_26807 &&
5455 table->mc_promisc_last != table->mc_promisc)
5456 efx_ef10_filter_remove_old(efx);
5457 if (table->mc_promisc) {
5458 if (nic_data->workaround_26807) {
5459 /* If we failed to insert promiscuous filters, rollback
5460 * and fall back to individual multicast filters
5461 */
5462 if (efx_ef10_filter_insert_def(efx, vlan,
5463 EFX_ENCAP_TYPE_NONE,
5464 true, true)) {
5465 /* Changing promisc state, so remove old filters */
5466 efx_ef10_filter_remove_old(efx);
5467 efx_ef10_filter_insert_addr_list(efx, vlan,
5468 true, false);
5469 }
5470 } else {
5471 /* If we failed to insert promiscuous filters, don't
5472 * rollback. Regardless, also insert the mc_list
5473 */
5474 efx_ef10_filter_insert_def(efx, vlan,
5475 EFX_ENCAP_TYPE_NONE,
5476 true, false);
5477 efx_ef10_filter_insert_addr_list(efx, vlan, true, false);
5478 }
5479 } else {
5480 /* If any filters failed to insert, rollback and fall back to
5481 * promiscuous mode - mc_def filter and maybe broadcast. If
5482 * that fails, roll back again and insert as many of our
5483 * individual multicast filters as we can.
5484 */
5485 if (efx_ef10_filter_insert_addr_list(efx, vlan, true, true)) {
5486 /* Changing promisc state, so remove old filters */
5487 if (nic_data->workaround_26807)
5488 efx_ef10_filter_remove_old(efx);
5489 if (efx_ef10_filter_insert_def(efx, vlan,
5490 EFX_ENCAP_TYPE_NONE,
5491 true, true))
5492 efx_ef10_filter_insert_addr_list(efx, vlan,
5493 true, false);
5494 }
5495 }
5496 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN,
5497 true, false);
5498 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN |
5499 EFX_ENCAP_FLAG_IPV6,
5500 true, false);
5501 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE,
5502 true, false);
5503 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE |
5504 EFX_ENCAP_FLAG_IPV6,
5505 true, false);
5506 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE,
5507 true, false);
5508 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE |
5509 EFX_ENCAP_FLAG_IPV6,
5510 true, false);
5511 }
5512
5513 /* Caller must hold efx->filter_sem for read if race against
5514 * efx_ef10_filter_table_remove() is possible
5515 */
5516 static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
5517 {
5518 struct efx_ef10_filter_table *table = efx->filter_state;
5519 struct net_device *net_dev = efx->net_dev;
5520 struct efx_ef10_filter_vlan *vlan;
5521 bool vlan_filter;
5522
5523 if (!efx_dev_registered(efx))
5524 return;
5525
5526 if (!table)
5527 return;
5528
5529 efx_ef10_filter_mark_old(efx);
5530
5531 /* Copy/convert the address lists; add the primary station
5532 * address and broadcast address
5533 */
5534 netif_addr_lock_bh(net_dev);
5535 efx_ef10_filter_uc_addr_list(efx);
5536 efx_ef10_filter_mc_addr_list(efx);
5537 netif_addr_unlock_bh(net_dev);
5538
5539 /* If VLAN filtering changes, all old filters are finally removed.
5540 * Do it in advance to avoid conflicts for unicast untagged and
5541 * VLAN 0 tagged filters.
5542 */
5543 vlan_filter = !!(net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
5544 if (table->vlan_filter != vlan_filter) {
5545 table->vlan_filter = vlan_filter;
5546 efx_ef10_filter_remove_old(efx);
5547 }
5548
5549 list_for_each_entry(vlan, &table->vlan_list, list)
5550 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
5551
5552 efx_ef10_filter_remove_old(efx);
5553 table->mc_promisc_last = table->mc_promisc;
5554 }
5555
5556 static struct efx_ef10_filter_vlan *efx_ef10_filter_find_vlan(struct efx_nic *efx, u16 vid)
5557 {
5558 struct efx_ef10_filter_table *table = efx->filter_state;
5559 struct efx_ef10_filter_vlan *vlan;
5560
5561 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
5562
5563 list_for_each_entry(vlan, &table->vlan_list, list) {
5564 if (vlan->vid == vid)
5565 return vlan;
5566 }
5567
5568 return NULL;
5569 }
5570
5571 static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid)
5572 {
5573 struct efx_ef10_filter_table *table = efx->filter_state;
5574 struct efx_ef10_filter_vlan *vlan;
5575 unsigned int i;
5576
5577 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5578 return -EINVAL;
5579
5580 vlan = efx_ef10_filter_find_vlan(efx, vid);
5581 if (WARN_ON(vlan)) {
5582 netif_err(efx, drv, efx->net_dev,
5583 "VLAN %u already added\n", vid);
5584 return -EALREADY;
5585 }
5586
5587 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
5588 if (!vlan)
5589 return -ENOMEM;
5590
5591 vlan->vid = vid;
5592
5593 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
5594 vlan->uc[i] = EFX_EF10_FILTER_ID_INVALID;
5595 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
5596 vlan->mc[i] = EFX_EF10_FILTER_ID_INVALID;
5597 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5598 vlan->default_filters[i] = EFX_EF10_FILTER_ID_INVALID;
5599
5600 list_add_tail(&vlan->list, &table->vlan_list);
5601
5602 if (efx_dev_registered(efx))
5603 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
5604
5605 return 0;
5606 }
5607
5608 static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
5609 struct efx_ef10_filter_vlan *vlan)
5610 {
5611 unsigned int i;
5612
5613 /* See comment in efx_ef10_filter_table_remove() */
5614 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5615 return;
5616
5617 list_del(&vlan->list);
5618
5619 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
5620 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
5621 vlan->uc[i]);
5622 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
5623 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
5624 vlan->mc[i]);
5625 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5626 if (vlan->default_filters[i] != EFX_EF10_FILTER_ID_INVALID)
5627 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
5628 vlan->default_filters[i]);
5629
5630 kfree(vlan);
5631 }
5632
5633 static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid)
5634 {
5635 struct efx_ef10_filter_vlan *vlan;
5636
5637 /* See comment in efx_ef10_filter_table_remove() */
5638 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5639 return;
5640
5641 vlan = efx_ef10_filter_find_vlan(efx, vid);
5642 if (!vlan) {
5643 netif_err(efx, drv, efx->net_dev,
5644 "VLAN %u not found in filter state\n", vid);
5645 return;
5646 }
5647
5648 efx_ef10_filter_del_vlan_internal(efx, vlan);
5649 }
5650
5651 static int efx_ef10_set_mac_address(struct efx_nic *efx)
5652 {
5653 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
5654 struct efx_ef10_nic_data *nic_data = efx->nic_data;
5655 bool was_enabled = efx->port_enabled;
5656 int rc;
5657
5658 efx_device_detach_sync(efx);
5659 efx_net_stop(efx->net_dev);
5660
5661 mutex_lock(&efx->mac_lock);
5662 down_write(&efx->filter_sem);
5663 efx_ef10_filter_table_remove(efx);
5664
5665 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
5666 efx->net_dev->dev_addr);
5667 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
5668 nic_data->vport_id);
5669 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
5670 sizeof(inbuf), NULL, 0, NULL);
5671
5672 efx_ef10_filter_table_probe(efx);
5673 up_write(&efx->filter_sem);
5674 mutex_unlock(&efx->mac_lock);
5675
5676 if (was_enabled)
5677 efx_net_open(efx->net_dev);
5678 efx_device_attach_if_not_resetting(efx);
5679
5680 #ifdef CONFIG_SFC_SRIOV
5681 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
5682 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
5683
5684 if (rc == -EPERM) {
5685 struct efx_nic *efx_pf;
5686
5687 /* Switch to PF and change MAC address on vport */
5688 efx_pf = pci_get_drvdata(pci_dev_pf);
5689
5690 rc = efx_ef10_sriov_set_vf_mac(efx_pf,
5691 nic_data->vf_index,
5692 efx->net_dev->dev_addr);
5693 } else if (!rc) {
5694 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
5695 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
5696 unsigned int i;
5697
5698 /* MAC address successfully changed by VF (with MAC
5699 * spoofing) so update the parent PF if possible.
5700 */
5701 for (i = 0; i < efx_pf->vf_count; ++i) {
5702 struct ef10_vf *vf = nic_data->vf + i;
5703
5704 if (vf->efx == efx) {
5705 ether_addr_copy(vf->mac,
5706 efx->net_dev->dev_addr);
5707 return 0;
5708 }
5709 }
5710 }
5711 } else
5712 #endif
5713 if (rc == -EPERM) {
5714 netif_err(efx, drv, efx->net_dev,
5715 "Cannot change MAC address; use sfboot to enable"
5716 " mac-spoofing on this interface\n");
5717 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
5718 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
5719 * fall-back to the method of changing the MAC address on the
5720 * vport. This only applies to PFs because such versions of
5721 * MCFW do not support VFs.
5722 */
5723 rc = efx_ef10_vport_set_mac_address(efx);
5724 } else {
5725 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
5726 sizeof(inbuf), NULL, 0, rc);
5727 }
5728
5729 return rc;
5730 }
5731
5732 static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
5733 {
5734 efx_ef10_filter_sync_rx_mode(efx);
5735
5736 return efx_mcdi_set_mac(efx);
5737 }
5738
5739 static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
5740 {
5741 efx_ef10_filter_sync_rx_mode(efx);
5742
5743 return 0;
5744 }
5745
5746 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
5747 {
5748 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
5749
5750 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
5751 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
5752 NULL, 0, NULL);
5753 }
5754
5755 /* MC BISTs follow a different poll mechanism to phy BISTs.
5756 * The BIST is done in the poll handler on the MC, and the MCDI command
5757 * will block until the BIST is done.
5758 */
5759 static int efx_ef10_poll_bist(struct efx_nic *efx)
5760 {
5761 int rc;
5762 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
5763 size_t outlen;
5764 u32 result;
5765
5766 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
5767 outbuf, sizeof(outbuf), &outlen);
5768 if (rc != 0)
5769 return rc;
5770
5771 if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
5772 return -EIO;
5773
5774 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
5775 switch (result) {
5776 case MC_CMD_POLL_BIST_PASSED:
5777 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
5778 return 0;
5779 case MC_CMD_POLL_BIST_TIMEOUT:
5780 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
5781 return -EIO;
5782 case MC_CMD_POLL_BIST_FAILED:
5783 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
5784 return -EIO;
5785 default:
5786 netif_err(efx, hw, efx->net_dev,
5787 "BIST returned unknown result %u", result);
5788 return -EIO;
5789 }
5790 }
5791
5792 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
5793 {
5794 int rc;
5795
5796 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
5797
5798 rc = efx_ef10_start_bist(efx, bist_type);
5799 if (rc != 0)
5800 return rc;
5801
5802 return efx_ef10_poll_bist(efx);
5803 }
5804
5805 static int
5806 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
5807 {
5808 int rc, rc2;
5809
5810 efx_reset_down(efx, RESET_TYPE_WORLD);
5811
5812 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
5813 NULL, 0, NULL, 0, NULL);
5814 if (rc != 0)
5815 goto out;
5816
5817 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
5818 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
5819
5820 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
5821
5822 out:
5823 if (rc == -EPERM)
5824 rc = 0;
5825 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
5826 return rc ? rc : rc2;
5827 }
5828
5829 #ifdef CONFIG_SFC_MTD
5830
5831 struct efx_ef10_nvram_type_info {
5832 u16 type, type_mask;
5833 u8 port;
5834 const char *name;
5835 };
5836
5837 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
5838 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
5839 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
5840 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
5841 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
5842 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
5843 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
5844 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
5845 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
5846 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
5847 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
5848 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
5849 };
5850
5851 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
5852 struct efx_mcdi_mtd_partition *part,
5853 unsigned int type)
5854 {
5855 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
5856 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
5857 const struct efx_ef10_nvram_type_info *info;
5858 size_t size, erase_size, outlen;
5859 bool protected;
5860 int rc;
5861
5862 for (info = efx_ef10_nvram_types; ; info++) {
5863 if (info ==
5864 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
5865 return -ENODEV;
5866 if ((type & ~info->type_mask) == info->type)
5867 break;
5868 }
5869 if (info->port != efx_port_num(efx))
5870 return -ENODEV;
5871
5872 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
5873 if (rc)
5874 return rc;
5875 if (protected)
5876 return -ENODEV; /* hide it */
5877
5878 part->nvram_type = type;
5879
5880 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
5881 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
5882 outbuf, sizeof(outbuf), &outlen);
5883 if (rc)
5884 return rc;
5885 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
5886 return -EIO;
5887 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
5888 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
5889 part->fw_subtype = MCDI_DWORD(outbuf,
5890 NVRAM_METADATA_OUT_SUBTYPE);
5891
5892 part->common.dev_type_name = "EF10 NVRAM manager";
5893 part->common.type_name = info->name;
5894
5895 part->common.mtd.type = MTD_NORFLASH;
5896 part->common.mtd.flags = MTD_CAP_NORFLASH;
5897 part->common.mtd.size = size;
5898 part->common.mtd.erasesize = erase_size;
5899
5900 return 0;
5901 }
5902
5903 static int efx_ef10_mtd_probe(struct efx_nic *efx)
5904 {
5905 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
5906 struct efx_mcdi_mtd_partition *parts;
5907 size_t outlen, n_parts_total, i, n_parts;
5908 unsigned int type;
5909 int rc;
5910
5911 ASSERT_RTNL();
5912
5913 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
5914 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
5915 outbuf, sizeof(outbuf), &outlen);
5916 if (rc)
5917 return rc;
5918 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
5919 return -EIO;
5920
5921 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
5922 if (n_parts_total >
5923 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
5924 return -EIO;
5925
5926 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
5927 if (!parts)
5928 return -ENOMEM;
5929
5930 n_parts = 0;
5931 for (i = 0; i < n_parts_total; i++) {
5932 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
5933 i);
5934 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
5935 if (rc == 0)
5936 n_parts++;
5937 else if (rc != -ENODEV)
5938 goto fail;
5939 }
5940
5941 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
5942 fail:
5943 if (rc)
5944 kfree(parts);
5945 return rc;
5946 }
5947
5948 #endif /* CONFIG_SFC_MTD */
5949
5950 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
5951 {
5952 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
5953 }
5954
5955 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
5956 u32 host_time) {}
5957
5958 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
5959 bool temp)
5960 {
5961 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
5962 int rc;
5963
5964 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
5965 channel->sync_events_state == SYNC_EVENTS_VALID ||
5966 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
5967 return 0;
5968 channel->sync_events_state = SYNC_EVENTS_REQUESTED;
5969
5970 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
5971 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
5972 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
5973 channel->channel);
5974
5975 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
5976 inbuf, sizeof(inbuf), NULL, 0, NULL);
5977
5978 if (rc != 0)
5979 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
5980 SYNC_EVENTS_DISABLED;
5981
5982 return rc;
5983 }
5984
5985 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
5986 bool temp)
5987 {
5988 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
5989 int rc;
5990
5991 if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
5992 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
5993 return 0;
5994 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
5995 channel->sync_events_state = SYNC_EVENTS_DISABLED;
5996 return 0;
5997 }
5998 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
5999 SYNC_EVENTS_DISABLED;
6000
6001 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
6002 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
6003 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
6004 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
6005 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
6006 channel->channel);
6007
6008 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
6009 inbuf, sizeof(inbuf), NULL, 0, NULL);
6010
6011 return rc;
6012 }
6013
6014 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
6015 bool temp)
6016 {
6017 int (*set)(struct efx_channel *channel, bool temp);
6018 struct efx_channel *channel;
6019
6020 set = en ?
6021 efx_ef10_rx_enable_timestamping :
6022 efx_ef10_rx_disable_timestamping;
6023
6024 efx_for_each_channel(channel, efx) {
6025 int rc = set(channel, temp);
6026 if (en && rc != 0) {
6027 efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
6028 return rc;
6029 }
6030 }
6031
6032 return 0;
6033 }
6034
6035 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
6036 struct hwtstamp_config *init)
6037 {
6038 return -EOPNOTSUPP;
6039 }
6040
6041 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
6042 struct hwtstamp_config *init)
6043 {
6044 int rc;
6045
6046 switch (init->rx_filter) {
6047 case HWTSTAMP_FILTER_NONE:
6048 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
6049 /* if TX timestamping is still requested then leave PTP on */
6050 return efx_ptp_change_mode(efx,
6051 init->tx_type != HWTSTAMP_TX_OFF, 0);
6052 case HWTSTAMP_FILTER_ALL:
6053 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
6054 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
6055 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
6056 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
6057 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6058 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6059 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
6060 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6061 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6062 case HWTSTAMP_FILTER_PTP_V2_EVENT:
6063 case HWTSTAMP_FILTER_PTP_V2_SYNC:
6064 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
6065 init->rx_filter = HWTSTAMP_FILTER_ALL;
6066 rc = efx_ptp_change_mode(efx, true, 0);
6067 if (!rc)
6068 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
6069 if (rc)
6070 efx_ptp_change_mode(efx, false, 0);
6071 return rc;
6072 default:
6073 return -ERANGE;
6074 }
6075 }
6076
6077 static int efx_ef10_get_phys_port_id(struct efx_nic *efx,
6078 struct netdev_phys_item_id *ppid)
6079 {
6080 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6081
6082 if (!is_valid_ether_addr(nic_data->port_id))
6083 return -EOPNOTSUPP;
6084
6085 ppid->id_len = ETH_ALEN;
6086 memcpy(ppid->id, nic_data->port_id, ppid->id_len);
6087
6088 return 0;
6089 }
6090
6091 static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid)
6092 {
6093 if (proto != htons(ETH_P_8021Q))
6094 return -EINVAL;
6095
6096 return efx_ef10_add_vlan(efx, vid);
6097 }
6098
6099 static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid)
6100 {
6101 if (proto != htons(ETH_P_8021Q))
6102 return -EINVAL;
6103
6104 return efx_ef10_del_vlan(efx, vid);
6105 }
6106
6107 /* We rely on the MCDI wiping out our TX rings if it made any changes to the
6108 * ports table, ensuring that any TSO descriptors that were made on a now-
6109 * removed tunnel port will be blown away and won't break things when we try
6110 * to transmit them using the new ports table.
6111 */
6112 static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading)
6113 {
6114 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6115 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX);
6116 MCDI_DECLARE_BUF(outbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN);
6117 bool will_reset = false;
6118 size_t num_entries = 0;
6119 size_t inlen, outlen;
6120 size_t i;
6121 int rc;
6122 efx_dword_t flags_and_num_entries;
6123
6124 WARN_ON(!mutex_is_locked(&nic_data->udp_tunnels_lock));
6125
6126 nic_data->udp_tunnels_dirty = false;
6127
6128 if (!(nic_data->datapath_caps &
6129 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) {
6130 efx_device_attach_if_not_resetting(efx);
6131 return 0;
6132 }
6133
6134 BUILD_BUG_ON(ARRAY_SIZE(nic_data->udp_tunnels) >
6135 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM);
6136
6137 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) {
6138 if (nic_data->udp_tunnels[i].count &&
6139 nic_data->udp_tunnels[i].port) {
6140 efx_dword_t entry;
6141
6142 EFX_POPULATE_DWORD_2(entry,
6143 TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT,
6144 ntohs(nic_data->udp_tunnels[i].port),
6145 TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL,
6146 nic_data->udp_tunnels[i].type);
6147 *_MCDI_ARRAY_DWORD(inbuf,
6148 SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES,
6149 num_entries++) = entry;
6150 }
6151 }
6152
6153 BUILD_BUG_ON((MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST -
6154 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST) * 8 !=
6155 EFX_WORD_1_LBN);
6156 BUILD_BUG_ON(MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN * 8 !=
6157 EFX_WORD_1_WIDTH);
6158 EFX_POPULATE_DWORD_2(flags_and_num_entries,
6159 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING,
6160 !!unloading,
6161 EFX_WORD_1, num_entries);
6162 *_MCDI_DWORD(inbuf, SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS) =
6163 flags_and_num_entries;
6164
6165 inlen = MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num_entries);
6166
6167 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS,
6168 inbuf, inlen, outbuf, sizeof(outbuf), &outlen);
6169 if (rc == -EIO) {
6170 /* Most likely the MC rebooted due to another function also
6171 * setting its tunnel port list. Mark the tunnel port list as
6172 * dirty, so it will be pushed upon coming up from the reboot.
6173 */
6174 nic_data->udp_tunnels_dirty = true;
6175 return 0;
6176 }
6177
6178 if (rc) {
6179 /* expected not available on unprivileged functions */
6180 if (rc != -EPERM)
6181 netif_warn(efx, drv, efx->net_dev,
6182 "Unable to set UDP tunnel ports; rc=%d.\n", rc);
6183 } else if (MCDI_DWORD(outbuf, SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS) &
6184 (1 << MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN)) {
6185 netif_info(efx, drv, efx->net_dev,
6186 "Rebooting MC due to UDP tunnel port list change\n");
6187 will_reset = true;
6188 if (unloading)
6189 /* Delay for the MC reset to complete. This will make
6190 * unloading other functions a bit smoother. This is a
6191 * race, but the other unload will work whichever way
6192 * it goes, this just avoids an unnecessary error
6193 * message.
6194 */
6195 msleep(100);
6196 }
6197 if (!will_reset && !unloading) {
6198 /* The caller will have detached, relying on the MC reset to
6199 * trigger a re-attach. Since there won't be an MC reset, we
6200 * have to do the attach ourselves.
6201 */
6202 efx_device_attach_if_not_resetting(efx);
6203 }
6204
6205 return rc;
6206 }
6207
6208 static int efx_ef10_udp_tnl_push_ports(struct efx_nic *efx)
6209 {
6210 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6211 int rc = 0;
6212
6213 mutex_lock(&nic_data->udp_tunnels_lock);
6214 if (nic_data->udp_tunnels_dirty) {
6215 /* Make sure all TX are stopped while we modify the table, else
6216 * we might race against an efx_features_check().
6217 */
6218 efx_device_detach_sync(efx);
6219 rc = efx_ef10_set_udp_tnl_ports(efx, false);
6220 }
6221 mutex_unlock(&nic_data->udp_tunnels_lock);
6222 return rc;
6223 }
6224
6225 static struct efx_udp_tunnel *__efx_ef10_udp_tnl_lookup_port(struct efx_nic *efx,
6226 __be16 port)
6227 {
6228 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6229 size_t i;
6230
6231 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) {
6232 if (!nic_data->udp_tunnels[i].count)
6233 continue;
6234 if (nic_data->udp_tunnels[i].port == port)
6235 return &nic_data->udp_tunnels[i];
6236 }
6237 return NULL;
6238 }
6239
6240 static int efx_ef10_udp_tnl_add_port(struct efx_nic *efx,
6241 struct efx_udp_tunnel tnl)
6242 {
6243 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6244 struct efx_udp_tunnel *match;
6245 char typebuf[8];
6246 size_t i;
6247 int rc;
6248
6249 if (!(nic_data->datapath_caps &
6250 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6251 return 0;
6252
6253 efx_get_udp_tunnel_type_name(tnl.type, typebuf, sizeof(typebuf));
6254 netif_dbg(efx, drv, efx->net_dev, "Adding UDP tunnel (%s) port %d\n",
6255 typebuf, ntohs(tnl.port));
6256
6257 mutex_lock(&nic_data->udp_tunnels_lock);
6258 /* Make sure all TX are stopped while we add to the table, else we
6259 * might race against an efx_features_check().
6260 */
6261 efx_device_detach_sync(efx);
6262
6263 match = __efx_ef10_udp_tnl_lookup_port(efx, tnl.port);
6264 if (match != NULL) {
6265 if (match->type == tnl.type) {
6266 netif_dbg(efx, drv, efx->net_dev,
6267 "Referencing existing tunnel entry\n");
6268 match->count++;
6269 /* No need to cause an MCDI update */
6270 rc = 0;
6271 goto unlock_out;
6272 }
6273 efx_get_udp_tunnel_type_name(match->type,
6274 typebuf, sizeof(typebuf));
6275 netif_dbg(efx, drv, efx->net_dev,
6276 "UDP port %d is already in use by %s\n",
6277 ntohs(tnl.port), typebuf);
6278 rc = -EEXIST;
6279 goto unlock_out;
6280 }
6281
6282 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i)
6283 if (!nic_data->udp_tunnels[i].count) {
6284 nic_data->udp_tunnels[i] = tnl;
6285 nic_data->udp_tunnels[i].count = 1;
6286 rc = efx_ef10_set_udp_tnl_ports(efx, false);
6287 goto unlock_out;
6288 }
6289
6290 netif_dbg(efx, drv, efx->net_dev,
6291 "Unable to add UDP tunnel (%s) port %d; insufficient resources.\n",
6292 typebuf, ntohs(tnl.port));
6293
6294 rc = -ENOMEM;
6295
6296 unlock_out:
6297 mutex_unlock(&nic_data->udp_tunnels_lock);
6298 return rc;
6299 }
6300
6301 /* Called under the TX lock with the TX queue running, hence no-one can be
6302 * in the middle of updating the UDP tunnels table. However, they could
6303 * have tried and failed the MCDI, in which case they'll have set the dirty
6304 * flag before dropping their locks.
6305 */
6306 static bool efx_ef10_udp_tnl_has_port(struct efx_nic *efx, __be16 port)
6307 {
6308 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6309
6310 if (!(nic_data->datapath_caps &
6311 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6312 return false;
6313
6314 if (nic_data->udp_tunnels_dirty)
6315 /* SW table may not match HW state, so just assume we can't
6316 * use any UDP tunnel offloads.
6317 */
6318 return false;
6319
6320 return __efx_ef10_udp_tnl_lookup_port(efx, port) != NULL;
6321 }
6322
6323 static int efx_ef10_udp_tnl_del_port(struct efx_nic *efx,
6324 struct efx_udp_tunnel tnl)
6325 {
6326 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6327 struct efx_udp_tunnel *match;
6328 char typebuf[8];
6329 int rc;
6330
6331 if (!(nic_data->datapath_caps &
6332 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6333 return 0;
6334
6335 efx_get_udp_tunnel_type_name(tnl.type, typebuf, sizeof(typebuf));
6336 netif_dbg(efx, drv, efx->net_dev, "Removing UDP tunnel (%s) port %d\n",
6337 typebuf, ntohs(tnl.port));
6338
6339 mutex_lock(&nic_data->udp_tunnels_lock);
6340 /* Make sure all TX are stopped while we remove from the table, else we
6341 * might race against an efx_features_check().
6342 */
6343 efx_device_detach_sync(efx);
6344
6345 match = __efx_ef10_udp_tnl_lookup_port(efx, tnl.port);
6346 if (match != NULL) {
6347 if (match->type == tnl.type) {
6348 if (--match->count) {
6349 /* Port is still in use, so nothing to do */
6350 netif_dbg(efx, drv, efx->net_dev,
6351 "UDP tunnel port %d remains active\n",
6352 ntohs(tnl.port));
6353 rc = 0;
6354 goto out_unlock;
6355 }
6356 rc = efx_ef10_set_udp_tnl_ports(efx, false);
6357 goto out_unlock;
6358 }
6359 efx_get_udp_tunnel_type_name(match->type,
6360 typebuf, sizeof(typebuf));
6361 netif_warn(efx, drv, efx->net_dev,
6362 "UDP port %d is actually in use by %s, not removing\n",
6363 ntohs(tnl.port), typebuf);
6364 }
6365 rc = -ENOENT;
6366
6367 out_unlock:
6368 mutex_unlock(&nic_data->udp_tunnels_lock);
6369 return rc;
6370 }
6371
6372 #define EF10_OFFLOAD_FEATURES \
6373 (NETIF_F_IP_CSUM | \
6374 NETIF_F_HW_VLAN_CTAG_FILTER | \
6375 NETIF_F_IPV6_CSUM | \
6376 NETIF_F_RXHASH | \
6377 NETIF_F_NTUPLE)
6378
6379 const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
6380 .is_vf = true,
6381 .mem_bar = EFX_MEM_VF_BAR,
6382 .mem_map_size = efx_ef10_mem_map_size,
6383 .probe = efx_ef10_probe_vf,
6384 .remove = efx_ef10_remove,
6385 .dimension_resources = efx_ef10_dimension_resources,
6386 .init = efx_ef10_init_nic,
6387 .fini = efx_port_dummy_op_void,
6388 .map_reset_reason = efx_ef10_map_reset_reason,
6389 .map_reset_flags = efx_ef10_map_reset_flags,
6390 .reset = efx_ef10_reset,
6391 .probe_port = efx_mcdi_port_probe,
6392 .remove_port = efx_mcdi_port_remove,
6393 .fini_dmaq = efx_ef10_fini_dmaq,
6394 .prepare_flr = efx_ef10_prepare_flr,
6395 .finish_flr = efx_port_dummy_op_void,
6396 .describe_stats = efx_ef10_describe_stats,
6397 .update_stats = efx_ef10_update_stats_vf,
6398 .start_stats = efx_port_dummy_op_void,
6399 .pull_stats = efx_port_dummy_op_void,
6400 .stop_stats = efx_port_dummy_op_void,
6401 .set_id_led = efx_mcdi_set_id_led,
6402 .push_irq_moderation = efx_ef10_push_irq_moderation,
6403 .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
6404 .check_mac_fault = efx_mcdi_mac_check_fault,
6405 .reconfigure_port = efx_mcdi_port_reconfigure,
6406 .get_wol = efx_ef10_get_wol_vf,
6407 .set_wol = efx_ef10_set_wol_vf,
6408 .resume_wol = efx_port_dummy_op_void,
6409 .mcdi_request = efx_ef10_mcdi_request,
6410 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
6411 .mcdi_read_response = efx_ef10_mcdi_read_response,
6412 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
6413 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
6414 .irq_enable_master = efx_port_dummy_op_void,
6415 .irq_test_generate = efx_ef10_irq_test_generate,
6416 .irq_disable_non_ev = efx_port_dummy_op_void,
6417 .irq_handle_msi = efx_ef10_msi_interrupt,
6418 .irq_handle_legacy = efx_ef10_legacy_interrupt,
6419 .tx_probe = efx_ef10_tx_probe,
6420 .tx_init = efx_ef10_tx_init,
6421 .tx_remove = efx_ef10_tx_remove,
6422 .tx_write = efx_ef10_tx_write,
6423 .tx_limit_len = efx_ef10_tx_limit_len,
6424 .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
6425 .rx_pull_rss_config = efx_ef10_rx_pull_rss_config,
6426 .rx_probe = efx_ef10_rx_probe,
6427 .rx_init = efx_ef10_rx_init,
6428 .rx_remove = efx_ef10_rx_remove,
6429 .rx_write = efx_ef10_rx_write,
6430 .rx_defer_refill = efx_ef10_rx_defer_refill,
6431 .ev_probe = efx_ef10_ev_probe,
6432 .ev_init = efx_ef10_ev_init,
6433 .ev_fini = efx_ef10_ev_fini,
6434 .ev_remove = efx_ef10_ev_remove,
6435 .ev_process = efx_ef10_ev_process,
6436 .ev_read_ack = efx_ef10_ev_read_ack,
6437 .ev_test_generate = efx_ef10_ev_test_generate,
6438 .filter_table_probe = efx_ef10_filter_table_probe,
6439 .filter_table_restore = efx_ef10_filter_table_restore,
6440 .filter_table_remove = efx_ef10_filter_table_remove,
6441 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
6442 .filter_insert = efx_ef10_filter_insert,
6443 .filter_remove_safe = efx_ef10_filter_remove_safe,
6444 .filter_get_safe = efx_ef10_filter_get_safe,
6445 .filter_clear_rx = efx_ef10_filter_clear_rx,
6446 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
6447 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
6448 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
6449 #ifdef CONFIG_RFS_ACCEL
6450 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
6451 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
6452 #endif
6453 #ifdef CONFIG_SFC_MTD
6454 .mtd_probe = efx_port_dummy_op_int,
6455 #endif
6456 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
6457 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
6458 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
6459 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
6460 #ifdef CONFIG_SFC_SRIOV
6461 .vswitching_probe = efx_ef10_vswitching_probe_vf,
6462 .vswitching_restore = efx_ef10_vswitching_restore_vf,
6463 .vswitching_remove = efx_ef10_vswitching_remove_vf,
6464 #endif
6465 .get_mac_address = efx_ef10_get_mac_address_vf,
6466 .set_mac_address = efx_ef10_set_mac_address,
6467
6468 .get_phys_port_id = efx_ef10_get_phys_port_id,
6469 .revision = EFX_REV_HUNT_A0,
6470 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
6471 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
6472 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
6473 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
6474 .can_rx_scatter = true,
6475 .always_rx_scatter = true,
6476 .min_interrupt_mode = EFX_INT_MODE_MSIX,
6477 .max_interrupt_mode = EFX_INT_MODE_MSIX,
6478 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
6479 .offload_features = EF10_OFFLOAD_FEATURES,
6480 .mcdi_max_ver = 2,
6481 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
6482 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
6483 1 << HWTSTAMP_FILTER_ALL,
6484 .rx_hash_key_size = 40,
6485 };
6486
6487 const struct efx_nic_type efx_hunt_a0_nic_type = {
6488 .is_vf = false,
6489 .mem_bar = EFX_MEM_BAR,
6490 .mem_map_size = efx_ef10_mem_map_size,
6491 .probe = efx_ef10_probe_pf,
6492 .remove = efx_ef10_remove,
6493 .dimension_resources = efx_ef10_dimension_resources,
6494 .init = efx_ef10_init_nic,
6495 .fini = efx_port_dummy_op_void,
6496 .map_reset_reason = efx_ef10_map_reset_reason,
6497 .map_reset_flags = efx_ef10_map_reset_flags,
6498 .reset = efx_ef10_reset,
6499 .probe_port = efx_mcdi_port_probe,
6500 .remove_port = efx_mcdi_port_remove,
6501 .fini_dmaq = efx_ef10_fini_dmaq,
6502 .prepare_flr = efx_ef10_prepare_flr,
6503 .finish_flr = efx_port_dummy_op_void,
6504 .describe_stats = efx_ef10_describe_stats,
6505 .update_stats = efx_ef10_update_stats_pf,
6506 .start_stats = efx_mcdi_mac_start_stats,
6507 .pull_stats = efx_mcdi_mac_pull_stats,
6508 .stop_stats = efx_mcdi_mac_stop_stats,
6509 .set_id_led = efx_mcdi_set_id_led,
6510 .push_irq_moderation = efx_ef10_push_irq_moderation,
6511 .reconfigure_mac = efx_ef10_mac_reconfigure,
6512 .check_mac_fault = efx_mcdi_mac_check_fault,
6513 .reconfigure_port = efx_mcdi_port_reconfigure,
6514 .get_wol = efx_ef10_get_wol,
6515 .set_wol = efx_ef10_set_wol,
6516 .resume_wol = efx_port_dummy_op_void,
6517 .test_chip = efx_ef10_test_chip,
6518 .test_nvram = efx_mcdi_nvram_test_all,
6519 .mcdi_request = efx_ef10_mcdi_request,
6520 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
6521 .mcdi_read_response = efx_ef10_mcdi_read_response,
6522 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
6523 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
6524 .irq_enable_master = efx_port_dummy_op_void,
6525 .irq_test_generate = efx_ef10_irq_test_generate,
6526 .irq_disable_non_ev = efx_port_dummy_op_void,
6527 .irq_handle_msi = efx_ef10_msi_interrupt,
6528 .irq_handle_legacy = efx_ef10_legacy_interrupt,
6529 .tx_probe = efx_ef10_tx_probe,
6530 .tx_init = efx_ef10_tx_init,
6531 .tx_remove = efx_ef10_tx_remove,
6532 .tx_write = efx_ef10_tx_write,
6533 .tx_limit_len = efx_ef10_tx_limit_len,
6534 .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
6535 .rx_pull_rss_config = efx_ef10_rx_pull_rss_config,
6536 .rx_probe = efx_ef10_rx_probe,
6537 .rx_init = efx_ef10_rx_init,
6538 .rx_remove = efx_ef10_rx_remove,
6539 .rx_write = efx_ef10_rx_write,
6540 .rx_defer_refill = efx_ef10_rx_defer_refill,
6541 .ev_probe = efx_ef10_ev_probe,
6542 .ev_init = efx_ef10_ev_init,
6543 .ev_fini = efx_ef10_ev_fini,
6544 .ev_remove = efx_ef10_ev_remove,
6545 .ev_process = efx_ef10_ev_process,
6546 .ev_read_ack = efx_ef10_ev_read_ack,
6547 .ev_test_generate = efx_ef10_ev_test_generate,
6548 .filter_table_probe = efx_ef10_filter_table_probe,
6549 .filter_table_restore = efx_ef10_filter_table_restore,
6550 .filter_table_remove = efx_ef10_filter_table_remove,
6551 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
6552 .filter_insert = efx_ef10_filter_insert,
6553 .filter_remove_safe = efx_ef10_filter_remove_safe,
6554 .filter_get_safe = efx_ef10_filter_get_safe,
6555 .filter_clear_rx = efx_ef10_filter_clear_rx,
6556 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
6557 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
6558 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
6559 #ifdef CONFIG_RFS_ACCEL
6560 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
6561 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
6562 #endif
6563 #ifdef CONFIG_SFC_MTD
6564 .mtd_probe = efx_ef10_mtd_probe,
6565 .mtd_rename = efx_mcdi_mtd_rename,
6566 .mtd_read = efx_mcdi_mtd_read,
6567 .mtd_erase = efx_mcdi_mtd_erase,
6568 .mtd_write = efx_mcdi_mtd_write,
6569 .mtd_sync = efx_mcdi_mtd_sync,
6570 #endif
6571 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
6572 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
6573 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
6574 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
6575 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
6576 .udp_tnl_push_ports = efx_ef10_udp_tnl_push_ports,
6577 .udp_tnl_add_port = efx_ef10_udp_tnl_add_port,
6578 .udp_tnl_has_port = efx_ef10_udp_tnl_has_port,
6579 .udp_tnl_del_port = efx_ef10_udp_tnl_del_port,
6580 #ifdef CONFIG_SFC_SRIOV
6581 .sriov_configure = efx_ef10_sriov_configure,
6582 .sriov_init = efx_ef10_sriov_init,
6583 .sriov_fini = efx_ef10_sriov_fini,
6584 .sriov_wanted = efx_ef10_sriov_wanted,
6585 .sriov_reset = efx_ef10_sriov_reset,
6586 .sriov_flr = efx_ef10_sriov_flr,
6587 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
6588 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
6589 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
6590 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
6591 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
6592 .vswitching_probe = efx_ef10_vswitching_probe_pf,
6593 .vswitching_restore = efx_ef10_vswitching_restore_pf,
6594 .vswitching_remove = efx_ef10_vswitching_remove_pf,
6595 #endif
6596 .get_mac_address = efx_ef10_get_mac_address_pf,
6597 .set_mac_address = efx_ef10_set_mac_address,
6598 .tso_versions = efx_ef10_tso_versions,
6599
6600 .get_phys_port_id = efx_ef10_get_phys_port_id,
6601 .revision = EFX_REV_HUNT_A0,
6602 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
6603 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
6604 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
6605 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
6606 .can_rx_scatter = true,
6607 .always_rx_scatter = true,
6608 .option_descriptors = true,
6609 .min_interrupt_mode = EFX_INT_MODE_LEGACY,
6610 .max_interrupt_mode = EFX_INT_MODE_MSIX,
6611 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
6612 .offload_features = EF10_OFFLOAD_FEATURES,
6613 .mcdi_max_ver = 2,
6614 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
6615 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
6616 1 << HWTSTAMP_FILTER_ALL,
6617 .rx_hash_key_size = 40,
6618 };
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