1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
10 #include "net_driver.h"
11 #include "ef10_regs.h"
14 #include "mcdi_pcol.h"
16 #include "workarounds.h"
18 #include "ef10_sriov.h"
20 #include <linux/jhash.h>
21 #include <linux/wait.h>
22 #include <linux/workqueue.h>
24 /* Hardware control for EF10 architecture including 'Huntington'. */
26 #define EFX_EF10_DRVGEN_EV 7
32 /* The reserved RSS context value */
33 #define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
34 /* The maximum size of a shared RSS context */
35 /* TODO: this should really be from the mcdi protocol export */
36 #define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
38 /* The filter table(s) are managed by firmware and we have write-only
39 * access. When removing filters we must identify them to the
40 * firmware by a 64-bit handle, but this is too wide for Linux kernel
41 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
42 * be able to tell in advance whether a requested insertion will
43 * replace an existing filter. Therefore we maintain a software hash
44 * table, which should be at least as large as the hardware hash
47 * Huntington has a single 8K filter table shared between all filter
48 * types and both ports.
50 #define HUNT_FILTER_TBL_ROWS 8192
52 #define EFX_EF10_FILTER_ID_INVALID 0xffff
54 #define EFX_EF10_FILTER_DEV_UC_MAX 32
55 #define EFX_EF10_FILTER_DEV_MC_MAX 256
58 struct efx_ef10_vlan
{
59 struct list_head list
;
63 /* Per-VLAN filters information */
64 struct efx_ef10_filter_vlan
{
65 struct list_head list
;
67 u16 uc
[EFX_EF10_FILTER_DEV_UC_MAX
];
68 u16 mc
[EFX_EF10_FILTER_DEV_MC_MAX
];
74 struct efx_ef10_dev_addr
{
78 struct efx_ef10_filter_table
{
79 /* The MCDI match masks supported by this fw & hw, in order of priority */
80 u32 rx_match_mcdi_flags
[
81 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM
];
82 unsigned int rx_match_count
;
85 unsigned long spec
; /* pointer to spec plus flag bits */
86 /* BUSY flag indicates that an update is in progress. AUTO_OLD is
87 * used to mark and sweep MAC filters for the device address lists.
89 #define EFX_EF10_FILTER_FLAG_BUSY 1UL
90 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
91 #define EFX_EF10_FILTER_FLAGS 3UL
92 u64 handle
; /* firmware handle */
94 wait_queue_head_t waitq
;
95 /* Shadow of net_device address lists, guarded by mac_lock */
96 struct efx_ef10_dev_addr dev_uc_list
[EFX_EF10_FILTER_DEV_UC_MAX
];
97 struct efx_ef10_dev_addr dev_mc_list
[EFX_EF10_FILTER_DEV_MC_MAX
];
102 /* Whether in multicast promiscuous mode when last changed */
103 bool mc_promisc_last
;
105 struct list_head vlan_list
;
108 /* An arbitrary search limit for the software hash table */
109 #define EFX_EF10_FILTER_SEARCH_LIMIT 200
111 static void efx_ef10_rx_free_indir_table(struct efx_nic
*efx
);
112 static void efx_ef10_filter_table_remove(struct efx_nic
*efx
);
113 static int efx_ef10_filter_add_vlan(struct efx_nic
*efx
, u16 vid
);
114 static void efx_ef10_filter_del_vlan_internal(struct efx_nic
*efx
,
115 struct efx_ef10_filter_vlan
*vlan
);
116 static void efx_ef10_filter_del_vlan(struct efx_nic
*efx
, u16 vid
);
118 static int efx_ef10_get_warm_boot_count(struct efx_nic
*efx
)
122 efx_readd(efx
, ®
, ER_DZ_BIU_MC_SFT_STATUS
);
123 return EFX_DWORD_FIELD(reg
, EFX_WORD_1
) == 0xb007 ?
124 EFX_DWORD_FIELD(reg
, EFX_WORD_0
) : -EIO
;
127 static unsigned int efx_ef10_mem_map_size(struct efx_nic
*efx
)
131 bar
= efx
->type
->mem_bar
;
132 return resource_size(&efx
->pci_dev
->resource
[bar
]);
135 static bool efx_ef10_is_vf(struct efx_nic
*efx
)
137 return efx
->type
->is_vf
;
140 static int efx_ef10_get_pf_index(struct efx_nic
*efx
)
142 MCDI_DECLARE_BUF(outbuf
, MC_CMD_GET_FUNCTION_INFO_OUT_LEN
);
143 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
147 rc
= efx_mcdi_rpc(efx
, MC_CMD_GET_FUNCTION_INFO
, NULL
, 0, outbuf
,
148 sizeof(outbuf
), &outlen
);
151 if (outlen
< sizeof(outbuf
))
154 nic_data
->pf_index
= MCDI_DWORD(outbuf
, GET_FUNCTION_INFO_OUT_PF
);
158 #ifdef CONFIG_SFC_SRIOV
159 static int efx_ef10_get_vf_index(struct efx_nic
*efx
)
161 MCDI_DECLARE_BUF(outbuf
, MC_CMD_GET_FUNCTION_INFO_OUT_LEN
);
162 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
166 rc
= efx_mcdi_rpc(efx
, MC_CMD_GET_FUNCTION_INFO
, NULL
, 0, outbuf
,
167 sizeof(outbuf
), &outlen
);
170 if (outlen
< sizeof(outbuf
))
173 nic_data
->vf_index
= MCDI_DWORD(outbuf
, GET_FUNCTION_INFO_OUT_VF
);
178 static int efx_ef10_init_datapath_caps(struct efx_nic
*efx
)
180 MCDI_DECLARE_BUF(outbuf
, MC_CMD_GET_CAPABILITIES_OUT_LEN
);
181 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
185 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN
!= 0);
187 rc
= efx_mcdi_rpc(efx
, MC_CMD_GET_CAPABILITIES
, NULL
, 0,
188 outbuf
, sizeof(outbuf
), &outlen
);
191 if (outlen
< sizeof(outbuf
)) {
192 netif_err(efx
, drv
, efx
->net_dev
,
193 "unable to read datapath firmware capabilities\n");
197 nic_data
->datapath_caps
=
198 MCDI_DWORD(outbuf
, GET_CAPABILITIES_OUT_FLAGS1
);
200 /* record the DPCPU firmware IDs to determine VEB vswitching support.
202 nic_data
->rx_dpcpu_fw_id
=
203 MCDI_WORD(outbuf
, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID
);
204 nic_data
->tx_dpcpu_fw_id
=
205 MCDI_WORD(outbuf
, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID
);
207 if (!(nic_data
->datapath_caps
&
208 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN
))) {
209 netif_err(efx
, probe
, efx
->net_dev
,
210 "current firmware does not support an RX prefix\n");
217 static int efx_ef10_get_sysclk_freq(struct efx_nic
*efx
)
219 MCDI_DECLARE_BUF(outbuf
, MC_CMD_GET_CLOCK_OUT_LEN
);
222 rc
= efx_mcdi_rpc(efx
, MC_CMD_GET_CLOCK
, NULL
, 0,
223 outbuf
, sizeof(outbuf
), NULL
);
226 rc
= MCDI_DWORD(outbuf
, GET_CLOCK_OUT_SYS_FREQ
);
227 return rc
> 0 ? rc
: -ERANGE
;
230 static int efx_ef10_get_mac_address_pf(struct efx_nic
*efx
, u8
*mac_address
)
232 MCDI_DECLARE_BUF(outbuf
, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN
);
236 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN
!= 0);
238 rc
= efx_mcdi_rpc(efx
, MC_CMD_GET_MAC_ADDRESSES
, NULL
, 0,
239 outbuf
, sizeof(outbuf
), &outlen
);
242 if (outlen
< MC_CMD_GET_MAC_ADDRESSES_OUT_LEN
)
245 ether_addr_copy(mac_address
,
246 MCDI_PTR(outbuf
, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE
));
250 static int efx_ef10_get_mac_address_vf(struct efx_nic
*efx
, u8
*mac_address
)
252 MCDI_DECLARE_BUF(inbuf
, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN
);
253 MCDI_DECLARE_BUF(outbuf
, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX
);
257 MCDI_SET_DWORD(inbuf
, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID
,
258 EVB_PORT_ID_ASSIGNED
);
259 rc
= efx_mcdi_rpc(efx
, MC_CMD_VPORT_GET_MAC_ADDRESSES
, inbuf
,
260 sizeof(inbuf
), outbuf
, sizeof(outbuf
), &outlen
);
264 if (outlen
< MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN
)
267 num_addrs
= MCDI_DWORD(outbuf
,
268 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT
);
270 WARN_ON(num_addrs
!= 1);
272 ether_addr_copy(mac_address
,
273 MCDI_PTR(outbuf
, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR
));
278 static ssize_t
efx_ef10_show_link_control_flag(struct device
*dev
,
279 struct device_attribute
*attr
,
282 struct efx_nic
*efx
= pci_get_drvdata(to_pci_dev(dev
));
284 return sprintf(buf
, "%d\n",
285 ((efx
->mcdi
->fn_flags
) &
286 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL
))
290 static ssize_t
efx_ef10_show_primary_flag(struct device
*dev
,
291 struct device_attribute
*attr
,
294 struct efx_nic
*efx
= pci_get_drvdata(to_pci_dev(dev
));
296 return sprintf(buf
, "%d\n",
297 ((efx
->mcdi
->fn_flags
) &
298 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY
))
302 static struct efx_ef10_vlan
*efx_ef10_find_vlan(struct efx_nic
*efx
, u16 vid
)
304 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
305 struct efx_ef10_vlan
*vlan
;
307 WARN_ON(!mutex_is_locked(&nic_data
->vlan_lock
));
309 list_for_each_entry(vlan
, &nic_data
->vlan_list
, list
) {
310 if (vlan
->vid
== vid
)
317 static int efx_ef10_add_vlan(struct efx_nic
*efx
, u16 vid
)
319 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
320 struct efx_ef10_vlan
*vlan
;
323 mutex_lock(&nic_data
->vlan_lock
);
325 vlan
= efx_ef10_find_vlan(efx
, vid
);
327 /* We add VID 0 on init. 8021q adds it on module init
328 * for all interfaces with VLAN filtring feature.
332 netif_warn(efx
, drv
, efx
->net_dev
,
333 "VLAN %u already added\n", vid
);
339 vlan
= kzalloc(sizeof(*vlan
), GFP_KERNEL
);
345 list_add_tail(&vlan
->list
, &nic_data
->vlan_list
);
347 if (efx
->filter_state
) {
348 mutex_lock(&efx
->mac_lock
);
349 down_write(&efx
->filter_sem
);
350 rc
= efx_ef10_filter_add_vlan(efx
, vlan
->vid
);
351 up_write(&efx
->filter_sem
);
352 mutex_unlock(&efx
->mac_lock
);
354 goto fail_filter_add_vlan
;
358 mutex_unlock(&nic_data
->vlan_lock
);
361 fail_filter_add_vlan
:
362 list_del(&vlan
->list
);
366 mutex_unlock(&nic_data
->vlan_lock
);
370 static void efx_ef10_del_vlan_internal(struct efx_nic
*efx
,
371 struct efx_ef10_vlan
*vlan
)
373 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
375 WARN_ON(!mutex_is_locked(&nic_data
->vlan_lock
));
377 if (efx
->filter_state
) {
378 down_write(&efx
->filter_sem
);
379 efx_ef10_filter_del_vlan(efx
, vlan
->vid
);
380 up_write(&efx
->filter_sem
);
383 list_del(&vlan
->list
);
387 static int efx_ef10_del_vlan(struct efx_nic
*efx
, u16 vid
)
389 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
390 struct efx_ef10_vlan
*vlan
;
393 /* 8021q removes VID 0 on module unload for all interfaces
394 * with VLAN filtering feature. We need to keep it to receive
400 mutex_lock(&nic_data
->vlan_lock
);
402 vlan
= efx_ef10_find_vlan(efx
, vid
);
404 netif_err(efx
, drv
, efx
->net_dev
,
405 "VLAN %u to be deleted not found\n", vid
);
408 efx_ef10_del_vlan_internal(efx
, vlan
);
411 mutex_unlock(&nic_data
->vlan_lock
);
416 static void efx_ef10_cleanup_vlans(struct efx_nic
*efx
)
418 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
419 struct efx_ef10_vlan
*vlan
, *next_vlan
;
421 mutex_lock(&nic_data
->vlan_lock
);
422 list_for_each_entry_safe(vlan
, next_vlan
, &nic_data
->vlan_list
, list
)
423 efx_ef10_del_vlan_internal(efx
, vlan
);
424 mutex_unlock(&nic_data
->vlan_lock
);
427 static DEVICE_ATTR(link_control_flag
, 0444, efx_ef10_show_link_control_flag
,
429 static DEVICE_ATTR(primary_flag
, 0444, efx_ef10_show_primary_flag
, NULL
);
431 static int efx_ef10_probe(struct efx_nic
*efx
)
433 struct efx_ef10_nic_data
*nic_data
;
434 struct net_device
*net_dev
= efx
->net_dev
;
437 /* We can have one VI for each 8K region. However, until we
438 * use TX option descriptors we need two TX queues per channel.
440 efx
->max_channels
= min_t(unsigned int,
442 efx_ef10_mem_map_size(efx
) /
443 (EFX_VI_PAGE_SIZE
* EFX_TXQ_TYPES
));
444 efx
->max_tx_channels
= efx
->max_channels
;
445 if (WARN_ON(efx
->max_channels
== 0))
448 nic_data
= kzalloc(sizeof(*nic_data
), GFP_KERNEL
);
451 efx
->nic_data
= nic_data
;
453 /* we assume later that we can copy from this buffer in dwords */
454 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2
% 4);
456 rc
= efx_nic_alloc_buffer(efx
, &nic_data
->mcdi_buf
,
457 8 + MCDI_CTL_SDU_LEN_MAX_V2
, GFP_KERNEL
);
461 /* Get the MC's warm boot count. In case it's rebooting right
462 * now, be prepared to retry.
466 rc
= efx_ef10_get_warm_boot_count(efx
);
473 nic_data
->warm_boot_count
= rc
;
475 nic_data
->rx_rss_context
= EFX_EF10_RSS_CONTEXT_INVALID
;
477 nic_data
->vport_id
= EVB_PORT_ID_ASSIGNED
;
479 /* In case we're recovering from a crash (kexec), we want to
480 * cancel any outstanding request by the previous user of this
481 * function. We send a special message using the least
482 * significant bits of the 'high' (doorbell) register.
484 _efx_writed(efx
, cpu_to_le32(1), ER_DZ_MC_DB_HWRD
);
486 rc
= efx_mcdi_init(efx
);
490 /* Reset (most) configuration for this function */
491 rc
= efx_mcdi_reset(efx
, RESET_TYPE_ALL
);
495 /* Enable event logging */
496 rc
= efx_mcdi_log_ctrl(efx
, true, false, 0);
500 rc
= device_create_file(&efx
->pci_dev
->dev
,
501 &dev_attr_link_control_flag
);
505 rc
= device_create_file(&efx
->pci_dev
->dev
, &dev_attr_primary_flag
);
509 rc
= efx_ef10_get_pf_index(efx
);
513 rc
= efx_ef10_init_datapath_caps(efx
);
517 efx
->rx_packet_len_offset
=
518 ES_DZ_RX_PREFIX_PKTLEN_OFST
- ES_DZ_RX_PREFIX_SIZE
;
520 rc
= efx_mcdi_port_get_number(efx
);
524 net_dev
->dev_port
= rc
;
526 rc
= efx
->type
->get_mac_address(efx
, efx
->net_dev
->perm_addr
);
530 rc
= efx_ef10_get_sysclk_freq(efx
);
533 efx
->timer_quantum_ns
= 1536000 / rc
; /* 1536 cycles */
535 /* Check whether firmware supports bug 35388 workaround.
536 * First try to enable it, then if we get EPERM, just
537 * ask if it's already enabled
539 rc
= efx_mcdi_set_workaround(efx
, MC_CMD_WORKAROUND_BUG35388
, true, NULL
);
541 nic_data
->workaround_35388
= true;
542 } else if (rc
== -EPERM
) {
543 unsigned int enabled
;
545 rc
= efx_mcdi_get_workarounds(efx
, NULL
, &enabled
);
548 nic_data
->workaround_35388
= enabled
&
549 MC_CMD_GET_WORKAROUNDS_OUT_BUG35388
;
550 } else if (rc
!= -ENOSYS
&& rc
!= -ENOENT
) {
553 netif_dbg(efx
, probe
, efx
->net_dev
,
554 "workaround for bug 35388 is %sabled\n",
555 nic_data
->workaround_35388
? "en" : "dis");
557 rc
= efx_mcdi_mon_probe(efx
);
558 if (rc
&& rc
!= -EPERM
)
561 efx_ptp_probe(efx
, NULL
);
563 #ifdef CONFIG_SFC_SRIOV
564 if ((efx
->pci_dev
->physfn
) && (!efx
->pci_dev
->is_physfn
)) {
565 struct pci_dev
*pci_dev_pf
= efx
->pci_dev
->physfn
;
566 struct efx_nic
*efx_pf
= pci_get_drvdata(pci_dev_pf
);
568 efx_pf
->type
->get_mac_address(efx_pf
, nic_data
->port_id
);
571 ether_addr_copy(nic_data
->port_id
, efx
->net_dev
->perm_addr
);
573 INIT_LIST_HEAD(&nic_data
->vlan_list
);
574 mutex_init(&nic_data
->vlan_lock
);
576 /* Add unspecified VID to support VLAN filtering being disabled */
577 rc
= efx_ef10_add_vlan(efx
, EFX_FILTER_VID_UNSPEC
);
579 goto fail_add_vid_unspec
;
581 /* If VLAN filtering is enabled, we need VID 0 to get untagged
582 * traffic. It is added automatically if 8021q module is loaded,
583 * but we can't rely on it since module may be not loaded.
585 rc
= efx_ef10_add_vlan(efx
, 0);
592 efx_ef10_cleanup_vlans(efx
);
594 mutex_destroy(&nic_data
->vlan_lock
);
596 efx_mcdi_mon_remove(efx
);
598 device_remove_file(&efx
->pci_dev
->dev
, &dev_attr_primary_flag
);
600 device_remove_file(&efx
->pci_dev
->dev
, &dev_attr_link_control_flag
);
604 efx_nic_free_buffer(efx
, &nic_data
->mcdi_buf
);
607 efx
->nic_data
= NULL
;
611 static int efx_ef10_free_vis(struct efx_nic
*efx
)
613 MCDI_DECLARE_BUF_ERR(outbuf
);
615 int rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_FREE_VIS
, NULL
, 0,
616 outbuf
, sizeof(outbuf
), &outlen
);
618 /* -EALREADY means nothing to free, so ignore */
622 efx_mcdi_display_error(efx
, MC_CMD_FREE_VIS
, 0, outbuf
, outlen
,
629 static void efx_ef10_free_piobufs(struct efx_nic
*efx
)
631 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
632 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FREE_PIOBUF_IN_LEN
);
636 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN
!= 0);
638 for (i
= 0; i
< nic_data
->n_piobufs
; i
++) {
639 MCDI_SET_DWORD(inbuf
, FREE_PIOBUF_IN_PIOBUF_HANDLE
,
640 nic_data
->piobuf_handle
[i
]);
641 rc
= efx_mcdi_rpc(efx
, MC_CMD_FREE_PIOBUF
, inbuf
, sizeof(inbuf
),
646 nic_data
->n_piobufs
= 0;
649 static int efx_ef10_alloc_piobufs(struct efx_nic
*efx
, unsigned int n
)
651 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
652 MCDI_DECLARE_BUF(outbuf
, MC_CMD_ALLOC_PIOBUF_OUT_LEN
);
657 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN
!= 0);
659 for (i
= 0; i
< n
; i
++) {
660 rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_ALLOC_PIOBUF
, NULL
, 0,
661 outbuf
, sizeof(outbuf
), &outlen
);
663 /* Don't display the MC error if we didn't have space
666 if (!(efx_ef10_is_vf(efx
) && rc
== -ENOSPC
))
667 efx_mcdi_display_error(efx
, MC_CMD_ALLOC_PIOBUF
,
668 0, outbuf
, outlen
, rc
);
671 if (outlen
< MC_CMD_ALLOC_PIOBUF_OUT_LEN
) {
675 nic_data
->piobuf_handle
[i
] =
676 MCDI_DWORD(outbuf
, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE
);
677 netif_dbg(efx
, probe
, efx
->net_dev
,
678 "allocated PIO buffer %u handle %x\n", i
,
679 nic_data
->piobuf_handle
[i
]);
682 nic_data
->n_piobufs
= i
;
684 efx_ef10_free_piobufs(efx
);
688 static int efx_ef10_link_piobufs(struct efx_nic
*efx
)
690 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
691 _MCDI_DECLARE_BUF(inbuf
,
692 max(MC_CMD_LINK_PIOBUF_IN_LEN
,
693 MC_CMD_UNLINK_PIOBUF_IN_LEN
));
694 struct efx_channel
*channel
;
695 struct efx_tx_queue
*tx_queue
;
696 unsigned int offset
, index
;
699 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN
!= 0);
700 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN
!= 0);
702 memset(inbuf
, 0, sizeof(inbuf
));
704 /* Link a buffer to each VI in the write-combining mapping */
705 for (index
= 0; index
< nic_data
->n_piobufs
; ++index
) {
706 MCDI_SET_DWORD(inbuf
, LINK_PIOBUF_IN_PIOBUF_HANDLE
,
707 nic_data
->piobuf_handle
[index
]);
708 MCDI_SET_DWORD(inbuf
, LINK_PIOBUF_IN_TXQ_INSTANCE
,
709 nic_data
->pio_write_vi_base
+ index
);
710 rc
= efx_mcdi_rpc(efx
, MC_CMD_LINK_PIOBUF
,
711 inbuf
, MC_CMD_LINK_PIOBUF_IN_LEN
,
714 netif_err(efx
, drv
, efx
->net_dev
,
715 "failed to link VI %u to PIO buffer %u (%d)\n",
716 nic_data
->pio_write_vi_base
+ index
, index
,
720 netif_dbg(efx
, probe
, efx
->net_dev
,
721 "linked VI %u to PIO buffer %u\n",
722 nic_data
->pio_write_vi_base
+ index
, index
);
725 /* Link a buffer to each TX queue */
726 efx_for_each_channel(channel
, efx
) {
727 efx_for_each_channel_tx_queue(tx_queue
, channel
) {
728 /* We assign the PIO buffers to queues in
729 * reverse order to allow for the following
732 offset
= ((efx
->tx_channel_offset
+ efx
->n_tx_channels
-
733 tx_queue
->channel
->channel
- 1) *
735 index
= offset
/ ER_DZ_TX_PIOBUF_SIZE
;
736 offset
= offset
% ER_DZ_TX_PIOBUF_SIZE
;
738 /* When the host page size is 4K, the first
739 * host page in the WC mapping may be within
740 * the same VI page as the last TX queue. We
741 * can only link one buffer to each VI.
743 if (tx_queue
->queue
== nic_data
->pio_write_vi_base
) {
747 MCDI_SET_DWORD(inbuf
,
748 LINK_PIOBUF_IN_PIOBUF_HANDLE
,
749 nic_data
->piobuf_handle
[index
]);
750 MCDI_SET_DWORD(inbuf
,
751 LINK_PIOBUF_IN_TXQ_INSTANCE
,
753 rc
= efx_mcdi_rpc(efx
, MC_CMD_LINK_PIOBUF
,
754 inbuf
, MC_CMD_LINK_PIOBUF_IN_LEN
,
759 /* This is non-fatal; the TX path just
760 * won't use PIO for this queue
762 netif_err(efx
, drv
, efx
->net_dev
,
763 "failed to link VI %u to PIO buffer %u (%d)\n",
764 tx_queue
->queue
, index
, rc
);
765 tx_queue
->piobuf
= NULL
;
768 nic_data
->pio_write_base
+
769 index
* EFX_VI_PAGE_SIZE
+ offset
;
770 tx_queue
->piobuf_offset
= offset
;
771 netif_dbg(efx
, probe
, efx
->net_dev
,
772 "linked VI %u to PIO buffer %u offset %x addr %p\n",
773 tx_queue
->queue
, index
,
774 tx_queue
->piobuf_offset
,
784 MCDI_SET_DWORD(inbuf
, UNLINK_PIOBUF_IN_TXQ_INSTANCE
,
785 nic_data
->pio_write_vi_base
+ index
);
786 efx_mcdi_rpc(efx
, MC_CMD_UNLINK_PIOBUF
,
787 inbuf
, MC_CMD_UNLINK_PIOBUF_IN_LEN
,
793 static void efx_ef10_forget_old_piobufs(struct efx_nic
*efx
)
795 struct efx_channel
*channel
;
796 struct efx_tx_queue
*tx_queue
;
798 /* All our existing PIO buffers went away */
799 efx_for_each_channel(channel
, efx
)
800 efx_for_each_channel_tx_queue(tx_queue
, channel
)
801 tx_queue
->piobuf
= NULL
;
804 #else /* !EFX_USE_PIO */
806 static int efx_ef10_alloc_piobufs(struct efx_nic
*efx
, unsigned int n
)
808 return n
== 0 ? 0 : -ENOBUFS
;
811 static int efx_ef10_link_piobufs(struct efx_nic
*efx
)
816 static void efx_ef10_free_piobufs(struct efx_nic
*efx
)
820 static void efx_ef10_forget_old_piobufs(struct efx_nic
*efx
)
824 #endif /* EFX_USE_PIO */
826 static void efx_ef10_remove(struct efx_nic
*efx
)
828 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
831 #ifdef CONFIG_SFC_SRIOV
832 struct efx_ef10_nic_data
*nic_data_pf
;
833 struct pci_dev
*pci_dev_pf
;
834 struct efx_nic
*efx_pf
;
837 if (efx
->pci_dev
->is_virtfn
) {
838 pci_dev_pf
= efx
->pci_dev
->physfn
;
840 efx_pf
= pci_get_drvdata(pci_dev_pf
);
841 nic_data_pf
= efx_pf
->nic_data
;
842 vf
= nic_data_pf
->vf
+ nic_data
->vf_index
;
845 netif_info(efx
, drv
, efx
->net_dev
,
846 "Could not get the PF id from VF\n");
850 efx_ef10_cleanup_vlans(efx
);
851 mutex_destroy(&nic_data
->vlan_lock
);
855 efx_mcdi_mon_remove(efx
);
857 efx_ef10_rx_free_indir_table(efx
);
859 if (nic_data
->wc_membase
)
860 iounmap(nic_data
->wc_membase
);
862 rc
= efx_ef10_free_vis(efx
);
865 if (!nic_data
->must_restore_piobufs
)
866 efx_ef10_free_piobufs(efx
);
868 device_remove_file(&efx
->pci_dev
->dev
, &dev_attr_primary_flag
);
869 device_remove_file(&efx
->pci_dev
->dev
, &dev_attr_link_control_flag
);
872 efx_nic_free_buffer(efx
, &nic_data
->mcdi_buf
);
876 static int efx_ef10_probe_pf(struct efx_nic
*efx
)
878 return efx_ef10_probe(efx
);
881 int efx_ef10_vadaptor_query(struct efx_nic
*efx
, unsigned int port_id
,
882 u32
*port_flags
, u32
*vadaptor_flags
,
883 unsigned int *vlan_tags
)
885 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
886 MCDI_DECLARE_BUF(inbuf
, MC_CMD_VADAPTOR_QUERY_IN_LEN
);
887 MCDI_DECLARE_BUF(outbuf
, MC_CMD_VADAPTOR_QUERY_OUT_LEN
);
891 if (nic_data
->datapath_caps
&
892 (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN
)) {
893 MCDI_SET_DWORD(inbuf
, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID
,
896 rc
= efx_mcdi_rpc(efx
, MC_CMD_VADAPTOR_QUERY
, inbuf
, sizeof(inbuf
),
897 outbuf
, sizeof(outbuf
), &outlen
);
901 if (outlen
< sizeof(outbuf
)) {
908 *port_flags
= MCDI_DWORD(outbuf
, VADAPTOR_QUERY_OUT_PORT_FLAGS
);
911 MCDI_DWORD(outbuf
, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS
);
915 VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS
);
920 int efx_ef10_vadaptor_alloc(struct efx_nic
*efx
, unsigned int port_id
)
922 MCDI_DECLARE_BUF(inbuf
, MC_CMD_VADAPTOR_ALLOC_IN_LEN
);
924 MCDI_SET_DWORD(inbuf
, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID
, port_id
);
925 return efx_mcdi_rpc(efx
, MC_CMD_VADAPTOR_ALLOC
, inbuf
, sizeof(inbuf
),
929 int efx_ef10_vadaptor_free(struct efx_nic
*efx
, unsigned int port_id
)
931 MCDI_DECLARE_BUF(inbuf
, MC_CMD_VADAPTOR_FREE_IN_LEN
);
933 MCDI_SET_DWORD(inbuf
, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID
, port_id
);
934 return efx_mcdi_rpc(efx
, MC_CMD_VADAPTOR_FREE
, inbuf
, sizeof(inbuf
),
938 int efx_ef10_vport_add_mac(struct efx_nic
*efx
,
939 unsigned int port_id
, u8
*mac
)
941 MCDI_DECLARE_BUF(inbuf
, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN
);
943 MCDI_SET_DWORD(inbuf
, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID
, port_id
);
944 ether_addr_copy(MCDI_PTR(inbuf
, VPORT_ADD_MAC_ADDRESS_IN_MACADDR
), mac
);
946 return efx_mcdi_rpc(efx
, MC_CMD_VPORT_ADD_MAC_ADDRESS
, inbuf
,
947 sizeof(inbuf
), NULL
, 0, NULL
);
950 int efx_ef10_vport_del_mac(struct efx_nic
*efx
,
951 unsigned int port_id
, u8
*mac
)
953 MCDI_DECLARE_BUF(inbuf
, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN
);
955 MCDI_SET_DWORD(inbuf
, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID
, port_id
);
956 ether_addr_copy(MCDI_PTR(inbuf
, VPORT_DEL_MAC_ADDRESS_IN_MACADDR
), mac
);
958 return efx_mcdi_rpc(efx
, MC_CMD_VPORT_DEL_MAC_ADDRESS
, inbuf
,
959 sizeof(inbuf
), NULL
, 0, NULL
);
962 #ifdef CONFIG_SFC_SRIOV
963 static int efx_ef10_probe_vf(struct efx_nic
*efx
)
966 struct pci_dev
*pci_dev_pf
;
968 /* If the parent PF has no VF data structure, it doesn't know about this
969 * VF so fail probe. The VF needs to be re-created. This can happen
970 * if the PF driver is unloaded while the VF is assigned to a guest.
972 pci_dev_pf
= efx
->pci_dev
->physfn
;
974 struct efx_nic
*efx_pf
= pci_get_drvdata(pci_dev_pf
);
975 struct efx_ef10_nic_data
*nic_data_pf
= efx_pf
->nic_data
;
977 if (!nic_data_pf
->vf
) {
978 netif_info(efx
, drv
, efx
->net_dev
,
979 "The VF cannot link to its parent PF; "
980 "please destroy and re-create the VF\n");
985 rc
= efx_ef10_probe(efx
);
989 rc
= efx_ef10_get_vf_index(efx
);
993 if (efx
->pci_dev
->is_virtfn
) {
994 if (efx
->pci_dev
->physfn
) {
995 struct efx_nic
*efx_pf
=
996 pci_get_drvdata(efx
->pci_dev
->physfn
);
997 struct efx_ef10_nic_data
*nic_data_p
= efx_pf
->nic_data
;
998 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1000 nic_data_p
->vf
[nic_data
->vf_index
].efx
= efx
;
1001 nic_data_p
->vf
[nic_data
->vf_index
].pci_dev
=
1004 netif_info(efx
, drv
, efx
->net_dev
,
1005 "Could not get the PF id from VF\n");
1011 efx_ef10_remove(efx
);
1015 static int efx_ef10_probe_vf(struct efx_nic
*efx
__attribute__ ((unused
)))
1021 static int efx_ef10_alloc_vis(struct efx_nic
*efx
,
1022 unsigned int min_vis
, unsigned int max_vis
)
1024 MCDI_DECLARE_BUF(inbuf
, MC_CMD_ALLOC_VIS_IN_LEN
);
1025 MCDI_DECLARE_BUF(outbuf
, MC_CMD_ALLOC_VIS_OUT_LEN
);
1026 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1030 MCDI_SET_DWORD(inbuf
, ALLOC_VIS_IN_MIN_VI_COUNT
, min_vis
);
1031 MCDI_SET_DWORD(inbuf
, ALLOC_VIS_IN_MAX_VI_COUNT
, max_vis
);
1032 rc
= efx_mcdi_rpc(efx
, MC_CMD_ALLOC_VIS
, inbuf
, sizeof(inbuf
),
1033 outbuf
, sizeof(outbuf
), &outlen
);
1037 if (outlen
< MC_CMD_ALLOC_VIS_OUT_LEN
)
1040 netif_dbg(efx
, drv
, efx
->net_dev
, "base VI is A0x%03x\n",
1041 MCDI_DWORD(outbuf
, ALLOC_VIS_OUT_VI_BASE
));
1043 nic_data
->vi_base
= MCDI_DWORD(outbuf
, ALLOC_VIS_OUT_VI_BASE
);
1044 nic_data
->n_allocated_vis
= MCDI_DWORD(outbuf
, ALLOC_VIS_OUT_VI_COUNT
);
1048 /* Note that the failure path of this function does not free
1049 * resources, as this will be done by efx_ef10_remove().
1051 static int efx_ef10_dimension_resources(struct efx_nic
*efx
)
1053 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1054 unsigned int uc_mem_map_size
, wc_mem_map_size
;
1055 unsigned int min_vis
= max(EFX_TXQ_TYPES
,
1056 efx_separate_tx_channels
? 2 : 1);
1057 unsigned int channel_vis
, pio_write_vi_base
, max_vis
;
1058 void __iomem
*membase
;
1061 channel_vis
= max(efx
->n_channels
, efx
->n_tx_channels
* EFX_TXQ_TYPES
);
1064 /* Try to allocate PIO buffers if wanted and if the full
1065 * number of PIO buffers would be sufficient to allocate one
1066 * copy-buffer per TX channel. Failure is non-fatal, as there
1067 * are only a small number of PIO buffers shared between all
1068 * functions of the controller.
1070 if (efx_piobuf_size
!= 0 &&
1071 ER_DZ_TX_PIOBUF_SIZE
/ efx_piobuf_size
* EF10_TX_PIOBUF_COUNT
>=
1072 efx
->n_tx_channels
) {
1073 unsigned int n_piobufs
=
1074 DIV_ROUND_UP(efx
->n_tx_channels
,
1075 ER_DZ_TX_PIOBUF_SIZE
/ efx_piobuf_size
);
1077 rc
= efx_ef10_alloc_piobufs(efx
, n_piobufs
);
1079 netif_err(efx
, probe
, efx
->net_dev
,
1080 "failed to allocate PIO buffers (%d)\n", rc
);
1082 netif_dbg(efx
, probe
, efx
->net_dev
,
1083 "allocated %u PIO buffers\n", n_piobufs
);
1086 nic_data
->n_piobufs
= 0;
1089 /* PIO buffers should be mapped with write-combining enabled,
1090 * and we want to make single UC and WC mappings rather than
1091 * several of each (in fact that's the only option if host
1092 * page size is >4K). So we may allocate some extra VIs just
1093 * for writing PIO buffers through.
1095 * The UC mapping contains (channel_vis - 1) complete VIs and the
1096 * first half of the next VI. Then the WC mapping begins with
1097 * the second half of this last VI.
1099 uc_mem_map_size
= PAGE_ALIGN((channel_vis
- 1) * EFX_VI_PAGE_SIZE
+
1101 if (nic_data
->n_piobufs
) {
1102 /* pio_write_vi_base rounds down to give the number of complete
1103 * VIs inside the UC mapping.
1105 pio_write_vi_base
= uc_mem_map_size
/ EFX_VI_PAGE_SIZE
;
1106 wc_mem_map_size
= (PAGE_ALIGN((pio_write_vi_base
+
1107 nic_data
->n_piobufs
) *
1110 max_vis
= pio_write_vi_base
+ nic_data
->n_piobufs
;
1112 pio_write_vi_base
= 0;
1113 wc_mem_map_size
= 0;
1114 max_vis
= channel_vis
;
1117 /* In case the last attached driver failed to free VIs, do it now */
1118 rc
= efx_ef10_free_vis(efx
);
1122 rc
= efx_ef10_alloc_vis(efx
, min_vis
, max_vis
);
1126 if (nic_data
->n_allocated_vis
< channel_vis
) {
1127 netif_info(efx
, drv
, efx
->net_dev
,
1128 "Could not allocate enough VIs to satisfy RSS"
1129 " requirements. Performance may not be optimal.\n");
1130 /* We didn't get the VIs to populate our channels.
1131 * We could keep what we got but then we'd have more
1132 * interrupts than we need.
1133 * Instead calculate new max_channels and restart
1135 efx
->max_channels
= nic_data
->n_allocated_vis
;
1136 efx
->max_tx_channels
=
1137 nic_data
->n_allocated_vis
/ EFX_TXQ_TYPES
;
1139 efx_ef10_free_vis(efx
);
1143 /* If we didn't get enough VIs to map all the PIO buffers, free the
1146 if (nic_data
->n_piobufs
&&
1147 nic_data
->n_allocated_vis
<
1148 pio_write_vi_base
+ nic_data
->n_piobufs
) {
1149 netif_dbg(efx
, probe
, efx
->net_dev
,
1150 "%u VIs are not sufficient to map %u PIO buffers\n",
1151 nic_data
->n_allocated_vis
, nic_data
->n_piobufs
);
1152 efx_ef10_free_piobufs(efx
);
1155 /* Shrink the original UC mapping of the memory BAR */
1156 membase
= ioremap_nocache(efx
->membase_phys
, uc_mem_map_size
);
1158 netif_err(efx
, probe
, efx
->net_dev
,
1159 "could not shrink memory BAR to %x\n",
1163 iounmap(efx
->membase
);
1164 efx
->membase
= membase
;
1166 /* Set up the WC mapping if needed */
1167 if (wc_mem_map_size
) {
1168 nic_data
->wc_membase
= ioremap_wc(efx
->membase_phys
+
1171 if (!nic_data
->wc_membase
) {
1172 netif_err(efx
, probe
, efx
->net_dev
,
1173 "could not allocate WC mapping of size %x\n",
1177 nic_data
->pio_write_vi_base
= pio_write_vi_base
;
1178 nic_data
->pio_write_base
=
1179 nic_data
->wc_membase
+
1180 (pio_write_vi_base
* EFX_VI_PAGE_SIZE
+ ER_DZ_TX_PIOBUF
-
1183 rc
= efx_ef10_link_piobufs(efx
);
1185 efx_ef10_free_piobufs(efx
);
1188 netif_dbg(efx
, probe
, efx
->net_dev
,
1189 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
1190 &efx
->membase_phys
, efx
->membase
, uc_mem_map_size
,
1191 nic_data
->wc_membase
, wc_mem_map_size
);
1196 static int efx_ef10_init_nic(struct efx_nic
*efx
)
1198 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1201 if (nic_data
->must_check_datapath_caps
) {
1202 rc
= efx_ef10_init_datapath_caps(efx
);
1205 nic_data
->must_check_datapath_caps
= false;
1208 if (nic_data
->must_realloc_vis
) {
1209 /* We cannot let the number of VIs change now */
1210 rc
= efx_ef10_alloc_vis(efx
, nic_data
->n_allocated_vis
,
1211 nic_data
->n_allocated_vis
);
1214 nic_data
->must_realloc_vis
= false;
1217 if (nic_data
->must_restore_piobufs
&& nic_data
->n_piobufs
) {
1218 rc
= efx_ef10_alloc_piobufs(efx
, nic_data
->n_piobufs
);
1220 rc
= efx_ef10_link_piobufs(efx
);
1222 efx_ef10_free_piobufs(efx
);
1225 /* Log an error on failure, but this is non-fatal */
1227 netif_err(efx
, drv
, efx
->net_dev
,
1228 "failed to restore PIO buffers (%d)\n", rc
);
1229 nic_data
->must_restore_piobufs
= false;
1232 /* don't fail init if RSS setup doesn't work */
1233 efx
->type
->rx_push_rss_config(efx
, false, efx
->rx_indir_table
);
1238 static void efx_ef10_reset_mc_allocations(struct efx_nic
*efx
)
1240 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1241 #ifdef CONFIG_SFC_SRIOV
1245 /* All our allocations have been reset */
1246 nic_data
->must_realloc_vis
= true;
1247 nic_data
->must_restore_filters
= true;
1248 nic_data
->must_restore_piobufs
= true;
1249 efx_ef10_forget_old_piobufs(efx
);
1250 nic_data
->rx_rss_context
= EFX_EF10_RSS_CONTEXT_INVALID
;
1252 /* Driver-created vswitches and vports must be re-created */
1253 nic_data
->must_probe_vswitching
= true;
1254 nic_data
->vport_id
= EVB_PORT_ID_ASSIGNED
;
1255 #ifdef CONFIG_SFC_SRIOV
1257 for (i
= 0; i
< efx
->vf_count
; i
++)
1258 nic_data
->vf
[i
].vport_id
= 0;
1262 static enum reset_type
efx_ef10_map_reset_reason(enum reset_type reason
)
1264 if (reason
== RESET_TYPE_MC_FAILURE
)
1265 return RESET_TYPE_DATAPATH
;
1267 return efx_mcdi_map_reset_reason(reason
);
1270 static int efx_ef10_map_reset_flags(u32
*flags
)
1273 EF10_RESET_PORT
= ((ETH_RESET_MAC
| ETH_RESET_PHY
) <<
1274 ETH_RESET_SHARED_SHIFT
),
1275 EF10_RESET_MC
= ((ETH_RESET_DMA
| ETH_RESET_FILTER
|
1276 ETH_RESET_OFFLOAD
| ETH_RESET_MAC
|
1277 ETH_RESET_PHY
| ETH_RESET_MGMT
) <<
1278 ETH_RESET_SHARED_SHIFT
)
1281 /* We assume for now that our PCI function is permitted to
1285 if ((*flags
& EF10_RESET_MC
) == EF10_RESET_MC
) {
1286 *flags
&= ~EF10_RESET_MC
;
1287 return RESET_TYPE_WORLD
;
1290 if ((*flags
& EF10_RESET_PORT
) == EF10_RESET_PORT
) {
1291 *flags
&= ~EF10_RESET_PORT
;
1292 return RESET_TYPE_ALL
;
1295 /* no invisible reset implemented */
1300 static int efx_ef10_reset(struct efx_nic
*efx
, enum reset_type reset_type
)
1302 int rc
= efx_mcdi_reset(efx
, reset_type
);
1304 /* Unprivileged functions return -EPERM, but need to return success
1305 * here so that the datapath is brought back up.
1307 if (reset_type
== RESET_TYPE_WORLD
&& rc
== -EPERM
)
1310 /* If it was a port reset, trigger reallocation of MC resources.
1311 * Note that on an MC reset nothing needs to be done now because we'll
1312 * detect the MC reset later and handle it then.
1313 * For an FLR, we never get an MC reset event, but the MC has reset all
1314 * resources assigned to us, so we have to trigger reallocation now.
1316 if ((reset_type
== RESET_TYPE_ALL
||
1317 reset_type
== RESET_TYPE_MCDI_TIMEOUT
) && !rc
)
1318 efx_ef10_reset_mc_allocations(efx
);
1322 #define EF10_DMA_STAT(ext_name, mcdi_name) \
1323 [EF10_STAT_ ## ext_name] = \
1324 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1325 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
1326 [EF10_STAT_ ## int_name] = \
1327 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1328 #define EF10_OTHER_STAT(ext_name) \
1329 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1330 #define GENERIC_SW_STAT(ext_name) \
1331 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1333 static const struct efx_hw_stat_desc efx_ef10_stat_desc
[EF10_STAT_COUNT
] = {
1334 EF10_DMA_STAT(port_tx_bytes
, TX_BYTES
),
1335 EF10_DMA_STAT(port_tx_packets
, TX_PKTS
),
1336 EF10_DMA_STAT(port_tx_pause
, TX_PAUSE_PKTS
),
1337 EF10_DMA_STAT(port_tx_control
, TX_CONTROL_PKTS
),
1338 EF10_DMA_STAT(port_tx_unicast
, TX_UNICAST_PKTS
),
1339 EF10_DMA_STAT(port_tx_multicast
, TX_MULTICAST_PKTS
),
1340 EF10_DMA_STAT(port_tx_broadcast
, TX_BROADCAST_PKTS
),
1341 EF10_DMA_STAT(port_tx_lt64
, TX_LT64_PKTS
),
1342 EF10_DMA_STAT(port_tx_64
, TX_64_PKTS
),
1343 EF10_DMA_STAT(port_tx_65_to_127
, TX_65_TO_127_PKTS
),
1344 EF10_DMA_STAT(port_tx_128_to_255
, TX_128_TO_255_PKTS
),
1345 EF10_DMA_STAT(port_tx_256_to_511
, TX_256_TO_511_PKTS
),
1346 EF10_DMA_STAT(port_tx_512_to_1023
, TX_512_TO_1023_PKTS
),
1347 EF10_DMA_STAT(port_tx_1024_to_15xx
, TX_1024_TO_15XX_PKTS
),
1348 EF10_DMA_STAT(port_tx_15xx_to_jumbo
, TX_15XX_TO_JUMBO_PKTS
),
1349 EF10_DMA_STAT(port_rx_bytes
, RX_BYTES
),
1350 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes
, RX_BAD_BYTES
),
1351 EF10_OTHER_STAT(port_rx_good_bytes
),
1352 EF10_OTHER_STAT(port_rx_bad_bytes
),
1353 EF10_DMA_STAT(port_rx_packets
, RX_PKTS
),
1354 EF10_DMA_STAT(port_rx_good
, RX_GOOD_PKTS
),
1355 EF10_DMA_STAT(port_rx_bad
, RX_BAD_FCS_PKTS
),
1356 EF10_DMA_STAT(port_rx_pause
, RX_PAUSE_PKTS
),
1357 EF10_DMA_STAT(port_rx_control
, RX_CONTROL_PKTS
),
1358 EF10_DMA_STAT(port_rx_unicast
, RX_UNICAST_PKTS
),
1359 EF10_DMA_STAT(port_rx_multicast
, RX_MULTICAST_PKTS
),
1360 EF10_DMA_STAT(port_rx_broadcast
, RX_BROADCAST_PKTS
),
1361 EF10_DMA_STAT(port_rx_lt64
, RX_UNDERSIZE_PKTS
),
1362 EF10_DMA_STAT(port_rx_64
, RX_64_PKTS
),
1363 EF10_DMA_STAT(port_rx_65_to_127
, RX_65_TO_127_PKTS
),
1364 EF10_DMA_STAT(port_rx_128_to_255
, RX_128_TO_255_PKTS
),
1365 EF10_DMA_STAT(port_rx_256_to_511
, RX_256_TO_511_PKTS
),
1366 EF10_DMA_STAT(port_rx_512_to_1023
, RX_512_TO_1023_PKTS
),
1367 EF10_DMA_STAT(port_rx_1024_to_15xx
, RX_1024_TO_15XX_PKTS
),
1368 EF10_DMA_STAT(port_rx_15xx_to_jumbo
, RX_15XX_TO_JUMBO_PKTS
),
1369 EF10_DMA_STAT(port_rx_gtjumbo
, RX_GTJUMBO_PKTS
),
1370 EF10_DMA_STAT(port_rx_bad_gtjumbo
, RX_JABBER_PKTS
),
1371 EF10_DMA_STAT(port_rx_overflow
, RX_OVERFLOW_PKTS
),
1372 EF10_DMA_STAT(port_rx_align_error
, RX_ALIGN_ERROR_PKTS
),
1373 EF10_DMA_STAT(port_rx_length_error
, RX_LENGTH_ERROR_PKTS
),
1374 EF10_DMA_STAT(port_rx_nodesc_drops
, RX_NODESC_DROPS
),
1375 GENERIC_SW_STAT(rx_nodesc_trunc
),
1376 GENERIC_SW_STAT(rx_noskb_drops
),
1377 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow
, PM_TRUNC_BB_OVERFLOW
),
1378 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow
, PM_DISCARD_BB_OVERFLOW
),
1379 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full
, PM_TRUNC_VFIFO_FULL
),
1380 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full
, PM_DISCARD_VFIFO_FULL
),
1381 EF10_DMA_STAT(port_rx_pm_trunc_qbb
, PM_TRUNC_QBB
),
1382 EF10_DMA_STAT(port_rx_pm_discard_qbb
, PM_DISCARD_QBB
),
1383 EF10_DMA_STAT(port_rx_pm_discard_mapping
, PM_DISCARD_MAPPING
),
1384 EF10_DMA_STAT(port_rx_dp_q_disabled_packets
, RXDP_Q_DISABLED_PKTS
),
1385 EF10_DMA_STAT(port_rx_dp_di_dropped_packets
, RXDP_DI_DROPPED_PKTS
),
1386 EF10_DMA_STAT(port_rx_dp_streaming_packets
, RXDP_STREAMING_PKTS
),
1387 EF10_DMA_STAT(port_rx_dp_hlb_fetch
, RXDP_HLB_FETCH_CONDITIONS
),
1388 EF10_DMA_STAT(port_rx_dp_hlb_wait
, RXDP_HLB_WAIT_CONDITIONS
),
1389 EF10_DMA_STAT(rx_unicast
, VADAPTER_RX_UNICAST_PACKETS
),
1390 EF10_DMA_STAT(rx_unicast_bytes
, VADAPTER_RX_UNICAST_BYTES
),
1391 EF10_DMA_STAT(rx_multicast
, VADAPTER_RX_MULTICAST_PACKETS
),
1392 EF10_DMA_STAT(rx_multicast_bytes
, VADAPTER_RX_MULTICAST_BYTES
),
1393 EF10_DMA_STAT(rx_broadcast
, VADAPTER_RX_BROADCAST_PACKETS
),
1394 EF10_DMA_STAT(rx_broadcast_bytes
, VADAPTER_RX_BROADCAST_BYTES
),
1395 EF10_DMA_STAT(rx_bad
, VADAPTER_RX_BAD_PACKETS
),
1396 EF10_DMA_STAT(rx_bad_bytes
, VADAPTER_RX_BAD_BYTES
),
1397 EF10_DMA_STAT(rx_overflow
, VADAPTER_RX_OVERFLOW
),
1398 EF10_DMA_STAT(tx_unicast
, VADAPTER_TX_UNICAST_PACKETS
),
1399 EF10_DMA_STAT(tx_unicast_bytes
, VADAPTER_TX_UNICAST_BYTES
),
1400 EF10_DMA_STAT(tx_multicast
, VADAPTER_TX_MULTICAST_PACKETS
),
1401 EF10_DMA_STAT(tx_multicast_bytes
, VADAPTER_TX_MULTICAST_BYTES
),
1402 EF10_DMA_STAT(tx_broadcast
, VADAPTER_TX_BROADCAST_PACKETS
),
1403 EF10_DMA_STAT(tx_broadcast_bytes
, VADAPTER_TX_BROADCAST_BYTES
),
1404 EF10_DMA_STAT(tx_bad
, VADAPTER_TX_BAD_PACKETS
),
1405 EF10_DMA_STAT(tx_bad_bytes
, VADAPTER_TX_BAD_BYTES
),
1406 EF10_DMA_STAT(tx_overflow
, VADAPTER_TX_OVERFLOW
),
1409 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \
1410 (1ULL << EF10_STAT_port_tx_packets) | \
1411 (1ULL << EF10_STAT_port_tx_pause) | \
1412 (1ULL << EF10_STAT_port_tx_unicast) | \
1413 (1ULL << EF10_STAT_port_tx_multicast) | \
1414 (1ULL << EF10_STAT_port_tx_broadcast) | \
1415 (1ULL << EF10_STAT_port_rx_bytes) | \
1417 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1418 (1ULL << EF10_STAT_port_rx_good_bytes) | \
1419 (1ULL << EF10_STAT_port_rx_bad_bytes) | \
1420 (1ULL << EF10_STAT_port_rx_packets) | \
1421 (1ULL << EF10_STAT_port_rx_good) | \
1422 (1ULL << EF10_STAT_port_rx_bad) | \
1423 (1ULL << EF10_STAT_port_rx_pause) | \
1424 (1ULL << EF10_STAT_port_rx_control) | \
1425 (1ULL << EF10_STAT_port_rx_unicast) | \
1426 (1ULL << EF10_STAT_port_rx_multicast) | \
1427 (1ULL << EF10_STAT_port_rx_broadcast) | \
1428 (1ULL << EF10_STAT_port_rx_lt64) | \
1429 (1ULL << EF10_STAT_port_rx_64) | \
1430 (1ULL << EF10_STAT_port_rx_65_to_127) | \
1431 (1ULL << EF10_STAT_port_rx_128_to_255) | \
1432 (1ULL << EF10_STAT_port_rx_256_to_511) | \
1433 (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1434 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1435 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1436 (1ULL << EF10_STAT_port_rx_gtjumbo) | \
1437 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1438 (1ULL << EF10_STAT_port_rx_overflow) | \
1439 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
1440 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1441 (1ULL << GENERIC_STAT_rx_noskb_drops))
1443 /* These statistics are only provided by the 10G MAC. For a 10G/40G
1444 * switchable port we do not expose these because they might not
1445 * include all the packets they should.
1447 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \
1448 (1ULL << EF10_STAT_port_tx_lt64) | \
1449 (1ULL << EF10_STAT_port_tx_64) | \
1450 (1ULL << EF10_STAT_port_tx_65_to_127) |\
1451 (1ULL << EF10_STAT_port_tx_128_to_255) |\
1452 (1ULL << EF10_STAT_port_tx_256_to_511) |\
1453 (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1454 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1455 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
1457 /* These statistics are only provided by the 40G MAC. For a 10G/40G
1458 * switchable port we do expose these because the errors will otherwise
1461 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1462 (1ULL << EF10_STAT_port_rx_length_error))
1464 /* These statistics are only provided if the firmware supports the
1465 * capability PM_AND_RXDP_COUNTERS.
1467 #define HUNT_PM_AND_RXDP_STAT_MASK ( \
1468 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \
1469 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \
1470 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \
1471 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \
1472 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \
1473 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \
1474 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \
1475 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \
1476 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \
1477 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \
1478 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \
1479 (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
1481 static u64
efx_ef10_raw_stat_mask(struct efx_nic
*efx
)
1483 u64 raw_mask
= HUNT_COMMON_STAT_MASK
;
1484 u32 port_caps
= efx_mcdi_phy_get_caps(efx
);
1485 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1487 if (!(efx
->mcdi
->fn_flags
&
1488 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL
))
1491 if (port_caps
& (1 << MC_CMD_PHY_CAP_40000FDX_LBN
))
1492 raw_mask
|= HUNT_40G_EXTRA_STAT_MASK
;
1494 raw_mask
|= HUNT_10G_ONLY_STAT_MASK
;
1496 if (nic_data
->datapath_caps
&
1497 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN
))
1498 raw_mask
|= HUNT_PM_AND_RXDP_STAT_MASK
;
1503 static void efx_ef10_get_stat_mask(struct efx_nic
*efx
, unsigned long *mask
)
1505 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1508 raw_mask
[0] = efx_ef10_raw_stat_mask(efx
);
1510 /* Only show vadaptor stats when EVB capability is present */
1511 if (nic_data
->datapath_caps
&
1512 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN
)) {
1513 raw_mask
[0] |= ~((1ULL << EF10_STAT_rx_unicast
) - 1);
1514 raw_mask
[1] = (1ULL << (EF10_STAT_COUNT
- 63)) - 1;
1519 #if BITS_PER_LONG == 64
1520 mask
[0] = raw_mask
[0];
1521 mask
[1] = raw_mask
[1];
1523 mask
[0] = raw_mask
[0] & 0xffffffff;
1524 mask
[1] = raw_mask
[0] >> 32;
1525 mask
[2] = raw_mask
[1] & 0xffffffff;
1526 mask
[3] = raw_mask
[1] >> 32;
1530 static size_t efx_ef10_describe_stats(struct efx_nic
*efx
, u8
*names
)
1532 DECLARE_BITMAP(mask
, EF10_STAT_COUNT
);
1534 efx_ef10_get_stat_mask(efx
, mask
);
1535 return efx_nic_describe_stats(efx_ef10_stat_desc
, EF10_STAT_COUNT
,
1539 static size_t efx_ef10_update_stats_common(struct efx_nic
*efx
, u64
*full_stats
,
1540 struct rtnl_link_stats64
*core_stats
)
1542 DECLARE_BITMAP(mask
, EF10_STAT_COUNT
);
1543 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1544 u64
*stats
= nic_data
->stats
;
1545 size_t stats_count
= 0, index
;
1547 efx_ef10_get_stat_mask(efx
, mask
);
1550 for_each_set_bit(index
, mask
, EF10_STAT_COUNT
) {
1551 if (efx_ef10_stat_desc
[index
].name
) {
1552 *full_stats
++ = stats
[index
];
1561 if (nic_data
->datapath_caps
&
1562 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN
) {
1563 /* Use vadaptor stats. */
1564 core_stats
->rx_packets
= stats
[EF10_STAT_rx_unicast
] +
1565 stats
[EF10_STAT_rx_multicast
] +
1566 stats
[EF10_STAT_rx_broadcast
];
1567 core_stats
->tx_packets
= stats
[EF10_STAT_tx_unicast
] +
1568 stats
[EF10_STAT_tx_multicast
] +
1569 stats
[EF10_STAT_tx_broadcast
];
1570 core_stats
->rx_bytes
= stats
[EF10_STAT_rx_unicast_bytes
] +
1571 stats
[EF10_STAT_rx_multicast_bytes
] +
1572 stats
[EF10_STAT_rx_broadcast_bytes
];
1573 core_stats
->tx_bytes
= stats
[EF10_STAT_tx_unicast_bytes
] +
1574 stats
[EF10_STAT_tx_multicast_bytes
] +
1575 stats
[EF10_STAT_tx_broadcast_bytes
];
1576 core_stats
->rx_dropped
= stats
[GENERIC_STAT_rx_nodesc_trunc
] +
1577 stats
[GENERIC_STAT_rx_noskb_drops
];
1578 core_stats
->multicast
= stats
[EF10_STAT_rx_multicast
];
1579 core_stats
->rx_crc_errors
= stats
[EF10_STAT_rx_bad
];
1580 core_stats
->rx_fifo_errors
= stats
[EF10_STAT_rx_overflow
];
1581 core_stats
->rx_errors
= core_stats
->rx_crc_errors
;
1582 core_stats
->tx_errors
= stats
[EF10_STAT_tx_bad
];
1584 /* Use port stats. */
1585 core_stats
->rx_packets
= stats
[EF10_STAT_port_rx_packets
];
1586 core_stats
->tx_packets
= stats
[EF10_STAT_port_tx_packets
];
1587 core_stats
->rx_bytes
= stats
[EF10_STAT_port_rx_bytes
];
1588 core_stats
->tx_bytes
= stats
[EF10_STAT_port_tx_bytes
];
1589 core_stats
->rx_dropped
= stats
[EF10_STAT_port_rx_nodesc_drops
] +
1590 stats
[GENERIC_STAT_rx_nodesc_trunc
] +
1591 stats
[GENERIC_STAT_rx_noskb_drops
];
1592 core_stats
->multicast
= stats
[EF10_STAT_port_rx_multicast
];
1593 core_stats
->rx_length_errors
=
1594 stats
[EF10_STAT_port_rx_gtjumbo
] +
1595 stats
[EF10_STAT_port_rx_length_error
];
1596 core_stats
->rx_crc_errors
= stats
[EF10_STAT_port_rx_bad
];
1597 core_stats
->rx_frame_errors
=
1598 stats
[EF10_STAT_port_rx_align_error
];
1599 core_stats
->rx_fifo_errors
= stats
[EF10_STAT_port_rx_overflow
];
1600 core_stats
->rx_errors
= (core_stats
->rx_length_errors
+
1601 core_stats
->rx_crc_errors
+
1602 core_stats
->rx_frame_errors
);
1608 static int efx_ef10_try_update_nic_stats_pf(struct efx_nic
*efx
)
1610 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1611 DECLARE_BITMAP(mask
, EF10_STAT_COUNT
);
1612 __le64 generation_start
, generation_end
;
1613 u64
*stats
= nic_data
->stats
;
1616 efx_ef10_get_stat_mask(efx
, mask
);
1618 dma_stats
= efx
->stats_buffer
.addr
;
1619 nic_data
= efx
->nic_data
;
1621 generation_end
= dma_stats
[MC_CMD_MAC_GENERATION_END
];
1622 if (generation_end
== EFX_MC_STATS_GENERATION_INVALID
)
1625 efx_nic_update_stats(efx_ef10_stat_desc
, EF10_STAT_COUNT
, mask
,
1626 stats
, efx
->stats_buffer
.addr
, false);
1628 generation_start
= dma_stats
[MC_CMD_MAC_GENERATION_START
];
1629 if (generation_end
!= generation_start
)
1632 /* Update derived statistics */
1633 efx_nic_fix_nodesc_drop_stat(efx
,
1634 &stats
[EF10_STAT_port_rx_nodesc_drops
]);
1635 stats
[EF10_STAT_port_rx_good_bytes
] =
1636 stats
[EF10_STAT_port_rx_bytes
] -
1637 stats
[EF10_STAT_port_rx_bytes_minus_good_bytes
];
1638 efx_update_diff_stat(&stats
[EF10_STAT_port_rx_bad_bytes
],
1639 stats
[EF10_STAT_port_rx_bytes_minus_good_bytes
]);
1640 efx_update_sw_stats(efx
, stats
);
1645 static size_t efx_ef10_update_stats_pf(struct efx_nic
*efx
, u64
*full_stats
,
1646 struct rtnl_link_stats64
*core_stats
)
1650 /* If we're unlucky enough to read statistics during the DMA, wait
1651 * up to 10ms for it to finish (typically takes <500us)
1653 for (retry
= 0; retry
< 100; ++retry
) {
1654 if (efx_ef10_try_update_nic_stats_pf(efx
) == 0)
1659 return efx_ef10_update_stats_common(efx
, full_stats
, core_stats
);
1662 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic
*efx
)
1664 MCDI_DECLARE_BUF(inbuf
, MC_CMD_MAC_STATS_IN_LEN
);
1665 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1666 DECLARE_BITMAP(mask
, EF10_STAT_COUNT
);
1667 __le64 generation_start
, generation_end
;
1668 u64
*stats
= nic_data
->stats
;
1669 u32 dma_len
= MC_CMD_MAC_NSTATS
* sizeof(u64
);
1670 struct efx_buffer stats_buf
;
1674 spin_unlock_bh(&efx
->stats_lock
);
1676 if (in_interrupt()) {
1677 /* If in atomic context, cannot update stats. Just update the
1678 * software stats and return so the caller can continue.
1680 spin_lock_bh(&efx
->stats_lock
);
1681 efx_update_sw_stats(efx
, stats
);
1685 efx_ef10_get_stat_mask(efx
, mask
);
1687 rc
= efx_nic_alloc_buffer(efx
, &stats_buf
, dma_len
, GFP_ATOMIC
);
1689 spin_lock_bh(&efx
->stats_lock
);
1693 dma_stats
= stats_buf
.addr
;
1694 dma_stats
[MC_CMD_MAC_GENERATION_END
] = EFX_MC_STATS_GENERATION_INVALID
;
1696 MCDI_SET_QWORD(inbuf
, MAC_STATS_IN_DMA_ADDR
, stats_buf
.dma_addr
);
1697 MCDI_POPULATE_DWORD_1(inbuf
, MAC_STATS_IN_CMD
,
1698 MAC_STATS_IN_DMA
, 1);
1699 MCDI_SET_DWORD(inbuf
, MAC_STATS_IN_DMA_LEN
, dma_len
);
1700 MCDI_SET_DWORD(inbuf
, MAC_STATS_IN_PORT_ID
, EVB_PORT_ID_ASSIGNED
);
1702 rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_MAC_STATS
, inbuf
, sizeof(inbuf
),
1704 spin_lock_bh(&efx
->stats_lock
);
1706 /* Expect ENOENT if DMA queues have not been set up */
1707 if (rc
!= -ENOENT
|| atomic_read(&efx
->active_queues
))
1708 efx_mcdi_display_error(efx
, MC_CMD_MAC_STATS
,
1709 sizeof(inbuf
), NULL
, 0, rc
);
1713 generation_end
= dma_stats
[MC_CMD_MAC_GENERATION_END
];
1714 if (generation_end
== EFX_MC_STATS_GENERATION_INVALID
) {
1719 efx_nic_update_stats(efx_ef10_stat_desc
, EF10_STAT_COUNT
, mask
,
1720 stats
, stats_buf
.addr
, false);
1722 generation_start
= dma_stats
[MC_CMD_MAC_GENERATION_START
];
1723 if (generation_end
!= generation_start
) {
1728 efx_update_sw_stats(efx
, stats
);
1730 efx_nic_free_buffer(efx
, &stats_buf
);
1734 static size_t efx_ef10_update_stats_vf(struct efx_nic
*efx
, u64
*full_stats
,
1735 struct rtnl_link_stats64
*core_stats
)
1737 if (efx_ef10_try_update_nic_stats_vf(efx
))
1740 return efx_ef10_update_stats_common(efx
, full_stats
, core_stats
);
1743 static void efx_ef10_push_irq_moderation(struct efx_channel
*channel
)
1745 struct efx_nic
*efx
= channel
->efx
;
1746 unsigned int mode
, value
;
1747 efx_dword_t timer_cmd
;
1749 if (channel
->irq_moderation
) {
1751 value
= channel
->irq_moderation
- 1;
1757 if (EFX_EF10_WORKAROUND_35388(efx
)) {
1758 EFX_POPULATE_DWORD_3(timer_cmd
, ERF_DD_EVQ_IND_TIMER_FLAGS
,
1759 EFE_DD_EVQ_IND_TIMER_FLAGS
,
1760 ERF_DD_EVQ_IND_TIMER_MODE
, mode
,
1761 ERF_DD_EVQ_IND_TIMER_VAL
, value
);
1762 efx_writed_page(efx
, &timer_cmd
, ER_DD_EVQ_INDIRECT
,
1765 EFX_POPULATE_DWORD_2(timer_cmd
, ERF_DZ_TC_TIMER_MODE
, mode
,
1766 ERF_DZ_TC_TIMER_VAL
, value
);
1767 efx_writed_page(efx
, &timer_cmd
, ER_DZ_EVQ_TMR
,
1772 static void efx_ef10_get_wol_vf(struct efx_nic
*efx
,
1773 struct ethtool_wolinfo
*wol
) {}
1775 static int efx_ef10_set_wol_vf(struct efx_nic
*efx
, u32 type
)
1780 static void efx_ef10_get_wol(struct efx_nic
*efx
, struct ethtool_wolinfo
*wol
)
1784 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
1787 static int efx_ef10_set_wol(struct efx_nic
*efx
, u32 type
)
1794 static void efx_ef10_mcdi_request(struct efx_nic
*efx
,
1795 const efx_dword_t
*hdr
, size_t hdr_len
,
1796 const efx_dword_t
*sdu
, size_t sdu_len
)
1798 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1799 u8
*pdu
= nic_data
->mcdi_buf
.addr
;
1801 memcpy(pdu
, hdr
, hdr_len
);
1802 memcpy(pdu
+ hdr_len
, sdu
, sdu_len
);
1805 /* The hardware provides 'low' and 'high' (doorbell) registers
1806 * for passing the 64-bit address of an MCDI request to
1807 * firmware. However the dwords are swapped by firmware. The
1808 * least significant bits of the doorbell are then 0 for all
1809 * MCDI requests due to alignment.
1811 _efx_writed(efx
, cpu_to_le32((u64
)nic_data
->mcdi_buf
.dma_addr
>> 32),
1813 _efx_writed(efx
, cpu_to_le32((u32
)nic_data
->mcdi_buf
.dma_addr
),
1817 static bool efx_ef10_mcdi_poll_response(struct efx_nic
*efx
)
1819 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1820 const efx_dword_t hdr
= *(const efx_dword_t
*)nic_data
->mcdi_buf
.addr
;
1823 return EFX_DWORD_FIELD(hdr
, MCDI_HEADER_RESPONSE
);
1827 efx_ef10_mcdi_read_response(struct efx_nic
*efx
, efx_dword_t
*outbuf
,
1828 size_t offset
, size_t outlen
)
1830 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1831 const u8
*pdu
= nic_data
->mcdi_buf
.addr
;
1833 memcpy(outbuf
, pdu
+ offset
, outlen
);
1836 static void efx_ef10_mcdi_reboot_detected(struct efx_nic
*efx
)
1838 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1840 /* All our allocations have been reset */
1841 efx_ef10_reset_mc_allocations(efx
);
1843 /* The datapath firmware might have been changed */
1844 nic_data
->must_check_datapath_caps
= true;
1846 /* MAC statistics have been cleared on the NIC; clear the local
1847 * statistic that we update with efx_update_diff_stat().
1849 nic_data
->stats
[EF10_STAT_port_rx_bad_bytes
] = 0;
1852 static int efx_ef10_mcdi_poll_reboot(struct efx_nic
*efx
)
1854 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1857 rc
= efx_ef10_get_warm_boot_count(efx
);
1859 /* The firmware is presumably in the process of
1860 * rebooting. However, we are supposed to report each
1861 * reboot just once, so we must only do that once we
1862 * can read and store the updated warm boot count.
1867 if (rc
== nic_data
->warm_boot_count
)
1870 nic_data
->warm_boot_count
= rc
;
1871 efx_ef10_mcdi_reboot_detected(efx
);
1876 /* Handle an MSI interrupt
1878 * Handle an MSI hardware interrupt. This routine schedules event
1879 * queue processing. No interrupt acknowledgement cycle is necessary.
1880 * Also, we never need to check that the interrupt is for us, since
1881 * MSI interrupts cannot be shared.
1883 static irqreturn_t
efx_ef10_msi_interrupt(int irq
, void *dev_id
)
1885 struct efx_msi_context
*context
= dev_id
;
1886 struct efx_nic
*efx
= context
->efx
;
1888 netif_vdbg(efx
, intr
, efx
->net_dev
,
1889 "IRQ %d on CPU %d\n", irq
, raw_smp_processor_id());
1891 if (likely(ACCESS_ONCE(efx
->irq_soft_enabled
))) {
1892 /* Note test interrupts */
1893 if (context
->index
== efx
->irq_level
)
1894 efx
->last_irq_cpu
= raw_smp_processor_id();
1896 /* Schedule processing of the channel */
1897 efx_schedule_channel_irq(efx
->channel
[context
->index
]);
1903 static irqreturn_t
efx_ef10_legacy_interrupt(int irq
, void *dev_id
)
1905 struct efx_nic
*efx
= dev_id
;
1906 bool soft_enabled
= ACCESS_ONCE(efx
->irq_soft_enabled
);
1907 struct efx_channel
*channel
;
1911 /* Read the ISR which also ACKs the interrupts */
1912 efx_readd(efx
, ®
, ER_DZ_BIU_INT_ISR
);
1913 queues
= EFX_DWORD_FIELD(reg
, ERF_DZ_ISR_REG
);
1918 if (likely(soft_enabled
)) {
1919 /* Note test interrupts */
1920 if (queues
& (1U << efx
->irq_level
))
1921 efx
->last_irq_cpu
= raw_smp_processor_id();
1923 efx_for_each_channel(channel
, efx
) {
1925 efx_schedule_channel_irq(channel
);
1930 netif_vdbg(efx
, intr
, efx
->net_dev
,
1931 "IRQ %d on CPU %d status " EFX_DWORD_FMT
"\n",
1932 irq
, raw_smp_processor_id(), EFX_DWORD_VAL(reg
));
1937 static void efx_ef10_irq_test_generate(struct efx_nic
*efx
)
1939 MCDI_DECLARE_BUF(inbuf
, MC_CMD_TRIGGER_INTERRUPT_IN_LEN
);
1941 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN
!= 0);
1943 MCDI_SET_DWORD(inbuf
, TRIGGER_INTERRUPT_IN_INTR_LEVEL
, efx
->irq_level
);
1944 (void) efx_mcdi_rpc(efx
, MC_CMD_TRIGGER_INTERRUPT
,
1945 inbuf
, sizeof(inbuf
), NULL
, 0, NULL
);
1948 static int efx_ef10_tx_probe(struct efx_tx_queue
*tx_queue
)
1950 return efx_nic_alloc_buffer(tx_queue
->efx
, &tx_queue
->txd
.buf
,
1951 (tx_queue
->ptr_mask
+ 1) *
1952 sizeof(efx_qword_t
),
1956 /* This writes to the TX_DESC_WPTR and also pushes data */
1957 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue
*tx_queue
,
1958 const efx_qword_t
*txd
)
1960 unsigned int write_ptr
;
1963 write_ptr
= tx_queue
->write_count
& tx_queue
->ptr_mask
;
1964 EFX_POPULATE_OWORD_1(reg
, ERF_DZ_TX_DESC_WPTR
, write_ptr
);
1965 reg
.qword
[0] = *txd
;
1966 efx_writeo_page(tx_queue
->efx
, ®
,
1967 ER_DZ_TX_DESC_UPD
, tx_queue
->queue
);
1970 static void efx_ef10_tx_init(struct efx_tx_queue
*tx_queue
)
1972 MCDI_DECLARE_BUF(inbuf
, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE
* 8 /
1974 bool csum_offload
= tx_queue
->queue
& EFX_TXQ_TYPE_OFFLOAD
;
1975 size_t entries
= tx_queue
->txd
.buf
.len
/ EFX_BUF_SIZE
;
1976 struct efx_channel
*channel
= tx_queue
->channel
;
1977 struct efx_nic
*efx
= tx_queue
->efx
;
1978 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1980 dma_addr_t dma_addr
;
1984 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN
!= 0);
1986 MCDI_SET_DWORD(inbuf
, INIT_TXQ_IN_SIZE
, tx_queue
->ptr_mask
+ 1);
1987 MCDI_SET_DWORD(inbuf
, INIT_TXQ_IN_TARGET_EVQ
, channel
->channel
);
1988 MCDI_SET_DWORD(inbuf
, INIT_TXQ_IN_LABEL
, tx_queue
->queue
);
1989 MCDI_SET_DWORD(inbuf
, INIT_TXQ_IN_INSTANCE
, tx_queue
->queue
);
1990 MCDI_POPULATE_DWORD_2(inbuf
, INIT_TXQ_IN_FLAGS
,
1991 INIT_TXQ_IN_FLAG_IP_CSUM_DIS
, !csum_offload
,
1992 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS
, !csum_offload
);
1993 MCDI_SET_DWORD(inbuf
, INIT_TXQ_IN_OWNER_ID
, 0);
1994 MCDI_SET_DWORD(inbuf
, INIT_TXQ_IN_PORT_ID
, nic_data
->vport_id
);
1996 dma_addr
= tx_queue
->txd
.buf
.dma_addr
;
1998 netif_dbg(efx
, hw
, efx
->net_dev
, "pushing TXQ %d. %zu entries (%llx)\n",
1999 tx_queue
->queue
, entries
, (u64
)dma_addr
);
2001 for (i
= 0; i
< entries
; ++i
) {
2002 MCDI_SET_ARRAY_QWORD(inbuf
, INIT_TXQ_IN_DMA_ADDR
, i
, dma_addr
);
2003 dma_addr
+= EFX_BUF_SIZE
;
2006 inlen
= MC_CMD_INIT_TXQ_IN_LEN(entries
);
2008 rc
= efx_mcdi_rpc(efx
, MC_CMD_INIT_TXQ
, inbuf
, inlen
,
2013 /* A previous user of this TX queue might have set us up the
2014 * bomb by writing a descriptor to the TX push collector but
2015 * not the doorbell. (Each collector belongs to a port, not a
2016 * queue or function, so cannot easily be reset.) We must
2017 * attempt to push a no-op descriptor in its place.
2019 tx_queue
->buffer
[0].flags
= EFX_TX_BUF_OPTION
;
2020 tx_queue
->insert_count
= 1;
2021 txd
= efx_tx_desc(tx_queue
, 0);
2022 EFX_POPULATE_QWORD_4(*txd
,
2023 ESF_DZ_TX_DESC_IS_OPT
, true,
2024 ESF_DZ_TX_OPTION_TYPE
,
2025 ESE_DZ_TX_OPTION_DESC_CRC_CSUM
,
2026 ESF_DZ_TX_OPTION_UDP_TCP_CSUM
, csum_offload
,
2027 ESF_DZ_TX_OPTION_IP_CSUM
, csum_offload
);
2028 tx_queue
->write_count
= 1;
2030 if (nic_data
->datapath_caps
&
2031 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN
)) {
2032 tx_queue
->tso_version
= 1;
2036 efx_ef10_push_tx_desc(tx_queue
, txd
);
2041 netdev_WARN(efx
->net_dev
, "failed to initialise TXQ %d\n",
2045 static void efx_ef10_tx_fini(struct efx_tx_queue
*tx_queue
)
2047 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FINI_TXQ_IN_LEN
);
2048 MCDI_DECLARE_BUF_ERR(outbuf
);
2049 struct efx_nic
*efx
= tx_queue
->efx
;
2053 MCDI_SET_DWORD(inbuf
, FINI_TXQ_IN_INSTANCE
,
2056 rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_FINI_TXQ
, inbuf
, sizeof(inbuf
),
2057 outbuf
, sizeof(outbuf
), &outlen
);
2059 if (rc
&& rc
!= -EALREADY
)
2065 efx_mcdi_display_error(efx
, MC_CMD_FINI_TXQ
, MC_CMD_FINI_TXQ_IN_LEN
,
2066 outbuf
, outlen
, rc
);
2069 static void efx_ef10_tx_remove(struct efx_tx_queue
*tx_queue
)
2071 efx_nic_free_buffer(tx_queue
->efx
, &tx_queue
->txd
.buf
);
2074 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
2075 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue
*tx_queue
)
2077 unsigned int write_ptr
;
2080 write_ptr
= tx_queue
->write_count
& tx_queue
->ptr_mask
;
2081 EFX_POPULATE_DWORD_1(reg
, ERF_DZ_TX_DESC_WPTR_DWORD
, write_ptr
);
2082 efx_writed_page(tx_queue
->efx
, ®
,
2083 ER_DZ_TX_DESC_UPD_DWORD
, tx_queue
->queue
);
2086 static void efx_ef10_tx_write(struct efx_tx_queue
*tx_queue
)
2088 unsigned int old_write_count
= tx_queue
->write_count
;
2089 struct efx_tx_buffer
*buffer
;
2090 unsigned int write_ptr
;
2093 tx_queue
->xmit_more_available
= false;
2094 if (unlikely(tx_queue
->write_count
== tx_queue
->insert_count
))
2098 write_ptr
= tx_queue
->write_count
& tx_queue
->ptr_mask
;
2099 buffer
= &tx_queue
->buffer
[write_ptr
];
2100 txd
= efx_tx_desc(tx_queue
, write_ptr
);
2101 ++tx_queue
->write_count
;
2103 /* Create TX descriptor ring entry */
2104 if (buffer
->flags
& EFX_TX_BUF_OPTION
) {
2105 *txd
= buffer
->option
;
2107 BUILD_BUG_ON(EFX_TX_BUF_CONT
!= 1);
2108 EFX_POPULATE_QWORD_3(
2111 buffer
->flags
& EFX_TX_BUF_CONT
,
2112 ESF_DZ_TX_KER_BYTE_CNT
, buffer
->len
,
2113 ESF_DZ_TX_KER_BUF_ADDR
, buffer
->dma_addr
);
2115 } while (tx_queue
->write_count
!= tx_queue
->insert_count
);
2117 wmb(); /* Ensure descriptors are written before they are fetched */
2119 if (efx_nic_may_push_tx_desc(tx_queue
, old_write_count
)) {
2120 txd
= efx_tx_desc(tx_queue
,
2121 old_write_count
& tx_queue
->ptr_mask
);
2122 efx_ef10_push_tx_desc(tx_queue
, txd
);
2125 efx_ef10_notify_tx_desc(tx_queue
);
2129 static int efx_ef10_alloc_rss_context(struct efx_nic
*efx
, u32
*context
,
2130 bool exclusive
, unsigned *context_size
)
2132 MCDI_DECLARE_BUF(inbuf
, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN
);
2133 MCDI_DECLARE_BUF(outbuf
, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN
);
2134 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
2137 u32 alloc_type
= exclusive
?
2138 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE
:
2139 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED
;
2140 unsigned rss_spread
= exclusive
?
2142 min(rounddown_pow_of_two(efx
->rss_spread
),
2143 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE
);
2145 if (!exclusive
&& rss_spread
== 1) {
2146 *context
= EFX_EF10_RSS_CONTEXT_INVALID
;
2152 if (nic_data
->datapath_caps
&
2153 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN
)
2156 MCDI_SET_DWORD(inbuf
, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID
,
2157 nic_data
->vport_id
);
2158 MCDI_SET_DWORD(inbuf
, RSS_CONTEXT_ALLOC_IN_TYPE
, alloc_type
);
2159 MCDI_SET_DWORD(inbuf
, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES
, rss_spread
);
2161 rc
= efx_mcdi_rpc(efx
, MC_CMD_RSS_CONTEXT_ALLOC
, inbuf
, sizeof(inbuf
),
2162 outbuf
, sizeof(outbuf
), &outlen
);
2166 if (outlen
< MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN
)
2169 *context
= MCDI_DWORD(outbuf
, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID
);
2172 *context_size
= rss_spread
;
2177 static void efx_ef10_free_rss_context(struct efx_nic
*efx
, u32 context
)
2179 MCDI_DECLARE_BUF(inbuf
, MC_CMD_RSS_CONTEXT_FREE_IN_LEN
);
2182 MCDI_SET_DWORD(inbuf
, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID
,
2185 rc
= efx_mcdi_rpc(efx
, MC_CMD_RSS_CONTEXT_FREE
, inbuf
, sizeof(inbuf
),
2190 static int efx_ef10_populate_rss_table(struct efx_nic
*efx
, u32 context
,
2191 const u32
*rx_indir_table
)
2193 MCDI_DECLARE_BUF(tablebuf
, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN
);
2194 MCDI_DECLARE_BUF(keybuf
, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN
);
2197 MCDI_SET_DWORD(tablebuf
, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID
,
2199 BUILD_BUG_ON(ARRAY_SIZE(efx
->rx_indir_table
) !=
2200 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN
);
2202 for (i
= 0; i
< ARRAY_SIZE(efx
->rx_indir_table
); ++i
)
2204 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE
)[i
] =
2205 (u8
) rx_indir_table
[i
];
2207 rc
= efx_mcdi_rpc(efx
, MC_CMD_RSS_CONTEXT_SET_TABLE
, tablebuf
,
2208 sizeof(tablebuf
), NULL
, 0, NULL
);
2212 MCDI_SET_DWORD(keybuf
, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID
,
2214 BUILD_BUG_ON(ARRAY_SIZE(efx
->rx_hash_key
) !=
2215 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN
);
2216 for (i
= 0; i
< ARRAY_SIZE(efx
->rx_hash_key
); ++i
)
2217 MCDI_PTR(keybuf
, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY
)[i
] =
2218 efx
->rx_hash_key
[i
];
2220 return efx_mcdi_rpc(efx
, MC_CMD_RSS_CONTEXT_SET_KEY
, keybuf
,
2221 sizeof(keybuf
), NULL
, 0, NULL
);
2224 static void efx_ef10_rx_free_indir_table(struct efx_nic
*efx
)
2226 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
2228 if (nic_data
->rx_rss_context
!= EFX_EF10_RSS_CONTEXT_INVALID
)
2229 efx_ef10_free_rss_context(efx
, nic_data
->rx_rss_context
);
2230 nic_data
->rx_rss_context
= EFX_EF10_RSS_CONTEXT_INVALID
;
2233 static int efx_ef10_rx_push_shared_rss_config(struct efx_nic
*efx
,
2234 unsigned *context_size
)
2236 u32 new_rx_rss_context
;
2237 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
2238 int rc
= efx_ef10_alloc_rss_context(efx
, &new_rx_rss_context
,
2239 false, context_size
);
2244 nic_data
->rx_rss_context
= new_rx_rss_context
;
2245 nic_data
->rx_rss_context_exclusive
= false;
2246 efx_set_default_rx_indir_table(efx
);
2250 static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic
*efx
,
2251 const u32
*rx_indir_table
)
2253 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
2255 u32 new_rx_rss_context
;
2257 if (nic_data
->rx_rss_context
== EFX_EF10_RSS_CONTEXT_INVALID
||
2258 !nic_data
->rx_rss_context_exclusive
) {
2259 rc
= efx_ef10_alloc_rss_context(efx
, &new_rx_rss_context
,
2261 if (rc
== -EOPNOTSUPP
)
2266 new_rx_rss_context
= nic_data
->rx_rss_context
;
2269 rc
= efx_ef10_populate_rss_table(efx
, new_rx_rss_context
,
2274 if (nic_data
->rx_rss_context
!= new_rx_rss_context
)
2275 efx_ef10_rx_free_indir_table(efx
);
2276 nic_data
->rx_rss_context
= new_rx_rss_context
;
2277 nic_data
->rx_rss_context_exclusive
= true;
2278 if (rx_indir_table
!= efx
->rx_indir_table
)
2279 memcpy(efx
->rx_indir_table
, rx_indir_table
,
2280 sizeof(efx
->rx_indir_table
));
2284 if (new_rx_rss_context
!= nic_data
->rx_rss_context
)
2285 efx_ef10_free_rss_context(efx
, new_rx_rss_context
);
2287 netif_err(efx
, hw
, efx
->net_dev
, "%s: failed rc=%d\n", __func__
, rc
);
2291 static int efx_ef10_pf_rx_push_rss_config(struct efx_nic
*efx
, bool user
,
2292 const u32
*rx_indir_table
)
2296 if (efx
->rss_spread
== 1)
2299 rc
= efx_ef10_rx_push_exclusive_rss_config(efx
, rx_indir_table
);
2301 if (rc
== -ENOBUFS
&& !user
) {
2302 unsigned context_size
;
2303 bool mismatch
= false;
2306 for (i
= 0; i
< ARRAY_SIZE(efx
->rx_indir_table
) && !mismatch
;
2308 mismatch
= rx_indir_table
[i
] !=
2309 ethtool_rxfh_indir_default(i
, efx
->rss_spread
);
2311 rc
= efx_ef10_rx_push_shared_rss_config(efx
, &context_size
);
2313 if (context_size
!= efx
->rss_spread
)
2314 netif_warn(efx
, probe
, efx
->net_dev
,
2315 "Could not allocate an exclusive RSS"
2316 " context; allocated a shared one of"
2318 " Wanted %u, got %u.\n",
2319 efx
->rss_spread
, context_size
);
2321 netif_warn(efx
, probe
, efx
->net_dev
,
2322 "Could not allocate an exclusive RSS"
2323 " context; allocated a shared one but"
2324 " could not apply custom"
2327 netif_info(efx
, probe
, efx
->net_dev
,
2328 "Could not allocate an exclusive RSS"
2329 " context; allocated a shared one.\n");
2335 static int efx_ef10_vf_rx_push_rss_config(struct efx_nic
*efx
, bool user
,
2336 const u32
*rx_indir_table
2337 __attribute__ ((unused
)))
2339 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
2343 if (nic_data
->rx_rss_context
!= EFX_EF10_RSS_CONTEXT_INVALID
)
2345 return efx_ef10_rx_push_shared_rss_config(efx
, NULL
);
2348 static int efx_ef10_rx_probe(struct efx_rx_queue
*rx_queue
)
2350 return efx_nic_alloc_buffer(rx_queue
->efx
, &rx_queue
->rxd
.buf
,
2351 (rx_queue
->ptr_mask
+ 1) *
2352 sizeof(efx_qword_t
),
2356 static void efx_ef10_rx_init(struct efx_rx_queue
*rx_queue
)
2358 MCDI_DECLARE_BUF(inbuf
,
2359 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE
* 8 /
2361 struct efx_channel
*channel
= efx_rx_queue_channel(rx_queue
);
2362 size_t entries
= rx_queue
->rxd
.buf
.len
/ EFX_BUF_SIZE
;
2363 struct efx_nic
*efx
= rx_queue
->efx
;
2364 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
2366 dma_addr_t dma_addr
;
2369 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN
!= 0);
2371 rx_queue
->scatter_n
= 0;
2372 rx_queue
->scatter_len
= 0;
2374 MCDI_SET_DWORD(inbuf
, INIT_RXQ_IN_SIZE
, rx_queue
->ptr_mask
+ 1);
2375 MCDI_SET_DWORD(inbuf
, INIT_RXQ_IN_TARGET_EVQ
, channel
->channel
);
2376 MCDI_SET_DWORD(inbuf
, INIT_RXQ_IN_LABEL
, efx_rx_queue_index(rx_queue
));
2377 MCDI_SET_DWORD(inbuf
, INIT_RXQ_IN_INSTANCE
,
2378 efx_rx_queue_index(rx_queue
));
2379 MCDI_POPULATE_DWORD_2(inbuf
, INIT_RXQ_IN_FLAGS
,
2380 INIT_RXQ_IN_FLAG_PREFIX
, 1,
2381 INIT_RXQ_IN_FLAG_TIMESTAMP
, 1);
2382 MCDI_SET_DWORD(inbuf
, INIT_RXQ_IN_OWNER_ID
, 0);
2383 MCDI_SET_DWORD(inbuf
, INIT_RXQ_IN_PORT_ID
, nic_data
->vport_id
);
2385 dma_addr
= rx_queue
->rxd
.buf
.dma_addr
;
2387 netif_dbg(efx
, hw
, efx
->net_dev
, "pushing RXQ %d. %zu entries (%llx)\n",
2388 efx_rx_queue_index(rx_queue
), entries
, (u64
)dma_addr
);
2390 for (i
= 0; i
< entries
; ++i
) {
2391 MCDI_SET_ARRAY_QWORD(inbuf
, INIT_RXQ_IN_DMA_ADDR
, i
, dma_addr
);
2392 dma_addr
+= EFX_BUF_SIZE
;
2395 inlen
= MC_CMD_INIT_RXQ_IN_LEN(entries
);
2397 rc
= efx_mcdi_rpc(efx
, MC_CMD_INIT_RXQ
, inbuf
, inlen
,
2400 netdev_WARN(efx
->net_dev
, "failed to initialise RXQ %d\n",
2401 efx_rx_queue_index(rx_queue
));
2404 static void efx_ef10_rx_fini(struct efx_rx_queue
*rx_queue
)
2406 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FINI_RXQ_IN_LEN
);
2407 MCDI_DECLARE_BUF_ERR(outbuf
);
2408 struct efx_nic
*efx
= rx_queue
->efx
;
2412 MCDI_SET_DWORD(inbuf
, FINI_RXQ_IN_INSTANCE
,
2413 efx_rx_queue_index(rx_queue
));
2415 rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_FINI_RXQ
, inbuf
, sizeof(inbuf
),
2416 outbuf
, sizeof(outbuf
), &outlen
);
2418 if (rc
&& rc
!= -EALREADY
)
2424 efx_mcdi_display_error(efx
, MC_CMD_FINI_RXQ
, MC_CMD_FINI_RXQ_IN_LEN
,
2425 outbuf
, outlen
, rc
);
2428 static void efx_ef10_rx_remove(struct efx_rx_queue
*rx_queue
)
2430 efx_nic_free_buffer(rx_queue
->efx
, &rx_queue
->rxd
.buf
);
2433 /* This creates an entry in the RX descriptor queue */
2435 efx_ef10_build_rx_desc(struct efx_rx_queue
*rx_queue
, unsigned int index
)
2437 struct efx_rx_buffer
*rx_buf
;
2440 rxd
= efx_rx_desc(rx_queue
, index
);
2441 rx_buf
= efx_rx_buffer(rx_queue
, index
);
2442 EFX_POPULATE_QWORD_2(*rxd
,
2443 ESF_DZ_RX_KER_BYTE_CNT
, rx_buf
->len
,
2444 ESF_DZ_RX_KER_BUF_ADDR
, rx_buf
->dma_addr
);
2447 static void efx_ef10_rx_write(struct efx_rx_queue
*rx_queue
)
2449 struct efx_nic
*efx
= rx_queue
->efx
;
2450 unsigned int write_count
;
2453 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2454 write_count
= rx_queue
->added_count
& ~7;
2455 if (rx_queue
->notified_count
== write_count
)
2459 efx_ef10_build_rx_desc(
2461 rx_queue
->notified_count
& rx_queue
->ptr_mask
);
2462 while (++rx_queue
->notified_count
!= write_count
);
2465 EFX_POPULATE_DWORD_1(reg
, ERF_DZ_RX_DESC_WPTR
,
2466 write_count
& rx_queue
->ptr_mask
);
2467 efx_writed_page(efx
, ®
, ER_DZ_RX_DESC_UPD
,
2468 efx_rx_queue_index(rx_queue
));
2471 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete
;
2473 static void efx_ef10_rx_defer_refill(struct efx_rx_queue
*rx_queue
)
2475 struct efx_channel
*channel
= efx_rx_queue_channel(rx_queue
);
2476 MCDI_DECLARE_BUF(inbuf
, MC_CMD_DRIVER_EVENT_IN_LEN
);
2479 EFX_POPULATE_QWORD_2(event
,
2480 ESF_DZ_EV_CODE
, EFX_EF10_DRVGEN_EV
,
2481 ESF_DZ_EV_DATA
, EFX_EF10_REFILL
);
2483 MCDI_SET_DWORD(inbuf
, DRIVER_EVENT_IN_EVQ
, channel
->channel
);
2485 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2486 * already swapped the data to little-endian order.
2488 memcpy(MCDI_PTR(inbuf
, DRIVER_EVENT_IN_DATA
), &event
.u64
[0],
2489 sizeof(efx_qword_t
));
2491 efx_mcdi_rpc_async(channel
->efx
, MC_CMD_DRIVER_EVENT
,
2492 inbuf
, sizeof(inbuf
), 0,
2493 efx_ef10_rx_defer_refill_complete
, 0);
2497 efx_ef10_rx_defer_refill_complete(struct efx_nic
*efx
, unsigned long cookie
,
2498 int rc
, efx_dword_t
*outbuf
,
2499 size_t outlen_actual
)
2504 static int efx_ef10_ev_probe(struct efx_channel
*channel
)
2506 return efx_nic_alloc_buffer(channel
->efx
, &channel
->eventq
.buf
,
2507 (channel
->eventq_mask
+ 1) *
2508 sizeof(efx_qword_t
),
2512 static void efx_ef10_ev_fini(struct efx_channel
*channel
)
2514 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FINI_EVQ_IN_LEN
);
2515 MCDI_DECLARE_BUF_ERR(outbuf
);
2516 struct efx_nic
*efx
= channel
->efx
;
2520 MCDI_SET_DWORD(inbuf
, FINI_EVQ_IN_INSTANCE
, channel
->channel
);
2522 rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_FINI_EVQ
, inbuf
, sizeof(inbuf
),
2523 outbuf
, sizeof(outbuf
), &outlen
);
2525 if (rc
&& rc
!= -EALREADY
)
2531 efx_mcdi_display_error(efx
, MC_CMD_FINI_EVQ
, MC_CMD_FINI_EVQ_IN_LEN
,
2532 outbuf
, outlen
, rc
);
2535 static int efx_ef10_ev_init(struct efx_channel
*channel
)
2537 MCDI_DECLARE_BUF(inbuf
,
2538 MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE
* 8 /
2540 MCDI_DECLARE_BUF(outbuf
, MC_CMD_INIT_EVQ_OUT_LEN
);
2541 size_t entries
= channel
->eventq
.buf
.len
/ EFX_BUF_SIZE
;
2542 struct efx_nic
*efx
= channel
->efx
;
2543 struct efx_ef10_nic_data
*nic_data
;
2544 bool supports_rx_merge
;
2545 size_t inlen
, outlen
;
2546 unsigned int enabled
, implemented
;
2547 dma_addr_t dma_addr
;
2551 nic_data
= efx
->nic_data
;
2553 !!(nic_data
->datapath_caps
&
2554 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN
);
2556 /* Fill event queue with all ones (i.e. empty events) */
2557 memset(channel
->eventq
.buf
.addr
, 0xff, channel
->eventq
.buf
.len
);
2559 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_SIZE
, channel
->eventq_mask
+ 1);
2560 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_INSTANCE
, channel
->channel
);
2561 /* INIT_EVQ expects index in vector table, not absolute */
2562 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_IRQ_NUM
, channel
->channel
);
2563 MCDI_POPULATE_DWORD_4(inbuf
, INIT_EVQ_IN_FLAGS
,
2564 INIT_EVQ_IN_FLAG_INTERRUPTING
, 1,
2565 INIT_EVQ_IN_FLAG_RX_MERGE
, 1,
2566 INIT_EVQ_IN_FLAG_TX_MERGE
, 1,
2567 INIT_EVQ_IN_FLAG_CUT_THRU
, !supports_rx_merge
);
2568 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_TMR_MODE
,
2569 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS
);
2570 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_TMR_LOAD
, 0);
2571 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_TMR_RELOAD
, 0);
2572 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_COUNT_MODE
,
2573 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS
);
2574 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_COUNT_THRSHLD
, 0);
2576 dma_addr
= channel
->eventq
.buf
.dma_addr
;
2577 for (i
= 0; i
< entries
; ++i
) {
2578 MCDI_SET_ARRAY_QWORD(inbuf
, INIT_EVQ_IN_DMA_ADDR
, i
, dma_addr
);
2579 dma_addr
+= EFX_BUF_SIZE
;
2582 inlen
= MC_CMD_INIT_EVQ_IN_LEN(entries
);
2584 rc
= efx_mcdi_rpc(efx
, MC_CMD_INIT_EVQ
, inbuf
, inlen
,
2585 outbuf
, sizeof(outbuf
), &outlen
);
2586 /* IRQ return is ignored */
2587 if (channel
->channel
|| rc
)
2590 /* Successfully created event queue on channel 0 */
2591 rc
= efx_mcdi_get_workarounds(efx
, &implemented
, &enabled
);
2592 if (rc
== -ENOSYS
) {
2593 /* GET_WORKAROUNDS was implemented before the bug26807
2594 * workaround, thus the latter must be unavailable in this fw
2596 nic_data
->workaround_26807
= false;
2601 nic_data
->workaround_26807
=
2602 !!(enabled
& MC_CMD_GET_WORKAROUNDS_OUT_BUG26807
);
2604 if (implemented
& MC_CMD_GET_WORKAROUNDS_OUT_BUG26807
&&
2605 !nic_data
->workaround_26807
) {
2608 rc
= efx_mcdi_set_workaround(efx
,
2609 MC_CMD_WORKAROUND_BUG26807
,
2614 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN
) {
2615 netif_info(efx
, drv
, efx
->net_dev
,
2616 "other functions on NIC have been reset\n");
2618 /* With MCFW v4.6.x and earlier, the
2619 * boot count will have incremented,
2620 * so re-read the warm_boot_count
2621 * value now to ensure this function
2622 * doesn't think it has changed next
2625 rc
= efx_ef10_get_warm_boot_count(efx
);
2627 nic_data
->warm_boot_count
= rc
;
2631 nic_data
->workaround_26807
= true;
2632 } else if (rc
== -EPERM
) {
2642 efx_ef10_ev_fini(channel
);
2646 static void efx_ef10_ev_remove(struct efx_channel
*channel
)
2648 efx_nic_free_buffer(channel
->efx
, &channel
->eventq
.buf
);
2651 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue
*rx_queue
,
2652 unsigned int rx_queue_label
)
2654 struct efx_nic
*efx
= rx_queue
->efx
;
2656 netif_info(efx
, hw
, efx
->net_dev
,
2657 "rx event arrived on queue %d labeled as queue %u\n",
2658 efx_rx_queue_index(rx_queue
), rx_queue_label
);
2660 efx_schedule_reset(efx
, RESET_TYPE_DISABLE
);
2664 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue
*rx_queue
,
2665 unsigned int actual
, unsigned int expected
)
2667 unsigned int dropped
= (actual
- expected
) & rx_queue
->ptr_mask
;
2668 struct efx_nic
*efx
= rx_queue
->efx
;
2670 netif_info(efx
, hw
, efx
->net_dev
,
2671 "dropped %d events (index=%d expected=%d)\n",
2672 dropped
, actual
, expected
);
2674 efx_schedule_reset(efx
, RESET_TYPE_DISABLE
);
2677 /* partially received RX was aborted. clean up. */
2678 static void efx_ef10_handle_rx_abort(struct efx_rx_queue
*rx_queue
)
2680 unsigned int rx_desc_ptr
;
2682 netif_dbg(rx_queue
->efx
, hw
, rx_queue
->efx
->net_dev
,
2683 "scattered RX aborted (dropping %u buffers)\n",
2684 rx_queue
->scatter_n
);
2686 rx_desc_ptr
= rx_queue
->removed_count
& rx_queue
->ptr_mask
;
2688 efx_rx_packet(rx_queue
, rx_desc_ptr
, rx_queue
->scatter_n
,
2689 0, EFX_RX_PKT_DISCARD
);
2691 rx_queue
->removed_count
+= rx_queue
->scatter_n
;
2692 rx_queue
->scatter_n
= 0;
2693 rx_queue
->scatter_len
= 0;
2694 ++efx_rx_queue_channel(rx_queue
)->n_rx_nodesc_trunc
;
2697 static int efx_ef10_handle_rx_event(struct efx_channel
*channel
,
2698 const efx_qword_t
*event
)
2700 unsigned int rx_bytes
, next_ptr_lbits
, rx_queue_label
, rx_l4_class
;
2701 unsigned int n_descs
, n_packets
, i
;
2702 struct efx_nic
*efx
= channel
->efx
;
2703 struct efx_rx_queue
*rx_queue
;
2707 if (unlikely(ACCESS_ONCE(efx
->reset_pending
)))
2710 /* Basic packet information */
2711 rx_bytes
= EFX_QWORD_FIELD(*event
, ESF_DZ_RX_BYTES
);
2712 next_ptr_lbits
= EFX_QWORD_FIELD(*event
, ESF_DZ_RX_DSC_PTR_LBITS
);
2713 rx_queue_label
= EFX_QWORD_FIELD(*event
, ESF_DZ_RX_QLABEL
);
2714 rx_l4_class
= EFX_QWORD_FIELD(*event
, ESF_DZ_RX_L4_CLASS
);
2715 rx_cont
= EFX_QWORD_FIELD(*event
, ESF_DZ_RX_CONT
);
2717 if (EFX_QWORD_FIELD(*event
, ESF_DZ_RX_DROP_EVENT
))
2718 netdev_WARN(efx
->net_dev
, "saw RX_DROP_EVENT: event="
2720 EFX_QWORD_VAL(*event
));
2722 rx_queue
= efx_channel_get_rx_queue(channel
);
2724 if (unlikely(rx_queue_label
!= efx_rx_queue_index(rx_queue
)))
2725 efx_ef10_handle_rx_wrong_queue(rx_queue
, rx_queue_label
);
2727 n_descs
= ((next_ptr_lbits
- rx_queue
->removed_count
) &
2728 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH
) - 1));
2730 if (n_descs
!= rx_queue
->scatter_n
+ 1) {
2731 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
2733 /* detect rx abort */
2734 if (unlikely(n_descs
== rx_queue
->scatter_n
)) {
2735 if (rx_queue
->scatter_n
== 0 || rx_bytes
!= 0)
2736 netdev_WARN(efx
->net_dev
,
2737 "invalid RX abort: scatter_n=%u event="
2739 rx_queue
->scatter_n
,
2740 EFX_QWORD_VAL(*event
));
2741 efx_ef10_handle_rx_abort(rx_queue
);
2745 /* Check that RX completion merging is valid, i.e.
2746 * the current firmware supports it and this is a
2747 * non-scattered packet.
2749 if (!(nic_data
->datapath_caps
&
2750 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN
)) ||
2751 rx_queue
->scatter_n
!= 0 || rx_cont
) {
2752 efx_ef10_handle_rx_bad_lbits(
2753 rx_queue
, next_ptr_lbits
,
2754 (rx_queue
->removed_count
+
2755 rx_queue
->scatter_n
+ 1) &
2756 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH
) - 1));
2760 /* Merged completion for multiple non-scattered packets */
2761 rx_queue
->scatter_n
= 1;
2762 rx_queue
->scatter_len
= 0;
2763 n_packets
= n_descs
;
2764 ++channel
->n_rx_merge_events
;
2765 channel
->n_rx_merge_packets
+= n_packets
;
2766 flags
|= EFX_RX_PKT_PREFIX_LEN
;
2768 ++rx_queue
->scatter_n
;
2769 rx_queue
->scatter_len
+= rx_bytes
;
2775 if (unlikely(EFX_QWORD_FIELD(*event
, ESF_DZ_RX_ECRC_ERR
)))
2776 flags
|= EFX_RX_PKT_DISCARD
;
2778 if (unlikely(EFX_QWORD_FIELD(*event
, ESF_DZ_RX_IPCKSUM_ERR
))) {
2779 channel
->n_rx_ip_hdr_chksum_err
+= n_packets
;
2780 } else if (unlikely(EFX_QWORD_FIELD(*event
,
2781 ESF_DZ_RX_TCPUDP_CKSUM_ERR
))) {
2782 channel
->n_rx_tcp_udp_chksum_err
+= n_packets
;
2783 } else if (rx_l4_class
== ESE_DZ_L4_CLASS_TCP
||
2784 rx_l4_class
== ESE_DZ_L4_CLASS_UDP
) {
2785 flags
|= EFX_RX_PKT_CSUMMED
;
2788 if (rx_l4_class
== ESE_DZ_L4_CLASS_TCP
)
2789 flags
|= EFX_RX_PKT_TCP
;
2791 channel
->irq_mod_score
+= 2 * n_packets
;
2793 /* Handle received packet(s) */
2794 for (i
= 0; i
< n_packets
; i
++) {
2795 efx_rx_packet(rx_queue
,
2796 rx_queue
->removed_count
& rx_queue
->ptr_mask
,
2797 rx_queue
->scatter_n
, rx_queue
->scatter_len
,
2799 rx_queue
->removed_count
+= rx_queue
->scatter_n
;
2802 rx_queue
->scatter_n
= 0;
2803 rx_queue
->scatter_len
= 0;
2809 efx_ef10_handle_tx_event(struct efx_channel
*channel
, efx_qword_t
*event
)
2811 struct efx_nic
*efx
= channel
->efx
;
2812 struct efx_tx_queue
*tx_queue
;
2813 unsigned int tx_ev_desc_ptr
;
2814 unsigned int tx_ev_q_label
;
2817 if (unlikely(ACCESS_ONCE(efx
->reset_pending
)))
2820 if (unlikely(EFX_QWORD_FIELD(*event
, ESF_DZ_TX_DROP_EVENT
)))
2823 /* Transmit completion */
2824 tx_ev_desc_ptr
= EFX_QWORD_FIELD(*event
, ESF_DZ_TX_DESCR_INDX
);
2825 tx_ev_q_label
= EFX_QWORD_FIELD(*event
, ESF_DZ_TX_QLABEL
);
2826 tx_queue
= efx_channel_get_tx_queue(channel
,
2827 tx_ev_q_label
% EFX_TXQ_TYPES
);
2828 tx_descs
= ((tx_ev_desc_ptr
+ 1 - tx_queue
->read_count
) &
2829 tx_queue
->ptr_mask
);
2830 efx_xmit_done(tx_queue
, tx_ev_desc_ptr
& tx_queue
->ptr_mask
);
2836 efx_ef10_handle_driver_event(struct efx_channel
*channel
, efx_qword_t
*event
)
2838 struct efx_nic
*efx
= channel
->efx
;
2841 subcode
= EFX_QWORD_FIELD(*event
, ESF_DZ_DRV_SUB_CODE
);
2844 case ESE_DZ_DRV_TIMER_EV
:
2845 case ESE_DZ_DRV_WAKE_UP_EV
:
2847 case ESE_DZ_DRV_START_UP_EV
:
2848 /* event queue init complete. ok. */
2851 netif_err(efx
, hw
, efx
->net_dev
,
2852 "channel %d unknown driver event type %d"
2853 " (data " EFX_QWORD_FMT
")\n",
2854 channel
->channel
, subcode
,
2855 EFX_QWORD_VAL(*event
));
2860 static void efx_ef10_handle_driver_generated_event(struct efx_channel
*channel
,
2863 struct efx_nic
*efx
= channel
->efx
;
2866 subcode
= EFX_QWORD_FIELD(*event
, EFX_DWORD_0
);
2870 channel
->event_test_cpu
= raw_smp_processor_id();
2872 case EFX_EF10_REFILL
:
2873 /* The queue must be empty, so we won't receive any rx
2874 * events, so efx_process_channel() won't refill the
2875 * queue. Refill it here
2877 efx_fast_push_rx_descriptors(&channel
->rx_queue
, true);
2880 netif_err(efx
, hw
, efx
->net_dev
,
2881 "channel %d unknown driver event type %u"
2882 " (data " EFX_QWORD_FMT
")\n",
2883 channel
->channel
, (unsigned) subcode
,
2884 EFX_QWORD_VAL(*event
));
2888 static int efx_ef10_ev_process(struct efx_channel
*channel
, int quota
)
2890 struct efx_nic
*efx
= channel
->efx
;
2891 efx_qword_t event
, *p_event
;
2892 unsigned int read_ptr
;
2900 read_ptr
= channel
->eventq_read_ptr
;
2903 p_event
= efx_event(channel
, read_ptr
);
2906 if (!efx_event_present(&event
))
2909 EFX_SET_QWORD(*p_event
);
2913 ev_code
= EFX_QWORD_FIELD(event
, ESF_DZ_EV_CODE
);
2915 netif_vdbg(efx
, drv
, efx
->net_dev
,
2916 "processing event on %d " EFX_QWORD_FMT
"\n",
2917 channel
->channel
, EFX_QWORD_VAL(event
));
2920 case ESE_DZ_EV_CODE_MCDI_EV
:
2921 efx_mcdi_process_event(channel
, &event
);
2923 case ESE_DZ_EV_CODE_RX_EV
:
2924 spent
+= efx_ef10_handle_rx_event(channel
, &event
);
2925 if (spent
>= quota
) {
2926 /* XXX can we split a merged event to
2927 * avoid going over-quota?
2933 case ESE_DZ_EV_CODE_TX_EV
:
2934 tx_descs
+= efx_ef10_handle_tx_event(channel
, &event
);
2935 if (tx_descs
> efx
->txq_entries
) {
2938 } else if (++spent
== quota
) {
2942 case ESE_DZ_EV_CODE_DRIVER_EV
:
2943 efx_ef10_handle_driver_event(channel
, &event
);
2944 if (++spent
== quota
)
2947 case EFX_EF10_DRVGEN_EV
:
2948 efx_ef10_handle_driver_generated_event(channel
, &event
);
2951 netif_err(efx
, hw
, efx
->net_dev
,
2952 "channel %d unknown event type %d"
2953 " (data " EFX_QWORD_FMT
")\n",
2954 channel
->channel
, ev_code
,
2955 EFX_QWORD_VAL(event
));
2960 channel
->eventq_read_ptr
= read_ptr
;
2964 static void efx_ef10_ev_read_ack(struct efx_channel
*channel
)
2966 struct efx_nic
*efx
= channel
->efx
;
2969 if (EFX_EF10_WORKAROUND_35388(efx
)) {
2970 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE
<
2971 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH
));
2972 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE
>
2973 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH
));
2975 EFX_POPULATE_DWORD_2(rptr
, ERF_DD_EVQ_IND_RPTR_FLAGS
,
2976 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH
,
2977 ERF_DD_EVQ_IND_RPTR
,
2978 (channel
->eventq_read_ptr
&
2979 channel
->eventq_mask
) >>
2980 ERF_DD_EVQ_IND_RPTR_WIDTH
);
2981 efx_writed_page(efx
, &rptr
, ER_DD_EVQ_INDIRECT
,
2983 EFX_POPULATE_DWORD_2(rptr
, ERF_DD_EVQ_IND_RPTR_FLAGS
,
2984 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW
,
2985 ERF_DD_EVQ_IND_RPTR
,
2986 channel
->eventq_read_ptr
&
2987 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH
) - 1));
2988 efx_writed_page(efx
, &rptr
, ER_DD_EVQ_INDIRECT
,
2991 EFX_POPULATE_DWORD_1(rptr
, ERF_DZ_EVQ_RPTR
,
2992 channel
->eventq_read_ptr
&
2993 channel
->eventq_mask
);
2994 efx_writed_page(efx
, &rptr
, ER_DZ_EVQ_RPTR
, channel
->channel
);
2998 static void efx_ef10_ev_test_generate(struct efx_channel
*channel
)
3000 MCDI_DECLARE_BUF(inbuf
, MC_CMD_DRIVER_EVENT_IN_LEN
);
3001 struct efx_nic
*efx
= channel
->efx
;
3005 EFX_POPULATE_QWORD_2(event
,
3006 ESF_DZ_EV_CODE
, EFX_EF10_DRVGEN_EV
,
3007 ESF_DZ_EV_DATA
, EFX_EF10_TEST
);
3009 MCDI_SET_DWORD(inbuf
, DRIVER_EVENT_IN_EVQ
, channel
->channel
);
3011 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3012 * already swapped the data to little-endian order.
3014 memcpy(MCDI_PTR(inbuf
, DRIVER_EVENT_IN_DATA
), &event
.u64
[0],
3015 sizeof(efx_qword_t
));
3017 rc
= efx_mcdi_rpc(efx
, MC_CMD_DRIVER_EVENT
, inbuf
, sizeof(inbuf
),
3026 netif_err(efx
, hw
, efx
->net_dev
, "%s: failed rc=%d\n", __func__
, rc
);
3029 void efx_ef10_handle_drain_event(struct efx_nic
*efx
)
3031 if (atomic_dec_and_test(&efx
->active_queues
))
3032 wake_up(&efx
->flush_wq
);
3034 WARN_ON(atomic_read(&efx
->active_queues
) < 0);
3037 static int efx_ef10_fini_dmaq(struct efx_nic
*efx
)
3039 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
3040 struct efx_channel
*channel
;
3041 struct efx_tx_queue
*tx_queue
;
3042 struct efx_rx_queue
*rx_queue
;
3045 /* If the MC has just rebooted, the TX/RX queues will have already been
3046 * torn down, but efx->active_queues needs to be set to zero.
3048 if (nic_data
->must_realloc_vis
) {
3049 atomic_set(&efx
->active_queues
, 0);
3053 /* Do not attempt to write to the NIC during EEH recovery */
3054 if (efx
->state
!= STATE_RECOVERY
) {
3055 efx_for_each_channel(channel
, efx
) {
3056 efx_for_each_channel_rx_queue(rx_queue
, channel
)
3057 efx_ef10_rx_fini(rx_queue
);
3058 efx_for_each_channel_tx_queue(tx_queue
, channel
)
3059 efx_ef10_tx_fini(tx_queue
);
3062 wait_event_timeout(efx
->flush_wq
,
3063 atomic_read(&efx
->active_queues
) == 0,
3064 msecs_to_jiffies(EFX_MAX_FLUSH_TIME
));
3065 pending
= atomic_read(&efx
->active_queues
);
3067 netif_err(efx
, hw
, efx
->net_dev
, "failed to flush %d queues\n",
3076 static void efx_ef10_prepare_flr(struct efx_nic
*efx
)
3078 atomic_set(&efx
->active_queues
, 0);
3081 static bool efx_ef10_filter_equal(const struct efx_filter_spec
*left
,
3082 const struct efx_filter_spec
*right
)
3084 if ((left
->match_flags
^ right
->match_flags
) |
3085 ((left
->flags
^ right
->flags
) &
3086 (EFX_FILTER_FLAG_RX
| EFX_FILTER_FLAG_TX
)))
3089 return memcmp(&left
->outer_vid
, &right
->outer_vid
,
3090 sizeof(struct efx_filter_spec
) -
3091 offsetof(struct efx_filter_spec
, outer_vid
)) == 0;
3094 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec
*spec
)
3096 BUILD_BUG_ON(offsetof(struct efx_filter_spec
, outer_vid
) & 3);
3097 return jhash2((const u32
*)&spec
->outer_vid
,
3098 (sizeof(struct efx_filter_spec
) -
3099 offsetof(struct efx_filter_spec
, outer_vid
)) / 4,
3101 /* XXX should we randomise the initval? */
3104 /* Decide whether a filter should be exclusive or else should allow
3105 * delivery to additional recipients. Currently we decide that
3106 * filters for specific local unicast MAC and IP addresses are
3109 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec
*spec
)
3111 if (spec
->match_flags
& EFX_FILTER_MATCH_LOC_MAC
&&
3112 !is_multicast_ether_addr(spec
->loc_mac
))
3115 if ((spec
->match_flags
&
3116 (EFX_FILTER_MATCH_ETHER_TYPE
| EFX_FILTER_MATCH_LOC_HOST
)) ==
3117 (EFX_FILTER_MATCH_ETHER_TYPE
| EFX_FILTER_MATCH_LOC_HOST
)) {
3118 if (spec
->ether_type
== htons(ETH_P_IP
) &&
3119 !ipv4_is_multicast(spec
->loc_host
[0]))
3121 if (spec
->ether_type
== htons(ETH_P_IPV6
) &&
3122 ((const u8
*)spec
->loc_host
)[0] != 0xff)
3129 static struct efx_filter_spec
*
3130 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table
*table
,
3131 unsigned int filter_idx
)
3133 return (struct efx_filter_spec
*)(table
->entry
[filter_idx
].spec
&
3134 ~EFX_EF10_FILTER_FLAGS
);
3138 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table
*table
,
3139 unsigned int filter_idx
)
3141 return table
->entry
[filter_idx
].spec
& EFX_EF10_FILTER_FLAGS
;
3145 efx_ef10_filter_set_entry(struct efx_ef10_filter_table
*table
,
3146 unsigned int filter_idx
,
3147 const struct efx_filter_spec
*spec
,
3150 table
->entry
[filter_idx
].spec
= (unsigned long)spec
| flags
;
3153 static void efx_ef10_filter_push_prep(struct efx_nic
*efx
,
3154 const struct efx_filter_spec
*spec
,
3155 efx_dword_t
*inbuf
, u64 handle
,
3158 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
3159 u32 flags
= spec
->flags
;
3161 memset(inbuf
, 0, MC_CMD_FILTER_OP_IN_LEN
);
3163 /* Remove RSS flag if we don't have an RSS context. */
3164 if (flags
& EFX_FILTER_FLAG_RX_RSS
&&
3165 spec
->rss_context
== EFX_FILTER_RSS_CONTEXT_DEFAULT
&&
3166 nic_data
->rx_rss_context
== EFX_EF10_RSS_CONTEXT_INVALID
)
3167 flags
&= ~EFX_FILTER_FLAG_RX_RSS
;
3170 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_OP
,
3171 MC_CMD_FILTER_OP_IN_OP_REPLACE
);
3172 MCDI_SET_QWORD(inbuf
, FILTER_OP_IN_HANDLE
, handle
);
3174 u32 match_fields
= 0;
3176 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_OP
,
3177 efx_ef10_filter_is_exclusive(spec
) ?
3178 MC_CMD_FILTER_OP_IN_OP_INSERT
:
3179 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE
);
3181 /* Convert match flags and values. Unlike almost
3182 * everything else in MCDI, these fields are in
3183 * network byte order.
3185 if (spec
->match_flags
& EFX_FILTER_MATCH_LOC_MAC_IG
)
3187 is_multicast_ether_addr(spec
->loc_mac
) ?
3188 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN
:
3189 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN
;
3190 #define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
3191 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
3193 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3194 mcdi_field ## _LBN; \
3196 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
3197 sizeof(spec->gen_field)); \
3198 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
3199 &spec->gen_field, sizeof(spec->gen_field)); \
3201 COPY_FIELD(REM_HOST
, rem_host
, SRC_IP
);
3202 COPY_FIELD(LOC_HOST
, loc_host
, DST_IP
);
3203 COPY_FIELD(REM_MAC
, rem_mac
, SRC_MAC
);
3204 COPY_FIELD(REM_PORT
, rem_port
, SRC_PORT
);
3205 COPY_FIELD(LOC_MAC
, loc_mac
, DST_MAC
);
3206 COPY_FIELD(LOC_PORT
, loc_port
, DST_PORT
);
3207 COPY_FIELD(ETHER_TYPE
, ether_type
, ETHER_TYPE
);
3208 COPY_FIELD(INNER_VID
, inner_vid
, INNER_VLAN
);
3209 COPY_FIELD(OUTER_VID
, outer_vid
, OUTER_VLAN
);
3210 COPY_FIELD(IP_PROTO
, ip_proto
, IP_PROTO
);
3212 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_MATCH_FIELDS
,
3216 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_PORT_ID
, nic_data
->vport_id
);
3217 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_RX_DEST
,
3218 spec
->dmaq_id
== EFX_FILTER_RX_DMAQ_ID_DROP
?
3219 MC_CMD_FILTER_OP_IN_RX_DEST_DROP
:
3220 MC_CMD_FILTER_OP_IN_RX_DEST_HOST
);
3221 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_TX_DOMAIN
, 0);
3222 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_TX_DEST
,
3223 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT
);
3224 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_RX_QUEUE
,
3225 spec
->dmaq_id
== EFX_FILTER_RX_DMAQ_ID_DROP
?
3227 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_RX_MODE
,
3228 (flags
& EFX_FILTER_FLAG_RX_RSS
) ?
3229 MC_CMD_FILTER_OP_IN_RX_MODE_RSS
:
3230 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE
);
3231 if (flags
& EFX_FILTER_FLAG_RX_RSS
)
3232 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_RX_CONTEXT
,
3233 spec
->rss_context
!=
3234 EFX_FILTER_RSS_CONTEXT_DEFAULT
?
3235 spec
->rss_context
: nic_data
->rx_rss_context
);
3238 static int efx_ef10_filter_push(struct efx_nic
*efx
,
3239 const struct efx_filter_spec
*spec
,
3240 u64
*handle
, bool replacing
)
3242 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FILTER_OP_IN_LEN
);
3243 MCDI_DECLARE_BUF(outbuf
, MC_CMD_FILTER_OP_OUT_LEN
);
3246 efx_ef10_filter_push_prep(efx
, spec
, inbuf
, *handle
, replacing
);
3247 rc
= efx_mcdi_rpc(efx
, MC_CMD_FILTER_OP
, inbuf
, sizeof(inbuf
),
3248 outbuf
, sizeof(outbuf
), NULL
);
3250 *handle
= MCDI_QWORD(outbuf
, FILTER_OP_OUT_HANDLE
);
3252 rc
= -EBUSY
; /* to match efx_farch_filter_insert() */
3256 static u32
efx_ef10_filter_mcdi_flags_from_spec(const struct efx_filter_spec
*spec
)
3258 unsigned int match_flags
= spec
->match_flags
;
3261 if (match_flags
& EFX_FILTER_MATCH_LOC_MAC_IG
) {
3262 match_flags
&= ~EFX_FILTER_MATCH_LOC_MAC_IG
;
3264 is_multicast_ether_addr(spec
->loc_mac
) ?
3265 (1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN
) :
3266 (1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN
);
3269 #define MAP_FILTER_TO_MCDI_FLAG(gen_flag, mcdi_field) { \
3270 unsigned int old_match_flags = match_flags; \
3271 match_flags &= ~EFX_FILTER_MATCH_ ## gen_flag; \
3272 if (match_flags != old_match_flags) \
3274 (1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3275 mcdi_field ## _LBN); \
3277 MAP_FILTER_TO_MCDI_FLAG(REM_HOST
, SRC_IP
);
3278 MAP_FILTER_TO_MCDI_FLAG(LOC_HOST
, DST_IP
);
3279 MAP_FILTER_TO_MCDI_FLAG(REM_MAC
, SRC_MAC
);
3280 MAP_FILTER_TO_MCDI_FLAG(REM_PORT
, SRC_PORT
);
3281 MAP_FILTER_TO_MCDI_FLAG(LOC_MAC
, DST_MAC
);
3282 MAP_FILTER_TO_MCDI_FLAG(LOC_PORT
, DST_PORT
);
3283 MAP_FILTER_TO_MCDI_FLAG(ETHER_TYPE
, ETHER_TYPE
);
3284 MAP_FILTER_TO_MCDI_FLAG(INNER_VID
, INNER_VLAN
);
3285 MAP_FILTER_TO_MCDI_FLAG(OUTER_VID
, OUTER_VLAN
);
3286 MAP_FILTER_TO_MCDI_FLAG(IP_PROTO
, IP_PROTO
);
3287 #undef MAP_FILTER_TO_MCDI_FLAG
3289 /* Did we map them all? */
3290 WARN_ON_ONCE(match_flags
);
3295 static int efx_ef10_filter_pri(struct efx_ef10_filter_table
*table
,
3296 const struct efx_filter_spec
*spec
)
3298 u32 mcdi_flags
= efx_ef10_filter_mcdi_flags_from_spec(spec
);
3299 unsigned int match_pri
;
3302 match_pri
< table
->rx_match_count
;
3304 if (table
->rx_match_mcdi_flags
[match_pri
] == mcdi_flags
)
3307 return -EPROTONOSUPPORT
;
3310 static s32
efx_ef10_filter_insert(struct efx_nic
*efx
,
3311 struct efx_filter_spec
*spec
,
3314 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3315 DECLARE_BITMAP(mc_rem_map
, EFX_EF10_FILTER_SEARCH_LIMIT
);
3316 struct efx_filter_spec
*saved_spec
;
3317 unsigned int match_pri
, hash
;
3318 unsigned int priv_flags
;
3319 bool replacing
= false;
3325 /* For now, only support RX filters */
3326 if ((spec
->flags
& (EFX_FILTER_FLAG_RX
| EFX_FILTER_FLAG_TX
)) !=
3330 rc
= efx_ef10_filter_pri(table
, spec
);
3335 hash
= efx_ef10_filter_hash(spec
);
3336 is_mc_recip
= efx_filter_is_mc_recipient(spec
);
3338 bitmap_zero(mc_rem_map
, EFX_EF10_FILTER_SEARCH_LIMIT
);
3340 /* Find any existing filters with the same match tuple or
3341 * else a free slot to insert at. If any of them are busy,
3342 * we have to wait and retry.
3345 unsigned int depth
= 1;
3348 spin_lock_bh(&efx
->filter_lock
);
3351 i
= (hash
+ depth
) & (HUNT_FILTER_TBL_ROWS
- 1);
3352 saved_spec
= efx_ef10_filter_entry_spec(table
, i
);
3357 } else if (efx_ef10_filter_equal(spec
, saved_spec
)) {
3358 if (table
->entry
[i
].spec
&
3359 EFX_EF10_FILTER_FLAG_BUSY
)
3361 if (spec
->priority
< saved_spec
->priority
&&
3362 spec
->priority
!= EFX_FILTER_PRI_AUTO
) {
3367 /* This is the only one */
3368 if (spec
->priority
==
3369 saved_spec
->priority
&&
3376 } else if (spec
->priority
>
3377 saved_spec
->priority
||
3379 saved_spec
->priority
&&
3384 __set_bit(depth
, mc_rem_map
);
3388 /* Once we reach the maximum search depth, use
3389 * the first suitable slot or return -EBUSY if
3392 if (depth
== EFX_EF10_FILTER_SEARCH_LIMIT
) {
3393 if (ins_index
< 0) {
3403 prepare_to_wait(&table
->waitq
, &wait
, TASK_UNINTERRUPTIBLE
);
3404 spin_unlock_bh(&efx
->filter_lock
);
3409 /* Create a software table entry if necessary, and mark it
3410 * busy. We might yet fail to insert, but any attempt to
3411 * insert a conflicting filter while we're waiting for the
3412 * firmware must find the busy entry.
3414 saved_spec
= efx_ef10_filter_entry_spec(table
, ins_index
);
3416 if (spec
->priority
== EFX_FILTER_PRI_AUTO
&&
3417 saved_spec
->priority
>= EFX_FILTER_PRI_AUTO
) {
3418 /* Just make sure it won't be removed */
3419 if (saved_spec
->priority
> EFX_FILTER_PRI_AUTO
)
3420 saved_spec
->flags
|= EFX_FILTER_FLAG_RX_OVER_AUTO
;
3421 table
->entry
[ins_index
].spec
&=
3422 ~EFX_EF10_FILTER_FLAG_AUTO_OLD
;
3427 priv_flags
= efx_ef10_filter_entry_flags(table
, ins_index
);
3429 saved_spec
= kmalloc(sizeof(*spec
), GFP_ATOMIC
);
3434 *saved_spec
= *spec
;
3437 efx_ef10_filter_set_entry(table
, ins_index
, saved_spec
,
3438 priv_flags
| EFX_EF10_FILTER_FLAG_BUSY
);
3440 /* Mark lower-priority multicast recipients busy prior to removal */
3442 unsigned int depth
, i
;
3444 for (depth
= 0; depth
< EFX_EF10_FILTER_SEARCH_LIMIT
; depth
++) {
3445 i
= (hash
+ depth
) & (HUNT_FILTER_TBL_ROWS
- 1);
3446 if (test_bit(depth
, mc_rem_map
))
3447 table
->entry
[i
].spec
|=
3448 EFX_EF10_FILTER_FLAG_BUSY
;
3452 spin_unlock_bh(&efx
->filter_lock
);
3454 rc
= efx_ef10_filter_push(efx
, spec
, &table
->entry
[ins_index
].handle
,
3457 /* Finalise the software table entry */
3458 spin_lock_bh(&efx
->filter_lock
);
3461 /* Update the fields that may differ */
3462 if (saved_spec
->priority
== EFX_FILTER_PRI_AUTO
)
3463 saved_spec
->flags
|=
3464 EFX_FILTER_FLAG_RX_OVER_AUTO
;
3465 saved_spec
->priority
= spec
->priority
;
3466 saved_spec
->flags
&= EFX_FILTER_FLAG_RX_OVER_AUTO
;
3467 saved_spec
->flags
|= spec
->flags
;
3468 saved_spec
->rss_context
= spec
->rss_context
;
3469 saved_spec
->dmaq_id
= spec
->dmaq_id
;
3471 } else if (!replacing
) {
3475 efx_ef10_filter_set_entry(table
, ins_index
, saved_spec
, priv_flags
);
3477 /* Remove and finalise entries for lower-priority multicast
3481 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FILTER_OP_IN_LEN
);
3482 unsigned int depth
, i
;
3484 memset(inbuf
, 0, sizeof(inbuf
));
3486 for (depth
= 0; depth
< EFX_EF10_FILTER_SEARCH_LIMIT
; depth
++) {
3487 if (!test_bit(depth
, mc_rem_map
))
3490 i
= (hash
+ depth
) & (HUNT_FILTER_TBL_ROWS
- 1);
3491 saved_spec
= efx_ef10_filter_entry_spec(table
, i
);
3492 priv_flags
= efx_ef10_filter_entry_flags(table
, i
);
3495 spin_unlock_bh(&efx
->filter_lock
);
3496 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_OP
,
3497 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE
);
3498 MCDI_SET_QWORD(inbuf
, FILTER_OP_IN_HANDLE
,
3499 table
->entry
[i
].handle
);
3500 rc
= efx_mcdi_rpc(efx
, MC_CMD_FILTER_OP
,
3501 inbuf
, sizeof(inbuf
),
3503 spin_lock_bh(&efx
->filter_lock
);
3511 priv_flags
&= ~EFX_EF10_FILTER_FLAG_BUSY
;
3513 efx_ef10_filter_set_entry(table
, i
, saved_spec
,
3518 /* If successful, return the inserted filter ID */
3520 rc
= match_pri
* HUNT_FILTER_TBL_ROWS
+ ins_index
;
3522 wake_up_all(&table
->waitq
);
3524 spin_unlock_bh(&efx
->filter_lock
);
3525 finish_wait(&table
->waitq
, &wait
);
3529 static void efx_ef10_filter_update_rx_scatter(struct efx_nic
*efx
)
3531 /* no need to do anything here on EF10 */
3535 * If !by_index, remove by ID
3536 * If by_index, remove by index
3537 * Filter ID may come from userland and must be range-checked.
3539 static int efx_ef10_filter_remove_internal(struct efx_nic
*efx
,
3540 unsigned int priority_mask
,
3541 u32 filter_id
, bool by_index
)
3543 unsigned int filter_idx
= filter_id
% HUNT_FILTER_TBL_ROWS
;
3544 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3545 MCDI_DECLARE_BUF(inbuf
,
3546 MC_CMD_FILTER_OP_IN_HANDLE_OFST
+
3547 MC_CMD_FILTER_OP_IN_HANDLE_LEN
);
3548 struct efx_filter_spec
*spec
;
3552 /* Find the software table entry and mark it busy. Don't
3553 * remove it yet; any attempt to update while we're waiting
3554 * for the firmware must find the busy entry.
3557 spin_lock_bh(&efx
->filter_lock
);
3558 if (!(table
->entry
[filter_idx
].spec
&
3559 EFX_EF10_FILTER_FLAG_BUSY
))
3561 prepare_to_wait(&table
->waitq
, &wait
, TASK_UNINTERRUPTIBLE
);
3562 spin_unlock_bh(&efx
->filter_lock
);
3566 spec
= efx_ef10_filter_entry_spec(table
, filter_idx
);
3569 efx_ef10_filter_pri(table
, spec
) !=
3570 filter_id
/ HUNT_FILTER_TBL_ROWS
)) {
3575 if (spec
->flags
& EFX_FILTER_FLAG_RX_OVER_AUTO
&&
3576 priority_mask
== (1U << EFX_FILTER_PRI_AUTO
)) {
3577 /* Just remove flags */
3578 spec
->flags
&= ~EFX_FILTER_FLAG_RX_OVER_AUTO
;
3579 table
->entry
[filter_idx
].spec
&= ~EFX_EF10_FILTER_FLAG_AUTO_OLD
;
3584 if (!(priority_mask
& (1U << spec
->priority
))) {
3589 table
->entry
[filter_idx
].spec
|= EFX_EF10_FILTER_FLAG_BUSY
;
3590 spin_unlock_bh(&efx
->filter_lock
);
3592 if (spec
->flags
& EFX_FILTER_FLAG_RX_OVER_AUTO
) {
3593 /* Reset to an automatic filter */
3595 struct efx_filter_spec new_spec
= *spec
;
3597 new_spec
.priority
= EFX_FILTER_PRI_AUTO
;
3598 new_spec
.flags
= (EFX_FILTER_FLAG_RX
|
3599 (efx_rss_enabled(efx
) ?
3600 EFX_FILTER_FLAG_RX_RSS
: 0));
3601 new_spec
.dmaq_id
= 0;
3602 new_spec
.rss_context
= EFX_FILTER_RSS_CONTEXT_DEFAULT
;
3603 rc
= efx_ef10_filter_push(efx
, &new_spec
,
3604 &table
->entry
[filter_idx
].handle
,
3607 spin_lock_bh(&efx
->filter_lock
);
3611 /* Really remove the filter */
3613 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_OP
,
3614 efx_ef10_filter_is_exclusive(spec
) ?
3615 MC_CMD_FILTER_OP_IN_OP_REMOVE
:
3616 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE
);
3617 MCDI_SET_QWORD(inbuf
, FILTER_OP_IN_HANDLE
,
3618 table
->entry
[filter_idx
].handle
);
3619 rc
= efx_mcdi_rpc(efx
, MC_CMD_FILTER_OP
,
3620 inbuf
, sizeof(inbuf
), NULL
, 0, NULL
);
3622 spin_lock_bh(&efx
->filter_lock
);
3625 efx_ef10_filter_set_entry(table
, filter_idx
, NULL
, 0);
3629 table
->entry
[filter_idx
].spec
&= ~EFX_EF10_FILTER_FLAG_BUSY
;
3630 wake_up_all(&table
->waitq
);
3632 spin_unlock_bh(&efx
->filter_lock
);
3633 finish_wait(&table
->waitq
, &wait
);
3637 static int efx_ef10_filter_remove_safe(struct efx_nic
*efx
,
3638 enum efx_filter_priority priority
,
3641 return efx_ef10_filter_remove_internal(efx
, 1U << priority
,
3645 static u32
efx_ef10_filter_get_unsafe_id(struct efx_nic
*efx
, u32 filter_id
)
3647 return filter_id
% HUNT_FILTER_TBL_ROWS
;
3650 static void efx_ef10_filter_remove_unsafe(struct efx_nic
*efx
,
3651 enum efx_filter_priority priority
,
3654 if (filter_id
== EFX_EF10_FILTER_ID_INVALID
)
3656 efx_ef10_filter_remove_internal(efx
, 1U << priority
, filter_id
, true);
3659 static int efx_ef10_filter_get_safe(struct efx_nic
*efx
,
3660 enum efx_filter_priority priority
,
3661 u32 filter_id
, struct efx_filter_spec
*spec
)
3663 unsigned int filter_idx
= filter_id
% HUNT_FILTER_TBL_ROWS
;
3664 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3665 const struct efx_filter_spec
*saved_spec
;
3668 spin_lock_bh(&efx
->filter_lock
);
3669 saved_spec
= efx_ef10_filter_entry_spec(table
, filter_idx
);
3670 if (saved_spec
&& saved_spec
->priority
== priority
&&
3671 efx_ef10_filter_pri(table
, saved_spec
) ==
3672 filter_id
/ HUNT_FILTER_TBL_ROWS
) {
3673 *spec
= *saved_spec
;
3678 spin_unlock_bh(&efx
->filter_lock
);
3682 static int efx_ef10_filter_clear_rx(struct efx_nic
*efx
,
3683 enum efx_filter_priority priority
)
3685 unsigned int priority_mask
;
3689 priority_mask
= (((1U << (priority
+ 1)) - 1) &
3690 ~(1U << EFX_FILTER_PRI_AUTO
));
3692 for (i
= 0; i
< HUNT_FILTER_TBL_ROWS
; i
++) {
3693 rc
= efx_ef10_filter_remove_internal(efx
, priority_mask
,
3695 if (rc
&& rc
!= -ENOENT
)
3702 static u32
efx_ef10_filter_count_rx_used(struct efx_nic
*efx
,
3703 enum efx_filter_priority priority
)
3705 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3706 unsigned int filter_idx
;
3709 spin_lock_bh(&efx
->filter_lock
);
3710 for (filter_idx
= 0; filter_idx
< HUNT_FILTER_TBL_ROWS
; filter_idx
++) {
3711 if (table
->entry
[filter_idx
].spec
&&
3712 efx_ef10_filter_entry_spec(table
, filter_idx
)->priority
==
3716 spin_unlock_bh(&efx
->filter_lock
);
3720 static u32
efx_ef10_filter_get_rx_id_limit(struct efx_nic
*efx
)
3722 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3724 return table
->rx_match_count
* HUNT_FILTER_TBL_ROWS
;
3727 static s32
efx_ef10_filter_get_rx_ids(struct efx_nic
*efx
,
3728 enum efx_filter_priority priority
,
3731 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3732 struct efx_filter_spec
*spec
;
3733 unsigned int filter_idx
;
3736 spin_lock_bh(&efx
->filter_lock
);
3737 for (filter_idx
= 0; filter_idx
< HUNT_FILTER_TBL_ROWS
; filter_idx
++) {
3738 spec
= efx_ef10_filter_entry_spec(table
, filter_idx
);
3739 if (spec
&& spec
->priority
== priority
) {
3740 if (count
== size
) {
3744 buf
[count
++] = (efx_ef10_filter_pri(table
, spec
) *
3745 HUNT_FILTER_TBL_ROWS
+
3749 spin_unlock_bh(&efx
->filter_lock
);
3753 #ifdef CONFIG_RFS_ACCEL
3755 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete
;
3757 static s32
efx_ef10_filter_rfs_insert(struct efx_nic
*efx
,
3758 struct efx_filter_spec
*spec
)
3760 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3761 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FILTER_OP_IN_LEN
);
3762 struct efx_filter_spec
*saved_spec
;
3763 unsigned int hash
, i
, depth
= 1;
3764 bool replacing
= false;
3769 /* Must be an RX filter without RSS and not for a multicast
3770 * destination address (RFS only works for connected sockets).
3771 * These restrictions allow us to pass only a tiny amount of
3772 * data through to the completion function.
3774 EFX_WARN_ON_PARANOID(spec
->flags
!=
3775 (EFX_FILTER_FLAG_RX
| EFX_FILTER_FLAG_RX_SCATTER
));
3776 EFX_WARN_ON_PARANOID(spec
->priority
!= EFX_FILTER_PRI_HINT
);
3777 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec
));
3779 hash
= efx_ef10_filter_hash(spec
);
3781 spin_lock_bh(&efx
->filter_lock
);
3783 /* Find any existing filter with the same match tuple or else
3784 * a free slot to insert at. If an existing filter is busy,
3785 * we have to give up.
3788 i
= (hash
+ depth
) & (HUNT_FILTER_TBL_ROWS
- 1);
3789 saved_spec
= efx_ef10_filter_entry_spec(table
, i
);
3794 } else if (efx_ef10_filter_equal(spec
, saved_spec
)) {
3795 if (table
->entry
[i
].spec
& EFX_EF10_FILTER_FLAG_BUSY
) {
3799 if (spec
->priority
< saved_spec
->priority
) {
3807 /* Once we reach the maximum search depth, use the
3808 * first suitable slot or return -EBUSY if there was
3811 if (depth
== EFX_EF10_FILTER_SEARCH_LIMIT
) {
3812 if (ins_index
< 0) {
3822 /* Create a software table entry if necessary, and mark it
3823 * busy. We might yet fail to insert, but any attempt to
3824 * insert a conflicting filter while we're waiting for the
3825 * firmware must find the busy entry.
3827 saved_spec
= efx_ef10_filter_entry_spec(table
, ins_index
);
3831 saved_spec
= kmalloc(sizeof(*spec
), GFP_ATOMIC
);
3836 *saved_spec
= *spec
;
3838 efx_ef10_filter_set_entry(table
, ins_index
, saved_spec
,
3839 EFX_EF10_FILTER_FLAG_BUSY
);
3841 spin_unlock_bh(&efx
->filter_lock
);
3843 /* Pack up the variables needed on completion */
3844 cookie
= replacing
<< 31 | ins_index
<< 16 | spec
->dmaq_id
;
3846 efx_ef10_filter_push_prep(efx
, spec
, inbuf
,
3847 table
->entry
[ins_index
].handle
, replacing
);
3848 efx_mcdi_rpc_async(efx
, MC_CMD_FILTER_OP
, inbuf
, sizeof(inbuf
),
3849 MC_CMD_FILTER_OP_OUT_LEN
,
3850 efx_ef10_filter_rfs_insert_complete
, cookie
);
3855 spin_unlock_bh(&efx
->filter_lock
);
3860 efx_ef10_filter_rfs_insert_complete(struct efx_nic
*efx
, unsigned long cookie
,
3861 int rc
, efx_dword_t
*outbuf
,
3862 size_t outlen_actual
)
3864 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3865 unsigned int ins_index
, dmaq_id
;
3866 struct efx_filter_spec
*spec
;
3869 /* Unpack the cookie */
3870 replacing
= cookie
>> 31;
3871 ins_index
= (cookie
>> 16) & (HUNT_FILTER_TBL_ROWS
- 1);
3872 dmaq_id
= cookie
& 0xffff;
3874 spin_lock_bh(&efx
->filter_lock
);
3875 spec
= efx_ef10_filter_entry_spec(table
, ins_index
);
3877 table
->entry
[ins_index
].handle
=
3878 MCDI_QWORD(outbuf
, FILTER_OP_OUT_HANDLE
);
3880 spec
->dmaq_id
= dmaq_id
;
3881 } else if (!replacing
) {
3885 efx_ef10_filter_set_entry(table
, ins_index
, spec
, 0);
3886 spin_unlock_bh(&efx
->filter_lock
);
3888 wake_up_all(&table
->waitq
);
3892 efx_ef10_filter_rfs_expire_complete(struct efx_nic
*efx
,
3893 unsigned long filter_idx
,
3894 int rc
, efx_dword_t
*outbuf
,
3895 size_t outlen_actual
);
3897 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic
*efx
, u32 flow_id
,
3898 unsigned int filter_idx
)
3900 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3901 struct efx_filter_spec
*spec
=
3902 efx_ef10_filter_entry_spec(table
, filter_idx
);
3903 MCDI_DECLARE_BUF(inbuf
,
3904 MC_CMD_FILTER_OP_IN_HANDLE_OFST
+
3905 MC_CMD_FILTER_OP_IN_HANDLE_LEN
);
3908 (table
->entry
[filter_idx
].spec
& EFX_EF10_FILTER_FLAG_BUSY
) ||
3909 spec
->priority
!= EFX_FILTER_PRI_HINT
||
3910 !rps_may_expire_flow(efx
->net_dev
, spec
->dmaq_id
,
3911 flow_id
, filter_idx
))
3914 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_OP
,
3915 MC_CMD_FILTER_OP_IN_OP_REMOVE
);
3916 MCDI_SET_QWORD(inbuf
, FILTER_OP_IN_HANDLE
,
3917 table
->entry
[filter_idx
].handle
);
3918 if (efx_mcdi_rpc_async(efx
, MC_CMD_FILTER_OP
, inbuf
, sizeof(inbuf
), 0,
3919 efx_ef10_filter_rfs_expire_complete
, filter_idx
))
3922 table
->entry
[filter_idx
].spec
|= EFX_EF10_FILTER_FLAG_BUSY
;
3927 efx_ef10_filter_rfs_expire_complete(struct efx_nic
*efx
,
3928 unsigned long filter_idx
,
3929 int rc
, efx_dword_t
*outbuf
,
3930 size_t outlen_actual
)
3932 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3933 struct efx_filter_spec
*spec
=
3934 efx_ef10_filter_entry_spec(table
, filter_idx
);
3936 spin_lock_bh(&efx
->filter_lock
);
3939 efx_ef10_filter_set_entry(table
, filter_idx
, NULL
, 0);
3941 table
->entry
[filter_idx
].spec
&= ~EFX_EF10_FILTER_FLAG_BUSY
;
3942 wake_up_all(&table
->waitq
);
3943 spin_unlock_bh(&efx
->filter_lock
);
3946 #endif /* CONFIG_RFS_ACCEL */
3948 static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags
)
3950 int match_flags
= 0;
3952 #define MAP_FLAG(gen_flag, mcdi_field) { \
3953 u32 old_mcdi_flags = mcdi_flags; \
3954 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3955 mcdi_field ## _LBN); \
3956 if (mcdi_flags != old_mcdi_flags) \
3957 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
3959 MAP_FLAG(LOC_MAC_IG
, UNKNOWN_UCAST_DST
);
3960 MAP_FLAG(LOC_MAC_IG
, UNKNOWN_MCAST_DST
);
3961 MAP_FLAG(REM_HOST
, SRC_IP
);
3962 MAP_FLAG(LOC_HOST
, DST_IP
);
3963 MAP_FLAG(REM_MAC
, SRC_MAC
);
3964 MAP_FLAG(REM_PORT
, SRC_PORT
);
3965 MAP_FLAG(LOC_MAC
, DST_MAC
);
3966 MAP_FLAG(LOC_PORT
, DST_PORT
);
3967 MAP_FLAG(ETHER_TYPE
, ETHER_TYPE
);
3968 MAP_FLAG(INNER_VID
, INNER_VLAN
);
3969 MAP_FLAG(OUTER_VID
, OUTER_VLAN
);
3970 MAP_FLAG(IP_PROTO
, IP_PROTO
);
3973 /* Did we map them all? */
3980 static void efx_ef10_filter_cleanup_vlans(struct efx_nic
*efx
)
3982 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3983 struct efx_ef10_filter_vlan
*vlan
, *next_vlan
;
3985 /* See comment in efx_ef10_filter_table_remove() */
3986 if (!efx_rwsem_assert_write_locked(&efx
->filter_sem
))
3992 list_for_each_entry_safe(vlan
, next_vlan
, &table
->vlan_list
, list
)
3993 efx_ef10_filter_del_vlan_internal(efx
, vlan
);
3996 static bool efx_ef10_filter_match_supported(struct efx_ef10_filter_table
*table
,
3997 enum efx_filter_match_flags match_flags
)
3999 unsigned int match_pri
;
4003 match_pri
< table
->rx_match_count
;
4005 mf
= efx_ef10_filter_match_flags_from_mcdi(
4006 table
->rx_match_mcdi_flags
[match_pri
]);
4007 if (mf
== match_flags
)
4014 static int efx_ef10_filter_table_probe(struct efx_nic
*efx
)
4016 MCDI_DECLARE_BUF(inbuf
, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN
);
4017 MCDI_DECLARE_BUF(outbuf
, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX
);
4018 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
4019 struct net_device
*net_dev
= efx
->net_dev
;
4020 unsigned int pd_match_pri
, pd_match_count
;
4021 struct efx_ef10_filter_table
*table
;
4022 struct efx_ef10_vlan
*vlan
;
4026 if (!efx_rwsem_assert_write_locked(&efx
->filter_sem
))
4029 if (efx
->filter_state
) /* already probed */
4032 table
= kzalloc(sizeof(*table
), GFP_KERNEL
);
4036 /* Find out which RX filter types are supported, and their priorities */
4037 MCDI_SET_DWORD(inbuf
, GET_PARSER_DISP_INFO_IN_OP
,
4038 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES
);
4039 rc
= efx_mcdi_rpc(efx
, MC_CMD_GET_PARSER_DISP_INFO
,
4040 inbuf
, sizeof(inbuf
), outbuf
, sizeof(outbuf
),
4044 pd_match_count
= MCDI_VAR_ARRAY_LEN(
4045 outlen
, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES
);
4046 table
->rx_match_count
= 0;
4048 for (pd_match_pri
= 0; pd_match_pri
< pd_match_count
; pd_match_pri
++) {
4052 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES
,
4054 rc
= efx_ef10_filter_match_flags_from_mcdi(mcdi_flags
);
4056 netif_dbg(efx
, probe
, efx
->net_dev
,
4057 "%s: fw flags %#x pri %u not supported in driver\n",
4058 __func__
, mcdi_flags
, pd_match_pri
);
4060 netif_dbg(efx
, probe
, efx
->net_dev
,
4061 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
4062 __func__
, mcdi_flags
, pd_match_pri
,
4063 rc
, table
->rx_match_count
);
4064 table
->rx_match_mcdi_flags
[table
->rx_match_count
] = mcdi_flags
;
4065 table
->rx_match_count
++;
4069 if ((efx_supported_features(efx
) & NETIF_F_HW_VLAN_CTAG_FILTER
) &&
4070 !(efx_ef10_filter_match_supported(table
,
4071 (EFX_FILTER_MATCH_OUTER_VID
| EFX_FILTER_MATCH_LOC_MAC
)) &&
4072 efx_ef10_filter_match_supported(table
,
4073 (EFX_FILTER_MATCH_OUTER_VID
| EFX_FILTER_MATCH_LOC_MAC_IG
)))) {
4074 netif_info(efx
, probe
, net_dev
,
4075 "VLAN filters are not supported in this firmware variant\n");
4076 net_dev
->features
&= ~NETIF_F_HW_VLAN_CTAG_FILTER
;
4077 efx
->fixed_features
&= ~NETIF_F_HW_VLAN_CTAG_FILTER
;
4078 net_dev
->hw_features
&= ~NETIF_F_HW_VLAN_CTAG_FILTER
;
4081 table
->entry
= vzalloc(HUNT_FILTER_TBL_ROWS
* sizeof(*table
->entry
));
4082 if (!table
->entry
) {
4087 table
->mc_promisc_last
= false;
4088 table
->vlan_filter
=
4089 !!(efx
->net_dev
->features
& NETIF_F_HW_VLAN_CTAG_FILTER
);
4090 INIT_LIST_HEAD(&table
->vlan_list
);
4092 efx
->filter_state
= table
;
4093 init_waitqueue_head(&table
->waitq
);
4095 list_for_each_entry(vlan
, &nic_data
->vlan_list
, list
) {
4096 rc
= efx_ef10_filter_add_vlan(efx
, vlan
->vid
);
4104 efx_ef10_filter_cleanup_vlans(efx
);
4105 efx
->filter_state
= NULL
;
4111 /* Caller must hold efx->filter_sem for read if race against
4112 * efx_ef10_filter_table_remove() is possible
4114 static void efx_ef10_filter_table_restore(struct efx_nic
*efx
)
4116 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4117 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
4118 struct efx_filter_spec
*spec
;
4119 unsigned int filter_idx
;
4120 bool failed
= false;
4123 WARN_ON(!rwsem_is_locked(&efx
->filter_sem
));
4125 if (!nic_data
->must_restore_filters
)
4131 spin_lock_bh(&efx
->filter_lock
);
4133 for (filter_idx
= 0; filter_idx
< HUNT_FILTER_TBL_ROWS
; filter_idx
++) {
4134 spec
= efx_ef10_filter_entry_spec(table
, filter_idx
);
4138 table
->entry
[filter_idx
].spec
|= EFX_EF10_FILTER_FLAG_BUSY
;
4139 spin_unlock_bh(&efx
->filter_lock
);
4141 rc
= efx_ef10_filter_push(efx
, spec
,
4142 &table
->entry
[filter_idx
].handle
,
4147 spin_lock_bh(&efx
->filter_lock
);
4150 efx_ef10_filter_set_entry(table
, filter_idx
, NULL
, 0);
4152 table
->entry
[filter_idx
].spec
&=
4153 ~EFX_EF10_FILTER_FLAG_BUSY
;
4157 spin_unlock_bh(&efx
->filter_lock
);
4160 netif_err(efx
, hw
, efx
->net_dev
,
4161 "unable to restore all filters\n");
4163 nic_data
->must_restore_filters
= false;
4166 static void efx_ef10_filter_table_remove(struct efx_nic
*efx
)
4168 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4169 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FILTER_OP_IN_LEN
);
4170 struct efx_filter_spec
*spec
;
4171 unsigned int filter_idx
;
4174 efx_ef10_filter_cleanup_vlans(efx
);
4175 efx
->filter_state
= NULL
;
4176 /* If we were called without locking, then it's not safe to free
4177 * the table as others might be using it. So we just WARN, leak
4178 * the memory, and potentially get an inconsistent filter table
4180 * This should never actually happen.
4182 if (!efx_rwsem_assert_write_locked(&efx
->filter_sem
))
4188 for (filter_idx
= 0; filter_idx
< HUNT_FILTER_TBL_ROWS
; filter_idx
++) {
4189 spec
= efx_ef10_filter_entry_spec(table
, filter_idx
);
4193 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_OP
,
4194 efx_ef10_filter_is_exclusive(spec
) ?
4195 MC_CMD_FILTER_OP_IN_OP_REMOVE
:
4196 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE
);
4197 MCDI_SET_QWORD(inbuf
, FILTER_OP_IN_HANDLE
,
4198 table
->entry
[filter_idx
].handle
);
4199 rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_FILTER_OP
, inbuf
,
4200 sizeof(inbuf
), NULL
, 0, NULL
);
4202 netif_info(efx
, drv
, efx
->net_dev
,
4203 "%s: filter %04x remove failed\n",
4204 __func__
, filter_idx
);
4208 vfree(table
->entry
);
4212 static void efx_ef10_filter_mark_one_old(struct efx_nic
*efx
, uint16_t *id
)
4214 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4215 unsigned int filter_idx
;
4217 if (*id
!= EFX_EF10_FILTER_ID_INVALID
) {
4218 filter_idx
= efx_ef10_filter_get_unsafe_id(efx
, *id
);
4219 if (!table
->entry
[filter_idx
].spec
)
4220 netif_dbg(efx
, drv
, efx
->net_dev
,
4221 "marked null spec old %04x:%04x\n", *id
,
4223 table
->entry
[filter_idx
].spec
|= EFX_EF10_FILTER_FLAG_AUTO_OLD
;
4224 *id
= EFX_EF10_FILTER_ID_INVALID
;
4228 /* Mark old per-VLAN filters that may need to be removed */
4229 static void _efx_ef10_filter_vlan_mark_old(struct efx_nic
*efx
,
4230 struct efx_ef10_filter_vlan
*vlan
)
4232 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4235 for (i
= 0; i
< table
->dev_uc_count
; i
++)
4236 efx_ef10_filter_mark_one_old(efx
, &vlan
->uc
[i
]);
4237 for (i
= 0; i
< table
->dev_mc_count
; i
++)
4238 efx_ef10_filter_mark_one_old(efx
, &vlan
->mc
[i
]);
4239 efx_ef10_filter_mark_one_old(efx
, &vlan
->ucdef
);
4240 efx_ef10_filter_mark_one_old(efx
, &vlan
->bcast
);
4241 efx_ef10_filter_mark_one_old(efx
, &vlan
->mcdef
);
4244 /* Mark old filters that may need to be removed.
4245 * Caller must hold efx->filter_sem for read if race against
4246 * efx_ef10_filter_table_remove() is possible
4248 static void efx_ef10_filter_mark_old(struct efx_nic
*efx
)
4250 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4251 struct efx_ef10_filter_vlan
*vlan
;
4253 spin_lock_bh(&efx
->filter_lock
);
4254 list_for_each_entry(vlan
, &table
->vlan_list
, list
)
4255 _efx_ef10_filter_vlan_mark_old(efx
, vlan
);
4256 spin_unlock_bh(&efx
->filter_lock
);
4259 static void efx_ef10_filter_uc_addr_list(struct efx_nic
*efx
)
4261 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4262 struct net_device
*net_dev
= efx
->net_dev
;
4263 struct netdev_hw_addr
*uc
;
4267 addr_count
= netdev_uc_count(net_dev
);
4268 table
->uc_promisc
= !!(net_dev
->flags
& IFF_PROMISC
);
4269 table
->dev_uc_count
= 1 + addr_count
;
4270 ether_addr_copy(table
->dev_uc_list
[0].addr
, net_dev
->dev_addr
);
4272 netdev_for_each_uc_addr(uc
, net_dev
) {
4273 if (i
>= EFX_EF10_FILTER_DEV_UC_MAX
) {
4274 table
->uc_promisc
= true;
4277 ether_addr_copy(table
->dev_uc_list
[i
].addr
, uc
->addr
);
4282 static void efx_ef10_filter_mc_addr_list(struct efx_nic
*efx
)
4284 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4285 struct net_device
*net_dev
= efx
->net_dev
;
4286 struct netdev_hw_addr
*mc
;
4287 unsigned int i
, addr_count
;
4289 table
->mc_promisc
= !!(net_dev
->flags
& (IFF_PROMISC
| IFF_ALLMULTI
));
4291 addr_count
= netdev_mc_count(net_dev
);
4293 netdev_for_each_mc_addr(mc
, net_dev
) {
4294 if (i
>= EFX_EF10_FILTER_DEV_MC_MAX
) {
4295 table
->mc_promisc
= true;
4298 ether_addr_copy(table
->dev_mc_list
[i
].addr
, mc
->addr
);
4302 table
->dev_mc_count
= i
;
4305 static int efx_ef10_filter_insert_addr_list(struct efx_nic
*efx
,
4306 struct efx_ef10_filter_vlan
*vlan
,
4307 bool multicast
, bool rollback
)
4309 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4310 struct efx_ef10_dev_addr
*addr_list
;
4311 enum efx_filter_flags filter_flags
;
4312 struct efx_filter_spec spec
;
4320 addr_list
= table
->dev_mc_list
;
4321 addr_count
= table
->dev_mc_count
;
4324 addr_list
= table
->dev_uc_list
;
4325 addr_count
= table
->dev_uc_count
;
4329 filter_flags
= efx_rss_enabled(efx
) ? EFX_FILTER_FLAG_RX_RSS
: 0;
4331 /* Insert/renew filters */
4332 for (i
= 0; i
< addr_count
; i
++) {
4333 efx_filter_init_rx(&spec
, EFX_FILTER_PRI_AUTO
, filter_flags
, 0);
4334 efx_filter_set_eth_local(&spec
, vlan
->vid
, addr_list
[i
].addr
);
4335 rc
= efx_ef10_filter_insert(efx
, &spec
, true);
4338 netif_info(efx
, drv
, efx
->net_dev
,
4339 "efx_ef10_filter_insert failed rc=%d\n",
4341 /* Fall back to promiscuous */
4342 for (j
= 0; j
< i
; j
++) {
4343 efx_ef10_filter_remove_unsafe(
4344 efx
, EFX_FILTER_PRI_AUTO
,
4346 ids
[j
] = EFX_EF10_FILTER_ID_INVALID
;
4350 /* mark as not inserted, and carry on */
4351 rc
= EFX_EF10_FILTER_ID_INVALID
;
4354 ids
[i
] = efx_ef10_filter_get_unsafe_id(efx
, rc
);
4357 if (multicast
&& rollback
) {
4358 /* Also need an Ethernet broadcast filter */
4359 efx_filter_init_rx(&spec
, EFX_FILTER_PRI_AUTO
, filter_flags
, 0);
4360 eth_broadcast_addr(baddr
);
4361 efx_filter_set_eth_local(&spec
, vlan
->vid
, baddr
);
4362 rc
= efx_ef10_filter_insert(efx
, &spec
, true);
4364 netif_warn(efx
, drv
, efx
->net_dev
,
4365 "Broadcast filter insert failed rc=%d\n", rc
);
4366 /* Fall back to promiscuous */
4367 for (j
= 0; j
< i
; j
++) {
4368 efx_ef10_filter_remove_unsafe(
4369 efx
, EFX_FILTER_PRI_AUTO
,
4371 ids
[j
] = EFX_EF10_FILTER_ID_INVALID
;
4375 EFX_WARN_ON_PARANOID(vlan
->bcast
!=
4376 EFX_EF10_FILTER_ID_INVALID
);
4377 vlan
->bcast
= efx_ef10_filter_get_unsafe_id(efx
, rc
);
4384 static int efx_ef10_filter_insert_def(struct efx_nic
*efx
,
4385 struct efx_ef10_filter_vlan
*vlan
,
4386 bool multicast
, bool rollback
)
4388 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
4389 enum efx_filter_flags filter_flags
;
4390 struct efx_filter_spec spec
;
4394 filter_flags
= efx_rss_enabled(efx
) ? EFX_FILTER_FLAG_RX_RSS
: 0;
4396 efx_filter_init_rx(&spec
, EFX_FILTER_PRI_AUTO
, filter_flags
, 0);
4399 efx_filter_set_mc_def(&spec
);
4401 efx_filter_set_uc_def(&spec
);
4403 if (vlan
->vid
!= EFX_FILTER_VID_UNSPEC
)
4404 efx_filter_set_eth_local(&spec
, vlan
->vid
, NULL
);
4406 rc
= efx_ef10_filter_insert(efx
, &spec
, true);
4408 netif_printk(efx
, drv
, rc
== -EPERM
? KERN_DEBUG
: KERN_WARNING
,
4410 "%scast mismatch filter insert failed rc=%d\n",
4411 multicast
? "Multi" : "Uni", rc
);
4412 } else if (multicast
) {
4413 EFX_WARN_ON_PARANOID(vlan
->mcdef
!= EFX_EF10_FILTER_ID_INVALID
);
4414 vlan
->mcdef
= efx_ef10_filter_get_unsafe_id(efx
, rc
);
4415 if (!nic_data
->workaround_26807
) {
4416 /* Also need an Ethernet broadcast filter */
4417 efx_filter_init_rx(&spec
, EFX_FILTER_PRI_AUTO
,
4419 eth_broadcast_addr(baddr
);
4420 efx_filter_set_eth_local(&spec
, vlan
->vid
, baddr
);
4421 rc
= efx_ef10_filter_insert(efx
, &spec
, true);
4423 netif_warn(efx
, drv
, efx
->net_dev
,
4424 "Broadcast filter insert failed rc=%d\n",
4427 /* Roll back the mc_def filter */
4428 efx_ef10_filter_remove_unsafe(
4429 efx
, EFX_FILTER_PRI_AUTO
,
4431 vlan
->mcdef
= EFX_EF10_FILTER_ID_INVALID
;
4435 EFX_WARN_ON_PARANOID(vlan
->bcast
!=
4436 EFX_EF10_FILTER_ID_INVALID
);
4437 vlan
->bcast
= efx_ef10_filter_get_unsafe_id(efx
, rc
);
4442 EFX_WARN_ON_PARANOID(vlan
->ucdef
!= EFX_EF10_FILTER_ID_INVALID
);
4449 /* Remove filters that weren't renewed. Since nothing else changes the AUTO_OLD
4450 * flag or removes these filters, we don't need to hold the filter_lock while
4451 * scanning for these filters.
4453 static void efx_ef10_filter_remove_old(struct efx_nic
*efx
)
4455 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4456 int remove_failed
= 0;
4457 int remove_noent
= 0;
4461 for (i
= 0; i
< HUNT_FILTER_TBL_ROWS
; i
++) {
4462 if (ACCESS_ONCE(table
->entry
[i
].spec
) &
4463 EFX_EF10_FILTER_FLAG_AUTO_OLD
) {
4464 rc
= efx_ef10_filter_remove_internal(efx
,
4465 1U << EFX_FILTER_PRI_AUTO
, i
, true);
4474 netif_info(efx
, drv
, efx
->net_dev
,
4475 "%s: failed to remove %d filters\n",
4476 __func__
, remove_failed
);
4478 netif_info(efx
, drv
, efx
->net_dev
,
4479 "%s: failed to remove %d non-existent filters\n",
4480 __func__
, remove_noent
);
4483 static int efx_ef10_vport_set_mac_address(struct efx_nic
*efx
)
4485 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
4486 u8 mac_old
[ETH_ALEN
];
4489 /* Only reconfigure a PF-created vport */
4490 if (is_zero_ether_addr(nic_data
->vport_mac
))
4493 efx_device_detach_sync(efx
);
4494 efx_net_stop(efx
->net_dev
);
4495 down_write(&efx
->filter_sem
);
4496 efx_ef10_filter_table_remove(efx
);
4497 up_write(&efx
->filter_sem
);
4499 rc
= efx_ef10_vadaptor_free(efx
, nic_data
->vport_id
);
4501 goto restore_filters
;
4503 ether_addr_copy(mac_old
, nic_data
->vport_mac
);
4504 rc
= efx_ef10_vport_del_mac(efx
, nic_data
->vport_id
,
4505 nic_data
->vport_mac
);
4507 goto restore_vadaptor
;
4509 rc
= efx_ef10_vport_add_mac(efx
, nic_data
->vport_id
,
4510 efx
->net_dev
->dev_addr
);
4512 ether_addr_copy(nic_data
->vport_mac
, efx
->net_dev
->dev_addr
);
4514 rc2
= efx_ef10_vport_add_mac(efx
, nic_data
->vport_id
, mac_old
);
4516 /* Failed to add original MAC, so clear vport_mac */
4517 eth_zero_addr(nic_data
->vport_mac
);
4523 rc2
= efx_ef10_vadaptor_alloc(efx
, nic_data
->vport_id
);
4527 down_write(&efx
->filter_sem
);
4528 rc2
= efx_ef10_filter_table_probe(efx
);
4529 up_write(&efx
->filter_sem
);
4533 rc2
= efx_net_open(efx
->net_dev
);
4537 netif_device_attach(efx
->net_dev
);
4542 netif_err(efx
, drv
, efx
->net_dev
,
4543 "Failed to restore when changing MAC address - scheduling reset\n");
4544 efx_schedule_reset(efx
, RESET_TYPE_DATAPATH
);
4546 return rc
? rc
: rc2
;
4549 /* Caller must hold efx->filter_sem for read if race against
4550 * efx_ef10_filter_table_remove() is possible
4552 static void efx_ef10_filter_vlan_sync_rx_mode(struct efx_nic
*efx
,
4553 struct efx_ef10_filter_vlan
*vlan
)
4555 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4556 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
4558 /* Do not install unspecified VID if VLAN filtering is enabled.
4559 * Do not install all specified VIDs if VLAN filtering is disabled.
4561 if ((vlan
->vid
== EFX_FILTER_VID_UNSPEC
) == table
->vlan_filter
)
4564 /* Insert/renew unicast filters */
4565 if (table
->uc_promisc
) {
4566 efx_ef10_filter_insert_def(efx
, vlan
, false, false);
4567 efx_ef10_filter_insert_addr_list(efx
, vlan
, false, false);
4569 /* If any of the filters failed to insert, fall back to
4570 * promiscuous mode - add in the uc_def filter. But keep
4571 * our individual unicast filters.
4573 if (efx_ef10_filter_insert_addr_list(efx
, vlan
, false, false))
4574 efx_ef10_filter_insert_def(efx
, vlan
, false, false);
4577 /* Insert/renew multicast filters */
4578 /* If changing promiscuous state with cascaded multicast filters, remove
4579 * old filters first, so that packets are dropped rather than duplicated
4581 if (nic_data
->workaround_26807
&&
4582 table
->mc_promisc_last
!= table
->mc_promisc
)
4583 efx_ef10_filter_remove_old(efx
);
4584 if (table
->mc_promisc
) {
4585 if (nic_data
->workaround_26807
) {
4586 /* If we failed to insert promiscuous filters, rollback
4587 * and fall back to individual multicast filters
4589 if (efx_ef10_filter_insert_def(efx
, vlan
, true, true)) {
4590 /* Changing promisc state, so remove old filters */
4591 efx_ef10_filter_remove_old(efx
);
4592 efx_ef10_filter_insert_addr_list(efx
, vlan
,
4596 /* If we failed to insert promiscuous filters, don't
4597 * rollback. Regardless, also insert the mc_list
4599 efx_ef10_filter_insert_def(efx
, vlan
, true, false);
4600 efx_ef10_filter_insert_addr_list(efx
, vlan
, true, false);
4603 /* If any filters failed to insert, rollback and fall back to
4604 * promiscuous mode - mc_def filter and maybe broadcast. If
4605 * that fails, roll back again and insert as many of our
4606 * individual multicast filters as we can.
4608 if (efx_ef10_filter_insert_addr_list(efx
, vlan
, true, true)) {
4609 /* Changing promisc state, so remove old filters */
4610 if (nic_data
->workaround_26807
)
4611 efx_ef10_filter_remove_old(efx
);
4612 if (efx_ef10_filter_insert_def(efx
, vlan
, true, true))
4613 efx_ef10_filter_insert_addr_list(efx
, vlan
,
4619 /* Caller must hold efx->filter_sem for read if race against
4620 * efx_ef10_filter_table_remove() is possible
4622 static void efx_ef10_filter_sync_rx_mode(struct efx_nic
*efx
)
4624 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4625 struct net_device
*net_dev
= efx
->net_dev
;
4626 struct efx_ef10_filter_vlan
*vlan
;
4629 if (!efx_dev_registered(efx
))
4635 efx_ef10_filter_mark_old(efx
);
4637 /* Copy/convert the address lists; add the primary station
4638 * address and broadcast address
4640 netif_addr_lock_bh(net_dev
);
4641 efx_ef10_filter_uc_addr_list(efx
);
4642 efx_ef10_filter_mc_addr_list(efx
);
4643 netif_addr_unlock_bh(net_dev
);
4645 /* If VLAN filtering changes, all old filters are finally removed.
4646 * Do it in advance to avoid conflicts for unicast untagged and
4647 * VLAN 0 tagged filters.
4649 vlan_filter
= !!(net_dev
->features
& NETIF_F_HW_VLAN_CTAG_FILTER
);
4650 if (table
->vlan_filter
!= vlan_filter
) {
4651 table
->vlan_filter
= vlan_filter
;
4652 efx_ef10_filter_remove_old(efx
);
4655 list_for_each_entry(vlan
, &table
->vlan_list
, list
)
4656 efx_ef10_filter_vlan_sync_rx_mode(efx
, vlan
);
4658 efx_ef10_filter_remove_old(efx
);
4659 table
->mc_promisc_last
= table
->mc_promisc
;
4662 static struct efx_ef10_filter_vlan
*efx_ef10_filter_find_vlan(struct efx_nic
*efx
, u16 vid
)
4664 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4665 struct efx_ef10_filter_vlan
*vlan
;
4667 WARN_ON(!rwsem_is_locked(&efx
->filter_sem
));
4669 list_for_each_entry(vlan
, &table
->vlan_list
, list
) {
4670 if (vlan
->vid
== vid
)
4677 static int efx_ef10_filter_add_vlan(struct efx_nic
*efx
, u16 vid
)
4679 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4680 struct efx_ef10_filter_vlan
*vlan
;
4683 if (!efx_rwsem_assert_write_locked(&efx
->filter_sem
))
4686 vlan
= efx_ef10_filter_find_vlan(efx
, vid
);
4687 if (WARN_ON(vlan
)) {
4688 netif_err(efx
, drv
, efx
->net_dev
,
4689 "VLAN %u already added\n", vid
);
4693 vlan
= kzalloc(sizeof(*vlan
), GFP_KERNEL
);
4699 for (i
= 0; i
< ARRAY_SIZE(vlan
->uc
); i
++)
4700 vlan
->uc
[i
] = EFX_EF10_FILTER_ID_INVALID
;
4701 for (i
= 0; i
< ARRAY_SIZE(vlan
->mc
); i
++)
4702 vlan
->mc
[i
] = EFX_EF10_FILTER_ID_INVALID
;
4703 vlan
->ucdef
= EFX_EF10_FILTER_ID_INVALID
;
4704 vlan
->bcast
= EFX_EF10_FILTER_ID_INVALID
;
4705 vlan
->mcdef
= EFX_EF10_FILTER_ID_INVALID
;
4707 list_add_tail(&vlan
->list
, &table
->vlan_list
);
4709 if (efx_dev_registered(efx
))
4710 efx_ef10_filter_vlan_sync_rx_mode(efx
, vlan
);
4715 static void efx_ef10_filter_del_vlan_internal(struct efx_nic
*efx
,
4716 struct efx_ef10_filter_vlan
*vlan
)
4720 /* See comment in efx_ef10_filter_table_remove() */
4721 if (!efx_rwsem_assert_write_locked(&efx
->filter_sem
))
4724 list_del(&vlan
->list
);
4726 for (i
= 0; i
< ARRAY_SIZE(vlan
->uc
); i
++)
4727 efx_ef10_filter_remove_unsafe(efx
, EFX_FILTER_PRI_AUTO
,
4729 for (i
= 0; i
< ARRAY_SIZE(vlan
->mc
); i
++)
4730 efx_ef10_filter_remove_unsafe(efx
, EFX_FILTER_PRI_AUTO
,
4732 efx_ef10_filter_remove_unsafe(efx
, EFX_FILTER_PRI_AUTO
, vlan
->ucdef
);
4733 efx_ef10_filter_remove_unsafe(efx
, EFX_FILTER_PRI_AUTO
, vlan
->bcast
);
4734 efx_ef10_filter_remove_unsafe(efx
, EFX_FILTER_PRI_AUTO
, vlan
->mcdef
);
4739 static void efx_ef10_filter_del_vlan(struct efx_nic
*efx
, u16 vid
)
4741 struct efx_ef10_filter_vlan
*vlan
;
4743 /* See comment in efx_ef10_filter_table_remove() */
4744 if (!efx_rwsem_assert_write_locked(&efx
->filter_sem
))
4747 vlan
= efx_ef10_filter_find_vlan(efx
, vid
);
4749 netif_err(efx
, drv
, efx
->net_dev
,
4750 "VLAN %u not found in filter state\n", vid
);
4754 efx_ef10_filter_del_vlan_internal(efx
, vlan
);
4757 static int efx_ef10_set_mac_address(struct efx_nic
*efx
)
4759 MCDI_DECLARE_BUF(inbuf
, MC_CMD_VADAPTOR_SET_MAC_IN_LEN
);
4760 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
4761 bool was_enabled
= efx
->port_enabled
;
4764 efx_device_detach_sync(efx
);
4765 efx_net_stop(efx
->net_dev
);
4767 mutex_lock(&efx
->mac_lock
);
4768 down_write(&efx
->filter_sem
);
4769 efx_ef10_filter_table_remove(efx
);
4771 ether_addr_copy(MCDI_PTR(inbuf
, VADAPTOR_SET_MAC_IN_MACADDR
),
4772 efx
->net_dev
->dev_addr
);
4773 MCDI_SET_DWORD(inbuf
, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID
,
4774 nic_data
->vport_id
);
4775 rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_VADAPTOR_SET_MAC
, inbuf
,
4776 sizeof(inbuf
), NULL
, 0, NULL
);
4778 efx_ef10_filter_table_probe(efx
);
4779 up_write(&efx
->filter_sem
);
4780 mutex_unlock(&efx
->mac_lock
);
4783 efx_net_open(efx
->net_dev
);
4784 netif_device_attach(efx
->net_dev
);
4786 #ifdef CONFIG_SFC_SRIOV
4787 if (efx
->pci_dev
->is_virtfn
&& efx
->pci_dev
->physfn
) {
4788 struct pci_dev
*pci_dev_pf
= efx
->pci_dev
->physfn
;
4791 struct efx_nic
*efx_pf
;
4793 /* Switch to PF and change MAC address on vport */
4794 efx_pf
= pci_get_drvdata(pci_dev_pf
);
4796 rc
= efx_ef10_sriov_set_vf_mac(efx_pf
,
4798 efx
->net_dev
->dev_addr
);
4800 struct efx_nic
*efx_pf
= pci_get_drvdata(pci_dev_pf
);
4801 struct efx_ef10_nic_data
*nic_data
= efx_pf
->nic_data
;
4804 /* MAC address successfully changed by VF (with MAC
4805 * spoofing) so update the parent PF if possible.
4807 for (i
= 0; i
< efx_pf
->vf_count
; ++i
) {
4808 struct ef10_vf
*vf
= nic_data
->vf
+ i
;
4810 if (vf
->efx
== efx
) {
4811 ether_addr_copy(vf
->mac
,
4812 efx
->net_dev
->dev_addr
);
4820 netif_err(efx
, drv
, efx
->net_dev
,
4821 "Cannot change MAC address; use sfboot to enable"
4822 " mac-spoofing on this interface\n");
4823 } else if (rc
== -ENOSYS
&& !efx_ef10_is_vf(efx
)) {
4824 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
4825 * fall-back to the method of changing the MAC address on the
4826 * vport. This only applies to PFs because such versions of
4827 * MCFW do not support VFs.
4829 rc
= efx_ef10_vport_set_mac_address(efx
);
4831 efx_mcdi_display_error(efx
, MC_CMD_VADAPTOR_SET_MAC
,
4832 sizeof(inbuf
), NULL
, 0, rc
);
4838 static int efx_ef10_mac_reconfigure(struct efx_nic
*efx
)
4840 efx_ef10_filter_sync_rx_mode(efx
);
4842 return efx_mcdi_set_mac(efx
);
4845 static int efx_ef10_mac_reconfigure_vf(struct efx_nic
*efx
)
4847 efx_ef10_filter_sync_rx_mode(efx
);
4852 static int efx_ef10_start_bist(struct efx_nic
*efx
, u32 bist_type
)
4854 MCDI_DECLARE_BUF(inbuf
, MC_CMD_START_BIST_IN_LEN
);
4856 MCDI_SET_DWORD(inbuf
, START_BIST_IN_TYPE
, bist_type
);
4857 return efx_mcdi_rpc(efx
, MC_CMD_START_BIST
, inbuf
, sizeof(inbuf
),
4861 /* MC BISTs follow a different poll mechanism to phy BISTs.
4862 * The BIST is done in the poll handler on the MC, and the MCDI command
4863 * will block until the BIST is done.
4865 static int efx_ef10_poll_bist(struct efx_nic
*efx
)
4868 MCDI_DECLARE_BUF(outbuf
, MC_CMD_POLL_BIST_OUT_LEN
);
4872 rc
= efx_mcdi_rpc(efx
, MC_CMD_POLL_BIST
, NULL
, 0,
4873 outbuf
, sizeof(outbuf
), &outlen
);
4877 if (outlen
< MC_CMD_POLL_BIST_OUT_LEN
)
4880 result
= MCDI_DWORD(outbuf
, POLL_BIST_OUT_RESULT
);
4882 case MC_CMD_POLL_BIST_PASSED
:
4883 netif_dbg(efx
, hw
, efx
->net_dev
, "BIST passed.\n");
4885 case MC_CMD_POLL_BIST_TIMEOUT
:
4886 netif_err(efx
, hw
, efx
->net_dev
, "BIST timed out\n");
4888 case MC_CMD_POLL_BIST_FAILED
:
4889 netif_err(efx
, hw
, efx
->net_dev
, "BIST failed.\n");
4892 netif_err(efx
, hw
, efx
->net_dev
,
4893 "BIST returned unknown result %u", result
);
4898 static int efx_ef10_run_bist(struct efx_nic
*efx
, u32 bist_type
)
4902 netif_dbg(efx
, drv
, efx
->net_dev
, "starting BIST type %u\n", bist_type
);
4904 rc
= efx_ef10_start_bist(efx
, bist_type
);
4908 return efx_ef10_poll_bist(efx
);
4912 efx_ef10_test_chip(struct efx_nic
*efx
, struct efx_self_tests
*tests
)
4916 efx_reset_down(efx
, RESET_TYPE_WORLD
);
4918 rc
= efx_mcdi_rpc(efx
, MC_CMD_ENABLE_OFFLINE_BIST
,
4919 NULL
, 0, NULL
, 0, NULL
);
4923 tests
->memory
= efx_ef10_run_bist(efx
, MC_CMD_MC_MEM_BIST
) ? -1 : 1;
4924 tests
->registers
= efx_ef10_run_bist(efx
, MC_CMD_REG_BIST
) ? -1 : 1;
4926 rc
= efx_mcdi_reset(efx
, RESET_TYPE_WORLD
);
4931 rc2
= efx_reset_up(efx
, RESET_TYPE_WORLD
, rc
== 0);
4932 return rc
? rc
: rc2
;
4935 #ifdef CONFIG_SFC_MTD
4937 struct efx_ef10_nvram_type_info
{
4938 u16 type
, type_mask
;
4943 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types
[] = {
4944 { NVRAM_PARTITION_TYPE_MC_FIRMWARE
, 0, 0, "sfc_mcfw" },
4945 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP
, 0, 0, "sfc_mcfw_backup" },
4946 { NVRAM_PARTITION_TYPE_EXPANSION_ROM
, 0, 0, "sfc_exp_rom" },
4947 { NVRAM_PARTITION_TYPE_STATIC_CONFIG
, 0, 0, "sfc_static_cfg" },
4948 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG
, 0, 0, "sfc_dynamic_cfg" },
4949 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0
, 0, 0, "sfc_exp_rom_cfg" },
4950 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1
, 0, 1, "sfc_exp_rom_cfg" },
4951 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2
, 0, 2, "sfc_exp_rom_cfg" },
4952 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3
, 0, 3, "sfc_exp_rom_cfg" },
4953 { NVRAM_PARTITION_TYPE_LICENSE
, 0, 0, "sfc_license" },
4954 { NVRAM_PARTITION_TYPE_PHY_MIN
, 0xff, 0, "sfc_phy_fw" },
4957 static int efx_ef10_mtd_probe_partition(struct efx_nic
*efx
,
4958 struct efx_mcdi_mtd_partition
*part
,
4961 MCDI_DECLARE_BUF(inbuf
, MC_CMD_NVRAM_METADATA_IN_LEN
);
4962 MCDI_DECLARE_BUF(outbuf
, MC_CMD_NVRAM_METADATA_OUT_LENMAX
);
4963 const struct efx_ef10_nvram_type_info
*info
;
4964 size_t size
, erase_size
, outlen
;
4968 for (info
= efx_ef10_nvram_types
; ; info
++) {
4970 efx_ef10_nvram_types
+ ARRAY_SIZE(efx_ef10_nvram_types
))
4972 if ((type
& ~info
->type_mask
) == info
->type
)
4975 if (info
->port
!= efx_port_num(efx
))
4978 rc
= efx_mcdi_nvram_info(efx
, type
, &size
, &erase_size
, &protected);
4982 return -ENODEV
; /* hide it */
4984 part
->nvram_type
= type
;
4986 MCDI_SET_DWORD(inbuf
, NVRAM_METADATA_IN_TYPE
, type
);
4987 rc
= efx_mcdi_rpc(efx
, MC_CMD_NVRAM_METADATA
, inbuf
, sizeof(inbuf
),
4988 outbuf
, sizeof(outbuf
), &outlen
);
4991 if (outlen
< MC_CMD_NVRAM_METADATA_OUT_LENMIN
)
4993 if (MCDI_DWORD(outbuf
, NVRAM_METADATA_OUT_FLAGS
) &
4994 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN
))
4995 part
->fw_subtype
= MCDI_DWORD(outbuf
,
4996 NVRAM_METADATA_OUT_SUBTYPE
);
4998 part
->common
.dev_type_name
= "EF10 NVRAM manager";
4999 part
->common
.type_name
= info
->name
;
5001 part
->common
.mtd
.type
= MTD_NORFLASH
;
5002 part
->common
.mtd
.flags
= MTD_CAP_NORFLASH
;
5003 part
->common
.mtd
.size
= size
;
5004 part
->common
.mtd
.erasesize
= erase_size
;
5009 static int efx_ef10_mtd_probe(struct efx_nic
*efx
)
5011 MCDI_DECLARE_BUF(outbuf
, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX
);
5012 struct efx_mcdi_mtd_partition
*parts
;
5013 size_t outlen
, n_parts_total
, i
, n_parts
;
5019 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN
!= 0);
5020 rc
= efx_mcdi_rpc(efx
, MC_CMD_NVRAM_PARTITIONS
, NULL
, 0,
5021 outbuf
, sizeof(outbuf
), &outlen
);
5024 if (outlen
< MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN
)
5027 n_parts_total
= MCDI_DWORD(outbuf
, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS
);
5029 MCDI_VAR_ARRAY_LEN(outlen
, NVRAM_PARTITIONS_OUT_TYPE_ID
))
5032 parts
= kcalloc(n_parts_total
, sizeof(*parts
), GFP_KERNEL
);
5037 for (i
= 0; i
< n_parts_total
; i
++) {
5038 type
= MCDI_ARRAY_DWORD(outbuf
, NVRAM_PARTITIONS_OUT_TYPE_ID
,
5040 rc
= efx_ef10_mtd_probe_partition(efx
, &parts
[n_parts
], type
);
5043 else if (rc
!= -ENODEV
)
5047 rc
= efx_mtd_add(efx
, &parts
[0].common
, n_parts
, sizeof(*parts
));
5054 #endif /* CONFIG_SFC_MTD */
5056 static void efx_ef10_ptp_write_host_time(struct efx_nic
*efx
, u32 host_time
)
5058 _efx_writed(efx
, cpu_to_le32(host_time
), ER_DZ_MC_DB_LWRD
);
5061 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic
*efx
,
5064 static int efx_ef10_rx_enable_timestamping(struct efx_channel
*channel
,
5067 MCDI_DECLARE_BUF(inbuf
, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN
);
5070 if (channel
->sync_events_state
== SYNC_EVENTS_REQUESTED
||
5071 channel
->sync_events_state
== SYNC_EVENTS_VALID
||
5072 (temp
&& channel
->sync_events_state
== SYNC_EVENTS_DISABLED
))
5074 channel
->sync_events_state
= SYNC_EVENTS_REQUESTED
;
5076 MCDI_SET_DWORD(inbuf
, PTP_IN_OP
, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE
);
5077 MCDI_SET_DWORD(inbuf
, PTP_IN_PERIPH_ID
, 0);
5078 MCDI_SET_DWORD(inbuf
, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE
,
5081 rc
= efx_mcdi_rpc(channel
->efx
, MC_CMD_PTP
,
5082 inbuf
, sizeof(inbuf
), NULL
, 0, NULL
);
5085 channel
->sync_events_state
= temp
? SYNC_EVENTS_QUIESCENT
:
5086 SYNC_EVENTS_DISABLED
;
5091 static int efx_ef10_rx_disable_timestamping(struct efx_channel
*channel
,
5094 MCDI_DECLARE_BUF(inbuf
, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN
);
5097 if (channel
->sync_events_state
== SYNC_EVENTS_DISABLED
||
5098 (temp
&& channel
->sync_events_state
== SYNC_EVENTS_QUIESCENT
))
5100 if (channel
->sync_events_state
== SYNC_EVENTS_QUIESCENT
) {
5101 channel
->sync_events_state
= SYNC_EVENTS_DISABLED
;
5104 channel
->sync_events_state
= temp
? SYNC_EVENTS_QUIESCENT
:
5105 SYNC_EVENTS_DISABLED
;
5107 MCDI_SET_DWORD(inbuf
, PTP_IN_OP
, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE
);
5108 MCDI_SET_DWORD(inbuf
, PTP_IN_PERIPH_ID
, 0);
5109 MCDI_SET_DWORD(inbuf
, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL
,
5110 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE
);
5111 MCDI_SET_DWORD(inbuf
, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE
,
5114 rc
= efx_mcdi_rpc(channel
->efx
, MC_CMD_PTP
,
5115 inbuf
, sizeof(inbuf
), NULL
, 0, NULL
);
5120 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic
*efx
, bool en
,
5123 int (*set
)(struct efx_channel
*channel
, bool temp
);
5124 struct efx_channel
*channel
;
5127 efx_ef10_rx_enable_timestamping
:
5128 efx_ef10_rx_disable_timestamping
;
5130 efx_for_each_channel(channel
, efx
) {
5131 int rc
= set(channel
, temp
);
5132 if (en
&& rc
!= 0) {
5133 efx_ef10_ptp_set_ts_sync_events(efx
, false, temp
);
5141 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic
*efx
,
5142 struct hwtstamp_config
*init
)
5147 static int efx_ef10_ptp_set_ts_config(struct efx_nic
*efx
,
5148 struct hwtstamp_config
*init
)
5152 switch (init
->rx_filter
) {
5153 case HWTSTAMP_FILTER_NONE
:
5154 efx_ef10_ptp_set_ts_sync_events(efx
, false, false);
5155 /* if TX timestamping is still requested then leave PTP on */
5156 return efx_ptp_change_mode(efx
,
5157 init
->tx_type
!= HWTSTAMP_TX_OFF
, 0);
5158 case HWTSTAMP_FILTER_ALL
:
5159 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
5160 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
5161 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
5162 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
5163 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
5164 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
5165 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT
:
5166 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC
:
5167 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ
:
5168 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
5169 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
5170 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
5171 init
->rx_filter
= HWTSTAMP_FILTER_ALL
;
5172 rc
= efx_ptp_change_mode(efx
, true, 0);
5174 rc
= efx_ef10_ptp_set_ts_sync_events(efx
, true, false);
5176 efx_ptp_change_mode(efx
, false, 0);
5183 static int efx_ef10_vlan_rx_add_vid(struct efx_nic
*efx
, __be16 proto
, u16 vid
)
5185 if (proto
!= htons(ETH_P_8021Q
))
5188 return efx_ef10_add_vlan(efx
, vid
);
5191 static int efx_ef10_vlan_rx_kill_vid(struct efx_nic
*efx
, __be16 proto
, u16 vid
)
5193 if (proto
!= htons(ETH_P_8021Q
))
5196 return efx_ef10_del_vlan(efx
, vid
);
5199 #define EF10_OFFLOAD_FEATURES \
5200 (NETIF_F_IP_CSUM | \
5201 NETIF_F_HW_VLAN_CTAG_FILTER | \
5202 NETIF_F_IPV6_CSUM | \
5206 const struct efx_nic_type efx_hunt_a0_vf_nic_type
= {
5208 .mem_bar
= EFX_MEM_VF_BAR
,
5209 .mem_map_size
= efx_ef10_mem_map_size
,
5210 .probe
= efx_ef10_probe_vf
,
5211 .remove
= efx_ef10_remove
,
5212 .dimension_resources
= efx_ef10_dimension_resources
,
5213 .init
= efx_ef10_init_nic
,
5214 .fini
= efx_port_dummy_op_void
,
5215 .map_reset_reason
= efx_ef10_map_reset_reason
,
5216 .map_reset_flags
= efx_ef10_map_reset_flags
,
5217 .reset
= efx_ef10_reset
,
5218 .probe_port
= efx_mcdi_port_probe
,
5219 .remove_port
= efx_mcdi_port_remove
,
5220 .fini_dmaq
= efx_ef10_fini_dmaq
,
5221 .prepare_flr
= efx_ef10_prepare_flr
,
5222 .finish_flr
= efx_port_dummy_op_void
,
5223 .describe_stats
= efx_ef10_describe_stats
,
5224 .update_stats
= efx_ef10_update_stats_vf
,
5225 .start_stats
= efx_port_dummy_op_void
,
5226 .pull_stats
= efx_port_dummy_op_void
,
5227 .stop_stats
= efx_port_dummy_op_void
,
5228 .set_id_led
= efx_mcdi_set_id_led
,
5229 .push_irq_moderation
= efx_ef10_push_irq_moderation
,
5230 .reconfigure_mac
= efx_ef10_mac_reconfigure_vf
,
5231 .check_mac_fault
= efx_mcdi_mac_check_fault
,
5232 .reconfigure_port
= efx_mcdi_port_reconfigure
,
5233 .get_wol
= efx_ef10_get_wol_vf
,
5234 .set_wol
= efx_ef10_set_wol_vf
,
5235 .resume_wol
= efx_port_dummy_op_void
,
5236 .mcdi_request
= efx_ef10_mcdi_request
,
5237 .mcdi_poll_response
= efx_ef10_mcdi_poll_response
,
5238 .mcdi_read_response
= efx_ef10_mcdi_read_response
,
5239 .mcdi_poll_reboot
= efx_ef10_mcdi_poll_reboot
,
5240 .mcdi_reboot_detected
= efx_ef10_mcdi_reboot_detected
,
5241 .irq_enable_master
= efx_port_dummy_op_void
,
5242 .irq_test_generate
= efx_ef10_irq_test_generate
,
5243 .irq_disable_non_ev
= efx_port_dummy_op_void
,
5244 .irq_handle_msi
= efx_ef10_msi_interrupt
,
5245 .irq_handle_legacy
= efx_ef10_legacy_interrupt
,
5246 .tx_probe
= efx_ef10_tx_probe
,
5247 .tx_init
= efx_ef10_tx_init
,
5248 .tx_remove
= efx_ef10_tx_remove
,
5249 .tx_write
= efx_ef10_tx_write
,
5250 .rx_push_rss_config
= efx_ef10_vf_rx_push_rss_config
,
5251 .rx_probe
= efx_ef10_rx_probe
,
5252 .rx_init
= efx_ef10_rx_init
,
5253 .rx_remove
= efx_ef10_rx_remove
,
5254 .rx_write
= efx_ef10_rx_write
,
5255 .rx_defer_refill
= efx_ef10_rx_defer_refill
,
5256 .ev_probe
= efx_ef10_ev_probe
,
5257 .ev_init
= efx_ef10_ev_init
,
5258 .ev_fini
= efx_ef10_ev_fini
,
5259 .ev_remove
= efx_ef10_ev_remove
,
5260 .ev_process
= efx_ef10_ev_process
,
5261 .ev_read_ack
= efx_ef10_ev_read_ack
,
5262 .ev_test_generate
= efx_ef10_ev_test_generate
,
5263 .filter_table_probe
= efx_ef10_filter_table_probe
,
5264 .filter_table_restore
= efx_ef10_filter_table_restore
,
5265 .filter_table_remove
= efx_ef10_filter_table_remove
,
5266 .filter_update_rx_scatter
= efx_ef10_filter_update_rx_scatter
,
5267 .filter_insert
= efx_ef10_filter_insert
,
5268 .filter_remove_safe
= efx_ef10_filter_remove_safe
,
5269 .filter_get_safe
= efx_ef10_filter_get_safe
,
5270 .filter_clear_rx
= efx_ef10_filter_clear_rx
,
5271 .filter_count_rx_used
= efx_ef10_filter_count_rx_used
,
5272 .filter_get_rx_id_limit
= efx_ef10_filter_get_rx_id_limit
,
5273 .filter_get_rx_ids
= efx_ef10_filter_get_rx_ids
,
5274 #ifdef CONFIG_RFS_ACCEL
5275 .filter_rfs_insert
= efx_ef10_filter_rfs_insert
,
5276 .filter_rfs_expire_one
= efx_ef10_filter_rfs_expire_one
,
5278 #ifdef CONFIG_SFC_MTD
5279 .mtd_probe
= efx_port_dummy_op_int
,
5281 .ptp_write_host_time
= efx_ef10_ptp_write_host_time_vf
,
5282 .ptp_set_ts_config
= efx_ef10_ptp_set_ts_config_vf
,
5283 .vlan_rx_add_vid
= efx_ef10_vlan_rx_add_vid
,
5284 .vlan_rx_kill_vid
= efx_ef10_vlan_rx_kill_vid
,
5285 #ifdef CONFIG_SFC_SRIOV
5286 .vswitching_probe
= efx_ef10_vswitching_probe_vf
,
5287 .vswitching_restore
= efx_ef10_vswitching_restore_vf
,
5288 .vswitching_remove
= efx_ef10_vswitching_remove_vf
,
5289 .sriov_get_phys_port_id
= efx_ef10_sriov_get_phys_port_id
,
5291 .get_mac_address
= efx_ef10_get_mac_address_vf
,
5292 .set_mac_address
= efx_ef10_set_mac_address
,
5294 .revision
= EFX_REV_HUNT_A0
,
5295 .max_dma_mask
= DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH
),
5296 .rx_prefix_size
= ES_DZ_RX_PREFIX_SIZE
,
5297 .rx_hash_offset
= ES_DZ_RX_PREFIX_HASH_OFST
,
5298 .rx_ts_offset
= ES_DZ_RX_PREFIX_TSTAMP_OFST
,
5299 .can_rx_scatter
= true,
5300 .always_rx_scatter
= true,
5301 .max_interrupt_mode
= EFX_INT_MODE_MSIX
,
5302 .timer_period_max
= 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH
,
5303 .offload_features
= EF10_OFFLOAD_FEATURES
,
5305 .max_rx_ip_filters
= HUNT_FILTER_TBL_ROWS
,
5306 .hwtstamp_filters
= 1 << HWTSTAMP_FILTER_NONE
|
5307 1 << HWTSTAMP_FILTER_ALL
,
5310 const struct efx_nic_type efx_hunt_a0_nic_type
= {
5312 .mem_bar
= EFX_MEM_BAR
,
5313 .mem_map_size
= efx_ef10_mem_map_size
,
5314 .probe
= efx_ef10_probe_pf
,
5315 .remove
= efx_ef10_remove
,
5316 .dimension_resources
= efx_ef10_dimension_resources
,
5317 .init
= efx_ef10_init_nic
,
5318 .fini
= efx_port_dummy_op_void
,
5319 .map_reset_reason
= efx_ef10_map_reset_reason
,
5320 .map_reset_flags
= efx_ef10_map_reset_flags
,
5321 .reset
= efx_ef10_reset
,
5322 .probe_port
= efx_mcdi_port_probe
,
5323 .remove_port
= efx_mcdi_port_remove
,
5324 .fini_dmaq
= efx_ef10_fini_dmaq
,
5325 .prepare_flr
= efx_ef10_prepare_flr
,
5326 .finish_flr
= efx_port_dummy_op_void
,
5327 .describe_stats
= efx_ef10_describe_stats
,
5328 .update_stats
= efx_ef10_update_stats_pf
,
5329 .start_stats
= efx_mcdi_mac_start_stats
,
5330 .pull_stats
= efx_mcdi_mac_pull_stats
,
5331 .stop_stats
= efx_mcdi_mac_stop_stats
,
5332 .set_id_led
= efx_mcdi_set_id_led
,
5333 .push_irq_moderation
= efx_ef10_push_irq_moderation
,
5334 .reconfigure_mac
= efx_ef10_mac_reconfigure
,
5335 .check_mac_fault
= efx_mcdi_mac_check_fault
,
5336 .reconfigure_port
= efx_mcdi_port_reconfigure
,
5337 .get_wol
= efx_ef10_get_wol
,
5338 .set_wol
= efx_ef10_set_wol
,
5339 .resume_wol
= efx_port_dummy_op_void
,
5340 .test_chip
= efx_ef10_test_chip
,
5341 .test_nvram
= efx_mcdi_nvram_test_all
,
5342 .mcdi_request
= efx_ef10_mcdi_request
,
5343 .mcdi_poll_response
= efx_ef10_mcdi_poll_response
,
5344 .mcdi_read_response
= efx_ef10_mcdi_read_response
,
5345 .mcdi_poll_reboot
= efx_ef10_mcdi_poll_reboot
,
5346 .mcdi_reboot_detected
= efx_ef10_mcdi_reboot_detected
,
5347 .irq_enable_master
= efx_port_dummy_op_void
,
5348 .irq_test_generate
= efx_ef10_irq_test_generate
,
5349 .irq_disable_non_ev
= efx_port_dummy_op_void
,
5350 .irq_handle_msi
= efx_ef10_msi_interrupt
,
5351 .irq_handle_legacy
= efx_ef10_legacy_interrupt
,
5352 .tx_probe
= efx_ef10_tx_probe
,
5353 .tx_init
= efx_ef10_tx_init
,
5354 .tx_remove
= efx_ef10_tx_remove
,
5355 .tx_write
= efx_ef10_tx_write
,
5356 .rx_push_rss_config
= efx_ef10_pf_rx_push_rss_config
,
5357 .rx_probe
= efx_ef10_rx_probe
,
5358 .rx_init
= efx_ef10_rx_init
,
5359 .rx_remove
= efx_ef10_rx_remove
,
5360 .rx_write
= efx_ef10_rx_write
,
5361 .rx_defer_refill
= efx_ef10_rx_defer_refill
,
5362 .ev_probe
= efx_ef10_ev_probe
,
5363 .ev_init
= efx_ef10_ev_init
,
5364 .ev_fini
= efx_ef10_ev_fini
,
5365 .ev_remove
= efx_ef10_ev_remove
,
5366 .ev_process
= efx_ef10_ev_process
,
5367 .ev_read_ack
= efx_ef10_ev_read_ack
,
5368 .ev_test_generate
= efx_ef10_ev_test_generate
,
5369 .filter_table_probe
= efx_ef10_filter_table_probe
,
5370 .filter_table_restore
= efx_ef10_filter_table_restore
,
5371 .filter_table_remove
= efx_ef10_filter_table_remove
,
5372 .filter_update_rx_scatter
= efx_ef10_filter_update_rx_scatter
,
5373 .filter_insert
= efx_ef10_filter_insert
,
5374 .filter_remove_safe
= efx_ef10_filter_remove_safe
,
5375 .filter_get_safe
= efx_ef10_filter_get_safe
,
5376 .filter_clear_rx
= efx_ef10_filter_clear_rx
,
5377 .filter_count_rx_used
= efx_ef10_filter_count_rx_used
,
5378 .filter_get_rx_id_limit
= efx_ef10_filter_get_rx_id_limit
,
5379 .filter_get_rx_ids
= efx_ef10_filter_get_rx_ids
,
5380 #ifdef CONFIG_RFS_ACCEL
5381 .filter_rfs_insert
= efx_ef10_filter_rfs_insert
,
5382 .filter_rfs_expire_one
= efx_ef10_filter_rfs_expire_one
,
5384 #ifdef CONFIG_SFC_MTD
5385 .mtd_probe
= efx_ef10_mtd_probe
,
5386 .mtd_rename
= efx_mcdi_mtd_rename
,
5387 .mtd_read
= efx_mcdi_mtd_read
,
5388 .mtd_erase
= efx_mcdi_mtd_erase
,
5389 .mtd_write
= efx_mcdi_mtd_write
,
5390 .mtd_sync
= efx_mcdi_mtd_sync
,
5392 .ptp_write_host_time
= efx_ef10_ptp_write_host_time
,
5393 .ptp_set_ts_sync_events
= efx_ef10_ptp_set_ts_sync_events
,
5394 .ptp_set_ts_config
= efx_ef10_ptp_set_ts_config
,
5395 .vlan_rx_add_vid
= efx_ef10_vlan_rx_add_vid
,
5396 .vlan_rx_kill_vid
= efx_ef10_vlan_rx_kill_vid
,
5397 #ifdef CONFIG_SFC_SRIOV
5398 .sriov_configure
= efx_ef10_sriov_configure
,
5399 .sriov_init
= efx_ef10_sriov_init
,
5400 .sriov_fini
= efx_ef10_sriov_fini
,
5401 .sriov_wanted
= efx_ef10_sriov_wanted
,
5402 .sriov_reset
= efx_ef10_sriov_reset
,
5403 .sriov_flr
= efx_ef10_sriov_flr
,
5404 .sriov_set_vf_mac
= efx_ef10_sriov_set_vf_mac
,
5405 .sriov_set_vf_vlan
= efx_ef10_sriov_set_vf_vlan
,
5406 .sriov_set_vf_spoofchk
= efx_ef10_sriov_set_vf_spoofchk
,
5407 .sriov_get_vf_config
= efx_ef10_sriov_get_vf_config
,
5408 .sriov_set_vf_link_state
= efx_ef10_sriov_set_vf_link_state
,
5409 .vswitching_probe
= efx_ef10_vswitching_probe_pf
,
5410 .vswitching_restore
= efx_ef10_vswitching_restore_pf
,
5411 .vswitching_remove
= efx_ef10_vswitching_remove_pf
,
5413 .get_mac_address
= efx_ef10_get_mac_address_pf
,
5414 .set_mac_address
= efx_ef10_set_mac_address
,
5416 .revision
= EFX_REV_HUNT_A0
,
5417 .max_dma_mask
= DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH
),
5418 .rx_prefix_size
= ES_DZ_RX_PREFIX_SIZE
,
5419 .rx_hash_offset
= ES_DZ_RX_PREFIX_HASH_OFST
,
5420 .rx_ts_offset
= ES_DZ_RX_PREFIX_TSTAMP_OFST
,
5421 .can_rx_scatter
= true,
5422 .always_rx_scatter
= true,
5423 .max_interrupt_mode
= EFX_INT_MODE_MSIX
,
5424 .timer_period_max
= 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH
,
5425 .offload_features
= EF10_OFFLOAD_FEATURES
,
5427 .max_rx_ip_filters
= HUNT_FILTER_TBL_ROWS
,
5428 .hwtstamp_filters
= 1 << HWTSTAMP_FILTER_NONE
|
5429 1 << HWTSTAMP_FILTER_ALL
,