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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / sfc / nic.c
1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2013 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/interrupt.h>
14 #include <linux/pci.h>
15 #include <linux/module.h>
16 #include <linux/seq_file.h>
17 #include <linux/cpu_rmap.h>
18 #include "net_driver.h"
19 #include "bitfield.h"
20 #include "efx.h"
21 #include "nic.h"
22 #include "ef10_regs.h"
23 #include "farch_regs.h"
24 #include "io.h"
25 #include "workarounds.h"
26
27 /**************************************************************************
28 *
29 * Generic buffer handling
30 * These buffers are used for interrupt status, MAC stats, etc.
31 *
32 **************************************************************************/
33
34 int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
35 unsigned int len, gfp_t gfp_flags)
36 {
37 buffer->addr = dma_zalloc_coherent(&efx->pci_dev->dev, len,
38 &buffer->dma_addr, gfp_flags);
39 if (!buffer->addr)
40 return -ENOMEM;
41 buffer->len = len;
42 return 0;
43 }
44
45 void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
46 {
47 if (buffer->addr) {
48 dma_free_coherent(&efx->pci_dev->dev, buffer->len,
49 buffer->addr, buffer->dma_addr);
50 buffer->addr = NULL;
51 }
52 }
53
54 /* Check whether an event is present in the eventq at the current
55 * read pointer. Only useful for self-test.
56 */
57 bool efx_nic_event_present(struct efx_channel *channel)
58 {
59 return efx_event_present(efx_event(channel, channel->eventq_read_ptr));
60 }
61
62 void efx_nic_event_test_start(struct efx_channel *channel)
63 {
64 channel->event_test_cpu = -1;
65 smp_wmb();
66 channel->efx->type->ev_test_generate(channel);
67 }
68
69 void efx_nic_irq_test_start(struct efx_nic *efx)
70 {
71 efx->last_irq_cpu = -1;
72 smp_wmb();
73 efx->type->irq_test_generate(efx);
74 }
75
76 /* Hook interrupt handler(s)
77 * Try MSI and then legacy interrupts.
78 */
79 int efx_nic_init_interrupt(struct efx_nic *efx)
80 {
81 struct efx_channel *channel;
82 unsigned int n_irqs;
83 int rc;
84
85 if (!EFX_INT_MODE_USE_MSI(efx)) {
86 rc = request_irq(efx->legacy_irq,
87 efx->type->irq_handle_legacy, IRQF_SHARED,
88 efx->name, efx);
89 if (rc) {
90 netif_err(efx, drv, efx->net_dev,
91 "failed to hook legacy IRQ %d\n",
92 efx->pci_dev->irq);
93 goto fail1;
94 }
95 return 0;
96 }
97
98 #ifdef CONFIG_RFS_ACCEL
99 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
100 efx->net_dev->rx_cpu_rmap =
101 alloc_irq_cpu_rmap(efx->n_rx_channels);
102 if (!efx->net_dev->rx_cpu_rmap) {
103 rc = -ENOMEM;
104 goto fail1;
105 }
106 }
107 #endif
108
109 /* Hook MSI or MSI-X interrupt */
110 n_irqs = 0;
111 efx_for_each_channel(channel, efx) {
112 rc = request_irq(channel->irq, efx->type->irq_handle_msi,
113 IRQF_PROBE_SHARED, /* Not shared */
114 efx->msi_context[channel->channel].name,
115 &efx->msi_context[channel->channel]);
116 if (rc) {
117 netif_err(efx, drv, efx->net_dev,
118 "failed to hook IRQ %d\n", channel->irq);
119 goto fail2;
120 }
121 ++n_irqs;
122
123 #ifdef CONFIG_RFS_ACCEL
124 if (efx->interrupt_mode == EFX_INT_MODE_MSIX &&
125 channel->channel < efx->n_rx_channels) {
126 rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap,
127 channel->irq);
128 if (rc)
129 goto fail2;
130 }
131 #endif
132 }
133
134 return 0;
135
136 fail2:
137 #ifdef CONFIG_RFS_ACCEL
138 free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
139 efx->net_dev->rx_cpu_rmap = NULL;
140 #endif
141 efx_for_each_channel(channel, efx) {
142 if (n_irqs-- == 0)
143 break;
144 free_irq(channel->irq, &efx->msi_context[channel->channel]);
145 }
146 fail1:
147 return rc;
148 }
149
150 void efx_nic_fini_interrupt(struct efx_nic *efx)
151 {
152 struct efx_channel *channel;
153
154 #ifdef CONFIG_RFS_ACCEL
155 free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
156 efx->net_dev->rx_cpu_rmap = NULL;
157 #endif
158
159 /* Disable MSI/MSI-X interrupts */
160 efx_for_each_channel(channel, efx)
161 free_irq(channel->irq, &efx->msi_context[channel->channel]);
162
163 /* Disable legacy interrupt */
164 if (efx->legacy_irq)
165 free_irq(efx->legacy_irq, efx);
166 }
167
168 /* Register dump */
169
170 #define REGISTER_REVISION_FA 1
171 #define REGISTER_REVISION_FB 2
172 #define REGISTER_REVISION_FC 3
173 #define REGISTER_REVISION_FZ 3 /* last Falcon arch revision */
174 #define REGISTER_REVISION_ED 4
175 #define REGISTER_REVISION_EZ 4 /* latest EF10 revision */
176
177 struct efx_nic_reg {
178 u32 offset:24;
179 u32 min_revision:3, max_revision:3;
180 };
181
182 #define REGISTER(name, arch, min_rev, max_rev) { \
183 arch ## R_ ## min_rev ## max_rev ## _ ## name, \
184 REGISTER_REVISION_ ## arch ## min_rev, \
185 REGISTER_REVISION_ ## arch ## max_rev \
186 }
187 #define REGISTER_AA(name) REGISTER(name, F, A, A)
188 #define REGISTER_AB(name) REGISTER(name, F, A, B)
189 #define REGISTER_AZ(name) REGISTER(name, F, A, Z)
190 #define REGISTER_BB(name) REGISTER(name, F, B, B)
191 #define REGISTER_BZ(name) REGISTER(name, F, B, Z)
192 #define REGISTER_CZ(name) REGISTER(name, F, C, Z)
193 #define REGISTER_DZ(name) REGISTER(name, E, D, Z)
194
195 static const struct efx_nic_reg efx_nic_regs[] = {
196 REGISTER_AZ(ADR_REGION),
197 REGISTER_AZ(INT_EN_KER),
198 REGISTER_BZ(INT_EN_CHAR),
199 REGISTER_AZ(INT_ADR_KER),
200 REGISTER_BZ(INT_ADR_CHAR),
201 /* INT_ACK_KER is WO */
202 /* INT_ISR0 is RC */
203 REGISTER_AZ(HW_INIT),
204 REGISTER_CZ(USR_EV_CFG),
205 REGISTER_AB(EE_SPI_HCMD),
206 REGISTER_AB(EE_SPI_HADR),
207 REGISTER_AB(EE_SPI_HDATA),
208 REGISTER_AB(EE_BASE_PAGE),
209 REGISTER_AB(EE_VPD_CFG0),
210 /* EE_VPD_SW_CNTL and EE_VPD_SW_DATA are not used */
211 /* PMBX_DBG_IADDR and PBMX_DBG_IDATA are indirect */
212 /* PCIE_CORE_INDIRECT is indirect */
213 REGISTER_AB(NIC_STAT),
214 REGISTER_AB(GPIO_CTL),
215 REGISTER_AB(GLB_CTL),
216 /* FATAL_INTR_KER and FATAL_INTR_CHAR are partly RC */
217 REGISTER_BZ(DP_CTRL),
218 REGISTER_AZ(MEM_STAT),
219 REGISTER_AZ(CS_DEBUG),
220 REGISTER_AZ(ALTERA_BUILD),
221 REGISTER_AZ(CSR_SPARE),
222 REGISTER_AB(PCIE_SD_CTL0123),
223 REGISTER_AB(PCIE_SD_CTL45),
224 REGISTER_AB(PCIE_PCS_CTL_STAT),
225 /* DEBUG_DATA_OUT is not used */
226 /* DRV_EV is WO */
227 REGISTER_AZ(EVQ_CTL),
228 REGISTER_AZ(EVQ_CNT1),
229 REGISTER_AZ(EVQ_CNT2),
230 REGISTER_AZ(BUF_TBL_CFG),
231 REGISTER_AZ(SRM_RX_DC_CFG),
232 REGISTER_AZ(SRM_TX_DC_CFG),
233 REGISTER_AZ(SRM_CFG),
234 /* BUF_TBL_UPD is WO */
235 REGISTER_AZ(SRM_UPD_EVQ),
236 REGISTER_AZ(SRAM_PARITY),
237 REGISTER_AZ(RX_CFG),
238 REGISTER_BZ(RX_FILTER_CTL),
239 /* RX_FLUSH_DESCQ is WO */
240 REGISTER_AZ(RX_DC_CFG),
241 REGISTER_AZ(RX_DC_PF_WM),
242 REGISTER_BZ(RX_RSS_TKEY),
243 /* RX_NODESC_DROP is RC */
244 REGISTER_AA(RX_SELF_RST),
245 /* RX_DEBUG, RX_PUSH_DROP are not used */
246 REGISTER_CZ(RX_RSS_IPV6_REG1),
247 REGISTER_CZ(RX_RSS_IPV6_REG2),
248 REGISTER_CZ(RX_RSS_IPV6_REG3),
249 /* TX_FLUSH_DESCQ is WO */
250 REGISTER_AZ(TX_DC_CFG),
251 REGISTER_AA(TX_CHKSM_CFG),
252 REGISTER_AZ(TX_CFG),
253 /* TX_PUSH_DROP is not used */
254 REGISTER_AZ(TX_RESERVED),
255 REGISTER_BZ(TX_PACE),
256 /* TX_PACE_DROP_QID is RC */
257 REGISTER_BB(TX_VLAN),
258 REGISTER_BZ(TX_IPFIL_PORTEN),
259 REGISTER_AB(MD_TXD),
260 REGISTER_AB(MD_RXD),
261 REGISTER_AB(MD_CS),
262 REGISTER_AB(MD_PHY_ADR),
263 REGISTER_AB(MD_ID),
264 /* MD_STAT is RC */
265 REGISTER_AB(MAC_STAT_DMA),
266 REGISTER_AB(MAC_CTRL),
267 REGISTER_BB(GEN_MODE),
268 REGISTER_AB(MAC_MC_HASH_REG0),
269 REGISTER_AB(MAC_MC_HASH_REG1),
270 REGISTER_AB(GM_CFG1),
271 REGISTER_AB(GM_CFG2),
272 /* GM_IPG and GM_HD are not used */
273 REGISTER_AB(GM_MAX_FLEN),
274 /* GM_TEST is not used */
275 REGISTER_AB(GM_ADR1),
276 REGISTER_AB(GM_ADR2),
277 REGISTER_AB(GMF_CFG0),
278 REGISTER_AB(GMF_CFG1),
279 REGISTER_AB(GMF_CFG2),
280 REGISTER_AB(GMF_CFG3),
281 REGISTER_AB(GMF_CFG4),
282 REGISTER_AB(GMF_CFG5),
283 REGISTER_BB(TX_SRC_MAC_CTL),
284 REGISTER_AB(XM_ADR_LO),
285 REGISTER_AB(XM_ADR_HI),
286 REGISTER_AB(XM_GLB_CFG),
287 REGISTER_AB(XM_TX_CFG),
288 REGISTER_AB(XM_RX_CFG),
289 REGISTER_AB(XM_MGT_INT_MASK),
290 REGISTER_AB(XM_FC),
291 REGISTER_AB(XM_PAUSE_TIME),
292 REGISTER_AB(XM_TX_PARAM),
293 REGISTER_AB(XM_RX_PARAM),
294 /* XM_MGT_INT_MSK (note no 'A') is RC */
295 REGISTER_AB(XX_PWR_RST),
296 REGISTER_AB(XX_SD_CTL),
297 REGISTER_AB(XX_TXDRV_CTL),
298 /* XX_PRBS_CTL, XX_PRBS_CHK and XX_PRBS_ERR are not used */
299 /* XX_CORE_STAT is partly RC */
300 REGISTER_DZ(BIU_HW_REV_ID),
301 REGISTER_DZ(MC_DB_LWRD),
302 REGISTER_DZ(MC_DB_HWRD),
303 };
304
305 struct efx_nic_reg_table {
306 u32 offset:24;
307 u32 min_revision:3, max_revision:3;
308 u32 step:6, rows:21;
309 };
310
311 #define REGISTER_TABLE_DIMENSIONS(_, offset, arch, min_rev, max_rev, step, rows) { \
312 offset, \
313 REGISTER_REVISION_ ## arch ## min_rev, \
314 REGISTER_REVISION_ ## arch ## max_rev, \
315 step, rows \
316 }
317 #define REGISTER_TABLE(name, arch, min_rev, max_rev) \
318 REGISTER_TABLE_DIMENSIONS( \
319 name, arch ## R_ ## min_rev ## max_rev ## _ ## name, \
320 arch, min_rev, max_rev, \
321 arch ## R_ ## min_rev ## max_rev ## _ ## name ## _STEP, \
322 arch ## R_ ## min_rev ## max_rev ## _ ## name ## _ROWS)
323 #define REGISTER_TABLE_AA(name) REGISTER_TABLE(name, F, A, A)
324 #define REGISTER_TABLE_AZ(name) REGISTER_TABLE(name, F, A, Z)
325 #define REGISTER_TABLE_BB(name) REGISTER_TABLE(name, F, B, B)
326 #define REGISTER_TABLE_BZ(name) REGISTER_TABLE(name, F, B, Z)
327 #define REGISTER_TABLE_BB_CZ(name) \
328 REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, F, B, B, \
329 FR_BZ_ ## name ## _STEP, \
330 FR_BB_ ## name ## _ROWS), \
331 REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, F, C, Z, \
332 FR_BZ_ ## name ## _STEP, \
333 FR_CZ_ ## name ## _ROWS)
334 #define REGISTER_TABLE_CZ(name) REGISTER_TABLE(name, F, C, Z)
335 #define REGISTER_TABLE_DZ(name) REGISTER_TABLE(name, E, D, Z)
336
337 static const struct efx_nic_reg_table efx_nic_reg_tables[] = {
338 /* DRIVER is not used */
339 /* EVQ_RPTR, TIMER_COMMAND, USR_EV and {RX,TX}_DESC_UPD are WO */
340 REGISTER_TABLE_BB(TX_IPFIL_TBL),
341 REGISTER_TABLE_BB(TX_SRC_MAC_TBL),
342 REGISTER_TABLE_AA(RX_DESC_PTR_TBL_KER),
343 REGISTER_TABLE_BB_CZ(RX_DESC_PTR_TBL),
344 REGISTER_TABLE_AA(TX_DESC_PTR_TBL_KER),
345 REGISTER_TABLE_BB_CZ(TX_DESC_PTR_TBL),
346 REGISTER_TABLE_AA(EVQ_PTR_TBL_KER),
347 REGISTER_TABLE_BB_CZ(EVQ_PTR_TBL),
348 /* We can't reasonably read all of the buffer table (up to 8MB!).
349 * However this driver will only use a few entries. Reading
350 * 1K entries allows for some expansion of queue count and
351 * size before we need to change the version. */
352 REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL_KER, FR_AA_BUF_FULL_TBL_KER,
353 F, A, A, 8, 1024),
354 REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL, FR_BZ_BUF_FULL_TBL,
355 F, B, Z, 8, 1024),
356 REGISTER_TABLE_CZ(RX_MAC_FILTER_TBL0),
357 REGISTER_TABLE_BB_CZ(TIMER_TBL),
358 REGISTER_TABLE_BB_CZ(TX_PACE_TBL),
359 REGISTER_TABLE_BZ(RX_INDIRECTION_TBL),
360 /* TX_FILTER_TBL0 is huge and not used by this driver */
361 REGISTER_TABLE_CZ(TX_MAC_FILTER_TBL0),
362 REGISTER_TABLE_CZ(MC_TREG_SMEM),
363 /* MSIX_PBA_TABLE is not mapped */
364 /* SRM_DBG is not mapped (and is redundant with BUF_FLL_TBL) */
365 REGISTER_TABLE_BZ(RX_FILTER_TBL0),
366 REGISTER_TABLE_DZ(BIU_MC_SFT_STATUS),
367 };
368
369 size_t efx_nic_get_regs_len(struct efx_nic *efx)
370 {
371 const struct efx_nic_reg *reg;
372 const struct efx_nic_reg_table *table;
373 size_t len = 0;
374
375 for (reg = efx_nic_regs;
376 reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
377 reg++)
378 if (efx->type->revision >= reg->min_revision &&
379 efx->type->revision <= reg->max_revision)
380 len += sizeof(efx_oword_t);
381
382 for (table = efx_nic_reg_tables;
383 table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
384 table++)
385 if (efx->type->revision >= table->min_revision &&
386 efx->type->revision <= table->max_revision)
387 len += table->rows * min_t(size_t, table->step, 16);
388
389 return len;
390 }
391
392 void efx_nic_get_regs(struct efx_nic *efx, void *buf)
393 {
394 const struct efx_nic_reg *reg;
395 const struct efx_nic_reg_table *table;
396
397 for (reg = efx_nic_regs;
398 reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
399 reg++) {
400 if (efx->type->revision >= reg->min_revision &&
401 efx->type->revision <= reg->max_revision) {
402 efx_reado(efx, (efx_oword_t *)buf, reg->offset);
403 buf += sizeof(efx_oword_t);
404 }
405 }
406
407 for (table = efx_nic_reg_tables;
408 table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
409 table++) {
410 size_t size, i;
411
412 if (!(efx->type->revision >= table->min_revision &&
413 efx->type->revision <= table->max_revision))
414 continue;
415
416 size = min_t(size_t, table->step, 16);
417
418 for (i = 0; i < table->rows; i++) {
419 switch (table->step) {
420 case 4: /* 32-bit SRAM */
421 efx_readd(efx, buf, table->offset + 4 * i);
422 break;
423 case 8: /* 64-bit SRAM */
424 efx_sram_readq(efx,
425 efx->membase + table->offset,
426 buf, i);
427 break;
428 case 16: /* 128-bit-readable register */
429 efx_reado_table(efx, buf, table->offset, i);
430 break;
431 case 32: /* 128-bit register, interleaved */
432 efx_reado_table(efx, buf, table->offset, 2 * i);
433 break;
434 default:
435 WARN_ON(1);
436 return;
437 }
438 buf += size;
439 }
440 }
441 }
442
443 /**
444 * efx_nic_describe_stats - Describe supported statistics for ethtool
445 * @desc: Array of &struct efx_hw_stat_desc describing the statistics
446 * @count: Length of the @desc array
447 * @mask: Bitmask of which elements of @desc are enabled
448 * @names: Buffer to copy names to, or %NULL. The names are copied
449 * starting at intervals of %ETH_GSTRING_LEN bytes.
450 *
451 * Returns the number of visible statistics, i.e. the number of set
452 * bits in the first @count bits of @mask for which a name is defined.
453 */
454 size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count,
455 const unsigned long *mask, u8 *names)
456 {
457 size_t visible = 0;
458 size_t index;
459
460 for_each_set_bit(index, mask, count) {
461 if (desc[index].name) {
462 if (names) {
463 strlcpy(names, desc[index].name,
464 ETH_GSTRING_LEN);
465 names += ETH_GSTRING_LEN;
466 }
467 ++visible;
468 }
469 }
470
471 return visible;
472 }
473
474 /**
475 * efx_nic_update_stats - Convert statistics DMA buffer to array of u64
476 * @desc: Array of &struct efx_hw_stat_desc describing the DMA buffer
477 * layout. DMA widths of 0, 16, 32 and 64 are supported; where
478 * the width is specified as 0 the corresponding element of
479 * @stats is not updated.
480 * @count: Length of the @desc array
481 * @mask: Bitmask of which elements of @desc are enabled
482 * @stats: Buffer to update with the converted statistics. The length
483 * of this array must be at least @count.
484 * @dma_buf: DMA buffer containing hardware statistics
485 * @accumulate: If set, the converted values will be added rather than
486 * directly stored to the corresponding elements of @stats
487 */
488 void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count,
489 const unsigned long *mask,
490 u64 *stats, const void *dma_buf, bool accumulate)
491 {
492 size_t index;
493
494 for_each_set_bit(index, mask, count) {
495 if (desc[index].dma_width) {
496 const void *addr = dma_buf + desc[index].offset;
497 u64 val;
498
499 switch (desc[index].dma_width) {
500 case 16:
501 val = le16_to_cpup((__le16 *)addr);
502 break;
503 case 32:
504 val = le32_to_cpup((__le32 *)addr);
505 break;
506 case 64:
507 val = le64_to_cpup((__le64 *)addr);
508 break;
509 default:
510 WARN_ON(1);
511 val = 0;
512 break;
513 }
514
515 if (accumulate)
516 stats[index] += val;
517 else
518 stats[index] = val;
519 }
520 }
521 }
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