drivers/net/ethernet/sfc/siena.c

   1 /****************************************************************************
   2  * Driver for Solarflare Solarstorm network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2006-2010 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 #include <linux/bitops.h>
  12 #include <linux/delay.h>
  13 #include <linux/pci.h>
  14 #include <linux/module.h>
  15 #include <linux/slab.h>
  16 #include <linux/random.h>
  17 #include "net_driver.h"
  18 #include "bitfield.h"
  19 #include "efx.h"
  20 #include "nic.h"
  21 #include "spi.h"
  22 #include "farch_regs.h"
  23 #include "io.h"
  24 #include "phy.h"
  25 #include "workarounds.h"
  26 #include "mcdi.h"
  27 #include "mcdi_pcol.h"
  28 #include "selftest.h"
  29
  30 /* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
  31
  32 static void siena_init_wol(struct efx_nic *efx);
  33
  34
  35 static void siena_push_irq_moderation(struct efx_channel *channel)
  36 {
  37         efx_dword_t timer_cmd;
  38
  39         if (channel->irq_moderation)
  40                 EFX_POPULATE_DWORD_2(timer_cmd,
  41                                      FRF_CZ_TC_TIMER_MODE,
  42                                      FFE_CZ_TIMER_MODE_INT_HLDOFF,
  43                                      FRF_CZ_TC_TIMER_VAL,
  44                                      channel->irq_moderation - 1);
  45         else
  46                 EFX_POPULATE_DWORD_2(timer_cmd,
  47                                      FRF_CZ_TC_TIMER_MODE,
  48                                      FFE_CZ_TIMER_MODE_DIS,
  49                                      FRF_CZ_TC_TIMER_VAL, 0);
  50         efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
  51                                channel->channel);
  52 }
  53
  54 void siena_prepare_flush(struct efx_nic *efx)
  55 {
  56         if (efx->fc_disable++ == 0)
  57                 efx_mcdi_set_mac(efx);
  58 }
  59
  60 void siena_finish_flush(struct efx_nic *efx)
  61 {
  62         if (--efx->fc_disable == 0)
  63                 efx_mcdi_set_mac(efx);
  64 }
  65
  66 static const struct efx_farch_register_test siena_register_tests[] = {
  67         { FR_AZ_ADR_REGION,
  68           EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
  69         { FR_CZ_USR_EV_CFG,
  70           EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
  71         { FR_AZ_RX_CFG,
  72           EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
  73         { FR_AZ_TX_CFG,
  74           EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
  75         { FR_AZ_TX_RESERVED,
  76           EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
  77         { FR_AZ_SRM_TX_DC_CFG,
  78           EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
  79         { FR_AZ_RX_DC_CFG,
  80           EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
  81         { FR_AZ_RX_DC_PF_WM,
  82           EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
  83         { FR_BZ_DP_CTRL,
  84           EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
  85         { FR_BZ_RX_RSS_TKEY,
  86           EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
  87         { FR_CZ_RX_RSS_IPV6_REG1,
  88           EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
  89         { FR_CZ_RX_RSS_IPV6_REG2,
  90           EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
  91         { FR_CZ_RX_RSS_IPV6_REG3,
  92           EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
  93 };
  94
  95 static int siena_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
  96 {
  97         enum reset_type reset_method = RESET_TYPE_ALL;
  98         int rc, rc2;
  99
 100         efx_reset_down(efx, reset_method);
 101
 102         /* Reset the chip immediately so that it is completely
 103          * quiescent regardless of what any VF driver does.
 104          */
 105         rc = efx_mcdi_reset(efx, reset_method);
 106         if (rc)
 107                 goto out;
 108
 109         tests->registers =
 110                 efx_farch_test_registers(efx, siena_register_tests,
 111                                          ARRAY_SIZE(siena_register_tests))
 112                 ? -1 : 1;
 113
 114         rc = efx_mcdi_reset(efx, reset_method);
 115 out:
 116         rc2 = efx_reset_up(efx, reset_method, rc == 0);
 117         return rc ? rc : rc2;
 118 }
 119
 120 /**************************************************************************
 121  *
 122  * Device reset
 123  *
 124  **************************************************************************
 125  */
 126
 127 static int siena_map_reset_flags(u32 *flags)
 128 {
 129         enum {
 130                 SIENA_RESET_PORT = (ETH_RESET_DMA | ETH_RESET_FILTER |
 131                                     ETH_RESET_OFFLOAD | ETH_RESET_MAC |
 132                                     ETH_RESET_PHY),
 133                 SIENA_RESET_MC = (SIENA_RESET_PORT |
 134                                   ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT),
 135         };
 136
 137         if ((*flags & SIENA_RESET_MC) == SIENA_RESET_MC) {
 138                 *flags &= ~SIENA_RESET_MC;
 139                 return RESET_TYPE_WORLD;
 140         }
 141
 142         if ((*flags & SIENA_RESET_PORT) == SIENA_RESET_PORT) {
 143                 *flags &= ~SIENA_RESET_PORT;
 144                 return RESET_TYPE_ALL;
 145         }
 146
 147         /* no invisible reset implemented */
 148
 149         return -EINVAL;
 150 }
 151
 152 #ifdef CONFIG_EEH
 153 /* When a PCI device is isolated from the bus, a subsequent MMIO read is
 154  * required for the kernel EEH mechanisms to notice. As the Solarflare driver
 155  * was written to minimise MMIO read (for latency) then a periodic call to check
 156  * the EEH status of the device is required so that device recovery can happen
 157  * in a timely fashion.
 158  */
 159 static void siena_monitor(struct efx_nic *efx)
 160 {
 161         struct eeh_dev *eehdev =
 162                 of_node_to_eeh_dev(pci_device_to_OF_node(efx->pci_dev));
 163
 164         eeh_dev_check_failure(eehdev);
 165 }
 166 #endif
 167
 168 static int siena_probe_nvconfig(struct efx_nic *efx)
 169 {
 170         u32 caps = 0;
 171         int rc;
 172
 173         rc = efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL, &caps);
 174
 175         efx->timer_quantum_ns =
 176                 (caps & (1 << MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN)) ?
 177                 3072 : 6144; /* 768 cycles */
 178         return rc;
 179 }
 180
 181 static void siena_dimension_resources(struct efx_nic *efx)
 182 {
 183         /* Each port has a small block of internal SRAM dedicated to
 184          * the buffer table and descriptor caches.  In theory we can
 185          * map both blocks to one port, but we don't.
 186          */
 187         efx_farch_dimension_resources(efx, FR_CZ_BUF_FULL_TBL_ROWS / 2);
 188 }
 189
 190 static unsigned int siena_mem_map_size(struct efx_nic *efx)
 191 {
 192         return FR_CZ_MC_TREG_SMEM +
 193                 FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS;
 194 }
 195
 196 static int siena_probe_nic(struct efx_nic *efx)
 197 {
 198         struct siena_nic_data *nic_data;
 199         bool already_attached = false;
 200         efx_oword_t reg;
 201         int rc;
 202
 203         /* Allocate storage for hardware specific data */
 204         nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
 205         if (!nic_data)
 206                 return -ENOMEM;
 207         efx->nic_data = nic_data;
 208
 209         if (efx_farch_fpga_ver(efx) != 0) {
 210                 netif_err(efx, probe, efx->net_dev,
 211                           "Siena FPGA not supported\n");
 212                 rc = -ENODEV;
 213                 goto fail1;
 214         }
 215
 216         efx->max_channels = EFX_MAX_CHANNELS;
 217
 218         efx_reado(efx, &reg, FR_AZ_CS_DEBUG);
 219         efx->port_num = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1;
 220
 221         rc = efx_mcdi_init(efx);
 222         if (rc)
 223                 goto fail1;
 224
 225         /* Let the BMC know that the driver is now in charge of link and
 226          * filter settings. We must do this before we reset the NIC */
 227         rc = efx_mcdi_drv_attach(efx, true, &already_attached);
 228         if (rc) {
 229                 netif_err(efx, probe, efx->net_dev,
 230                           "Unable to register driver with MCPU\n");
 231                 goto fail2;
 232         }
 233         if (already_attached)
 234                 /* Not a fatal error */
 235                 netif_err(efx, probe, efx->net_dev,
 236                           "Host already registered with MCPU\n");
 237
 238         /* Now we can reset the NIC */
 239         rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
 240         if (rc) {
 241                 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
 242                 goto fail3;
 243         }
 244
 245         siena_init_wol(efx);
 246
 247         /* Allocate memory for INT_KER */
 248         rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t),
 249                                   GFP_KERNEL);
 250         if (rc)
 251                 goto fail4;
 252         BUG_ON(efx->irq_status.dma_addr & 0x0f);
 253
 254         netif_dbg(efx, probe, efx->net_dev,
 255                   "INT_KER at %llx (virt %p phys %llx)\n",
 256                   (unsigned long long)efx->irq_status.dma_addr,
 257                   efx->irq_status.addr,
 258                   (unsigned long long)virt_to_phys(efx->irq_status.addr));
 259
 260         /* Read in the non-volatile configuration */
 261         rc = siena_probe_nvconfig(efx);
 262         if (rc == -EINVAL) {
 263                 netif_err(efx, probe, efx->net_dev,
 264                           "NVRAM is invalid therefore using defaults\n");
 265                 efx->phy_type = PHY_TYPE_NONE;
 266                 efx->mdio.prtad = MDIO_PRTAD_NONE;
 267         } else if (rc) {
 268                 goto fail5;
 269         }
 270
 271         rc = efx_mcdi_mon_probe(efx);
 272         if (rc)
 273                 goto fail5;
 274
 275         efx_sriov_probe(efx);
 276         efx_ptp_probe(efx);
 277
 278         return 0;
 279
 280 fail5:
 281         efx_nic_free_buffer(efx, &efx->irq_status);
 282 fail4:
 283 fail3:
 284         efx_mcdi_drv_attach(efx, false, NULL);
 285 fail2:
 286         efx_mcdi_fini(efx);
 287 fail1:
 288         kfree(efx->nic_data);
 289         return rc;
 290 }
 291
 292 /* This call performs hardware-specific global initialisation, such as
 293  * defining the descriptor cache sizes and number of RSS channels.
 294  * It does not set up any buffers, descriptor rings or event queues.
 295  */
 296 static int siena_init_nic(struct efx_nic *efx)
 297 {
 298         efx_oword_t temp;
 299         int rc;
 300
 301         /* Recover from a failed assertion post-reset */
 302         rc = efx_mcdi_handle_assertion(efx);
 303         if (rc)
 304                 return rc;
 305
 306         /* Squash TX of packets of 16 bytes or less */
 307         efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
 308         EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
 309         efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
 310
 311         /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
 312          * descriptors (which is bad).
 313          */
 314         efx_reado(efx, &temp, FR_AZ_TX_CFG);
 315         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
 316         EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
 317         efx_writeo(efx, &temp, FR_AZ_TX_CFG);
 318
 319         efx_reado(efx, &temp, FR_AZ_RX_CFG);
 320         EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
 321         EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
 322         /* Enable hash insertion. This is broken for the 'Falcon' hash
 323          * if IPv6 hashing is also enabled, so also select Toeplitz
 324          * TCP/IPv4 and IPv4 hashes. */
 325         EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1);
 326         EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1);
 327         EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1);
 328         EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_USR_BUF_SIZE,
 329                             EFX_RX_USR_BUF_SIZE >> 5);
 330         efx_writeo(efx, &temp, FR_AZ_RX_CFG);
 331
 332         /* Set hash key for IPv4 */
 333         memcpy(&temp, efx->rx_hash_key, sizeof(temp));
 334         efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
 335
 336         /* Enable IPv6 RSS */
 337         BUILD_BUG_ON(sizeof(efx->rx_hash_key) <
 338                      2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 ||
 339                      FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0);
 340         memcpy(&temp, efx->rx_hash_key, sizeof(temp));
 341         efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
 342         memcpy(&temp, efx->rx_hash_key + sizeof(temp), sizeof(temp));
 343         efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
 344         EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1,
 345                              FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1);
 346         memcpy(&temp, efx->rx_hash_key + 2 * sizeof(temp),
 347                FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
 348         efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
 349
 350         /* Enable event logging */
 351         rc = efx_mcdi_log_ctrl(efx, true, false, 0);
 352         if (rc)
 353                 return rc;
 354
 355         /* Set destination of both TX and RX Flush events */
 356         EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
 357         efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
 358
 359         EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
 360         efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
 361
 362         efx_farch_init_common(efx);
 363         return 0;
 364 }
 365
 366 static void siena_remove_nic(struct efx_nic *efx)
 367 {
 368         efx_mcdi_mon_remove(efx);
 369
 370         efx_nic_free_buffer(efx, &efx->irq_status);
 371
 372         efx_mcdi_reset(efx, RESET_TYPE_ALL);
 373
 374         /* Relinquish the device back to the BMC */
 375         efx_mcdi_drv_attach(efx, false, NULL);
 376
 377         /* Tear down the private nic state */
 378         kfree(efx->nic_data);
 379         efx->nic_data = NULL;
 380
 381         efx_mcdi_fini(efx);
 382 }
 383
 384 static int siena_try_update_nic_stats(struct efx_nic *efx)
 385 {
 386         __le64 *dma_stats;
 387         struct efx_mac_stats *mac_stats;
 388         __le64 generation_start, generation_end;
 389
 390         mac_stats = &efx->mac_stats;
 391         dma_stats = efx->stats_buffer.addr;
 392
 393         generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
 394         if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
 395                 return 0;
 396         rmb();
 397
 398 #define MAC_STAT(M, D) \
 399         mac_stats->M = le64_to_cpu(dma_stats[MC_CMD_MAC_ ## D])
 400
 401         MAC_STAT(tx_bytes, TX_BYTES);
 402         MAC_STAT(tx_bad_bytes, TX_BAD_BYTES);
 403         efx_update_diff_stat(&mac_stats->tx_good_bytes,
 404                              mac_stats->tx_bytes - mac_stats->tx_bad_bytes);
 405         MAC_STAT(tx_packets, TX_PKTS);
 406         MAC_STAT(tx_bad, TX_BAD_FCS_PKTS);
 407         MAC_STAT(tx_pause, TX_PAUSE_PKTS);
 408         MAC_STAT(tx_control, TX_CONTROL_PKTS);
 409         MAC_STAT(tx_unicast, TX_UNICAST_PKTS);
 410         MAC_STAT(tx_multicast, TX_MULTICAST_PKTS);
 411         MAC_STAT(tx_broadcast, TX_BROADCAST_PKTS);
 412         MAC_STAT(tx_lt64, TX_LT64_PKTS);
 413         MAC_STAT(tx_64, TX_64_PKTS);
 414         MAC_STAT(tx_65_to_127, TX_65_TO_127_PKTS);
 415         MAC_STAT(tx_128_to_255, TX_128_TO_255_PKTS);
 416         MAC_STAT(tx_256_to_511, TX_256_TO_511_PKTS);
 417         MAC_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS);
 418         MAC_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS);
 419         MAC_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS);
 420         MAC_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS);
 421         mac_stats->tx_collision = 0;
 422         MAC_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS);
 423         MAC_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS);
 424         MAC_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS);
 425         MAC_STAT(tx_deferred, TX_DEFERRED_PKTS);
 426         MAC_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS);
 427         mac_stats->tx_collision = (mac_stats->tx_single_collision +
 428                                    mac_stats->tx_multiple_collision +
 429                                    mac_stats->tx_excessive_collision +
 430                                    mac_stats->tx_late_collision);
 431         MAC_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS);
 432         MAC_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS);
 433         MAC_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS);
 434         MAC_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS);
 435         MAC_STAT(rx_bytes, RX_BYTES);
 436         MAC_STAT(rx_bad_bytes, RX_BAD_BYTES);
 437         efx_update_diff_stat(&mac_stats->rx_good_bytes,
 438                              mac_stats->rx_bytes - mac_stats->rx_bad_bytes);
 439         MAC_STAT(rx_packets, RX_PKTS);
 440         MAC_STAT(rx_good, RX_GOOD_PKTS);
 441         MAC_STAT(rx_bad, RX_BAD_FCS_PKTS);
 442         MAC_STAT(rx_pause, RX_PAUSE_PKTS);
 443         MAC_STAT(rx_control, RX_CONTROL_PKTS);
 444         MAC_STAT(rx_unicast, RX_UNICAST_PKTS);
 445         MAC_STAT(rx_multicast, RX_MULTICAST_PKTS);
 446         MAC_STAT(rx_broadcast, RX_BROADCAST_PKTS);
 447         MAC_STAT(rx_lt64, RX_UNDERSIZE_PKTS);
 448         MAC_STAT(rx_64, RX_64_PKTS);
 449         MAC_STAT(rx_65_to_127, RX_65_TO_127_PKTS);
 450         MAC_STAT(rx_128_to_255, RX_128_TO_255_PKTS);
 451         MAC_STAT(rx_256_to_511, RX_256_TO_511_PKTS);
 452         MAC_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS);
 453         MAC_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS);
 454         MAC_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS);
 455         MAC_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS);
 456         mac_stats->rx_bad_lt64 = 0;
 457         mac_stats->rx_bad_64_to_15xx = 0;
 458         mac_stats->rx_bad_15xx_to_jumbo = 0;
 459         MAC_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS);
 460         MAC_STAT(rx_overflow, RX_OVERFLOW_PKTS);
 461         mac_stats->rx_missed = 0;
 462         MAC_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS);
 463         MAC_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS);
 464         MAC_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS);
 465         MAC_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS);
 466         MAC_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS);
 467         mac_stats->rx_good_lt64 = 0;
 468
 469         efx->n_rx_nodesc_drop_cnt =
 470                 le64_to_cpu(dma_stats[MC_CMD_MAC_RX_NODESC_DROPS]);
 471
 472 #undef MAC_STAT
 473
 474         rmb();
 475         generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
 476         if (generation_end != generation_start)
 477                 return -EAGAIN;
 478
 479         return 0;
 480 }
 481
 482 static void siena_update_nic_stats(struct efx_nic *efx)
 483 {
 484         int retry;
 485
 486         /* If we're unlucky enough to read statistics wduring the DMA, wait
 487          * up to 10ms for it to finish (typically takes <500us) */
 488         for (retry = 0; retry < 100; ++retry) {
 489                 if (siena_try_update_nic_stats(efx) == 0)
 490                         return;
 491                 udelay(100);
 492         }
 493
 494         /* Use the old values instead */
 495 }
 496
 497 static int siena_mac_reconfigure(struct efx_nic *efx)
 498 {
 499         MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_MCAST_HASH_IN_LEN);
 500         int rc;
 501
 502         BUILD_BUG_ON(MC_CMD_SET_MCAST_HASH_IN_LEN !=
 503                      MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST +
 504                      sizeof(efx->multicast_hash));
 505
 506         efx_farch_filter_sync_rx_mode(efx);
 507
 508         WARN_ON(!mutex_is_locked(&efx->mac_lock));
 509
 510         rc = efx_mcdi_set_mac(efx);
 511         if (rc != 0)
 512                 return rc;
 513
 514         memcpy(MCDI_PTR(inbuf, SET_MCAST_HASH_IN_HASH0),
 515                efx->multicast_hash.byte, sizeof(efx->multicast_hash));
 516         return efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH,
 517                             inbuf, sizeof(inbuf), NULL, 0, NULL);
 518 }
 519
 520 /**************************************************************************
 521  *
 522  * Wake on LAN
 523  *
 524  **************************************************************************
 525  */
 526
 527 static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
 528 {
 529         struct siena_nic_data *nic_data = efx->nic_data;
 530
 531         wol->supported = WAKE_MAGIC;
 532         if (nic_data->wol_filter_id != -1)
 533                 wol->wolopts = WAKE_MAGIC;
 534         else
 535                 wol->wolopts = 0;
 536         memset(&wol->sopass, 0, sizeof(wol->sopass));
 537 }
 538
 539
 540 static int siena_set_wol(struct efx_nic *efx, u32 type)
 541 {
 542         struct siena_nic_data *nic_data = efx->nic_data;
 543         int rc;
 544
 545         if (type & ~WAKE_MAGIC)
 546                 return -EINVAL;
 547
 548         if (type & WAKE_MAGIC) {
 549                 if (nic_data->wol_filter_id != -1)
 550                         efx_mcdi_wol_filter_remove(efx,
 551                                                    nic_data->wol_filter_id);
 552                 rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr,
 553                                                    &nic_data->wol_filter_id);
 554                 if (rc)
 555                         goto fail;
 556
 557                 pci_wake_from_d3(efx->pci_dev, true);
 558         } else {
 559                 rc = efx_mcdi_wol_filter_reset(efx);
 560                 nic_data->wol_filter_id = -1;
 561                 pci_wake_from_d3(efx->pci_dev, false);
 562                 if (rc)
 563                         goto fail;
 564         }
 565
 566         return 0;
 567  fail:
 568         netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n",
 569                   __func__, type, rc);
 570         return rc;
 571 }
 572
 573
 574 static void siena_init_wol(struct efx_nic *efx)
 575 {
 576         struct siena_nic_data *nic_data = efx->nic_data;
 577         int rc;
 578
 579         rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
 580
 581         if (rc != 0) {
 582                 /* If it failed, attempt to get into a synchronised
 583                  * state with MC by resetting any set WoL filters */
 584                 efx_mcdi_wol_filter_reset(efx);
 585                 nic_data->wol_filter_id = -1;
 586         } else if (nic_data->wol_filter_id != -1) {
 587                 pci_wake_from_d3(efx->pci_dev, true);
 588         }
 589 }
 590
 591 /**************************************************************************
 592  *
 593  * MCDI
 594  *
 595  **************************************************************************
 596  */
 597
 598 #define MCDI_PDU(efx)                                                   \
 599         (efx_port_num(efx) ? MC_SMEM_P1_PDU_OFST : MC_SMEM_P0_PDU_OFST)
 600 #define MCDI_DOORBELL(efx)                                              \
 601         (efx_port_num(efx) ? MC_SMEM_P1_DOORBELL_OFST : MC_SMEM_P0_DOORBELL_OFST)
 602 #define MCDI_STATUS(efx)                                                \
 603         (efx_port_num(efx) ? MC_SMEM_P1_STATUS_OFST : MC_SMEM_P0_STATUS_OFST)
 604
 605 static void siena_mcdi_request(struct efx_nic *efx,
 606                                const efx_dword_t *hdr, size_t hdr_len,
 607                                const efx_dword_t *sdu, size_t sdu_len)
 608 {
 609         unsigned pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
 610         unsigned doorbell = FR_CZ_MC_TREG_SMEM + MCDI_DOORBELL(efx);
 611         unsigned int i;
 612         unsigned int inlen_dw = DIV_ROUND_UP(sdu_len, 4);
 613
 614         EFX_BUG_ON_PARANOID(hdr_len != 4);
 615
 616         efx_writed(efx, hdr, pdu);
 617
 618         for (i = 0; i < inlen_dw; i++)
 619                 efx_writed(efx, &sdu[i], pdu + hdr_len + 4 * i);
 620
 621         /* Ensure the request is written out before the doorbell */
 622         wmb();
 623
 624         /* ring the doorbell with a distinctive value */
 625         _efx_writed(efx, (__force __le32) 0x45789abc, doorbell);
 626 }
 627
 628 static bool siena_mcdi_poll_response(struct efx_nic *efx)
 629 {
 630         unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
 631         efx_dword_t hdr;
 632
 633         efx_readd(efx, &hdr, pdu);
 634
 635         /* All 1's indicates that shared memory is in reset (and is
 636          * not a valid hdr). Wait for it to come out reset before
 637          * completing the command
 638          */
 639         return EFX_DWORD_FIELD(hdr, EFX_DWORD_0) != 0xffffffff &&
 640                 EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
 641 }
 642
 643 static void siena_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
 644                                      size_t offset, size_t outlen)
 645 {
 646         unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
 647         unsigned int outlen_dw = DIV_ROUND_UP(outlen, 4);
 648         int i;
 649
 650         for (i = 0; i < outlen_dw; i++)
 651                 efx_readd(efx, &outbuf[i], pdu + offset + 4 * i);
 652 }
 653
 654 static int siena_mcdi_poll_reboot(struct efx_nic *efx)
 655 {
 656         unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_STATUS(efx);
 657         efx_dword_t reg;
 658         u32 value;
 659
 660         efx_readd(efx, &reg, addr);
 661         value = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
 662
 663         if (value == 0)
 664                 return 0;
 665
 666         EFX_ZERO_DWORD(reg);
 667         efx_writed(efx, &reg, addr);
 668
 669         if (value == MC_STATUS_DWORD_ASSERT)
 670                 return -EINTR;
 671         else
 672                 return -EIO;
 673 }
 674
 675 /**************************************************************************
 676  *
 677  * Revision-dependent attributes used by efx.c and nic.c
 678  *
 679  **************************************************************************
 680  */
 681
 682 const struct efx_nic_type siena_a0_nic_type = {
 683         .mem_map_size = siena_mem_map_size,
 684         .probe = siena_probe_nic,
 685         .remove = siena_remove_nic,
 686         .init = siena_init_nic,
 687         .dimension_resources = siena_dimension_resources,
 688         .fini = efx_port_dummy_op_void,
 689 #ifdef CONFIG_EEH
 690         .monitor = siena_monitor,
 691 #else
 692         .monitor = NULL,
 693 #endif
 694         .map_reset_reason = efx_mcdi_map_reset_reason,
 695         .map_reset_flags = siena_map_reset_flags,
 696         .reset = efx_mcdi_reset,
 697         .probe_port = efx_mcdi_port_probe,
 698         .remove_port = efx_mcdi_port_remove,
 699         .fini_dmaq = efx_farch_fini_dmaq,
 700         .prepare_flush = siena_prepare_flush,
 701         .finish_flush = siena_finish_flush,
 702         .update_stats = siena_update_nic_stats,
 703         .start_stats = efx_mcdi_mac_start_stats,
 704         .stop_stats = efx_mcdi_mac_stop_stats,
 705         .set_id_led = efx_mcdi_set_id_led,
 706         .push_irq_moderation = siena_push_irq_moderation,
 707         .reconfigure_mac = siena_mac_reconfigure,
 708         .check_mac_fault = efx_mcdi_mac_check_fault,
 709         .reconfigure_port = efx_mcdi_port_reconfigure,
 710         .get_wol = siena_get_wol,
 711         .set_wol = siena_set_wol,
 712         .resume_wol = siena_init_wol,
 713         .test_chip = siena_test_chip,
 714         .test_nvram = efx_mcdi_nvram_test_all,
 715         .mcdi_request = siena_mcdi_request,
 716         .mcdi_poll_response = siena_mcdi_poll_response,
 717         .mcdi_read_response = siena_mcdi_read_response,
 718         .mcdi_poll_reboot = siena_mcdi_poll_reboot,
 719         .irq_enable_master = efx_farch_irq_enable_master,
 720         .irq_test_generate = efx_farch_irq_test_generate,
 721         .irq_disable_non_ev = efx_farch_irq_disable_master,
 722         .irq_handle_msi = efx_farch_msi_interrupt,
 723         .irq_handle_legacy = efx_farch_legacy_interrupt,
 724         .tx_probe = efx_farch_tx_probe,
 725         .tx_init = efx_farch_tx_init,
 726         .tx_remove = efx_farch_tx_remove,
 727         .tx_write = efx_farch_tx_write,
 728         .rx_push_indir_table = efx_farch_rx_push_indir_table,
 729         .rx_probe = efx_farch_rx_probe,
 730         .rx_init = efx_farch_rx_init,
 731         .rx_remove = efx_farch_rx_remove,
 732         .rx_write = efx_farch_rx_write,
 733         .rx_defer_refill = efx_farch_rx_defer_refill,
 734         .ev_probe = efx_farch_ev_probe,
 735         .ev_init = efx_farch_ev_init,
 736         .ev_fini = efx_farch_ev_fini,
 737         .ev_remove = efx_farch_ev_remove,
 738         .ev_process = efx_farch_ev_process,
 739         .ev_read_ack = efx_farch_ev_read_ack,
 740         .ev_test_generate = efx_farch_ev_test_generate,
 741         .filter_table_probe = efx_farch_filter_table_probe,
 742         .filter_table_restore = efx_farch_filter_table_restore,
 743         .filter_table_remove = efx_farch_filter_table_remove,
 744         .filter_update_rx_scatter = efx_farch_filter_update_rx_scatter,
 745         .filter_insert = efx_farch_filter_insert,
 746         .filter_remove_safe = efx_farch_filter_remove_safe,
 747         .filter_get_safe = efx_farch_filter_get_safe,
 748         .filter_clear_rx = efx_farch_filter_clear_rx,
 749         .filter_count_rx_used = efx_farch_filter_count_rx_used,
 750         .filter_get_rx_id_limit = efx_farch_filter_get_rx_id_limit,
 751         .filter_get_rx_ids = efx_farch_filter_get_rx_ids,
 752 #ifdef CONFIG_RFS_ACCEL
 753         .filter_rfs_insert = efx_farch_filter_rfs_insert,
 754         .filter_rfs_expire_one = efx_farch_filter_rfs_expire_one,
 755 #endif
 756
 757         .revision = EFX_REV_SIENA_A0,
 758         .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
 759         .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
 760         .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
 761         .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
 762         .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
 763         .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
 764         .rx_buffer_hash_size = 0x10,
 765         .rx_buffer_padding = 0,
 766         .can_rx_scatter = true,
 767         .max_interrupt_mode = EFX_INT_MODE_MSIX,
 768         .timer_period_max = 1 << FRF_CZ_TC_TIMER_VAL_WIDTH,
 769         .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
 770                              NETIF_F_RXHASH | NETIF_F_NTUPLE),
 771         .mcdi_max_ver = 1,
 772         .max_rx_ip_filters = FR_BZ_RX_FILTER_TBL0_ROWS,
 773 };