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[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / sfc / siena.c
1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2013 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/random.h>
17 #include "net_driver.h"
18 #include "bitfield.h"
19 #include "efx.h"
20 #include "nic.h"
21 #include "farch_regs.h"
22 #include "io.h"
23 #include "workarounds.h"
24 #include "mcdi.h"
25 #include "mcdi_pcol.h"
26 #include "selftest.h"
27 #include "siena_sriov.h"
28
29 /* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
30
31 static void siena_init_wol(struct efx_nic *efx);
32
33
34 static void siena_push_irq_moderation(struct efx_channel *channel)
35 {
36 struct efx_nic *efx = channel->efx;
37 efx_dword_t timer_cmd;
38
39 if (channel->irq_moderation_us) {
40 unsigned int ticks;
41
42 ticks = efx_usecs_to_ticks(efx, channel->irq_moderation_us);
43 EFX_POPULATE_DWORD_2(timer_cmd,
44 FRF_CZ_TC_TIMER_MODE,
45 FFE_CZ_TIMER_MODE_INT_HLDOFF,
46 FRF_CZ_TC_TIMER_VAL,
47 ticks - 1);
48 } else {
49 EFX_POPULATE_DWORD_2(timer_cmd,
50 FRF_CZ_TC_TIMER_MODE,
51 FFE_CZ_TIMER_MODE_DIS,
52 FRF_CZ_TC_TIMER_VAL, 0);
53 }
54 efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
55 channel->channel);
56 }
57
58 void siena_prepare_flush(struct efx_nic *efx)
59 {
60 if (efx->fc_disable++ == 0)
61 efx_mcdi_set_mac(efx);
62 }
63
64 void siena_finish_flush(struct efx_nic *efx)
65 {
66 if (--efx->fc_disable == 0)
67 efx_mcdi_set_mac(efx);
68 }
69
70 static const struct efx_farch_register_test siena_register_tests[] = {
71 { FR_AZ_ADR_REGION,
72 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
73 { FR_CZ_USR_EV_CFG,
74 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
75 { FR_AZ_RX_CFG,
76 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
77 { FR_AZ_TX_CFG,
78 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
79 { FR_AZ_TX_RESERVED,
80 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
81 { FR_AZ_SRM_TX_DC_CFG,
82 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
83 { FR_AZ_RX_DC_CFG,
84 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
85 { FR_AZ_RX_DC_PF_WM,
86 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
87 { FR_BZ_DP_CTRL,
88 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
89 { FR_BZ_RX_RSS_TKEY,
90 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
91 { FR_CZ_RX_RSS_IPV6_REG1,
92 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
93 { FR_CZ_RX_RSS_IPV6_REG2,
94 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
95 { FR_CZ_RX_RSS_IPV6_REG3,
96 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
97 };
98
99 static int siena_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
100 {
101 enum reset_type reset_method = RESET_TYPE_ALL;
102 int rc, rc2;
103
104 efx_reset_down(efx, reset_method);
105
106 /* Reset the chip immediately so that it is completely
107 * quiescent regardless of what any VF driver does.
108 */
109 rc = efx_mcdi_reset(efx, reset_method);
110 if (rc)
111 goto out;
112
113 tests->registers =
114 efx_farch_test_registers(efx, siena_register_tests,
115 ARRAY_SIZE(siena_register_tests))
116 ? -1 : 1;
117
118 rc = efx_mcdi_reset(efx, reset_method);
119 out:
120 rc2 = efx_reset_up(efx, reset_method, rc == 0);
121 return rc ? rc : rc2;
122 }
123
124 /**************************************************************************
125 *
126 * PTP
127 *
128 **************************************************************************
129 */
130
131 static void siena_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
132 {
133 _efx_writed(efx, cpu_to_le32(host_time),
134 FR_CZ_MC_TREG_SMEM + MC_SMEM_P0_PTP_TIME_OFST);
135 }
136
137 static int siena_ptp_set_ts_config(struct efx_nic *efx,
138 struct hwtstamp_config *init)
139 {
140 int rc;
141
142 switch (init->rx_filter) {
143 case HWTSTAMP_FILTER_NONE:
144 /* if TX timestamping is still requested then leave PTP on */
145 return efx_ptp_change_mode(efx,
146 init->tx_type != HWTSTAMP_TX_OFF,
147 efx_ptp_get_mode(efx));
148 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
149 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
150 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
151 init->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
152 return efx_ptp_change_mode(efx, true, MC_CMD_PTP_MODE_V1);
153 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
154 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
155 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
156 init->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
157 rc = efx_ptp_change_mode(efx, true,
158 MC_CMD_PTP_MODE_V2_ENHANCED);
159 /* bug 33070 - old versions of the firmware do not support the
160 * improved UUID filtering option. Similarly old versions of the
161 * application do not expect it to be enabled. If the firmware
162 * does not accept the enhanced mode, fall back to the standard
163 * PTP v2 UUID filtering. */
164 if (rc != 0)
165 rc = efx_ptp_change_mode(efx, true, MC_CMD_PTP_MODE_V2);
166 return rc;
167 default:
168 return -ERANGE;
169 }
170 }
171
172 /**************************************************************************
173 *
174 * Device reset
175 *
176 **************************************************************************
177 */
178
179 static int siena_map_reset_flags(u32 *flags)
180 {
181 enum {
182 SIENA_RESET_PORT = (ETH_RESET_DMA | ETH_RESET_FILTER |
183 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
184 ETH_RESET_PHY),
185 SIENA_RESET_MC = (SIENA_RESET_PORT |
186 ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT),
187 };
188
189 if ((*flags & SIENA_RESET_MC) == SIENA_RESET_MC) {
190 *flags &= ~SIENA_RESET_MC;
191 return RESET_TYPE_WORLD;
192 }
193
194 if ((*flags & SIENA_RESET_PORT) == SIENA_RESET_PORT) {
195 *flags &= ~SIENA_RESET_PORT;
196 return RESET_TYPE_ALL;
197 }
198
199 /* no invisible reset implemented */
200
201 return -EINVAL;
202 }
203
204 #ifdef CONFIG_EEH
205 /* When a PCI device is isolated from the bus, a subsequent MMIO read is
206 * required for the kernel EEH mechanisms to notice. As the Solarflare driver
207 * was written to minimise MMIO read (for latency) then a periodic call to check
208 * the EEH status of the device is required so that device recovery can happen
209 * in a timely fashion.
210 */
211 static void siena_monitor(struct efx_nic *efx)
212 {
213 struct eeh_dev *eehdev = pci_dev_to_eeh_dev(efx->pci_dev);
214
215 eeh_dev_check_failure(eehdev);
216 }
217 #endif
218
219 static int siena_probe_nvconfig(struct efx_nic *efx)
220 {
221 u32 caps = 0;
222 int rc;
223
224 rc = efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL, &caps);
225
226 efx->timer_quantum_ns =
227 (caps & (1 << MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN)) ?
228 3072 : 6144; /* 768 cycles */
229 efx->timer_max_ns = efx->type->timer_period_max *
230 efx->timer_quantum_ns;
231
232 return rc;
233 }
234
235 static int siena_dimension_resources(struct efx_nic *efx)
236 {
237 /* Each port has a small block of internal SRAM dedicated to
238 * the buffer table and descriptor caches. In theory we can
239 * map both blocks to one port, but we don't.
240 */
241 efx_farch_dimension_resources(efx, FR_CZ_BUF_FULL_TBL_ROWS / 2);
242 return 0;
243 }
244
245 static unsigned int siena_mem_map_size(struct efx_nic *efx)
246 {
247 return FR_CZ_MC_TREG_SMEM +
248 FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS;
249 }
250
251 static int siena_probe_nic(struct efx_nic *efx)
252 {
253 struct siena_nic_data *nic_data;
254 efx_oword_t reg;
255 int rc;
256
257 /* Allocate storage for hardware specific data */
258 nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
259 if (!nic_data)
260 return -ENOMEM;
261 nic_data->efx = efx;
262 efx->nic_data = nic_data;
263
264 if (efx_farch_fpga_ver(efx) != 0) {
265 netif_err(efx, probe, efx->net_dev,
266 "Siena FPGA not supported\n");
267 rc = -ENODEV;
268 goto fail1;
269 }
270
271 efx->max_channels = EFX_MAX_CHANNELS;
272 efx->max_tx_channels = EFX_MAX_CHANNELS;
273
274 efx_reado(efx, &reg, FR_AZ_CS_DEBUG);
275 efx->port_num = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1;
276
277 rc = efx_mcdi_init(efx);
278 if (rc)
279 goto fail1;
280
281 /* Now we can reset the NIC */
282 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
283 if (rc) {
284 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
285 goto fail3;
286 }
287
288 siena_init_wol(efx);
289
290 /* Allocate memory for INT_KER */
291 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t),
292 GFP_KERNEL);
293 if (rc)
294 goto fail4;
295 BUG_ON(efx->irq_status.dma_addr & 0x0f);
296
297 netif_dbg(efx, probe, efx->net_dev,
298 "INT_KER at %llx (virt %p phys %llx)\n",
299 (unsigned long long)efx->irq_status.dma_addr,
300 efx->irq_status.addr,
301 (unsigned long long)virt_to_phys(efx->irq_status.addr));
302
303 /* Read in the non-volatile configuration */
304 rc = siena_probe_nvconfig(efx);
305 if (rc == -EINVAL) {
306 netif_err(efx, probe, efx->net_dev,
307 "NVRAM is invalid therefore using defaults\n");
308 efx->phy_type = PHY_TYPE_NONE;
309 efx->mdio.prtad = MDIO_PRTAD_NONE;
310 } else if (rc) {
311 goto fail5;
312 }
313
314 rc = efx_mcdi_mon_probe(efx);
315 if (rc)
316 goto fail5;
317
318 #ifdef CONFIG_SFC_SRIOV
319 efx_siena_sriov_probe(efx);
320 #endif
321 efx_ptp_defer_probe_with_channel(efx);
322
323 return 0;
324
325 fail5:
326 efx_nic_free_buffer(efx, &efx->irq_status);
327 fail4:
328 fail3:
329 efx_mcdi_fini(efx);
330 fail1:
331 kfree(efx->nic_data);
332 return rc;
333 }
334
335 static int siena_rx_push_rss_config(struct efx_nic *efx, bool user,
336 const u32 *rx_indir_table)
337 {
338 efx_oword_t temp;
339
340 /* Set hash key for IPv4 */
341 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
342 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
343
344 /* Enable IPv6 RSS */
345 BUILD_BUG_ON(sizeof(efx->rx_hash_key) <
346 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 ||
347 FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0);
348 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
349 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
350 memcpy(&temp, efx->rx_hash_key + sizeof(temp), sizeof(temp));
351 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
352 EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1,
353 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1);
354 memcpy(&temp, efx->rx_hash_key + 2 * sizeof(temp),
355 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
356 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
357
358 memcpy(efx->rx_indir_table, rx_indir_table,
359 sizeof(efx->rx_indir_table));
360 efx_farch_rx_push_indir_table(efx);
361
362 return 0;
363 }
364
365 /* This call performs hardware-specific global initialisation, such as
366 * defining the descriptor cache sizes and number of RSS channels.
367 * It does not set up any buffers, descriptor rings or event queues.
368 */
369 static int siena_init_nic(struct efx_nic *efx)
370 {
371 efx_oword_t temp;
372 int rc;
373
374 /* Recover from a failed assertion post-reset */
375 rc = efx_mcdi_handle_assertion(efx);
376 if (rc)
377 return rc;
378
379 /* Squash TX of packets of 16 bytes or less */
380 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
381 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
382 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
383
384 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
385 * descriptors (which is bad).
386 */
387 efx_reado(efx, &temp, FR_AZ_TX_CFG);
388 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
389 EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
390 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
391
392 efx_reado(efx, &temp, FR_AZ_RX_CFG);
393 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
394 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
395 /* Enable hash insertion. This is broken for the 'Falcon' hash
396 * if IPv6 hashing is also enabled, so also select Toeplitz
397 * TCP/IPv4 and IPv4 hashes. */
398 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1);
399 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1);
400 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1);
401 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_USR_BUF_SIZE,
402 EFX_RX_USR_BUF_SIZE >> 5);
403 efx_writeo(efx, &temp, FR_AZ_RX_CFG);
404
405 siena_rx_push_rss_config(efx, false, efx->rx_indir_table);
406
407 /* Enable event logging */
408 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
409 if (rc)
410 return rc;
411
412 /* Set destination of both TX and RX Flush events */
413 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
414 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
415
416 EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
417 efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
418
419 efx_farch_init_common(efx);
420 return 0;
421 }
422
423 static void siena_remove_nic(struct efx_nic *efx)
424 {
425 efx_mcdi_mon_remove(efx);
426
427 efx_nic_free_buffer(efx, &efx->irq_status);
428
429 efx_mcdi_reset(efx, RESET_TYPE_ALL);
430
431 efx_mcdi_fini(efx);
432
433 /* Tear down the private nic state */
434 kfree(efx->nic_data);
435 efx->nic_data = NULL;
436 }
437
438 #define SIENA_DMA_STAT(ext_name, mcdi_name) \
439 [SIENA_STAT_ ## ext_name] = \
440 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
441 #define SIENA_OTHER_STAT(ext_name) \
442 [SIENA_STAT_ ## ext_name] = { #ext_name, 0, 0 }
443 #define GENERIC_SW_STAT(ext_name) \
444 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
445
446 static const struct efx_hw_stat_desc siena_stat_desc[SIENA_STAT_COUNT] = {
447 SIENA_DMA_STAT(tx_bytes, TX_BYTES),
448 SIENA_OTHER_STAT(tx_good_bytes),
449 SIENA_DMA_STAT(tx_bad_bytes, TX_BAD_BYTES),
450 SIENA_DMA_STAT(tx_packets, TX_PKTS),
451 SIENA_DMA_STAT(tx_bad, TX_BAD_FCS_PKTS),
452 SIENA_DMA_STAT(tx_pause, TX_PAUSE_PKTS),
453 SIENA_DMA_STAT(tx_control, TX_CONTROL_PKTS),
454 SIENA_DMA_STAT(tx_unicast, TX_UNICAST_PKTS),
455 SIENA_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS),
456 SIENA_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS),
457 SIENA_DMA_STAT(tx_lt64, TX_LT64_PKTS),
458 SIENA_DMA_STAT(tx_64, TX_64_PKTS),
459 SIENA_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS),
460 SIENA_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS),
461 SIENA_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS),
462 SIENA_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS),
463 SIENA_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
464 SIENA_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
465 SIENA_DMA_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS),
466 SIENA_OTHER_STAT(tx_collision),
467 SIENA_DMA_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS),
468 SIENA_DMA_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS),
469 SIENA_DMA_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS),
470 SIENA_DMA_STAT(tx_deferred, TX_DEFERRED_PKTS),
471 SIENA_DMA_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS),
472 SIENA_DMA_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS),
473 SIENA_DMA_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS),
474 SIENA_DMA_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS),
475 SIENA_DMA_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS),
476 SIENA_DMA_STAT(rx_bytes, RX_BYTES),
477 SIENA_OTHER_STAT(rx_good_bytes),
478 SIENA_DMA_STAT(rx_bad_bytes, RX_BAD_BYTES),
479 SIENA_DMA_STAT(rx_packets, RX_PKTS),
480 SIENA_DMA_STAT(rx_good, RX_GOOD_PKTS),
481 SIENA_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS),
482 SIENA_DMA_STAT(rx_pause, RX_PAUSE_PKTS),
483 SIENA_DMA_STAT(rx_control, RX_CONTROL_PKTS),
484 SIENA_DMA_STAT(rx_unicast, RX_UNICAST_PKTS),
485 SIENA_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS),
486 SIENA_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS),
487 SIENA_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS),
488 SIENA_DMA_STAT(rx_64, RX_64_PKTS),
489 SIENA_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS),
490 SIENA_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS),
491 SIENA_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS),
492 SIENA_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS),
493 SIENA_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
494 SIENA_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
495 SIENA_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS),
496 SIENA_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS),
497 SIENA_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS),
498 SIENA_DMA_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS),
499 SIENA_DMA_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS),
500 SIENA_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS),
501 SIENA_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS),
502 SIENA_DMA_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS),
503 SIENA_DMA_STAT(rx_nodesc_drop_cnt, RX_NODESC_DROPS),
504 GENERIC_SW_STAT(rx_nodesc_trunc),
505 GENERIC_SW_STAT(rx_noskb_drops),
506 };
507 static const unsigned long siena_stat_mask[] = {
508 [0 ... BITS_TO_LONGS(SIENA_STAT_COUNT) - 1] = ~0UL,
509 };
510
511 static size_t siena_describe_nic_stats(struct efx_nic *efx, u8 *names)
512 {
513 return efx_nic_describe_stats(siena_stat_desc, SIENA_STAT_COUNT,
514 siena_stat_mask, names);
515 }
516
517 static int siena_try_update_nic_stats(struct efx_nic *efx)
518 {
519 struct siena_nic_data *nic_data = efx->nic_data;
520 u64 *stats = nic_data->stats;
521 __le64 *dma_stats;
522 __le64 generation_start, generation_end;
523
524 dma_stats = efx->stats_buffer.addr;
525
526 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
527 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
528 return 0;
529 rmb();
530 efx_nic_update_stats(siena_stat_desc, SIENA_STAT_COUNT, siena_stat_mask,
531 stats, efx->stats_buffer.addr, false);
532 rmb();
533 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
534 if (generation_end != generation_start)
535 return -EAGAIN;
536
537 /* Update derived statistics */
538 efx_nic_fix_nodesc_drop_stat(efx,
539 &stats[SIENA_STAT_rx_nodesc_drop_cnt]);
540 efx_update_diff_stat(&stats[SIENA_STAT_tx_good_bytes],
541 stats[SIENA_STAT_tx_bytes] -
542 stats[SIENA_STAT_tx_bad_bytes]);
543 stats[SIENA_STAT_tx_collision] =
544 stats[SIENA_STAT_tx_single_collision] +
545 stats[SIENA_STAT_tx_multiple_collision] +
546 stats[SIENA_STAT_tx_excessive_collision] +
547 stats[SIENA_STAT_tx_late_collision];
548 efx_update_diff_stat(&stats[SIENA_STAT_rx_good_bytes],
549 stats[SIENA_STAT_rx_bytes] -
550 stats[SIENA_STAT_rx_bad_bytes]);
551 efx_update_sw_stats(efx, stats);
552 return 0;
553 }
554
555 static size_t siena_update_nic_stats(struct efx_nic *efx, u64 *full_stats,
556 struct rtnl_link_stats64 *core_stats)
557 {
558 struct siena_nic_data *nic_data = efx->nic_data;
559 u64 *stats = nic_data->stats;
560 int retry;
561
562 /* If we're unlucky enough to read statistics wduring the DMA, wait
563 * up to 10ms for it to finish (typically takes <500us) */
564 for (retry = 0; retry < 100; ++retry) {
565 if (siena_try_update_nic_stats(efx) == 0)
566 break;
567 udelay(100);
568 }
569
570 if (full_stats)
571 memcpy(full_stats, stats, sizeof(u64) * SIENA_STAT_COUNT);
572
573 if (core_stats) {
574 core_stats->rx_packets = stats[SIENA_STAT_rx_packets];
575 core_stats->tx_packets = stats[SIENA_STAT_tx_packets];
576 core_stats->rx_bytes = stats[SIENA_STAT_rx_bytes];
577 core_stats->tx_bytes = stats[SIENA_STAT_tx_bytes];
578 core_stats->rx_dropped = stats[SIENA_STAT_rx_nodesc_drop_cnt] +
579 stats[GENERIC_STAT_rx_nodesc_trunc] +
580 stats[GENERIC_STAT_rx_noskb_drops];
581 core_stats->multicast = stats[SIENA_STAT_rx_multicast];
582 core_stats->collisions = stats[SIENA_STAT_tx_collision];
583 core_stats->rx_length_errors =
584 stats[SIENA_STAT_rx_gtjumbo] +
585 stats[SIENA_STAT_rx_length_error];
586 core_stats->rx_crc_errors = stats[SIENA_STAT_rx_bad];
587 core_stats->rx_frame_errors = stats[SIENA_STAT_rx_align_error];
588 core_stats->rx_fifo_errors = stats[SIENA_STAT_rx_overflow];
589 core_stats->tx_window_errors =
590 stats[SIENA_STAT_tx_late_collision];
591
592 core_stats->rx_errors = (core_stats->rx_length_errors +
593 core_stats->rx_crc_errors +
594 core_stats->rx_frame_errors +
595 stats[SIENA_STAT_rx_symbol_error]);
596 core_stats->tx_errors = (core_stats->tx_window_errors +
597 stats[SIENA_STAT_tx_bad]);
598 }
599
600 return SIENA_STAT_COUNT;
601 }
602
603 static int siena_mac_reconfigure(struct efx_nic *efx)
604 {
605 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_MCAST_HASH_IN_LEN);
606 int rc;
607
608 BUILD_BUG_ON(MC_CMD_SET_MCAST_HASH_IN_LEN !=
609 MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST +
610 sizeof(efx->multicast_hash));
611
612 efx_farch_filter_sync_rx_mode(efx);
613
614 WARN_ON(!mutex_is_locked(&efx->mac_lock));
615
616 rc = efx_mcdi_set_mac(efx);
617 if (rc != 0)
618 return rc;
619
620 memcpy(MCDI_PTR(inbuf, SET_MCAST_HASH_IN_HASH0),
621 efx->multicast_hash.byte, sizeof(efx->multicast_hash));
622 return efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH,
623 inbuf, sizeof(inbuf), NULL, 0, NULL);
624 }
625
626 /**************************************************************************
627 *
628 * Wake on LAN
629 *
630 **************************************************************************
631 */
632
633 static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
634 {
635 struct siena_nic_data *nic_data = efx->nic_data;
636
637 wol->supported = WAKE_MAGIC;
638 if (nic_data->wol_filter_id != -1)
639 wol->wolopts = WAKE_MAGIC;
640 else
641 wol->wolopts = 0;
642 memset(&wol->sopass, 0, sizeof(wol->sopass));
643 }
644
645
646 static int siena_set_wol(struct efx_nic *efx, u32 type)
647 {
648 struct siena_nic_data *nic_data = efx->nic_data;
649 int rc;
650
651 if (type & ~WAKE_MAGIC)
652 return -EINVAL;
653
654 if (type & WAKE_MAGIC) {
655 if (nic_data->wol_filter_id != -1)
656 efx_mcdi_wol_filter_remove(efx,
657 nic_data->wol_filter_id);
658 rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr,
659 &nic_data->wol_filter_id);
660 if (rc)
661 goto fail;
662
663 pci_wake_from_d3(efx->pci_dev, true);
664 } else {
665 rc = efx_mcdi_wol_filter_reset(efx);
666 nic_data->wol_filter_id = -1;
667 pci_wake_from_d3(efx->pci_dev, false);
668 if (rc)
669 goto fail;
670 }
671
672 return 0;
673 fail:
674 netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n",
675 __func__, type, rc);
676 return rc;
677 }
678
679
680 static void siena_init_wol(struct efx_nic *efx)
681 {
682 struct siena_nic_data *nic_data = efx->nic_data;
683 int rc;
684
685 rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
686
687 if (rc != 0) {
688 /* If it failed, attempt to get into a synchronised
689 * state with MC by resetting any set WoL filters */
690 efx_mcdi_wol_filter_reset(efx);
691 nic_data->wol_filter_id = -1;
692 } else if (nic_data->wol_filter_id != -1) {
693 pci_wake_from_d3(efx->pci_dev, true);
694 }
695 }
696
697 /**************************************************************************
698 *
699 * MCDI
700 *
701 **************************************************************************
702 */
703
704 #define MCDI_PDU(efx) \
705 (efx_port_num(efx) ? MC_SMEM_P1_PDU_OFST : MC_SMEM_P0_PDU_OFST)
706 #define MCDI_DOORBELL(efx) \
707 (efx_port_num(efx) ? MC_SMEM_P1_DOORBELL_OFST : MC_SMEM_P0_DOORBELL_OFST)
708 #define MCDI_STATUS(efx) \
709 (efx_port_num(efx) ? MC_SMEM_P1_STATUS_OFST : MC_SMEM_P0_STATUS_OFST)
710
711 static void siena_mcdi_request(struct efx_nic *efx,
712 const efx_dword_t *hdr, size_t hdr_len,
713 const efx_dword_t *sdu, size_t sdu_len)
714 {
715 unsigned pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
716 unsigned doorbell = FR_CZ_MC_TREG_SMEM + MCDI_DOORBELL(efx);
717 unsigned int i;
718 unsigned int inlen_dw = DIV_ROUND_UP(sdu_len, 4);
719
720 EFX_WARN_ON_PARANOID(hdr_len != 4);
721
722 efx_writed(efx, hdr, pdu);
723
724 for (i = 0; i < inlen_dw; i++)
725 efx_writed(efx, &sdu[i], pdu + hdr_len + 4 * i);
726
727 /* Ensure the request is written out before the doorbell */
728 wmb();
729
730 /* ring the doorbell with a distinctive value */
731 _efx_writed(efx, (__force __le32) 0x45789abc, doorbell);
732 }
733
734 static bool siena_mcdi_poll_response(struct efx_nic *efx)
735 {
736 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
737 efx_dword_t hdr;
738
739 efx_readd(efx, &hdr, pdu);
740
741 /* All 1's indicates that shared memory is in reset (and is
742 * not a valid hdr). Wait for it to come out reset before
743 * completing the command
744 */
745 return EFX_DWORD_FIELD(hdr, EFX_DWORD_0) != 0xffffffff &&
746 EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
747 }
748
749 static void siena_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
750 size_t offset, size_t outlen)
751 {
752 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
753 unsigned int outlen_dw = DIV_ROUND_UP(outlen, 4);
754 int i;
755
756 for (i = 0; i < outlen_dw; i++)
757 efx_readd(efx, &outbuf[i], pdu + offset + 4 * i);
758 }
759
760 static int siena_mcdi_poll_reboot(struct efx_nic *efx)
761 {
762 struct siena_nic_data *nic_data = efx->nic_data;
763 unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_STATUS(efx);
764 efx_dword_t reg;
765 u32 value;
766
767 efx_readd(efx, &reg, addr);
768 value = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
769
770 if (value == 0)
771 return 0;
772
773 EFX_ZERO_DWORD(reg);
774 efx_writed(efx, &reg, addr);
775
776 /* MAC statistics have been cleared on the NIC; clear the local
777 * copies that we update with efx_update_diff_stat().
778 */
779 nic_data->stats[SIENA_STAT_tx_good_bytes] = 0;
780 nic_data->stats[SIENA_STAT_rx_good_bytes] = 0;
781
782 if (value == MC_STATUS_DWORD_ASSERT)
783 return -EINTR;
784 else
785 return -EIO;
786 }
787
788 /**************************************************************************
789 *
790 * MTD
791 *
792 **************************************************************************
793 */
794
795 #ifdef CONFIG_SFC_MTD
796
797 struct siena_nvram_type_info {
798 int port;
799 const char *name;
800 };
801
802 static const struct siena_nvram_type_info siena_nvram_types[] = {
803 [MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO] = { 0, "sfc_dummy_phy" },
804 [MC_CMD_NVRAM_TYPE_MC_FW] = { 0, "sfc_mcfw" },
805 [MC_CMD_NVRAM_TYPE_MC_FW_BACKUP] = { 0, "sfc_mcfw_backup" },
806 [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0] = { 0, "sfc_static_cfg" },
807 [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1] = { 1, "sfc_static_cfg" },
808 [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0] = { 0, "sfc_dynamic_cfg" },
809 [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1] = { 1, "sfc_dynamic_cfg" },
810 [MC_CMD_NVRAM_TYPE_EXP_ROM] = { 0, "sfc_exp_rom" },
811 [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0] = { 0, "sfc_exp_rom_cfg" },
812 [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1] = { 1, "sfc_exp_rom_cfg" },
813 [MC_CMD_NVRAM_TYPE_PHY_PORT0] = { 0, "sfc_phy_fw" },
814 [MC_CMD_NVRAM_TYPE_PHY_PORT1] = { 1, "sfc_phy_fw" },
815 [MC_CMD_NVRAM_TYPE_FPGA] = { 0, "sfc_fpga" },
816 };
817
818 static int siena_mtd_probe_partition(struct efx_nic *efx,
819 struct efx_mcdi_mtd_partition *part,
820 unsigned int type)
821 {
822 const struct siena_nvram_type_info *info;
823 size_t size, erase_size;
824 bool protected;
825 int rc;
826
827 if (type >= ARRAY_SIZE(siena_nvram_types) ||
828 siena_nvram_types[type].name == NULL)
829 return -ENODEV;
830
831 info = &siena_nvram_types[type];
832
833 if (info->port != efx_port_num(efx))
834 return -ENODEV;
835
836 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
837 if (rc)
838 return rc;
839 if (protected)
840 return -ENODEV; /* hide it */
841
842 part->nvram_type = type;
843 part->common.dev_type_name = "Siena NVRAM manager";
844 part->common.type_name = info->name;
845
846 part->common.mtd.type = MTD_NORFLASH;
847 part->common.mtd.flags = MTD_CAP_NORFLASH;
848 part->common.mtd.size = size;
849 part->common.mtd.erasesize = erase_size;
850
851 return 0;
852 }
853
854 static int siena_mtd_get_fw_subtypes(struct efx_nic *efx,
855 struct efx_mcdi_mtd_partition *parts,
856 size_t n_parts)
857 {
858 uint16_t fw_subtype_list[
859 MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM];
860 size_t i;
861 int rc;
862
863 rc = efx_mcdi_get_board_cfg(efx, NULL, fw_subtype_list, NULL);
864 if (rc)
865 return rc;
866
867 for (i = 0; i < n_parts; i++)
868 parts[i].fw_subtype = fw_subtype_list[parts[i].nvram_type];
869
870 return 0;
871 }
872
873 static int siena_mtd_probe(struct efx_nic *efx)
874 {
875 struct efx_mcdi_mtd_partition *parts;
876 u32 nvram_types;
877 unsigned int type;
878 size_t n_parts;
879 int rc;
880
881 ASSERT_RTNL();
882
883 rc = efx_mcdi_nvram_types(efx, &nvram_types);
884 if (rc)
885 return rc;
886
887 parts = kcalloc(hweight32(nvram_types), sizeof(*parts), GFP_KERNEL);
888 if (!parts)
889 return -ENOMEM;
890
891 type = 0;
892 n_parts = 0;
893
894 while (nvram_types != 0) {
895 if (nvram_types & 1) {
896 rc = siena_mtd_probe_partition(efx, &parts[n_parts],
897 type);
898 if (rc == 0)
899 n_parts++;
900 else if (rc != -ENODEV)
901 goto fail;
902 }
903 type++;
904 nvram_types >>= 1;
905 }
906
907 rc = siena_mtd_get_fw_subtypes(efx, parts, n_parts);
908 if (rc)
909 goto fail;
910
911 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
912 fail:
913 if (rc)
914 kfree(parts);
915 return rc;
916 }
917
918 #endif /* CONFIG_SFC_MTD */
919
920 /**************************************************************************
921 *
922 * Revision-dependent attributes used by efx.c and nic.c
923 *
924 **************************************************************************
925 */
926
927 const struct efx_nic_type siena_a0_nic_type = {
928 .is_vf = false,
929 .mem_bar = EFX_MEM_BAR,
930 .mem_map_size = siena_mem_map_size,
931 .probe = siena_probe_nic,
932 .remove = siena_remove_nic,
933 .init = siena_init_nic,
934 .dimension_resources = siena_dimension_resources,
935 .fini = efx_port_dummy_op_void,
936 #ifdef CONFIG_EEH
937 .monitor = siena_monitor,
938 #else
939 .monitor = NULL,
940 #endif
941 .map_reset_reason = efx_mcdi_map_reset_reason,
942 .map_reset_flags = siena_map_reset_flags,
943 .reset = efx_mcdi_reset,
944 .probe_port = efx_mcdi_port_probe,
945 .remove_port = efx_mcdi_port_remove,
946 .fini_dmaq = efx_farch_fini_dmaq,
947 .prepare_flush = siena_prepare_flush,
948 .finish_flush = siena_finish_flush,
949 .prepare_flr = efx_port_dummy_op_void,
950 .finish_flr = efx_farch_finish_flr,
951 .describe_stats = siena_describe_nic_stats,
952 .update_stats = siena_update_nic_stats,
953 .start_stats = efx_mcdi_mac_start_stats,
954 .pull_stats = efx_mcdi_mac_pull_stats,
955 .stop_stats = efx_mcdi_mac_stop_stats,
956 .set_id_led = efx_mcdi_set_id_led,
957 .push_irq_moderation = siena_push_irq_moderation,
958 .reconfigure_mac = siena_mac_reconfigure,
959 .check_mac_fault = efx_mcdi_mac_check_fault,
960 .reconfigure_port = efx_mcdi_port_reconfigure,
961 .get_wol = siena_get_wol,
962 .set_wol = siena_set_wol,
963 .resume_wol = siena_init_wol,
964 .test_chip = siena_test_chip,
965 .test_nvram = efx_mcdi_nvram_test_all,
966 .mcdi_request = siena_mcdi_request,
967 .mcdi_poll_response = siena_mcdi_poll_response,
968 .mcdi_read_response = siena_mcdi_read_response,
969 .mcdi_poll_reboot = siena_mcdi_poll_reboot,
970 .irq_enable_master = efx_farch_irq_enable_master,
971 .irq_test_generate = efx_farch_irq_test_generate,
972 .irq_disable_non_ev = efx_farch_irq_disable_master,
973 .irq_handle_msi = efx_farch_msi_interrupt,
974 .irq_handle_legacy = efx_farch_legacy_interrupt,
975 .tx_probe = efx_farch_tx_probe,
976 .tx_init = efx_farch_tx_init,
977 .tx_remove = efx_farch_tx_remove,
978 .tx_write = efx_farch_tx_write,
979 .tx_limit_len = efx_farch_tx_limit_len,
980 .rx_push_rss_config = siena_rx_push_rss_config,
981 .rx_probe = efx_farch_rx_probe,
982 .rx_init = efx_farch_rx_init,
983 .rx_remove = efx_farch_rx_remove,
984 .rx_write = efx_farch_rx_write,
985 .rx_defer_refill = efx_farch_rx_defer_refill,
986 .ev_probe = efx_farch_ev_probe,
987 .ev_init = efx_farch_ev_init,
988 .ev_fini = efx_farch_ev_fini,
989 .ev_remove = efx_farch_ev_remove,
990 .ev_process = efx_farch_ev_process,
991 .ev_read_ack = efx_farch_ev_read_ack,
992 .ev_test_generate = efx_farch_ev_test_generate,
993 .filter_table_probe = efx_farch_filter_table_probe,
994 .filter_table_restore = efx_farch_filter_table_restore,
995 .filter_table_remove = efx_farch_filter_table_remove,
996 .filter_update_rx_scatter = efx_farch_filter_update_rx_scatter,
997 .filter_insert = efx_farch_filter_insert,
998 .filter_remove_safe = efx_farch_filter_remove_safe,
999 .filter_get_safe = efx_farch_filter_get_safe,
1000 .filter_clear_rx = efx_farch_filter_clear_rx,
1001 .filter_count_rx_used = efx_farch_filter_count_rx_used,
1002 .filter_get_rx_id_limit = efx_farch_filter_get_rx_id_limit,
1003 .filter_get_rx_ids = efx_farch_filter_get_rx_ids,
1004 #ifdef CONFIG_RFS_ACCEL
1005 .filter_rfs_insert = efx_farch_filter_rfs_insert,
1006 .filter_rfs_expire_one = efx_farch_filter_rfs_expire_one,
1007 #endif
1008 #ifdef CONFIG_SFC_MTD
1009 .mtd_probe = siena_mtd_probe,
1010 .mtd_rename = efx_mcdi_mtd_rename,
1011 .mtd_read = efx_mcdi_mtd_read,
1012 .mtd_erase = efx_mcdi_mtd_erase,
1013 .mtd_write = efx_mcdi_mtd_write,
1014 .mtd_sync = efx_mcdi_mtd_sync,
1015 #endif
1016 .ptp_write_host_time = siena_ptp_write_host_time,
1017 .ptp_set_ts_config = siena_ptp_set_ts_config,
1018 #ifdef CONFIG_SFC_SRIOV
1019 .sriov_configure = efx_siena_sriov_configure,
1020 .sriov_init = efx_siena_sriov_init,
1021 .sriov_fini = efx_siena_sriov_fini,
1022 .sriov_wanted = efx_siena_sriov_wanted,
1023 .sriov_reset = efx_siena_sriov_reset,
1024 .sriov_flr = efx_siena_sriov_flr,
1025 .sriov_set_vf_mac = efx_siena_sriov_set_vf_mac,
1026 .sriov_set_vf_vlan = efx_siena_sriov_set_vf_vlan,
1027 .sriov_set_vf_spoofchk = efx_siena_sriov_set_vf_spoofchk,
1028 .sriov_get_vf_config = efx_siena_sriov_get_vf_config,
1029 .vswitching_probe = efx_port_dummy_op_int,
1030 .vswitching_restore = efx_port_dummy_op_int,
1031 .vswitching_remove = efx_port_dummy_op_void,
1032 .set_mac_address = efx_siena_sriov_mac_address_changed,
1033 #endif
1034
1035 .revision = EFX_REV_SIENA_A0,
1036 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
1037 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
1038 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
1039 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
1040 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
1041 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
1042 .rx_prefix_size = FS_BZ_RX_PREFIX_SIZE,
1043 .rx_hash_offset = FS_BZ_RX_PREFIX_HASH_OFST,
1044 .rx_buffer_padding = 0,
1045 .can_rx_scatter = true,
1046 .max_interrupt_mode = EFX_INT_MODE_MSIX,
1047 .timer_period_max = 1 << FRF_CZ_TC_TIMER_VAL_WIDTH,
1048 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1049 NETIF_F_RXHASH | NETIF_F_NTUPLE),
1050 .mcdi_max_ver = 1,
1051 .max_rx_ip_filters = FR_BZ_RX_FILTER_TBL0_ROWS,
1052 .hwtstamp_filters = (1 << HWTSTAMP_FILTER_NONE |
1053 1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT |
1054 1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT),
1055 };
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