drivers/net/ethernet/stmicro/stmmac/common.h

   1 /*******************************************************************************
   2   STMMAC Common Header File
   3
   4   Copyright (C) 2007-2009  STMicroelectronics Ltd
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  23 *******************************************************************************/
  24
  25 #ifndef __COMMON_H__
  26 #define __COMMON_H__
  27
  28 #include <linux/etherdevice.h>
  29 #include <linux/netdevice.h>
  30 #include <linux/stmmac.h>
  31 #include <linux/phy.h>
  32 #include <linux/module.h>
  33 #if IS_ENABLED(CONFIG_VLAN_8021Q)
  34 #define STMMAC_VLAN_TAG_USED
  35 #include <linux/if_vlan.h>
  36 #endif
  37
  38 #include "descs.h"
  39 #include "mmc.h"
  40
  41 /* Synopsys Core versions */
  42 #define DWMAC_CORE_3_40 0x34
  43 #define DWMAC_CORE_3_50 0x35
  44 #define DWMAC_CORE_4_00 0x40
  45 #define STMMAC_CHAN0    0       /* Always supported and default for all chips */
  46
  47 /* These need to be power of two, and >= 4 */
  48 #define DMA_TX_SIZE 512
  49 #define DMA_RX_SIZE 512
  50 #define STMMAC_GET_ENTRY(x, size)       ((x + 1) & (size - 1))
  51
  52 #undef FRAME_FILTER_DEBUG
  53 /* #define FRAME_FILTER_DEBUG */
  54
  55 /* Extra statistic and debug information exposed by ethtool */
  56 struct stmmac_extra_stats {
  57         /* Transmit errors */
  58         unsigned long tx_underflow ____cacheline_aligned;
  59         unsigned long tx_carrier;
  60         unsigned long tx_losscarrier;
  61         unsigned long vlan_tag;
  62         unsigned long tx_deferred;
  63         unsigned long tx_vlan;
  64         unsigned long tx_jabber;
  65         unsigned long tx_frame_flushed;
  66         unsigned long tx_payload_error;
  67         unsigned long tx_ip_header_error;
  68         /* Receive errors */
  69         unsigned long rx_desc;
  70         unsigned long sa_filter_fail;
  71         unsigned long overflow_error;
  72         unsigned long ipc_csum_error;
  73         unsigned long rx_collision;
  74         unsigned long rx_crc;
  75         unsigned long dribbling_bit;
  76         unsigned long rx_length;
  77         unsigned long rx_mii;
  78         unsigned long rx_multicast;
  79         unsigned long rx_gmac_overflow;
  80         unsigned long rx_watchdog;
  81         unsigned long da_rx_filter_fail;
  82         unsigned long sa_rx_filter_fail;
  83         unsigned long rx_missed_cntr;
  84         unsigned long rx_overflow_cntr;
  85         unsigned long rx_vlan;
  86         /* Tx/Rx IRQ error info */
  87         unsigned long tx_undeflow_irq;
  88         unsigned long tx_process_stopped_irq;
  89         unsigned long tx_jabber_irq;
  90         unsigned long rx_overflow_irq;
  91         unsigned long rx_buf_unav_irq;
  92         unsigned long rx_process_stopped_irq;
  93         unsigned long rx_watchdog_irq;
  94         unsigned long tx_early_irq;
  95         unsigned long fatal_bus_error_irq;
  96         /* Tx/Rx IRQ Events */
  97         unsigned long rx_early_irq;
  98         unsigned long threshold;
  99         unsigned long tx_pkt_n;
 100         unsigned long rx_pkt_n;
 101         unsigned long normal_irq_n;
 102         unsigned long rx_normal_irq_n;
 103         unsigned long napi_poll;
 104         unsigned long tx_normal_irq_n;
 105         unsigned long tx_clean;
 106         unsigned long tx_set_ic_bit;
 107         unsigned long irq_receive_pmt_irq_n;
 108         /* MMC info */
 109         unsigned long mmc_tx_irq_n;
 110         unsigned long mmc_rx_irq_n;
 111         unsigned long mmc_rx_csum_offload_irq_n;
 112         /* EEE */
 113         unsigned long irq_tx_path_in_lpi_mode_n;
 114         unsigned long irq_tx_path_exit_lpi_mode_n;
 115         unsigned long irq_rx_path_in_lpi_mode_n;
 116         unsigned long irq_rx_path_exit_lpi_mode_n;
 117         unsigned long phy_eee_wakeup_error_n;
 118         /* Extended RDES status */
 119         unsigned long ip_hdr_err;
 120         unsigned long ip_payload_err;
 121         unsigned long ip_csum_bypassed;
 122         unsigned long ipv4_pkt_rcvd;
 123         unsigned long ipv6_pkt_rcvd;
 124         unsigned long no_ptp_rx_msg_type_ext;
 125         unsigned long ptp_rx_msg_type_sync;
 126         unsigned long ptp_rx_msg_type_follow_up;
 127         unsigned long ptp_rx_msg_type_delay_req;
 128         unsigned long ptp_rx_msg_type_delay_resp;
 129         unsigned long ptp_rx_msg_type_pdelay_req;
 130         unsigned long ptp_rx_msg_type_pdelay_resp;
 131         unsigned long ptp_rx_msg_type_pdelay_follow_up;
 132         unsigned long ptp_rx_msg_type_announce;
 133         unsigned long ptp_rx_msg_type_management;
 134         unsigned long ptp_rx_msg_pkt_reserved_type;
 135         unsigned long ptp_frame_type;
 136         unsigned long ptp_ver;
 137         unsigned long timestamp_dropped;
 138         unsigned long av_pkt_rcvd;
 139         unsigned long av_tagged_pkt_rcvd;
 140         unsigned long vlan_tag_priority_val;
 141         unsigned long l3_filter_match;
 142         unsigned long l4_filter_match;
 143         unsigned long l3_l4_filter_no_match;
 144         /* PCS */
 145         unsigned long irq_pcs_ane_n;
 146         unsigned long irq_pcs_link_n;
 147         unsigned long irq_rgmii_n;
 148         unsigned long pcs_link;
 149         unsigned long pcs_duplex;
 150         unsigned long pcs_speed;
 151         /* debug register */
 152         unsigned long mtl_tx_status_fifo_full;
 153         unsigned long mtl_tx_fifo_not_empty;
 154         unsigned long mmtl_fifo_ctrl;
 155         unsigned long mtl_tx_fifo_read_ctrl_write;
 156         unsigned long mtl_tx_fifo_read_ctrl_wait;
 157         unsigned long mtl_tx_fifo_read_ctrl_read;
 158         unsigned long mtl_tx_fifo_read_ctrl_idle;
 159         unsigned long mac_tx_in_pause;
 160         unsigned long mac_tx_frame_ctrl_xfer;
 161         unsigned long mac_tx_frame_ctrl_idle;
 162         unsigned long mac_tx_frame_ctrl_wait;
 163         unsigned long mac_tx_frame_ctrl_pause;
 164         unsigned long mac_gmii_tx_proto_engine;
 165         unsigned long mtl_rx_fifo_fill_level_full;
 166         unsigned long mtl_rx_fifo_fill_above_thresh;
 167         unsigned long mtl_rx_fifo_fill_below_thresh;
 168         unsigned long mtl_rx_fifo_fill_level_empty;
 169         unsigned long mtl_rx_fifo_read_ctrl_flush;
 170         unsigned long mtl_rx_fifo_read_ctrl_read_data;
 171         unsigned long mtl_rx_fifo_read_ctrl_status;
 172         unsigned long mtl_rx_fifo_read_ctrl_idle;
 173         unsigned long mtl_rx_fifo_ctrl_active;
 174         unsigned long mac_rx_frame_ctrl_fifo;
 175         unsigned long mac_gmii_rx_proto_engine;
 176         /* TSO */
 177         unsigned long tx_tso_frames;
 178         unsigned long tx_tso_nfrags;
 179 };
 180
 181 /* CSR Frequency Access Defines*/
 182 #define CSR_F_35M       35000000
 183 #define CSR_F_60M       60000000
 184 #define CSR_F_100M      100000000
 185 #define CSR_F_150M      150000000
 186 #define CSR_F_250M      250000000
 187 #define CSR_F_300M      300000000
 188
 189 #define MAC_CSR_H_FRQ_MASK      0x20
 190
 191 #define HASH_TABLE_SIZE 64
 192 #define PAUSE_TIME 0xffff
 193
 194 /* Flow Control defines */
 195 #define FLOW_OFF        0
 196 #define FLOW_RX         1
 197 #define FLOW_TX         2
 198 #define FLOW_AUTO       (FLOW_TX | FLOW_RX)
 199
 200 /* PCS defines */
 201 #define STMMAC_PCS_RGMII        (1 << 0)
 202 #define STMMAC_PCS_SGMII        (1 << 1)
 203 #define STMMAC_PCS_TBI          (1 << 2)
 204 #define STMMAC_PCS_RTBI         (1 << 3)
 205
 206 #define SF_DMA_MODE 1           /* DMA STORE-AND-FORWARD Operation Mode */
 207
 208 /* DAM HW feature register fields */
 209 #define DMA_HW_FEAT_MIISEL      0x00000001      /* 10/100 Mbps Support */
 210 #define DMA_HW_FEAT_GMIISEL     0x00000002      /* 1000 Mbps Support */
 211 #define DMA_HW_FEAT_HDSEL       0x00000004      /* Half-Duplex Support */
 212 #define DMA_HW_FEAT_EXTHASHEN   0x00000008      /* Expanded DA Hash Filter */
 213 #define DMA_HW_FEAT_HASHSEL     0x00000010      /* HASH Filter */
 214 #define DMA_HW_FEAT_ADDMAC      0x00000020      /* Multiple MAC Addr Reg */
 215 #define DMA_HW_FEAT_PCSSEL      0x00000040      /* PCS registers */
 216 #define DMA_HW_FEAT_L3L4FLTREN  0x00000080      /* Layer 3 & Layer 4 Feature */
 217 #define DMA_HW_FEAT_SMASEL      0x00000100      /* SMA(MDIO) Interface */
 218 #define DMA_HW_FEAT_RWKSEL      0x00000200      /* PMT Remote Wakeup */
 219 #define DMA_HW_FEAT_MGKSEL      0x00000400      /* PMT Magic Packet */
 220 #define DMA_HW_FEAT_MMCSEL      0x00000800      /* RMON Module */
 221 #define DMA_HW_FEAT_TSVER1SEL   0x00001000      /* Only IEEE 1588-2002 */
 222 #define DMA_HW_FEAT_TSVER2SEL   0x00002000      /* IEEE 1588-2008 PTPv2 */
 223 #define DMA_HW_FEAT_EEESEL      0x00004000      /* Energy Efficient Ethernet */
 224 #define DMA_HW_FEAT_AVSEL       0x00008000      /* AV Feature */
 225 #define DMA_HW_FEAT_TXCOESEL    0x00010000      /* Checksum Offload in Tx */
 226 #define DMA_HW_FEAT_RXTYP1COE   0x00020000      /* IP COE (Type 1) in Rx */
 227 #define DMA_HW_FEAT_RXTYP2COE   0x00040000      /* IP COE (Type 2) in Rx */
 228 #define DMA_HW_FEAT_RXFIFOSIZE  0x00080000      /* Rx FIFO > 2048 Bytes */
 229 #define DMA_HW_FEAT_RXCHCNT     0x00300000      /* No. additional Rx Channels */
 230 #define DMA_HW_FEAT_TXCHCNT     0x00c00000      /* No. additional Tx Channels */
 231 #define DMA_HW_FEAT_ENHDESSEL   0x01000000      /* Alternate Descriptor */
 232 /* Timestamping with Internal System Time */
 233 #define DMA_HW_FEAT_INTTSEN     0x02000000
 234 #define DMA_HW_FEAT_FLEXIPPSEN  0x04000000      /* Flexible PPS Output */
 235 #define DMA_HW_FEAT_SAVLANINS   0x08000000      /* Source Addr or VLAN */
 236 #define DMA_HW_FEAT_ACTPHYIF    0x70000000      /* Active/selected PHY iface */
 237 #define DEFAULT_DMA_PBL         8
 238
 239 /* PCS status and mask defines */
 240 #define PCS_ANE_IRQ             BIT(2)  /* PCS Auto-Negotiation */
 241 #define PCS_LINK_IRQ            BIT(1)  /* PCS Link */
 242 #define PCS_RGSMIIIS_IRQ        BIT(0)  /* RGMII or SMII Interrupt */
 243
 244 /* Max/Min RI Watchdog Timer count value */
 245 #define MAX_DMA_RIWT            0xff
 246 #define MIN_DMA_RIWT            0x20
 247 /* Tx coalesce parameters */
 248 #define STMMAC_COAL_TX_TIMER    40000
 249 #define STMMAC_MAX_COAL_TX_TICK 100000
 250 #define STMMAC_TX_MAX_FRAMES    256
 251 #define STMMAC_TX_FRAMES        64
 252
 253 /* Rx IPC status */
 254 enum rx_frame_status {
 255         good_frame = 0x0,
 256         discard_frame = 0x1,
 257         csum_none = 0x2,
 258         llc_snap = 0x4,
 259         dma_own = 0x8,
 260         rx_not_ls = 0x10,
 261 };
 262
 263 /* Tx status */
 264 enum tx_frame_status {
 265         tx_done = 0x0,
 266         tx_not_ls = 0x1,
 267         tx_err = 0x2,
 268         tx_dma_own = 0x4,
 269 };
 270
 271 enum dma_irq_status {
 272         tx_hard_error = 0x1,
 273         tx_hard_error_bump_tc = 0x2,
 274         handle_rx = 0x4,
 275         handle_tx = 0x8,
 276 };
 277
 278 /* EEE and LPI defines */
 279 #define CORE_IRQ_TX_PATH_IN_LPI_MODE    (1 << 0)
 280 #define CORE_IRQ_TX_PATH_EXIT_LPI_MODE  (1 << 1)
 281 #define CORE_IRQ_RX_PATH_IN_LPI_MODE    (1 << 2)
 282 #define CORE_IRQ_RX_PATH_EXIT_LPI_MODE  (1 << 3)
 283
 284 #define CORE_IRQ_MTL_RX_OVERFLOW        BIT(8)
 285
 286 /* Physical Coding Sublayer */
 287 struct rgmii_adv {
 288         unsigned int pause;
 289         unsigned int duplex;
 290         unsigned int lp_pause;
 291         unsigned int lp_duplex;
 292 };
 293
 294 #define STMMAC_PCS_PAUSE        1
 295 #define STMMAC_PCS_ASYM_PAUSE   2
 296
 297 /* DMA HW capabilities */
 298 struct dma_features {
 299         unsigned int mbps_10_100;
 300         unsigned int mbps_1000;
 301         unsigned int half_duplex;
 302         unsigned int hash_filter;
 303         unsigned int multi_addr;
 304         unsigned int pcs;
 305         unsigned int sma_mdio;
 306         unsigned int pmt_remote_wake_up;
 307         unsigned int pmt_magic_frame;
 308         unsigned int rmon;
 309         /* IEEE 1588-2002 */
 310         unsigned int time_stamp;
 311         /* IEEE 1588-2008 */
 312         unsigned int atime_stamp;
 313         /* 802.3az - Energy-Efficient Ethernet (EEE) */
 314         unsigned int eee;
 315         unsigned int av;
 316         unsigned int tsoen;
 317         /* TX and RX csum */
 318         unsigned int tx_coe;
 319         unsigned int rx_coe;
 320         unsigned int rx_coe_type1;
 321         unsigned int rx_coe_type2;
 322         unsigned int rxfifo_over_2048;
 323         /* TX and RX number of channels */
 324         unsigned int number_rx_channel;
 325         unsigned int number_tx_channel;
 326         /* Alternate (enhanced) DESC mode */
 327         unsigned int enh_desc;
 328 };
 329
 330 /* GMAC TX FIFO is 8K, Rx FIFO is 16K */
 331 #define BUF_SIZE_16KiB 16384
 332 #define BUF_SIZE_8KiB 8192
 333 #define BUF_SIZE_4KiB 4096
 334 #define BUF_SIZE_2KiB 2048
 335
 336 /* Power Down and WOL */
 337 #define PMT_NOT_SUPPORTED 0
 338 #define PMT_SUPPORTED 1
 339
 340 /* Common MAC defines */
 341 #define MAC_CTRL_REG            0x00000000      /* MAC Control */
 342 #define MAC_ENABLE_TX           0x00000008      /* Transmitter Enable */
 343 #define MAC_RNABLE_RX           0x00000004      /* Receiver Enable */
 344
 345 /* Default LPI timers */
 346 #define STMMAC_DEFAULT_LIT_LS   0x3E8
 347 #define STMMAC_DEFAULT_TWT_LS   0x1E
 348
 349 #define STMMAC_CHAIN_MODE       0x1
 350 #define STMMAC_RING_MODE        0x2
 351
 352 #define JUMBO_LEN               9000
 353
 354 /* Descriptors helpers */
 355 struct stmmac_desc_ops {
 356         /* DMA RX descriptor ring initialization */
 357         void (*init_rx_desc) (struct dma_desc *p, int disable_rx_ic, int mode,
 358                               int end);
 359         /* DMA TX descriptor ring initialization */
 360         void (*init_tx_desc) (struct dma_desc *p, int mode, int end);
 361
 362         /* Invoked by the xmit function to prepare the tx descriptor */
 363         void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
 364                                  bool csum_flag, int mode, bool tx_own,
 365                                  bool ls);
 366         void (*prepare_tso_tx_desc)(struct dma_desc *p, int is_fs, int len1,
 367                                     int len2, bool tx_own, bool ls,
 368                                     unsigned int tcphdrlen,
 369                                     unsigned int tcppayloadlen);
 370         /* Set/get the owner of the descriptor */
 371         void (*set_tx_owner) (struct dma_desc *p);
 372         int (*get_tx_owner) (struct dma_desc *p);
 373         /* Clean the tx descriptor as soon as the tx irq is received */
 374         void (*release_tx_desc) (struct dma_desc *p, int mode);
 375         /* Clear interrupt on tx frame completion. When this bit is
 376          * set an interrupt happens as soon as the frame is transmitted */
 377         void (*set_tx_ic)(struct dma_desc *p);
 378         /* Last tx segment reports the transmit status */
 379         int (*get_tx_ls) (struct dma_desc *p);
 380         /* Return the transmit status looking at the TDES1 */
 381         int (*tx_status) (void *data, struct stmmac_extra_stats *x,
 382                           struct dma_desc *p, void __iomem *ioaddr);
 383         /* Get the buffer size from the descriptor */
 384         int (*get_tx_len) (struct dma_desc *p);
 385         /* Handle extra events on specific interrupts hw dependent */
 386         void (*set_rx_owner) (struct dma_desc *p);
 387         /* Get the receive frame size */
 388         int (*get_rx_frame_len) (struct dma_desc *p, int rx_coe_type);
 389         /* Return the reception status looking at the RDES1 */
 390         int (*rx_status) (void *data, struct stmmac_extra_stats *x,
 391                           struct dma_desc *p);
 392         void (*rx_extended_status) (void *data, struct stmmac_extra_stats *x,
 393                                     struct dma_extended_desc *p);
 394         /* Set tx timestamp enable bit */
 395         void (*enable_tx_timestamp) (struct dma_desc *p);
 396         /* get tx timestamp status */
 397         int (*get_tx_timestamp_status) (struct dma_desc *p);
 398         /* get timestamp value */
 399          u64(*get_timestamp) (void *desc, u32 ats);
 400         /* get rx timestamp status */
 401         int (*get_rx_timestamp_status) (void *desc, u32 ats);
 402         /* Display ring */
 403         void (*display_ring)(void *head, unsigned int size, bool rx);
 404         /* set MSS via context descriptor */
 405         void (*set_mss)(struct dma_desc *p, unsigned int mss);
 406 };
 407
 408 extern const struct stmmac_desc_ops enh_desc_ops;
 409 extern const struct stmmac_desc_ops ndesc_ops;
 410
 411 /* Specific DMA helpers */
 412 struct stmmac_dma_ops {
 413         /* DMA core initialization */
 414         int (*reset)(void __iomem *ioaddr);
 415         void (*init)(void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg,
 416                      u32 dma_tx, u32 dma_rx, int atds);
 417         /* Configure the AXI Bus Mode Register */
 418         void (*axi)(void __iomem *ioaddr, struct stmmac_axi *axi);
 419         /* Dump DMA registers */
 420         void (*dump_regs) (void __iomem *ioaddr);
 421         /* Set tx/rx threshold in the csr6 register
 422          * An invalid value enables the store-and-forward mode */
 423         void (*dma_mode)(void __iomem *ioaddr, int txmode, int rxmode,
 424                          int rxfifosz);
 425         /* To track extra statistic (if supported) */
 426         void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
 427                                    void __iomem *ioaddr);
 428         void (*enable_dma_transmission) (void __iomem *ioaddr);
 429         void (*enable_dma_irq) (void __iomem *ioaddr);
 430         void (*disable_dma_irq) (void __iomem *ioaddr);
 431         void (*start_tx) (void __iomem *ioaddr);
 432         void (*stop_tx) (void __iomem *ioaddr);
 433         void (*start_rx) (void __iomem *ioaddr);
 434         void (*stop_rx) (void __iomem *ioaddr);
 435         int (*dma_interrupt) (void __iomem *ioaddr,
 436                               struct stmmac_extra_stats *x);
 437         /* If supported then get the optional core features */
 438         void (*get_hw_feature)(void __iomem *ioaddr,
 439                                struct dma_features *dma_cap);
 440         /* Program the HW RX Watchdog */
 441         void (*rx_watchdog) (void __iomem *ioaddr, u32 riwt);
 442         void (*set_tx_ring_len)(void __iomem *ioaddr, u32 len);
 443         void (*set_rx_ring_len)(void __iomem *ioaddr, u32 len);
 444         void (*set_rx_tail_ptr)(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
 445         void (*set_tx_tail_ptr)(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
 446         void (*enable_tso)(void __iomem *ioaddr, bool en, u32 chan);
 447 };
 448
 449 struct mac_device_info;
 450
 451 /* Helpers to program the MAC core */
 452 struct stmmac_ops {
 453         /* MAC core initialization */
 454         void (*core_init)(struct mac_device_info *hw, int mtu);
 455         /* Enable and verify that the IPC module is supported */
 456         int (*rx_ipc)(struct mac_device_info *hw);
 457         /* Dump MAC registers */
 458         void (*dump_regs)(struct mac_device_info *hw);
 459         /* Handle extra events on specific interrupts hw dependent */
 460         int (*host_irq_status)(struct mac_device_info *hw,
 461                                struct stmmac_extra_stats *x);
 462         /* Multicast filter setting */
 463         void (*set_filter)(struct mac_device_info *hw, struct net_device *dev);
 464         /* Flow control setting */
 465         void (*flow_ctrl)(struct mac_device_info *hw, unsigned int duplex,
 466                           unsigned int fc, unsigned int pause_time);
 467         /* Set power management mode (e.g. magic frame) */
 468         void (*pmt)(struct mac_device_info *hw, unsigned long mode);
 469         /* Set/Get Unicast MAC addresses */
 470         void (*set_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
 471                               unsigned int reg_n);
 472         void (*get_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
 473                               unsigned int reg_n);
 474         void (*set_eee_mode)(struct mac_device_info *hw);
 475         void (*reset_eee_mode)(struct mac_device_info *hw);
 476         void (*set_eee_timer)(struct mac_device_info *hw, int ls, int tw);
 477         void (*set_eee_pls)(struct mac_device_info *hw, int link);
 478         void (*debug)(void __iomem *ioaddr, struct stmmac_extra_stats *x);
 479         /* PCS calls */
 480         void (*pcs_ctrl_ane)(void __iomem *ioaddr, bool ane, bool srgmi_ral,
 481                              bool loopback);
 482         void (*pcs_rane)(void __iomem *ioaddr, bool restart);
 483         void (*pcs_get_adv_lp)(void __iomem *ioaddr, struct rgmii_adv *adv);
 484 };
 485
 486 /* PTP and HW Timer helpers */
 487 struct stmmac_hwtimestamp {
 488         void (*config_hw_tstamping) (void __iomem *ioaddr, u32 data);
 489         u32 (*config_sub_second_increment)(void __iomem *ioaddr, u32 ptp_clock,
 490                                            int gmac4);
 491         int (*init_systime) (void __iomem *ioaddr, u32 sec, u32 nsec);
 492         int (*config_addend) (void __iomem *ioaddr, u32 addend);
 493         int (*adjust_systime) (void __iomem *ioaddr, u32 sec, u32 nsec,
 494                                int add_sub, int gmac4);
 495          u64(*get_systime) (void __iomem *ioaddr);
 496 };
 497
 498 extern const struct stmmac_hwtimestamp stmmac_ptp;
 499 extern const struct stmmac_mode_ops dwmac4_ring_mode_ops;
 500
 501 struct mac_link {
 502         int port;
 503         int duplex;
 504         int speed;
 505 };
 506
 507 struct mii_regs {
 508         unsigned int addr;      /* MII Address */
 509         unsigned int data;      /* MII Data */
 510         unsigned int addr_shift;        /* MII address shift */
 511         unsigned int reg_shift;         /* MII reg shift */
 512         unsigned int addr_mask;         /* MII address mask */
 513         unsigned int reg_mask;          /* MII reg mask */
 514         unsigned int clk_csr_shift;
 515         unsigned int clk_csr_mask;
 516 };
 517
 518 /* Helpers to manage the descriptors for chain and ring modes */
 519 struct stmmac_mode_ops {
 520         void (*init) (void *des, dma_addr_t phy_addr, unsigned int size,
 521                       unsigned int extend_desc);
 522         unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
 523         int (*jumbo_frm)(void *priv, struct sk_buff *skb, int csum);
 524         int (*set_16kib_bfsize)(int mtu);
 525         void (*init_desc3)(struct dma_desc *p);
 526         void (*refill_desc3) (void *priv, struct dma_desc *p);
 527         void (*clean_desc3) (void *priv, struct dma_desc *p);
 528 };
 529
 530 struct mac_device_info {
 531         const struct stmmac_ops *mac;
 532         const struct stmmac_desc_ops *desc;
 533         const struct stmmac_dma_ops *dma;
 534         const struct stmmac_mode_ops *mode;
 535         const struct stmmac_hwtimestamp *ptp;
 536         struct mii_regs mii;    /* MII register Addresses */
 537         struct mac_link link;
 538         void __iomem *pcsr;     /* vpointer to device CSRs */
 539         int multicast_filter_bins;
 540         int unicast_filter_entries;
 541         int mcast_bits_log2;
 542         unsigned int rx_csum;
 543         unsigned int pcs;
 544         unsigned int pmt;
 545         unsigned int ps;
 546 };
 547
 548 struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr, int mcbins,
 549                                         int perfect_uc_entries,
 550                                         int *synopsys_id);
 551 struct mac_device_info *dwmac100_setup(void __iomem *ioaddr, int *synopsys_id);
 552 struct mac_device_info *dwmac4_setup(void __iomem *ioaddr, int mcbins,
 553                                      int perfect_uc_entries, int *synopsys_id);
 554
 555 void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
 556                          unsigned int high, unsigned int low);
 557 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
 558                          unsigned int high, unsigned int low);
 559 void stmmac_set_mac(void __iomem *ioaddr, bool enable);
 560
 561 void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
 562                                 unsigned int high, unsigned int low);
 563 void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
 564                                 unsigned int high, unsigned int low);
 565 void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable);
 566
 567 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
 568
 569 extern const struct stmmac_mode_ops ring_mode_ops;
 570 extern const struct stmmac_mode_ops chain_mode_ops;
 571 extern const struct stmmac_desc_ops dwmac4_desc_ops;
 572
 573 /**
 574  * stmmac_get_synopsys_id - return the SYINID.
 575  * @priv: driver private structure
 576  * Description: this simple function is to decode and return the SYINID
 577  * starting from the HW core register.
 578  */
 579 static inline u32 stmmac_get_synopsys_id(u32 hwid)
 580 {
 581         /* Check Synopsys Id (not available on old chips) */
 582         if (likely(hwid)) {
 583                 u32 uid = ((hwid & 0x0000ff00) >> 8);
 584                 u32 synid = (hwid & 0x000000ff);
 585
 586                 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
 587                         uid, synid);
 588
 589                 return synid;
 590         }
 591         return 0;
 592 }
 593 #endif /* __COMMON_H__ */