1 /*******************************************************************************
2 STMMAC Common Header File
4 Copyright (C) 2007-2009 STMicroelectronics Ltd
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
22 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
23 *******************************************************************************/
28 #include <linux/etherdevice.h>
29 #include <linux/netdevice.h>
30 #include <linux/phy.h>
31 #include <linux/module.h>
32 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
33 #define STMMAC_VLAN_TAG_USED
34 #include <linux/if_vlan.h>
40 /* Synopsys Core versions */
41 #define DWMAC_CORE_3_40 0x34
42 #define DWMAC_CORE_3_50 0x35
44 #undef FRAME_FILTER_DEBUG
45 /* #define FRAME_FILTER_DEBUG */
47 /* Extra statistic and debug information exposed by ethtool */
48 struct stmmac_extra_stats
{
50 unsigned long tx_underflow ____cacheline_aligned
;
51 unsigned long tx_carrier
;
52 unsigned long tx_losscarrier
;
53 unsigned long vlan_tag
;
54 unsigned long tx_deferred
;
55 unsigned long tx_vlan
;
56 unsigned long tx_jabber
;
57 unsigned long tx_frame_flushed
;
58 unsigned long tx_payload_error
;
59 unsigned long tx_ip_header_error
;
61 unsigned long rx_desc
;
62 unsigned long sa_filter_fail
;
63 unsigned long overflow_error
;
64 unsigned long ipc_csum_error
;
65 unsigned long rx_collision
;
67 unsigned long dribbling_bit
;
68 unsigned long rx_length
;
70 unsigned long rx_multicast
;
71 unsigned long rx_gmac_overflow
;
72 unsigned long rx_watchdog
;
73 unsigned long da_rx_filter_fail
;
74 unsigned long sa_rx_filter_fail
;
75 unsigned long rx_missed_cntr
;
76 unsigned long rx_overflow_cntr
;
77 unsigned long rx_vlan
;
78 /* Tx/Rx IRQ error info */
79 unsigned long tx_undeflow_irq
;
80 unsigned long tx_process_stopped_irq
;
81 unsigned long tx_jabber_irq
;
82 unsigned long rx_overflow_irq
;
83 unsigned long rx_buf_unav_irq
;
84 unsigned long rx_process_stopped_irq
;
85 unsigned long rx_watchdog_irq
;
86 unsigned long tx_early_irq
;
87 unsigned long fatal_bus_error_irq
;
88 /* Tx/Rx IRQ Events */
89 unsigned long rx_early_irq
;
90 unsigned long threshold
;
91 unsigned long tx_pkt_n
;
92 unsigned long rx_pkt_n
;
93 unsigned long normal_irq_n
;
94 unsigned long rx_normal_irq_n
;
95 unsigned long napi_poll
;
96 unsigned long tx_normal_irq_n
;
97 unsigned long tx_clean
;
98 unsigned long tx_reset_ic_bit
;
99 unsigned long irq_receive_pmt_irq_n
;
101 unsigned long mmc_tx_irq_n
;
102 unsigned long mmc_rx_irq_n
;
103 unsigned long mmc_rx_csum_offload_irq_n
;
105 unsigned long irq_tx_path_in_lpi_mode_n
;
106 unsigned long irq_tx_path_exit_lpi_mode_n
;
107 unsigned long irq_rx_path_in_lpi_mode_n
;
108 unsigned long irq_rx_path_exit_lpi_mode_n
;
109 unsigned long phy_eee_wakeup_error_n
;
110 /* Extended RDES status */
111 unsigned long ip_hdr_err
;
112 unsigned long ip_payload_err
;
113 unsigned long ip_csum_bypassed
;
114 unsigned long ipv4_pkt_rcvd
;
115 unsigned long ipv6_pkt_rcvd
;
116 unsigned long rx_msg_type_ext_no_ptp
;
117 unsigned long rx_msg_type_sync
;
118 unsigned long rx_msg_type_follow_up
;
119 unsigned long rx_msg_type_delay_req
;
120 unsigned long rx_msg_type_delay_resp
;
121 unsigned long rx_msg_type_pdelay_req
;
122 unsigned long rx_msg_type_pdelay_resp
;
123 unsigned long rx_msg_type_pdelay_follow_up
;
124 unsigned long ptp_frame_type
;
125 unsigned long ptp_ver
;
126 unsigned long timestamp_dropped
;
127 unsigned long av_pkt_rcvd
;
128 unsigned long av_tagged_pkt_rcvd
;
129 unsigned long vlan_tag_priority_val
;
130 unsigned long l3_filter_match
;
131 unsigned long l4_filter_match
;
132 unsigned long l3_l4_filter_no_match
;
134 unsigned long irq_pcs_ane_n
;
135 unsigned long irq_pcs_link_n
;
136 unsigned long irq_rgmii_n
;
137 unsigned long pcs_link
;
138 unsigned long pcs_duplex
;
139 unsigned long pcs_speed
;
141 unsigned long mtl_tx_status_fifo_full
;
142 unsigned long mtl_tx_fifo_not_empty
;
143 unsigned long mmtl_fifo_ctrl
;
144 unsigned long mtl_tx_fifo_read_ctrl_write
;
145 unsigned long mtl_tx_fifo_read_ctrl_wait
;
146 unsigned long mtl_tx_fifo_read_ctrl_read
;
147 unsigned long mtl_tx_fifo_read_ctrl_idle
;
148 unsigned long mac_tx_in_pause
;
149 unsigned long mac_tx_frame_ctrl_xfer
;
150 unsigned long mac_tx_frame_ctrl_idle
;
151 unsigned long mac_tx_frame_ctrl_wait
;
152 unsigned long mac_tx_frame_ctrl_pause
;
153 unsigned long mac_gmii_tx_proto_engine
;
154 unsigned long mtl_rx_fifo_fill_level_full
;
155 unsigned long mtl_rx_fifo_fill_above_thresh
;
156 unsigned long mtl_rx_fifo_fill_below_thresh
;
157 unsigned long mtl_rx_fifo_fill_level_empty
;
158 unsigned long mtl_rx_fifo_read_ctrl_flush
;
159 unsigned long mtl_rx_fifo_read_ctrl_read_data
;
160 unsigned long mtl_rx_fifo_read_ctrl_status
;
161 unsigned long mtl_rx_fifo_read_ctrl_idle
;
162 unsigned long mtl_rx_fifo_ctrl_active
;
163 unsigned long mac_rx_frame_ctrl_fifo
;
164 unsigned long mac_gmii_rx_proto_engine
;
167 /* CSR Frequency Access Defines*/
168 #define CSR_F_35M 35000000
169 #define CSR_F_60M 60000000
170 #define CSR_F_100M 100000000
171 #define CSR_F_150M 150000000
172 #define CSR_F_250M 250000000
173 #define CSR_F_300M 300000000
175 #define MAC_CSR_H_FRQ_MASK 0x20
177 #define HASH_TABLE_SIZE 64
178 #define PAUSE_TIME 0xffff
180 /* Flow Control defines */
184 #define FLOW_AUTO (FLOW_TX | FLOW_RX)
187 #define STMMAC_PCS_RGMII (1 << 0)
188 #define STMMAC_PCS_SGMII (1 << 1)
189 #define STMMAC_PCS_TBI (1 << 2)
190 #define STMMAC_PCS_RTBI (1 << 3)
192 #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
194 /* DAM HW feature register fields */
195 #define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
196 #define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
197 #define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
198 #define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
199 #define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
200 #define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */
201 #define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
202 #define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
203 #define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
204 #define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
205 #define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
206 #define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
207 #define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */
208 #define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */
209 #define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
210 #define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
211 #define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
212 #define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */
213 #define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */
214 #define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
215 #define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */
216 #define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */
217 #define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */
218 /* Timestamping with Internal System Time */
219 #define DMA_HW_FEAT_INTTSEN 0x02000000
220 #define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
221 #define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */
222 #define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */
223 #define DEFAULT_DMA_PBL 8
225 /* Max/Min RI Watchdog Timer count value */
226 #define MAX_DMA_RIWT 0xff
227 #define MIN_DMA_RIWT 0x20
228 /* Tx coalesce parameters */
229 #define STMMAC_COAL_TX_TIMER 40000
230 #define STMMAC_MAX_COAL_TX_TICK 100000
231 #define STMMAC_TX_MAX_FRAMES 256
232 #define STMMAC_TX_FRAMES 64
235 enum rx_frame_status
{
242 enum dma_irq_status
{
244 tx_hard_error_bump_tc
= 0x2,
249 /* EEE and LPI defines */
250 #define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0)
251 #define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1)
252 #define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2)
253 #define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3)
255 #define CORE_PCS_ANE_COMPLETE (1 << 5)
256 #define CORE_PCS_LINK_STATUS (1 << 6)
257 #define CORE_RGMII_IRQ (1 << 7)
259 /* Physical Coding Sublayer */
263 unsigned int lp_pause
;
264 unsigned int lp_duplex
;
267 #define STMMAC_PCS_PAUSE 1
268 #define STMMAC_PCS_ASYM_PAUSE 2
270 /* DMA HW capabilities */
271 struct dma_features
{
272 unsigned int mbps_10_100
;
273 unsigned int mbps_1000
;
274 unsigned int half_duplex
;
275 unsigned int hash_filter
;
276 unsigned int multi_addr
;
278 unsigned int sma_mdio
;
279 unsigned int pmt_remote_wake_up
;
280 unsigned int pmt_magic_frame
;
283 unsigned int time_stamp
;
285 unsigned int atime_stamp
;
286 /* 802.3az - Energy-Efficient Ethernet (EEE) */
291 unsigned int rx_coe_type1
;
292 unsigned int rx_coe_type2
;
293 unsigned int rxfifo_over_2048
;
294 /* TX and RX number of channels */
295 unsigned int number_rx_channel
;
296 unsigned int number_tx_channel
;
297 /* Alternate (enhanced) DESC mode */
298 unsigned int enh_desc
;
301 /* GMAC TX FIFO is 8K, Rx FIFO is 16K */
302 #define BUF_SIZE_16KiB 16384
303 #define BUF_SIZE_8KiB 8192
304 #define BUF_SIZE_4KiB 4096
305 #define BUF_SIZE_2KiB 2048
307 /* Power Down and WOL */
308 #define PMT_NOT_SUPPORTED 0
309 #define PMT_SUPPORTED 1
311 /* Common MAC defines */
312 #define MAC_CTRL_REG 0x00000000 /* MAC Control */
313 #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
314 #define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */
316 /* Default LPI timers */
317 #define STMMAC_DEFAULT_LIT_LS 0x3E8
318 #define STMMAC_DEFAULT_TWT_LS 0x1E
320 #define STMMAC_CHAIN_MODE 0x1
321 #define STMMAC_RING_MODE 0x2
323 #define JUMBO_LEN 9000
325 /* Descriptors helpers */
326 struct stmmac_desc_ops
{
327 /* DMA RX descriptor ring initialization */
328 void (*init_rx_desc
) (struct dma_desc
*p
, int disable_rx_ic
, int mode
,
330 /* DMA TX descriptor ring initialization */
331 void (*init_tx_desc
) (struct dma_desc
*p
, int mode
, int end
);
333 /* Invoked by the xmit function to prepare the tx descriptor */
334 void (*prepare_tx_desc
) (struct dma_desc
*p
, int is_fs
, int len
,
335 int csum_flag
, int mode
);
336 /* Set/get the owner of the descriptor */
337 void (*set_tx_owner
) (struct dma_desc
*p
);
338 int (*get_tx_owner
) (struct dma_desc
*p
);
339 /* Invoked by the xmit function to close the tx descriptor */
340 void (*close_tx_desc
) (struct dma_desc
*p
);
341 /* Clean the tx descriptor as soon as the tx irq is received */
342 void (*release_tx_desc
) (struct dma_desc
*p
, int mode
);
343 /* Clear interrupt on tx frame completion. When this bit is
344 * set an interrupt happens as soon as the frame is transmitted */
345 void (*clear_tx_ic
) (struct dma_desc
*p
);
346 /* Last tx segment reports the transmit status */
347 int (*get_tx_ls
) (struct dma_desc
*p
);
348 /* Return the transmit status looking at the TDES1 */
349 int (*tx_status
) (void *data
, struct stmmac_extra_stats
*x
,
350 struct dma_desc
*p
, void __iomem
*ioaddr
);
351 /* Get the buffer size from the descriptor */
352 int (*get_tx_len
) (struct dma_desc
*p
);
353 /* Handle extra events on specific interrupts hw dependent */
354 int (*get_rx_owner
) (struct dma_desc
*p
);
355 void (*set_rx_owner
) (struct dma_desc
*p
);
356 /* Get the receive frame size */
357 int (*get_rx_frame_len
) (struct dma_desc
*p
, int rx_coe_type
);
358 /* Return the reception status looking at the RDES1 */
359 int (*rx_status
) (void *data
, struct stmmac_extra_stats
*x
,
361 void (*rx_extended_status
) (void *data
, struct stmmac_extra_stats
*x
,
362 struct dma_extended_desc
*p
);
363 /* Set tx timestamp enable bit */
364 void (*enable_tx_timestamp
) (struct dma_desc
*p
);
365 /* get tx timestamp status */
366 int (*get_tx_timestamp_status
) (struct dma_desc
*p
);
367 /* get timestamp value */
368 u64(*get_timestamp
) (void *desc
, u32 ats
);
369 /* get rx timestamp status */
370 int (*get_rx_timestamp_status
) (void *desc
, u32 ats
);
373 extern const struct stmmac_desc_ops enh_desc_ops
;
374 extern const struct stmmac_desc_ops ndesc_ops
;
376 /* Specific DMA helpers */
377 struct stmmac_dma_ops
{
378 /* DMA core initialization */
379 int (*reset
)(void __iomem
*ioaddr
);
380 void (*init
)(void __iomem
*ioaddr
, int pbl
, int fb
, int mb
,
381 int burst_len
, u32 dma_tx
, u32 dma_rx
, int atds
);
382 /* Dump DMA registers */
383 void (*dump_regs
) (void __iomem
*ioaddr
);
384 /* Set tx/rx threshold in the csr6 register
385 * An invalid value enables the store-and-forward mode */
386 void (*dma_mode
)(void __iomem
*ioaddr
, int txmode
, int rxmode
,
388 /* To track extra statistic (if supported) */
389 void (*dma_diagnostic_fr
) (void *data
, struct stmmac_extra_stats
*x
,
390 void __iomem
*ioaddr
);
391 void (*enable_dma_transmission
) (void __iomem
*ioaddr
);
392 void (*enable_dma_irq
) (void __iomem
*ioaddr
);
393 void (*disable_dma_irq
) (void __iomem
*ioaddr
);
394 void (*start_tx
) (void __iomem
*ioaddr
);
395 void (*stop_tx
) (void __iomem
*ioaddr
);
396 void (*start_rx
) (void __iomem
*ioaddr
);
397 void (*stop_rx
) (void __iomem
*ioaddr
);
398 int (*dma_interrupt
) (void __iomem
*ioaddr
,
399 struct stmmac_extra_stats
*x
);
400 /* If supported then get the optional core features */
401 unsigned int (*get_hw_feature
) (void __iomem
*ioaddr
);
402 /* Program the HW RX Watchdog */
403 void (*rx_watchdog
) (void __iomem
*ioaddr
, u32 riwt
);
406 struct mac_device_info
;
408 /* Helpers to program the MAC core */
410 /* MAC core initialization */
411 void (*core_init
)(struct mac_device_info
*hw
, int mtu
);
412 /* Enable and verify that the IPC module is supported */
413 int (*rx_ipc
)(struct mac_device_info
*hw
);
414 /* Dump MAC registers */
415 void (*dump_regs
)(struct mac_device_info
*hw
);
416 /* Handle extra events on specific interrupts hw dependent */
417 int (*host_irq_status
)(struct mac_device_info
*hw
,
418 struct stmmac_extra_stats
*x
);
419 /* Multicast filter setting */
420 void (*set_filter
)(struct mac_device_info
*hw
, struct net_device
*dev
);
421 /* Flow control setting */
422 void (*flow_ctrl
)(struct mac_device_info
*hw
, unsigned int duplex
,
423 unsigned int fc
, unsigned int pause_time
);
424 /* Set power management mode (e.g. magic frame) */
425 void (*pmt
)(struct mac_device_info
*hw
, unsigned long mode
);
426 /* Set/Get Unicast MAC addresses */
427 void (*set_umac_addr
)(struct mac_device_info
*hw
, unsigned char *addr
,
429 void (*get_umac_addr
)(struct mac_device_info
*hw
, unsigned char *addr
,
431 void (*set_eee_mode
)(struct mac_device_info
*hw
);
432 void (*reset_eee_mode
)(struct mac_device_info
*hw
);
433 void (*set_eee_timer
)(struct mac_device_info
*hw
, int ls
, int tw
);
434 void (*set_eee_pls
)(struct mac_device_info
*hw
, int link
);
435 void (*ctrl_ane
)(struct mac_device_info
*hw
, bool restart
);
436 void (*get_adv
)(struct mac_device_info
*hw
, struct rgmii_adv
*adv
);
437 void (*debug
)(void __iomem
*ioaddr
, struct stmmac_extra_stats
*x
);
440 /* PTP and HW Timer helpers */
441 struct stmmac_hwtimestamp
{
442 void (*config_hw_tstamping
) (void __iomem
*ioaddr
, u32 data
);
443 u32 (*config_sub_second_increment
) (void __iomem
*ioaddr
, u32 clk_rate
);
444 int (*init_systime
) (void __iomem
*ioaddr
, u32 sec
, u32 nsec
);
445 int (*config_addend
) (void __iomem
*ioaddr
, u32 addend
);
446 int (*adjust_systime
) (void __iomem
*ioaddr
, u32 sec
, u32 nsec
,
448 u64(*get_systime
) (void __iomem
*ioaddr
);
451 extern const struct stmmac_hwtimestamp stmmac_ptp
;
460 unsigned int addr
; /* MII Address */
461 unsigned int data
; /* MII Data */
464 /* Helpers to manage the descriptors for chain and ring modes */
465 struct stmmac_mode_ops
{
466 void (*init
) (void *des
, dma_addr_t phy_addr
, unsigned int size
,
467 unsigned int extend_desc
);
468 unsigned int (*is_jumbo_frm
) (int len
, int ehn_desc
);
469 int (*jumbo_frm
)(void *priv
, struct sk_buff
*skb
, int csum
);
470 int (*set_16kib_bfsize
)(int mtu
);
471 void (*init_desc3
)(struct dma_desc
*p
);
472 void (*refill_desc3
) (void *priv
, struct dma_desc
*p
);
473 void (*clean_desc3
) (void *priv
, struct dma_desc
*p
);
476 struct mac_device_info
{
477 const struct stmmac_ops
*mac
;
478 const struct stmmac_desc_ops
*desc
;
479 const struct stmmac_dma_ops
*dma
;
480 const struct stmmac_mode_ops
*mode
;
481 const struct stmmac_hwtimestamp
*ptp
;
482 struct mii_regs mii
; /* MII register Addresses */
483 struct mac_link link
;
484 unsigned int synopsys_uid
;
485 void __iomem
*pcsr
; /* vpointer to device CSRs */
486 int multicast_filter_bins
;
487 int unicast_filter_entries
;
489 unsigned int rx_csum
;
492 struct mac_device_info
*dwmac1000_setup(void __iomem
*ioaddr
, int mcbins
,
493 int perfect_uc_entries
);
494 struct mac_device_info
*dwmac100_setup(void __iomem
*ioaddr
);
496 void stmmac_set_mac_addr(void __iomem
*ioaddr
, u8 addr
[6],
497 unsigned int high
, unsigned int low
);
498 void stmmac_get_mac_addr(void __iomem
*ioaddr
, unsigned char *addr
,
499 unsigned int high
, unsigned int low
);
501 void stmmac_set_mac(void __iomem
*ioaddr
, bool enable
);
503 void dwmac_dma_flush_tx_fifo(void __iomem
*ioaddr
);
504 extern const struct stmmac_mode_ops ring_mode_ops
;
505 extern const struct stmmac_mode_ops chain_mode_ops
;
507 #endif /* __COMMON_H__ */